1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39*eeaaefe9SLeandro Lupori #include "power8-pmu.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 48efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 49fcf5ef2aSThomas Huth 50fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 51fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 52fcf5ef2aSThomas Huth #else 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 54fcf5ef2aSThomas Huth #endif 55fcf5ef2aSThomas Huth /*****************************************************************************/ 56fcf5ef2aSThomas Huth /* Code translation helpers */ 57fcf5ef2aSThomas Huth 58fcf5ef2aSThomas Huth /* global register indexes */ 59fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 60fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 61fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 62fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 63fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 64fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 65fcf5ef2aSThomas Huth static TCGv cpu_nip; 66fcf5ef2aSThomas Huth static TCGv cpu_msr; 67fcf5ef2aSThomas Huth static TCGv cpu_ctr; 68fcf5ef2aSThomas Huth static TCGv cpu_lr; 69fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 70fcf5ef2aSThomas Huth static TCGv cpu_cfar; 71fcf5ef2aSThomas Huth #endif 72dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 73fcf5ef2aSThomas Huth static TCGv cpu_reserve; 74253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 75fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 76fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 77fcf5ef2aSThomas Huth 78fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth void ppc_translate_init(void) 81fcf5ef2aSThomas Huth { 82fcf5ef2aSThomas Huth int i; 83fcf5ef2aSThomas Huth char *p; 84fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 85fcf5ef2aSThomas Huth 86fcf5ef2aSThomas Huth p = cpu_reg_names; 87fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 88fcf5ef2aSThomas Huth 89fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 90fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 91fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 92fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 93fcf5ef2aSThomas Huth p += 5; 94fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 95fcf5ef2aSThomas Huth } 96fcf5ef2aSThomas Huth 97fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 98fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 99fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 100fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 101fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 103fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 104fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 105fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 106fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 108fcf5ef2aSThomas Huth } 109fcf5ef2aSThomas Huth 110fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 111fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 112fcf5ef2aSThomas Huth 113fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 114fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 115fcf5ef2aSThomas Huth 116fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 117fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 118fcf5ef2aSThomas Huth 119fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 120fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 121fcf5ef2aSThomas Huth 122fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 123fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 124fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 125fcf5ef2aSThomas Huth #endif 126fcf5ef2aSThomas Huth 127fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 128fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 129fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 131fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 133fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 135dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 136dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 137dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 139fcf5ef2aSThomas Huth 140fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 141fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 142fcf5ef2aSThomas Huth "reserve_addr"); 143253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 144253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 145253ce7b2SNikunj A Dadhania "reserve_val"); 146fcf5ef2aSThomas Huth 147fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 148fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 149fcf5ef2aSThomas Huth 150fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 151efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 152efe843d8SDavid Gibson "access_type"); 153fcf5ef2aSThomas Huth } 154fcf5ef2aSThomas Huth 155fcf5ef2aSThomas Huth /* internal defines */ 156fcf5ef2aSThomas Huth struct DisasContext { 157b6bac4bcSEmilio G. Cota DisasContextBase base; 1582c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 159fcf5ef2aSThomas Huth uint32_t opcode; 160fcf5ef2aSThomas Huth /* Routine used to access memory */ 161fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 162fcf5ef2aSThomas Huth bool lazy_tlb_flush; 163fcf5ef2aSThomas Huth bool need_access_type; 164fcf5ef2aSThomas Huth int mem_idx; 165fcf5ef2aSThomas Huth int access_type; 166fcf5ef2aSThomas Huth /* Translation flags */ 16714776ab5STony Nguyen MemOp default_tcg_memop_mask; 168fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 169fcf5ef2aSThomas Huth bool sf_mode; 170fcf5ef2aSThomas Huth bool has_cfar; 171fcf5ef2aSThomas Huth #endif 172fcf5ef2aSThomas Huth bool fpu_enabled; 173fcf5ef2aSThomas Huth bool altivec_enabled; 174fcf5ef2aSThomas Huth bool vsx_enabled; 175fcf5ef2aSThomas Huth bool spe_enabled; 176fcf5ef2aSThomas Huth bool tm_enabled; 177c6fd28fdSSuraj Jitindar Singh bool gtse; 1781db3632aSMatheus Ferst bool hr; 179f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 180f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1818b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1828b3d1c49SLeandro Lupori bool pmc_other; 18346d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 184fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 185fcf5ef2aSThomas Huth int singlestep_enabled; 1860e3bf489SRoman Kapl uint32_t flags; 187fcf5ef2aSThomas Huth uint64_t insns_flags; 188fcf5ef2aSThomas Huth uint64_t insns_flags2; 189fcf5ef2aSThomas Huth }; 190fcf5ef2aSThomas Huth 191a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 192a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 193a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 194a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 195a9b5b3d0SRichard Henderson 196fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 197fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 198fcf5ef2aSThomas Huth { 199ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 200fcf5ef2aSThomas Huth return ctx->le_mode; 201fcf5ef2aSThomas Huth #else 202fcf5ef2aSThomas Huth return !ctx->le_mode; 203fcf5ef2aSThomas Huth #endif 204fcf5ef2aSThomas Huth } 205fcf5ef2aSThomas Huth 206fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 207fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 208fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 209fcf5ef2aSThomas Huth #else 210fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 211fcf5ef2aSThomas Huth #endif 212fcf5ef2aSThomas Huth 213fcf5ef2aSThomas Huth struct opc_handler_t { 214fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 215fcf5ef2aSThomas Huth uint32_t inval1; 216fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 217fcf5ef2aSThomas Huth uint32_t inval2; 218fcf5ef2aSThomas Huth /* instruction type */ 219fcf5ef2aSThomas Huth uint64_t type; 220fcf5ef2aSThomas Huth /* extended instruction type */ 221fcf5ef2aSThomas Huth uint64_t type2; 222fcf5ef2aSThomas Huth /* handler */ 223fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 224fcf5ef2aSThomas Huth }; 225fcf5ef2aSThomas Huth 2260e3bf489SRoman Kapl /* SPR load/store helpers */ 2270e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2280e3bf489SRoman Kapl { 2290e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2300e3bf489SRoman Kapl } 2310e3bf489SRoman Kapl 2320e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2330e3bf489SRoman Kapl { 2340e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2350e3bf489SRoman Kapl } 2360e3bf489SRoman Kapl 237fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 238fcf5ef2aSThomas Huth { 239fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 240fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 241fcf5ef2aSThomas Huth ctx->access_type = access_type; 242fcf5ef2aSThomas Huth } 243fcf5ef2aSThomas Huth } 244fcf5ef2aSThomas Huth 245fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 246fcf5ef2aSThomas Huth { 247fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 248fcf5ef2aSThomas Huth nip = (uint32_t)nip; 249fcf5ef2aSThomas Huth } 250fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 251fcf5ef2aSThomas Huth } 252fcf5ef2aSThomas Huth 253fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 254fcf5ef2aSThomas Huth { 255fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 256fcf5ef2aSThomas Huth 257efe843d8SDavid Gibson /* 258efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 259efe843d8SDavid Gibson * faulting instruction 260fcf5ef2aSThomas Huth */ 2612c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 262fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 263fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 264fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 265fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 266fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2673d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 268fcf5ef2aSThomas Huth } 269fcf5ef2aSThomas Huth 270fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 271fcf5ef2aSThomas Huth { 272fcf5ef2aSThomas Huth TCGv_i32 t0; 273fcf5ef2aSThomas Huth 274efe843d8SDavid Gibson /* 275efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 276efe843d8SDavid Gibson * faulting instruction 277fcf5ef2aSThomas Huth */ 2782c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 279fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 280fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 281fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2823d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 283fcf5ef2aSThomas Huth } 284fcf5ef2aSThomas Huth 285fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 286fcf5ef2aSThomas Huth target_ulong nip) 287fcf5ef2aSThomas Huth { 288fcf5ef2aSThomas Huth TCGv_i32 t0; 289fcf5ef2aSThomas Huth 290fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 291fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 292fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 293fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2943d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 295fcf5ef2aSThomas Huth } 296fcf5ef2aSThomas Huth 297f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 298f5b6daacSRichard Henderson { 299f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 300f5b6daacSRichard Henderson gen_io_start(); 301f5b6daacSRichard Henderson /* 302f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 303f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 304f5b6daacSRichard Henderson * decide if we need to return to the main loop. 305f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 306f5b6daacSRichard Henderson */ 307f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 308f5b6daacSRichard Henderson } 309f5b6daacSRichard Henderson } 310f5b6daacSRichard Henderson 3112fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3122fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3132fdedcbcSMatheus Ferst { 3142fdedcbcSMatheus Ferst gen_icount_io_start(ctx); 3152fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3162fdedcbcSMatheus Ferst } 3172fdedcbcSMatheus Ferst #endif 3182fdedcbcSMatheus Ferst 319e150ac89SRoman Kapl /* 320e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 321e150ac89SRoman Kapl * SPR registers for this exception. 322e150ac89SRoman Kapl * 323e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 324e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3250e3bf489SRoman Kapl */ 326e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3270e3bf489SRoman Kapl { 3280e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3290e3bf489SRoman Kapl target_ulong dbsr = 0; 330e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3310e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 332e150ac89SRoman Kapl } else { 333e150ac89SRoman Kapl /* Must have been branch */ 3340e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3350e3bf489SRoman Kapl } 3360e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3370e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3380e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3390e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3400e3bf489SRoman Kapl tcg_temp_free(t0); 3410e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3420e3bf489SRoman Kapl } else { 343e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3440e3bf489SRoman Kapl } 3450e3bf489SRoman Kapl } 3460e3bf489SRoman Kapl 347fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 348fcf5ef2aSThomas Huth { 3499498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3503d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 353fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 354fcf5ef2aSThomas Huth { 355fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 356fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 357fcf5ef2aSThomas Huth } 358fcf5ef2aSThomas Huth 359fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 360fcf5ef2aSThomas Huth { 361fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 362fcf5ef2aSThomas Huth } 363fcf5ef2aSThomas Huth 364fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 365fcf5ef2aSThomas Huth { 366fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 367fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 368fcf5ef2aSThomas Huth } 369fcf5ef2aSThomas Huth 37037f219c8SBruno Larsen (billionai) /*****************************************************************************/ 37137f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 37237f219c8SBruno Larsen (billionai) 373a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 37437f219c8SBruno Larsen (billionai) { 37537f219c8SBruno Larsen (billionai) #if 0 37637f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 37737f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 37837f219c8SBruno Larsen (billionai) #endif 37937f219c8SBruno Larsen (billionai) } 38037f219c8SBruno Larsen (billionai) 38137f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 38237f219c8SBruno Larsen (billionai) 38337f219c8SBruno Larsen (billionai) /* 38437f219c8SBruno Larsen (billionai) * Generic callbacks: 38537f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 38637f219c8SBruno Larsen (billionai) */ 38737f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 38837f219c8SBruno Larsen (billionai) { 38937f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39137f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 39237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39337f219c8SBruno Larsen (billionai) #endif 39437f219c8SBruno Larsen (billionai) } 39537f219c8SBruno Larsen (billionai) 396a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 39737f219c8SBruno Larsen (billionai) { 39837f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 39937f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 40037f219c8SBruno Larsen (billionai) } 40137f219c8SBruno Larsen (billionai) 40237f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 40337f219c8SBruno Larsen (billionai) { 40437f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 40537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 40637f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 40737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 40837f219c8SBruno Larsen (billionai) #endif 40937f219c8SBruno Larsen (billionai) } 41037f219c8SBruno Larsen (billionai) 411a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 41237f219c8SBruno Larsen (billionai) { 41337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 41437f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41537f219c8SBruno Larsen (billionai) } 41637f219c8SBruno Larsen (billionai) 4177aeac354SDaniel Henrique Barboza void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 4187aeac354SDaniel Henrique Barboza { 4197aeac354SDaniel Henrique Barboza spr_write_generic(ctx, sprn, gprn); 4207aeac354SDaniel Henrique Barboza 4217aeac354SDaniel Henrique Barboza /* 4227aeac354SDaniel Henrique Barboza * SPR_CTRL writes must force a new translation block, 4237aeac354SDaniel Henrique Barboza * allowing the PMU to calculate the run latch events with 4247aeac354SDaniel Henrique Barboza * more accuracy. 4257aeac354SDaniel Henrique Barboza */ 4267aeac354SDaniel Henrique Barboza ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4277aeac354SDaniel Henrique Barboza } 4287aeac354SDaniel Henrique Barboza 42937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 430a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43137f219c8SBruno Larsen (billionai) { 43237f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43437f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 43737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43837f219c8SBruno Larsen (billionai) #else 43937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 44037f219c8SBruno Larsen (billionai) #endif 44137f219c8SBruno Larsen (billionai) } 44237f219c8SBruno Larsen (billionai) 443a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 44437f219c8SBruno Larsen (billionai) { 44537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44737f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 44837f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 44937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 45037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 45137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 45337f219c8SBruno Larsen (billionai) } 45437f219c8SBruno Larsen (billionai) 455a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 45637f219c8SBruno Larsen (billionai) { 45737f219c8SBruno Larsen (billionai) } 45837f219c8SBruno Larsen (billionai) 45937f219c8SBruno Larsen (billionai) #endif 46037f219c8SBruno Larsen (billionai) 46137f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 46237f219c8SBruno Larsen (billionai) /* XER */ 463a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 46437f219c8SBruno Larsen (billionai) { 46537f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 46637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 46737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 46837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 46937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 47037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 47137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 47237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 47337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 47437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 47537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47637f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 47737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 47837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 48037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 48137f219c8SBruno Larsen (billionai) } 48237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 48337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 48437f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 48537f219c8SBruno Larsen (billionai) } 48637f219c8SBruno Larsen (billionai) 487a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 48837f219c8SBruno Larsen (billionai) { 48937f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 49037f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 49137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 49237f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 49337f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 49437f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 49537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 49637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 49737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 49837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 49937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 50037f219c8SBruno Larsen (billionai) } 50137f219c8SBruno Larsen (billionai) 50237f219c8SBruno Larsen (billionai) /* LR */ 503a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 50437f219c8SBruno Larsen (billionai) { 50537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 50637f219c8SBruno Larsen (billionai) } 50737f219c8SBruno Larsen (billionai) 508a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 50937f219c8SBruno Larsen (billionai) { 51037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 51137f219c8SBruno Larsen (billionai) } 51237f219c8SBruno Larsen (billionai) 51337f219c8SBruno Larsen (billionai) /* CFAR */ 51437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 515a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 51637f219c8SBruno Larsen (billionai) { 51737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 51837f219c8SBruno Larsen (billionai) } 51937f219c8SBruno Larsen (billionai) 520a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 52137f219c8SBruno Larsen (billionai) { 52237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 52337f219c8SBruno Larsen (billionai) } 52437f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 52537f219c8SBruno Larsen (billionai) 52637f219c8SBruno Larsen (billionai) /* CTR */ 527a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 52837f219c8SBruno Larsen (billionai) { 52937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 53037f219c8SBruno Larsen (billionai) } 53137f219c8SBruno Larsen (billionai) 532a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 53337f219c8SBruno Larsen (billionai) { 53437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 53537f219c8SBruno Larsen (billionai) } 53637f219c8SBruno Larsen (billionai) 53737f219c8SBruno Larsen (billionai) /* User read access to SPR */ 53837f219c8SBruno Larsen (billionai) /* USPRx */ 53937f219c8SBruno Larsen (billionai) /* UMMCRx */ 54037f219c8SBruno Larsen (billionai) /* UPMCx */ 54137f219c8SBruno Larsen (billionai) /* USIA */ 54237f219c8SBruno Larsen (billionai) /* UDECR */ 543a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 54437f219c8SBruno Larsen (billionai) { 54537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 54637f219c8SBruno Larsen (billionai) } 54737f219c8SBruno Larsen (billionai) 54837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 549a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 55037f219c8SBruno Larsen (billionai) { 55137f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 55237f219c8SBruno Larsen (billionai) } 55337f219c8SBruno Larsen (billionai) #endif 55437f219c8SBruno Larsen (billionai) 55537f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 55637f219c8SBruno Larsen (billionai) /* DECR */ 55737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 558a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 55937f219c8SBruno Larsen (billionai) { 560f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56137f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 56237f219c8SBruno Larsen (billionai) } 56337f219c8SBruno Larsen (billionai) 564a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 56537f219c8SBruno Larsen (billionai) { 566f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56737f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 56837f219c8SBruno Larsen (billionai) } 56937f219c8SBruno Larsen (billionai) #endif 57037f219c8SBruno Larsen (billionai) 57137f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 57237f219c8SBruno Larsen (billionai) /* Time base */ 573a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 57437f219c8SBruno Larsen (billionai) { 575f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57637f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 57737f219c8SBruno Larsen (billionai) } 57837f219c8SBruno Larsen (billionai) 579a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 58037f219c8SBruno Larsen (billionai) { 581f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58237f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 58337f219c8SBruno Larsen (billionai) } 58437f219c8SBruno Larsen (billionai) 585a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 58637f219c8SBruno Larsen (billionai) { 58737f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 58837f219c8SBruno Larsen (billionai) } 58937f219c8SBruno Larsen (billionai) 590a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 59137f219c8SBruno Larsen (billionai) { 59237f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 59337f219c8SBruno Larsen (billionai) } 59437f219c8SBruno Larsen (billionai) 59537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 596a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 59737f219c8SBruno Larsen (billionai) { 598f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59937f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 60037f219c8SBruno Larsen (billionai) } 60137f219c8SBruno Larsen (billionai) 602a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 60337f219c8SBruno Larsen (billionai) { 604f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60537f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 60637f219c8SBruno Larsen (billionai) } 60737f219c8SBruno Larsen (billionai) 608a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 60937f219c8SBruno Larsen (billionai) { 61037f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 61137f219c8SBruno Larsen (billionai) } 61237f219c8SBruno Larsen (billionai) 613a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 61437f219c8SBruno Larsen (billionai) { 61537f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 61637f219c8SBruno Larsen (billionai) } 61737f219c8SBruno Larsen (billionai) 61837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 619a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 62037f219c8SBruno Larsen (billionai) { 621f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62237f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 62337f219c8SBruno Larsen (billionai) } 62437f219c8SBruno Larsen (billionai) 625a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 62637f219c8SBruno Larsen (billionai) { 627f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62837f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 62937f219c8SBruno Larsen (billionai) } 63037f219c8SBruno Larsen (billionai) 63137f219c8SBruno Larsen (billionai) /* HDECR */ 632a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 63337f219c8SBruno Larsen (billionai) { 634f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63537f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 63637f219c8SBruno Larsen (billionai) } 63737f219c8SBruno Larsen (billionai) 638a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 63937f219c8SBruno Larsen (billionai) { 640f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64137f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 64237f219c8SBruno Larsen (billionai) } 64337f219c8SBruno Larsen (billionai) 644a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 64537f219c8SBruno Larsen (billionai) { 646f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64737f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 64837f219c8SBruno Larsen (billionai) } 64937f219c8SBruno Larsen (billionai) 650a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 65137f219c8SBruno Larsen (billionai) { 652f5b6daacSRichard Henderson gen_icount_io_start(ctx); 65337f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 65437f219c8SBruno Larsen (billionai) } 65537f219c8SBruno Larsen (billionai) 656a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 65737f219c8SBruno Larsen (billionai) { 658f5b6daacSRichard Henderson gen_icount_io_start(ctx); 65937f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 66037f219c8SBruno Larsen (billionai) } 66137f219c8SBruno Larsen (billionai) 66237f219c8SBruno Larsen (billionai) #endif 66337f219c8SBruno Larsen (billionai) #endif 66437f219c8SBruno Larsen (billionai) 66537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 66637f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 66737f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 668a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 66937f219c8SBruno Larsen (billionai) { 67037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 67137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 67237f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 67337f219c8SBruno Larsen (billionai) } 67437f219c8SBruno Larsen (billionai) 675a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 67637f219c8SBruno Larsen (billionai) { 67737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 67837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 67937f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 68037f219c8SBruno Larsen (billionai) } 68137f219c8SBruno Larsen (billionai) 682a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 68337f219c8SBruno Larsen (billionai) { 68437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 68537f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 68637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68737f219c8SBruno Larsen (billionai) } 68837f219c8SBruno Larsen (billionai) 689a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 69037f219c8SBruno Larsen (billionai) { 69137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 69237f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 69337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69437f219c8SBruno Larsen (billionai) } 69537f219c8SBruno Larsen (billionai) 696a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 69737f219c8SBruno Larsen (billionai) { 69837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 69937f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 70037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70137f219c8SBruno Larsen (billionai) } 70237f219c8SBruno Larsen (billionai) 703a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 70437f219c8SBruno Larsen (billionai) { 70537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 70637f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 70737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70837f219c8SBruno Larsen (billionai) } 70937f219c8SBruno Larsen (billionai) 71037f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 71137f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 712a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 71337f219c8SBruno Larsen (billionai) { 71437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 71537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 71637f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 71737f219c8SBruno Larsen (billionai) } 71837f219c8SBruno Larsen (billionai) 719a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 72037f219c8SBruno Larsen (billionai) { 72137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 72237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 72337f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 72437f219c8SBruno Larsen (billionai) } 72537f219c8SBruno Larsen (billionai) 726a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 72737f219c8SBruno Larsen (billionai) { 72837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 72937f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 73037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73137f219c8SBruno Larsen (billionai) } 73237f219c8SBruno Larsen (billionai) 733a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 73437f219c8SBruno Larsen (billionai) { 73537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 73637f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 73737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73837f219c8SBruno Larsen (billionai) } 73937f219c8SBruno Larsen (billionai) 740a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 74137f219c8SBruno Larsen (billionai) { 74237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 74337f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 74437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74537f219c8SBruno Larsen (billionai) } 74637f219c8SBruno Larsen (billionai) 747a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 74837f219c8SBruno Larsen (billionai) { 74937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 75037f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 75137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75237f219c8SBruno Larsen (billionai) } 75337f219c8SBruno Larsen (billionai) 75437f219c8SBruno Larsen (billionai) /* SDR1 */ 755a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 75637f219c8SBruno Larsen (billionai) { 75737f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 75837f219c8SBruno Larsen (billionai) } 75937f219c8SBruno Larsen (billionai) 76037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 76137f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 76237f219c8SBruno Larsen (billionai) /* PIDR */ 763a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 76437f219c8SBruno Larsen (billionai) { 76537f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 76637f219c8SBruno Larsen (billionai) } 76737f219c8SBruno Larsen (billionai) 768a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 76937f219c8SBruno Larsen (billionai) { 77037f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 77137f219c8SBruno Larsen (billionai) } 77237f219c8SBruno Larsen (billionai) 773a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 77437f219c8SBruno Larsen (billionai) { 77537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 77637f219c8SBruno Larsen (billionai) } 77737f219c8SBruno Larsen (billionai) 778a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 77937f219c8SBruno Larsen (billionai) { 78037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 78137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 78237f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 78337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 78437f219c8SBruno Larsen (billionai) } 785a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 78637f219c8SBruno Larsen (billionai) { 78737f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) 79537f219c8SBruno Larsen (billionai) /* DPDES */ 796a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 79737f219c8SBruno Larsen (billionai) { 79837f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 79937f219c8SBruno Larsen (billionai) } 80037f219c8SBruno Larsen (billionai) 801a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 80237f219c8SBruno Larsen (billionai) { 80337f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 80437f219c8SBruno Larsen (billionai) } 80537f219c8SBruno Larsen (billionai) #endif 80637f219c8SBruno Larsen (billionai) #endif 80737f219c8SBruno Larsen (billionai) 80837f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 80937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 810a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 81137f219c8SBruno Larsen (billionai) { 812f5b6daacSRichard Henderson gen_icount_io_start(ctx); 81337f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 81437f219c8SBruno Larsen (billionai) } 81537f219c8SBruno Larsen (billionai) 816a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 81737f219c8SBruno Larsen (billionai) { 818f5b6daacSRichard Henderson gen_icount_io_start(ctx); 81937f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 82037f219c8SBruno Larsen (billionai) } 82137f219c8SBruno Larsen (billionai) 822a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 82337f219c8SBruno Larsen (billionai) { 824f5b6daacSRichard Henderson gen_icount_io_start(ctx); 82537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 82637f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 82737f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 828d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 82937f219c8SBruno Larsen (billionai) } 83037f219c8SBruno Larsen (billionai) 831a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 83237f219c8SBruno Larsen (billionai) { 833f5b6daacSRichard Henderson gen_icount_io_start(ctx); 83437f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) 837cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 838cbd8f17dSCédric Le Goater { 839cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 840cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 841cbd8f17dSCédric Le Goater } 842cbd8f17dSCédric Le Goater 843cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 844cbd8f17dSCédric Le Goater { 845cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 846cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 847cbd8f17dSCédric Le Goater } 848cbd8f17dSCédric Le Goater 849dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 850dd69d140SCédric Le Goater { 851dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 852dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 85347822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 854dd69d140SCédric Le Goater tcg_temp_free(t0); 855dd69d140SCédric Le Goater } 856dd69d140SCédric Le Goater 857a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 85837f219c8SBruno Larsen (billionai) { 859f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 86137f219c8SBruno Larsen (billionai) } 86237f219c8SBruno Larsen (billionai) 863a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 86437f219c8SBruno Larsen (billionai) { 865f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86637f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 86737f219c8SBruno Larsen (billionai) } 86837f219c8SBruno Larsen (billionai) #endif 86937f219c8SBruno Larsen (billionai) 870328c95fcSCédric Le Goater /* PIR */ 87137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 872a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 87337f219c8SBruno Larsen (billionai) { 87437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 87537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 87637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 87737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 87837f219c8SBruno Larsen (billionai) } 87937f219c8SBruno Larsen (billionai) #endif 88037f219c8SBruno Larsen (billionai) 88137f219c8SBruno Larsen (billionai) /* SPE specific registers */ 882a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 88337f219c8SBruno Larsen (billionai) { 88437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 88537f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 88637f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 88737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 88837f219c8SBruno Larsen (billionai) } 88937f219c8SBruno Larsen (billionai) 890a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 89137f219c8SBruno Larsen (billionai) { 89237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 89337f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 89437f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 89537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89637f219c8SBruno Larsen (billionai) } 89737f219c8SBruno Larsen (billionai) 89837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 89937f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 900a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 90137f219c8SBruno Larsen (billionai) { 90237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 90437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 90537f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 90637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 90737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90837f219c8SBruno Larsen (billionai) } 90937f219c8SBruno Larsen (billionai) 910a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 91137f219c8SBruno Larsen (billionai) { 91237f219c8SBruno Larsen (billionai) int sprn_offs; 91337f219c8SBruno Larsen (billionai) 91437f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 91537f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 91637f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 91737f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 91837f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 91937f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 92037f219c8SBruno Larsen (billionai) } else { 9218e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9228e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9238e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 92437f219c8SBruno Larsen (billionai) return; 92537f219c8SBruno Larsen (billionai) } 92637f219c8SBruno Larsen (billionai) 92737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 92937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 93037f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 93137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93337f219c8SBruno Larsen (billionai) } 93437f219c8SBruno Larsen (billionai) #endif 93537f219c8SBruno Larsen (billionai) 93637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 93737f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 938a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 93937f219c8SBruno Larsen (billionai) { 94037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 94137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 94237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 94337f219c8SBruno Larsen (billionai) 94437f219c8SBruno Larsen (billionai) /* 94537f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 94637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 94737f219c8SBruno Larsen (billionai) */ 94837f219c8SBruno Larsen (billionai) 94937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 95037f219c8SBruno Larsen (billionai) if (ctx->pr) { 95137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 95237f219c8SBruno Larsen (billionai) } else { 95337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 95437f219c8SBruno Larsen (billionai) } 95537f219c8SBruno Larsen (billionai) 95637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 95737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 95837f219c8SBruno Larsen (billionai) 95937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 96037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 96137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 96237f219c8SBruno Larsen (billionai) 96337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 96437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 96537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 96637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 96737f219c8SBruno Larsen (billionai) 96837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 96937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 97037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 97137f219c8SBruno Larsen (billionai) } 97237f219c8SBruno Larsen (billionai) 973a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 97437f219c8SBruno Larsen (billionai) { 97537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 97737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 97837f219c8SBruno Larsen (billionai) 97937f219c8SBruno Larsen (billionai) /* 98037f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 98137f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 98237f219c8SBruno Larsen (billionai) */ 98337f219c8SBruno Larsen (billionai) 98437f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 98537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 98637f219c8SBruno Larsen (billionai) 98737f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98937f219c8SBruno Larsen (billionai) 99037f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 99137f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 99237f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 99337f219c8SBruno Larsen (billionai) 99437f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 99537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 99637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 99737f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 99837f219c8SBruno Larsen (billionai) 99937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 100037f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 100137f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 100237f219c8SBruno Larsen (billionai) } 100337f219c8SBruno Larsen (billionai) 1004a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 100537f219c8SBruno Larsen (billionai) { 100637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100937f219c8SBruno Larsen (billionai) 101037f219c8SBruno Larsen (billionai) /* 101137f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 101237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 101337f219c8SBruno Larsen (billionai) */ 101437f219c8SBruno Larsen (billionai) 101537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 101637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101737f219c8SBruno Larsen (billionai) 101837f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 102037f219c8SBruno Larsen (billionai) 102137f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 102237f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 102337f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 102437f219c8SBruno Larsen (billionai) 102537f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 102637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 102837f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 102937f219c8SBruno Larsen (billionai) 103037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 103137f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 103237f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 103337f219c8SBruno Larsen (billionai) } 103437f219c8SBruno Larsen (billionai) #endif 103537f219c8SBruno Larsen (billionai) #endif 103637f219c8SBruno Larsen (billionai) 103737f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1038a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 103937f219c8SBruno Larsen (billionai) { 104037f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 104137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 104237f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 104337f219c8SBruno Larsen (billionai) } 104437f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 104537f219c8SBruno Larsen (billionai) 104637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1047a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 104837f219c8SBruno Larsen (billionai) { 104937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 105037f219c8SBruno Larsen (billionai) 105137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 105237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 105337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105437f219c8SBruno Larsen (billionai) } 105537f219c8SBruno Larsen (billionai) 1056a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 105737f219c8SBruno Larsen (billionai) { 105837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 105937f219c8SBruno Larsen (billionai) 106037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 106137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 106237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 106337f219c8SBruno Larsen (billionai) } 106437f219c8SBruno Larsen (billionai) 1065a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 106637f219c8SBruno Larsen (billionai) { 106737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106837f219c8SBruno Larsen (billionai) 106937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 107037f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 107137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107337f219c8SBruno Larsen (billionai) } 107437f219c8SBruno Larsen (billionai) 1075a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 107637f219c8SBruno Larsen (billionai) { 107737f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 107837f219c8SBruno Larsen (billionai) } 107937f219c8SBruno Larsen (billionai) 1080a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 108137f219c8SBruno Larsen (billionai) { 108237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 108337f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 108437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 108537f219c8SBruno Larsen (billionai) } 1086a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 108737f219c8SBruno Larsen (billionai) { 108837f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 108937f219c8SBruno Larsen (billionai) } 1090a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 109137f219c8SBruno Larsen (billionai) { 109237f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 109337f219c8SBruno Larsen (billionai) } 109437f219c8SBruno Larsen (billionai) 109537f219c8SBruno Larsen (billionai) #endif 109637f219c8SBruno Larsen (billionai) 109737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1098a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 109937f219c8SBruno Larsen (billionai) { 110037f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 110137f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 110237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 110337f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 110437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 110537f219c8SBruno Larsen (billionai) tcg_temp_free(val); 110637f219c8SBruno Larsen (billionai) } 110737f219c8SBruno Larsen (billionai) 1108a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 110937f219c8SBruno Larsen (billionai) { 111037f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 111137f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 111237f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 111337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 111437f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 111537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 111637f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 111737f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 111837f219c8SBruno Larsen (billionai) } 111937f219c8SBruno Larsen (billionai) 112037f219c8SBruno Larsen (billionai) #endif 112137f219c8SBruno Larsen (billionai) 112237f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 112337f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 112437f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 112537f219c8SBruno Larsen (billionai) { 112637f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 112737f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 112837f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 112937f219c8SBruno Larsen (billionai) 113037f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 113137f219c8SBruno Larsen (billionai) 113237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 113337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 113437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 113537f219c8SBruno Larsen (billionai) } 113637f219c8SBruno Larsen (billionai) 113737f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 113837f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 113937f219c8SBruno Larsen (billionai) { 114037f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 114137f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 114237f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 114337f219c8SBruno Larsen (billionai) 114437f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 114537f219c8SBruno Larsen (billionai) 114637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 114737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 114837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 114937f219c8SBruno Larsen (billionai) } 115037f219c8SBruno Larsen (billionai) 1151a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 115237f219c8SBruno Larsen (billionai) { 115337f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 115437f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 115537f219c8SBruno Larsen (billionai) 115637f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 115737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 115837f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 115937f219c8SBruno Larsen (billionai) 116037f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 116137f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 116237f219c8SBruno Larsen (billionai) } 116337f219c8SBruno Larsen (billionai) 1164a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 116537f219c8SBruno Larsen (billionai) { 116637f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 116937f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 117037f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 117137f219c8SBruno Larsen (billionai) 117237f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 117337f219c8SBruno Larsen (billionai) } 117437f219c8SBruno Larsen (billionai) 117537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1176a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 117737f219c8SBruno Larsen (billionai) { 117837f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 117937f219c8SBruno Larsen (billionai) 118037f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 118137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 118237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 118337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 118437f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 118537f219c8SBruno Larsen (billionai) } 118637f219c8SBruno Larsen (billionai) 1187a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 118837f219c8SBruno Larsen (billionai) { 118937f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 119037f219c8SBruno Larsen (billionai) } 119137f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 119237f219c8SBruno Larsen (billionai) 1193a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 119437f219c8SBruno Larsen (billionai) { 119537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 119637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 119737f219c8SBruno Larsen (billionai) } 119837f219c8SBruno Larsen (billionai) 1199a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 120037f219c8SBruno Larsen (billionai) { 120137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 120237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 120337f219c8SBruno Larsen (billionai) } 120437f219c8SBruno Larsen (billionai) 1205a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 120637f219c8SBruno Larsen (billionai) { 120737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 120837f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 120937f219c8SBruno Larsen (billionai) } 121037f219c8SBruno Larsen (billionai) 1211a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 121237f219c8SBruno Larsen (billionai) { 121337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121437f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 121537f219c8SBruno Larsen (billionai) } 121637f219c8SBruno Larsen (billionai) 1217a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 121837f219c8SBruno Larsen (billionai) { 121937f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122037f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 122137f219c8SBruno Larsen (billionai) } 122237f219c8SBruno Larsen (billionai) 1223a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 122437f219c8SBruno Larsen (billionai) { 122537f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122637f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 122737f219c8SBruno Larsen (billionai) } 122837f219c8SBruno Larsen (billionai) 1229a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 123037f219c8SBruno Larsen (billionai) { 123137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123237f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123337f219c8SBruno Larsen (billionai) } 123437f219c8SBruno Larsen (billionai) 1235a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 123637f219c8SBruno Larsen (billionai) { 123737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123937f219c8SBruno Larsen (billionai) } 124037f219c8SBruno Larsen (billionai) 1241a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 124237f219c8SBruno Larsen (billionai) { 124337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124437f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124537f219c8SBruno Larsen (billionai) } 124637f219c8SBruno Larsen (billionai) 1247a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 124837f219c8SBruno Larsen (billionai) { 124937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125037f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125137f219c8SBruno Larsen (billionai) } 125237f219c8SBruno Larsen (billionai) #endif 125337f219c8SBruno Larsen (billionai) 1254fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1255fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1256fcf5ef2aSThomas Huth 1257fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1258fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1259fcf5ef2aSThomas Huth 1260fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1261fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1262fcf5ef2aSThomas Huth 1263fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1264fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1265fcf5ef2aSThomas Huth 1266fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1267fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1268fcf5ef2aSThomas Huth 1269fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1270fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1271fcf5ef2aSThomas Huth 1272fcf5ef2aSThomas Huth typedef struct opcode_t { 1273fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1274fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1275fcf5ef2aSThomas Huth unsigned char pad[4]; 1276fcf5ef2aSThomas Huth #endif 1277fcf5ef2aSThomas Huth opc_handler_t handler; 1278fcf5ef2aSThomas Huth const char *oname; 1279fcf5ef2aSThomas Huth } opcode_t; 1280fcf5ef2aSThomas Huth 12819f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 12829f0cf041SMatheus Ferst { 12839f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 12849f0cf041SMatheus Ferst } 12859f0cf041SMatheus Ferst 1286fcf5ef2aSThomas Huth /* Helpers for priv. check */ 12879f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1288fcf5ef2aSThomas Huth do { \ 12899f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1290fcf5ef2aSThomas Huth } while (0) 1291fcf5ef2aSThomas Huth 1292fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 12939f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 12949f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 12959f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1296fcf5ef2aSThomas Huth #else 12979f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1298fcf5ef2aSThomas Huth do { \ 1299fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 13009f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1301fcf5ef2aSThomas Huth } \ 1302fcf5ef2aSThomas Huth } while (0) 13039f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1304fcf5ef2aSThomas Huth do { \ 1305fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13069f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1307fcf5ef2aSThomas Huth } \ 1308fcf5ef2aSThomas Huth } while (0) 13099f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1310fcf5ef2aSThomas Huth do { \ 1311fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13129f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1313fcf5ef2aSThomas Huth } \ 1314fcf5ef2aSThomas Huth } while (0) 1315fcf5ef2aSThomas Huth #endif 1316fcf5ef2aSThomas Huth 13179f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1318fcf5ef2aSThomas Huth 1319fcf5ef2aSThomas Huth /*****************************************************************************/ 1320fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1321fcf5ef2aSThomas Huth 1322fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1323fcf5ef2aSThomas Huth { \ 1324fcf5ef2aSThomas Huth .opc1 = op1, \ 1325fcf5ef2aSThomas Huth .opc2 = op2, \ 1326fcf5ef2aSThomas Huth .opc3 = op3, \ 1327fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1328fcf5ef2aSThomas Huth .handler = { \ 1329fcf5ef2aSThomas Huth .inval1 = invl, \ 1330fcf5ef2aSThomas Huth .type = _typ, \ 1331fcf5ef2aSThomas Huth .type2 = _typ2, \ 1332fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1333fcf5ef2aSThomas Huth }, \ 1334fcf5ef2aSThomas Huth .oname = stringify(name), \ 1335fcf5ef2aSThomas Huth } 1336fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1337fcf5ef2aSThomas Huth { \ 1338fcf5ef2aSThomas Huth .opc1 = op1, \ 1339fcf5ef2aSThomas Huth .opc2 = op2, \ 1340fcf5ef2aSThomas Huth .opc3 = op3, \ 1341fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1342fcf5ef2aSThomas Huth .handler = { \ 1343fcf5ef2aSThomas Huth .inval1 = invl1, \ 1344fcf5ef2aSThomas Huth .inval2 = invl2, \ 1345fcf5ef2aSThomas Huth .type = _typ, \ 1346fcf5ef2aSThomas Huth .type2 = _typ2, \ 1347fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1348fcf5ef2aSThomas Huth }, \ 1349fcf5ef2aSThomas Huth .oname = stringify(name), \ 1350fcf5ef2aSThomas Huth } 1351fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1352fcf5ef2aSThomas Huth { \ 1353fcf5ef2aSThomas Huth .opc1 = op1, \ 1354fcf5ef2aSThomas Huth .opc2 = op2, \ 1355fcf5ef2aSThomas Huth .opc3 = op3, \ 1356fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1357fcf5ef2aSThomas Huth .handler = { \ 1358fcf5ef2aSThomas Huth .inval1 = invl, \ 1359fcf5ef2aSThomas Huth .type = _typ, \ 1360fcf5ef2aSThomas Huth .type2 = _typ2, \ 1361fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1362fcf5ef2aSThomas Huth }, \ 1363fcf5ef2aSThomas Huth .oname = onam, \ 1364fcf5ef2aSThomas Huth } 1365fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1366fcf5ef2aSThomas Huth { \ 1367fcf5ef2aSThomas Huth .opc1 = op1, \ 1368fcf5ef2aSThomas Huth .opc2 = op2, \ 1369fcf5ef2aSThomas Huth .opc3 = op3, \ 1370fcf5ef2aSThomas Huth .opc4 = op4, \ 1371fcf5ef2aSThomas Huth .handler = { \ 1372fcf5ef2aSThomas Huth .inval1 = invl, \ 1373fcf5ef2aSThomas Huth .type = _typ, \ 1374fcf5ef2aSThomas Huth .type2 = _typ2, \ 1375fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1376fcf5ef2aSThomas Huth }, \ 1377fcf5ef2aSThomas Huth .oname = stringify(name), \ 1378fcf5ef2aSThomas Huth } 1379fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1380fcf5ef2aSThomas Huth { \ 1381fcf5ef2aSThomas Huth .opc1 = op1, \ 1382fcf5ef2aSThomas Huth .opc2 = op2, \ 1383fcf5ef2aSThomas Huth .opc3 = op3, \ 1384fcf5ef2aSThomas Huth .opc4 = op4, \ 1385fcf5ef2aSThomas Huth .handler = { \ 1386fcf5ef2aSThomas Huth .inval1 = invl, \ 1387fcf5ef2aSThomas Huth .type = _typ, \ 1388fcf5ef2aSThomas Huth .type2 = _typ2, \ 1389fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1390fcf5ef2aSThomas Huth }, \ 1391fcf5ef2aSThomas Huth .oname = onam, \ 1392fcf5ef2aSThomas Huth } 1393fcf5ef2aSThomas Huth 1394fcf5ef2aSThomas Huth /* Invalid instruction */ 1395fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1396fcf5ef2aSThomas Huth { 1397fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1398fcf5ef2aSThomas Huth } 1399fcf5ef2aSThomas Huth 1400fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1401fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1402fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1403fcf5ef2aSThomas Huth .type = PPC_NONE, 1404fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1405fcf5ef2aSThomas Huth .handler = gen_invalid, 1406fcf5ef2aSThomas Huth }; 1407fcf5ef2aSThomas Huth 1408fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1409fcf5ef2aSThomas Huth 1410fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1411fcf5ef2aSThomas Huth { 1412fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1413b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1414b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1415fcf5ef2aSThomas Huth 1416b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1417b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1418efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1419efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1420b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1421efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1422efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1423b62b3686Spbonzini@redhat.com 1424b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1425fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1426b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1427fcf5ef2aSThomas Huth 1428fcf5ef2aSThomas Huth tcg_temp_free(t0); 1429b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1430b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1431fcf5ef2aSThomas Huth } 1432fcf5ef2aSThomas Huth 1433fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1434fcf5ef2aSThomas Huth { 1435fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1436fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1437fcf5ef2aSThomas Huth tcg_temp_free(t0); 1438fcf5ef2aSThomas Huth } 1439fcf5ef2aSThomas Huth 1440fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1441fcf5ef2aSThomas Huth { 1442fcf5ef2aSThomas Huth TCGv t0, t1; 1443fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1444fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1445fcf5ef2aSThomas Huth if (s) { 1446fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1447fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1448fcf5ef2aSThomas Huth } else { 1449fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1450fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1451fcf5ef2aSThomas Huth } 1452fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1453fcf5ef2aSThomas Huth tcg_temp_free(t1); 1454fcf5ef2aSThomas Huth tcg_temp_free(t0); 1455fcf5ef2aSThomas Huth } 1456fcf5ef2aSThomas Huth 1457fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1458fcf5ef2aSThomas Huth { 1459fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1460fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1461fcf5ef2aSThomas Huth tcg_temp_free(t0); 1462fcf5ef2aSThomas Huth } 1463fcf5ef2aSThomas Huth 1464fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1465fcf5ef2aSThomas Huth { 1466fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1467fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1468fcf5ef2aSThomas Huth } else { 1469fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1470fcf5ef2aSThomas Huth } 1471fcf5ef2aSThomas Huth } 1472fcf5ef2aSThomas Huth 1473fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1474fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1475fcf5ef2aSThomas Huth { 1476fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1477fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1478fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1479fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1480fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1481fcf5ef2aSThomas Huth 1482fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1483fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1484fcf5ef2aSThomas Huth 1485fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1486fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1487fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1488fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1489fcf5ef2aSThomas Huth 1490fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1491fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1492fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1493fcf5ef2aSThomas Huth 1494fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1495fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1496fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1497fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1498fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1499fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1500fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1501fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1502fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1503fcf5ef2aSThomas Huth } 1504efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1505fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1506fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1507fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1508fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1509fcf5ef2aSThomas Huth } 1510fcf5ef2aSThomas Huth 1511fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1512fcf5ef2aSThomas Huth /* cmpeqb */ 1513fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1514fcf5ef2aSThomas Huth { 1515fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1516fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1517fcf5ef2aSThomas Huth } 1518fcf5ef2aSThomas Huth #endif 1519fcf5ef2aSThomas Huth 1520fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1521fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1522fcf5ef2aSThomas Huth { 1523fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1524fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1525fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1526fcf5ef2aSThomas Huth TCGv zr; 1527fcf5ef2aSThomas Huth 1528fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1529fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1530fcf5ef2aSThomas Huth 1531fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1532fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1533fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1534fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1535fcf5ef2aSThomas Huth tcg_temp_free(zr); 1536fcf5ef2aSThomas Huth tcg_temp_free(t0); 1537fcf5ef2aSThomas Huth } 1538fcf5ef2aSThomas Huth 1539fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1540fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1541fcf5ef2aSThomas Huth { 1542fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1543fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1544fcf5ef2aSThomas Huth } 1545fcf5ef2aSThomas Huth 1546fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1547fcf5ef2aSThomas Huth 1548fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1549fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1550fcf5ef2aSThomas Huth { 1551fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1552fcf5ef2aSThomas Huth 1553fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1554fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1555fcf5ef2aSThomas Huth if (sub) { 1556fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1557fcf5ef2aSThomas Huth } else { 1558fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1559fcf5ef2aSThomas Huth } 1560fcf5ef2aSThomas Huth tcg_temp_free(t0); 1561fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1562dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1563dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1564dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1565fcf5ef2aSThomas Huth } 1566dc0ad844SNikunj A Dadhania } else { 1567dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1568dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1569dc0ad844SNikunj A Dadhania } 157038a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1571dc0ad844SNikunj A Dadhania } 1572fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1573fcf5ef2aSThomas Huth } 1574fcf5ef2aSThomas Huth 15756b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15766b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15774c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15786b10d008SNikunj A Dadhania { 15796b10d008SNikunj A Dadhania TCGv t0; 15806b10d008SNikunj A Dadhania 15816b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 15826b10d008SNikunj A Dadhania return; 15836b10d008SNikunj A Dadhania } 15846b10d008SNikunj A Dadhania 15856b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 158633903d0aSNikunj A Dadhania if (sub) { 158733903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 158833903d0aSNikunj A Dadhania } else { 15896b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 159033903d0aSNikunj A Dadhania } 15916b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 15924c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 15936b10d008SNikunj A Dadhania tcg_temp_free(t0); 15946b10d008SNikunj A Dadhania } 15956b10d008SNikunj A Dadhania 1596fcf5ef2aSThomas Huth /* Common add function */ 1597fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 15984c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 15994c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1600fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1601fcf5ef2aSThomas Huth { 1602fcf5ef2aSThomas Huth TCGv t0 = ret; 1603fcf5ef2aSThomas Huth 1604fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1605fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1606fcf5ef2aSThomas Huth } 1607fcf5ef2aSThomas Huth 1608fcf5ef2aSThomas Huth if (compute_ca) { 1609fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1610efe843d8SDavid Gibson /* 1611efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1612efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1613efe843d8SDavid Gibson * produce the carry into bit 32. 1614efe843d8SDavid Gibson */ 1615fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1616fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1617fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1618fcf5ef2aSThomas Huth if (add_ca) { 16194c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1620fcf5ef2aSThomas Huth } 16214c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1622fcf5ef2aSThomas Huth tcg_temp_free(t1); 16234c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16246b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16254c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16266b10d008SNikunj A Dadhania } 1627fcf5ef2aSThomas Huth } else { 1628fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1629fcf5ef2aSThomas Huth if (add_ca) { 16304c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16314c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1632fcf5ef2aSThomas Huth } else { 16334c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1634fcf5ef2aSThomas Huth } 16354c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1636fcf5ef2aSThomas Huth tcg_temp_free(zero); 1637fcf5ef2aSThomas Huth } 1638fcf5ef2aSThomas Huth } else { 1639fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1640fcf5ef2aSThomas Huth if (add_ca) { 16414c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1642fcf5ef2aSThomas Huth } 1643fcf5ef2aSThomas Huth } 1644fcf5ef2aSThomas Huth 1645fcf5ef2aSThomas Huth if (compute_ov) { 1646fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1647fcf5ef2aSThomas Huth } 1648fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1649fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1650fcf5ef2aSThomas Huth } 1651fcf5ef2aSThomas Huth 165211f4e8f8SRichard Henderson if (t0 != ret) { 1653fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1654fcf5ef2aSThomas Huth tcg_temp_free(t0); 1655fcf5ef2aSThomas Huth } 1656fcf5ef2aSThomas Huth } 1657fcf5ef2aSThomas Huth /* Add functions with two operands */ 16584c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1659fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1660fcf5ef2aSThomas Huth { \ 1661fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1662fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16634c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1664fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1665fcf5ef2aSThomas Huth } 1666fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16674c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1668fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1669fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1670fcf5ef2aSThomas Huth { \ 1671fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1672fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1673fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16744c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1675fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1676fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1677fcf5ef2aSThomas Huth } 1678fcf5ef2aSThomas Huth 1679fcf5ef2aSThomas Huth /* add add. addo addo. */ 16804c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16814c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1682fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16834c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16844c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1685fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 16864c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 16874c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1688fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 16894c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 16904c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 16914c5920afSSuraj Jitindar Singh /* addex */ 16924c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1693fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 16944c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 16954c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1696fcf5ef2aSThomas Huth /* addic addic.*/ 1697fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1698fcf5ef2aSThomas Huth { 1699fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1700fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17014c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1702fcf5ef2aSThomas Huth tcg_temp_free(c); 1703fcf5ef2aSThomas Huth } 1704fcf5ef2aSThomas Huth 1705fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1706fcf5ef2aSThomas Huth { 1707fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1708fcf5ef2aSThomas Huth } 1709fcf5ef2aSThomas Huth 1710fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1711fcf5ef2aSThomas Huth { 1712fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1713fcf5ef2aSThomas Huth } 1714fcf5ef2aSThomas Huth 1715fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1716fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1717fcf5ef2aSThomas Huth { 1718fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1719fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1720fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1721fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1722fcf5ef2aSThomas Huth 1723fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1724fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1725fcf5ef2aSThomas Huth if (sign) { 1726fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1727fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1728fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1729fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1730fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1731fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1732fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1733fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1734fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1735fcf5ef2aSThomas Huth } else { 1736fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1737fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1738fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1739fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1740fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1741fcf5ef2aSThomas Huth } 1742fcf5ef2aSThomas Huth if (compute_ov) { 1743fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1744c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1745c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1746c44027ffSNikunj A Dadhania } 1747fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1748fcf5ef2aSThomas Huth } 1749fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1750fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1751fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1752fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1753fcf5ef2aSThomas Huth 1754efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1755fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1756fcf5ef2aSThomas Huth } 1757efe843d8SDavid Gibson } 1758fcf5ef2aSThomas Huth /* Div functions */ 1759fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1760fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1761fcf5ef2aSThomas Huth { \ 1762fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1763fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1764fcf5ef2aSThomas Huth sign, compute_ov); \ 1765fcf5ef2aSThomas Huth } 1766fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1767fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1768fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1769fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1770fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1771fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1772fcf5ef2aSThomas Huth 1773fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1774fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1775fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1776fcf5ef2aSThomas Huth { \ 1777fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1778fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1779fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1780fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1781fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1782fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1783fcf5ef2aSThomas Huth } \ 1784fcf5ef2aSThomas Huth } 1785fcf5ef2aSThomas Huth 1786fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1787fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1788fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1789fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1790fcf5ef2aSThomas Huth 1791fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1792fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1793fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1794fcf5ef2aSThomas Huth { 1795fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1796fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1797fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1798fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1799fcf5ef2aSThomas Huth 1800fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1801fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1802fcf5ef2aSThomas Huth if (sign) { 1803fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1804fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1805fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1806fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1807fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1808fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1809fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1810fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1811fcf5ef2aSThomas Huth } else { 1812fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1813fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1814fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1815fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1816fcf5ef2aSThomas Huth } 1817fcf5ef2aSThomas Huth if (compute_ov) { 1818fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1819c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1820c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1821c44027ffSNikunj A Dadhania } 1822fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1823fcf5ef2aSThomas Huth } 1824fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1825fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1826fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1827fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1828fcf5ef2aSThomas Huth 1829efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1830fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1831fcf5ef2aSThomas Huth } 1832efe843d8SDavid Gibson } 1833fcf5ef2aSThomas Huth 1834fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1835fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1836fcf5ef2aSThomas Huth { \ 1837fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1838fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1839fcf5ef2aSThomas Huth sign, compute_ov); \ 1840fcf5ef2aSThomas Huth } 1841c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1842fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1843fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1844c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1845fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1846fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1847fcf5ef2aSThomas Huth 1848fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1849fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1850fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1851fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1852fcf5ef2aSThomas Huth #endif 1853fcf5ef2aSThomas Huth 1854fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1855fcf5ef2aSThomas Huth TCGv arg2, int sign) 1856fcf5ef2aSThomas Huth { 1857fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1858fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1859fcf5ef2aSThomas Huth 1860fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1861fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1862fcf5ef2aSThomas Huth if (sign) { 1863fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1864fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1865fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1866fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1867fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1868fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1869fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1870fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1871fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1872fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1873fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1874fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1875fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1876fcf5ef2aSThomas Huth } else { 1877fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1878fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1879fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1880fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1881fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1882fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1883fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1884fcf5ef2aSThomas Huth } 1885fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1886fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1887fcf5ef2aSThomas Huth } 1888fcf5ef2aSThomas Huth 1889fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1890fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1891fcf5ef2aSThomas Huth { \ 1892fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1893fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1894fcf5ef2aSThomas Huth sign); \ 1895fcf5ef2aSThomas Huth } 1896fcf5ef2aSThomas Huth 1897fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1898fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1899fcf5ef2aSThomas Huth 1900fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1901fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1902fcf5ef2aSThomas Huth TCGv arg2, int sign) 1903fcf5ef2aSThomas Huth { 1904fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1905fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1906fcf5ef2aSThomas Huth 1907fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1908fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1909fcf5ef2aSThomas Huth if (sign) { 1910fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1911fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1912fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1913fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1914fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1915fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1916fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1917fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1918fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1919fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1920fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1921fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1922fcf5ef2aSThomas Huth } else { 1923fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1924fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1925fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1926fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1927fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1928fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1929fcf5ef2aSThomas Huth } 1930fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1931fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1932fcf5ef2aSThomas Huth } 1933fcf5ef2aSThomas Huth 1934fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1935fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1936fcf5ef2aSThomas Huth { \ 1937fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1938fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1939fcf5ef2aSThomas Huth sign); \ 1940fcf5ef2aSThomas Huth } 1941fcf5ef2aSThomas Huth 1942fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1943fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1944fcf5ef2aSThomas Huth #endif 1945fcf5ef2aSThomas Huth 1946fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1947fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1948fcf5ef2aSThomas Huth { 1949fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1950fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1951fcf5ef2aSThomas Huth 1952fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1953fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1954fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1955fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1956fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1957fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1958efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1959fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1960fcf5ef2aSThomas Huth } 1961efe843d8SDavid Gibson } 1962fcf5ef2aSThomas Huth 1963fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1964fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1965fcf5ef2aSThomas Huth { 1966fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1967fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1968fcf5ef2aSThomas Huth 1969fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1970fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1971fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1972fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1973fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1974fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1975efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1976fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1977fcf5ef2aSThomas Huth } 1978efe843d8SDavid Gibson } 1979fcf5ef2aSThomas Huth 1980fcf5ef2aSThomas Huth /* mullw mullw. */ 1981fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1982fcf5ef2aSThomas Huth { 1983fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1984fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1985fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1986fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1987fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1988fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1989fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1990fcf5ef2aSThomas Huth tcg_temp_free(t0); 1991fcf5ef2aSThomas Huth tcg_temp_free(t1); 1992fcf5ef2aSThomas Huth #else 1993fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1994fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1995fcf5ef2aSThomas Huth #endif 1996efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1997fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1998fcf5ef2aSThomas Huth } 1999efe843d8SDavid Gibson } 2000fcf5ef2aSThomas Huth 2001fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2002fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2003fcf5ef2aSThomas Huth { 2004fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2005fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2006fcf5ef2aSThomas Huth 2007fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2008fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2009fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2010fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2011fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2012fcf5ef2aSThomas Huth #else 2013fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2014fcf5ef2aSThomas Huth #endif 2015fcf5ef2aSThomas Huth 2016fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2017fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2018fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 201961aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 202061aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 202161aa9a69SNikunj A Dadhania } 2022fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2023fcf5ef2aSThomas Huth 2024fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2025fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2026efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2027fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2028fcf5ef2aSThomas Huth } 2029efe843d8SDavid Gibson } 2030fcf5ef2aSThomas Huth 2031fcf5ef2aSThomas Huth /* mulli */ 2032fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2033fcf5ef2aSThomas Huth { 2034fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2035fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2036fcf5ef2aSThomas Huth } 2037fcf5ef2aSThomas Huth 2038fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2039fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2040fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2041fcf5ef2aSThomas Huth { 2042fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2043fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2044fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2045fcf5ef2aSThomas Huth tcg_temp_free(lo); 2046fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2047fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2048fcf5ef2aSThomas Huth } 2049fcf5ef2aSThomas Huth } 2050fcf5ef2aSThomas Huth 2051fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2052fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2053fcf5ef2aSThomas Huth { 2054fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2055fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2056fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2057fcf5ef2aSThomas Huth tcg_temp_free(lo); 2058fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2059fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2060fcf5ef2aSThomas Huth } 2061fcf5ef2aSThomas Huth } 2062fcf5ef2aSThomas Huth 2063fcf5ef2aSThomas Huth /* mulld mulld. */ 2064fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2065fcf5ef2aSThomas Huth { 2066fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2067fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2068efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2069fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2070fcf5ef2aSThomas Huth } 2071efe843d8SDavid Gibson } 2072fcf5ef2aSThomas Huth 2073fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2074fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2075fcf5ef2aSThomas Huth { 2076fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2077fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2078fcf5ef2aSThomas Huth 2079fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2080fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2081fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2082fcf5ef2aSThomas Huth 2083fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2084fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 208561aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 208661aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 208761aa9a69SNikunj A Dadhania } 2088fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2089fcf5ef2aSThomas Huth 2090fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2091fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2092fcf5ef2aSThomas Huth 2093fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2094fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2095fcf5ef2aSThomas Huth } 2096fcf5ef2aSThomas Huth } 2097fcf5ef2aSThomas Huth #endif 2098fcf5ef2aSThomas Huth 2099fcf5ef2aSThomas Huth /* Common subf function */ 2100fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2101fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2102fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2103fcf5ef2aSThomas Huth { 2104fcf5ef2aSThomas Huth TCGv t0 = ret; 2105fcf5ef2aSThomas Huth 2106fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2107fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2108fcf5ef2aSThomas Huth } 2109fcf5ef2aSThomas Huth 2110fcf5ef2aSThomas Huth if (compute_ca) { 2111fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2112fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2113efe843d8SDavid Gibson /* 2114efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2115efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2116efe843d8SDavid Gibson * produce the carry into bit 32. 2117efe843d8SDavid Gibson */ 2118fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2119fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2120fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2121fcf5ef2aSThomas Huth if (add_ca) { 2122fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2123fcf5ef2aSThomas Huth } else { 2124fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2125fcf5ef2aSThomas Huth } 2126fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2127fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2128fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2129fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2130fcf5ef2aSThomas Huth tcg_temp_free(t1); 2131e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 213233903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 213333903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 213433903d0aSNikunj A Dadhania } 2135fcf5ef2aSThomas Huth } else if (add_ca) { 2136fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2137fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2138fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2139fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2140fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21414c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2142fcf5ef2aSThomas Huth tcg_temp_free(zero); 2143fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2144fcf5ef2aSThomas Huth } else { 2145fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2146fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21474c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2148fcf5ef2aSThomas Huth } 2149fcf5ef2aSThomas Huth } else if (add_ca) { 2150efe843d8SDavid Gibson /* 2151efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2152efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2153efe843d8SDavid Gibson */ 2154fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2155fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2156fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2157fcf5ef2aSThomas Huth } else { 2158fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2159fcf5ef2aSThomas Huth } 2160fcf5ef2aSThomas Huth 2161fcf5ef2aSThomas Huth if (compute_ov) { 2162fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2163fcf5ef2aSThomas Huth } 2164fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2165fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2166fcf5ef2aSThomas Huth } 2167fcf5ef2aSThomas Huth 216811f4e8f8SRichard Henderson if (t0 != ret) { 2169fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2170fcf5ef2aSThomas Huth tcg_temp_free(t0); 2171fcf5ef2aSThomas Huth } 2172fcf5ef2aSThomas Huth } 2173fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2174fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2175fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2176fcf5ef2aSThomas Huth { \ 2177fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2178fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2179fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2180fcf5ef2aSThomas Huth } 2181fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2182fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2183fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2184fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2185fcf5ef2aSThomas Huth { \ 2186fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2187fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2188fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2189fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2190fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2191fcf5ef2aSThomas Huth } 2192fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2193fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2194fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2195fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2196fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2197fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2198fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2199fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2200fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2201fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2202fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2203fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2204fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2205fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2206fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2207fcf5ef2aSThomas Huth 2208fcf5ef2aSThomas Huth /* subfic */ 2209fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2210fcf5ef2aSThomas Huth { 2211fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2212fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2213fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2214fcf5ef2aSThomas Huth tcg_temp_free(c); 2215fcf5ef2aSThomas Huth } 2216fcf5ef2aSThomas Huth 2217fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2218fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2219fcf5ef2aSThomas Huth { 2220fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2221fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2222fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2223fcf5ef2aSThomas Huth tcg_temp_free(zero); 2224fcf5ef2aSThomas Huth } 2225fcf5ef2aSThomas Huth 2226fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2227fcf5ef2aSThomas Huth { 22281480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22291480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22301480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22311480d71cSNikunj A Dadhania } 2232fcf5ef2aSThomas Huth } 2233fcf5ef2aSThomas Huth 2234fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2235fcf5ef2aSThomas Huth { 2236fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2237fcf5ef2aSThomas Huth } 2238fcf5ef2aSThomas Huth 2239fcf5ef2aSThomas Huth /*** Integer logical ***/ 2240fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2241fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2242fcf5ef2aSThomas Huth { \ 2243fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2244fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2245fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2246fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2247fcf5ef2aSThomas Huth } 2248fcf5ef2aSThomas Huth 2249fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2250fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2251fcf5ef2aSThomas Huth { \ 2252fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2253fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2254fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2255fcf5ef2aSThomas Huth } 2256fcf5ef2aSThomas Huth 2257fcf5ef2aSThomas Huth /* and & and. */ 2258fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2259fcf5ef2aSThomas Huth /* andc & andc. */ 2260fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2261fcf5ef2aSThomas Huth 2262fcf5ef2aSThomas Huth /* andi. */ 2263fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2264fcf5ef2aSThomas Huth { 2265efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2266efe843d8SDavid Gibson UIMM(ctx->opcode)); 2267fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2268fcf5ef2aSThomas Huth } 2269fcf5ef2aSThomas Huth 2270fcf5ef2aSThomas Huth /* andis. */ 2271fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2272fcf5ef2aSThomas Huth { 2273efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2274efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2275fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2276fcf5ef2aSThomas Huth } 2277fcf5ef2aSThomas Huth 2278fcf5ef2aSThomas Huth /* cntlzw */ 2279fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2280fcf5ef2aSThomas Huth { 22819b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22829b8514e5SRichard Henderson 22839b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22849b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22859b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22869b8514e5SRichard Henderson tcg_temp_free_i32(t); 22879b8514e5SRichard Henderson 2288efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2289fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2290fcf5ef2aSThomas Huth } 2291efe843d8SDavid Gibson } 2292fcf5ef2aSThomas Huth 2293fcf5ef2aSThomas Huth /* cnttzw */ 2294fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2295fcf5ef2aSThomas Huth { 22969b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22979b8514e5SRichard Henderson 22989b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22999b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23009b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23019b8514e5SRichard Henderson tcg_temp_free_i32(t); 23029b8514e5SRichard Henderson 2303fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2304fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2305fcf5ef2aSThomas Huth } 2306fcf5ef2aSThomas Huth } 2307fcf5ef2aSThomas Huth 2308fcf5ef2aSThomas Huth /* eqv & eqv. */ 2309fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2310fcf5ef2aSThomas Huth /* extsb & extsb. */ 2311fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2312fcf5ef2aSThomas Huth /* extsh & extsh. */ 2313fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2314fcf5ef2aSThomas Huth /* nand & nand. */ 2315fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2316fcf5ef2aSThomas Huth /* nor & nor. */ 2317fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2318fcf5ef2aSThomas Huth 2319fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2320fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2321fcf5ef2aSThomas Huth { 2322fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2323fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2324fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2325fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2326fcf5ef2aSThomas Huth 2327fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2328b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2329fcf5ef2aSThomas Huth } 2330fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2331fcf5ef2aSThomas Huth 2332fcf5ef2aSThomas Huth /* or & or. */ 2333fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2334fcf5ef2aSThomas Huth { 2335fcf5ef2aSThomas Huth int rs, ra, rb; 2336fcf5ef2aSThomas Huth 2337fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2338fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2339fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2340fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2341fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2342efe843d8SDavid Gibson if (rs != rb) { 2343fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2344efe843d8SDavid Gibson } else { 2345fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2346efe843d8SDavid Gibson } 2347efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2348fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2349efe843d8SDavid Gibson } 2350fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2351fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2352fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2353fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2354fcf5ef2aSThomas Huth int prio = 0; 2355fcf5ef2aSThomas Huth 2356fcf5ef2aSThomas Huth switch (rs) { 2357fcf5ef2aSThomas Huth case 1: 2358fcf5ef2aSThomas Huth /* Set process priority to low */ 2359fcf5ef2aSThomas Huth prio = 2; 2360fcf5ef2aSThomas Huth break; 2361fcf5ef2aSThomas Huth case 6: 2362fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2363fcf5ef2aSThomas Huth prio = 3; 2364fcf5ef2aSThomas Huth break; 2365fcf5ef2aSThomas Huth case 2: 2366fcf5ef2aSThomas Huth /* Set process priority to normal */ 2367fcf5ef2aSThomas Huth prio = 4; 2368fcf5ef2aSThomas Huth break; 2369fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2370fcf5ef2aSThomas Huth case 31: 2371fcf5ef2aSThomas Huth if (!ctx->pr) { 2372fcf5ef2aSThomas Huth /* Set process priority to very low */ 2373fcf5ef2aSThomas Huth prio = 1; 2374fcf5ef2aSThomas Huth } 2375fcf5ef2aSThomas Huth break; 2376fcf5ef2aSThomas Huth case 5: 2377fcf5ef2aSThomas Huth if (!ctx->pr) { 2378fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2379fcf5ef2aSThomas Huth prio = 5; 2380fcf5ef2aSThomas Huth } 2381fcf5ef2aSThomas Huth break; 2382fcf5ef2aSThomas Huth case 3: 2383fcf5ef2aSThomas Huth if (!ctx->pr) { 2384fcf5ef2aSThomas Huth /* Set process priority to high */ 2385fcf5ef2aSThomas Huth prio = 6; 2386fcf5ef2aSThomas Huth } 2387fcf5ef2aSThomas Huth break; 2388fcf5ef2aSThomas Huth case 7: 2389fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2390fcf5ef2aSThomas Huth /* Set process priority to very high */ 2391fcf5ef2aSThomas Huth prio = 7; 2392fcf5ef2aSThomas Huth } 2393fcf5ef2aSThomas Huth break; 2394fcf5ef2aSThomas Huth #endif 2395fcf5ef2aSThomas Huth default: 2396fcf5ef2aSThomas Huth break; 2397fcf5ef2aSThomas Huth } 2398fcf5ef2aSThomas Huth if (prio) { 2399fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2400fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2401fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2402fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2403fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2404fcf5ef2aSThomas Huth tcg_temp_free(t0); 2405fcf5ef2aSThomas Huth } 2406fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2407efe843d8SDavid Gibson /* 2408efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2409efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2410efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2411efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2412fcf5ef2aSThomas Huth */ 2413fcf5ef2aSThomas Huth gen_pause(ctx); 2414fcf5ef2aSThomas Huth #endif 2415fcf5ef2aSThomas Huth #endif 2416fcf5ef2aSThomas Huth } 2417fcf5ef2aSThomas Huth } 2418fcf5ef2aSThomas Huth /* orc & orc. */ 2419fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2420fcf5ef2aSThomas Huth 2421fcf5ef2aSThomas Huth /* xor & xor. */ 2422fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2423fcf5ef2aSThomas Huth { 2424fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2425efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2426efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2427efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2428efe843d8SDavid Gibson } else { 2429fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2430efe843d8SDavid Gibson } 2431efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2432fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2433fcf5ef2aSThomas Huth } 2434efe843d8SDavid Gibson } 2435fcf5ef2aSThomas Huth 2436fcf5ef2aSThomas Huth /* ori */ 2437fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2438fcf5ef2aSThomas Huth { 2439fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2440fcf5ef2aSThomas Huth 2441fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2442fcf5ef2aSThomas Huth return; 2443fcf5ef2aSThomas Huth } 2444fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2445fcf5ef2aSThomas Huth } 2446fcf5ef2aSThomas Huth 2447fcf5ef2aSThomas Huth /* oris */ 2448fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2449fcf5ef2aSThomas Huth { 2450fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2451fcf5ef2aSThomas Huth 2452fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2453fcf5ef2aSThomas Huth /* NOP */ 2454fcf5ef2aSThomas Huth return; 2455fcf5ef2aSThomas Huth } 2456efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2457efe843d8SDavid Gibson uimm << 16); 2458fcf5ef2aSThomas Huth } 2459fcf5ef2aSThomas Huth 2460fcf5ef2aSThomas Huth /* xori */ 2461fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2462fcf5ef2aSThomas Huth { 2463fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2464fcf5ef2aSThomas Huth 2465fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2466fcf5ef2aSThomas Huth /* NOP */ 2467fcf5ef2aSThomas Huth return; 2468fcf5ef2aSThomas Huth } 2469fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2470fcf5ef2aSThomas Huth } 2471fcf5ef2aSThomas Huth 2472fcf5ef2aSThomas Huth /* xoris */ 2473fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2474fcf5ef2aSThomas Huth { 2475fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2476fcf5ef2aSThomas Huth 2477fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2478fcf5ef2aSThomas Huth /* NOP */ 2479fcf5ef2aSThomas Huth return; 2480fcf5ef2aSThomas Huth } 2481efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2482efe843d8SDavid Gibson uimm << 16); 2483fcf5ef2aSThomas Huth } 2484fcf5ef2aSThomas Huth 2485fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2486fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2487fcf5ef2aSThomas Huth { 2488fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2489fcf5ef2aSThomas Huth } 2490fcf5ef2aSThomas Huth 2491fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2492fcf5ef2aSThomas Huth { 249379770002SRichard Henderson #if defined(TARGET_PPC64) 2494fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 249579770002SRichard Henderson #else 249679770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 249779770002SRichard Henderson #endif 2498fcf5ef2aSThomas Huth } 2499fcf5ef2aSThomas Huth 2500fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2501fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2502fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2503fcf5ef2aSThomas Huth { 250479770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2505fcf5ef2aSThomas Huth } 2506fcf5ef2aSThomas Huth #endif 2507fcf5ef2aSThomas Huth 2508fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2509fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2510fcf5ef2aSThomas Huth { 2511fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2512fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2513fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2514fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2515fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2516fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2517fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2518fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2519fcf5ef2aSThomas Huth tcg_temp_free(t0); 2520fcf5ef2aSThomas Huth } 2521fcf5ef2aSThomas Huth 2522fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2523fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2524fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2525fcf5ef2aSThomas Huth { 2526fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2527fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2528fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2529fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2530fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2531fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2532fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2533fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2534fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2535fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2536fcf5ef2aSThomas Huth tcg_temp_free(t0); 2537fcf5ef2aSThomas Huth } 2538fcf5ef2aSThomas Huth #endif 2539fcf5ef2aSThomas Huth 2540fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2541fcf5ef2aSThomas Huth /* bpermd */ 2542fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2543fcf5ef2aSThomas Huth { 2544fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2545fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2546fcf5ef2aSThomas Huth } 2547fcf5ef2aSThomas Huth #endif 2548fcf5ef2aSThomas Huth 2549fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2550fcf5ef2aSThomas Huth /* extsw & extsw. */ 2551fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2552fcf5ef2aSThomas Huth 2553fcf5ef2aSThomas Huth /* cntlzd */ 2554fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2555fcf5ef2aSThomas Huth { 25569b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2557efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2558fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2559fcf5ef2aSThomas Huth } 2560efe843d8SDavid Gibson } 2561fcf5ef2aSThomas Huth 2562fcf5ef2aSThomas Huth /* cnttzd */ 2563fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2564fcf5ef2aSThomas Huth { 25659b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2566fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2567fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2568fcf5ef2aSThomas Huth } 2569fcf5ef2aSThomas Huth } 2570fcf5ef2aSThomas Huth 2571fcf5ef2aSThomas Huth /* darn */ 2572fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2573fcf5ef2aSThomas Huth { 2574fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2575fcf5ef2aSThomas Huth 25767e4357f6SRichard Henderson if (l > 2) { 25777e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25787e4357f6SRichard Henderson } else { 2579f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2580fcf5ef2aSThomas Huth if (l == 0) { 2581fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25827e4357f6SRichard Henderson } else { 2583fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2584fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25857e4357f6SRichard Henderson } 2586fcf5ef2aSThomas Huth } 2587fcf5ef2aSThomas Huth } 2588fcf5ef2aSThomas Huth #endif 2589fcf5ef2aSThomas Huth 2590fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2591fcf5ef2aSThomas Huth 2592fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2593fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2594fcf5ef2aSThomas Huth { 2595fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2596fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2597fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2598fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2599fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2600fcf5ef2aSThomas Huth 2601fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2602fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2603fcf5ef2aSThomas Huth } else { 2604fcf5ef2aSThomas Huth target_ulong mask; 2605c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2606fcf5ef2aSThomas Huth TCGv t1; 2607fcf5ef2aSThomas Huth 2608fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2609fcf5ef2aSThomas Huth mb += 32; 2610fcf5ef2aSThomas Huth me += 32; 2611fcf5ef2aSThomas Huth #endif 2612fcf5ef2aSThomas Huth mask = MASK(mb, me); 2613fcf5ef2aSThomas Huth 2614c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2615c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2616c4f6a4a3SDaniele Buono mask_in_32b = false; 2617c4f6a4a3SDaniele Buono } 2618c4f6a4a3SDaniele Buono #endif 2619fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2620c4f6a4a3SDaniele Buono if (mask_in_32b) { 2621fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2622fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2623fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2624fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2625fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2626fcf5ef2aSThomas Huth } else { 2627fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2628fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2629fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2630fcf5ef2aSThomas Huth #else 2631fcf5ef2aSThomas Huth g_assert_not_reached(); 2632fcf5ef2aSThomas Huth #endif 2633fcf5ef2aSThomas Huth } 2634fcf5ef2aSThomas Huth 2635fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2636fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2637fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2638fcf5ef2aSThomas Huth tcg_temp_free(t1); 2639fcf5ef2aSThomas Huth } 2640fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2641fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2642fcf5ef2aSThomas Huth } 2643fcf5ef2aSThomas Huth } 2644fcf5ef2aSThomas Huth 2645fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2646fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2647fcf5ef2aSThomas Huth { 2648fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2649fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26507b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26517b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26527b4d326fSRichard Henderson int me = ME(ctx->opcode); 26537b4d326fSRichard Henderson int len = me - mb + 1; 26547b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2655fcf5ef2aSThomas Huth 26567b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26577b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26587b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26597b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2660fcf5ef2aSThomas Huth } else { 2661fcf5ef2aSThomas Huth target_ulong mask; 2662c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2663fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2664fcf5ef2aSThomas Huth mb += 32; 2665fcf5ef2aSThomas Huth me += 32; 2666fcf5ef2aSThomas Huth #endif 2667fcf5ef2aSThomas Huth mask = MASK(mb, me); 2668c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2669c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2670c4f6a4a3SDaniele Buono mask_in_32b = false; 2671c4f6a4a3SDaniele Buono } 2672c4f6a4a3SDaniele Buono #endif 2673c4f6a4a3SDaniele Buono if (mask_in_32b) { 26747b4d326fSRichard Henderson if (sh == 0) { 26757b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 267694f040aaSVitaly Chikunov } else { 2677fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2678fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2679fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2680fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2681fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2682fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 268394f040aaSVitaly Chikunov } 2684fcf5ef2aSThomas Huth } else { 2685fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2686fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2687fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2688fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2689fcf5ef2aSThomas Huth #else 2690fcf5ef2aSThomas Huth g_assert_not_reached(); 2691fcf5ef2aSThomas Huth #endif 2692fcf5ef2aSThomas Huth } 2693fcf5ef2aSThomas Huth } 2694fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2695fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2696fcf5ef2aSThomas Huth } 2697fcf5ef2aSThomas Huth } 2698fcf5ef2aSThomas Huth 2699fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2700fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2701fcf5ef2aSThomas Huth { 2702fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2703fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2704fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2705fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2706fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2707fcf5ef2aSThomas Huth target_ulong mask; 2708c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2709fcf5ef2aSThomas Huth 2710fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2711fcf5ef2aSThomas Huth mb += 32; 2712fcf5ef2aSThomas Huth me += 32; 2713fcf5ef2aSThomas Huth #endif 2714fcf5ef2aSThomas Huth mask = MASK(mb, me); 2715fcf5ef2aSThomas Huth 2716c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2717c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2718c4f6a4a3SDaniele Buono mask_in_32b = false; 2719c4f6a4a3SDaniele Buono } 2720c4f6a4a3SDaniele Buono #endif 2721c4f6a4a3SDaniele Buono if (mask_in_32b) { 2722fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2723fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2724fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2725fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2726fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2727fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2728fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2729fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2730fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2731fcf5ef2aSThomas Huth } else { 2732fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2733fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2734fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2735fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2736fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2737fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2738fcf5ef2aSThomas Huth #else 2739fcf5ef2aSThomas Huth g_assert_not_reached(); 2740fcf5ef2aSThomas Huth #endif 2741fcf5ef2aSThomas Huth } 2742fcf5ef2aSThomas Huth 2743fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2744fcf5ef2aSThomas Huth 2745fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2746fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2747fcf5ef2aSThomas Huth } 2748fcf5ef2aSThomas Huth } 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2751fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2752fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2753fcf5ef2aSThomas Huth { \ 2754fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2755fcf5ef2aSThomas Huth } \ 2756fcf5ef2aSThomas Huth \ 2757fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2758fcf5ef2aSThomas Huth { \ 2759fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2760fcf5ef2aSThomas Huth } 2761fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2762fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2763fcf5ef2aSThomas Huth { \ 2764fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2765fcf5ef2aSThomas Huth } \ 2766fcf5ef2aSThomas Huth \ 2767fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2768fcf5ef2aSThomas Huth { \ 2769fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2770fcf5ef2aSThomas Huth } \ 2771fcf5ef2aSThomas Huth \ 2772fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2773fcf5ef2aSThomas Huth { \ 2774fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2775fcf5ef2aSThomas Huth } \ 2776fcf5ef2aSThomas Huth \ 2777fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2778fcf5ef2aSThomas Huth { \ 2779fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2780fcf5ef2aSThomas Huth } 2781fcf5ef2aSThomas Huth 2782fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2783fcf5ef2aSThomas Huth { 2784fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2785fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27867b4d326fSRichard Henderson int len = me - mb + 1; 27877b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2788fcf5ef2aSThomas Huth 27897b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27907b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27917b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27927b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2793fcf5ef2aSThomas Huth } else { 2794fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2795fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2796fcf5ef2aSThomas Huth } 2797fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2798fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2799fcf5ef2aSThomas Huth } 2800fcf5ef2aSThomas Huth } 2801fcf5ef2aSThomas Huth 2802fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2803fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2804fcf5ef2aSThomas Huth { 2805fcf5ef2aSThomas Huth uint32_t sh, mb; 2806fcf5ef2aSThomas Huth 2807fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2808fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2809fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2810fcf5ef2aSThomas Huth } 2811fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2812fcf5ef2aSThomas Huth 2813fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2814fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2815fcf5ef2aSThomas Huth { 2816fcf5ef2aSThomas Huth uint32_t sh, me; 2817fcf5ef2aSThomas Huth 2818fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2819fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2820fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2821fcf5ef2aSThomas Huth } 2822fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2823fcf5ef2aSThomas Huth 2824fcf5ef2aSThomas Huth /* rldic - rldic. */ 2825fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2826fcf5ef2aSThomas Huth { 2827fcf5ef2aSThomas Huth uint32_t sh, mb; 2828fcf5ef2aSThomas Huth 2829fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2830fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2831fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2832fcf5ef2aSThomas Huth } 2833fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2834fcf5ef2aSThomas Huth 2835fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2836fcf5ef2aSThomas Huth { 2837fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2838fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2839fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2840fcf5ef2aSThomas Huth TCGv t0; 2841fcf5ef2aSThomas Huth 2842fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2843fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2844fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2845fcf5ef2aSThomas Huth tcg_temp_free(t0); 2846fcf5ef2aSThomas Huth 2847fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2848fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2849fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2850fcf5ef2aSThomas Huth } 2851fcf5ef2aSThomas Huth } 2852fcf5ef2aSThomas Huth 2853fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2854fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2855fcf5ef2aSThomas Huth { 2856fcf5ef2aSThomas Huth uint32_t mb; 2857fcf5ef2aSThomas Huth 2858fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2859fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2860fcf5ef2aSThomas Huth } 2861fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2862fcf5ef2aSThomas Huth 2863fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2864fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2865fcf5ef2aSThomas Huth { 2866fcf5ef2aSThomas Huth uint32_t me; 2867fcf5ef2aSThomas Huth 2868fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2869fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2870fcf5ef2aSThomas Huth } 2871fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2872fcf5ef2aSThomas Huth 2873fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2874fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2875fcf5ef2aSThomas Huth { 2876fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2877fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2878fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2879fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2880fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2881fcf5ef2aSThomas Huth 2882fcf5ef2aSThomas Huth if (mb <= me) { 2883fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2884fcf5ef2aSThomas Huth } else { 2885fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2886fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2887fcf5ef2aSThomas Huth 2888fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2889fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2890fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2891fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2892fcf5ef2aSThomas Huth tcg_temp_free(t1); 2893fcf5ef2aSThomas Huth } 2894fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2895fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2896fcf5ef2aSThomas Huth } 2897fcf5ef2aSThomas Huth } 2898fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2899fcf5ef2aSThomas Huth #endif 2900fcf5ef2aSThomas Huth 2901fcf5ef2aSThomas Huth /*** Integer shift ***/ 2902fcf5ef2aSThomas Huth 2903fcf5ef2aSThomas Huth /* slw & slw. */ 2904fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2905fcf5ef2aSThomas Huth { 2906fcf5ef2aSThomas Huth TCGv t0, t1; 2907fcf5ef2aSThomas Huth 2908fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2909fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2910fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2911fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2912fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2913fcf5ef2aSThomas Huth #else 2914fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2915fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2916fcf5ef2aSThomas Huth #endif 2917fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2918fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2919fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2920fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2921fcf5ef2aSThomas Huth tcg_temp_free(t1); 2922fcf5ef2aSThomas Huth tcg_temp_free(t0); 2923fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2924efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2925fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2926fcf5ef2aSThomas Huth } 2927efe843d8SDavid Gibson } 2928fcf5ef2aSThomas Huth 2929fcf5ef2aSThomas Huth /* sraw & sraw. */ 2930fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2931fcf5ef2aSThomas Huth { 2932fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2933fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2934efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2935fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2936fcf5ef2aSThomas Huth } 2937efe843d8SDavid Gibson } 2938fcf5ef2aSThomas Huth 2939fcf5ef2aSThomas Huth /* srawi & srawi. */ 2940fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2941fcf5ef2aSThomas Huth { 2942fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2943fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2944fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2945fcf5ef2aSThomas Huth if (sh == 0) { 2946fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2947fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2948af1c259fSSandipan Das if (is_isa300(ctx)) { 2949af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2950af1c259fSSandipan Das } 2951fcf5ef2aSThomas Huth } else { 2952fcf5ef2aSThomas Huth TCGv t0; 2953fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2954fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2955fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2956fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2957fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2958fcf5ef2aSThomas Huth tcg_temp_free(t0); 2959fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2960af1c259fSSandipan Das if (is_isa300(ctx)) { 2961af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2962af1c259fSSandipan Das } 2963fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2964fcf5ef2aSThomas Huth } 2965fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2966fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2967fcf5ef2aSThomas Huth } 2968fcf5ef2aSThomas Huth } 2969fcf5ef2aSThomas Huth 2970fcf5ef2aSThomas Huth /* srw & srw. */ 2971fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2972fcf5ef2aSThomas Huth { 2973fcf5ef2aSThomas Huth TCGv t0, t1; 2974fcf5ef2aSThomas Huth 2975fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2976fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2977fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2978fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2979fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2980fcf5ef2aSThomas Huth #else 2981fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2982fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2983fcf5ef2aSThomas Huth #endif 2984fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2985fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2986fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2987fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2988fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2989fcf5ef2aSThomas Huth tcg_temp_free(t1); 2990fcf5ef2aSThomas Huth tcg_temp_free(t0); 2991efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2992fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2993fcf5ef2aSThomas Huth } 2994efe843d8SDavid Gibson } 2995fcf5ef2aSThomas Huth 2996fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2997fcf5ef2aSThomas Huth /* sld & sld. */ 2998fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2999fcf5ef2aSThomas Huth { 3000fcf5ef2aSThomas Huth TCGv t0, t1; 3001fcf5ef2aSThomas Huth 3002fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3003fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3004fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3005fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3006fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3007fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3008fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3009fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3010fcf5ef2aSThomas Huth tcg_temp_free(t1); 3011fcf5ef2aSThomas Huth tcg_temp_free(t0); 3012efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3013fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3014fcf5ef2aSThomas Huth } 3015efe843d8SDavid Gibson } 3016fcf5ef2aSThomas Huth 3017fcf5ef2aSThomas Huth /* srad & srad. */ 3018fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3019fcf5ef2aSThomas Huth { 3020fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3021fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3022efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3023fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3024fcf5ef2aSThomas Huth } 3025efe843d8SDavid Gibson } 3026fcf5ef2aSThomas Huth /* sradi & sradi. */ 3027fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3028fcf5ef2aSThomas Huth { 3029fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3030fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3031fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3032fcf5ef2aSThomas Huth if (sh == 0) { 3033fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3034fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3035af1c259fSSandipan Das if (is_isa300(ctx)) { 3036af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3037af1c259fSSandipan Das } 3038fcf5ef2aSThomas Huth } else { 3039fcf5ef2aSThomas Huth TCGv t0; 3040fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3041fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3042fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3043fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3044fcf5ef2aSThomas Huth tcg_temp_free(t0); 3045fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3046af1c259fSSandipan Das if (is_isa300(ctx)) { 3047af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3048af1c259fSSandipan Das } 3049fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3050fcf5ef2aSThomas Huth } 3051fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3052fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3053fcf5ef2aSThomas Huth } 3054fcf5ef2aSThomas Huth } 3055fcf5ef2aSThomas Huth 3056fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3057fcf5ef2aSThomas Huth { 3058fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3059fcf5ef2aSThomas Huth } 3060fcf5ef2aSThomas Huth 3061fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3062fcf5ef2aSThomas Huth { 3063fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3064fcf5ef2aSThomas Huth } 3065fcf5ef2aSThomas Huth 3066fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3067fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3068fcf5ef2aSThomas Huth { 3069fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3070fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3071fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3072fcf5ef2aSThomas Huth 3073fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3074fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3075fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3076fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3077fcf5ef2aSThomas Huth } 3078fcf5ef2aSThomas Huth } 3079fcf5ef2aSThomas Huth 3080fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3081fcf5ef2aSThomas Huth { 3082fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth 3085fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3086fcf5ef2aSThomas Huth { 3087fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3088fcf5ef2aSThomas Huth } 3089fcf5ef2aSThomas Huth 3090fcf5ef2aSThomas Huth /* srd & srd. */ 3091fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3092fcf5ef2aSThomas Huth { 3093fcf5ef2aSThomas Huth TCGv t0, t1; 3094fcf5ef2aSThomas Huth 3095fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3096fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3097fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3098fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3099fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3100fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3101fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3102fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3103fcf5ef2aSThomas Huth tcg_temp_free(t1); 3104fcf5ef2aSThomas Huth tcg_temp_free(t0); 3105efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3106fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3107fcf5ef2aSThomas Huth } 3108efe843d8SDavid Gibson } 3109fcf5ef2aSThomas Huth #endif 3110fcf5ef2aSThomas Huth 3111fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3112fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3113fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3114fcf5ef2aSThomas Huth target_long maskl) 3115fcf5ef2aSThomas Huth { 3116fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3117fcf5ef2aSThomas Huth 3118fcf5ef2aSThomas Huth simm &= ~maskl; 3119fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3120fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3121fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3122fcf5ef2aSThomas Huth } 3123fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3124fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3125fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3126fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3127fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3128fcf5ef2aSThomas Huth } 3129fcf5ef2aSThomas Huth } else { 3130fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3131fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3132fcf5ef2aSThomas Huth } else { 3133fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3134fcf5ef2aSThomas Huth } 3135fcf5ef2aSThomas Huth } 3136fcf5ef2aSThomas Huth } 3137fcf5ef2aSThomas Huth 3138fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3139fcf5ef2aSThomas Huth { 3140fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3141fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3142fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3143fcf5ef2aSThomas Huth } else { 3144fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3145fcf5ef2aSThomas Huth } 3146fcf5ef2aSThomas Huth } else { 3147fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3148fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3149fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3150fcf5ef2aSThomas Huth } 3151fcf5ef2aSThomas Huth } 3152fcf5ef2aSThomas Huth } 3153fcf5ef2aSThomas Huth 3154fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3155fcf5ef2aSThomas Huth { 3156fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3157fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3158fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3159fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3160fcf5ef2aSThomas Huth } else { 3161fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3162fcf5ef2aSThomas Huth } 3163fcf5ef2aSThomas Huth } 3164fcf5ef2aSThomas Huth 3165fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3166fcf5ef2aSThomas Huth target_long val) 3167fcf5ef2aSThomas Huth { 3168fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3169fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3170fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3171fcf5ef2aSThomas Huth } 3172fcf5ef2aSThomas Huth } 3173fcf5ef2aSThomas Huth 3174fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3175fcf5ef2aSThomas Huth { 3176fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3177fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3178fcf5ef2aSThomas Huth } 3179fcf5ef2aSThomas Huth 3180eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3181eb63efd9SFernando Eckhardt Valle { 3182eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3183eb63efd9SFernando Eckhardt Valle if (ra) { 3184eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3185eb63efd9SFernando Eckhardt Valle } else { 3186eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3187eb63efd9SFernando Eckhardt Valle } 3188eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3189eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3190eb63efd9SFernando Eckhardt Valle } 3191eb63efd9SFernando Eckhardt Valle return ea; 3192eb63efd9SFernando Eckhardt Valle } 3193eb63efd9SFernando Eckhardt Valle 3194fcf5ef2aSThomas Huth /*** Integer load ***/ 3195fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3196fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3197fcf5ef2aSThomas Huth 3198fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3199fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3200fcf5ef2aSThomas Huth TCGv val, \ 3201fcf5ef2aSThomas Huth TCGv addr) \ 3202fcf5ef2aSThomas Huth { \ 3203fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3204fcf5ef2aSThomas Huth } 3205fcf5ef2aSThomas Huth 3206fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3207fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3208fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3209fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3210fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3211fcf5ef2aSThomas Huth 3212fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3213fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3214fcf5ef2aSThomas Huth 3215fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3216fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3217fcf5ef2aSThomas Huth TCGv_i64 val, \ 3218fcf5ef2aSThomas Huth TCGv addr) \ 3219fcf5ef2aSThomas Huth { \ 3220fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3221fcf5ef2aSThomas Huth } 3222fcf5ef2aSThomas Huth 3223fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3224fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3225fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3226fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3227fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3228fcf5ef2aSThomas Huth 3229fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3230fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3231fcf5ef2aSThomas Huth #endif 3232fcf5ef2aSThomas Huth 3233fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3234fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3235fcf5ef2aSThomas Huth TCGv val, \ 3236fcf5ef2aSThomas Huth TCGv addr) \ 3237fcf5ef2aSThomas Huth { \ 3238fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3239fcf5ef2aSThomas Huth } 3240fcf5ef2aSThomas Huth 3241e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3242fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3243e8f4c8d6SRichard Henderson #endif 3244fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3245fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3246fcf5ef2aSThomas Huth 3247fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3248fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3249fcf5ef2aSThomas Huth 3250fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3251fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3252fcf5ef2aSThomas Huth TCGv_i64 val, \ 3253fcf5ef2aSThomas Huth TCGv addr) \ 3254fcf5ef2aSThomas Huth { \ 3255fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3256fcf5ef2aSThomas Huth } 3257fcf5ef2aSThomas Huth 3258fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3259fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3260fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3261fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3262fcf5ef2aSThomas Huth 3263fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3264fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3265fcf5ef2aSThomas Huth #endif 3266fcf5ef2aSThomas Huth 3267fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3268fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3269fcf5ef2aSThomas Huth { \ 3270fcf5ef2aSThomas Huth TCGv EA; \ 32719f0cf041SMatheus Ferst chk(ctx); \ 3272fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3273fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3274fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3275fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3276fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3277fcf5ef2aSThomas Huth } 3278fcf5ef2aSThomas Huth 3279fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3280fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3281fcf5ef2aSThomas Huth 3282fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3283fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3284fcf5ef2aSThomas Huth 328550728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 328650728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 328750728199SRoman Kapl { \ 328850728199SRoman Kapl TCGv EA; \ 32899f0cf041SMatheus Ferst CHK_SV(ctx); \ 329050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 329150728199SRoman Kapl EA = tcg_temp_new(); \ 329250728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 329350728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 329450728199SRoman Kapl tcg_temp_free(EA); \ 329550728199SRoman Kapl } 329650728199SRoman Kapl 329750728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 329850728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 329950728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 330050728199SRoman Kapl #if defined(TARGET_PPC64) 3301fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 330250728199SRoman Kapl #endif 330350728199SRoman Kapl 3304fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3305fcf5ef2aSThomas Huth /* CI load/store variants */ 3306fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3307fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3308fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3309fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3310fcf5ef2aSThomas Huth #endif 3311fcf5ef2aSThomas Huth 3312fcf5ef2aSThomas Huth /*** Integer store ***/ 3313fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3314fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3315fcf5ef2aSThomas Huth { \ 3316fcf5ef2aSThomas Huth TCGv EA; \ 33179f0cf041SMatheus Ferst chk(ctx); \ 3318fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3319fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3320fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3321fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3322fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3323fcf5ef2aSThomas Huth } 3324fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3325fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3326fcf5ef2aSThomas Huth 3327fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3328fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3329fcf5ef2aSThomas Huth 333050728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 333150728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 333250728199SRoman Kapl { \ 333350728199SRoman Kapl TCGv EA; \ 33349f0cf041SMatheus Ferst CHK_SV(ctx); \ 333550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 333650728199SRoman Kapl EA = tcg_temp_new(); \ 333750728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 333850728199SRoman Kapl tcg_gen_qemu_st_tl( \ 333950728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 334050728199SRoman Kapl tcg_temp_free(EA); \ 334150728199SRoman Kapl } 334250728199SRoman Kapl 334350728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 334450728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 334550728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 334650728199SRoman Kapl #if defined(TARGET_PPC64) 3347fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 334850728199SRoman Kapl #endif 334950728199SRoman Kapl 3350fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3351fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3352fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3353fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3354fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3355fcf5ef2aSThomas Huth #endif 3356fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3357fcf5ef2aSThomas Huth 3358fcf5ef2aSThomas Huth /* lhbrx */ 3359fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3360fcf5ef2aSThomas Huth 3361fcf5ef2aSThomas Huth /* lwbrx */ 3362fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3363fcf5ef2aSThomas Huth 3364fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3365fcf5ef2aSThomas Huth /* ldbrx */ 3366fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3367fcf5ef2aSThomas Huth /* stdbrx */ 3368fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3369fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3370fcf5ef2aSThomas Huth 3371fcf5ef2aSThomas Huth /* sthbrx */ 3372fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3373fcf5ef2aSThomas Huth /* stwbrx */ 3374fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3375fcf5ef2aSThomas Huth 3376fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3377fcf5ef2aSThomas Huth 3378fcf5ef2aSThomas Huth /* lmw */ 3379fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3380fcf5ef2aSThomas Huth { 3381fcf5ef2aSThomas Huth TCGv t0; 3382fcf5ef2aSThomas Huth TCGv_i32 t1; 3383fcf5ef2aSThomas Huth 3384fcf5ef2aSThomas Huth if (ctx->le_mode) { 3385fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3386fcf5ef2aSThomas Huth return; 3387fcf5ef2aSThomas Huth } 3388fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3389fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3390fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3391fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3392fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3393fcf5ef2aSThomas Huth tcg_temp_free(t0); 3394fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3395fcf5ef2aSThomas Huth } 3396fcf5ef2aSThomas Huth 3397fcf5ef2aSThomas Huth /* stmw */ 3398fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3399fcf5ef2aSThomas Huth { 3400fcf5ef2aSThomas Huth TCGv t0; 3401fcf5ef2aSThomas Huth TCGv_i32 t1; 3402fcf5ef2aSThomas Huth 3403fcf5ef2aSThomas Huth if (ctx->le_mode) { 3404fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3405fcf5ef2aSThomas Huth return; 3406fcf5ef2aSThomas Huth } 3407fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3408fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3409fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3410fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3411fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3412fcf5ef2aSThomas Huth tcg_temp_free(t0); 3413fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3414fcf5ef2aSThomas Huth } 3415fcf5ef2aSThomas Huth 3416fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3417fcf5ef2aSThomas Huth 3418fcf5ef2aSThomas Huth /* lswi */ 3419efe843d8SDavid Gibson /* 3420efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3421efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3422efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3423efe843d8SDavid Gibson * spec... 3424fcf5ef2aSThomas Huth */ 3425fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3426fcf5ef2aSThomas Huth { 3427fcf5ef2aSThomas Huth TCGv t0; 3428fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3429fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3430fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3431fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3432fcf5ef2aSThomas Huth int nr; 3433fcf5ef2aSThomas Huth 3434fcf5ef2aSThomas Huth if (ctx->le_mode) { 3435fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3436fcf5ef2aSThomas Huth return; 3437fcf5ef2aSThomas Huth } 3438efe843d8SDavid Gibson if (nb == 0) { 3439fcf5ef2aSThomas Huth nb = 32; 3440efe843d8SDavid Gibson } 3441f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3442fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3443fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3444fcf5ef2aSThomas Huth return; 3445fcf5ef2aSThomas Huth } 3446fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3447fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3448fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3449fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3450fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3451fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3452fcf5ef2aSThomas Huth tcg_temp_free(t0); 3453fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3454fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3455fcf5ef2aSThomas Huth } 3456fcf5ef2aSThomas Huth 3457fcf5ef2aSThomas Huth /* lswx */ 3458fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3459fcf5ef2aSThomas Huth { 3460fcf5ef2aSThomas Huth TCGv t0; 3461fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3462fcf5ef2aSThomas Huth 3463fcf5ef2aSThomas Huth if (ctx->le_mode) { 3464fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3465fcf5ef2aSThomas Huth return; 3466fcf5ef2aSThomas Huth } 3467fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3468fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3469fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3470fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3471fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3472fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3473fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3474fcf5ef2aSThomas Huth tcg_temp_free(t0); 3475fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3476fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3477fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3478fcf5ef2aSThomas Huth } 3479fcf5ef2aSThomas Huth 3480fcf5ef2aSThomas Huth /* stswi */ 3481fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3482fcf5ef2aSThomas Huth { 3483fcf5ef2aSThomas Huth TCGv t0; 3484fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3485fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3486fcf5ef2aSThomas Huth 3487fcf5ef2aSThomas Huth if (ctx->le_mode) { 3488fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3489fcf5ef2aSThomas Huth return; 3490fcf5ef2aSThomas Huth } 3491fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3492fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3493fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3494efe843d8SDavid Gibson if (nb == 0) { 3495fcf5ef2aSThomas Huth nb = 32; 3496efe843d8SDavid Gibson } 3497fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3498fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3499fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3500fcf5ef2aSThomas Huth tcg_temp_free(t0); 3501fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3502fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3503fcf5ef2aSThomas Huth } 3504fcf5ef2aSThomas Huth 3505fcf5ef2aSThomas Huth /* stswx */ 3506fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3507fcf5ef2aSThomas Huth { 3508fcf5ef2aSThomas Huth TCGv t0; 3509fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3510fcf5ef2aSThomas Huth 3511fcf5ef2aSThomas Huth if (ctx->le_mode) { 3512fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3513fcf5ef2aSThomas Huth return; 3514fcf5ef2aSThomas Huth } 3515fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3516fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3517fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3518fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3519fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3520fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3521fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3522fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3523fcf5ef2aSThomas Huth tcg_temp_free(t0); 3524fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3525fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3526fcf5ef2aSThomas Huth } 3527fcf5ef2aSThomas Huth 3528fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3529fcf5ef2aSThomas Huth /* eieio */ 3530fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3531fcf5ef2aSThomas Huth { 3532fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3533fcb830afSNicholas Piggin 3534fcb830afSNicholas Piggin /* 3535fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3536fcb830afSNicholas Piggin * operations in the set: 3537fcb830afSNicholas Piggin * - loads from CI memory. 3538fcb830afSNicholas Piggin * - stores to CI memory. 3539fcb830afSNicholas Piggin * - stores to WT memory. 3540fcb830afSNicholas Piggin * 3541fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3542fcb830afSNicholas Piggin * - stores to cacheble memory. 3543fcb830afSNicholas Piggin * 3544fcb830afSNicholas Piggin * It also serializes instructions: 3545fcb830afSNicholas Piggin * - dcbt and dcbst. 3546fcb830afSNicholas Piggin * 3547fcb830afSNicholas Piggin * It separately serializes: 3548fcb830afSNicholas Piggin * - tlbie and tlbsync. 3549fcb830afSNicholas Piggin * 3550fcb830afSNicholas Piggin * And separately serializes: 3551fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3552fcb830afSNicholas Piggin * 3553fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3554fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3555fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3556fcb830afSNicholas Piggin * serialization. 3557fcb830afSNicholas Piggin */ 3558c8fd8373SCédric Le Goater 3559c8fd8373SCédric Le Goater /* 3560c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3561c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3562c8fd8373SCédric Le Goater */ 3563c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3564c8fd8373SCédric Le Goater /* 3565c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3566c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3567c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3568c8fd8373SCédric Le Goater * complain to the user. 3569c8fd8373SCédric Le Goater */ 3570c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3571c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 35722c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3573c8fd8373SCédric Le Goater } else { 3574c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3575c8fd8373SCédric Le Goater } 3576c8fd8373SCédric Le Goater } 3577c8fd8373SCédric Le Goater 3578c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3579fcf5ef2aSThomas Huth } 3580fcf5ef2aSThomas Huth 3581fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3582fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3583fcf5ef2aSThomas Huth { 3584fcf5ef2aSThomas Huth TCGv_i32 t; 3585fcf5ef2aSThomas Huth TCGLabel *l; 3586fcf5ef2aSThomas Huth 3587fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3588fcf5ef2aSThomas Huth return; 3589fcf5ef2aSThomas Huth } 3590fcf5ef2aSThomas Huth l = gen_new_label(); 3591fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3592fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3593fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3594fcf5ef2aSThomas Huth if (global) { 3595fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3596fcf5ef2aSThomas Huth } else { 3597fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3598fcf5ef2aSThomas Huth } 3599fcf5ef2aSThomas Huth gen_set_label(l); 3600fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3601fcf5ef2aSThomas Huth } 3602fcf5ef2aSThomas Huth #else 3603fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3604fcf5ef2aSThomas Huth #endif 3605fcf5ef2aSThomas Huth 3606fcf5ef2aSThomas Huth /* isync */ 3607fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3608fcf5ef2aSThomas Huth { 3609fcf5ef2aSThomas Huth /* 3610fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3611fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3612fcf5ef2aSThomas Huth */ 3613fcf5ef2aSThomas Huth if (!ctx->pr) { 3614fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3615fcf5ef2aSThomas Huth } 36164771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3617d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3618fcf5ef2aSThomas Huth } 3619fcf5ef2aSThomas Huth 3620fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3621fcf5ef2aSThomas Huth 362214776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 36232a4e6c1bSRichard Henderson { 36242a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 36252a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 36262a4e6c1bSRichard Henderson 36272a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 36282a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 36292a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 36302a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 36312a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 36322a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 36332a4e6c1bSRichard Henderson tcg_temp_free(t0); 36342a4e6c1bSRichard Henderson } 36352a4e6c1bSRichard Henderson 3636fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3637fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3638fcf5ef2aSThomas Huth { \ 36392a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3640fcf5ef2aSThomas Huth } 3641fcf5ef2aSThomas Huth 3642fcf5ef2aSThomas Huth /* lwarx */ 3643fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3644fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3645fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3646fcf5ef2aSThomas Huth 364714776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 364820923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 364920923c1dSRichard Henderson { 365020923c1dSRichard Henderson TCGv t = tcg_temp_new(); 365120923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 365220923c1dSRichard Henderson TCGv u = tcg_temp_new(); 365320923c1dSRichard Henderson 365420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 365520923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 365620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 365720923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 365820923c1dSRichard Henderson 365920923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 366020923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 366120923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 366220923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 366320923c1dSRichard Henderson 366420923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 366520923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 366620923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 366720923c1dSRichard Henderson 366820923c1dSRichard Henderson tcg_temp_free(t); 366920923c1dSRichard Henderson tcg_temp_free(t2); 367020923c1dSRichard Henderson tcg_temp_free(u); 367120923c1dSRichard Henderson } 367220923c1dSRichard Henderson 367314776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 367420ba8504SRichard Henderson { 367520ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 367620ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 367720923c1dSRichard Henderson int rt = rD(ctx->opcode); 367820923c1dSRichard Henderson bool need_serial; 367920ba8504SRichard Henderson TCGv src, dst; 368020ba8504SRichard Henderson 368120ba8504SRichard Henderson gen_addr_register(ctx, EA); 368220923c1dSRichard Henderson dst = cpu_gpr[rt]; 368320923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 368420ba8504SRichard Henderson 368520923c1dSRichard Henderson need_serial = false; 368620ba8504SRichard Henderson memop |= MO_ALIGN; 368720ba8504SRichard Henderson switch (gpr_FC) { 368820ba8504SRichard Henderson case 0: /* Fetch and add */ 368920ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 369020ba8504SRichard Henderson break; 369120ba8504SRichard Henderson case 1: /* Fetch and xor */ 369220ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 369320ba8504SRichard Henderson break; 369420ba8504SRichard Henderson case 2: /* Fetch and or */ 369520ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 369620ba8504SRichard Henderson break; 369720ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 369820ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 369920ba8504SRichard Henderson break; 3700b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3701b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3702b8ce0f86SRichard Henderson break; 3703b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3704b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3705b8ce0f86SRichard Henderson break; 3706b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3707b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3708b8ce0f86SRichard Henderson break; 3709b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3710b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3711b8ce0f86SRichard Henderson break; 371220ba8504SRichard Henderson case 8: /* Swap */ 371320ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 371420ba8504SRichard Henderson break; 371520923c1dSRichard Henderson 371620923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 371720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 371820923c1dSRichard Henderson need_serial = true; 371920923c1dSRichard Henderson } else { 372020923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 372120923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 372220923c1dSRichard Henderson 372320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 372420923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 372520923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 372620923c1dSRichard Henderson } else { 372720923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 372820923c1dSRichard Henderson } 372920923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 373020923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 373120923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 373220923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 373320923c1dSRichard Henderson 373420923c1dSRichard Henderson tcg_temp_free(t0); 373520923c1dSRichard Henderson tcg_temp_free(t1); 373620923c1dSRichard Henderson } 373720ba8504SRichard Henderson break; 373820923c1dSRichard Henderson 373920923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 374020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374120923c1dSRichard Henderson need_serial = true; 374220923c1dSRichard Henderson } else { 374320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 374420923c1dSRichard Henderson } 374520923c1dSRichard Henderson break; 374620923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 374720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374820923c1dSRichard Henderson need_serial = true; 374920923c1dSRichard Henderson } else { 375020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 375120923c1dSRichard Henderson } 375220923c1dSRichard Henderson break; 375320923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 375420923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 375520923c1dSRichard Henderson need_serial = true; 375620923c1dSRichard Henderson } else { 375720923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 375820923c1dSRichard Henderson } 375920923c1dSRichard Henderson break; 376020923c1dSRichard Henderson 376120ba8504SRichard Henderson default: 376220ba8504SRichard Henderson /* invoke data storage error handler */ 376320ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 376420ba8504SRichard Henderson } 376520ba8504SRichard Henderson tcg_temp_free(EA); 376620923c1dSRichard Henderson 376720923c1dSRichard Henderson if (need_serial) { 376820923c1dSRichard Henderson /* Restart with exclusive lock. */ 376920923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 377020923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 377120923c1dSRichard Henderson } 3772a68a6146SBalamuruhan S } 3773a68a6146SBalamuruhan S 377420ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 377520ba8504SRichard Henderson { 377620ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 377720ba8504SRichard Henderson } 377820ba8504SRichard Henderson 377920ba8504SRichard Henderson #ifdef TARGET_PPC64 378020ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 378120ba8504SRichard Henderson { 3782fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 378320ba8504SRichard Henderson } 3784a68a6146SBalamuruhan S #endif 3785a68a6146SBalamuruhan S 378614776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 37879deb041cSRichard Henderson { 37889deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 37899deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 37909deb041cSRichard Henderson TCGv src, discard; 37919deb041cSRichard Henderson 37929deb041cSRichard Henderson gen_addr_register(ctx, EA); 37939deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 37949deb041cSRichard Henderson discard = tcg_temp_new(); 37959deb041cSRichard Henderson 37969deb041cSRichard Henderson memop |= MO_ALIGN; 37979deb041cSRichard Henderson switch (gpr_FC) { 37989deb041cSRichard Henderson case 0: /* add and Store */ 37999deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38009deb041cSRichard Henderson break; 38019deb041cSRichard Henderson case 1: /* xor and Store */ 38029deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38039deb041cSRichard Henderson break; 38049deb041cSRichard Henderson case 2: /* Or and Store */ 38059deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38069deb041cSRichard Henderson break; 38079deb041cSRichard Henderson case 3: /* 'and' and Store */ 38089deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38099deb041cSRichard Henderson break; 38109deb041cSRichard Henderson case 4: /* Store max unsigned */ 3811b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3812b8ce0f86SRichard Henderson break; 38139deb041cSRichard Henderson case 5: /* Store max signed */ 3814b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3815b8ce0f86SRichard Henderson break; 38169deb041cSRichard Henderson case 6: /* Store min unsigned */ 3817b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3818b8ce0f86SRichard Henderson break; 38199deb041cSRichard Henderson case 7: /* Store min signed */ 3820b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3821b8ce0f86SRichard Henderson break; 38229deb041cSRichard Henderson case 24: /* Store twin */ 38237fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 38247fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 38257fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 38267fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 38277fbc2b20SRichard Henderson } else { 38287fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 38297fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 38307fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 38317fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 38327fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 38337fbc2b20SRichard Henderson 38347fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 38357fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 38367fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 38377fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 38387fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 38397fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 38407fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 38417fbc2b20SRichard Henderson 38427fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 38437fbc2b20SRichard Henderson tcg_temp_free(s2); 38447fbc2b20SRichard Henderson tcg_temp_free(s); 38457fbc2b20SRichard Henderson tcg_temp_free(t2); 38467fbc2b20SRichard Henderson tcg_temp_free(t); 38477fbc2b20SRichard Henderson } 38489deb041cSRichard Henderson break; 38499deb041cSRichard Henderson default: 38509deb041cSRichard Henderson /* invoke data storage error handler */ 38519deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 38529deb041cSRichard Henderson } 38539deb041cSRichard Henderson tcg_temp_free(discard); 38549deb041cSRichard Henderson tcg_temp_free(EA); 3855a3401188SBalamuruhan S } 3856a3401188SBalamuruhan S 38579deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 38589deb041cSRichard Henderson { 38599deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 38609deb041cSRichard Henderson } 38619deb041cSRichard Henderson 38629deb041cSRichard Henderson #ifdef TARGET_PPC64 38639deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 38649deb041cSRichard Henderson { 3865fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 38669deb041cSRichard Henderson } 3867a3401188SBalamuruhan S #endif 3868a3401188SBalamuruhan S 386914776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3870fcf5ef2aSThomas Huth { 3871253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3872253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3873d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3874d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3875fcf5ef2aSThomas Huth 3876d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3877d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3878d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3879d8b86898SRichard Henderson tcg_temp_free(t0); 3880253ce7b2SNikunj A Dadhania 3881253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3882253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3883253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3884253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3885253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3886253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3887253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3888253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3889253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3890253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3891253ce7b2SNikunj A Dadhania 3892fcf5ef2aSThomas Huth gen_set_label(l1); 38934771df23SNikunj A Dadhania 3894efe843d8SDavid Gibson /* 3895efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3896efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3897efe843d8SDavid Gibson */ 38984771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3899253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3900253ce7b2SNikunj A Dadhania 3901253ce7b2SNikunj A Dadhania gen_set_label(l2); 3902fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3903fcf5ef2aSThomas Huth } 3904fcf5ef2aSThomas Huth 3905fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3906fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3907fcf5ef2aSThomas Huth { \ 3908d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3909fcf5ef2aSThomas Huth } 3910fcf5ef2aSThomas Huth 3911fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3912fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3913fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3914fcf5ef2aSThomas Huth 3915fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3916fcf5ef2aSThomas Huth /* ldarx */ 3917fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3918fcf5ef2aSThomas Huth /* stdcx. */ 3919fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3920fcf5ef2aSThomas Huth 3921fcf5ef2aSThomas Huth /* lqarx */ 3922fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3923fcf5ef2aSThomas Huth { 3924fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 392594bf2658SRichard Henderson TCGv EA, hi, lo; 3926fcf5ef2aSThomas Huth 3927fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3928fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3929fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3930fcf5ef2aSThomas Huth return; 3931fcf5ef2aSThomas Huth } 3932fcf5ef2aSThomas Huth 3933fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 393494bf2658SRichard Henderson EA = tcg_temp_new(); 3935fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 393694bf2658SRichard Henderson 393794bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 393894bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 393994bf2658SRichard Henderson hi = cpu_gpr[rd]; 394094bf2658SRichard Henderson 394194bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3942f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 394394bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 394494bf2658SRichard Henderson if (ctx->le_mode) { 394568e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 394694bf2658SRichard Henderson ctx->mem_idx)); 394794bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3948fcf5ef2aSThomas Huth } else { 394968e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 395094bf2658SRichard Henderson ctx->mem_idx)); 395194bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3952fcf5ef2aSThomas Huth } 395394bf2658SRichard Henderson tcg_temp_free_i32(oi); 395494bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3955f34ec0f6SRichard Henderson } else { 395694bf2658SRichard Henderson /* Restart with exclusive lock. */ 395794bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 395894bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 395994bf2658SRichard Henderson tcg_temp_free(EA); 396094bf2658SRichard Henderson return; 3961f34ec0f6SRichard Henderson } 396294bf2658SRichard Henderson } else if (ctx->le_mode) { 3963fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEUQ | MO_ALIGN_16); 3964fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3965fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3966fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEUQ); 396794bf2658SRichard Henderson } else { 3968fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEUQ | MO_ALIGN_16); 396994bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 397094bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3971fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ); 397294bf2658SRichard Henderson } 3973fcf5ef2aSThomas Huth tcg_temp_free(EA); 397494bf2658SRichard Henderson 397594bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 397694bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3977fcf5ef2aSThomas Huth } 3978fcf5ef2aSThomas Huth 3979fcf5ef2aSThomas Huth /* stqcx. */ 3980fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3981fcf5ef2aSThomas Huth { 39824a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 39834a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3984fcf5ef2aSThomas Huth 39854a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3986fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3987fcf5ef2aSThomas Huth return; 3988fcf5ef2aSThomas Huth } 39894a9b3c5dSRichard Henderson 3990fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 39914a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3992fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3993fcf5ef2aSThomas Huth 39944a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 39954a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 39964a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3997fcf5ef2aSThomas Huth 39984a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3999f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 400068e33d86SRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 40014a9b3c5dSRichard Henderson if (ctx->le_mode) { 4002f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4003f34ec0f6SRichard Henderson EA, lo, hi, oi); 4004fcf5ef2aSThomas Huth } else { 4005f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4006f34ec0f6SRichard Henderson EA, lo, hi, oi); 4007fcf5ef2aSThomas Huth } 4008f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4009f34ec0f6SRichard Henderson } else { 40104a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 40114a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 40124a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4013f34ec0f6SRichard Henderson } 4014fcf5ef2aSThomas Huth tcg_temp_free(EA); 40154a9b3c5dSRichard Henderson } else { 40164a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 40174a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 40184a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 40194a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4020fcf5ef2aSThomas Huth 40214a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 40224a9b3c5dSRichard Henderson tcg_temp_free(EA); 40234a9b3c5dSRichard Henderson 40244a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 40254a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40264a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 40274a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 40284a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40294a9b3c5dSRichard Henderson 40304a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40314a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 40324a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40334a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 40344a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 40354a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40364a9b3c5dSRichard Henderson 40374a9b3c5dSRichard Henderson /* Success */ 40384a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 40394a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40404a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 40414a9b3c5dSRichard Henderson 40424a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40434a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 40444a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 40454a9b3c5dSRichard Henderson 40464a9b3c5dSRichard Henderson gen_set_label(lab_fail); 40474a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40484a9b3c5dSRichard Henderson 40494a9b3c5dSRichard Henderson gen_set_label(lab_over); 40504a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 40514a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 40524a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 40534a9b3c5dSRichard Henderson } 40544a9b3c5dSRichard Henderson } 4055fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4056fcf5ef2aSThomas Huth 4057fcf5ef2aSThomas Huth /* sync */ 4058fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4059fcf5ef2aSThomas Huth { 406003abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 4061fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4062fcf5ef2aSThomas Huth 406303abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 406403abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 406503abfd90SNicholas Piggin } 406603abfd90SNicholas Piggin 4067fcf5ef2aSThomas Huth /* 4068fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4069fcf5ef2aSThomas Huth * 4070fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4071fcf5ef2aSThomas Huth * 4072fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4073fcf5ef2aSThomas Huth * check MSR_PR as well. 4074fcf5ef2aSThomas Huth */ 4075fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4076fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4077fcf5ef2aSThomas Huth } 407803abfd90SNicholas Piggin 407903abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 4080fcf5ef2aSThomas Huth } 4081fcf5ef2aSThomas Huth 4082fcf5ef2aSThomas Huth /* wait */ 4083fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4084fcf5ef2aSThomas Huth { 40850c9717ffSNicholas Piggin uint32_t wc; 40860c9717ffSNicholas Piggin 40870c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 40880c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 40890c9717ffSNicholas Piggin 40900c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 40910c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 40920c9717ffSNicholas Piggin wc = WC(ctx->opcode); 40930c9717ffSNicholas Piggin } else { 40940c9717ffSNicholas Piggin wc = 0; 40950c9717ffSNicholas Piggin } 40960c9717ffSNicholas Piggin 40970c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 40980c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 40990c9717ffSNicholas Piggin wc = WC(ctx->opcode); 41000c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 41010c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 41020c9717ffSNicholas Piggin 41030c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 41040c9717ffSNicholas Piggin if (wc == 3) { 41050c9717ffSNicholas Piggin gen_invalid(ctx); 41060c9717ffSNicholas Piggin return; 41070c9717ffSNicholas Piggin } 41080c9717ffSNicholas Piggin 41090c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 41100c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 41110c9717ffSNicholas Piggin gen_invalid(ctx); 41120c9717ffSNicholas Piggin return; 41130c9717ffSNicholas Piggin } 41140c9717ffSNicholas Piggin 41150c9717ffSNicholas Piggin } else { /* ISA300 */ 41160c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 41170c9717ffSNicholas Piggin if (wc > 0) { 41180c9717ffSNicholas Piggin gen_invalid(ctx); 41190c9717ffSNicholas Piggin return; 41200c9717ffSNicholas Piggin } 41210c9717ffSNicholas Piggin } 41220c9717ffSNicholas Piggin 41230c9717ffSNicholas Piggin } else { 41240c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 41250c9717ffSNicholas Piggin gen_invalid(ctx); 41260c9717ffSNicholas Piggin return; 41270c9717ffSNicholas Piggin } 41280c9717ffSNicholas Piggin 41290c9717ffSNicholas Piggin /* 41300c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 41310c9717ffSNicholas Piggin * to occur. 41320c9717ffSNicholas Piggin */ 41330c9717ffSNicholas Piggin if (wc == 0) { 4134fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4135fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4136fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4137fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4138fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4139b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4140fcf5ef2aSThomas Huth } 4141fcf5ef2aSThomas Huth 41420c9717ffSNicholas Piggin /* 41430c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 41440c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 41450c9717ffSNicholas Piggin * 41460c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 41470c9717ffSNicholas Piggin * no-ops. 41480c9717ffSNicholas Piggin * 41490c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 41500c9717ffSNicholas Piggin * 41510c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 41520c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 41530c9717ffSNicholas Piggin * 41540c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 41550c9717ffSNicholas Piggin * 41560c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 41570c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 41580c9717ffSNicholas Piggin * can be implemented as a no-op. 41590c9717ffSNicholas Piggin * 41600c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 41610c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 41620c9717ffSNicholas Piggin * no-op. 41630c9717ffSNicholas Piggin * 41640c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 41650c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 41660c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 41670c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 41680c9717ffSNicholas Piggin * (if suboptimal). 41690c9717ffSNicholas Piggin */ 41700c9717ffSNicholas Piggin } 41710c9717ffSNicholas Piggin 4172fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4173fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4174fcf5ef2aSThomas Huth { 4175fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41769f0cf041SMatheus Ferst GEN_PRIV(ctx); 4177fcf5ef2aSThomas Huth #else 4178fcf5ef2aSThomas Huth TCGv_i32 t; 4179fcf5ef2aSThomas Huth 41809f0cf041SMatheus Ferst CHK_HV(ctx); 4181fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4182fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4183fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4184154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4185154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4186fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4187fcf5ef2aSThomas Huth } 4188fcf5ef2aSThomas Huth 4189fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4190fcf5ef2aSThomas Huth { 4191fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41929f0cf041SMatheus Ferst GEN_PRIV(ctx); 4193fcf5ef2aSThomas Huth #else 4194fcf5ef2aSThomas Huth TCGv_i32 t; 4195fcf5ef2aSThomas Huth 41969f0cf041SMatheus Ferst CHK_HV(ctx); 4197fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4198fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4199fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4200154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4201154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4202fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4203fcf5ef2aSThomas Huth } 4204fcf5ef2aSThomas Huth 4205cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4206cdee0e72SNikunj A Dadhania { 420721c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 42089f0cf041SMatheus Ferst GEN_PRIV(ctx); 420921c0d66aSBenjamin Herrenschmidt #else 421021c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 421121c0d66aSBenjamin Herrenschmidt 42129f0cf041SMatheus Ferst CHK_HV(ctx); 421321c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 421421c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 421521c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 421621c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 421721c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 421821c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4219cdee0e72SNikunj A Dadhania } 4220cdee0e72SNikunj A Dadhania 4221fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4222fcf5ef2aSThomas Huth { 4223fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42249f0cf041SMatheus Ferst GEN_PRIV(ctx); 4225fcf5ef2aSThomas Huth #else 4226fcf5ef2aSThomas Huth TCGv_i32 t; 4227fcf5ef2aSThomas Huth 42289f0cf041SMatheus Ferst CHK_HV(ctx); 4229fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4230fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4231fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4232154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4233154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4234fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4235fcf5ef2aSThomas Huth } 4236fcf5ef2aSThomas Huth 4237fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4238fcf5ef2aSThomas Huth { 4239fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42409f0cf041SMatheus Ferst GEN_PRIV(ctx); 4241fcf5ef2aSThomas Huth #else 4242fcf5ef2aSThomas Huth TCGv_i32 t; 4243fcf5ef2aSThomas Huth 42449f0cf041SMatheus Ferst CHK_HV(ctx); 4245fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4246fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4247fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4248154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4249154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4250fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4251fcf5ef2aSThomas Huth } 4252fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4253fcf5ef2aSThomas Huth 4254fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4255fcf5ef2aSThomas Huth { 4256fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4257efe843d8SDavid Gibson if (ctx->has_cfar) { 4258fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4259efe843d8SDavid Gibson } 4260fcf5ef2aSThomas Huth #endif 4261fcf5ef2aSThomas Huth } 4262fcf5ef2aSThomas Huth 426346d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 426446d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 426546d396bdSDaniel Henrique Barboza { 426646d396bdSDaniel Henrique Barboza /* 426746d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 426846d396bdSDaniel Henrique Barboza * instructions. 426946d396bdSDaniel Henrique Barboza */ 427046d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 427146d396bdSDaniel Henrique Barboza return; 427246d396bdSDaniel Henrique Barboza } 427346d396bdSDaniel Henrique Barboza 427446d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4275*eeaaefe9SLeandro Lupori TCGLabel *l; 4276*eeaaefe9SLeandro Lupori TCGv t0; 4277*eeaaefe9SLeandro Lupori 427846d396bdSDaniel Henrique Barboza /* 427946d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 428046d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 428146d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 428246d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 428346d396bdSDaniel Henrique Barboza */ 428446d396bdSDaniel Henrique Barboza gen_icount_io_start(ctx); 428546d396bdSDaniel Henrique Barboza 4286*eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4287*eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4288*eeaaefe9SLeandro Lupori l = gen_new_label(); 4289*eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4290*eeaaefe9SLeandro Lupori 4291*eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4292*eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4293*eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4294*eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4295*eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4296*eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4297*eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4298*eeaaefe9SLeandro Lupori } 4299*eeaaefe9SLeandro Lupori 4300*eeaaefe9SLeandro Lupori gen_set_label(l); 4301*eeaaefe9SLeandro Lupori tcg_temp_free(t0); 4302*eeaaefe9SLeandro Lupori } else { 430346d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4304*eeaaefe9SLeandro Lupori } 430546d396bdSDaniel Henrique Barboza #else 430646d396bdSDaniel Henrique Barboza /* 430746d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 430846d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 430946d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 431046d396bdSDaniel Henrique Barboza */ 431146d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 431246d396bdSDaniel Henrique Barboza 431346d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 431446d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 431546d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 431646d396bdSDaniel Henrique Barboza 431746d396bdSDaniel Henrique Barboza tcg_temp_free(t0); 431846d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 431946d396bdSDaniel Henrique Barboza } 432046d396bdSDaniel Henrique Barboza #else 432146d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 432246d396bdSDaniel Henrique Barboza { 432346d396bdSDaniel Henrique Barboza return; 432446d396bdSDaniel Henrique Barboza } 432546d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 432646d396bdSDaniel Henrique Barboza 4327fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4328fcf5ef2aSThomas Huth { 43296e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4330fcf5ef2aSThomas Huth } 4331fcf5ef2aSThomas Huth 43320e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 43330e3bf489SRoman Kapl { 43349498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 43350e3bf489SRoman Kapl gen_debug_exception(ctx); 43360e3bf489SRoman Kapl } else { 433746d396bdSDaniel Henrique Barboza /* 433846d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 433946d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 434046d396bdSDaniel Henrique Barboza */ 434146d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 434246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 434346d396bdSDaniel Henrique Barboza } 434446d396bdSDaniel Henrique Barboza 43450e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 43460e3bf489SRoman Kapl } 43470e3bf489SRoman Kapl } 43480e3bf489SRoman Kapl 4349fcf5ef2aSThomas Huth /*** Branch ***/ 4350c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4351fcf5ef2aSThomas Huth { 4352fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4353fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4354fcf5ef2aSThomas Huth } 4355fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 435646d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4357fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4358fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 435907ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4360fcf5ef2aSThomas Huth } else { 4361fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 43620e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4363fcf5ef2aSThomas Huth } 4364fcf5ef2aSThomas Huth } 4365fcf5ef2aSThomas Huth 4366fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4367fcf5ef2aSThomas Huth { 4368fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4369fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4370fcf5ef2aSThomas Huth } 4371fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4372fcf5ef2aSThomas Huth } 4373fcf5ef2aSThomas Huth 4374fcf5ef2aSThomas Huth /* b ba bl bla */ 4375fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4376fcf5ef2aSThomas Huth { 4377fcf5ef2aSThomas Huth target_ulong li, target; 4378fcf5ef2aSThomas Huth 4379fcf5ef2aSThomas Huth /* sign extend LI */ 4380fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4381fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4382fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43832c2bcb1bSRichard Henderson target = ctx->cia + li; 4384fcf5ef2aSThomas Huth } else { 4385fcf5ef2aSThomas Huth target = li; 4386fcf5ef2aSThomas Huth } 4387fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4388b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4389fcf5ef2aSThomas Huth } 43902c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4391fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 43926086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4393fcf5ef2aSThomas Huth } 4394fcf5ef2aSThomas Huth 4395fcf5ef2aSThomas Huth #define BCOND_IM 0 4396fcf5ef2aSThomas Huth #define BCOND_LR 1 4397fcf5ef2aSThomas Huth #define BCOND_CTR 2 4398fcf5ef2aSThomas Huth #define BCOND_TAR 3 4399fcf5ef2aSThomas Huth 4400c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4401fcf5ef2aSThomas Huth { 4402fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4403fcf5ef2aSThomas Huth TCGLabel *l1; 4404fcf5ef2aSThomas Huth TCGv target; 44050e3bf489SRoman Kapl 4406fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4407fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4408efe843d8SDavid Gibson if (type == BCOND_CTR) { 4409fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4410efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4411fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4412efe843d8SDavid Gibson } else { 4413fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4414efe843d8SDavid Gibson } 4415fcf5ef2aSThomas Huth } else { 4416f764718dSRichard Henderson target = NULL; 4417fcf5ef2aSThomas Huth } 4418efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4419b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4420efe843d8SDavid Gibson } 4421fcf5ef2aSThomas Huth l1 = gen_new_label(); 4422fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4423fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4424fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4425fa200c95SGreg Kurz 4426fa200c95SGreg Kurz if (type == BCOND_CTR) { 4427fa200c95SGreg Kurz /* 4428fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4429fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4430fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 443115d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 443215d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 443315d68c5eSGreg Kurz * it basically useless and thus never used in real code. 443415d68c5eSGreg Kurz * 443515d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 443615d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 443715d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 443815d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 443915d68c5eSGreg Kurz * doing anything else harmful. 4440fa200c95SGreg Kurz */ 4441d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4442fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 44439acc95cdSGreg Kurz tcg_temp_free(temp); 44449acc95cdSGreg Kurz tcg_temp_free(target); 4445fcf5ef2aSThomas Huth return; 4446fcf5ef2aSThomas Huth } 4447fa200c95SGreg Kurz 4448fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4449fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4450fa200c95SGreg Kurz } else { 4451fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4452fa200c95SGreg Kurz } 4453fa200c95SGreg Kurz if (bo & 0x2) { 4454fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4455fa200c95SGreg Kurz } else { 4456fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4457fa200c95SGreg Kurz } 4458fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4459fa200c95SGreg Kurz } else { 4460fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4461fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4462fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4463fcf5ef2aSThomas Huth } else { 4464fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4465fcf5ef2aSThomas Huth } 4466fcf5ef2aSThomas Huth if (bo & 0x2) { 4467fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4468fcf5ef2aSThomas Huth } else { 4469fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4470fcf5ef2aSThomas Huth } 4471fa200c95SGreg Kurz } 4472fcf5ef2aSThomas Huth tcg_temp_free(temp); 4473fcf5ef2aSThomas Huth } 4474fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4475fcf5ef2aSThomas Huth /* Test CR */ 4476fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4477fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4478fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4479fcf5ef2aSThomas Huth 4480fcf5ef2aSThomas Huth if (bo & 0x8) { 4481fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4482fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4483fcf5ef2aSThomas Huth } else { 4484fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4485fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4486fcf5ef2aSThomas Huth } 4487fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4488fcf5ef2aSThomas Huth } 44892c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4490fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4491fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4492fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 44932c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4494fcf5ef2aSThomas Huth } else { 4495fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4496fcf5ef2aSThomas Huth } 4497fcf5ef2aSThomas Huth } else { 4498fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4499fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4500fcf5ef2aSThomas Huth } else { 4501fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4502fcf5ef2aSThomas Huth } 45030e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4504c4a2e3a9SRichard Henderson tcg_temp_free(target); 4505c4a2e3a9SRichard Henderson } 4506fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 45070e3bf489SRoman Kapl /* fallthrough case */ 4508fcf5ef2aSThomas Huth gen_set_label(l1); 4509b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4510fcf5ef2aSThomas Huth } 45116086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4512fcf5ef2aSThomas Huth } 4513fcf5ef2aSThomas Huth 4514fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4515fcf5ef2aSThomas Huth { 4516fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4517fcf5ef2aSThomas Huth } 4518fcf5ef2aSThomas Huth 4519fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4520fcf5ef2aSThomas Huth { 4521fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4522fcf5ef2aSThomas Huth } 4523fcf5ef2aSThomas Huth 4524fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4525fcf5ef2aSThomas Huth { 4526fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4527fcf5ef2aSThomas Huth } 4528fcf5ef2aSThomas Huth 4529fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4530fcf5ef2aSThomas Huth { 4531fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4532fcf5ef2aSThomas Huth } 4533fcf5ef2aSThomas Huth 4534fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4535fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4536fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4537fcf5ef2aSThomas Huth { \ 4538fcf5ef2aSThomas Huth uint8_t bitmask; \ 4539fcf5ef2aSThomas Huth int sh; \ 4540fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4541fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4542fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4543fcf5ef2aSThomas Huth if (sh > 0) \ 4544fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4545fcf5ef2aSThomas Huth else if (sh < 0) \ 4546fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4547fcf5ef2aSThomas Huth else \ 4548fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4549fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4550fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4551fcf5ef2aSThomas Huth if (sh > 0) \ 4552fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4553fcf5ef2aSThomas Huth else if (sh < 0) \ 4554fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4555fcf5ef2aSThomas Huth else \ 4556fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4557fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4558fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4559fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4560fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4561fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4562fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4563fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4564fcf5ef2aSThomas Huth } 4565fcf5ef2aSThomas Huth 4566fcf5ef2aSThomas Huth /* crand */ 4567fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4568fcf5ef2aSThomas Huth /* crandc */ 4569fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4570fcf5ef2aSThomas Huth /* creqv */ 4571fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4572fcf5ef2aSThomas Huth /* crnand */ 4573fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4574fcf5ef2aSThomas Huth /* crnor */ 4575fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4576fcf5ef2aSThomas Huth /* cror */ 4577fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4578fcf5ef2aSThomas Huth /* crorc */ 4579fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4580fcf5ef2aSThomas Huth /* crxor */ 4581fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4582fcf5ef2aSThomas Huth 4583fcf5ef2aSThomas Huth /* mcrf */ 4584fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4585fcf5ef2aSThomas Huth { 4586fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4587fcf5ef2aSThomas Huth } 4588fcf5ef2aSThomas Huth 4589fcf5ef2aSThomas Huth /*** System linkage ***/ 4590fcf5ef2aSThomas Huth 4591fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4592fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4593fcf5ef2aSThomas Huth { 4594fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 45959f0cf041SMatheus Ferst GEN_PRIV(ctx); 4596fcf5ef2aSThomas Huth #else 4597efe843d8SDavid Gibson /* 4598efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4599fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4600fcf5ef2aSThomas Huth */ 4601d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4602fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4603fcf5ef2aSThomas Huth return; 4604fcf5ef2aSThomas Huth } 4605fcf5ef2aSThomas Huth /* Restore CPU state */ 46069f0cf041SMatheus Ferst CHK_SV(ctx); 4607f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46082c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4609fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 461059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4611fcf5ef2aSThomas Huth #endif 4612fcf5ef2aSThomas Huth } 4613fcf5ef2aSThomas Huth 4614fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4615fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4616fcf5ef2aSThomas Huth { 4617fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 46189f0cf041SMatheus Ferst GEN_PRIV(ctx); 4619fcf5ef2aSThomas Huth #else 4620fcf5ef2aSThomas Huth /* Restore CPU state */ 46219f0cf041SMatheus Ferst CHK_SV(ctx); 4622f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46232c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4624fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 462559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4626fcf5ef2aSThomas Huth #endif 4627fcf5ef2aSThomas Huth } 4628fcf5ef2aSThomas Huth 46293c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46303c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 46313c89b8d6SNicholas Piggin { 46323c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 46339f0cf041SMatheus Ferst GEN_PRIV(ctx); 46343c89b8d6SNicholas Piggin #else 46353c89b8d6SNicholas Piggin /* Restore CPU state */ 46369f0cf041SMatheus Ferst CHK_SV(ctx); 4637f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46382c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 46393c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 464059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 46413c89b8d6SNicholas Piggin #endif 46423c89b8d6SNicholas Piggin } 46433c89b8d6SNicholas Piggin #endif 46443c89b8d6SNicholas Piggin 4645fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4646fcf5ef2aSThomas Huth { 4647fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 46489f0cf041SMatheus Ferst GEN_PRIV(ctx); 4649fcf5ef2aSThomas Huth #else 4650fcf5ef2aSThomas Huth /* Restore CPU state */ 46519f0cf041SMatheus Ferst CHK_HV(ctx); 4652fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 465359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4654fcf5ef2aSThomas Huth #endif 4655fcf5ef2aSThomas Huth } 4656fcf5ef2aSThomas Huth #endif 4657fcf5ef2aSThomas Huth 4658fcf5ef2aSThomas Huth /* sc */ 4659fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4660fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4661fcf5ef2aSThomas Huth #else 4662fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 46633c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4664fcf5ef2aSThomas Huth #endif 4665fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4666fcf5ef2aSThomas Huth { 4667fcf5ef2aSThomas Huth uint32_t lev; 4668fcf5ef2aSThomas Huth 4669fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4670fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4671fcf5ef2aSThomas Huth } 4672fcf5ef2aSThomas Huth 46733c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 46743c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46753c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 46763c89b8d6SNicholas Piggin { 4677f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 46783c89b8d6SNicholas Piggin 4679f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 46802c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4681f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 46823c89b8d6SNicholas Piggin 46837a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 46843c89b8d6SNicholas Piggin } 46853c89b8d6SNicholas Piggin #endif 46863c89b8d6SNicholas Piggin #endif 46873c89b8d6SNicholas Piggin 4688fcf5ef2aSThomas Huth /*** Trap ***/ 4689fcf5ef2aSThomas Huth 4690fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4691fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4692fcf5ef2aSThomas Huth { 4693fcf5ef2aSThomas Huth /* Trap never */ 4694fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4695fcf5ef2aSThomas Huth return true; 4696fcf5ef2aSThomas Huth } 4697fcf5ef2aSThomas Huth /* Trap always */ 4698fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4699fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4700fcf5ef2aSThomas Huth return true; 4701fcf5ef2aSThomas Huth } 4702fcf5ef2aSThomas Huth return false; 4703fcf5ef2aSThomas Huth } 4704fcf5ef2aSThomas Huth 4705fcf5ef2aSThomas Huth /* tw */ 4706fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4707fcf5ef2aSThomas Huth { 4708fcf5ef2aSThomas Huth TCGv_i32 t0; 4709fcf5ef2aSThomas Huth 4710fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4711fcf5ef2aSThomas Huth return; 4712fcf5ef2aSThomas Huth } 4713fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4714fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4715fcf5ef2aSThomas Huth t0); 4716fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4717fcf5ef2aSThomas Huth } 4718fcf5ef2aSThomas Huth 4719fcf5ef2aSThomas Huth /* twi */ 4720fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4721fcf5ef2aSThomas Huth { 4722fcf5ef2aSThomas Huth TCGv t0; 4723fcf5ef2aSThomas Huth TCGv_i32 t1; 4724fcf5ef2aSThomas Huth 4725fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4726fcf5ef2aSThomas Huth return; 4727fcf5ef2aSThomas Huth } 4728fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4729fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4730fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4731fcf5ef2aSThomas Huth tcg_temp_free(t0); 4732fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4733fcf5ef2aSThomas Huth } 4734fcf5ef2aSThomas Huth 4735fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4736fcf5ef2aSThomas Huth /* td */ 4737fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4738fcf5ef2aSThomas Huth { 4739fcf5ef2aSThomas Huth TCGv_i32 t0; 4740fcf5ef2aSThomas Huth 4741fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4742fcf5ef2aSThomas Huth return; 4743fcf5ef2aSThomas Huth } 4744fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4745fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4746fcf5ef2aSThomas Huth t0); 4747fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4748fcf5ef2aSThomas Huth } 4749fcf5ef2aSThomas Huth 4750fcf5ef2aSThomas Huth /* tdi */ 4751fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4752fcf5ef2aSThomas Huth { 4753fcf5ef2aSThomas Huth TCGv t0; 4754fcf5ef2aSThomas Huth TCGv_i32 t1; 4755fcf5ef2aSThomas Huth 4756fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4757fcf5ef2aSThomas Huth return; 4758fcf5ef2aSThomas Huth } 4759fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4760fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4761fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4762fcf5ef2aSThomas Huth tcg_temp_free(t0); 4763fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4764fcf5ef2aSThomas Huth } 4765fcf5ef2aSThomas Huth #endif 4766fcf5ef2aSThomas Huth 4767fcf5ef2aSThomas Huth /*** Processor control ***/ 4768fcf5ef2aSThomas Huth 4769fcf5ef2aSThomas Huth /* mcrxr */ 4770fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4771fcf5ef2aSThomas Huth { 4772fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4773fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4774fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4775fcf5ef2aSThomas Huth 4776fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4777fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4778fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4779fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4780fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4781fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4782fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4783fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4784fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4785fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4786fcf5ef2aSThomas Huth 4787fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4788fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4789fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4790fcf5ef2aSThomas Huth } 4791fcf5ef2aSThomas Huth 4792b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4793b63d0434SNikunj A Dadhania /* mcrxrx */ 4794b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4795b63d0434SNikunj A Dadhania { 4796b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4797b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4798b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4799b63d0434SNikunj A Dadhania 4800b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4801b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4802b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4803b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4804b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4805b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4806b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4807b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4808b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4809b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4810b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4811b63d0434SNikunj A Dadhania } 4812b63d0434SNikunj A Dadhania #endif 4813b63d0434SNikunj A Dadhania 4814fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4815fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4816fcf5ef2aSThomas Huth { 4817fcf5ef2aSThomas Huth uint32_t crm, crn; 4818fcf5ef2aSThomas Huth 4819fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4820fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4821fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4822fcf5ef2aSThomas Huth crn = ctz32(crm); 4823fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4824fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4825fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4826fcf5ef2aSThomas Huth } 4827fcf5ef2aSThomas Huth } else { 4828fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4829fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4830fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4831fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4832fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4833fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4834fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4835fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4836fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4837fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4838fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4839fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4840fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4841fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4842fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4843fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4844fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4845fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4846fcf5ef2aSThomas Huth } 4847fcf5ef2aSThomas Huth } 4848fcf5ef2aSThomas Huth 4849fcf5ef2aSThomas Huth /* mfmsr */ 4850fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4851fcf5ef2aSThomas Huth { 48529f0cf041SMatheus Ferst CHK_SV(ctx); 4853fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4854fcf5ef2aSThomas Huth } 4855fcf5ef2aSThomas Huth 4856fcf5ef2aSThomas Huth /* mfspr */ 4857fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4858fcf5ef2aSThomas Huth { 4859fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4860fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4861fcf5ef2aSThomas Huth 4862fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4863fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4864fcf5ef2aSThomas Huth #else 4865fcf5ef2aSThomas Huth if (ctx->pr) { 4866fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4867fcf5ef2aSThomas Huth } else if (ctx->hv) { 4868fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4869fcf5ef2aSThomas Huth } else { 4870fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4871fcf5ef2aSThomas Huth } 4872fcf5ef2aSThomas Huth #endif 4873fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4874fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4875fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4876fcf5ef2aSThomas Huth } else { 4877fcf5ef2aSThomas Huth /* Privilege exception */ 4878efe843d8SDavid Gibson /* 4879efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4880fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4881fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4882fcf5ef2aSThomas Huth */ 4883fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 488431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 488531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48862c2bcb1bSRichard Henderson ctx->cia); 4887fcf5ef2aSThomas Huth } 4888fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4889fcf5ef2aSThomas Huth } 4890fcf5ef2aSThomas Huth } else { 4891fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4892fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4893fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4894fcf5ef2aSThomas Huth /* This is a nop */ 4895fcf5ef2aSThomas Huth return; 4896fcf5ef2aSThomas Huth } 4897fcf5ef2aSThomas Huth /* Not defined */ 489831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 489931085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 49002c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4901fcf5ef2aSThomas Huth 4902efe843d8SDavid Gibson /* 4903efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4904efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4905fcf5ef2aSThomas Huth */ 4906fcf5ef2aSThomas Huth if (sprn & 0x10) { 4907fcf5ef2aSThomas Huth if (ctx->pr) { 49081315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4909fcf5ef2aSThomas Huth } 4910fcf5ef2aSThomas Huth } else { 4911fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 49121315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4913fcf5ef2aSThomas Huth } 4914fcf5ef2aSThomas Huth } 4915fcf5ef2aSThomas Huth } 4916fcf5ef2aSThomas Huth } 4917fcf5ef2aSThomas Huth 4918fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4919fcf5ef2aSThomas Huth { 4920fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4921fcf5ef2aSThomas Huth } 4922fcf5ef2aSThomas Huth 4923fcf5ef2aSThomas Huth /* mftb */ 4924fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4925fcf5ef2aSThomas Huth { 4926fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4927fcf5ef2aSThomas Huth } 4928fcf5ef2aSThomas Huth 4929fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4930fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4931fcf5ef2aSThomas Huth { 4932fcf5ef2aSThomas Huth uint32_t crm, crn; 4933fcf5ef2aSThomas Huth 4934fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4935fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4936fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4937fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4938fcf5ef2aSThomas Huth crn = ctz32(crm); 4939fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4940fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4941fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4942fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4943fcf5ef2aSThomas Huth } 4944fcf5ef2aSThomas Huth } else { 4945fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4946fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4947fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4948fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4949fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4950fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4951fcf5ef2aSThomas Huth } 4952fcf5ef2aSThomas Huth } 4953fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4954fcf5ef2aSThomas Huth } 4955fcf5ef2aSThomas Huth } 4956fcf5ef2aSThomas Huth 4957fcf5ef2aSThomas Huth /* mtmsr */ 4958fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4959fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4960fcf5ef2aSThomas Huth { 4961caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4962caf590ddSNicholas Piggin gen_invalid(ctx); 4963caf590ddSNicholas Piggin return; 4964caf590ddSNicholas Piggin } 4965caf590ddSNicholas Piggin 49669f0cf041SMatheus Ferst CHK_SV(ctx); 4967fcf5ef2aSThomas Huth 4968fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49696fa5726bSMatheus Ferst TCGv t0, t1; 49706fa5726bSMatheus Ferst target_ulong mask; 49716fa5726bSMatheus Ferst 49726fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49736fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49746fa5726bSMatheus Ferst 4975f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49766fa5726bSMatheus Ferst 4977fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49785ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49796fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4980fcf5ef2aSThomas Huth } else { 49816fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 49826fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 49836fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4984efe843d8SDavid Gibson /* 4985efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4986efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4987efe843d8SDavid Gibson * ppc_store_msr 4988fcf5ef2aSThomas Huth */ 4989b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4990fcf5ef2aSThomas Huth } 49916fa5726bSMatheus Ferst 49926fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 49936fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 49946fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 49956fa5726bSMatheus Ferst 49966fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 49976fa5726bSMatheus Ferst 49985ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4999d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 50006fa5726bSMatheus Ferst 50016fa5726bSMatheus Ferst tcg_temp_free(t0); 50026fa5726bSMatheus Ferst tcg_temp_free(t1); 5003fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5004fcf5ef2aSThomas Huth } 5005fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5006fcf5ef2aSThomas Huth 5007fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5008fcf5ef2aSThomas Huth { 50099f0cf041SMatheus Ferst CHK_SV(ctx); 5010fcf5ef2aSThomas Huth 5011fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 50126fa5726bSMatheus Ferst TCGv t0, t1; 50136fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 50146fa5726bSMatheus Ferst 50156fa5726bSMatheus Ferst t0 = tcg_temp_new(); 50166fa5726bSMatheus Ferst t1 = tcg_temp_new(); 50176fa5726bSMatheus Ferst 5018f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5019fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 50205ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 50216fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 5022fcf5ef2aSThomas Huth } else { 50236fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 50246fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 5025fcf5ef2aSThomas Huth 5026efe843d8SDavid Gibson /* 5027efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5028efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5029efe843d8SDavid Gibson * ppc_store_msr 5030fcf5ef2aSThomas Huth */ 5031b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5032fcf5ef2aSThomas Huth } 50336fa5726bSMatheus Ferst 50346fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 50356fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 50366fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 50376fa5726bSMatheus Ferst 50386fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 50396fa5726bSMatheus Ferst 50405ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5041d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 50426fa5726bSMatheus Ferst 50436fa5726bSMatheus Ferst tcg_temp_free(t0); 50446fa5726bSMatheus Ferst tcg_temp_free(t1); 5045fcf5ef2aSThomas Huth #endif 5046fcf5ef2aSThomas Huth } 5047fcf5ef2aSThomas Huth 5048fcf5ef2aSThomas Huth /* mtspr */ 5049fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5050fcf5ef2aSThomas Huth { 5051fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5052fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5053fcf5ef2aSThomas Huth 5054fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5055fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5056fcf5ef2aSThomas Huth #else 5057fcf5ef2aSThomas Huth if (ctx->pr) { 5058fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5059fcf5ef2aSThomas Huth } else if (ctx->hv) { 5060fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5061fcf5ef2aSThomas Huth } else { 5062fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5063fcf5ef2aSThomas Huth } 5064fcf5ef2aSThomas Huth #endif 5065fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5066fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5067fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5068fcf5ef2aSThomas Huth } else { 5069fcf5ef2aSThomas Huth /* Privilege exception */ 507031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 507131085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 50722c2bcb1bSRichard Henderson ctx->cia); 5073fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5074fcf5ef2aSThomas Huth } 5075fcf5ef2aSThomas Huth } else { 5076fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5077fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5078fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5079fcf5ef2aSThomas Huth /* This is a nop */ 5080fcf5ef2aSThomas Huth return; 5081fcf5ef2aSThomas Huth } 5082fcf5ef2aSThomas Huth 5083fcf5ef2aSThomas Huth /* Not defined */ 508431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 508531085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 50862c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5087fcf5ef2aSThomas Huth 5088fcf5ef2aSThomas Huth 5089efe843d8SDavid Gibson /* 5090efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5091efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5092fcf5ef2aSThomas Huth */ 5093fcf5ef2aSThomas Huth if (sprn & 0x10) { 5094fcf5ef2aSThomas Huth if (ctx->pr) { 50951315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5096fcf5ef2aSThomas Huth } 5097fcf5ef2aSThomas Huth } else { 5098fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 50991315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5100fcf5ef2aSThomas Huth } 5101fcf5ef2aSThomas Huth } 5102fcf5ef2aSThomas Huth } 5103fcf5ef2aSThomas Huth } 5104fcf5ef2aSThomas Huth 5105fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5106fcf5ef2aSThomas Huth /* setb */ 5107fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5108fcf5ef2aSThomas Huth { 5109fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 51106f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 51116f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5112fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5113fcf5ef2aSThomas Huth 5114fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5115fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5116fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5117fcf5ef2aSThomas Huth 5118fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5119fcf5ef2aSThomas Huth } 5120fcf5ef2aSThomas Huth #endif 5121fcf5ef2aSThomas Huth 5122fcf5ef2aSThomas Huth /*** Cache management ***/ 5123fcf5ef2aSThomas Huth 5124fcf5ef2aSThomas Huth /* dcbf */ 5125fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5126fcf5ef2aSThomas Huth { 5127fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5128fcf5ef2aSThomas Huth TCGv t0; 5129fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5130fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5131fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5132fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5133fcf5ef2aSThomas Huth tcg_temp_free(t0); 5134fcf5ef2aSThomas Huth } 5135fcf5ef2aSThomas Huth 513650728199SRoman Kapl /* dcbfep (external PID dcbf) */ 513750728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 513850728199SRoman Kapl { 513950728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 514050728199SRoman Kapl TCGv t0; 51419f0cf041SMatheus Ferst CHK_SV(ctx); 514250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 514350728199SRoman Kapl t0 = tcg_temp_new(); 514450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 514550728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 514650728199SRoman Kapl tcg_temp_free(t0); 514750728199SRoman Kapl } 514850728199SRoman Kapl 5149fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5150fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5151fcf5ef2aSThomas Huth { 5152fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51539f0cf041SMatheus Ferst GEN_PRIV(ctx); 5154fcf5ef2aSThomas Huth #else 5155fcf5ef2aSThomas Huth TCGv EA, val; 5156fcf5ef2aSThomas Huth 51579f0cf041SMatheus Ferst CHK_SV(ctx); 5158fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5159fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5160fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5161fcf5ef2aSThomas Huth val = tcg_temp_new(); 5162fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5163fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5164fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5165fcf5ef2aSThomas Huth tcg_temp_free(val); 5166fcf5ef2aSThomas Huth tcg_temp_free(EA); 5167fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5168fcf5ef2aSThomas Huth } 5169fcf5ef2aSThomas Huth 5170fcf5ef2aSThomas Huth /* dcdst */ 5171fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5172fcf5ef2aSThomas Huth { 5173fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5174fcf5ef2aSThomas Huth TCGv t0; 5175fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5176fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5177fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5178fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5179fcf5ef2aSThomas Huth tcg_temp_free(t0); 5180fcf5ef2aSThomas Huth } 5181fcf5ef2aSThomas Huth 518250728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 518350728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 518450728199SRoman Kapl { 518550728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 518650728199SRoman Kapl TCGv t0; 518750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 518850728199SRoman Kapl t0 = tcg_temp_new(); 518950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 519050728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 519150728199SRoman Kapl tcg_temp_free(t0); 519250728199SRoman Kapl } 519350728199SRoman Kapl 5194fcf5ef2aSThomas Huth /* dcbt */ 5195fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5196fcf5ef2aSThomas Huth { 5197efe843d8SDavid Gibson /* 5198efe843d8SDavid Gibson * interpreted as no-op 5199efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5200efe843d8SDavid Gibson * does not generate any exception 5201fcf5ef2aSThomas Huth */ 5202fcf5ef2aSThomas Huth } 5203fcf5ef2aSThomas Huth 520450728199SRoman Kapl /* dcbtep */ 520550728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 520650728199SRoman Kapl { 5207efe843d8SDavid Gibson /* 5208efe843d8SDavid Gibson * interpreted as no-op 5209efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5210efe843d8SDavid Gibson * does not generate any exception 521150728199SRoman Kapl */ 521250728199SRoman Kapl } 521350728199SRoman Kapl 5214fcf5ef2aSThomas Huth /* dcbtst */ 5215fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5216fcf5ef2aSThomas Huth { 5217efe843d8SDavid Gibson /* 5218efe843d8SDavid Gibson * interpreted as no-op 5219efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5220efe843d8SDavid Gibson * does not generate any exception 5221fcf5ef2aSThomas Huth */ 5222fcf5ef2aSThomas Huth } 5223fcf5ef2aSThomas Huth 522450728199SRoman Kapl /* dcbtstep */ 522550728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 522650728199SRoman Kapl { 5227efe843d8SDavid Gibson /* 5228efe843d8SDavid Gibson * interpreted as no-op 5229efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5230efe843d8SDavid Gibson * does not generate any exception 523150728199SRoman Kapl */ 523250728199SRoman Kapl } 523350728199SRoman Kapl 5234fcf5ef2aSThomas Huth /* dcbtls */ 5235fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5236fcf5ef2aSThomas Huth { 5237fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5238fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5239fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5240fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5241fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5242fcf5ef2aSThomas Huth tcg_temp_free(t0); 5243fcf5ef2aSThomas Huth } 5244fcf5ef2aSThomas Huth 5245fcf5ef2aSThomas Huth /* dcbz */ 5246fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5247fcf5ef2aSThomas Huth { 5248fcf5ef2aSThomas Huth TCGv tcgv_addr; 5249fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5250fcf5ef2aSThomas Huth 5251fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5252fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5253fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5254fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5255fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5256fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5257fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5258fcf5ef2aSThomas Huth } 5259fcf5ef2aSThomas Huth 526050728199SRoman Kapl /* dcbzep */ 526150728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 526250728199SRoman Kapl { 526350728199SRoman Kapl TCGv tcgv_addr; 526450728199SRoman Kapl TCGv_i32 tcgv_op; 526550728199SRoman Kapl 526650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 526750728199SRoman Kapl tcgv_addr = tcg_temp_new(); 526850728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 526950728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 527050728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 527150728199SRoman Kapl tcg_temp_free(tcgv_addr); 527250728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 527350728199SRoman Kapl } 527450728199SRoman Kapl 5275fcf5ef2aSThomas Huth /* dst / dstt */ 5276fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5277fcf5ef2aSThomas Huth { 5278fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5279fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5280fcf5ef2aSThomas Huth } else { 5281fcf5ef2aSThomas Huth /* interpreted as no-op */ 5282fcf5ef2aSThomas Huth } 5283fcf5ef2aSThomas Huth } 5284fcf5ef2aSThomas Huth 5285fcf5ef2aSThomas Huth /* dstst /dststt */ 5286fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5287fcf5ef2aSThomas Huth { 5288fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5289fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5290fcf5ef2aSThomas Huth } else { 5291fcf5ef2aSThomas Huth /* interpreted as no-op */ 5292fcf5ef2aSThomas Huth } 5293fcf5ef2aSThomas Huth 5294fcf5ef2aSThomas Huth } 5295fcf5ef2aSThomas Huth 5296fcf5ef2aSThomas Huth /* dss / dssall */ 5297fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5298fcf5ef2aSThomas Huth { 5299fcf5ef2aSThomas Huth /* interpreted as no-op */ 5300fcf5ef2aSThomas Huth } 5301fcf5ef2aSThomas Huth 5302fcf5ef2aSThomas Huth /* icbi */ 5303fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5304fcf5ef2aSThomas Huth { 5305fcf5ef2aSThomas Huth TCGv t0; 5306fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5307fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5308fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5309fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5310fcf5ef2aSThomas Huth tcg_temp_free(t0); 5311fcf5ef2aSThomas Huth } 5312fcf5ef2aSThomas Huth 531350728199SRoman Kapl /* icbiep */ 531450728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 531550728199SRoman Kapl { 531650728199SRoman Kapl TCGv t0; 531750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 531850728199SRoman Kapl t0 = tcg_temp_new(); 531950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 532050728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 532150728199SRoman Kapl tcg_temp_free(t0); 532250728199SRoman Kapl } 532350728199SRoman Kapl 5324fcf5ef2aSThomas Huth /* Optional: */ 5325fcf5ef2aSThomas Huth /* dcba */ 5326fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5327fcf5ef2aSThomas Huth { 5328efe843d8SDavid Gibson /* 5329efe843d8SDavid Gibson * interpreted as no-op 5330efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5331fcf5ef2aSThomas Huth * but does not generate any exception 5332fcf5ef2aSThomas Huth */ 5333fcf5ef2aSThomas Huth } 5334fcf5ef2aSThomas Huth 5335fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5336fcf5ef2aSThomas Huth /* Supervisor only: */ 5337fcf5ef2aSThomas Huth 5338fcf5ef2aSThomas Huth /* mfsr */ 5339fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5340fcf5ef2aSThomas Huth { 5341fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53429f0cf041SMatheus Ferst GEN_PRIV(ctx); 5343fcf5ef2aSThomas Huth #else 5344fcf5ef2aSThomas Huth TCGv t0; 5345fcf5ef2aSThomas Huth 53469f0cf041SMatheus Ferst CHK_SV(ctx); 5347fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5348fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5349fcf5ef2aSThomas Huth tcg_temp_free(t0); 5350fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5351fcf5ef2aSThomas Huth } 5352fcf5ef2aSThomas Huth 5353fcf5ef2aSThomas Huth /* mfsrin */ 5354fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5355fcf5ef2aSThomas Huth { 5356fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53579f0cf041SMatheus Ferst GEN_PRIV(ctx); 5358fcf5ef2aSThomas Huth #else 5359fcf5ef2aSThomas Huth TCGv t0; 5360fcf5ef2aSThomas Huth 53619f0cf041SMatheus Ferst CHK_SV(ctx); 5362fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5363e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5364fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5365fcf5ef2aSThomas Huth tcg_temp_free(t0); 5366fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5367fcf5ef2aSThomas Huth } 5368fcf5ef2aSThomas Huth 5369fcf5ef2aSThomas Huth /* mtsr */ 5370fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5371fcf5ef2aSThomas Huth { 5372fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53739f0cf041SMatheus Ferst GEN_PRIV(ctx); 5374fcf5ef2aSThomas Huth #else 5375fcf5ef2aSThomas Huth TCGv t0; 5376fcf5ef2aSThomas Huth 53779f0cf041SMatheus Ferst CHK_SV(ctx); 5378fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5379fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5380fcf5ef2aSThomas Huth tcg_temp_free(t0); 5381fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5382fcf5ef2aSThomas Huth } 5383fcf5ef2aSThomas Huth 5384fcf5ef2aSThomas Huth /* mtsrin */ 5385fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5386fcf5ef2aSThomas Huth { 5387fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53889f0cf041SMatheus Ferst GEN_PRIV(ctx); 5389fcf5ef2aSThomas Huth #else 5390fcf5ef2aSThomas Huth TCGv t0; 53919f0cf041SMatheus Ferst CHK_SV(ctx); 5392fcf5ef2aSThomas Huth 5393fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5394e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5395fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5396fcf5ef2aSThomas Huth tcg_temp_free(t0); 5397fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5398fcf5ef2aSThomas Huth } 5399fcf5ef2aSThomas Huth 5400fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5401fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5402fcf5ef2aSThomas Huth 5403fcf5ef2aSThomas Huth /* mfsr */ 5404fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5405fcf5ef2aSThomas Huth { 5406fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54079f0cf041SMatheus Ferst GEN_PRIV(ctx); 5408fcf5ef2aSThomas Huth #else 5409fcf5ef2aSThomas Huth TCGv t0; 5410fcf5ef2aSThomas Huth 54119f0cf041SMatheus Ferst CHK_SV(ctx); 5412fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5413fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5414fcf5ef2aSThomas Huth tcg_temp_free(t0); 5415fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5416fcf5ef2aSThomas Huth } 5417fcf5ef2aSThomas Huth 5418fcf5ef2aSThomas Huth /* mfsrin */ 5419fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5420fcf5ef2aSThomas Huth { 5421fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54229f0cf041SMatheus Ferst GEN_PRIV(ctx); 5423fcf5ef2aSThomas Huth #else 5424fcf5ef2aSThomas Huth TCGv t0; 5425fcf5ef2aSThomas Huth 54269f0cf041SMatheus Ferst CHK_SV(ctx); 5427fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5428e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5429fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5430fcf5ef2aSThomas Huth tcg_temp_free(t0); 5431fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5432fcf5ef2aSThomas Huth } 5433fcf5ef2aSThomas Huth 5434fcf5ef2aSThomas Huth /* mtsr */ 5435fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5436fcf5ef2aSThomas Huth { 5437fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54389f0cf041SMatheus Ferst GEN_PRIV(ctx); 5439fcf5ef2aSThomas Huth #else 5440fcf5ef2aSThomas Huth TCGv t0; 5441fcf5ef2aSThomas Huth 54429f0cf041SMatheus Ferst CHK_SV(ctx); 5443fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5444fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5445fcf5ef2aSThomas Huth tcg_temp_free(t0); 5446fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5447fcf5ef2aSThomas Huth } 5448fcf5ef2aSThomas Huth 5449fcf5ef2aSThomas Huth /* mtsrin */ 5450fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5451fcf5ef2aSThomas Huth { 5452fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54539f0cf041SMatheus Ferst GEN_PRIV(ctx); 5454fcf5ef2aSThomas Huth #else 5455fcf5ef2aSThomas Huth TCGv t0; 5456fcf5ef2aSThomas Huth 54579f0cf041SMatheus Ferst CHK_SV(ctx); 5458fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5459e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5460fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5461fcf5ef2aSThomas Huth tcg_temp_free(t0); 5462fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5463fcf5ef2aSThomas Huth } 5464fcf5ef2aSThomas Huth 5465fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5466fcf5ef2aSThomas Huth 5467fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5468fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5469fcf5ef2aSThomas Huth 5470fcf5ef2aSThomas Huth /* tlbia */ 5471fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5472fcf5ef2aSThomas Huth { 5473fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54749f0cf041SMatheus Ferst GEN_PRIV(ctx); 5475fcf5ef2aSThomas Huth #else 54769f0cf041SMatheus Ferst CHK_HV(ctx); 5477fcf5ef2aSThomas Huth 5478fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5479fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5480fcf5ef2aSThomas Huth } 5481fcf5ef2aSThomas Huth 5482fcf5ef2aSThomas Huth /* tlbsync */ 5483fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5484fcf5ef2aSThomas Huth { 5485fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54869f0cf041SMatheus Ferst GEN_PRIV(ctx); 5487fcf5ef2aSThomas Huth #else 548891c60f12SCédric Le Goater 548991c60f12SCédric Le Goater if (ctx->gtse) { 54909f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 549191c60f12SCédric Le Goater } else { 54929f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 549391c60f12SCédric Le Goater } 5494fcf5ef2aSThomas Huth 5495fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5496fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5497fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5498fcf5ef2aSThomas Huth } 5499fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5500fcf5ef2aSThomas Huth } 5501fcf5ef2aSThomas Huth 5502fcf5ef2aSThomas Huth /*** External control ***/ 5503fcf5ef2aSThomas Huth /* Optional: */ 5504fcf5ef2aSThomas Huth 5505fcf5ef2aSThomas Huth /* eciwx */ 5506fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5507fcf5ef2aSThomas Huth { 5508fcf5ef2aSThomas Huth TCGv t0; 5509fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5510fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5511fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5512fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5513c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5514c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5515fcf5ef2aSThomas Huth tcg_temp_free(t0); 5516fcf5ef2aSThomas Huth } 5517fcf5ef2aSThomas Huth 5518fcf5ef2aSThomas Huth /* ecowx */ 5519fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5520fcf5ef2aSThomas Huth { 5521fcf5ef2aSThomas Huth TCGv t0; 5522fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5523fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5524fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5525fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5526c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5527c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5528fcf5ef2aSThomas Huth tcg_temp_free(t0); 5529fcf5ef2aSThomas Huth } 5530fcf5ef2aSThomas Huth 5531fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5532fcf5ef2aSThomas Huth 5533fcf5ef2aSThomas Huth /* tlbld */ 5534fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5535fcf5ef2aSThomas Huth { 5536fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55379f0cf041SMatheus Ferst GEN_PRIV(ctx); 5538fcf5ef2aSThomas Huth #else 55399f0cf041SMatheus Ferst CHK_SV(ctx); 5540fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5541fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5542fcf5ef2aSThomas Huth } 5543fcf5ef2aSThomas Huth 5544fcf5ef2aSThomas Huth /* tlbli */ 5545fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5546fcf5ef2aSThomas Huth { 5547fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55489f0cf041SMatheus Ferst GEN_PRIV(ctx); 5549fcf5ef2aSThomas Huth #else 55509f0cf041SMatheus Ferst CHK_SV(ctx); 5551fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5552fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5553fcf5ef2aSThomas Huth } 5554fcf5ef2aSThomas Huth 5555fcf5ef2aSThomas Huth /* BookE specific instructions */ 5556fcf5ef2aSThomas Huth 5557fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5558fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5559fcf5ef2aSThomas Huth { 5560fcf5ef2aSThomas Huth /* XXX: TODO */ 5561fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5562fcf5ef2aSThomas Huth } 5563fcf5ef2aSThomas Huth 5564fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5565fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5566fcf5ef2aSThomas Huth { 5567fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55689f0cf041SMatheus Ferst GEN_PRIV(ctx); 5569fcf5ef2aSThomas Huth #else 5570fcf5ef2aSThomas Huth TCGv t0; 5571fcf5ef2aSThomas Huth 55729f0cf041SMatheus Ferst CHK_SV(ctx); 5573fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5574fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5575fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5576fcf5ef2aSThomas Huth tcg_temp_free(t0); 5577fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5578fcf5ef2aSThomas Huth } 5579fcf5ef2aSThomas Huth 5580fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5581fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5582fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5583fcf5ef2aSThomas Huth { 5584fcf5ef2aSThomas Huth TCGv t0, t1; 5585fcf5ef2aSThomas Huth 5586fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5587fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5588fcf5ef2aSThomas Huth 5589fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5590fcf5ef2aSThomas Huth case 0x05: 5591fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5592fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5593fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5594fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5595fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5596fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5597fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5598fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5599fcf5ef2aSThomas Huth break; 5600fcf5ef2aSThomas Huth case 0x04: 5601fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5602fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5603fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5604fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5605fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5606fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5607fcf5ef2aSThomas Huth break; 5608fcf5ef2aSThomas Huth case 0x01: 5609fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5610fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5611fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5612fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5613fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5614fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5615fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5616fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5617fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5618fcf5ef2aSThomas Huth break; 5619fcf5ef2aSThomas Huth case 0x00: 5620fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5621fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5622fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5623fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5624fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5625fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5626fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5627fcf5ef2aSThomas Huth break; 5628fcf5ef2aSThomas Huth case 0x0D: 5629fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5630fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5631fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5632fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5633fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5634fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5635fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5636fcf5ef2aSThomas Huth break; 5637fcf5ef2aSThomas Huth case 0x0C: 5638fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5639fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5640fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5641fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5642fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5643fcf5ef2aSThomas Huth break; 5644fcf5ef2aSThomas Huth } 5645fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5646fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5647fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5648fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5649fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5650fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5651fcf5ef2aSThomas Huth } else { 5652fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5653fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5654fcf5ef2aSThomas Huth } 5655fcf5ef2aSThomas Huth 5656fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5657fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5658fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5659fcf5ef2aSThomas Huth 5660fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5661fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5662fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5663fcf5ef2aSThomas Huth } 5664fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5665fcf5ef2aSThomas Huth /* Signed */ 5666fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5667fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5668fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5669fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5670fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5671fcf5ef2aSThomas Huth /* Saturate */ 5672fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5673fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5674fcf5ef2aSThomas Huth } 5675fcf5ef2aSThomas Huth } else { 5676fcf5ef2aSThomas Huth /* Unsigned */ 5677fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5678fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5679fcf5ef2aSThomas Huth /* Saturate */ 5680fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5681fcf5ef2aSThomas Huth } 5682fcf5ef2aSThomas Huth } 5683fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5684fcf5ef2aSThomas Huth /* Check overflow */ 5685fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5686fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5687fcf5ef2aSThomas Huth } 5688fcf5ef2aSThomas Huth gen_set_label(l1); 5689fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5690fcf5ef2aSThomas Huth } 5691fcf5ef2aSThomas Huth } else { 5692fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5693fcf5ef2aSThomas Huth } 5694fcf5ef2aSThomas Huth tcg_temp_free(t0); 5695fcf5ef2aSThomas Huth tcg_temp_free(t1); 5696fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5697fcf5ef2aSThomas Huth /* Update Rc0 */ 5698fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5699fcf5ef2aSThomas Huth } 5700fcf5ef2aSThomas Huth } 5701fcf5ef2aSThomas Huth 5702fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5703fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5704fcf5ef2aSThomas Huth { \ 5705fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5706fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5707fcf5ef2aSThomas Huth } 5708fcf5ef2aSThomas Huth 5709fcf5ef2aSThomas Huth /* macchw - macchw. */ 5710fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5711fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5712fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5713fcf5ef2aSThomas Huth /* macchws - macchws. */ 5714fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5715fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5716fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5717fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5718fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5719fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5720fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5721fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5722fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5723fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5724fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5725fcf5ef2aSThomas Huth /* machhw - machhw. */ 5726fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5727fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5728fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5729fcf5ef2aSThomas Huth /* machhws - machhws. */ 5730fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5731fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5732fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5733fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5734fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5735fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5736fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5737fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5738fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5739fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5740fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5741fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5742fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5743fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5744fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5745fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5746fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5747fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5748fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5749fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5750fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5751fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5752fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5753fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5754fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5755fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5756fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5757fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5758fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5759fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5760fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5761fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5762fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5763fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5764fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5765fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5766fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5767fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5768fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5769fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5770fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5771fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5772fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5773fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5774fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5775fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5776fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5777fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5778fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5779fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5780fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5781fcf5ef2aSThomas Huth 5782fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5783fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5784fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5785fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5786fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5787fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5788fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5789fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5790fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5791fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5792fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5793fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5794fcf5ef2aSThomas Huth 5795fcf5ef2aSThomas Huth /* mfdcr */ 5796fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5797fcf5ef2aSThomas Huth { 5798fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57999f0cf041SMatheus Ferst GEN_PRIV(ctx); 5800fcf5ef2aSThomas Huth #else 5801fcf5ef2aSThomas Huth TCGv dcrn; 5802fcf5ef2aSThomas Huth 58039f0cf041SMatheus Ferst CHK_SV(ctx); 5804fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5805fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5806fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5807fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5808fcf5ef2aSThomas Huth } 5809fcf5ef2aSThomas Huth 5810fcf5ef2aSThomas Huth /* mtdcr */ 5811fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5812fcf5ef2aSThomas Huth { 5813fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58149f0cf041SMatheus Ferst GEN_PRIV(ctx); 5815fcf5ef2aSThomas Huth #else 5816fcf5ef2aSThomas Huth TCGv dcrn; 5817fcf5ef2aSThomas Huth 58189f0cf041SMatheus Ferst CHK_SV(ctx); 5819fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5820fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5821fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5822fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5823fcf5ef2aSThomas Huth } 5824fcf5ef2aSThomas Huth 5825fcf5ef2aSThomas Huth /* mfdcrx */ 5826fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5827fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5828fcf5ef2aSThomas Huth { 5829fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58309f0cf041SMatheus Ferst GEN_PRIV(ctx); 5831fcf5ef2aSThomas Huth #else 58329f0cf041SMatheus Ferst CHK_SV(ctx); 5833fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5834fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5835fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5836fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5837fcf5ef2aSThomas Huth } 5838fcf5ef2aSThomas Huth 5839fcf5ef2aSThomas Huth /* mtdcrx */ 5840fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5841fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5842fcf5ef2aSThomas Huth { 5843fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58449f0cf041SMatheus Ferst GEN_PRIV(ctx); 5845fcf5ef2aSThomas Huth #else 58469f0cf041SMatheus Ferst CHK_SV(ctx); 5847fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5848fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5849fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5850fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5851fcf5ef2aSThomas Huth } 5852fcf5ef2aSThomas Huth 5853fcf5ef2aSThomas Huth /* dccci */ 5854fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5855fcf5ef2aSThomas Huth { 58569f0cf041SMatheus Ferst CHK_SV(ctx); 5857fcf5ef2aSThomas Huth /* interpreted as no-op */ 5858fcf5ef2aSThomas Huth } 5859fcf5ef2aSThomas Huth 5860fcf5ef2aSThomas Huth /* dcread */ 5861fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5862fcf5ef2aSThomas Huth { 5863fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5865fcf5ef2aSThomas Huth #else 5866fcf5ef2aSThomas Huth TCGv EA, val; 5867fcf5ef2aSThomas Huth 58689f0cf041SMatheus Ferst CHK_SV(ctx); 5869fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5870fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5871fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5872fcf5ef2aSThomas Huth val = tcg_temp_new(); 5873fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5874fcf5ef2aSThomas Huth tcg_temp_free(val); 5875fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5876fcf5ef2aSThomas Huth tcg_temp_free(EA); 5877fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5878fcf5ef2aSThomas Huth } 5879fcf5ef2aSThomas Huth 5880fcf5ef2aSThomas Huth /* icbt */ 5881fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5882fcf5ef2aSThomas Huth { 5883efe843d8SDavid Gibson /* 5884efe843d8SDavid Gibson * interpreted as no-op 5885efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5886efe843d8SDavid Gibson * does not generate any exception 5887fcf5ef2aSThomas Huth */ 5888fcf5ef2aSThomas Huth } 5889fcf5ef2aSThomas Huth 5890fcf5ef2aSThomas Huth /* iccci */ 5891fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5892fcf5ef2aSThomas Huth { 58939f0cf041SMatheus Ferst CHK_SV(ctx); 5894fcf5ef2aSThomas Huth /* interpreted as no-op */ 5895fcf5ef2aSThomas Huth } 5896fcf5ef2aSThomas Huth 5897fcf5ef2aSThomas Huth /* icread */ 5898fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5899fcf5ef2aSThomas Huth { 59009f0cf041SMatheus Ferst CHK_SV(ctx); 5901fcf5ef2aSThomas Huth /* interpreted as no-op */ 5902fcf5ef2aSThomas Huth } 5903fcf5ef2aSThomas Huth 5904fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5905fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5906fcf5ef2aSThomas Huth { 5907fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59089f0cf041SMatheus Ferst GEN_PRIV(ctx); 5909fcf5ef2aSThomas Huth #else 59109f0cf041SMatheus Ferst CHK_SV(ctx); 5911fcf5ef2aSThomas Huth /* Restore CPU state */ 5912fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 591359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5914fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5915fcf5ef2aSThomas Huth } 5916fcf5ef2aSThomas Huth 5917fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5918fcf5ef2aSThomas Huth { 5919fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59209f0cf041SMatheus Ferst GEN_PRIV(ctx); 5921fcf5ef2aSThomas Huth #else 59229f0cf041SMatheus Ferst CHK_SV(ctx); 5923fcf5ef2aSThomas Huth /* Restore CPU state */ 5924fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 592559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5926fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5927fcf5ef2aSThomas Huth } 5928fcf5ef2aSThomas Huth 5929fcf5ef2aSThomas Huth /* BookE specific */ 5930fcf5ef2aSThomas Huth 5931fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5932fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5933fcf5ef2aSThomas Huth { 5934fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59359f0cf041SMatheus Ferst GEN_PRIV(ctx); 5936fcf5ef2aSThomas Huth #else 59379f0cf041SMatheus Ferst CHK_SV(ctx); 5938fcf5ef2aSThomas Huth /* Restore CPU state */ 5939fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 594059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5941fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5942fcf5ef2aSThomas Huth } 5943fcf5ef2aSThomas Huth 5944fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5945fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5946fcf5ef2aSThomas Huth { 5947fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59489f0cf041SMatheus Ferst GEN_PRIV(ctx); 5949fcf5ef2aSThomas Huth #else 59509f0cf041SMatheus Ferst CHK_SV(ctx); 5951fcf5ef2aSThomas Huth /* Restore CPU state */ 5952fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 595359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5954fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5955fcf5ef2aSThomas Huth } 5956fcf5ef2aSThomas Huth 5957fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5958fcf5ef2aSThomas Huth 5959fcf5ef2aSThomas Huth /* tlbre */ 5960fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5961fcf5ef2aSThomas Huth { 5962fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59639f0cf041SMatheus Ferst GEN_PRIV(ctx); 5964fcf5ef2aSThomas Huth #else 59659f0cf041SMatheus Ferst CHK_SV(ctx); 5966fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5967fcf5ef2aSThomas Huth case 0: 5968fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5969fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5970fcf5ef2aSThomas Huth break; 5971fcf5ef2aSThomas Huth case 1: 5972fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5973fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5974fcf5ef2aSThomas Huth break; 5975fcf5ef2aSThomas Huth default: 5976fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5977fcf5ef2aSThomas Huth break; 5978fcf5ef2aSThomas Huth } 5979fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5980fcf5ef2aSThomas Huth } 5981fcf5ef2aSThomas Huth 5982fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5983fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5984fcf5ef2aSThomas Huth { 5985fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59869f0cf041SMatheus Ferst GEN_PRIV(ctx); 5987fcf5ef2aSThomas Huth #else 5988fcf5ef2aSThomas Huth TCGv t0; 5989fcf5ef2aSThomas Huth 59909f0cf041SMatheus Ferst CHK_SV(ctx); 5991fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5992fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5993fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5994fcf5ef2aSThomas Huth tcg_temp_free(t0); 5995fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5996fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5997fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5998fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5999fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6000fcf5ef2aSThomas Huth gen_set_label(l1); 6001fcf5ef2aSThomas Huth } 6002fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6003fcf5ef2aSThomas Huth } 6004fcf5ef2aSThomas Huth 6005fcf5ef2aSThomas Huth /* tlbwe */ 6006fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6007fcf5ef2aSThomas Huth { 6008fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60099f0cf041SMatheus Ferst GEN_PRIV(ctx); 6010fcf5ef2aSThomas Huth #else 60119f0cf041SMatheus Ferst CHK_SV(ctx); 6012fcf5ef2aSThomas Huth 6013fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6014fcf5ef2aSThomas Huth case 0: 6015fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6016fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6017fcf5ef2aSThomas Huth break; 6018fcf5ef2aSThomas Huth case 1: 6019fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6020fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6021fcf5ef2aSThomas Huth break; 6022fcf5ef2aSThomas Huth default: 6023fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6024fcf5ef2aSThomas Huth break; 6025fcf5ef2aSThomas Huth } 6026fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6027fcf5ef2aSThomas Huth } 6028fcf5ef2aSThomas Huth 6029fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6030fcf5ef2aSThomas Huth 6031fcf5ef2aSThomas Huth /* tlbre */ 6032fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6033fcf5ef2aSThomas Huth { 6034fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60359f0cf041SMatheus Ferst GEN_PRIV(ctx); 6036fcf5ef2aSThomas Huth #else 60379f0cf041SMatheus Ferst CHK_SV(ctx); 6038fcf5ef2aSThomas Huth 6039fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6040fcf5ef2aSThomas Huth case 0: 6041fcf5ef2aSThomas Huth case 1: 6042fcf5ef2aSThomas Huth case 2: 6043fcf5ef2aSThomas Huth { 6044fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6045fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6046fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6047fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6048fcf5ef2aSThomas Huth } 6049fcf5ef2aSThomas Huth break; 6050fcf5ef2aSThomas Huth default: 6051fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6052fcf5ef2aSThomas Huth break; 6053fcf5ef2aSThomas Huth } 6054fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6055fcf5ef2aSThomas Huth } 6056fcf5ef2aSThomas Huth 6057fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6058fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6059fcf5ef2aSThomas Huth { 6060fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60619f0cf041SMatheus Ferst GEN_PRIV(ctx); 6062fcf5ef2aSThomas Huth #else 6063fcf5ef2aSThomas Huth TCGv t0; 6064fcf5ef2aSThomas Huth 60659f0cf041SMatheus Ferst CHK_SV(ctx); 6066fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6067fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6068fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6069fcf5ef2aSThomas Huth tcg_temp_free(t0); 6070fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6071fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6072fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6073fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6074fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6075fcf5ef2aSThomas Huth gen_set_label(l1); 6076fcf5ef2aSThomas Huth } 6077fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6078fcf5ef2aSThomas Huth } 6079fcf5ef2aSThomas Huth 6080fcf5ef2aSThomas Huth /* tlbwe */ 6081fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6082fcf5ef2aSThomas Huth { 6083fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60849f0cf041SMatheus Ferst GEN_PRIV(ctx); 6085fcf5ef2aSThomas Huth #else 60869f0cf041SMatheus Ferst CHK_SV(ctx); 6087fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6088fcf5ef2aSThomas Huth case 0: 6089fcf5ef2aSThomas Huth case 1: 6090fcf5ef2aSThomas Huth case 2: 6091fcf5ef2aSThomas Huth { 6092fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6093fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6094fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6095fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6096fcf5ef2aSThomas Huth } 6097fcf5ef2aSThomas Huth break; 6098fcf5ef2aSThomas Huth default: 6099fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6100fcf5ef2aSThomas Huth break; 6101fcf5ef2aSThomas Huth } 6102fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6103fcf5ef2aSThomas Huth } 6104fcf5ef2aSThomas Huth 6105fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6106fcf5ef2aSThomas Huth 6107fcf5ef2aSThomas Huth /* tlbre */ 6108fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6109fcf5ef2aSThomas Huth { 6110fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61119f0cf041SMatheus Ferst GEN_PRIV(ctx); 6112fcf5ef2aSThomas Huth #else 61139f0cf041SMatheus Ferst CHK_SV(ctx); 6114fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6115fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6116fcf5ef2aSThomas Huth } 6117fcf5ef2aSThomas Huth 6118fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6119fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6120fcf5ef2aSThomas Huth { 6121fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61229f0cf041SMatheus Ferst GEN_PRIV(ctx); 6123fcf5ef2aSThomas Huth #else 6124fcf5ef2aSThomas Huth TCGv t0; 6125fcf5ef2aSThomas Huth 61269f0cf041SMatheus Ferst CHK_SV(ctx); 6127fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6128fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6129fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6130fcf5ef2aSThomas Huth } else { 6131fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6132fcf5ef2aSThomas Huth } 6133fcf5ef2aSThomas Huth 6134fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6135fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6136fcf5ef2aSThomas Huth tcg_temp_free(t0); 6137fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6138fcf5ef2aSThomas Huth } 6139fcf5ef2aSThomas Huth 6140fcf5ef2aSThomas Huth /* tlbwe */ 6141fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6142fcf5ef2aSThomas Huth { 6143fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61449f0cf041SMatheus Ferst GEN_PRIV(ctx); 6145fcf5ef2aSThomas Huth #else 61469f0cf041SMatheus Ferst CHK_SV(ctx); 6147fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6148fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6149fcf5ef2aSThomas Huth } 6150fcf5ef2aSThomas Huth 6151fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6152fcf5ef2aSThomas Huth { 6153fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61549f0cf041SMatheus Ferst GEN_PRIV(ctx); 6155fcf5ef2aSThomas Huth #else 6156fcf5ef2aSThomas Huth TCGv t0; 6157fcf5ef2aSThomas Huth 61589f0cf041SMatheus Ferst CHK_SV(ctx); 6159fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6160fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6161fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6162fcf5ef2aSThomas Huth tcg_temp_free(t0); 6163fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6164fcf5ef2aSThomas Huth } 6165fcf5ef2aSThomas Huth 6166fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6167fcf5ef2aSThomas Huth { 6168fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61699f0cf041SMatheus Ferst GEN_PRIV(ctx); 6170fcf5ef2aSThomas Huth #else 6171fcf5ef2aSThomas Huth TCGv t0; 6172fcf5ef2aSThomas Huth 61739f0cf041SMatheus Ferst CHK_SV(ctx); 6174fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6175fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6176fcf5ef2aSThomas Huth 6177fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 6178fcf5ef2aSThomas Huth case 0: 6179fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6180fcf5ef2aSThomas Huth break; 6181fcf5ef2aSThomas Huth case 1: 6182fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6183fcf5ef2aSThomas Huth break; 6184fcf5ef2aSThomas Huth case 3: 6185fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6186fcf5ef2aSThomas Huth break; 6187fcf5ef2aSThomas Huth default: 6188fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6189fcf5ef2aSThomas Huth break; 6190fcf5ef2aSThomas Huth } 6191fcf5ef2aSThomas Huth 6192fcf5ef2aSThomas Huth tcg_temp_free(t0); 6193fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6194fcf5ef2aSThomas Huth } 6195fcf5ef2aSThomas Huth 6196fcf5ef2aSThomas Huth /* wrtee */ 6197fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6198fcf5ef2aSThomas Huth { 6199fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 62009f0cf041SMatheus Ferst GEN_PRIV(ctx); 6201fcf5ef2aSThomas Huth #else 6202fcf5ef2aSThomas Huth TCGv t0; 6203fcf5ef2aSThomas Huth 62049f0cf041SMatheus Ferst CHK_SV(ctx); 6205fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6206fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6207fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6208fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 62092fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6210fcf5ef2aSThomas Huth tcg_temp_free(t0); 6211efe843d8SDavid Gibson /* 6212efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6213efe843d8SDavid Gibson * just set msr_ee to 1 6214fcf5ef2aSThomas Huth */ 6215d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6216fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6217fcf5ef2aSThomas Huth } 6218fcf5ef2aSThomas Huth 6219fcf5ef2aSThomas Huth /* wrteei */ 6220fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6221fcf5ef2aSThomas Huth { 6222fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 62239f0cf041SMatheus Ferst GEN_PRIV(ctx); 6224fcf5ef2aSThomas Huth #else 62259f0cf041SMatheus Ferst CHK_SV(ctx); 6226fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6227fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 62282fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6229fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6230d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6231fcf5ef2aSThomas Huth } else { 6232fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6233fcf5ef2aSThomas Huth } 6234fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6235fcf5ef2aSThomas Huth } 6236fcf5ef2aSThomas Huth 6237fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6238fcf5ef2aSThomas Huth 6239fcf5ef2aSThomas Huth /* dlmzb */ 6240fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6241fcf5ef2aSThomas Huth { 6242fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6243fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6244fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6245fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6246fcf5ef2aSThomas Huth } 6247fcf5ef2aSThomas Huth 6248fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6249fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6250fcf5ef2aSThomas Huth { 6251fcf5ef2aSThomas Huth /* interpreted as no-op */ 6252fcf5ef2aSThomas Huth } 6253fcf5ef2aSThomas Huth 6254fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6255fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6256fcf5ef2aSThomas Huth { 625727a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 625827a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 625927a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 626027a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 626127a3ea7eSBALATON Zoltan } 626227a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6263fcf5ef2aSThomas Huth } 6264fcf5ef2aSThomas Huth 6265fcf5ef2aSThomas Huth /* icbt */ 6266fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6267fcf5ef2aSThomas Huth { 6268efe843d8SDavid Gibson /* 6269efe843d8SDavid Gibson * interpreted as no-op 6270efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6271efe843d8SDavid Gibson * does not generate any exception 6272fcf5ef2aSThomas Huth */ 6273fcf5ef2aSThomas Huth } 6274fcf5ef2aSThomas Huth 6275fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6276fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6277fcf5ef2aSThomas Huth { 6278fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6279fcf5ef2aSThomas Huth 6280fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6281fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6282fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6283fcf5ef2aSThomas Huth } 6284fcf5ef2aSThomas Huth 6285fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6286fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6287fcf5ef2aSThomas Huth { 6288fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6289fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6290fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6291fcf5ef2aSThomas Huth 6292fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6293fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6294fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6295fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6296fcf5ef2aSThomas Huth } else { 6297fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6298fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6299fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6300fcf5ef2aSThomas Huth } 6301fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6302fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6303fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6304fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6305fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6306fcf5ef2aSThomas Huth } 6307fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6308fcf5ef2aSThomas Huth 6309fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6310fcf5ef2aSThomas Huth { 6311fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6312fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6313fcf5ef2aSThomas Huth return; 6314fcf5ef2aSThomas Huth } 6315fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6316fcf5ef2aSThomas Huth } 6317fcf5ef2aSThomas Huth 6318fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6319fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6320fcf5ef2aSThomas Huth { \ 6321fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6322fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6323fcf5ef2aSThomas Huth return; \ 6324fcf5ef2aSThomas Huth } \ 6325efe843d8SDavid Gibson /* \ 6326efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6327fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6328fcf5ef2aSThomas Huth * \ 6329fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6330fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6331fcf5ef2aSThomas Huth */ \ 6332fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6333fcf5ef2aSThomas Huth } 6334fcf5ef2aSThomas Huth 6335fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6336fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6337fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6338fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6339fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6340fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6341fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6342efe843d8SDavid Gibson 6343b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6344b8b4576eSSuraj Jitindar Singh { 6345efe843d8SDavid Gibson /* Do Nothing */ 6346b8b4576eSSuraj Jitindar Singh } 6347fcf5ef2aSThomas Huth 634880b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 634980b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 635080b8c1eeSNikunj A Dadhania { \ 6351efe843d8SDavid Gibson /* \ 6352efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6353efe843d8SDavid Gibson * implementation of the copy paste facility \ 635480b8c1eeSNikunj A Dadhania */ \ 635580b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 635680b8c1eeSNikunj A Dadhania } 635780b8c1eeSNikunj A Dadhania 635880b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 635980b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 636080b8c1eeSNikunj A Dadhania 6361fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6362fcf5ef2aSThomas Huth { 6363fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6364fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6365fcf5ef2aSThomas Huth return; 6366fcf5ef2aSThomas Huth } 6367efe843d8SDavid Gibson /* 6368efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6369efe843d8SDavid Gibson * simple: 6370fcf5ef2aSThomas Huth * 6371fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6372fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6373fcf5ef2aSThomas Huth */ 6374fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6375fcf5ef2aSThomas Huth } 6376fcf5ef2aSThomas Huth 6377fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6378fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6379fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6380fcf5ef2aSThomas Huth { \ 63819f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6382fcf5ef2aSThomas Huth } 6383fcf5ef2aSThomas Huth 6384fcf5ef2aSThomas Huth #else 6385fcf5ef2aSThomas Huth 6386fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6387fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6388fcf5ef2aSThomas Huth { \ 63899f0cf041SMatheus Ferst CHK_SV(ctx); \ 6390fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6391fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6392fcf5ef2aSThomas Huth return; \ 6393fcf5ef2aSThomas Huth } \ 6394efe843d8SDavid Gibson /* \ 6395efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6396fcf5ef2aSThomas Huth * simple: \ 6397fcf5ef2aSThomas Huth * \ 6398fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6399fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6400fcf5ef2aSThomas Huth */ \ 6401fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6402fcf5ef2aSThomas Huth } 6403fcf5ef2aSThomas Huth 6404fcf5ef2aSThomas Huth #endif 6405fcf5ef2aSThomas Huth 6406fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6407fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6408fcf5ef2aSThomas Huth 64091a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 64101a404c91SMark Cave-Ayland { 6411e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 64121a404c91SMark Cave-Ayland } 64131a404c91SMark Cave-Ayland 64141a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 64151a404c91SMark Cave-Ayland { 6416e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 64174b65b6e7SVíctor Colombo /* 64184b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 64194b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 64204b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 64214b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 64224b65b6e7SVíctor Colombo * to be 0. 64234b65b6e7SVíctor Colombo */ 64244b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 64251a404c91SMark Cave-Ayland } 64261a404c91SMark Cave-Ayland 6427c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6428c4a18dbfSMark Cave-Ayland { 642937da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6430c4a18dbfSMark Cave-Ayland } 6431c4a18dbfSMark Cave-Ayland 6432c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6433c4a18dbfSMark Cave-Ayland { 643437da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6435c4a18dbfSMark Cave-Ayland } 6436c4a18dbfSMark Cave-Ayland 6437c9826ae9SRichard Henderson /* 6438f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6439f2aabda8SRichard Henderson */ 6440d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6441d39b2cc7SLuis Pires { 6442d39b2cc7SLuis Pires return x * 2; 6443d39b2cc7SLuis Pires } 6444d39b2cc7SLuis Pires 6445f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6446f2aabda8SRichard Henderson { 6447f2aabda8SRichard Henderson return x * 4; 6448f2aabda8SRichard Henderson } 6449f2aabda8SRichard Henderson 6450e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6451e10271e1SMatheus Ferst { 6452e10271e1SMatheus Ferst return x * 16; 6453e10271e1SMatheus Ferst } 6454e10271e1SMatheus Ferst 6455670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6456670f1da3SVíctor Colombo { 6457670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6458670f1da3SVíctor Colombo } 6459670f1da3SVíctor Colombo 6460f2aabda8SRichard Henderson /* 6461c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6462c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6463c9826ae9SRichard Henderson * proper variable. 6464c9826ae9SRichard Henderson */ 6465c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6466c9826ae9SRichard Henderson do { \ 6467c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6468c9826ae9SRichard Henderson return false; \ 6469c9826ae9SRichard Henderson } \ 6470c9826ae9SRichard Henderson } while (0) 6471c9826ae9SRichard Henderson 6472c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6473c9826ae9SRichard Henderson do { \ 6474c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6475c9826ae9SRichard Henderson return false; \ 6476c9826ae9SRichard Henderson } \ 6477c9826ae9SRichard Henderson } while (0) 6478c9826ae9SRichard Henderson 6479c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6480c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6481c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6482c9826ae9SRichard Henderson #else 6483c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6484c9826ae9SRichard Henderson #endif 6485c9826ae9SRichard Henderson 6486e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6487e2205a46SBruno Larsen do { \ 6488e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6489e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6490e2205a46SBruno Larsen return true; \ 6491e2205a46SBruno Larsen } \ 6492e2205a46SBruno Larsen } while (0) 6493e2205a46SBruno Larsen 64948226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 64958226cb2dSBruno Larsen (billionai) do { \ 64968226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 64978226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 64988226cb2dSBruno Larsen (billionai) return true; \ 64998226cb2dSBruno Larsen (billionai) } \ 65008226cb2dSBruno Larsen (billionai) } while (0) 65018226cb2dSBruno Larsen (billionai) 650286057426SFernando Valle #define REQUIRE_FPU(ctx) \ 650386057426SFernando Valle do { \ 650486057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 650586057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 650686057426SFernando Valle return true; \ 650786057426SFernando Valle } \ 650886057426SFernando Valle } while (0) 650986057426SFernando Valle 6510fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6511fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6512fc34e81aSMatheus Ferst do { \ 6513fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6514fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6515fc34e81aSMatheus Ferst return true; \ 6516fc34e81aSMatheus Ferst } \ 6517fc34e81aSMatheus Ferst } while (0) 6518fc34e81aSMatheus Ferst 6519fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6520fc34e81aSMatheus Ferst do { \ 6521e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6522fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6523fc34e81aSMatheus Ferst return true; \ 6524fc34e81aSMatheus Ferst } \ 6525fc34e81aSMatheus Ferst } while (0) 6526fc34e81aSMatheus Ferst #else 6527fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6528fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6529fc34e81aSMatheus Ferst #endif 6530fc34e81aSMatheus Ferst 6531f2aabda8SRichard Henderson /* 6532f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6533f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6534f2aabda8SRichard Henderson */ 6535f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6536f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6537f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 653819f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 653919f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 654019f0862dSLuis Pires { \ 654119f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 654219f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 654319f0862dSLuis Pires } 654419f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 654519f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 654619f0862dSLuis Pires { \ 654719f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 654819f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 654919f0862dSLuis Pires } 6550f2aabda8SRichard Henderson 6551f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6552f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6553f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 655419f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 655519f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 655619f0862dSLuis Pires { \ 655719f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 655819f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 655919f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 656019f0862dSLuis Pires } 6561f2aabda8SRichard Henderson 6562f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6563f2aabda8SRichard Henderson 6564f2aabda8SRichard Henderson 656599082815SRichard Henderson #include "decode-insn32.c.inc" 656699082815SRichard Henderson #include "decode-insn64.c.inc" 6567565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6568565cb109SGustavo Romero 6569725b2d4dSFernando Eckhardt Valle /* 6570725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6571725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6572725b2d4dSFernando Eckhardt Valle */ 6573725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6574725b2d4dSFernando Eckhardt Valle { 6575725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6576725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6577725b2d4dSFernando Eckhardt Valle d->si = a->si; 6578725b2d4dSFernando Eckhardt Valle if (a->r) { 6579725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6580725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6581725b2d4dSFernando Eckhardt Valle return false; 6582725b2d4dSFernando Eckhardt Valle } 6583725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6584725b2d4dSFernando Eckhardt Valle } 6585725b2d4dSFernando Eckhardt Valle return true; 6586725b2d4dSFernando Eckhardt Valle } 6587725b2d4dSFernando Eckhardt Valle 658899082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 658999082815SRichard Henderson 6590139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6591fcf5ef2aSThomas Huth 6592139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6593fcf5ef2aSThomas Huth 6594139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6595fcf5ef2aSThomas Huth 6596139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6597fcf5ef2aSThomas Huth 6598139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6599fcf5ef2aSThomas Huth 66001f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 66011f26c751SDaniel Henrique Barboza 660298f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 660398f43417SMatheus Ferst 6604016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6605016b6e1dSLeandro Lupori 660620e2d04eSLeandro Lupori /* Handles lfdp */ 66075cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 66085cb091a4SNikunj A Dadhania { 660920e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 66105cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 66115cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 66125cb091a4SNikunj A Dadhania } 66135cb091a4SNikunj A Dadhania } 66145cb091a4SNikunj A Dadhania return gen_invalid(ctx); 66155cb091a4SNikunj A Dadhania } 66165cb091a4SNikunj A Dadhania 661720e2d04eSLeandro Lupori /* Handles stfdp */ 6618e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6619e3001664SNikunj A Dadhania { 662020e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 662120e2d04eSLeandro Lupori /* stfdp */ 6622e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6623e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6624e3001664SNikunj A Dadhania } 6625e3001664SNikunj A Dadhania } 6626e3001664SNikunj A Dadhania return gen_invalid(ctx); 6627e3001664SNikunj A Dadhania } 6628e3001664SNikunj A Dadhania 66299d69cfa2SLijun Pan #if defined(TARGET_PPC64) 66309d69cfa2SLijun Pan /* brd */ 66319d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 66329d69cfa2SLijun Pan { 66339d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 66349d69cfa2SLijun Pan } 66359d69cfa2SLijun Pan 66369d69cfa2SLijun Pan /* brw */ 66379d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 66389d69cfa2SLijun Pan { 66399d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 66409d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 66419d69cfa2SLijun Pan 66429d69cfa2SLijun Pan } 66439d69cfa2SLijun Pan 66449d69cfa2SLijun Pan /* brh */ 66459d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 66469d69cfa2SLijun Pan { 6647491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 66489d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 66499d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 66509d69cfa2SLijun Pan 66519d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6652491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6653491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 66549d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 66559d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 66569d69cfa2SLijun Pan 66579d69cfa2SLijun Pan tcg_temp_free_i64(t1); 66589d69cfa2SLijun Pan tcg_temp_free_i64(t2); 66599d69cfa2SLijun Pan } 66609d69cfa2SLijun Pan #endif 66619d69cfa2SLijun Pan 6662fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 66639d69cfa2SLijun Pan #if defined(TARGET_PPC64) 66649d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 66659d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 66669d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 66679d69cfa2SLijun Pan #endif 6668fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6669fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6670fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6671fcf5ef2aSThomas Huth #endif 6672fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6673fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6674fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6675fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6676fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6677fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6678fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6679fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6680fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6681fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6682fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6683fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6684fcf5ef2aSThomas Huth #endif 6685fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6686fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6687fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6688fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6689fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6690fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6691fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 669280b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6693b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 669480b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6695fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6696fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6697fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6698fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6699fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6700fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6701fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6702fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6703fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6704fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6705fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6706fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6707fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6708fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6709fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6710fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6711fcf5ef2aSThomas Huth #endif 6712fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6713fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6714fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6715fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6716fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6717fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6718fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6719fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6720fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6721fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6722fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6723fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6724fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6725fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6726fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6727fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6728fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6729fcf5ef2aSThomas Huth #endif 67305cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 67315cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 673272b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6733e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6734fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6735fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6736fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6737fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6738fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6739fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6740c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6741fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6742fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6743fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6744fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6745a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6746a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6747fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6748fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6749fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6750fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6751a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6752a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6753fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6754fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6755fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6756fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6757fcf5ef2aSThomas Huth #endif 6758fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 67590c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 67600c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 67610c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6762fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6763fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6764fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6765fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6766fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6767fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6768fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6769fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6770fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 67713c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 67723c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 67733c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 67743c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 67753c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 67763c89b8d6SNicholas Piggin #endif 6777cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6778fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6779fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6780fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6781fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6782fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6783fcf5ef2aSThomas Huth #endif 67843c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 67853c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 67863c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6787fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6788fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6789fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6790fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6791fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6792fcf5ef2aSThomas Huth #endif 6793fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6794fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6795fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6796fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6797fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6798fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6799fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6800fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6801fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6802b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6803fcf5ef2aSThomas Huth #endif 6804fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6805fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6806fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 680750728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6808fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6809fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 681050728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6811fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 681250728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6813fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 681450728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6815fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6816fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 681750728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6818fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 681999d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6820fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6821fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 682250728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6823fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6824fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6825fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6826fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6827fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6828fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6829fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6830fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6831fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6832fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6833fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6834fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6835fcf5ef2aSThomas Huth #endif 6836fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6837efe843d8SDavid Gibson /* 6838efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6839efe843d8SDavid Gibson * different ISA versions 6840efe843d8SDavid Gibson */ 6841fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6842fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6843fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6844fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6845fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6846fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6847fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6848fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6849fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6850fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6851fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6852fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6853fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6854fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6855fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6856fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6857fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6858fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6859fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6860fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6861fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6862fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6863fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6864fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6865fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6866fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6867fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6868fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6869fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6870fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6871fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6872fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6873fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6874fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6875fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6876fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6877fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6878fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6879fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6880fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6881fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 688227a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6883fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6884fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 68850c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 68860c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6887fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6888fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6889fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6890fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6891fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6892fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6893fcf5ef2aSThomas Huth PPC2_ISA300), 6894fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6895fcf5ef2aSThomas Huth #endif 6896fcf5ef2aSThomas Huth 6897fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6898fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6899fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6900fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6901fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6902fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6903fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6904fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6905fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6906fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6907fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6908fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6909fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6910fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6911fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 69124c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6913fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6914fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6915fcf5ef2aSThomas Huth 6916fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6917fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6918fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6919fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6920fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6921fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6922fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6923fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6924fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6925fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6926fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6927fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6928fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6929fcf5ef2aSThomas Huth 6930fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6931fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6932fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6933fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6934fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6935fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6936fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6937fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6938fcf5ef2aSThomas Huth 6939fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6940fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6941fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6942fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6943fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6944fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6945fcf5ef2aSThomas Huth 6946fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6947fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6948fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6949fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6950fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6951fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6952fcf5ef2aSThomas Huth #endif 6953fcf5ef2aSThomas Huth 6954fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6955fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6956fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6957fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6958fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6959fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6960fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6961fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6962fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6963fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6964fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6965fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6966fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6967fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6968fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6969fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6970fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6971fcf5ef2aSThomas Huth 6972fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6973fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6974fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6975fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6976fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6977fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6978fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6979fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6980fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6981fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6982fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6983fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6984fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6985fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6986fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6987fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6988fcf5ef2aSThomas Huth #endif 6989fcf5ef2aSThomas Huth 6990fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6991fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6992fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6993fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6994fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6995fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6996fcf5ef2aSThomas Huth PPC_64B) 6997fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6998fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6999fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7000fcf5ef2aSThomas Huth PPC_64B), \ 7001fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7002fcf5ef2aSThomas Huth PPC_64B), \ 7003fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7004fcf5ef2aSThomas Huth PPC_64B) 7005fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7006fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7007fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7008fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7009fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7010fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7011fcf5ef2aSThomas Huth #endif 7012fcf5ef2aSThomas Huth 7013fcf5ef2aSThomas Huth #undef GEN_LDX_E 7014fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7015fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7016fcf5ef2aSThomas Huth 7017fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7018fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7019fcf5ef2aSThomas Huth 7020fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7021fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7022fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7023fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7024fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7025fcf5ef2aSThomas Huth #endif 7026fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7027fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7028fcf5ef2aSThomas Huth 702950728199SRoman Kapl /* External PID based load */ 703050728199SRoman Kapl #undef GEN_LDEPX 703150728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 703250728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 703350728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 703450728199SRoman Kapl 703550728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 703650728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 703750728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 703850728199SRoman Kapl #if defined(TARGET_PPC64) 7039fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 704050728199SRoman Kapl #endif 704150728199SRoman Kapl 7042fcf5ef2aSThomas Huth #undef GEN_STX_E 7043fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 70440123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7045fcf5ef2aSThomas Huth 7046fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7047fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7048fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7049fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7050fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7051fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7052fcf5ef2aSThomas Huth #endif 7053fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7054fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7055fcf5ef2aSThomas Huth 705650728199SRoman Kapl #undef GEN_STEPX 705750728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 705850728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 705950728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 706050728199SRoman Kapl 706150728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 706250728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 706350728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 706450728199SRoman Kapl #if defined(TARGET_PPC64) 7065fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 706650728199SRoman Kapl #endif 706750728199SRoman Kapl 7068fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7069fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7070fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7071fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7072fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7073fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7074fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7075fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7076fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7077fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7078fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7079fcf5ef2aSThomas Huth 7080fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7081fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7082fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7083fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7084fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7085fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7086fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7087fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7088fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7089fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7090fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7091fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7092fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7093fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7094fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7096fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7104fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7106fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7108fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7110fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7112fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7114fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7116fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7118fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7120fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7122fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7124fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7125fcf5ef2aSThomas Huth 7126fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7127fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7128fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7129fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7130fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7131fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7132fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7133fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7134fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7135fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7136fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7137fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7138fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7139fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7140fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7141fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7142fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7143fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7144fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7145fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7146fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7147fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7148fcf5ef2aSThomas Huth 7149139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 7150fcf5ef2aSThomas Huth 7151139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 7152fcf5ef2aSThomas Huth 7153139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 7154fcf5ef2aSThomas Huth 7155139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 7156fcf5ef2aSThomas Huth }; 7157fcf5ef2aSThomas Huth 71587468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71597468e2c8SBruno Larsen (billionai) /* Opcode types */ 71607468e2c8SBruno Larsen (billionai) enum { 71617468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 71627468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 71637468e2c8SBruno Larsen (billionai) }; 71647468e2c8SBruno Larsen (billionai) 71657468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 71667468e2c8SBruno Larsen (billionai) 71677468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 71687468e2c8SBruno Larsen (billionai) { 71697468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 71707468e2c8SBruno Larsen (billionai) } 71717468e2c8SBruno Larsen (billionai) 71727468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 71737468e2c8SBruno Larsen (billionai) { 71747468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 71757468e2c8SBruno Larsen (billionai) } 71767468e2c8SBruno Larsen (billionai) 71777468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 71787468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 71797468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 71807468e2c8SBruno Larsen (billionai) { 71817468e2c8SBruno Larsen (billionai) int i; 71827468e2c8SBruno Larsen (billionai) 71837468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 71847468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71857468e2c8SBruno Larsen (billionai) } 71867468e2c8SBruno Larsen (billionai) } 71877468e2c8SBruno Larsen (billionai) 71887468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 71897468e2c8SBruno Larsen (billionai) { 71907468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 71917468e2c8SBruno Larsen (billionai) 71927468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 71937468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 71947468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 71957468e2c8SBruno Larsen (billionai) 71967468e2c8SBruno Larsen (billionai) return 0; 71977468e2c8SBruno Larsen (billionai) } 71987468e2c8SBruno Larsen (billionai) 71997468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 72007468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72017468e2c8SBruno Larsen (billionai) { 72027468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 72037468e2c8SBruno Larsen (billionai) return -1; 72047468e2c8SBruno Larsen (billionai) } 72057468e2c8SBruno Larsen (billionai) table[idx] = handler; 72067468e2c8SBruno Larsen (billionai) 72077468e2c8SBruno Larsen (billionai) return 0; 72087468e2c8SBruno Larsen (billionai) } 72097468e2c8SBruno Larsen (billionai) 72107468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 72117468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 72127468e2c8SBruno Larsen (billionai) { 72137468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 72147468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 72157468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 72167468e2c8SBruno Larsen (billionai) return -1; 72177468e2c8SBruno Larsen (billionai) } 72187468e2c8SBruno Larsen (billionai) 72197468e2c8SBruno Larsen (billionai) return 0; 72207468e2c8SBruno Larsen (billionai) } 72217468e2c8SBruno Larsen (billionai) 72227468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 72237468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72247468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72257468e2c8SBruno Larsen (billionai) { 72267468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 72277468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 72287468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 72297468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 72307468e2c8SBruno Larsen (billionai) return -1; 72317468e2c8SBruno Larsen (billionai) } 72327468e2c8SBruno Larsen (billionai) } else { 72337468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 72347468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 72357468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 72367468e2c8SBruno Larsen (billionai) return -1; 72377468e2c8SBruno Larsen (billionai) } 72387468e2c8SBruno Larsen (billionai) } 72397468e2c8SBruno Larsen (billionai) if (handler != NULL && 72407468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 72417468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 72427468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 72437468e2c8SBruno Larsen (billionai) return -1; 72447468e2c8SBruno Larsen (billionai) } 72457468e2c8SBruno Larsen (billionai) 72467468e2c8SBruno Larsen (billionai) return 0; 72477468e2c8SBruno Larsen (billionai) } 72487468e2c8SBruno Larsen (billionai) 72497468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 72507468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72517468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72527468e2c8SBruno Larsen (billionai) { 72537468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 72547468e2c8SBruno Larsen (billionai) } 72557468e2c8SBruno Larsen (billionai) 72567468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 72577468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72587468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 72597468e2c8SBruno Larsen (billionai) { 72607468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 72617468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 72627468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 72637468e2c8SBruno Larsen (billionai) return -1; 72647468e2c8SBruno Larsen (billionai) } 72657468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 72667468e2c8SBruno Larsen (billionai) handler) < 0) { 72677468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 72687468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 72697468e2c8SBruno Larsen (billionai) return -1; 72707468e2c8SBruno Larsen (billionai) } 72717468e2c8SBruno Larsen (billionai) 72727468e2c8SBruno Larsen (billionai) return 0; 72737468e2c8SBruno Larsen (billionai) } 72747468e2c8SBruno Larsen (billionai) 72757468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 72767468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72777468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 72787468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72797468e2c8SBruno Larsen (billionai) { 72807468e2c8SBruno Larsen (billionai) opc_handler_t **table; 72817468e2c8SBruno Larsen (billionai) 72827468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 72837468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 72847468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 72857468e2c8SBruno Larsen (billionai) return -1; 72867468e2c8SBruno Larsen (billionai) } 72877468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 72887468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 72897468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 72907468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 72917468e2c8SBruno Larsen (billionai) return -1; 72927468e2c8SBruno Larsen (billionai) } 72937468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 72947468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 72957468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 72967468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 72977468e2c8SBruno Larsen (billionai) return -1; 72987468e2c8SBruno Larsen (billionai) } 72997468e2c8SBruno Larsen (billionai) return 0; 73007468e2c8SBruno Larsen (billionai) } 73017468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 73027468e2c8SBruno Larsen (billionai) { 73037468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 73047468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 73057468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 73067468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 73077468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 73087468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 73097468e2c8SBruno Larsen (billionai) return -1; 73107468e2c8SBruno Larsen (billionai) } 73117468e2c8SBruno Larsen (billionai) } else { 73127468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 73137468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 73147468e2c8SBruno Larsen (billionai) return -1; 73157468e2c8SBruno Larsen (billionai) } 73167468e2c8SBruno Larsen (billionai) } 73177468e2c8SBruno Larsen (billionai) } else { 73187468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 73197468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 73207468e2c8SBruno Larsen (billionai) return -1; 73217468e2c8SBruno Larsen (billionai) } 73227468e2c8SBruno Larsen (billionai) } 73237468e2c8SBruno Larsen (billionai) } else { 73247468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 73257468e2c8SBruno Larsen (billionai) return -1; 73267468e2c8SBruno Larsen (billionai) } 73277468e2c8SBruno Larsen (billionai) } 73287468e2c8SBruno Larsen (billionai) 73297468e2c8SBruno Larsen (billionai) return 0; 73307468e2c8SBruno Larsen (billionai) } 73317468e2c8SBruno Larsen (billionai) 73327468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 73337468e2c8SBruno Larsen (billionai) { 73347468e2c8SBruno Larsen (billionai) int i, count, tmp; 73357468e2c8SBruno Larsen (billionai) 73367468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 73377468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 73387468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 73397468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 73407468e2c8SBruno Larsen (billionai) } 73417468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 73427468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 73437468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 73447468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 73457468e2c8SBruno Larsen (billionai) if (tmp == 0) { 73467468e2c8SBruno Larsen (billionai) free(table[i]); 73477468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 73487468e2c8SBruno Larsen (billionai) } else { 73497468e2c8SBruno Larsen (billionai) count++; 73507468e2c8SBruno Larsen (billionai) } 73517468e2c8SBruno Larsen (billionai) } else { 73527468e2c8SBruno Larsen (billionai) count++; 73537468e2c8SBruno Larsen (billionai) } 73547468e2c8SBruno Larsen (billionai) } 73557468e2c8SBruno Larsen (billionai) } 73567468e2c8SBruno Larsen (billionai) 73577468e2c8SBruno Larsen (billionai) return count; 73587468e2c8SBruno Larsen (billionai) } 73597468e2c8SBruno Larsen (billionai) 73607468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 73617468e2c8SBruno Larsen (billionai) { 73627468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 73637468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 73647468e2c8SBruno Larsen (billionai) } 73657468e2c8SBruno Larsen (billionai) } 73667468e2c8SBruno Larsen (billionai) 73677468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 73687468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 73697468e2c8SBruno Larsen (billionai) { 73707468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 73717468e2c8SBruno Larsen (billionai) opcode_t *opc; 73727468e2c8SBruno Larsen (billionai) 73737468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 73747468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 73757468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 73767468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 73777468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 73787468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 73797468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 73807468e2c8SBruno Larsen (billionai) opc->opc3); 73817468e2c8SBruno Larsen (billionai) return; 73827468e2c8SBruno Larsen (billionai) } 73837468e2c8SBruno Larsen (billionai) } 73847468e2c8SBruno Larsen (billionai) } 73857468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 73867468e2c8SBruno Larsen (billionai) fflush(stdout); 73877468e2c8SBruno Larsen (billionai) fflush(stderr); 73887468e2c8SBruno Larsen (billionai) } 73897468e2c8SBruno Larsen (billionai) 73907468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 73917468e2c8SBruno Larsen (billionai) { 73927468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 73937468e2c8SBruno Larsen (billionai) int i, j, k; 73947468e2c8SBruno Larsen (billionai) 73957468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 73967468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 73977468e2c8SBruno Larsen (billionai) continue; 73987468e2c8SBruno Larsen (billionai) } 73997468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 74007468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 74017468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 74027468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 74037468e2c8SBruno Larsen (billionai) continue; 74047468e2c8SBruno Larsen (billionai) } 74057468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 74067468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 74077468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 74087468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 74097468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 74107468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 74117468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74127468e2c8SBruno Larsen (billionai) } 74137468e2c8SBruno Larsen (billionai) } 74147468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 74157468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74167468e2c8SBruno Larsen (billionai) } 74177468e2c8SBruno Larsen (billionai) } 74187468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 74197468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74207468e2c8SBruno Larsen (billionai) } 74217468e2c8SBruno Larsen (billionai) } 74227468e2c8SBruno Larsen (billionai) } 74237468e2c8SBruno Larsen (billionai) 74247468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 74257468e2c8SBruno Larsen (billionai) { 74267468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 74277468e2c8SBruno Larsen (billionai) 74287468e2c8SBruno Larsen (billionai) /* 74297468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 74307468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 74317468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 74327468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 74337468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 74347468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 74357468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 74367468e2c8SBruno Larsen (billionai) */ 74377468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 74387468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 74397468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 74407468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 74417468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 74427468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 74437468e2c8SBruno Larsen (billionai) } 74447468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 74457468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 74467468e2c8SBruno Larsen (billionai) return 0; 74477468e2c8SBruno Larsen (billionai) } 74487468e2c8SBruno Larsen (billionai) 7449624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7450624cb07fSRichard Henderson { 7451624cb07fSRichard Henderson opc_handler_t **table, *handler; 7452624cb07fSRichard Henderson uint32_t inval; 7453624cb07fSRichard Henderson 7454624cb07fSRichard Henderson ctx->opcode = insn; 7455624cb07fSRichard Henderson 7456624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7457624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7458624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7459624cb07fSRichard Henderson 7460624cb07fSRichard Henderson table = cpu->opcodes; 7461624cb07fSRichard Henderson handler = table[opc1(insn)]; 7462624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7463624cb07fSRichard Henderson table = ind_table(handler); 7464624cb07fSRichard Henderson handler = table[opc2(insn)]; 7465624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7466624cb07fSRichard Henderson table = ind_table(handler); 7467624cb07fSRichard Henderson handler = table[opc3(insn)]; 7468624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7469624cb07fSRichard Henderson table = ind_table(handler); 7470624cb07fSRichard Henderson handler = table[opc4(insn)]; 7471624cb07fSRichard Henderson } 7472624cb07fSRichard Henderson } 7473624cb07fSRichard Henderson } 7474624cb07fSRichard Henderson 7475624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7476624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7477624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7478624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7479624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7480624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7481624cb07fSRichard Henderson insn, ctx->cia); 7482624cb07fSRichard Henderson return false; 7483624cb07fSRichard Henderson } 7484624cb07fSRichard Henderson 7485624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7486624cb07fSRichard Henderson && Rc(insn))) { 7487624cb07fSRichard Henderson inval = handler->inval2; 7488624cb07fSRichard Henderson } else { 7489624cb07fSRichard Henderson inval = handler->inval1; 7490624cb07fSRichard Henderson } 7491624cb07fSRichard Henderson 7492624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7493624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7494624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7495624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7496624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7497624cb07fSRichard Henderson insn, ctx->cia); 7498624cb07fSRichard Henderson return false; 7499624cb07fSRichard Henderson } 7500624cb07fSRichard Henderson 7501624cb07fSRichard Henderson handler->handler(ctx); 7502624cb07fSRichard Henderson return true; 7503624cb07fSRichard Henderson } 7504624cb07fSRichard Henderson 7505b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7506fcf5ef2aSThomas Huth { 7507b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 75089c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 75092df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7510fcf5ef2aSThomas Huth 7511b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 75122df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7513d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 75142df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 75152df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7516b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7517b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7518b0c2d521SEmilio G. Cota ctx->access_type = -1; 7519d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 75202df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7521b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 75220e3bf489SRoman Kapl ctx->flags = env->flags; 7523fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 75242df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7525b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7526fcf5ef2aSThomas Huth #endif 7527e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7528d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7529fcf5ef2aSThomas Huth 75302df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 75312df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 75322df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 75332df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 75342df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7535f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 75361db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7537f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7538f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 75398b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 75408b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 754146d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 75422df4fe7aSRichard Henderson 7543b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 75442df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 75452df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 75469498d103SRichard Henderson ctx->base.max_insns = 1; 7547efe843d8SDavid Gibson } 75482df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7549b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7550efe843d8SDavid Gibson } 755113b45575SRichard Henderson } 7552fcf5ef2aSThomas Huth 7553b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7554b0c2d521SEmilio G. Cota { 7555b0c2d521SEmilio G. Cota } 7556fcf5ef2aSThomas Huth 7557b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7558b0c2d521SEmilio G. Cota { 7559b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7560b0c2d521SEmilio G. Cota } 7561b0c2d521SEmilio G. Cota 756299082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 756399082815SRichard Henderson { 756499082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 756599082815SRichard Henderson return opc1(insn) == 1; 756699082815SRichard Henderson } 756799082815SRichard Henderson 7568b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7569b0c2d521SEmilio G. Cota { 7570b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 757128876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7572b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 757399082815SRichard Henderson target_ulong pc; 7574624cb07fSRichard Henderson uint32_t insn; 7575624cb07fSRichard Henderson bool ok; 7576b0c2d521SEmilio G. Cota 7577fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7578fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7579b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7580b0c2d521SEmilio G. Cota 758199082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 75824e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 758399082815SRichard Henderson ctx->base.pc_next = pc += 4; 7584fcf5ef2aSThomas Huth 758599082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 758699082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 758799082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 758899082815SRichard Henderson } else if ((pc & 63) == 0) { 758999082815SRichard Henderson /* 759099082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 759199082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 759299082815SRichard Henderson * 64-byte address boundary (system alignment error). 759399082815SRichard Henderson */ 759499082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 759599082815SRichard Henderson ok = true; 759699082815SRichard Henderson } else { 75974e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 75984e116893SIlya Leoshkevich need_byteswap(ctx)); 759999082815SRichard Henderson ctx->base.pc_next = pc += 4; 760099082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 760199082815SRichard Henderson } 7602624cb07fSRichard Henderson if (!ok) { 7603624cb07fSRichard Henderson gen_invalid(ctx); 7604fcf5ef2aSThomas Huth } 7605624cb07fSRichard Henderson 760664a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 760799082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 760864a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 760964a0f644SRichard Henderson } 761064a0f644SRichard Henderson 761151eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 7612fcf5ef2aSThomas Huth } 7613b0c2d521SEmilio G. Cota 7614b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7615b0c2d521SEmilio G. Cota { 7616b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7617a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7618a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7619b0c2d521SEmilio G. Cota 7620a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7621a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 76223d8a5b69SRichard Henderson return; 76233d8a5b69SRichard Henderson } 76243d8a5b69SRichard Henderson 7625a9b5b3d0SRichard Henderson /* Honor single stepping. */ 76269498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 76279498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7628a9b5b3d0SRichard Henderson switch (is_jmp) { 7629a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7630a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7631a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7632a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7633a9b5b3d0SRichard Henderson break; 7634a9b5b3d0SRichard Henderson case DISAS_EXIT: 7635a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7636a9b5b3d0SRichard Henderson break; 7637a9b5b3d0SRichard Henderson default: 7638a9b5b3d0SRichard Henderson g_assert_not_reached(); 7639fcf5ef2aSThomas Huth } 764013b45575SRichard Henderson 7641a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7642a9b5b3d0SRichard Henderson return; 7643a9b5b3d0SRichard Henderson } 7644a9b5b3d0SRichard Henderson 7645a9b5b3d0SRichard Henderson switch (is_jmp) { 7646a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7647a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 764846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7649a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7650a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7651a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7652a9b5b3d0SRichard Henderson break; 7653a9b5b3d0SRichard Henderson } 7654a9b5b3d0SRichard Henderson /* fall through */ 7655a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7656a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7657a9b5b3d0SRichard Henderson /* fall through */ 7658a9b5b3d0SRichard Henderson case DISAS_CHAIN: 765946d396bdSDaniel Henrique Barboza /* 766046d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 766146d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 766246d396bdSDaniel Henrique Barboza */ 766346d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 766446d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 766546d396bdSDaniel Henrique Barboza } 766646d396bdSDaniel Henrique Barboza 7667a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7668a9b5b3d0SRichard Henderson break; 7669a9b5b3d0SRichard Henderson 7670a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7671a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7672a9b5b3d0SRichard Henderson /* fall through */ 7673a9b5b3d0SRichard Henderson case DISAS_EXIT: 767446d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 767507ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7676a9b5b3d0SRichard Henderson break; 7677a9b5b3d0SRichard Henderson 7678a9b5b3d0SRichard Henderson default: 7679a9b5b3d0SRichard Henderson g_assert_not_reached(); 7680fcf5ef2aSThomas Huth } 7681fcf5ef2aSThomas Huth } 7682b0c2d521SEmilio G. Cota 76838eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 76848eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7685b0c2d521SEmilio G. Cota { 76868eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 76878eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7688b0c2d521SEmilio G. Cota } 7689b0c2d521SEmilio G. Cota 7690b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7691b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7692b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7693b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7694b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7695b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7696b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7697b0c2d521SEmilio G. Cota }; 7698b0c2d521SEmilio G. Cota 7699306c8721SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 7700306c8721SRichard Henderson target_ulong pc, void *host_pc) 7701b0c2d521SEmilio G. Cota { 7702b0c2d521SEmilio G. Cota DisasContext ctx; 7703b0c2d521SEmilio G. Cota 7704306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7705fcf5ef2aSThomas Huth } 7706