1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26fcf5ef2aSThomas Huth #include "tcg-op.h" 27fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #include "trace-tcg.h" 34b6bac4bcSEmilio G. Cota #include "exec/translator.h" 35fcf5ef2aSThomas Huth #include "exec/log.h" 36f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 37fcf5ef2aSThomas Huth 38fcf5ef2aSThomas Huth 39fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 40fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 41fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 44fcf5ef2aSThomas Huth //#define PPC_DEBUG_DISAS 45fcf5ef2aSThomas Huth //#define DO_PPC_STATISTICS 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 48fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 49fcf5ef2aSThomas Huth #else 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 51fcf5ef2aSThomas Huth #endif 52fcf5ef2aSThomas Huth /*****************************************************************************/ 53fcf5ef2aSThomas Huth /* Code translation helpers */ 54fcf5ef2aSThomas Huth 55fcf5ef2aSThomas Huth /* global register indexes */ 56fcf5ef2aSThomas Huth static char cpu_reg_names[10*3 + 22*4 /* GPR */ 57fcf5ef2aSThomas Huth + 10*4 + 22*5 /* SPE GPRh */ 58fcf5ef2aSThomas Huth + 8*5 /* CRF */]; 59fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 60fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 61fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 62fcf5ef2aSThomas Huth static TCGv cpu_nip; 63fcf5ef2aSThomas Huth static TCGv cpu_msr; 64fcf5ef2aSThomas Huth static TCGv cpu_ctr; 65fcf5ef2aSThomas Huth static TCGv cpu_lr; 66fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 67fcf5ef2aSThomas Huth static TCGv cpu_cfar; 68fcf5ef2aSThomas Huth #endif 69dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 70fcf5ef2aSThomas Huth static TCGv cpu_reserve; 71253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 72fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 73fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 74fcf5ef2aSThomas Huth 75fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth void ppc_translate_init(void) 78fcf5ef2aSThomas Huth { 79fcf5ef2aSThomas Huth int i; 80fcf5ef2aSThomas Huth char* p; 81fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 82fcf5ef2aSThomas Huth 83fcf5ef2aSThomas Huth p = cpu_reg_names; 84fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 85fcf5ef2aSThomas Huth 86fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 87fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 88fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 89fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 90fcf5ef2aSThomas Huth p += 5; 91fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 92fcf5ef2aSThomas Huth } 93fcf5ef2aSThomas Huth 94fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 95fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 96fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 97fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 98fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 99fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 101fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 105fcf5ef2aSThomas Huth } 106fcf5ef2aSThomas Huth 107fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 108fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 109fcf5ef2aSThomas Huth 110fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 111fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 112fcf5ef2aSThomas Huth 113fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 114fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 115fcf5ef2aSThomas Huth 116fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 117fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 118fcf5ef2aSThomas Huth 119fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 120fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 122fcf5ef2aSThomas Huth #endif 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 125fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 126fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 128fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 130fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 132dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 133dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 134dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 136fcf5ef2aSThomas Huth 137fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 138fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 139fcf5ef2aSThomas Huth "reserve_addr"); 140253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 141253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 142253ce7b2SNikunj A Dadhania "reserve_val"); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 145fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 146fcf5ef2aSThomas Huth 147fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 148fcf5ef2aSThomas Huth offsetof(CPUPPCState, access_type), "access_type"); 149fcf5ef2aSThomas Huth } 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth /* internal defines */ 152fcf5ef2aSThomas Huth struct DisasContext { 153b6bac4bcSEmilio G. Cota DisasContextBase base; 154fcf5ef2aSThomas Huth uint32_t opcode; 155fcf5ef2aSThomas Huth uint32_t exception; 156fcf5ef2aSThomas Huth /* Routine used to access memory */ 157fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 158fcf5ef2aSThomas Huth bool lazy_tlb_flush; 159fcf5ef2aSThomas Huth bool need_access_type; 160fcf5ef2aSThomas Huth int mem_idx; 161fcf5ef2aSThomas Huth int access_type; 162fcf5ef2aSThomas Huth /* Translation flags */ 163fcf5ef2aSThomas Huth TCGMemOp default_tcg_memop_mask; 164fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 165fcf5ef2aSThomas Huth bool sf_mode; 166fcf5ef2aSThomas Huth bool has_cfar; 167fcf5ef2aSThomas Huth #endif 168fcf5ef2aSThomas Huth bool fpu_enabled; 169fcf5ef2aSThomas Huth bool altivec_enabled; 170fcf5ef2aSThomas Huth bool vsx_enabled; 171fcf5ef2aSThomas Huth bool spe_enabled; 172fcf5ef2aSThomas Huth bool tm_enabled; 173c6fd28fdSSuraj Jitindar Singh bool gtse; 174fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 175fcf5ef2aSThomas Huth int singlestep_enabled; 1760e3bf489SRoman Kapl uint32_t flags; 177fcf5ef2aSThomas Huth uint64_t insns_flags; 178fcf5ef2aSThomas Huth uint64_t insns_flags2; 179fcf5ef2aSThomas Huth }; 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 182fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 183fcf5ef2aSThomas Huth { 184fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 185fcf5ef2aSThomas Huth return ctx->le_mode; 186fcf5ef2aSThomas Huth #else 187fcf5ef2aSThomas Huth return !ctx->le_mode; 188fcf5ef2aSThomas Huth #endif 189fcf5ef2aSThomas Huth } 190fcf5ef2aSThomas Huth 191fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 192fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 193fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 194fcf5ef2aSThomas Huth #else 195fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 196fcf5ef2aSThomas Huth #endif 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth struct opc_handler_t { 199fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 200fcf5ef2aSThomas Huth uint32_t inval1; 201fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 202fcf5ef2aSThomas Huth uint32_t inval2; 203fcf5ef2aSThomas Huth /* instruction type */ 204fcf5ef2aSThomas Huth uint64_t type; 205fcf5ef2aSThomas Huth /* extended instruction type */ 206fcf5ef2aSThomas Huth uint64_t type2; 207fcf5ef2aSThomas Huth /* handler */ 208fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 209fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 210fcf5ef2aSThomas Huth const char *oname; 211fcf5ef2aSThomas Huth #endif 212fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 213fcf5ef2aSThomas Huth uint64_t count; 214fcf5ef2aSThomas Huth #endif 215fcf5ef2aSThomas Huth }; 216fcf5ef2aSThomas Huth 2170e3bf489SRoman Kapl /* SPR load/store helpers */ 2180e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2190e3bf489SRoman Kapl { 2200e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2210e3bf489SRoman Kapl } 2220e3bf489SRoman Kapl 2230e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2240e3bf489SRoman Kapl { 2250e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2260e3bf489SRoman Kapl } 2270e3bf489SRoman Kapl 228fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 229fcf5ef2aSThomas Huth { 230fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 231fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 232fcf5ef2aSThomas Huth ctx->access_type = access_type; 233fcf5ef2aSThomas Huth } 234fcf5ef2aSThomas Huth } 235fcf5ef2aSThomas Huth 236fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 237fcf5ef2aSThomas Huth { 238fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 239fcf5ef2aSThomas Huth nip = (uint32_t)nip; 240fcf5ef2aSThomas Huth } 241fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 242fcf5ef2aSThomas Huth } 243fcf5ef2aSThomas Huth 244fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 245fcf5ef2aSThomas Huth { 246fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 247fcf5ef2aSThomas Huth 248fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 249fcf5ef2aSThomas Huth * the faulting instruction 250fcf5ef2aSThomas Huth */ 251fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 252b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 253fcf5ef2aSThomas Huth } 254fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 255fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 256fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 257fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 258fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 259fcf5ef2aSThomas Huth ctx->exception = (excp); 260fcf5ef2aSThomas Huth } 261fcf5ef2aSThomas Huth 262fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 263fcf5ef2aSThomas Huth { 264fcf5ef2aSThomas Huth TCGv_i32 t0; 265fcf5ef2aSThomas Huth 266fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 267fcf5ef2aSThomas Huth * the faulting instruction 268fcf5ef2aSThomas Huth */ 269fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 270b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 271fcf5ef2aSThomas Huth } 272fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 273fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 274fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 275fcf5ef2aSThomas Huth ctx->exception = (excp); 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth 278fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 279fcf5ef2aSThomas Huth target_ulong nip) 280fcf5ef2aSThomas Huth { 281fcf5ef2aSThomas Huth TCGv_i32 t0; 282fcf5ef2aSThomas Huth 283fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 284fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 285fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 286fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 287fcf5ef2aSThomas Huth ctx->exception = (excp); 288fcf5ef2aSThomas Huth } 289fcf5ef2aSThomas Huth 290*e150ac89SRoman Kapl /* 291*e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 292*e150ac89SRoman Kapl * SPR registers for this exception. 293*e150ac89SRoman Kapl * 294*e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 295*e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 2960e3bf489SRoman Kapl */ 297*e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 2980e3bf489SRoman Kapl { 2990e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3000e3bf489SRoman Kapl target_ulong dbsr = 0; 301*e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3020e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 303*e150ac89SRoman Kapl } else { 304*e150ac89SRoman Kapl /* Must have been branch */ 3050e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3060e3bf489SRoman Kapl } 3070e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3080e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3090e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3100e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3110e3bf489SRoman Kapl tcg_temp_free(t0); 3120e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3130e3bf489SRoman Kapl } else { 314*e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3150e3bf489SRoman Kapl } 3160e3bf489SRoman Kapl } 3170e3bf489SRoman Kapl 318fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 319fcf5ef2aSThomas Huth { 320fcf5ef2aSThomas Huth TCGv_i32 t0; 321fcf5ef2aSThomas Huth 322fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 323fcf5ef2aSThomas Huth * the faulting instruction 324fcf5ef2aSThomas Huth */ 325fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 326fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 327b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 328fcf5ef2aSThomas Huth } 329fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 330fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 331fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 332fcf5ef2aSThomas Huth } 333fcf5ef2aSThomas Huth 334fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 335fcf5ef2aSThomas Huth { 336fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 337fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 338fcf5ef2aSThomas Huth } 339fcf5ef2aSThomas Huth 340fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 341fcf5ef2aSThomas Huth { 342fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 343fcf5ef2aSThomas Huth } 344fcf5ef2aSThomas Huth 345fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 346fcf5ef2aSThomas Huth { 347fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 348fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 349fcf5ef2aSThomas Huth } 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth /* Stop translation */ 352fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 353fcf5ef2aSThomas Huth { 354b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 355fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 358fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 359fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 360fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 361fcf5ef2aSThomas Huth { 362fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 363fcf5ef2aSThomas Huth } 364fcf5ef2aSThomas Huth #endif 365fcf5ef2aSThomas Huth 366fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 367fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 368fcf5ef2aSThomas Huth 369fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 370fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 371fcf5ef2aSThomas Huth 372fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 373fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 374fcf5ef2aSThomas Huth 375fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 376fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 377fcf5ef2aSThomas Huth 378fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 379fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 380fcf5ef2aSThomas Huth 381fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 382fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 383fcf5ef2aSThomas Huth 384fcf5ef2aSThomas Huth typedef struct opcode_t { 385fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 386fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 387fcf5ef2aSThomas Huth unsigned char pad[4]; 388fcf5ef2aSThomas Huth #endif 389fcf5ef2aSThomas Huth opc_handler_t handler; 390fcf5ef2aSThomas Huth const char *oname; 391fcf5ef2aSThomas Huth } opcode_t; 392fcf5ef2aSThomas Huth 393fcf5ef2aSThomas Huth /* Helpers for priv. check */ 394fcf5ef2aSThomas Huth #define GEN_PRIV \ 395fcf5ef2aSThomas Huth do { \ 396fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 397fcf5ef2aSThomas Huth } while (0) 398fcf5ef2aSThomas Huth 399fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 400fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 401fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 402fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 403fcf5ef2aSThomas Huth #else 404fcf5ef2aSThomas Huth #define CHK_HV \ 405fcf5ef2aSThomas Huth do { \ 406fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 407fcf5ef2aSThomas Huth GEN_PRIV; \ 408fcf5ef2aSThomas Huth } \ 409fcf5ef2aSThomas Huth } while (0) 410fcf5ef2aSThomas Huth #define CHK_SV \ 411fcf5ef2aSThomas Huth do { \ 412fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 413fcf5ef2aSThomas Huth GEN_PRIV; \ 414fcf5ef2aSThomas Huth } \ 415fcf5ef2aSThomas Huth } while (0) 416fcf5ef2aSThomas Huth #define CHK_HVRM \ 417fcf5ef2aSThomas Huth do { \ 418fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 419fcf5ef2aSThomas Huth GEN_PRIV; \ 420fcf5ef2aSThomas Huth } \ 421fcf5ef2aSThomas Huth } while (0) 422fcf5ef2aSThomas Huth #endif 423fcf5ef2aSThomas Huth 424fcf5ef2aSThomas Huth #define CHK_NONE 425fcf5ef2aSThomas Huth 426fcf5ef2aSThomas Huth /*****************************************************************************/ 427fcf5ef2aSThomas Huth /* PowerPC instructions table */ 428fcf5ef2aSThomas Huth 429fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 430fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 431fcf5ef2aSThomas Huth { \ 432fcf5ef2aSThomas Huth .opc1 = op1, \ 433fcf5ef2aSThomas Huth .opc2 = op2, \ 434fcf5ef2aSThomas Huth .opc3 = op3, \ 435fcf5ef2aSThomas Huth .opc4 = 0xff, \ 436fcf5ef2aSThomas Huth .handler = { \ 437fcf5ef2aSThomas Huth .inval1 = invl, \ 438fcf5ef2aSThomas Huth .type = _typ, \ 439fcf5ef2aSThomas Huth .type2 = _typ2, \ 440fcf5ef2aSThomas Huth .handler = &gen_##name, \ 441fcf5ef2aSThomas Huth .oname = stringify(name), \ 442fcf5ef2aSThomas Huth }, \ 443fcf5ef2aSThomas Huth .oname = stringify(name), \ 444fcf5ef2aSThomas Huth } 445fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 446fcf5ef2aSThomas Huth { \ 447fcf5ef2aSThomas Huth .opc1 = op1, \ 448fcf5ef2aSThomas Huth .opc2 = op2, \ 449fcf5ef2aSThomas Huth .opc3 = op3, \ 450fcf5ef2aSThomas Huth .opc4 = 0xff, \ 451fcf5ef2aSThomas Huth .handler = { \ 452fcf5ef2aSThomas Huth .inval1 = invl1, \ 453fcf5ef2aSThomas Huth .inval2 = invl2, \ 454fcf5ef2aSThomas Huth .type = _typ, \ 455fcf5ef2aSThomas Huth .type2 = _typ2, \ 456fcf5ef2aSThomas Huth .handler = &gen_##name, \ 457fcf5ef2aSThomas Huth .oname = stringify(name), \ 458fcf5ef2aSThomas Huth }, \ 459fcf5ef2aSThomas Huth .oname = stringify(name), \ 460fcf5ef2aSThomas Huth } 461fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 462fcf5ef2aSThomas Huth { \ 463fcf5ef2aSThomas Huth .opc1 = op1, \ 464fcf5ef2aSThomas Huth .opc2 = op2, \ 465fcf5ef2aSThomas Huth .opc3 = op3, \ 466fcf5ef2aSThomas Huth .opc4 = 0xff, \ 467fcf5ef2aSThomas Huth .handler = { \ 468fcf5ef2aSThomas Huth .inval1 = invl, \ 469fcf5ef2aSThomas Huth .type = _typ, \ 470fcf5ef2aSThomas Huth .type2 = _typ2, \ 471fcf5ef2aSThomas Huth .handler = &gen_##name, \ 472fcf5ef2aSThomas Huth .oname = onam, \ 473fcf5ef2aSThomas Huth }, \ 474fcf5ef2aSThomas Huth .oname = onam, \ 475fcf5ef2aSThomas Huth } 476fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 477fcf5ef2aSThomas Huth { \ 478fcf5ef2aSThomas Huth .opc1 = op1, \ 479fcf5ef2aSThomas Huth .opc2 = op2, \ 480fcf5ef2aSThomas Huth .opc3 = op3, \ 481fcf5ef2aSThomas Huth .opc4 = op4, \ 482fcf5ef2aSThomas Huth .handler = { \ 483fcf5ef2aSThomas Huth .inval1 = invl, \ 484fcf5ef2aSThomas Huth .type = _typ, \ 485fcf5ef2aSThomas Huth .type2 = _typ2, \ 486fcf5ef2aSThomas Huth .handler = &gen_##name, \ 487fcf5ef2aSThomas Huth .oname = stringify(name), \ 488fcf5ef2aSThomas Huth }, \ 489fcf5ef2aSThomas Huth .oname = stringify(name), \ 490fcf5ef2aSThomas Huth } 491fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 492fcf5ef2aSThomas Huth { \ 493fcf5ef2aSThomas Huth .opc1 = op1, \ 494fcf5ef2aSThomas Huth .opc2 = op2, \ 495fcf5ef2aSThomas Huth .opc3 = op3, \ 496fcf5ef2aSThomas Huth .opc4 = op4, \ 497fcf5ef2aSThomas Huth .handler = { \ 498fcf5ef2aSThomas Huth .inval1 = invl, \ 499fcf5ef2aSThomas Huth .type = _typ, \ 500fcf5ef2aSThomas Huth .type2 = _typ2, \ 501fcf5ef2aSThomas Huth .handler = &gen_##name, \ 502fcf5ef2aSThomas Huth .oname = onam, \ 503fcf5ef2aSThomas Huth }, \ 504fcf5ef2aSThomas Huth .oname = onam, \ 505fcf5ef2aSThomas Huth } 506fcf5ef2aSThomas Huth #else 507fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 508fcf5ef2aSThomas Huth { \ 509fcf5ef2aSThomas Huth .opc1 = op1, \ 510fcf5ef2aSThomas Huth .opc2 = op2, \ 511fcf5ef2aSThomas Huth .opc3 = op3, \ 512fcf5ef2aSThomas Huth .opc4 = 0xff, \ 513fcf5ef2aSThomas Huth .handler = { \ 514fcf5ef2aSThomas Huth .inval1 = invl, \ 515fcf5ef2aSThomas Huth .type = _typ, \ 516fcf5ef2aSThomas Huth .type2 = _typ2, \ 517fcf5ef2aSThomas Huth .handler = &gen_##name, \ 518fcf5ef2aSThomas Huth }, \ 519fcf5ef2aSThomas Huth .oname = stringify(name), \ 520fcf5ef2aSThomas Huth } 521fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 522fcf5ef2aSThomas Huth { \ 523fcf5ef2aSThomas Huth .opc1 = op1, \ 524fcf5ef2aSThomas Huth .opc2 = op2, \ 525fcf5ef2aSThomas Huth .opc3 = op3, \ 526fcf5ef2aSThomas Huth .opc4 = 0xff, \ 527fcf5ef2aSThomas Huth .handler = { \ 528fcf5ef2aSThomas Huth .inval1 = invl1, \ 529fcf5ef2aSThomas Huth .inval2 = invl2, \ 530fcf5ef2aSThomas Huth .type = _typ, \ 531fcf5ef2aSThomas Huth .type2 = _typ2, \ 532fcf5ef2aSThomas Huth .handler = &gen_##name, \ 533fcf5ef2aSThomas Huth }, \ 534fcf5ef2aSThomas Huth .oname = stringify(name), \ 535fcf5ef2aSThomas Huth } 536fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 537fcf5ef2aSThomas Huth { \ 538fcf5ef2aSThomas Huth .opc1 = op1, \ 539fcf5ef2aSThomas Huth .opc2 = op2, \ 540fcf5ef2aSThomas Huth .opc3 = op3, \ 541fcf5ef2aSThomas Huth .opc4 = 0xff, \ 542fcf5ef2aSThomas Huth .handler = { \ 543fcf5ef2aSThomas Huth .inval1 = invl, \ 544fcf5ef2aSThomas Huth .type = _typ, \ 545fcf5ef2aSThomas Huth .type2 = _typ2, \ 546fcf5ef2aSThomas Huth .handler = &gen_##name, \ 547fcf5ef2aSThomas Huth }, \ 548fcf5ef2aSThomas Huth .oname = onam, \ 549fcf5ef2aSThomas Huth } 550fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 551fcf5ef2aSThomas Huth { \ 552fcf5ef2aSThomas Huth .opc1 = op1, \ 553fcf5ef2aSThomas Huth .opc2 = op2, \ 554fcf5ef2aSThomas Huth .opc3 = op3, \ 555fcf5ef2aSThomas Huth .opc4 = op4, \ 556fcf5ef2aSThomas Huth .handler = { \ 557fcf5ef2aSThomas Huth .inval1 = invl, \ 558fcf5ef2aSThomas Huth .type = _typ, \ 559fcf5ef2aSThomas Huth .type2 = _typ2, \ 560fcf5ef2aSThomas Huth .handler = &gen_##name, \ 561fcf5ef2aSThomas Huth }, \ 562fcf5ef2aSThomas Huth .oname = stringify(name), \ 563fcf5ef2aSThomas Huth } 564fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 565fcf5ef2aSThomas Huth { \ 566fcf5ef2aSThomas Huth .opc1 = op1, \ 567fcf5ef2aSThomas Huth .opc2 = op2, \ 568fcf5ef2aSThomas Huth .opc3 = op3, \ 569fcf5ef2aSThomas Huth .opc4 = op4, \ 570fcf5ef2aSThomas Huth .handler = { \ 571fcf5ef2aSThomas Huth .inval1 = invl, \ 572fcf5ef2aSThomas Huth .type = _typ, \ 573fcf5ef2aSThomas Huth .type2 = _typ2, \ 574fcf5ef2aSThomas Huth .handler = &gen_##name, \ 575fcf5ef2aSThomas Huth }, \ 576fcf5ef2aSThomas Huth .oname = onam, \ 577fcf5ef2aSThomas Huth } 578fcf5ef2aSThomas Huth #endif 579fcf5ef2aSThomas Huth 580fcf5ef2aSThomas Huth /* Invalid instruction */ 581fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 582fcf5ef2aSThomas Huth { 583fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 584fcf5ef2aSThomas Huth } 585fcf5ef2aSThomas Huth 586fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 587fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 588fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 589fcf5ef2aSThomas Huth .type = PPC_NONE, 590fcf5ef2aSThomas Huth .type2 = PPC_NONE, 591fcf5ef2aSThomas Huth .handler = gen_invalid, 592fcf5ef2aSThomas Huth }; 593fcf5ef2aSThomas Huth 594fcf5ef2aSThomas Huth /*** Integer comparison ***/ 595fcf5ef2aSThomas Huth 596fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 597fcf5ef2aSThomas Huth { 598fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 599b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 600b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 601fcf5ef2aSThomas Huth 602b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 603b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 604b62b3686Spbonzini@redhat.com tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0); 605b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 606b62b3686Spbonzini@redhat.com tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0); 607b62b3686Spbonzini@redhat.com 608b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 609fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 610b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 611fcf5ef2aSThomas Huth 612fcf5ef2aSThomas Huth tcg_temp_free(t0); 613b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 614b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 615fcf5ef2aSThomas Huth } 616fcf5ef2aSThomas Huth 617fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 618fcf5ef2aSThomas Huth { 619fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 620fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 621fcf5ef2aSThomas Huth tcg_temp_free(t0); 622fcf5ef2aSThomas Huth } 623fcf5ef2aSThomas Huth 624fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 625fcf5ef2aSThomas Huth { 626fcf5ef2aSThomas Huth TCGv t0, t1; 627fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 628fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 629fcf5ef2aSThomas Huth if (s) { 630fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 631fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 632fcf5ef2aSThomas Huth } else { 633fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 634fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 635fcf5ef2aSThomas Huth } 636fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 637fcf5ef2aSThomas Huth tcg_temp_free(t1); 638fcf5ef2aSThomas Huth tcg_temp_free(t0); 639fcf5ef2aSThomas Huth } 640fcf5ef2aSThomas Huth 641fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 642fcf5ef2aSThomas Huth { 643fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 644fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 645fcf5ef2aSThomas Huth tcg_temp_free(t0); 646fcf5ef2aSThomas Huth } 647fcf5ef2aSThomas Huth 648fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 649fcf5ef2aSThomas Huth { 650fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 651fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 652fcf5ef2aSThomas Huth } else { 653fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 654fcf5ef2aSThomas Huth } 655fcf5ef2aSThomas Huth } 656fcf5ef2aSThomas Huth 657fcf5ef2aSThomas Huth /* cmp */ 658fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 659fcf5ef2aSThomas Huth { 660fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 661fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 662fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 663fcf5ef2aSThomas Huth } else { 664fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 665fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 666fcf5ef2aSThomas Huth } 667fcf5ef2aSThomas Huth } 668fcf5ef2aSThomas Huth 669fcf5ef2aSThomas Huth /* cmpi */ 670fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 671fcf5ef2aSThomas Huth { 672fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 673fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 674fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 675fcf5ef2aSThomas Huth } else { 676fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 677fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 678fcf5ef2aSThomas Huth } 679fcf5ef2aSThomas Huth } 680fcf5ef2aSThomas Huth 681fcf5ef2aSThomas Huth /* cmpl */ 682fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 683fcf5ef2aSThomas Huth { 684fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 685fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 686fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 687fcf5ef2aSThomas Huth } else { 688fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 689fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 690fcf5ef2aSThomas Huth } 691fcf5ef2aSThomas Huth } 692fcf5ef2aSThomas Huth 693fcf5ef2aSThomas Huth /* cmpli */ 694fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 695fcf5ef2aSThomas Huth { 696fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 697fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 698fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 699fcf5ef2aSThomas Huth } else { 700fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 701fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 702fcf5ef2aSThomas Huth } 703fcf5ef2aSThomas Huth } 704fcf5ef2aSThomas Huth 705fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 706fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 707fcf5ef2aSThomas Huth { 708fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 709fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 710fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 711fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 712fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 713fcf5ef2aSThomas Huth 714fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 715fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 716fcf5ef2aSThomas Huth 717fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 718fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 719fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 720fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 721fcf5ef2aSThomas Huth 722fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 723fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 724fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 725fcf5ef2aSThomas Huth 726fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 727fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 728fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 729fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 730fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 731fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 732fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 733fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 734fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 735fcf5ef2aSThomas Huth } 736efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 737fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 738fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 739fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 740fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 741fcf5ef2aSThomas Huth } 742fcf5ef2aSThomas Huth 743fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 744fcf5ef2aSThomas Huth /* cmpeqb */ 745fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 746fcf5ef2aSThomas Huth { 747fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 748fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 749fcf5ef2aSThomas Huth } 750fcf5ef2aSThomas Huth #endif 751fcf5ef2aSThomas Huth 752fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 753fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 754fcf5ef2aSThomas Huth { 755fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 756fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 757fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 758fcf5ef2aSThomas Huth TCGv zr; 759fcf5ef2aSThomas Huth 760fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 761fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 762fcf5ef2aSThomas Huth 763fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 764fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 765fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 766fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 767fcf5ef2aSThomas Huth tcg_temp_free(zr); 768fcf5ef2aSThomas Huth tcg_temp_free(t0); 769fcf5ef2aSThomas Huth } 770fcf5ef2aSThomas Huth 771fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 772fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 773fcf5ef2aSThomas Huth { 774fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 775fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 776fcf5ef2aSThomas Huth } 777fcf5ef2aSThomas Huth 778fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 779fcf5ef2aSThomas Huth 780fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 781fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 782fcf5ef2aSThomas Huth { 783fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 784fcf5ef2aSThomas Huth 785fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 786fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 787fcf5ef2aSThomas Huth if (sub) { 788fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 789fcf5ef2aSThomas Huth } else { 790fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 791fcf5ef2aSThomas Huth } 792fcf5ef2aSThomas Huth tcg_temp_free(t0); 793fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 794dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 795dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 796dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 797fcf5ef2aSThomas Huth } 798dc0ad844SNikunj A Dadhania } else { 799dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 800dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 801dc0ad844SNikunj A Dadhania } 80238a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 803dc0ad844SNikunj A Dadhania } 804fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 805fcf5ef2aSThomas Huth } 806fcf5ef2aSThomas Huth 8076b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8086b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 8094c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 8106b10d008SNikunj A Dadhania { 8116b10d008SNikunj A Dadhania TCGv t0; 8126b10d008SNikunj A Dadhania 8136b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8146b10d008SNikunj A Dadhania return; 8156b10d008SNikunj A Dadhania } 8166b10d008SNikunj A Dadhania 8176b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 81833903d0aSNikunj A Dadhania if (sub) { 81933903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 82033903d0aSNikunj A Dadhania } else { 8216b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 82233903d0aSNikunj A Dadhania } 8236b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 8244c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 8256b10d008SNikunj A Dadhania tcg_temp_free(t0); 8266b10d008SNikunj A Dadhania } 8276b10d008SNikunj A Dadhania 828fcf5ef2aSThomas Huth /* Common add function */ 829fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 8304c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 8314c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 832fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 833fcf5ef2aSThomas Huth { 834fcf5ef2aSThomas Huth TCGv t0 = ret; 835fcf5ef2aSThomas Huth 836fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 837fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 838fcf5ef2aSThomas Huth } 839fcf5ef2aSThomas Huth 840fcf5ef2aSThomas Huth if (compute_ca) { 841fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 842fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 843fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 844fcf5ef2aSThomas Huth carry into bit 32. */ 845fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 846fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 847fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 848fcf5ef2aSThomas Huth if (add_ca) { 8494c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 850fcf5ef2aSThomas Huth } 8514c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 852fcf5ef2aSThomas Huth tcg_temp_free(t1); 8534c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 8546b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 8554c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 8566b10d008SNikunj A Dadhania } 857fcf5ef2aSThomas Huth } else { 858fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 859fcf5ef2aSThomas Huth if (add_ca) { 8604c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 8614c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 862fcf5ef2aSThomas Huth } else { 8634c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 864fcf5ef2aSThomas Huth } 8654c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 866fcf5ef2aSThomas Huth tcg_temp_free(zero); 867fcf5ef2aSThomas Huth } 868fcf5ef2aSThomas Huth } else { 869fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 870fcf5ef2aSThomas Huth if (add_ca) { 8714c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 872fcf5ef2aSThomas Huth } 873fcf5ef2aSThomas Huth } 874fcf5ef2aSThomas Huth 875fcf5ef2aSThomas Huth if (compute_ov) { 876fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 877fcf5ef2aSThomas Huth } 878fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 879fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 880fcf5ef2aSThomas Huth } 881fcf5ef2aSThomas Huth 88211f4e8f8SRichard Henderson if (t0 != ret) { 883fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 884fcf5ef2aSThomas Huth tcg_temp_free(t0); 885fcf5ef2aSThomas Huth } 886fcf5ef2aSThomas Huth } 887fcf5ef2aSThomas Huth /* Add functions with two operands */ 8884c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 889fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 890fcf5ef2aSThomas Huth { \ 891fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 892fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 8934c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 894fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 895fcf5ef2aSThomas Huth } 896fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 8974c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 898fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 899fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 900fcf5ef2aSThomas Huth { \ 901fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 902fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 903fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 9044c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 905fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 906fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 907fcf5ef2aSThomas Huth } 908fcf5ef2aSThomas Huth 909fcf5ef2aSThomas Huth /* add add. addo addo. */ 9104c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 9114c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 912fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 9134c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 9144c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 915fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 9164c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 9174c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 918fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 9194c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 9204c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 9214c5920afSSuraj Jitindar Singh /* addex */ 9224c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 923fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 9244c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 9254c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 926fcf5ef2aSThomas Huth /* addi */ 927fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 928fcf5ef2aSThomas Huth { 929fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 930fcf5ef2aSThomas Huth 931fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 932fcf5ef2aSThomas Huth /* li case */ 933fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 934fcf5ef2aSThomas Huth } else { 935fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 936fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 937fcf5ef2aSThomas Huth } 938fcf5ef2aSThomas Huth } 939fcf5ef2aSThomas Huth /* addic addic.*/ 940fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 941fcf5ef2aSThomas Huth { 942fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 943fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 9444c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 945fcf5ef2aSThomas Huth tcg_temp_free(c); 946fcf5ef2aSThomas Huth } 947fcf5ef2aSThomas Huth 948fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 949fcf5ef2aSThomas Huth { 950fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 951fcf5ef2aSThomas Huth } 952fcf5ef2aSThomas Huth 953fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 954fcf5ef2aSThomas Huth { 955fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 956fcf5ef2aSThomas Huth } 957fcf5ef2aSThomas Huth 958fcf5ef2aSThomas Huth /* addis */ 959fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 960fcf5ef2aSThomas Huth { 961fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 962fcf5ef2aSThomas Huth 963fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 964fcf5ef2aSThomas Huth /* lis case */ 965fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 966fcf5ef2aSThomas Huth } else { 967fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 968fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 969fcf5ef2aSThomas Huth } 970fcf5ef2aSThomas Huth } 971fcf5ef2aSThomas Huth 972fcf5ef2aSThomas Huth /* addpcis */ 973fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 974fcf5ef2aSThomas Huth { 975fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 976fcf5ef2aSThomas Huth 977b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 978fcf5ef2aSThomas Huth } 979fcf5ef2aSThomas Huth 980fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 981fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 982fcf5ef2aSThomas Huth { 983fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 984fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 985fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 986fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 987fcf5ef2aSThomas Huth 988fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 989fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 990fcf5ef2aSThomas Huth if (sign) { 991fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 992fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 993fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 994fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 995fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 996fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 997fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 998fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 999fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1000fcf5ef2aSThomas Huth } else { 1001fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1002fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1003fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1004fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1005fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1006fcf5ef2aSThomas Huth } 1007fcf5ef2aSThomas Huth if (compute_ov) { 1008fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1009c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1010c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1011c44027ffSNikunj A Dadhania } 1012fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1013fcf5ef2aSThomas Huth } 1014fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1015fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1016fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1017fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1018fcf5ef2aSThomas Huth 1019fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1020fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1021fcf5ef2aSThomas Huth } 1022fcf5ef2aSThomas Huth /* Div functions */ 1023fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1024fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1025fcf5ef2aSThomas Huth { \ 1026fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1027fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1028fcf5ef2aSThomas Huth sign, compute_ov); \ 1029fcf5ef2aSThomas Huth } 1030fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1031fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1032fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1033fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1034fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1035fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1036fcf5ef2aSThomas Huth 1037fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1038fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1039fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1040fcf5ef2aSThomas Huth { \ 1041fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1042fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1043fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1044fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1045fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1046fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1047fcf5ef2aSThomas Huth } \ 1048fcf5ef2aSThomas Huth } 1049fcf5ef2aSThomas Huth 1050fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1051fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1052fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1053fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1054fcf5ef2aSThomas Huth 1055fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1056fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1057fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1058fcf5ef2aSThomas Huth { 1059fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1060fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1061fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1062fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1063fcf5ef2aSThomas Huth 1064fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1065fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1066fcf5ef2aSThomas Huth if (sign) { 1067fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1068fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1069fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1070fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1071fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1072fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1073fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1074fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1075fcf5ef2aSThomas Huth } else { 1076fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1077fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1078fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1079fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1080fcf5ef2aSThomas Huth } 1081fcf5ef2aSThomas Huth if (compute_ov) { 1082fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1083c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1084c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1085c44027ffSNikunj A Dadhania } 1086fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1087fcf5ef2aSThomas Huth } 1088fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1089fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1090fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1091fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1092fcf5ef2aSThomas Huth 1093fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1094fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1095fcf5ef2aSThomas Huth } 1096fcf5ef2aSThomas Huth 1097fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1098fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1099fcf5ef2aSThomas Huth { \ 1100fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1101fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1102fcf5ef2aSThomas Huth sign, compute_ov); \ 1103fcf5ef2aSThomas Huth } 1104c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1105fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1106fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1107c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1108fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1109fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1110fcf5ef2aSThomas Huth 1111fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1112fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1113fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1114fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1115fcf5ef2aSThomas Huth #endif 1116fcf5ef2aSThomas Huth 1117fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1118fcf5ef2aSThomas Huth TCGv arg2, int sign) 1119fcf5ef2aSThomas Huth { 1120fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1121fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1122fcf5ef2aSThomas Huth 1123fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1124fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1125fcf5ef2aSThomas Huth if (sign) { 1126fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1127fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1128fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1129fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1130fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1131fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1132fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1133fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1134fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1135fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1136fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1137fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1138fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1139fcf5ef2aSThomas Huth } else { 1140fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1141fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1142fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1143fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1144fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1145fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1146fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1147fcf5ef2aSThomas Huth } 1148fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1149fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1150fcf5ef2aSThomas Huth } 1151fcf5ef2aSThomas Huth 1152fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1153fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1154fcf5ef2aSThomas Huth { \ 1155fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1156fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1157fcf5ef2aSThomas Huth sign); \ 1158fcf5ef2aSThomas Huth } 1159fcf5ef2aSThomas Huth 1160fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1161fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1162fcf5ef2aSThomas Huth 1163fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1164fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1165fcf5ef2aSThomas Huth TCGv arg2, int sign) 1166fcf5ef2aSThomas Huth { 1167fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1168fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1169fcf5ef2aSThomas Huth 1170fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1171fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1172fcf5ef2aSThomas Huth if (sign) { 1173fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1174fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1175fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1176fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1177fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1178fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1179fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1180fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1181fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1182fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1183fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1184fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1185fcf5ef2aSThomas Huth } else { 1186fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1187fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1188fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1189fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1190fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1191fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1192fcf5ef2aSThomas Huth } 1193fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1194fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1195fcf5ef2aSThomas Huth } 1196fcf5ef2aSThomas Huth 1197fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1198fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1199fcf5ef2aSThomas Huth { \ 1200fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1201fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1202fcf5ef2aSThomas Huth sign); \ 1203fcf5ef2aSThomas Huth } 1204fcf5ef2aSThomas Huth 1205fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1206fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1207fcf5ef2aSThomas Huth #endif 1208fcf5ef2aSThomas Huth 1209fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1210fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1211fcf5ef2aSThomas Huth { 1212fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1213fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1214fcf5ef2aSThomas Huth 1215fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1216fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1217fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1218fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1219fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1220fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1221fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1222fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1223fcf5ef2aSThomas Huth } 1224fcf5ef2aSThomas Huth 1225fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1226fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1227fcf5ef2aSThomas Huth { 1228fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1229fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1230fcf5ef2aSThomas Huth 1231fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1232fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1233fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1234fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1235fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1236fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1237fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1238fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1239fcf5ef2aSThomas Huth } 1240fcf5ef2aSThomas Huth 1241fcf5ef2aSThomas Huth /* mullw mullw. */ 1242fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1243fcf5ef2aSThomas Huth { 1244fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1245fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1246fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1247fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1248fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1249fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1250fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1251fcf5ef2aSThomas Huth tcg_temp_free(t0); 1252fcf5ef2aSThomas Huth tcg_temp_free(t1); 1253fcf5ef2aSThomas Huth #else 1254fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1255fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1256fcf5ef2aSThomas Huth #endif 1257fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1258fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1259fcf5ef2aSThomas Huth } 1260fcf5ef2aSThomas Huth 1261fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1262fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1263fcf5ef2aSThomas Huth { 1264fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1265fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1266fcf5ef2aSThomas Huth 1267fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1268fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1269fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1270fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1271fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1272fcf5ef2aSThomas Huth #else 1273fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1274fcf5ef2aSThomas Huth #endif 1275fcf5ef2aSThomas Huth 1276fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1277fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1278fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 127961aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 128061aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 128161aa9a69SNikunj A Dadhania } 1282fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1283fcf5ef2aSThomas Huth 1284fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1285fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1286fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1287fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1288fcf5ef2aSThomas Huth } 1289fcf5ef2aSThomas Huth 1290fcf5ef2aSThomas Huth /* mulli */ 1291fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1292fcf5ef2aSThomas Huth { 1293fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1294fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1295fcf5ef2aSThomas Huth } 1296fcf5ef2aSThomas Huth 1297fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1298fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1299fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1300fcf5ef2aSThomas Huth { 1301fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1302fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1303fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1304fcf5ef2aSThomas Huth tcg_temp_free(lo); 1305fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1306fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1307fcf5ef2aSThomas Huth } 1308fcf5ef2aSThomas Huth } 1309fcf5ef2aSThomas Huth 1310fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1311fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1312fcf5ef2aSThomas Huth { 1313fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1314fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1315fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1316fcf5ef2aSThomas Huth tcg_temp_free(lo); 1317fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1318fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1319fcf5ef2aSThomas Huth } 1320fcf5ef2aSThomas Huth } 1321fcf5ef2aSThomas Huth 1322fcf5ef2aSThomas Huth /* mulld mulld. */ 1323fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1324fcf5ef2aSThomas Huth { 1325fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1326fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1327fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1328fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1329fcf5ef2aSThomas Huth } 1330fcf5ef2aSThomas Huth 1331fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1332fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1333fcf5ef2aSThomas Huth { 1334fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1335fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1336fcf5ef2aSThomas Huth 1337fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1338fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1339fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1340fcf5ef2aSThomas Huth 1341fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1342fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 134361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 134461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 134561aa9a69SNikunj A Dadhania } 1346fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1347fcf5ef2aSThomas Huth 1348fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1349fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1350fcf5ef2aSThomas Huth 1351fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1352fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1353fcf5ef2aSThomas Huth } 1354fcf5ef2aSThomas Huth } 1355fcf5ef2aSThomas Huth #endif 1356fcf5ef2aSThomas Huth 1357fcf5ef2aSThomas Huth /* Common subf function */ 1358fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1359fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1360fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1361fcf5ef2aSThomas Huth { 1362fcf5ef2aSThomas Huth TCGv t0 = ret; 1363fcf5ef2aSThomas Huth 1364fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1365fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1366fcf5ef2aSThomas Huth } 1367fcf5ef2aSThomas Huth 1368fcf5ef2aSThomas Huth if (compute_ca) { 1369fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1370fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1371fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 1372fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 1373fcf5ef2aSThomas Huth carry into bit 32. */ 1374fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1375fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1376fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1377fcf5ef2aSThomas Huth if (add_ca) { 1378fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1379fcf5ef2aSThomas Huth } else { 1380fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1381fcf5ef2aSThomas Huth } 1382fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1383fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1384fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1385fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1386fcf5ef2aSThomas Huth tcg_temp_free(t1); 1387e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 138833903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 138933903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 139033903d0aSNikunj A Dadhania } 1391fcf5ef2aSThomas Huth } else if (add_ca) { 1392fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1393fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1394fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1395fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1396fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 13974c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1398fcf5ef2aSThomas Huth tcg_temp_free(zero); 1399fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1400fcf5ef2aSThomas Huth } else { 1401fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1402fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 14034c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1404fcf5ef2aSThomas Huth } 1405fcf5ef2aSThomas Huth } else if (add_ca) { 1406fcf5ef2aSThomas Huth /* Since we're ignoring carry-out, we can simplify the 1407fcf5ef2aSThomas Huth standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1408fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1409fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1410fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1411fcf5ef2aSThomas Huth } else { 1412fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1413fcf5ef2aSThomas Huth } 1414fcf5ef2aSThomas Huth 1415fcf5ef2aSThomas Huth if (compute_ov) { 1416fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1419fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1420fcf5ef2aSThomas Huth } 1421fcf5ef2aSThomas Huth 142211f4e8f8SRichard Henderson if (t0 != ret) { 1423fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1424fcf5ef2aSThomas Huth tcg_temp_free(t0); 1425fcf5ef2aSThomas Huth } 1426fcf5ef2aSThomas Huth } 1427fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1428fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1429fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1430fcf5ef2aSThomas Huth { \ 1431fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1432fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1433fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1434fcf5ef2aSThomas Huth } 1435fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1436fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1437fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1438fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1439fcf5ef2aSThomas Huth { \ 1440fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1441fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1442fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1443fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1444fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1445fcf5ef2aSThomas Huth } 1446fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1447fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1448fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1449fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1450fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1451fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1452fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1453fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1454fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1455fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1456fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1457fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1458fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1459fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1460fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1461fcf5ef2aSThomas Huth 1462fcf5ef2aSThomas Huth /* subfic */ 1463fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1464fcf5ef2aSThomas Huth { 1465fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1466fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1467fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1468fcf5ef2aSThomas Huth tcg_temp_free(c); 1469fcf5ef2aSThomas Huth } 1470fcf5ef2aSThomas Huth 1471fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1472fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1473fcf5ef2aSThomas Huth { 1474fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1475fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1476fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1477fcf5ef2aSThomas Huth tcg_temp_free(zero); 1478fcf5ef2aSThomas Huth } 1479fcf5ef2aSThomas Huth 1480fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1481fcf5ef2aSThomas Huth { 14821480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 14831480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 14841480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 14851480d71cSNikunj A Dadhania } 1486fcf5ef2aSThomas Huth } 1487fcf5ef2aSThomas Huth 1488fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1489fcf5ef2aSThomas Huth { 1490fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1491fcf5ef2aSThomas Huth } 1492fcf5ef2aSThomas Huth 1493fcf5ef2aSThomas Huth /*** Integer logical ***/ 1494fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1495fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1496fcf5ef2aSThomas Huth { \ 1497fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1498fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1499fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1500fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1501fcf5ef2aSThomas Huth } 1502fcf5ef2aSThomas Huth 1503fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1504fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1505fcf5ef2aSThomas Huth { \ 1506fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1507fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1508fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1509fcf5ef2aSThomas Huth } 1510fcf5ef2aSThomas Huth 1511fcf5ef2aSThomas Huth /* and & and. */ 1512fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1513fcf5ef2aSThomas Huth /* andc & andc. */ 1514fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1515fcf5ef2aSThomas Huth 1516fcf5ef2aSThomas Huth /* andi. */ 1517fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1518fcf5ef2aSThomas Huth { 1519fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1520fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1521fcf5ef2aSThomas Huth } 1522fcf5ef2aSThomas Huth 1523fcf5ef2aSThomas Huth /* andis. */ 1524fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1525fcf5ef2aSThomas Huth { 1526fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1527fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1528fcf5ef2aSThomas Huth } 1529fcf5ef2aSThomas Huth 1530fcf5ef2aSThomas Huth /* cntlzw */ 1531fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1532fcf5ef2aSThomas Huth { 15339b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15349b8514e5SRichard Henderson 15359b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15369b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15379b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15389b8514e5SRichard Henderson tcg_temp_free_i32(t); 15399b8514e5SRichard Henderson 1540fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1541fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1542fcf5ef2aSThomas Huth } 1543fcf5ef2aSThomas Huth 1544fcf5ef2aSThomas Huth /* cnttzw */ 1545fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1546fcf5ef2aSThomas Huth { 15479b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15489b8514e5SRichard Henderson 15499b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15509b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15519b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15529b8514e5SRichard Henderson tcg_temp_free_i32(t); 15539b8514e5SRichard Henderson 1554fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1555fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1556fcf5ef2aSThomas Huth } 1557fcf5ef2aSThomas Huth } 1558fcf5ef2aSThomas Huth 1559fcf5ef2aSThomas Huth /* eqv & eqv. */ 1560fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1561fcf5ef2aSThomas Huth /* extsb & extsb. */ 1562fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1563fcf5ef2aSThomas Huth /* extsh & extsh. */ 1564fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1565fcf5ef2aSThomas Huth /* nand & nand. */ 1566fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1567fcf5ef2aSThomas Huth /* nor & nor. */ 1568fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1569fcf5ef2aSThomas Huth 1570fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1571fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1572fcf5ef2aSThomas Huth { 1573fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1574fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1575fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1576fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1577fcf5ef2aSThomas Huth 1578fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1579b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1580fcf5ef2aSThomas Huth } 1581fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1582fcf5ef2aSThomas Huth 1583fcf5ef2aSThomas Huth /* or & or. */ 1584fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1585fcf5ef2aSThomas Huth { 1586fcf5ef2aSThomas Huth int rs, ra, rb; 1587fcf5ef2aSThomas Huth 1588fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1589fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1590fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1591fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1592fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1593fcf5ef2aSThomas Huth if (rs != rb) 1594fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1595fcf5ef2aSThomas Huth else 1596fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1597fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1598fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1599fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1600fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1601fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1602fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1603fcf5ef2aSThomas Huth int prio = 0; 1604fcf5ef2aSThomas Huth 1605fcf5ef2aSThomas Huth switch (rs) { 1606fcf5ef2aSThomas Huth case 1: 1607fcf5ef2aSThomas Huth /* Set process priority to low */ 1608fcf5ef2aSThomas Huth prio = 2; 1609fcf5ef2aSThomas Huth break; 1610fcf5ef2aSThomas Huth case 6: 1611fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1612fcf5ef2aSThomas Huth prio = 3; 1613fcf5ef2aSThomas Huth break; 1614fcf5ef2aSThomas Huth case 2: 1615fcf5ef2aSThomas Huth /* Set process priority to normal */ 1616fcf5ef2aSThomas Huth prio = 4; 1617fcf5ef2aSThomas Huth break; 1618fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1619fcf5ef2aSThomas Huth case 31: 1620fcf5ef2aSThomas Huth if (!ctx->pr) { 1621fcf5ef2aSThomas Huth /* Set process priority to very low */ 1622fcf5ef2aSThomas Huth prio = 1; 1623fcf5ef2aSThomas Huth } 1624fcf5ef2aSThomas Huth break; 1625fcf5ef2aSThomas Huth case 5: 1626fcf5ef2aSThomas Huth if (!ctx->pr) { 1627fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1628fcf5ef2aSThomas Huth prio = 5; 1629fcf5ef2aSThomas Huth } 1630fcf5ef2aSThomas Huth break; 1631fcf5ef2aSThomas Huth case 3: 1632fcf5ef2aSThomas Huth if (!ctx->pr) { 1633fcf5ef2aSThomas Huth /* Set process priority to high */ 1634fcf5ef2aSThomas Huth prio = 6; 1635fcf5ef2aSThomas Huth } 1636fcf5ef2aSThomas Huth break; 1637fcf5ef2aSThomas Huth case 7: 1638fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1639fcf5ef2aSThomas Huth /* Set process priority to very high */ 1640fcf5ef2aSThomas Huth prio = 7; 1641fcf5ef2aSThomas Huth } 1642fcf5ef2aSThomas Huth break; 1643fcf5ef2aSThomas Huth #endif 1644fcf5ef2aSThomas Huth default: 1645fcf5ef2aSThomas Huth break; 1646fcf5ef2aSThomas Huth } 1647fcf5ef2aSThomas Huth if (prio) { 1648fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1649fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1650fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1651fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1652fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1653fcf5ef2aSThomas Huth tcg_temp_free(t0); 1654fcf5ef2aSThomas Huth } 1655fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1656fcf5ef2aSThomas Huth /* Pause out of TCG otherwise spin loops with smt_low eat too much 1657fcf5ef2aSThomas Huth * CPU and the kernel hangs. This applies to all encodings other 1658fcf5ef2aSThomas Huth * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1659fcf5ef2aSThomas Huth * and all currently undefined. 1660fcf5ef2aSThomas Huth */ 1661fcf5ef2aSThomas Huth gen_pause(ctx); 1662fcf5ef2aSThomas Huth #endif 1663fcf5ef2aSThomas Huth #endif 1664fcf5ef2aSThomas Huth } 1665fcf5ef2aSThomas Huth } 1666fcf5ef2aSThomas Huth /* orc & orc. */ 1667fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1668fcf5ef2aSThomas Huth 1669fcf5ef2aSThomas Huth /* xor & xor. */ 1670fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1671fcf5ef2aSThomas Huth { 1672fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1673fcf5ef2aSThomas Huth if (rS(ctx->opcode) != rB(ctx->opcode)) 1674fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1675fcf5ef2aSThomas Huth else 1676fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1677fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1678fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1679fcf5ef2aSThomas Huth } 1680fcf5ef2aSThomas Huth 1681fcf5ef2aSThomas Huth /* ori */ 1682fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1683fcf5ef2aSThomas Huth { 1684fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1685fcf5ef2aSThomas Huth 1686fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1687fcf5ef2aSThomas Huth return; 1688fcf5ef2aSThomas Huth } 1689fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1690fcf5ef2aSThomas Huth } 1691fcf5ef2aSThomas Huth 1692fcf5ef2aSThomas Huth /* oris */ 1693fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1694fcf5ef2aSThomas Huth { 1695fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1696fcf5ef2aSThomas Huth 1697fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1698fcf5ef2aSThomas Huth /* NOP */ 1699fcf5ef2aSThomas Huth return; 1700fcf5ef2aSThomas Huth } 1701fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1702fcf5ef2aSThomas Huth } 1703fcf5ef2aSThomas Huth 1704fcf5ef2aSThomas Huth /* xori */ 1705fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1706fcf5ef2aSThomas Huth { 1707fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1708fcf5ef2aSThomas Huth 1709fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1710fcf5ef2aSThomas Huth /* NOP */ 1711fcf5ef2aSThomas Huth return; 1712fcf5ef2aSThomas Huth } 1713fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1714fcf5ef2aSThomas Huth } 1715fcf5ef2aSThomas Huth 1716fcf5ef2aSThomas Huth /* xoris */ 1717fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1718fcf5ef2aSThomas Huth { 1719fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1720fcf5ef2aSThomas Huth 1721fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1722fcf5ef2aSThomas Huth /* NOP */ 1723fcf5ef2aSThomas Huth return; 1724fcf5ef2aSThomas Huth } 1725fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1726fcf5ef2aSThomas Huth } 1727fcf5ef2aSThomas Huth 1728fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1729fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1730fcf5ef2aSThomas Huth { 1731fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1732fcf5ef2aSThomas Huth } 1733fcf5ef2aSThomas Huth 1734fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1735fcf5ef2aSThomas Huth { 173679770002SRichard Henderson #if defined(TARGET_PPC64) 1737fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 173879770002SRichard Henderson #else 173979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 174079770002SRichard Henderson #endif 1741fcf5ef2aSThomas Huth } 1742fcf5ef2aSThomas Huth 1743fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1744fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1745fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1746fcf5ef2aSThomas Huth { 174779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1748fcf5ef2aSThomas Huth } 1749fcf5ef2aSThomas Huth #endif 1750fcf5ef2aSThomas Huth 1751fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1752fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1753fcf5ef2aSThomas Huth { 1754fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1755fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1756fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1757fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1758fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1759fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1760fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1761fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1762fcf5ef2aSThomas Huth tcg_temp_free(t0); 1763fcf5ef2aSThomas Huth } 1764fcf5ef2aSThomas Huth 1765fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1766fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1767fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1768fcf5ef2aSThomas Huth { 1769fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1770fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1771fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1772fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1773fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1774fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1775fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1776fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1777fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1778fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1779fcf5ef2aSThomas Huth tcg_temp_free(t0); 1780fcf5ef2aSThomas Huth } 1781fcf5ef2aSThomas Huth #endif 1782fcf5ef2aSThomas Huth 1783fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1784fcf5ef2aSThomas Huth /* bpermd */ 1785fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1786fcf5ef2aSThomas Huth { 1787fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1788fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1789fcf5ef2aSThomas Huth } 1790fcf5ef2aSThomas Huth #endif 1791fcf5ef2aSThomas Huth 1792fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1793fcf5ef2aSThomas Huth /* extsw & extsw. */ 1794fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1795fcf5ef2aSThomas Huth 1796fcf5ef2aSThomas Huth /* cntlzd */ 1797fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1798fcf5ef2aSThomas Huth { 17999b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1800fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1801fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1802fcf5ef2aSThomas Huth } 1803fcf5ef2aSThomas Huth 1804fcf5ef2aSThomas Huth /* cnttzd */ 1805fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1806fcf5ef2aSThomas Huth { 18079b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1808fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1809fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1810fcf5ef2aSThomas Huth } 1811fcf5ef2aSThomas Huth } 1812fcf5ef2aSThomas Huth 1813fcf5ef2aSThomas Huth /* darn */ 1814fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1815fcf5ef2aSThomas Huth { 1816fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1817fcf5ef2aSThomas Huth 1818fcf5ef2aSThomas Huth if (l == 0) { 1819fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1820fcf5ef2aSThomas Huth } else if (l <= 2) { 1821fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1822fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1823fcf5ef2aSThomas Huth } else { 1824fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1825fcf5ef2aSThomas Huth } 1826fcf5ef2aSThomas Huth } 1827fcf5ef2aSThomas Huth #endif 1828fcf5ef2aSThomas Huth 1829fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1830fcf5ef2aSThomas Huth 1831fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1832fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1833fcf5ef2aSThomas Huth { 1834fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1835fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1836fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1837fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1838fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1839fcf5ef2aSThomas Huth 1840fcf5ef2aSThomas Huth if (sh == (31-me) && mb <= me) { 1841fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1842fcf5ef2aSThomas Huth } else { 1843fcf5ef2aSThomas Huth target_ulong mask; 1844fcf5ef2aSThomas Huth TCGv t1; 1845fcf5ef2aSThomas Huth 1846fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1847fcf5ef2aSThomas Huth mb += 32; 1848fcf5ef2aSThomas Huth me += 32; 1849fcf5ef2aSThomas Huth #endif 1850fcf5ef2aSThomas Huth mask = MASK(mb, me); 1851fcf5ef2aSThomas Huth 1852fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1853fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1854fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1855fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1856fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1857fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1858fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1859fcf5ef2aSThomas Huth } else { 1860fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1861fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1862fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1863fcf5ef2aSThomas Huth #else 1864fcf5ef2aSThomas Huth g_assert_not_reached(); 1865fcf5ef2aSThomas Huth #endif 1866fcf5ef2aSThomas Huth } 1867fcf5ef2aSThomas Huth 1868fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1869fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1870fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1871fcf5ef2aSThomas Huth tcg_temp_free(t1); 1872fcf5ef2aSThomas Huth } 1873fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1874fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1875fcf5ef2aSThomas Huth } 1876fcf5ef2aSThomas Huth } 1877fcf5ef2aSThomas Huth 1878fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1879fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1880fcf5ef2aSThomas Huth { 1881fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1882fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 18837b4d326fSRichard Henderson int sh = SH(ctx->opcode); 18847b4d326fSRichard Henderson int mb = MB(ctx->opcode); 18857b4d326fSRichard Henderson int me = ME(ctx->opcode); 18867b4d326fSRichard Henderson int len = me - mb + 1; 18877b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1888fcf5ef2aSThomas Huth 18897b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 18907b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 18917b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 18927b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1893fcf5ef2aSThomas Huth } else { 1894fcf5ef2aSThomas Huth target_ulong mask; 1895fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1896fcf5ef2aSThomas Huth mb += 32; 1897fcf5ef2aSThomas Huth me += 32; 1898fcf5ef2aSThomas Huth #endif 1899fcf5ef2aSThomas Huth mask = MASK(mb, me); 19007b4d326fSRichard Henderson if (sh == 0) { 19017b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 19027b4d326fSRichard Henderson } else if (mask <= 0xffffffffu) { 1903fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1904fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1905fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1906fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1907fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1908fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1909fcf5ef2aSThomas Huth } else { 1910fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1911fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1912fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1913fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1914fcf5ef2aSThomas Huth #else 1915fcf5ef2aSThomas Huth g_assert_not_reached(); 1916fcf5ef2aSThomas Huth #endif 1917fcf5ef2aSThomas Huth } 1918fcf5ef2aSThomas Huth } 1919fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1920fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1921fcf5ef2aSThomas Huth } 1922fcf5ef2aSThomas Huth } 1923fcf5ef2aSThomas Huth 1924fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1925fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1926fcf5ef2aSThomas Huth { 1927fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1928fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1929fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1930fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1931fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1932fcf5ef2aSThomas Huth target_ulong mask; 1933fcf5ef2aSThomas Huth 1934fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1935fcf5ef2aSThomas Huth mb += 32; 1936fcf5ef2aSThomas Huth me += 32; 1937fcf5ef2aSThomas Huth #endif 1938fcf5ef2aSThomas Huth mask = MASK(mb, me); 1939fcf5ef2aSThomas Huth 1940fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1941fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1942fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1943fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1944fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1945fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1946fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1947fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1948fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1949fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1950fcf5ef2aSThomas Huth } else { 1951fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1952fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1953fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1954fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1955fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1956fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1957fcf5ef2aSThomas Huth #else 1958fcf5ef2aSThomas Huth g_assert_not_reached(); 1959fcf5ef2aSThomas Huth #endif 1960fcf5ef2aSThomas Huth } 1961fcf5ef2aSThomas Huth 1962fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 1963fcf5ef2aSThomas Huth 1964fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1965fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1966fcf5ef2aSThomas Huth } 1967fcf5ef2aSThomas Huth } 1968fcf5ef2aSThomas Huth 1969fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1970fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 1971fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1972fcf5ef2aSThomas Huth { \ 1973fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 1974fcf5ef2aSThomas Huth } \ 1975fcf5ef2aSThomas Huth \ 1976fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1977fcf5ef2aSThomas Huth { \ 1978fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 1979fcf5ef2aSThomas Huth } 1980fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 1981fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1982fcf5ef2aSThomas Huth { \ 1983fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 1984fcf5ef2aSThomas Huth } \ 1985fcf5ef2aSThomas Huth \ 1986fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1987fcf5ef2aSThomas Huth { \ 1988fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 1989fcf5ef2aSThomas Huth } \ 1990fcf5ef2aSThomas Huth \ 1991fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 1992fcf5ef2aSThomas Huth { \ 1993fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 1994fcf5ef2aSThomas Huth } \ 1995fcf5ef2aSThomas Huth \ 1996fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 1997fcf5ef2aSThomas Huth { \ 1998fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 1999fcf5ef2aSThomas Huth } 2000fcf5ef2aSThomas Huth 2001fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2002fcf5ef2aSThomas Huth { 2003fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2004fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20057b4d326fSRichard Henderson int len = me - mb + 1; 20067b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2007fcf5ef2aSThomas Huth 20087b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20097b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20107b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20117b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2012fcf5ef2aSThomas Huth } else { 2013fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2014fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2015fcf5ef2aSThomas Huth } 2016fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2017fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2018fcf5ef2aSThomas Huth } 2019fcf5ef2aSThomas Huth } 2020fcf5ef2aSThomas Huth 2021fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2022fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2023fcf5ef2aSThomas Huth { 2024fcf5ef2aSThomas Huth uint32_t sh, mb; 2025fcf5ef2aSThomas Huth 2026fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2027fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2028fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2029fcf5ef2aSThomas Huth } 2030fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2031fcf5ef2aSThomas Huth 2032fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2033fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2034fcf5ef2aSThomas Huth { 2035fcf5ef2aSThomas Huth uint32_t sh, me; 2036fcf5ef2aSThomas Huth 2037fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2038fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2039fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2040fcf5ef2aSThomas Huth } 2041fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2042fcf5ef2aSThomas Huth 2043fcf5ef2aSThomas Huth /* rldic - rldic. */ 2044fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2045fcf5ef2aSThomas Huth { 2046fcf5ef2aSThomas Huth uint32_t sh, mb; 2047fcf5ef2aSThomas Huth 2048fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2049fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2050fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2051fcf5ef2aSThomas Huth } 2052fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2053fcf5ef2aSThomas Huth 2054fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2055fcf5ef2aSThomas Huth { 2056fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2057fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2058fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2059fcf5ef2aSThomas Huth TCGv t0; 2060fcf5ef2aSThomas Huth 2061fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2062fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2063fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2064fcf5ef2aSThomas Huth tcg_temp_free(t0); 2065fcf5ef2aSThomas Huth 2066fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2067fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2068fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2069fcf5ef2aSThomas Huth } 2070fcf5ef2aSThomas Huth } 2071fcf5ef2aSThomas Huth 2072fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2073fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2074fcf5ef2aSThomas Huth { 2075fcf5ef2aSThomas Huth uint32_t mb; 2076fcf5ef2aSThomas Huth 2077fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2078fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2079fcf5ef2aSThomas Huth } 2080fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2083fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2084fcf5ef2aSThomas Huth { 2085fcf5ef2aSThomas Huth uint32_t me; 2086fcf5ef2aSThomas Huth 2087fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2088fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2089fcf5ef2aSThomas Huth } 2090fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2091fcf5ef2aSThomas Huth 2092fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2093fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2094fcf5ef2aSThomas Huth { 2095fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2096fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2097fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2098fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2099fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2100fcf5ef2aSThomas Huth 2101fcf5ef2aSThomas Huth if (mb <= me) { 2102fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2103fcf5ef2aSThomas Huth } else { 2104fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2105fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2106fcf5ef2aSThomas Huth 2107fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2108fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2109fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2110fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2111fcf5ef2aSThomas Huth tcg_temp_free(t1); 2112fcf5ef2aSThomas Huth } 2113fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2114fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2115fcf5ef2aSThomas Huth } 2116fcf5ef2aSThomas Huth } 2117fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2118fcf5ef2aSThomas Huth #endif 2119fcf5ef2aSThomas Huth 2120fcf5ef2aSThomas Huth /*** Integer shift ***/ 2121fcf5ef2aSThomas Huth 2122fcf5ef2aSThomas Huth /* slw & slw. */ 2123fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2124fcf5ef2aSThomas Huth { 2125fcf5ef2aSThomas Huth TCGv t0, t1; 2126fcf5ef2aSThomas Huth 2127fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2128fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2129fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2130fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2131fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2132fcf5ef2aSThomas Huth #else 2133fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2134fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2135fcf5ef2aSThomas Huth #endif 2136fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2137fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2138fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2139fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2140fcf5ef2aSThomas Huth tcg_temp_free(t1); 2141fcf5ef2aSThomas Huth tcg_temp_free(t0); 2142fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2143fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2144fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2145fcf5ef2aSThomas Huth } 2146fcf5ef2aSThomas Huth 2147fcf5ef2aSThomas Huth /* sraw & sraw. */ 2148fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2149fcf5ef2aSThomas Huth { 2150fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2151fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2152fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2153fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2154fcf5ef2aSThomas Huth } 2155fcf5ef2aSThomas Huth 2156fcf5ef2aSThomas Huth /* srawi & srawi. */ 2157fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2158fcf5ef2aSThomas Huth { 2159fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2160fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2161fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2162fcf5ef2aSThomas Huth if (sh == 0) { 2163fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2164fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2165af1c259fSSandipan Das if (is_isa300(ctx)) { 2166af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2167af1c259fSSandipan Das } 2168fcf5ef2aSThomas Huth } else { 2169fcf5ef2aSThomas Huth TCGv t0; 2170fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2171fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2172fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2173fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2174fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2175fcf5ef2aSThomas Huth tcg_temp_free(t0); 2176fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2177af1c259fSSandipan Das if (is_isa300(ctx)) { 2178af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2179af1c259fSSandipan Das } 2180fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2181fcf5ef2aSThomas Huth } 2182fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2183fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2184fcf5ef2aSThomas Huth } 2185fcf5ef2aSThomas Huth } 2186fcf5ef2aSThomas Huth 2187fcf5ef2aSThomas Huth /* srw & srw. */ 2188fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2189fcf5ef2aSThomas Huth { 2190fcf5ef2aSThomas Huth TCGv t0, t1; 2191fcf5ef2aSThomas Huth 2192fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2193fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2194fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2195fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2196fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2197fcf5ef2aSThomas Huth #else 2198fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2199fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2200fcf5ef2aSThomas Huth #endif 2201fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2202fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2203fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2204fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2205fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2206fcf5ef2aSThomas Huth tcg_temp_free(t1); 2207fcf5ef2aSThomas Huth tcg_temp_free(t0); 2208fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2209fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2210fcf5ef2aSThomas Huth } 2211fcf5ef2aSThomas Huth 2212fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2213fcf5ef2aSThomas Huth /* sld & sld. */ 2214fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2215fcf5ef2aSThomas Huth { 2216fcf5ef2aSThomas Huth TCGv t0, t1; 2217fcf5ef2aSThomas Huth 2218fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2219fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2220fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2221fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2222fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2223fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2224fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2225fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2226fcf5ef2aSThomas Huth tcg_temp_free(t1); 2227fcf5ef2aSThomas Huth tcg_temp_free(t0); 2228fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2229fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2230fcf5ef2aSThomas Huth } 2231fcf5ef2aSThomas Huth 2232fcf5ef2aSThomas Huth /* srad & srad. */ 2233fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2234fcf5ef2aSThomas Huth { 2235fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2236fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2237fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2238fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2239fcf5ef2aSThomas Huth } 2240fcf5ef2aSThomas Huth /* sradi & sradi. */ 2241fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2242fcf5ef2aSThomas Huth { 2243fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2244fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2245fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2246fcf5ef2aSThomas Huth if (sh == 0) { 2247fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2248fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2249af1c259fSSandipan Das if (is_isa300(ctx)) { 2250af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2251af1c259fSSandipan Das } 2252fcf5ef2aSThomas Huth } else { 2253fcf5ef2aSThomas Huth TCGv t0; 2254fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2255fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2256fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2257fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2258fcf5ef2aSThomas Huth tcg_temp_free(t0); 2259fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2260af1c259fSSandipan Das if (is_isa300(ctx)) { 2261af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2262af1c259fSSandipan Das } 2263fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2264fcf5ef2aSThomas Huth } 2265fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2266fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2267fcf5ef2aSThomas Huth } 2268fcf5ef2aSThomas Huth } 2269fcf5ef2aSThomas Huth 2270fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2271fcf5ef2aSThomas Huth { 2272fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2273fcf5ef2aSThomas Huth } 2274fcf5ef2aSThomas Huth 2275fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2276fcf5ef2aSThomas Huth { 2277fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2278fcf5ef2aSThomas Huth } 2279fcf5ef2aSThomas Huth 2280fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2281fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2282fcf5ef2aSThomas Huth { 2283fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2284fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2285fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2286fcf5ef2aSThomas Huth 2287fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2288fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2289fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2290fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2291fcf5ef2aSThomas Huth } 2292fcf5ef2aSThomas Huth } 2293fcf5ef2aSThomas Huth 2294fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2295fcf5ef2aSThomas Huth { 2296fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2297fcf5ef2aSThomas Huth } 2298fcf5ef2aSThomas Huth 2299fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2300fcf5ef2aSThomas Huth { 2301fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2302fcf5ef2aSThomas Huth } 2303fcf5ef2aSThomas Huth 2304fcf5ef2aSThomas Huth /* srd & srd. */ 2305fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2306fcf5ef2aSThomas Huth { 2307fcf5ef2aSThomas Huth TCGv t0, t1; 2308fcf5ef2aSThomas Huth 2309fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2310fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2311fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2312fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2313fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2314fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2315fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2316fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2317fcf5ef2aSThomas Huth tcg_temp_free(t1); 2318fcf5ef2aSThomas Huth tcg_temp_free(t0); 2319fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2320fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2321fcf5ef2aSThomas Huth } 2322fcf5ef2aSThomas Huth #endif 2323fcf5ef2aSThomas Huth 2324fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2325fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2326fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2327fcf5ef2aSThomas Huth target_long maskl) 2328fcf5ef2aSThomas Huth { 2329fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2330fcf5ef2aSThomas Huth 2331fcf5ef2aSThomas Huth simm &= ~maskl; 2332fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2333fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2334fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2335fcf5ef2aSThomas Huth } 2336fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2337fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2338fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2339fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2340fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2341fcf5ef2aSThomas Huth } 2342fcf5ef2aSThomas Huth } else { 2343fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2344fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2345fcf5ef2aSThomas Huth } else { 2346fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2347fcf5ef2aSThomas Huth } 2348fcf5ef2aSThomas Huth } 2349fcf5ef2aSThomas Huth } 2350fcf5ef2aSThomas Huth 2351fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2352fcf5ef2aSThomas Huth { 2353fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2354fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2355fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2356fcf5ef2aSThomas Huth } else { 2357fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2358fcf5ef2aSThomas Huth } 2359fcf5ef2aSThomas Huth } else { 2360fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2361fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2362fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2363fcf5ef2aSThomas Huth } 2364fcf5ef2aSThomas Huth } 2365fcf5ef2aSThomas Huth } 2366fcf5ef2aSThomas Huth 2367fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2368fcf5ef2aSThomas Huth { 2369fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2370fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2371fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2372fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2373fcf5ef2aSThomas Huth } else { 2374fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2375fcf5ef2aSThomas Huth } 2376fcf5ef2aSThomas Huth } 2377fcf5ef2aSThomas Huth 2378fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2379fcf5ef2aSThomas Huth target_long val) 2380fcf5ef2aSThomas Huth { 2381fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2382fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2383fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth } 2386fcf5ef2aSThomas Huth 2387fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2388fcf5ef2aSThomas Huth { 2389fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2390fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2391fcf5ef2aSThomas Huth } 2392fcf5ef2aSThomas Huth 2393fcf5ef2aSThomas Huth /*** Integer load ***/ 2394fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2395fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2396fcf5ef2aSThomas Huth 2397fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2398fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2399fcf5ef2aSThomas Huth TCGv val, \ 2400fcf5ef2aSThomas Huth TCGv addr) \ 2401fcf5ef2aSThomas Huth { \ 2402fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2403fcf5ef2aSThomas Huth } 2404fcf5ef2aSThomas Huth 2405fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2406fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2407fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2408fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2409fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2410fcf5ef2aSThomas Huth 2411fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2412fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2413fcf5ef2aSThomas Huth 2414fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2415fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2416fcf5ef2aSThomas Huth TCGv_i64 val, \ 2417fcf5ef2aSThomas Huth TCGv addr) \ 2418fcf5ef2aSThomas Huth { \ 2419fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2420fcf5ef2aSThomas Huth } 2421fcf5ef2aSThomas Huth 2422fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2423fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2424fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2425fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2426fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2427fcf5ef2aSThomas Huth 2428fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2429fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2430fcf5ef2aSThomas Huth #endif 2431fcf5ef2aSThomas Huth 2432fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2433fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2434fcf5ef2aSThomas Huth TCGv val, \ 2435fcf5ef2aSThomas Huth TCGv addr) \ 2436fcf5ef2aSThomas Huth { \ 2437fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2438fcf5ef2aSThomas Huth } 2439fcf5ef2aSThomas Huth 2440fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2441fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2442fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2443fcf5ef2aSThomas Huth 2444fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2445fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2446fcf5ef2aSThomas Huth 2447fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2448fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2449fcf5ef2aSThomas Huth TCGv_i64 val, \ 2450fcf5ef2aSThomas Huth TCGv addr) \ 2451fcf5ef2aSThomas Huth { \ 2452fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2453fcf5ef2aSThomas Huth } 2454fcf5ef2aSThomas Huth 2455fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2456fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2457fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2458fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2459fcf5ef2aSThomas Huth 2460fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2461fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2462fcf5ef2aSThomas Huth #endif 2463fcf5ef2aSThomas Huth 2464fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2465fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2466fcf5ef2aSThomas Huth { \ 2467fcf5ef2aSThomas Huth TCGv EA; \ 2468fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2469fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2470fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2471fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2472fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2473fcf5ef2aSThomas Huth } 2474fcf5ef2aSThomas Huth 2475fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2476fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2477fcf5ef2aSThomas Huth { \ 2478fcf5ef2aSThomas Huth TCGv EA; \ 2479fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2480fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2481fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2482fcf5ef2aSThomas Huth return; \ 2483fcf5ef2aSThomas Huth } \ 2484fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2485fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2486fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2487fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2488fcf5ef2aSThomas Huth else \ 2489fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2490fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2491fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2492fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2493fcf5ef2aSThomas Huth } 2494fcf5ef2aSThomas Huth 2495fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2496fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2497fcf5ef2aSThomas Huth { \ 2498fcf5ef2aSThomas Huth TCGv EA; \ 2499fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2500fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2501fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2502fcf5ef2aSThomas Huth return; \ 2503fcf5ef2aSThomas Huth } \ 2504fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2505fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2506fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2507fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2508fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2509fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2510fcf5ef2aSThomas Huth } 2511fcf5ef2aSThomas Huth 2512fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2513fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2514fcf5ef2aSThomas Huth { \ 2515fcf5ef2aSThomas Huth TCGv EA; \ 2516fcf5ef2aSThomas Huth chk; \ 2517fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2518fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2519fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2520fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2521fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2522fcf5ef2aSThomas Huth } 2523fcf5ef2aSThomas Huth 2524fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2525fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2528fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2529fcf5ef2aSThomas Huth 2530fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2531fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2532fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2533fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2534fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2535fcf5ef2aSThomas Huth 2536fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2537fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2538fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2539fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2540fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2541fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2542fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2543fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 254450728199SRoman Kapl 254550728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 254650728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 254750728199SRoman Kapl { \ 254850728199SRoman Kapl TCGv EA; \ 254950728199SRoman Kapl CHK_SV; \ 255050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 255150728199SRoman Kapl EA = tcg_temp_new(); \ 255250728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 255350728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 255450728199SRoman Kapl tcg_temp_free(EA); \ 255550728199SRoman Kapl } 255650728199SRoman Kapl 255750728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 255850728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 255950728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 256050728199SRoman Kapl #if defined(TARGET_PPC64) 256150728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 256250728199SRoman Kapl #endif 256350728199SRoman Kapl 2564fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2565fcf5ef2aSThomas Huth /* lwaux */ 2566fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2567fcf5ef2aSThomas Huth /* lwax */ 2568fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2569fcf5ef2aSThomas Huth /* ldux */ 2570fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2571fcf5ef2aSThomas Huth /* ldx */ 2572fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2573fcf5ef2aSThomas Huth 2574fcf5ef2aSThomas Huth /* CI load/store variants */ 2575fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2576fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2577fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2578fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2579fcf5ef2aSThomas Huth 2580fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2581fcf5ef2aSThomas Huth { 2582fcf5ef2aSThomas Huth TCGv EA; 2583fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2584fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2585fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2586fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2587fcf5ef2aSThomas Huth return; 2588fcf5ef2aSThomas Huth } 2589fcf5ef2aSThomas Huth } 2590fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2591fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2592fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2593fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2594fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2595fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2596fcf5ef2aSThomas Huth } else { 2597fcf5ef2aSThomas Huth /* ld - ldu */ 2598fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2599fcf5ef2aSThomas Huth } 2600fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2601fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2602fcf5ef2aSThomas Huth tcg_temp_free(EA); 2603fcf5ef2aSThomas Huth } 2604fcf5ef2aSThomas Huth 2605fcf5ef2aSThomas Huth /* lq */ 2606fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2607fcf5ef2aSThomas Huth { 2608fcf5ef2aSThomas Huth int ra, rd; 260994bf2658SRichard Henderson TCGv EA, hi, lo; 2610fcf5ef2aSThomas Huth 2611fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2612fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2613fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2614fcf5ef2aSThomas Huth 2615fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2616fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2617fcf5ef2aSThomas Huth return; 2618fcf5ef2aSThomas Huth } 2619fcf5ef2aSThomas Huth 2620fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2621fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2622fcf5ef2aSThomas Huth return; 2623fcf5ef2aSThomas Huth } 2624fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2625fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2626fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2627fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2628fcf5ef2aSThomas Huth return; 2629fcf5ef2aSThomas Huth } 2630fcf5ef2aSThomas Huth 2631fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2632fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2633fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2634fcf5ef2aSThomas Huth 263594bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 263694bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 263794bf2658SRichard Henderson hi = cpu_gpr[rd]; 263894bf2658SRichard Henderson 263994bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2640f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 264194bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 264294bf2658SRichard Henderson if (ctx->le_mode) { 264394bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 264494bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2645fcf5ef2aSThomas Huth } else { 264694bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 264794bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 264894bf2658SRichard Henderson } 264994bf2658SRichard Henderson tcg_temp_free_i32(oi); 265094bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2651f34ec0f6SRichard Henderson } else { 265294bf2658SRichard Henderson /* Restart with exclusive lock. */ 265394bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 265494bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2655f34ec0f6SRichard Henderson } 265694bf2658SRichard Henderson } else if (ctx->le_mode) { 265794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2658fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 265994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 266094bf2658SRichard Henderson } else { 266194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 266294bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 266394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2664fcf5ef2aSThomas Huth } 2665fcf5ef2aSThomas Huth tcg_temp_free(EA); 2666fcf5ef2aSThomas Huth } 2667fcf5ef2aSThomas Huth #endif 2668fcf5ef2aSThomas Huth 2669fcf5ef2aSThomas Huth /*** Integer store ***/ 2670fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2671fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2672fcf5ef2aSThomas Huth { \ 2673fcf5ef2aSThomas Huth TCGv EA; \ 2674fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2675fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2676fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2677fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2678fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2679fcf5ef2aSThomas Huth } 2680fcf5ef2aSThomas Huth 2681fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2682fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2683fcf5ef2aSThomas Huth { \ 2684fcf5ef2aSThomas Huth TCGv EA; \ 2685fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2686fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2687fcf5ef2aSThomas Huth return; \ 2688fcf5ef2aSThomas Huth } \ 2689fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2690fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2691fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2692fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2693fcf5ef2aSThomas Huth else \ 2694fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2695fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2696fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2697fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2698fcf5ef2aSThomas Huth } 2699fcf5ef2aSThomas Huth 2700fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2701fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2702fcf5ef2aSThomas Huth { \ 2703fcf5ef2aSThomas Huth TCGv EA; \ 2704fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2705fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2706fcf5ef2aSThomas Huth return; \ 2707fcf5ef2aSThomas Huth } \ 2708fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2709fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2710fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2711fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2712fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2713fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2714fcf5ef2aSThomas Huth } 2715fcf5ef2aSThomas Huth 2716fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2717fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2718fcf5ef2aSThomas Huth { \ 2719fcf5ef2aSThomas Huth TCGv EA; \ 2720fcf5ef2aSThomas Huth chk; \ 2721fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2722fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2723fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2724fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2725fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2726fcf5ef2aSThomas Huth } 2727fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2728fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2729fcf5ef2aSThomas Huth 2730fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2731fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2732fcf5ef2aSThomas Huth 2733fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2734fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2735fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2736fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2737fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2738fcf5ef2aSThomas Huth 2739fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2740fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2741fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2742fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2743fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2744fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 274550728199SRoman Kapl 274650728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 274750728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 274850728199SRoman Kapl { \ 274950728199SRoman Kapl TCGv EA; \ 275050728199SRoman Kapl CHK_SV; \ 275150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 275250728199SRoman Kapl EA = tcg_temp_new(); \ 275350728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 275450728199SRoman Kapl tcg_gen_qemu_st_tl( \ 275550728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 275650728199SRoman Kapl tcg_temp_free(EA); \ 275750728199SRoman Kapl } 275850728199SRoman Kapl 275950728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 276050728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 276150728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 276250728199SRoman Kapl #if defined(TARGET_PPC64) 276350728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 276450728199SRoman Kapl #endif 276550728199SRoman Kapl 2766fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2767fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2768fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2769fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2770fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2771fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2772fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2773fcf5ef2aSThomas Huth 2774fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2775fcf5ef2aSThomas Huth { 2776fcf5ef2aSThomas Huth int rs; 2777fcf5ef2aSThomas Huth TCGv EA; 2778fcf5ef2aSThomas Huth 2779fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2780fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2781fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2782fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2783f89ced5fSRichard Henderson TCGv hi, lo; 2784fcf5ef2aSThomas Huth 2785fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2786fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2787fcf5ef2aSThomas Huth } 2788fcf5ef2aSThomas Huth 2789fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2790fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2791fcf5ef2aSThomas Huth return; 2792fcf5ef2aSThomas Huth } 2793fcf5ef2aSThomas Huth 2794fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2795fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2796fcf5ef2aSThomas Huth return; 2797fcf5ef2aSThomas Huth } 2798fcf5ef2aSThomas Huth 2799fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2800fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2801fcf5ef2aSThomas Huth return; 2802fcf5ef2aSThomas Huth } 2803fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2804fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2805fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2806fcf5ef2aSThomas Huth 2807f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 2808f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 2809f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 2810f89ced5fSRichard Henderson 2811f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2812f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 2813f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 2814f89ced5fSRichard Henderson if (ctx->le_mode) { 2815f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2816f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2817fcf5ef2aSThomas Huth } else { 2818f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2819f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2820f89ced5fSRichard Henderson } 2821f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 2822f34ec0f6SRichard Henderson } else { 2823f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 2824f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 2825f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2826f34ec0f6SRichard Henderson } 2827f89ced5fSRichard Henderson } else if (ctx->le_mode) { 2828f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2829fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2830f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2831f89ced5fSRichard Henderson } else { 2832f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2833f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 2834f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2835fcf5ef2aSThomas Huth } 2836fcf5ef2aSThomas Huth tcg_temp_free(EA); 2837fcf5ef2aSThomas Huth } else { 2838fcf5ef2aSThomas Huth /* std / stdu */ 2839fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2840fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2841fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2842fcf5ef2aSThomas Huth return; 2843fcf5ef2aSThomas Huth } 2844fcf5ef2aSThomas Huth } 2845fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2846fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2847fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2848fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2849fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2850fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2851fcf5ef2aSThomas Huth tcg_temp_free(EA); 2852fcf5ef2aSThomas Huth } 2853fcf5ef2aSThomas Huth } 2854fcf5ef2aSThomas Huth #endif 2855fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2856fcf5ef2aSThomas Huth 2857fcf5ef2aSThomas Huth /* lhbrx */ 2858fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2859fcf5ef2aSThomas Huth 2860fcf5ef2aSThomas Huth /* lwbrx */ 2861fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2862fcf5ef2aSThomas Huth 2863fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2864fcf5ef2aSThomas Huth /* ldbrx */ 2865fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2866fcf5ef2aSThomas Huth /* stdbrx */ 2867fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2868fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2869fcf5ef2aSThomas Huth 2870fcf5ef2aSThomas Huth /* sthbrx */ 2871fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2872fcf5ef2aSThomas Huth /* stwbrx */ 2873fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2874fcf5ef2aSThomas Huth 2875fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2876fcf5ef2aSThomas Huth 2877fcf5ef2aSThomas Huth /* lmw */ 2878fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2879fcf5ef2aSThomas Huth { 2880fcf5ef2aSThomas Huth TCGv t0; 2881fcf5ef2aSThomas Huth TCGv_i32 t1; 2882fcf5ef2aSThomas Huth 2883fcf5ef2aSThomas Huth if (ctx->le_mode) { 2884fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2885fcf5ef2aSThomas Huth return; 2886fcf5ef2aSThomas Huth } 2887fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2888fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2889fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2890fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2891fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2892fcf5ef2aSThomas Huth tcg_temp_free(t0); 2893fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2894fcf5ef2aSThomas Huth } 2895fcf5ef2aSThomas Huth 2896fcf5ef2aSThomas Huth /* stmw */ 2897fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2898fcf5ef2aSThomas Huth { 2899fcf5ef2aSThomas Huth TCGv t0; 2900fcf5ef2aSThomas Huth TCGv_i32 t1; 2901fcf5ef2aSThomas Huth 2902fcf5ef2aSThomas Huth if (ctx->le_mode) { 2903fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2904fcf5ef2aSThomas Huth return; 2905fcf5ef2aSThomas Huth } 2906fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2907fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2908fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2909fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2910fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2911fcf5ef2aSThomas Huth tcg_temp_free(t0); 2912fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2913fcf5ef2aSThomas Huth } 2914fcf5ef2aSThomas Huth 2915fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2916fcf5ef2aSThomas Huth 2917fcf5ef2aSThomas Huth /* lswi */ 2918fcf5ef2aSThomas Huth /* PowerPC32 specification says we must generate an exception if 2919fcf5ef2aSThomas Huth * rA is in the range of registers to be loaded. 2920fcf5ef2aSThomas Huth * In an other hand, IBM says this is valid, but rA won't be loaded. 2921fcf5ef2aSThomas Huth * For now, I'll follow the spec... 2922fcf5ef2aSThomas Huth */ 2923fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2924fcf5ef2aSThomas Huth { 2925fcf5ef2aSThomas Huth TCGv t0; 2926fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2927fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2928fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2929fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2930fcf5ef2aSThomas Huth int nr; 2931fcf5ef2aSThomas Huth 2932fcf5ef2aSThomas Huth if (ctx->le_mode) { 2933fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2934fcf5ef2aSThomas Huth return; 2935fcf5ef2aSThomas Huth } 2936fcf5ef2aSThomas Huth if (nb == 0) 2937fcf5ef2aSThomas Huth nb = 32; 2938f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 2939fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2940fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2941fcf5ef2aSThomas Huth return; 2942fcf5ef2aSThomas Huth } 2943fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2944fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2945fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2946fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2947fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 2948fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 2949fcf5ef2aSThomas Huth tcg_temp_free(t0); 2950fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2951fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2952fcf5ef2aSThomas Huth } 2953fcf5ef2aSThomas Huth 2954fcf5ef2aSThomas Huth /* lswx */ 2955fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 2956fcf5ef2aSThomas Huth { 2957fcf5ef2aSThomas Huth TCGv t0; 2958fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 2959fcf5ef2aSThomas Huth 2960fcf5ef2aSThomas Huth if (ctx->le_mode) { 2961fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2962fcf5ef2aSThomas Huth return; 2963fcf5ef2aSThomas Huth } 2964fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2965fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2966fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2967fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2968fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 2969fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 2970fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2971fcf5ef2aSThomas Huth tcg_temp_free(t0); 2972fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2973fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2974fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2975fcf5ef2aSThomas Huth } 2976fcf5ef2aSThomas Huth 2977fcf5ef2aSThomas Huth /* stswi */ 2978fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 2979fcf5ef2aSThomas Huth { 2980fcf5ef2aSThomas Huth TCGv t0; 2981fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2982fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2983fcf5ef2aSThomas Huth 2984fcf5ef2aSThomas Huth if (ctx->le_mode) { 2985fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2986fcf5ef2aSThomas Huth return; 2987fcf5ef2aSThomas Huth } 2988fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2989fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2990fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2991fcf5ef2aSThomas Huth if (nb == 0) 2992fcf5ef2aSThomas Huth nb = 32; 2993fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2994fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2995fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2996fcf5ef2aSThomas Huth tcg_temp_free(t0); 2997fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2998fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2999fcf5ef2aSThomas Huth } 3000fcf5ef2aSThomas Huth 3001fcf5ef2aSThomas Huth /* stswx */ 3002fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3003fcf5ef2aSThomas Huth { 3004fcf5ef2aSThomas Huth TCGv t0; 3005fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3006fcf5ef2aSThomas Huth 3007fcf5ef2aSThomas Huth if (ctx->le_mode) { 3008fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3009fcf5ef2aSThomas Huth return; 3010fcf5ef2aSThomas Huth } 3011fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3012fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3013fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3014fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3015fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3016fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3017fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3018fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3019fcf5ef2aSThomas Huth tcg_temp_free(t0); 3020fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3021fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3022fcf5ef2aSThomas Huth } 3023fcf5ef2aSThomas Huth 3024fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3025fcf5ef2aSThomas Huth /* eieio */ 3026fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3027fcf5ef2aSThomas Huth { 3028c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3029c8fd8373SCédric Le Goater 3030c8fd8373SCédric Le Goater /* 3031c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3032c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3033c8fd8373SCédric Le Goater */ 3034c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3035c8fd8373SCédric Le Goater /* 3036c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3037c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3038c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3039c8fd8373SCédric Le Goater * complain to the user. 3040c8fd8373SCédric Le Goater */ 3041c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3042c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3043c8fd8373SCédric Le Goater TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3044c8fd8373SCédric Le Goater } else { 3045c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3046c8fd8373SCédric Le Goater } 3047c8fd8373SCédric Le Goater } 3048c8fd8373SCédric Le Goater 3049c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3050fcf5ef2aSThomas Huth } 3051fcf5ef2aSThomas Huth 3052fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3053fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3054fcf5ef2aSThomas Huth { 3055fcf5ef2aSThomas Huth TCGv_i32 t; 3056fcf5ef2aSThomas Huth TCGLabel *l; 3057fcf5ef2aSThomas Huth 3058fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3059fcf5ef2aSThomas Huth return; 3060fcf5ef2aSThomas Huth } 3061fcf5ef2aSThomas Huth l = gen_new_label(); 3062fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3063fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3064fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3065fcf5ef2aSThomas Huth if (global) { 3066fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3067fcf5ef2aSThomas Huth } else { 3068fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3069fcf5ef2aSThomas Huth } 3070fcf5ef2aSThomas Huth gen_set_label(l); 3071fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3072fcf5ef2aSThomas Huth } 3073fcf5ef2aSThomas Huth #else 3074fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3075fcf5ef2aSThomas Huth #endif 3076fcf5ef2aSThomas Huth 3077fcf5ef2aSThomas Huth /* isync */ 3078fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3079fcf5ef2aSThomas Huth { 3080fcf5ef2aSThomas Huth /* 3081fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3082fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3083fcf5ef2aSThomas Huth */ 3084fcf5ef2aSThomas Huth if (!ctx->pr) { 3085fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3086fcf5ef2aSThomas Huth } 30874771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3088fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3089fcf5ef2aSThomas Huth } 3090fcf5ef2aSThomas Huth 3091fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3092fcf5ef2aSThomas Huth 30932a4e6c1bSRichard Henderson static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) 30942a4e6c1bSRichard Henderson { 30952a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 30962a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 30972a4e6c1bSRichard Henderson 30982a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 30992a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 31002a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 31012a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 31022a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 31032a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 31042a4e6c1bSRichard Henderson tcg_temp_free(t0); 31052a4e6c1bSRichard Henderson } 31062a4e6c1bSRichard Henderson 3107fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3108fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3109fcf5ef2aSThomas Huth { \ 31102a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3111fcf5ef2aSThomas Huth } 3112fcf5ef2aSThomas Huth 3113fcf5ef2aSThomas Huth /* lwarx */ 3114fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3115fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3116fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3117fcf5ef2aSThomas Huth 311820923c1dSRichard Henderson static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, 311920923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 312020923c1dSRichard Henderson { 312120923c1dSRichard Henderson TCGv t = tcg_temp_new(); 312220923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 312320923c1dSRichard Henderson TCGv u = tcg_temp_new(); 312420923c1dSRichard Henderson 312520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 312620923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 312720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 312820923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 312920923c1dSRichard Henderson 313020923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 313120923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 313220923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 313320923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 313420923c1dSRichard Henderson 313520923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 313620923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 313720923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 313820923c1dSRichard Henderson 313920923c1dSRichard Henderson tcg_temp_free(t); 314020923c1dSRichard Henderson tcg_temp_free(t2); 314120923c1dSRichard Henderson tcg_temp_free(u); 314220923c1dSRichard Henderson } 314320923c1dSRichard Henderson 314420ba8504SRichard Henderson static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) 314520ba8504SRichard Henderson { 314620ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 314720ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 314820923c1dSRichard Henderson int rt = rD(ctx->opcode); 314920923c1dSRichard Henderson bool need_serial; 315020ba8504SRichard Henderson TCGv src, dst; 315120ba8504SRichard Henderson 315220ba8504SRichard Henderson gen_addr_register(ctx, EA); 315320923c1dSRichard Henderson dst = cpu_gpr[rt]; 315420923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 315520ba8504SRichard Henderson 315620923c1dSRichard Henderson need_serial = false; 315720ba8504SRichard Henderson memop |= MO_ALIGN; 315820ba8504SRichard Henderson switch (gpr_FC) { 315920ba8504SRichard Henderson case 0: /* Fetch and add */ 316020ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 316120ba8504SRichard Henderson break; 316220ba8504SRichard Henderson case 1: /* Fetch and xor */ 316320ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 316420ba8504SRichard Henderson break; 316520ba8504SRichard Henderson case 2: /* Fetch and or */ 316620ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 316720ba8504SRichard Henderson break; 316820ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 316920ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 317020ba8504SRichard Henderson break; 3171b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3172b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3173b8ce0f86SRichard Henderson break; 3174b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3175b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3176b8ce0f86SRichard Henderson break; 3177b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3178b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3179b8ce0f86SRichard Henderson break; 3180b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3181b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3182b8ce0f86SRichard Henderson break; 318320ba8504SRichard Henderson case 8: /* Swap */ 318420ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 318520ba8504SRichard Henderson break; 318620923c1dSRichard Henderson 318720923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 318820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 318920923c1dSRichard Henderson need_serial = true; 319020923c1dSRichard Henderson } else { 319120923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 319220923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 319320923c1dSRichard Henderson 319420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 319520923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 319620923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 319720923c1dSRichard Henderson } else { 319820923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 319920923c1dSRichard Henderson } 320020923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 320120923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 320220923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 320320923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 320420923c1dSRichard Henderson 320520923c1dSRichard Henderson tcg_temp_free(t0); 320620923c1dSRichard Henderson tcg_temp_free(t1); 320720923c1dSRichard Henderson } 320820ba8504SRichard Henderson break; 320920923c1dSRichard Henderson 321020923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 321120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 321220923c1dSRichard Henderson need_serial = true; 321320923c1dSRichard Henderson } else { 321420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 321520923c1dSRichard Henderson } 321620923c1dSRichard Henderson break; 321720923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 321820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 321920923c1dSRichard Henderson need_serial = true; 322020923c1dSRichard Henderson } else { 322120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 322220923c1dSRichard Henderson } 322320923c1dSRichard Henderson break; 322420923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 322520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 322620923c1dSRichard Henderson need_serial = true; 322720923c1dSRichard Henderson } else { 322820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 322920923c1dSRichard Henderson } 323020923c1dSRichard Henderson break; 323120923c1dSRichard Henderson 323220ba8504SRichard Henderson default: 323320ba8504SRichard Henderson /* invoke data storage error handler */ 323420ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 323520ba8504SRichard Henderson } 323620ba8504SRichard Henderson tcg_temp_free(EA); 323720923c1dSRichard Henderson 323820923c1dSRichard Henderson if (need_serial) { 323920923c1dSRichard Henderson /* Restart with exclusive lock. */ 324020923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 324120923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 324220923c1dSRichard Henderson } 3243a68a6146SBalamuruhan S } 3244a68a6146SBalamuruhan S 324520ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 324620ba8504SRichard Henderson { 324720ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 324820ba8504SRichard Henderson } 324920ba8504SRichard Henderson 325020ba8504SRichard Henderson #ifdef TARGET_PPC64 325120ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 325220ba8504SRichard Henderson { 325320ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 325420ba8504SRichard Henderson } 3255a68a6146SBalamuruhan S #endif 3256a68a6146SBalamuruhan S 32579deb041cSRichard Henderson static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) 32589deb041cSRichard Henderson { 32599deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 32609deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 32619deb041cSRichard Henderson TCGv src, discard; 32629deb041cSRichard Henderson 32639deb041cSRichard Henderson gen_addr_register(ctx, EA); 32649deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 32659deb041cSRichard Henderson discard = tcg_temp_new(); 32669deb041cSRichard Henderson 32679deb041cSRichard Henderson memop |= MO_ALIGN; 32689deb041cSRichard Henderson switch (gpr_FC) { 32699deb041cSRichard Henderson case 0: /* add and Store */ 32709deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 32719deb041cSRichard Henderson break; 32729deb041cSRichard Henderson case 1: /* xor and Store */ 32739deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 32749deb041cSRichard Henderson break; 32759deb041cSRichard Henderson case 2: /* Or and Store */ 32769deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 32779deb041cSRichard Henderson break; 32789deb041cSRichard Henderson case 3: /* 'and' and Store */ 32799deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 32809deb041cSRichard Henderson break; 32819deb041cSRichard Henderson case 4: /* Store max unsigned */ 3282b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3283b8ce0f86SRichard Henderson break; 32849deb041cSRichard Henderson case 5: /* Store max signed */ 3285b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3286b8ce0f86SRichard Henderson break; 32879deb041cSRichard Henderson case 6: /* Store min unsigned */ 3288b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3289b8ce0f86SRichard Henderson break; 32909deb041cSRichard Henderson case 7: /* Store min signed */ 3291b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3292b8ce0f86SRichard Henderson break; 32939deb041cSRichard Henderson case 24: /* Store twin */ 32947fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 32957fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 32967fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 32977fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 32987fbc2b20SRichard Henderson } else { 32997fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 33007fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 33017fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 33027fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 33037fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 33047fbc2b20SRichard Henderson 33057fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 33067fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 33077fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 33087fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 33097fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 33107fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 33117fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 33127fbc2b20SRichard Henderson 33137fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 33147fbc2b20SRichard Henderson tcg_temp_free(s2); 33157fbc2b20SRichard Henderson tcg_temp_free(s); 33167fbc2b20SRichard Henderson tcg_temp_free(t2); 33177fbc2b20SRichard Henderson tcg_temp_free(t); 33187fbc2b20SRichard Henderson } 33199deb041cSRichard Henderson break; 33209deb041cSRichard Henderson default: 33219deb041cSRichard Henderson /* invoke data storage error handler */ 33229deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 33239deb041cSRichard Henderson } 33249deb041cSRichard Henderson tcg_temp_free(discard); 33259deb041cSRichard Henderson tcg_temp_free(EA); 3326a3401188SBalamuruhan S } 3327a3401188SBalamuruhan S 33289deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 33299deb041cSRichard Henderson { 33309deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 33319deb041cSRichard Henderson } 33329deb041cSRichard Henderson 33339deb041cSRichard Henderson #ifdef TARGET_PPC64 33349deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 33359deb041cSRichard Henderson { 33369deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 33379deb041cSRichard Henderson } 3338a3401188SBalamuruhan S #endif 3339a3401188SBalamuruhan S 3340d8b86898SRichard Henderson static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) 3341fcf5ef2aSThomas Huth { 3342253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3343253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3344d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3345d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3346fcf5ef2aSThomas Huth 3347d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3348d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3349d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3350d8b86898SRichard Henderson tcg_temp_free(t0); 3351253ce7b2SNikunj A Dadhania 3352253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3353253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3354253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3355253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3356253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3357253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3358253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3359253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3360253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3361253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3362253ce7b2SNikunj A Dadhania 3363fcf5ef2aSThomas Huth gen_set_label(l1); 33644771df23SNikunj A Dadhania 33654771df23SNikunj A Dadhania /* Address mismatch implies failure. But we still need to provide the 33664771df23SNikunj A Dadhania memory barrier semantics of the instruction. */ 33674771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3368253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3369253ce7b2SNikunj A Dadhania 3370253ce7b2SNikunj A Dadhania gen_set_label(l2); 3371fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3372fcf5ef2aSThomas Huth } 3373fcf5ef2aSThomas Huth 3374fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3375fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3376fcf5ef2aSThomas Huth { \ 3377d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3378fcf5ef2aSThomas Huth } 3379fcf5ef2aSThomas Huth 3380fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3381fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3382fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3383fcf5ef2aSThomas Huth 3384fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3385fcf5ef2aSThomas Huth /* ldarx */ 3386fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3387fcf5ef2aSThomas Huth /* stdcx. */ 3388fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3389fcf5ef2aSThomas Huth 3390fcf5ef2aSThomas Huth /* lqarx */ 3391fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3392fcf5ef2aSThomas Huth { 3393fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 339494bf2658SRichard Henderson TCGv EA, hi, lo; 3395fcf5ef2aSThomas Huth 3396fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3397fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3398fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3399fcf5ef2aSThomas Huth return; 3400fcf5ef2aSThomas Huth } 3401fcf5ef2aSThomas Huth 3402fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 340394bf2658SRichard Henderson EA = tcg_temp_new(); 3404fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 340594bf2658SRichard Henderson 340694bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 340794bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 340894bf2658SRichard Henderson hi = cpu_gpr[rd]; 340994bf2658SRichard Henderson 341094bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3411f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 341294bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 341394bf2658SRichard Henderson if (ctx->le_mode) { 341494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 341594bf2658SRichard Henderson ctx->mem_idx)); 341694bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3417fcf5ef2aSThomas Huth } else { 341894bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 341994bf2658SRichard Henderson ctx->mem_idx)); 342094bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3421fcf5ef2aSThomas Huth } 342294bf2658SRichard Henderson tcg_temp_free_i32(oi); 342394bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3424f34ec0f6SRichard Henderson } else { 342594bf2658SRichard Henderson /* Restart with exclusive lock. */ 342694bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 342794bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 342894bf2658SRichard Henderson tcg_temp_free(EA); 342994bf2658SRichard Henderson return; 3430f34ec0f6SRichard Henderson } 343194bf2658SRichard Henderson } else if (ctx->le_mode) { 343294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3433fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3434fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 343594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 343694bf2658SRichard Henderson } else { 343794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 343894bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 343994bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 344094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 344194bf2658SRichard Henderson } 3442fcf5ef2aSThomas Huth tcg_temp_free(EA); 344394bf2658SRichard Henderson 344494bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 344594bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3446fcf5ef2aSThomas Huth } 3447fcf5ef2aSThomas Huth 3448fcf5ef2aSThomas Huth /* stqcx. */ 3449fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3450fcf5ef2aSThomas Huth { 34514a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 34524a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3453fcf5ef2aSThomas Huth 34544a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3455fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3456fcf5ef2aSThomas Huth return; 3457fcf5ef2aSThomas Huth } 34584a9b3c5dSRichard Henderson 3459fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 34604a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3461fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3462fcf5ef2aSThomas Huth 34634a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 34644a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 34654a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3466fcf5ef2aSThomas Huth 34674a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3468f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 34694a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 34704a9b3c5dSRichard Henderson if (ctx->le_mode) { 3471f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3472f34ec0f6SRichard Henderson EA, lo, hi, oi); 3473fcf5ef2aSThomas Huth } else { 3474f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3475f34ec0f6SRichard Henderson EA, lo, hi, oi); 3476fcf5ef2aSThomas Huth } 3477f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 3478f34ec0f6SRichard Henderson } else { 34794a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 34804a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 34814a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3482f34ec0f6SRichard Henderson } 3483fcf5ef2aSThomas Huth tcg_temp_free(EA); 34844a9b3c5dSRichard Henderson } else { 34854a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 34864a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 34874a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 34884a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 3489fcf5ef2aSThomas Huth 34904a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 34914a9b3c5dSRichard Henderson tcg_temp_free(EA); 34924a9b3c5dSRichard Henderson 34934a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 34944a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 34954a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 34964a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 34974a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 34984a9b3c5dSRichard Henderson 34994a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35004a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 35014a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35024a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 35034a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 35044a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35054a9b3c5dSRichard Henderson 35064a9b3c5dSRichard Henderson /* Success */ 35074a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 35084a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35094a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 35104a9b3c5dSRichard Henderson 35114a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35124a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 35134a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 35144a9b3c5dSRichard Henderson 35154a9b3c5dSRichard Henderson gen_set_label(lab_fail); 35164a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35174a9b3c5dSRichard Henderson 35184a9b3c5dSRichard Henderson gen_set_label(lab_over); 35194a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 35204a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 35214a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 35224a9b3c5dSRichard Henderson } 35234a9b3c5dSRichard Henderson } 3524fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3525fcf5ef2aSThomas Huth 3526fcf5ef2aSThomas Huth /* sync */ 3527fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3528fcf5ef2aSThomas Huth { 3529fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3530fcf5ef2aSThomas Huth 3531fcf5ef2aSThomas Huth /* 3532fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3533fcf5ef2aSThomas Huth * 3534fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3535fcf5ef2aSThomas Huth * 3536fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3537fcf5ef2aSThomas Huth * check MSR_PR as well. 3538fcf5ef2aSThomas Huth */ 3539fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3540fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3541fcf5ef2aSThomas Huth } 35424771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3543fcf5ef2aSThomas Huth } 3544fcf5ef2aSThomas Huth 3545fcf5ef2aSThomas Huth /* wait */ 3546fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3547fcf5ef2aSThomas Huth { 3548fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3549fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3550fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3551fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3552fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3553b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3554fcf5ef2aSThomas Huth } 3555fcf5ef2aSThomas Huth 3556fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3557fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3558fcf5ef2aSThomas Huth { 3559fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3560fcf5ef2aSThomas Huth GEN_PRIV; 3561fcf5ef2aSThomas Huth #else 3562fcf5ef2aSThomas Huth TCGv_i32 t; 3563fcf5ef2aSThomas Huth 3564fcf5ef2aSThomas Huth CHK_HV; 3565fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3566fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3567fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3568fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3569fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3570fcf5ef2aSThomas Huth } 3571fcf5ef2aSThomas Huth 3572fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3573fcf5ef2aSThomas Huth { 3574fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3575fcf5ef2aSThomas Huth GEN_PRIV; 3576fcf5ef2aSThomas Huth #else 3577fcf5ef2aSThomas Huth TCGv_i32 t; 3578fcf5ef2aSThomas Huth 3579fcf5ef2aSThomas Huth CHK_HV; 3580fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3581fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3582fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3583fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3584fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3585fcf5ef2aSThomas Huth } 3586fcf5ef2aSThomas Huth 3587cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3588cdee0e72SNikunj A Dadhania { 3589cdee0e72SNikunj A Dadhania gen_nap(ctx); 3590cdee0e72SNikunj A Dadhania } 3591cdee0e72SNikunj A Dadhania 3592fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3593fcf5ef2aSThomas Huth { 3594fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3595fcf5ef2aSThomas Huth GEN_PRIV; 3596fcf5ef2aSThomas Huth #else 3597fcf5ef2aSThomas Huth TCGv_i32 t; 3598fcf5ef2aSThomas Huth 3599fcf5ef2aSThomas Huth CHK_HV; 3600fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3601fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3602fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3603fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3604fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3605fcf5ef2aSThomas Huth } 3606fcf5ef2aSThomas Huth 3607fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3608fcf5ef2aSThomas Huth { 3609fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3610fcf5ef2aSThomas Huth GEN_PRIV; 3611fcf5ef2aSThomas Huth #else 3612fcf5ef2aSThomas Huth TCGv_i32 t; 3613fcf5ef2aSThomas Huth 3614fcf5ef2aSThomas Huth CHK_HV; 3615fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3616fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3617fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3618fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3619fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3620fcf5ef2aSThomas Huth } 3621fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3622fcf5ef2aSThomas Huth 3623fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3624fcf5ef2aSThomas Huth { 3625fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3626fcf5ef2aSThomas Huth if (ctx->has_cfar) 3627fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3628fcf5ef2aSThomas Huth #endif 3629fcf5ef2aSThomas Huth } 3630fcf5ef2aSThomas Huth 3631fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3632fcf5ef2aSThomas Huth { 3633fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3634fcf5ef2aSThomas Huth return false; 3635fcf5ef2aSThomas Huth } 3636fcf5ef2aSThomas Huth 3637fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3638b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3639fcf5ef2aSThomas Huth #else 3640fcf5ef2aSThomas Huth return true; 3641fcf5ef2aSThomas Huth #endif 3642fcf5ef2aSThomas Huth } 3643fcf5ef2aSThomas Huth 36440e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 36450e3bf489SRoman Kapl { 36460e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 36470e3bf489SRoman Kapl if (unlikely(sse)) { 36480e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 36490e3bf489SRoman Kapl gen_debug_exception(ctx); 36500e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3651*e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 36520e3bf489SRoman Kapl gen_exception(ctx, excp); 36530e3bf489SRoman Kapl } 36540e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 36550e3bf489SRoman Kapl } else { 36560e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 36570e3bf489SRoman Kapl } 36580e3bf489SRoman Kapl } 36590e3bf489SRoman Kapl 3660fcf5ef2aSThomas Huth /*** Branch ***/ 3661c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3662fcf5ef2aSThomas Huth { 3663fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3664fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3665fcf5ef2aSThomas Huth } 3666fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3667fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3668fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 366907ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 3670fcf5ef2aSThomas Huth } else { 3671fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 36720e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3673fcf5ef2aSThomas Huth } 3674fcf5ef2aSThomas Huth } 3675fcf5ef2aSThomas Huth 3676fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3677fcf5ef2aSThomas Huth { 3678fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3679fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3680fcf5ef2aSThomas Huth } 3681fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3682fcf5ef2aSThomas Huth } 3683fcf5ef2aSThomas Huth 3684fcf5ef2aSThomas Huth /* b ba bl bla */ 3685fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3686fcf5ef2aSThomas Huth { 3687fcf5ef2aSThomas Huth target_ulong li, target; 3688fcf5ef2aSThomas Huth 3689fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3690fcf5ef2aSThomas Huth /* sign extend LI */ 3691fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3692fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3693fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3694b6bac4bcSEmilio G. Cota target = ctx->base.pc_next + li - 4; 3695fcf5ef2aSThomas Huth } else { 3696fcf5ef2aSThomas Huth target = li; 3697fcf5ef2aSThomas Huth } 3698fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3699b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3700fcf5ef2aSThomas Huth } 3701b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3702fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3703fcf5ef2aSThomas Huth } 3704fcf5ef2aSThomas Huth 3705fcf5ef2aSThomas Huth #define BCOND_IM 0 3706fcf5ef2aSThomas Huth #define BCOND_LR 1 3707fcf5ef2aSThomas Huth #define BCOND_CTR 2 3708fcf5ef2aSThomas Huth #define BCOND_TAR 3 3709fcf5ef2aSThomas Huth 3710c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 3711fcf5ef2aSThomas Huth { 3712fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3713fcf5ef2aSThomas Huth TCGLabel *l1; 3714fcf5ef2aSThomas Huth TCGv target; 3715fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 37160e3bf489SRoman Kapl 3717fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3718fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3719fcf5ef2aSThomas Huth if (type == BCOND_CTR) 3720fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3721fcf5ef2aSThomas Huth else if (type == BCOND_TAR) 3722fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3723fcf5ef2aSThomas Huth else 3724fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3725fcf5ef2aSThomas Huth } else { 3726f764718dSRichard Henderson target = NULL; 3727fcf5ef2aSThomas Huth } 3728fcf5ef2aSThomas Huth if (LK(ctx->opcode)) 3729b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3730fcf5ef2aSThomas Huth l1 = gen_new_label(); 3731fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3732fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3733fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3734fcf5ef2aSThomas Huth if (unlikely(type == BCOND_CTR)) { 3735fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3736fcf5ef2aSThomas Huth return; 3737fcf5ef2aSThomas Huth } 3738fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3739fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3740fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3741fcf5ef2aSThomas Huth } else { 3742fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3743fcf5ef2aSThomas Huth } 3744fcf5ef2aSThomas Huth if (bo & 0x2) { 3745fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3746fcf5ef2aSThomas Huth } else { 3747fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3748fcf5ef2aSThomas Huth } 3749fcf5ef2aSThomas Huth tcg_temp_free(temp); 3750fcf5ef2aSThomas Huth } 3751fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3752fcf5ef2aSThomas Huth /* Test CR */ 3753fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3754fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3755fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3756fcf5ef2aSThomas Huth 3757fcf5ef2aSThomas Huth if (bo & 0x8) { 3758fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3759fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3760fcf5ef2aSThomas Huth } else { 3761fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3762fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3763fcf5ef2aSThomas Huth } 3764fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3765fcf5ef2aSThomas Huth } 3766b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3767fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3768fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3769fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3770b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3771fcf5ef2aSThomas Huth } else { 3772fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3773fcf5ef2aSThomas Huth } 3774fcf5ef2aSThomas Huth } else { 3775fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3776fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3777fcf5ef2aSThomas Huth } else { 3778fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3779fcf5ef2aSThomas Huth } 37800e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3781c4a2e3a9SRichard Henderson tcg_temp_free(target); 3782c4a2e3a9SRichard Henderson } 3783fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 37840e3bf489SRoman Kapl /* fallthrough case */ 3785fcf5ef2aSThomas Huth gen_set_label(l1); 3786b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 3787fcf5ef2aSThomas Huth } 3788fcf5ef2aSThomas Huth } 3789fcf5ef2aSThomas Huth 3790fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3791fcf5ef2aSThomas Huth { 3792fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3793fcf5ef2aSThomas Huth } 3794fcf5ef2aSThomas Huth 3795fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3796fcf5ef2aSThomas Huth { 3797fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3798fcf5ef2aSThomas Huth } 3799fcf5ef2aSThomas Huth 3800fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3801fcf5ef2aSThomas Huth { 3802fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3803fcf5ef2aSThomas Huth } 3804fcf5ef2aSThomas Huth 3805fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3806fcf5ef2aSThomas Huth { 3807fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3808fcf5ef2aSThomas Huth } 3809fcf5ef2aSThomas Huth 3810fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3811fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3812fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3813fcf5ef2aSThomas Huth { \ 3814fcf5ef2aSThomas Huth uint8_t bitmask; \ 3815fcf5ef2aSThomas Huth int sh; \ 3816fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3817fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3818fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3819fcf5ef2aSThomas Huth if (sh > 0) \ 3820fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3821fcf5ef2aSThomas Huth else if (sh < 0) \ 3822fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3823fcf5ef2aSThomas Huth else \ 3824fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3825fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3826fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3827fcf5ef2aSThomas Huth if (sh > 0) \ 3828fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3829fcf5ef2aSThomas Huth else if (sh < 0) \ 3830fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3831fcf5ef2aSThomas Huth else \ 3832fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3833fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3834fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3835fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3836fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3837fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3838fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3839fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3840fcf5ef2aSThomas Huth } 3841fcf5ef2aSThomas Huth 3842fcf5ef2aSThomas Huth /* crand */ 3843fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3844fcf5ef2aSThomas Huth /* crandc */ 3845fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3846fcf5ef2aSThomas Huth /* creqv */ 3847fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3848fcf5ef2aSThomas Huth /* crnand */ 3849fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3850fcf5ef2aSThomas Huth /* crnor */ 3851fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3852fcf5ef2aSThomas Huth /* cror */ 3853fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3854fcf5ef2aSThomas Huth /* crorc */ 3855fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3856fcf5ef2aSThomas Huth /* crxor */ 3857fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3858fcf5ef2aSThomas Huth 3859fcf5ef2aSThomas Huth /* mcrf */ 3860fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3861fcf5ef2aSThomas Huth { 3862fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3863fcf5ef2aSThomas Huth } 3864fcf5ef2aSThomas Huth 3865fcf5ef2aSThomas Huth /*** System linkage ***/ 3866fcf5ef2aSThomas Huth 3867fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3868fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3869fcf5ef2aSThomas Huth { 3870fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3871fcf5ef2aSThomas Huth GEN_PRIV; 3872fcf5ef2aSThomas Huth #else 3873fcf5ef2aSThomas Huth /* This instruction doesn't exist anymore on 64-bit server 3874fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3875fcf5ef2aSThomas Huth */ 3876fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_SEGMENT_64B) { 3877fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3878fcf5ef2aSThomas Huth return; 3879fcf5ef2aSThomas Huth } 3880fcf5ef2aSThomas Huth /* Restore CPU state */ 3881fcf5ef2aSThomas Huth CHK_SV; 3882a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3883a59d628fSMaria Klimushenkova gen_io_start(); 3884a59d628fSMaria Klimushenkova } 3885b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3886fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3887fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3888a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3889a59d628fSMaria Klimushenkova gen_io_end(); 3890a59d628fSMaria Klimushenkova } 3891fcf5ef2aSThomas Huth #endif 3892fcf5ef2aSThomas Huth } 3893fcf5ef2aSThomas Huth 3894fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3895fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 3896fcf5ef2aSThomas Huth { 3897fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3898fcf5ef2aSThomas Huth GEN_PRIV; 3899fcf5ef2aSThomas Huth #else 3900fcf5ef2aSThomas Huth /* Restore CPU state */ 3901fcf5ef2aSThomas Huth CHK_SV; 3902a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3903a59d628fSMaria Klimushenkova gen_io_start(); 3904a59d628fSMaria Klimushenkova } 3905b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3906fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 3907fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3908a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3909a59d628fSMaria Klimushenkova gen_io_end(); 3910a59d628fSMaria Klimushenkova } 3911fcf5ef2aSThomas Huth #endif 3912fcf5ef2aSThomas Huth } 3913fcf5ef2aSThomas Huth 3914fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 3915fcf5ef2aSThomas Huth { 3916fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3917fcf5ef2aSThomas Huth GEN_PRIV; 3918fcf5ef2aSThomas Huth #else 3919fcf5ef2aSThomas Huth /* Restore CPU state */ 3920fcf5ef2aSThomas Huth CHK_HV; 3921fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 3922fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3923fcf5ef2aSThomas Huth #endif 3924fcf5ef2aSThomas Huth } 3925fcf5ef2aSThomas Huth #endif 3926fcf5ef2aSThomas Huth 3927fcf5ef2aSThomas Huth /* sc */ 3928fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3929fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3930fcf5ef2aSThomas Huth #else 3931fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3932fcf5ef2aSThomas Huth #endif 3933fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 3934fcf5ef2aSThomas Huth { 3935fcf5ef2aSThomas Huth uint32_t lev; 3936fcf5ef2aSThomas Huth 3937fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 3938fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3939fcf5ef2aSThomas Huth } 3940fcf5ef2aSThomas Huth 3941fcf5ef2aSThomas Huth /*** Trap ***/ 3942fcf5ef2aSThomas Huth 3943fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 3944fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 3945fcf5ef2aSThomas Huth { 3946fcf5ef2aSThomas Huth /* Trap never */ 3947fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 3948fcf5ef2aSThomas Huth return true; 3949fcf5ef2aSThomas Huth } 3950fcf5ef2aSThomas Huth /* Trap always */ 3951fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 3952fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3953fcf5ef2aSThomas Huth return true; 3954fcf5ef2aSThomas Huth } 3955fcf5ef2aSThomas Huth return false; 3956fcf5ef2aSThomas Huth } 3957fcf5ef2aSThomas Huth 3958fcf5ef2aSThomas Huth /* tw */ 3959fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 3960fcf5ef2aSThomas Huth { 3961fcf5ef2aSThomas Huth TCGv_i32 t0; 3962fcf5ef2aSThomas Huth 3963fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3964fcf5ef2aSThomas Huth return; 3965fcf5ef2aSThomas Huth } 3966fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3967fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3968fcf5ef2aSThomas Huth t0); 3969fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3970fcf5ef2aSThomas Huth } 3971fcf5ef2aSThomas Huth 3972fcf5ef2aSThomas Huth /* twi */ 3973fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 3974fcf5ef2aSThomas Huth { 3975fcf5ef2aSThomas Huth TCGv t0; 3976fcf5ef2aSThomas Huth TCGv_i32 t1; 3977fcf5ef2aSThomas Huth 3978fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3979fcf5ef2aSThomas Huth return; 3980fcf5ef2aSThomas Huth } 3981fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3982fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3983fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3984fcf5ef2aSThomas Huth tcg_temp_free(t0); 3985fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3986fcf5ef2aSThomas Huth } 3987fcf5ef2aSThomas Huth 3988fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3989fcf5ef2aSThomas Huth /* td */ 3990fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 3991fcf5ef2aSThomas Huth { 3992fcf5ef2aSThomas Huth TCGv_i32 t0; 3993fcf5ef2aSThomas Huth 3994fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3995fcf5ef2aSThomas Huth return; 3996fcf5ef2aSThomas Huth } 3997fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3998fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3999fcf5ef2aSThomas Huth t0); 4000fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4001fcf5ef2aSThomas Huth } 4002fcf5ef2aSThomas Huth 4003fcf5ef2aSThomas Huth /* tdi */ 4004fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4005fcf5ef2aSThomas Huth { 4006fcf5ef2aSThomas Huth TCGv t0; 4007fcf5ef2aSThomas Huth TCGv_i32 t1; 4008fcf5ef2aSThomas Huth 4009fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4010fcf5ef2aSThomas Huth return; 4011fcf5ef2aSThomas Huth } 4012fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4013fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4014fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4015fcf5ef2aSThomas Huth tcg_temp_free(t0); 4016fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4017fcf5ef2aSThomas Huth } 4018fcf5ef2aSThomas Huth #endif 4019fcf5ef2aSThomas Huth 4020fcf5ef2aSThomas Huth /*** Processor control ***/ 4021fcf5ef2aSThomas Huth 4022dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 4023fcf5ef2aSThomas Huth { 4024fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4025fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4026fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4027fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 4028fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4029fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4030fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4031fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 4032fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 4033fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 4034dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 4035dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4036dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4037dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4038dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4039dd09c361SNikunj A Dadhania } 4040fcf5ef2aSThomas Huth tcg_temp_free(t0); 4041fcf5ef2aSThomas Huth tcg_temp_free(t1); 4042fcf5ef2aSThomas Huth tcg_temp_free(t2); 4043fcf5ef2aSThomas Huth } 4044fcf5ef2aSThomas Huth 4045fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 4046fcf5ef2aSThomas Huth { 4047dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 4048fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 4049dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 4050dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 4051dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 4052dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4053dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 40541bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 40551bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 40561bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4057fcf5ef2aSThomas Huth } 4058fcf5ef2aSThomas Huth 4059fcf5ef2aSThomas Huth /* mcrxr */ 4060fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4061fcf5ef2aSThomas Huth { 4062fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4063fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4064fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4065fcf5ef2aSThomas Huth 4066fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4067fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4068fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4069fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4070fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4071fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4072fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4073fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4074fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4075fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4076fcf5ef2aSThomas Huth 4077fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4078fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4079fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4080fcf5ef2aSThomas Huth } 4081fcf5ef2aSThomas Huth 4082b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4083b63d0434SNikunj A Dadhania /* mcrxrx */ 4084b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4085b63d0434SNikunj A Dadhania { 4086b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4087b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4088b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4089b63d0434SNikunj A Dadhania 4090b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4091b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4092b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4093b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4094b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4095b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4096b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4097b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4098b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4099b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4100b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4101b63d0434SNikunj A Dadhania } 4102b63d0434SNikunj A Dadhania #endif 4103b63d0434SNikunj A Dadhania 4104fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4105fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4106fcf5ef2aSThomas Huth { 4107fcf5ef2aSThomas Huth uint32_t crm, crn; 4108fcf5ef2aSThomas Huth 4109fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4110fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4111fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4112fcf5ef2aSThomas Huth crn = ctz32 (crm); 4113fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4114fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4115fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4116fcf5ef2aSThomas Huth } 4117fcf5ef2aSThomas Huth } else { 4118fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4119fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4120fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4121fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4122fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4123fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4124fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4125fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4126fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4127fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4128fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4129fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4130fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4131fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4132fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4133fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4134fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4135fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4136fcf5ef2aSThomas Huth } 4137fcf5ef2aSThomas Huth } 4138fcf5ef2aSThomas Huth 4139fcf5ef2aSThomas Huth /* mfmsr */ 4140fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4141fcf5ef2aSThomas Huth { 4142fcf5ef2aSThomas Huth CHK_SV; 4143fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4144fcf5ef2aSThomas Huth } 4145fcf5ef2aSThomas Huth 4146fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4147fcf5ef2aSThomas Huth { 4148fcf5ef2aSThomas Huth #if 0 4149fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4150fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 4151fcf5ef2aSThomas Huth #endif 4152fcf5ef2aSThomas Huth } 4153fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 4154fcf5ef2aSThomas Huth 4155fcf5ef2aSThomas Huth /* mfspr */ 4156fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4157fcf5ef2aSThomas Huth { 4158fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4159fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4160fcf5ef2aSThomas Huth 4161fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4162fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4163fcf5ef2aSThomas Huth #else 4164fcf5ef2aSThomas Huth if (ctx->pr) { 4165fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4166fcf5ef2aSThomas Huth } else if (ctx->hv) { 4167fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4168fcf5ef2aSThomas Huth } else { 4169fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4170fcf5ef2aSThomas Huth } 4171fcf5ef2aSThomas Huth #endif 4172fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4173fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4174fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4175fcf5ef2aSThomas Huth } else { 4176fcf5ef2aSThomas Huth /* Privilege exception */ 4177fcf5ef2aSThomas Huth /* This is a hack to avoid warnings when running Linux: 4178fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4179fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4180fcf5ef2aSThomas Huth */ 4181fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 418231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 418331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4184b6bac4bcSEmilio G. Cota ctx->base.pc_next - 4); 4185fcf5ef2aSThomas Huth } 4186fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4187fcf5ef2aSThomas Huth } 4188fcf5ef2aSThomas Huth } else { 4189fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4190fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4191fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4192fcf5ef2aSThomas Huth /* This is a nop */ 4193fcf5ef2aSThomas Huth return; 4194fcf5ef2aSThomas Huth } 4195fcf5ef2aSThomas Huth /* Not defined */ 419631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 419731085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 4198b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4199fcf5ef2aSThomas Huth 4200fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4201fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4202fcf5ef2aSThomas Huth */ 4203fcf5ef2aSThomas Huth if (sprn & 0x10) { 4204fcf5ef2aSThomas Huth if (ctx->pr) { 4205fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4206fcf5ef2aSThomas Huth } 4207fcf5ef2aSThomas Huth } else { 4208fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4209fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4210fcf5ef2aSThomas Huth } 4211fcf5ef2aSThomas Huth } 4212fcf5ef2aSThomas Huth } 4213fcf5ef2aSThomas Huth } 4214fcf5ef2aSThomas Huth 4215fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4216fcf5ef2aSThomas Huth { 4217fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4218fcf5ef2aSThomas Huth } 4219fcf5ef2aSThomas Huth 4220fcf5ef2aSThomas Huth /* mftb */ 4221fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4222fcf5ef2aSThomas Huth { 4223fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4224fcf5ef2aSThomas Huth } 4225fcf5ef2aSThomas Huth 4226fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4227fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4228fcf5ef2aSThomas Huth { 4229fcf5ef2aSThomas Huth uint32_t crm, crn; 4230fcf5ef2aSThomas Huth 4231fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4232fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4233fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4234fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4235fcf5ef2aSThomas Huth crn = ctz32 (crm); 4236fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4237fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4238fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4239fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4240fcf5ef2aSThomas Huth } 4241fcf5ef2aSThomas Huth } else { 4242fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4243fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4244fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4245fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4246fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4247fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4248fcf5ef2aSThomas Huth } 4249fcf5ef2aSThomas Huth } 4250fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4251fcf5ef2aSThomas Huth } 4252fcf5ef2aSThomas Huth } 4253fcf5ef2aSThomas Huth 4254fcf5ef2aSThomas Huth /* mtmsr */ 4255fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4256fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4257fcf5ef2aSThomas Huth { 4258fcf5ef2aSThomas Huth CHK_SV; 4259fcf5ef2aSThomas Huth 4260fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4261fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4262fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4263fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4264fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4265fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4266fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4267fcf5ef2aSThomas Huth tcg_temp_free(t0); 4268fcf5ef2aSThomas Huth } else { 4269fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4270fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4271fcf5ef2aSThomas Huth * directly from ppc_store_msr 4272fcf5ef2aSThomas Huth */ 4273b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4274b8edea50SPavel Dovgalyuk gen_io_start(); 4275b8edea50SPavel Dovgalyuk } 4276b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4277fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4278fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4279fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4280fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4281b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4282b8edea50SPavel Dovgalyuk gen_io_end(); 4283b8edea50SPavel Dovgalyuk } 4284fcf5ef2aSThomas Huth } 4285fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4286fcf5ef2aSThomas Huth } 4287fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4288fcf5ef2aSThomas Huth 4289fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4290fcf5ef2aSThomas Huth { 4291fcf5ef2aSThomas Huth CHK_SV; 4292fcf5ef2aSThomas Huth 4293fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4294fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4295fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4296fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4297fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4298fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4299fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4300fcf5ef2aSThomas Huth tcg_temp_free(t0); 4301fcf5ef2aSThomas Huth } else { 4302fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4303fcf5ef2aSThomas Huth 4304fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4305fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4306fcf5ef2aSThomas Huth * directly from ppc_store_msr 4307fcf5ef2aSThomas Huth */ 4308b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4309b8edea50SPavel Dovgalyuk gen_io_start(); 4310b8edea50SPavel Dovgalyuk } 4311b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4312fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4313fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4314fcf5ef2aSThomas Huth #else 4315fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4316fcf5ef2aSThomas Huth #endif 4317fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4318b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4319b8edea50SPavel Dovgalyuk gen_io_end(); 4320b8edea50SPavel Dovgalyuk } 4321fcf5ef2aSThomas Huth tcg_temp_free(msr); 4322fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4323fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4324fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4325fcf5ef2aSThomas Huth } 4326fcf5ef2aSThomas Huth #endif 4327fcf5ef2aSThomas Huth } 4328fcf5ef2aSThomas Huth 4329fcf5ef2aSThomas Huth /* mtspr */ 4330fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4331fcf5ef2aSThomas Huth { 4332fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4333fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4334fcf5ef2aSThomas Huth 4335fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4336fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4337fcf5ef2aSThomas Huth #else 4338fcf5ef2aSThomas Huth if (ctx->pr) { 4339fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4340fcf5ef2aSThomas Huth } else if (ctx->hv) { 4341fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4342fcf5ef2aSThomas Huth } else { 4343fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4344fcf5ef2aSThomas Huth } 4345fcf5ef2aSThomas Huth #endif 4346fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4347fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4348fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4349fcf5ef2aSThomas Huth } else { 4350fcf5ef2aSThomas Huth /* Privilege exception */ 435131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 435231085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 435331085338SThomas Huth ctx->base.pc_next - 4); 4354fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4355fcf5ef2aSThomas Huth } 4356fcf5ef2aSThomas Huth } else { 4357fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4358fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4359fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4360fcf5ef2aSThomas Huth /* This is a nop */ 4361fcf5ef2aSThomas Huth return; 4362fcf5ef2aSThomas Huth } 4363fcf5ef2aSThomas Huth 4364fcf5ef2aSThomas Huth /* Not defined */ 436531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 436631085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 4367b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4368fcf5ef2aSThomas Huth 4369fcf5ef2aSThomas Huth 4370fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4371fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4372fcf5ef2aSThomas Huth */ 4373fcf5ef2aSThomas Huth if (sprn & 0x10) { 4374fcf5ef2aSThomas Huth if (ctx->pr) { 4375fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4376fcf5ef2aSThomas Huth } 4377fcf5ef2aSThomas Huth } else { 4378fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4379fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4380fcf5ef2aSThomas Huth } 4381fcf5ef2aSThomas Huth } 4382fcf5ef2aSThomas Huth } 4383fcf5ef2aSThomas Huth } 4384fcf5ef2aSThomas Huth 4385fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4386fcf5ef2aSThomas Huth /* setb */ 4387fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4388fcf5ef2aSThomas Huth { 4389fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4390fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4391fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4392fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4393fcf5ef2aSThomas Huth 4394fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4395fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4396fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4397fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4398fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4399fcf5ef2aSThomas Huth 4400fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4401fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4402fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4403fcf5ef2aSThomas Huth } 4404fcf5ef2aSThomas Huth #endif 4405fcf5ef2aSThomas Huth 4406fcf5ef2aSThomas Huth /*** Cache management ***/ 4407fcf5ef2aSThomas Huth 4408fcf5ef2aSThomas Huth /* dcbf */ 4409fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4410fcf5ef2aSThomas Huth { 4411fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4412fcf5ef2aSThomas Huth TCGv t0; 4413fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4414fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4415fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4416fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4417fcf5ef2aSThomas Huth tcg_temp_free(t0); 4418fcf5ef2aSThomas Huth } 4419fcf5ef2aSThomas Huth 442050728199SRoman Kapl /* dcbfep (external PID dcbf) */ 442150728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 442250728199SRoman Kapl { 442350728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 442450728199SRoman Kapl TCGv t0; 442550728199SRoman Kapl CHK_SV; 442650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 442750728199SRoman Kapl t0 = tcg_temp_new(); 442850728199SRoman Kapl gen_addr_reg_index(ctx, t0); 442950728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 443050728199SRoman Kapl tcg_temp_free(t0); 443150728199SRoman Kapl } 443250728199SRoman Kapl 4433fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4434fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4435fcf5ef2aSThomas Huth { 4436fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4437fcf5ef2aSThomas Huth GEN_PRIV; 4438fcf5ef2aSThomas Huth #else 4439fcf5ef2aSThomas Huth TCGv EA, val; 4440fcf5ef2aSThomas Huth 4441fcf5ef2aSThomas Huth CHK_SV; 4442fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4443fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4444fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4445fcf5ef2aSThomas Huth val = tcg_temp_new(); 4446fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4447fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4448fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4449fcf5ef2aSThomas Huth tcg_temp_free(val); 4450fcf5ef2aSThomas Huth tcg_temp_free(EA); 4451fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4452fcf5ef2aSThomas Huth } 4453fcf5ef2aSThomas Huth 4454fcf5ef2aSThomas Huth /* dcdst */ 4455fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4456fcf5ef2aSThomas Huth { 4457fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4458fcf5ef2aSThomas Huth TCGv t0; 4459fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4460fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4461fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4462fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4463fcf5ef2aSThomas Huth tcg_temp_free(t0); 4464fcf5ef2aSThomas Huth } 4465fcf5ef2aSThomas Huth 446650728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 446750728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 446850728199SRoman Kapl { 446950728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 447050728199SRoman Kapl TCGv t0; 447150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 447250728199SRoman Kapl t0 = tcg_temp_new(); 447350728199SRoman Kapl gen_addr_reg_index(ctx, t0); 447450728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 447550728199SRoman Kapl tcg_temp_free(t0); 447650728199SRoman Kapl } 447750728199SRoman Kapl 4478fcf5ef2aSThomas Huth /* dcbt */ 4479fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4480fcf5ef2aSThomas Huth { 4481fcf5ef2aSThomas Huth /* interpreted as no-op */ 4482fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4483fcf5ef2aSThomas Huth * but does not generate any exception 4484fcf5ef2aSThomas Huth */ 4485fcf5ef2aSThomas Huth } 4486fcf5ef2aSThomas Huth 448750728199SRoman Kapl /* dcbtep */ 448850728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 448950728199SRoman Kapl { 449050728199SRoman Kapl /* interpreted as no-op */ 449150728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU 449250728199SRoman Kapl * but does not generate any exception 449350728199SRoman Kapl */ 449450728199SRoman Kapl } 449550728199SRoman Kapl 4496fcf5ef2aSThomas Huth /* dcbtst */ 4497fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4498fcf5ef2aSThomas Huth { 4499fcf5ef2aSThomas Huth /* interpreted as no-op */ 4500fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4501fcf5ef2aSThomas Huth * but does not generate any exception 4502fcf5ef2aSThomas Huth */ 4503fcf5ef2aSThomas Huth } 4504fcf5ef2aSThomas Huth 450550728199SRoman Kapl /* dcbtstep */ 450650728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 450750728199SRoman Kapl { 450850728199SRoman Kapl /* interpreted as no-op */ 450950728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU 451050728199SRoman Kapl * but does not generate any exception 451150728199SRoman Kapl */ 451250728199SRoman Kapl } 451350728199SRoman Kapl 4514fcf5ef2aSThomas Huth /* dcbtls */ 4515fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4516fcf5ef2aSThomas Huth { 4517fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4518fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4519fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4520fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4521fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4522fcf5ef2aSThomas Huth tcg_temp_free(t0); 4523fcf5ef2aSThomas Huth } 4524fcf5ef2aSThomas Huth 4525fcf5ef2aSThomas Huth /* dcbz */ 4526fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4527fcf5ef2aSThomas Huth { 4528fcf5ef2aSThomas Huth TCGv tcgv_addr; 4529fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4530fcf5ef2aSThomas Huth 4531fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4532fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4533fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4534fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4535fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4536fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4537fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4538fcf5ef2aSThomas Huth } 4539fcf5ef2aSThomas Huth 454050728199SRoman Kapl /* dcbzep */ 454150728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 454250728199SRoman Kapl { 454350728199SRoman Kapl TCGv tcgv_addr; 454450728199SRoman Kapl TCGv_i32 tcgv_op; 454550728199SRoman Kapl 454650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 454750728199SRoman Kapl tcgv_addr = tcg_temp_new(); 454850728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 454950728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 455050728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 455150728199SRoman Kapl tcg_temp_free(tcgv_addr); 455250728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 455350728199SRoman Kapl } 455450728199SRoman Kapl 4555fcf5ef2aSThomas Huth /* dst / dstt */ 4556fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4557fcf5ef2aSThomas Huth { 4558fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4559fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4560fcf5ef2aSThomas Huth } else { 4561fcf5ef2aSThomas Huth /* interpreted as no-op */ 4562fcf5ef2aSThomas Huth } 4563fcf5ef2aSThomas Huth } 4564fcf5ef2aSThomas Huth 4565fcf5ef2aSThomas Huth /* dstst /dststt */ 4566fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4567fcf5ef2aSThomas Huth { 4568fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4569fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4570fcf5ef2aSThomas Huth } else { 4571fcf5ef2aSThomas Huth /* interpreted as no-op */ 4572fcf5ef2aSThomas Huth } 4573fcf5ef2aSThomas Huth 4574fcf5ef2aSThomas Huth } 4575fcf5ef2aSThomas Huth 4576fcf5ef2aSThomas Huth /* dss / dssall */ 4577fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4578fcf5ef2aSThomas Huth { 4579fcf5ef2aSThomas Huth /* interpreted as no-op */ 4580fcf5ef2aSThomas Huth } 4581fcf5ef2aSThomas Huth 4582fcf5ef2aSThomas Huth /* icbi */ 4583fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4584fcf5ef2aSThomas Huth { 4585fcf5ef2aSThomas Huth TCGv t0; 4586fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4587fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4588fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4589fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4590fcf5ef2aSThomas Huth tcg_temp_free(t0); 4591fcf5ef2aSThomas Huth } 4592fcf5ef2aSThomas Huth 459350728199SRoman Kapl /* icbiep */ 459450728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 459550728199SRoman Kapl { 459650728199SRoman Kapl TCGv t0; 459750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 459850728199SRoman Kapl t0 = tcg_temp_new(); 459950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 460050728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 460150728199SRoman Kapl tcg_temp_free(t0); 460250728199SRoman Kapl } 460350728199SRoman Kapl 4604fcf5ef2aSThomas Huth /* Optional: */ 4605fcf5ef2aSThomas Huth /* dcba */ 4606fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4607fcf5ef2aSThomas Huth { 4608fcf5ef2aSThomas Huth /* interpreted as no-op */ 4609fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a store by the MMU 4610fcf5ef2aSThomas Huth * but does not generate any exception 4611fcf5ef2aSThomas Huth */ 4612fcf5ef2aSThomas Huth } 4613fcf5ef2aSThomas Huth 4614fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4615fcf5ef2aSThomas Huth /* Supervisor only: */ 4616fcf5ef2aSThomas Huth 4617fcf5ef2aSThomas Huth /* mfsr */ 4618fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4619fcf5ef2aSThomas Huth { 4620fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4621fcf5ef2aSThomas Huth GEN_PRIV; 4622fcf5ef2aSThomas Huth #else 4623fcf5ef2aSThomas Huth TCGv t0; 4624fcf5ef2aSThomas Huth 4625fcf5ef2aSThomas Huth CHK_SV; 4626fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4627fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4628fcf5ef2aSThomas Huth tcg_temp_free(t0); 4629fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4630fcf5ef2aSThomas Huth } 4631fcf5ef2aSThomas Huth 4632fcf5ef2aSThomas Huth /* mfsrin */ 4633fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4634fcf5ef2aSThomas Huth { 4635fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4636fcf5ef2aSThomas Huth GEN_PRIV; 4637fcf5ef2aSThomas Huth #else 4638fcf5ef2aSThomas Huth TCGv t0; 4639fcf5ef2aSThomas Huth 4640fcf5ef2aSThomas Huth CHK_SV; 4641fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4642e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4643fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4644fcf5ef2aSThomas Huth tcg_temp_free(t0); 4645fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4646fcf5ef2aSThomas Huth } 4647fcf5ef2aSThomas Huth 4648fcf5ef2aSThomas Huth /* mtsr */ 4649fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4650fcf5ef2aSThomas Huth { 4651fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4652fcf5ef2aSThomas Huth GEN_PRIV; 4653fcf5ef2aSThomas Huth #else 4654fcf5ef2aSThomas Huth TCGv t0; 4655fcf5ef2aSThomas Huth 4656fcf5ef2aSThomas Huth CHK_SV; 4657fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4658fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4659fcf5ef2aSThomas Huth tcg_temp_free(t0); 4660fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4661fcf5ef2aSThomas Huth } 4662fcf5ef2aSThomas Huth 4663fcf5ef2aSThomas Huth /* mtsrin */ 4664fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4665fcf5ef2aSThomas Huth { 4666fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4667fcf5ef2aSThomas Huth GEN_PRIV; 4668fcf5ef2aSThomas Huth #else 4669fcf5ef2aSThomas Huth TCGv t0; 4670fcf5ef2aSThomas Huth CHK_SV; 4671fcf5ef2aSThomas Huth 4672fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4673e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4674fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4675fcf5ef2aSThomas Huth tcg_temp_free(t0); 4676fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4677fcf5ef2aSThomas Huth } 4678fcf5ef2aSThomas Huth 4679fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4680fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4681fcf5ef2aSThomas Huth 4682fcf5ef2aSThomas Huth /* mfsr */ 4683fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4684fcf5ef2aSThomas Huth { 4685fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4686fcf5ef2aSThomas Huth GEN_PRIV; 4687fcf5ef2aSThomas Huth #else 4688fcf5ef2aSThomas Huth TCGv t0; 4689fcf5ef2aSThomas Huth 4690fcf5ef2aSThomas Huth CHK_SV; 4691fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4692fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4693fcf5ef2aSThomas Huth tcg_temp_free(t0); 4694fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4695fcf5ef2aSThomas Huth } 4696fcf5ef2aSThomas Huth 4697fcf5ef2aSThomas Huth /* mfsrin */ 4698fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4699fcf5ef2aSThomas Huth { 4700fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4701fcf5ef2aSThomas Huth GEN_PRIV; 4702fcf5ef2aSThomas Huth #else 4703fcf5ef2aSThomas Huth TCGv t0; 4704fcf5ef2aSThomas Huth 4705fcf5ef2aSThomas Huth CHK_SV; 4706fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4707e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4708fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4709fcf5ef2aSThomas Huth tcg_temp_free(t0); 4710fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4711fcf5ef2aSThomas Huth } 4712fcf5ef2aSThomas Huth 4713fcf5ef2aSThomas Huth /* mtsr */ 4714fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4715fcf5ef2aSThomas Huth { 4716fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4717fcf5ef2aSThomas Huth GEN_PRIV; 4718fcf5ef2aSThomas Huth #else 4719fcf5ef2aSThomas Huth TCGv t0; 4720fcf5ef2aSThomas Huth 4721fcf5ef2aSThomas Huth CHK_SV; 4722fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4723fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4724fcf5ef2aSThomas Huth tcg_temp_free(t0); 4725fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4726fcf5ef2aSThomas Huth } 4727fcf5ef2aSThomas Huth 4728fcf5ef2aSThomas Huth /* mtsrin */ 4729fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4730fcf5ef2aSThomas Huth { 4731fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4732fcf5ef2aSThomas Huth GEN_PRIV; 4733fcf5ef2aSThomas Huth #else 4734fcf5ef2aSThomas Huth TCGv t0; 4735fcf5ef2aSThomas Huth 4736fcf5ef2aSThomas Huth CHK_SV; 4737fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4738e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4739fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4740fcf5ef2aSThomas Huth tcg_temp_free(t0); 4741fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4742fcf5ef2aSThomas Huth } 4743fcf5ef2aSThomas Huth 4744fcf5ef2aSThomas Huth /* slbmte */ 4745fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4746fcf5ef2aSThomas Huth { 4747fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4748fcf5ef2aSThomas Huth GEN_PRIV; 4749fcf5ef2aSThomas Huth #else 4750fcf5ef2aSThomas Huth CHK_SV; 4751fcf5ef2aSThomas Huth 4752fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4753fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4754fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4755fcf5ef2aSThomas Huth } 4756fcf5ef2aSThomas Huth 4757fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4758fcf5ef2aSThomas Huth { 4759fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4760fcf5ef2aSThomas Huth GEN_PRIV; 4761fcf5ef2aSThomas Huth #else 4762fcf5ef2aSThomas Huth CHK_SV; 4763fcf5ef2aSThomas Huth 4764fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4765fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4766fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4767fcf5ef2aSThomas Huth } 4768fcf5ef2aSThomas Huth 4769fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4770fcf5ef2aSThomas Huth { 4771fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4772fcf5ef2aSThomas Huth GEN_PRIV; 4773fcf5ef2aSThomas Huth #else 4774fcf5ef2aSThomas Huth CHK_SV; 4775fcf5ef2aSThomas Huth 4776fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4777fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4778fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4779fcf5ef2aSThomas Huth } 4780fcf5ef2aSThomas Huth 4781fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4782fcf5ef2aSThomas Huth { 4783fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4784fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4785fcf5ef2aSThomas Huth #else 4786fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4787fcf5ef2aSThomas Huth 4788fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4789fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4790fcf5ef2aSThomas Huth return; 4791fcf5ef2aSThomas Huth } 4792fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4793fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4794fcf5ef2aSThomas Huth l1 = gen_new_label(); 4795fcf5ef2aSThomas Huth l2 = gen_new_label(); 4796fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4797fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4798efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4799fcf5ef2aSThomas Huth tcg_gen_br(l2); 4800fcf5ef2aSThomas Huth gen_set_label(l1); 4801fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4802fcf5ef2aSThomas Huth gen_set_label(l2); 4803fcf5ef2aSThomas Huth #endif 4804fcf5ef2aSThomas Huth } 4805fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4806fcf5ef2aSThomas Huth 4807fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4808fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4809fcf5ef2aSThomas Huth 4810fcf5ef2aSThomas Huth /* tlbia */ 4811fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4812fcf5ef2aSThomas Huth { 4813fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4814fcf5ef2aSThomas Huth GEN_PRIV; 4815fcf5ef2aSThomas Huth #else 4816fcf5ef2aSThomas Huth CHK_HV; 4817fcf5ef2aSThomas Huth 4818fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4819fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4820fcf5ef2aSThomas Huth } 4821fcf5ef2aSThomas Huth 4822fcf5ef2aSThomas Huth /* tlbiel */ 4823fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4824fcf5ef2aSThomas Huth { 4825fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4826fcf5ef2aSThomas Huth GEN_PRIV; 4827fcf5ef2aSThomas Huth #else 4828fcf5ef2aSThomas Huth CHK_SV; 4829fcf5ef2aSThomas Huth 4830fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4831fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4832fcf5ef2aSThomas Huth } 4833fcf5ef2aSThomas Huth 4834fcf5ef2aSThomas Huth /* tlbie */ 4835fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4836fcf5ef2aSThomas Huth { 4837fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4838fcf5ef2aSThomas Huth GEN_PRIV; 4839fcf5ef2aSThomas Huth #else 4840fcf5ef2aSThomas Huth TCGv_i32 t1; 4841c6fd28fdSSuraj Jitindar Singh 4842c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 484391c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4844c6fd28fdSSuraj Jitindar Singh } else { 4845c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 4846c6fd28fdSSuraj Jitindar Singh } 4847fcf5ef2aSThomas Huth 4848fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4849fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4850fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4851fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4852fcf5ef2aSThomas Huth tcg_temp_free(t0); 4853fcf5ef2aSThomas Huth } else { 4854fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4855fcf5ef2aSThomas Huth } 4856fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4857fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4858fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4859fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4860fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4861fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4862fcf5ef2aSThomas Huth } 4863fcf5ef2aSThomas Huth 4864fcf5ef2aSThomas Huth /* tlbsync */ 4865fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4866fcf5ef2aSThomas Huth { 4867fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4868fcf5ef2aSThomas Huth GEN_PRIV; 4869fcf5ef2aSThomas Huth #else 487091c60f12SCédric Le Goater 487191c60f12SCédric Le Goater if (ctx->gtse) { 487291c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 487391c60f12SCédric Le Goater } else { 487491c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 487591c60f12SCédric Le Goater } 4876fcf5ef2aSThomas Huth 4877fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4878fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4879fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4880fcf5ef2aSThomas Huth } 4881fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4882fcf5ef2aSThomas Huth } 4883fcf5ef2aSThomas Huth 4884fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4885fcf5ef2aSThomas Huth /* slbia */ 4886fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 4887fcf5ef2aSThomas Huth { 4888fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4889fcf5ef2aSThomas Huth GEN_PRIV; 4890fcf5ef2aSThomas Huth #else 4891fcf5ef2aSThomas Huth CHK_SV; 4892fcf5ef2aSThomas Huth 4893fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 4894fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4895fcf5ef2aSThomas Huth } 4896fcf5ef2aSThomas Huth 4897fcf5ef2aSThomas Huth /* slbie */ 4898fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 4899fcf5ef2aSThomas Huth { 4900fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4901fcf5ef2aSThomas Huth GEN_PRIV; 4902fcf5ef2aSThomas Huth #else 4903fcf5ef2aSThomas Huth CHK_SV; 4904fcf5ef2aSThomas Huth 4905fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4906fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4907fcf5ef2aSThomas Huth } 4908a63f1dfcSNikunj A Dadhania 4909a63f1dfcSNikunj A Dadhania /* slbieg */ 4910a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 4911a63f1dfcSNikunj A Dadhania { 4912a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 4913a63f1dfcSNikunj A Dadhania GEN_PRIV; 4914a63f1dfcSNikunj A Dadhania #else 4915a63f1dfcSNikunj A Dadhania CHK_SV; 4916a63f1dfcSNikunj A Dadhania 4917a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4918a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 4919a63f1dfcSNikunj A Dadhania } 4920a63f1dfcSNikunj A Dadhania 492162d897caSNikunj A Dadhania /* slbsync */ 492262d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 492362d897caSNikunj A Dadhania { 492462d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 492562d897caSNikunj A Dadhania GEN_PRIV; 492662d897caSNikunj A Dadhania #else 492762d897caSNikunj A Dadhania CHK_SV; 492862d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 492962d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 493062d897caSNikunj A Dadhania } 493162d897caSNikunj A Dadhania 4932fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4933fcf5ef2aSThomas Huth 4934fcf5ef2aSThomas Huth /*** External control ***/ 4935fcf5ef2aSThomas Huth /* Optional: */ 4936fcf5ef2aSThomas Huth 4937fcf5ef2aSThomas Huth /* eciwx */ 4938fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 4939fcf5ef2aSThomas Huth { 4940fcf5ef2aSThomas Huth TCGv t0; 4941fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4942fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4943fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4944fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4945c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4946c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 4947fcf5ef2aSThomas Huth tcg_temp_free(t0); 4948fcf5ef2aSThomas Huth } 4949fcf5ef2aSThomas Huth 4950fcf5ef2aSThomas Huth /* ecowx */ 4951fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 4952fcf5ef2aSThomas Huth { 4953fcf5ef2aSThomas Huth TCGv t0; 4954fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4955fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4956fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4957fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4958c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4959c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 4960fcf5ef2aSThomas Huth tcg_temp_free(t0); 4961fcf5ef2aSThomas Huth } 4962fcf5ef2aSThomas Huth 4963fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 4964fcf5ef2aSThomas Huth 4965fcf5ef2aSThomas Huth /* abs - abs. */ 4966fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 4967fcf5ef2aSThomas Huth { 4968fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4969fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4970fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4971fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4972fcf5ef2aSThomas Huth tcg_gen_br(l2); 4973fcf5ef2aSThomas Huth gen_set_label(l1); 4974fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4975fcf5ef2aSThomas Huth gen_set_label(l2); 4976fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4977fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4978fcf5ef2aSThomas Huth } 4979fcf5ef2aSThomas Huth 4980fcf5ef2aSThomas Huth /* abso - abso. */ 4981fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 4982fcf5ef2aSThomas Huth { 4983fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4984fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4985fcf5ef2aSThomas Huth TCGLabel *l3 = gen_new_label(); 4986fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4987fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4988fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4989fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4990fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4991fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4992fcf5ef2aSThomas Huth tcg_gen_br(l2); 4993fcf5ef2aSThomas Huth gen_set_label(l1); 4994fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4995fcf5ef2aSThomas Huth tcg_gen_br(l3); 4996fcf5ef2aSThomas Huth gen_set_label(l2); 4997fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4998fcf5ef2aSThomas Huth gen_set_label(l3); 4999fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5000fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5001fcf5ef2aSThomas Huth } 5002fcf5ef2aSThomas Huth 5003fcf5ef2aSThomas Huth /* clcs */ 5004fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5005fcf5ef2aSThomas Huth { 5006fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5007fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5008fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5009fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5010fcf5ef2aSThomas Huth } 5011fcf5ef2aSThomas Huth 5012fcf5ef2aSThomas Huth /* div - div. */ 5013fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5014fcf5ef2aSThomas Huth { 5015fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5016fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5017fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5018fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5019fcf5ef2aSThomas Huth } 5020fcf5ef2aSThomas Huth 5021fcf5ef2aSThomas Huth /* divo - divo. */ 5022fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5023fcf5ef2aSThomas Huth { 5024fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5025fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5026fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5027fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5028fcf5ef2aSThomas Huth } 5029fcf5ef2aSThomas Huth 5030fcf5ef2aSThomas Huth /* divs - divs. */ 5031fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5032fcf5ef2aSThomas Huth { 5033fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5034fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5035fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5036fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5037fcf5ef2aSThomas Huth } 5038fcf5ef2aSThomas Huth 5039fcf5ef2aSThomas Huth /* divso - divso. */ 5040fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5041fcf5ef2aSThomas Huth { 5042fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5043fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5044fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5045fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5046fcf5ef2aSThomas Huth } 5047fcf5ef2aSThomas Huth 5048fcf5ef2aSThomas Huth /* doz - doz. */ 5049fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5050fcf5ef2aSThomas Huth { 5051fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5052fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5053fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 5054fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5055fcf5ef2aSThomas Huth tcg_gen_br(l2); 5056fcf5ef2aSThomas Huth gen_set_label(l1); 5057fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5058fcf5ef2aSThomas Huth gen_set_label(l2); 5059fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5060fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5061fcf5ef2aSThomas Huth } 5062fcf5ef2aSThomas Huth 5063fcf5ef2aSThomas Huth /* dozo - dozo. */ 5064fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5065fcf5ef2aSThomas Huth { 5066fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5067fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5068fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5069fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5070fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5071fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5072fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5073fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 5074fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5075fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5076fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5077fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5078fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5079fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5080fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5081fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5082fcf5ef2aSThomas Huth tcg_gen_br(l2); 5083fcf5ef2aSThomas Huth gen_set_label(l1); 5084fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5085fcf5ef2aSThomas Huth gen_set_label(l2); 5086fcf5ef2aSThomas Huth tcg_temp_free(t0); 5087fcf5ef2aSThomas Huth tcg_temp_free(t1); 5088fcf5ef2aSThomas Huth tcg_temp_free(t2); 5089fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5090fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5091fcf5ef2aSThomas Huth } 5092fcf5ef2aSThomas Huth 5093fcf5ef2aSThomas Huth /* dozi */ 5094fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5095fcf5ef2aSThomas Huth { 5096fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5097fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5098fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5099fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5100fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5101fcf5ef2aSThomas Huth tcg_gen_br(l2); 5102fcf5ef2aSThomas Huth gen_set_label(l1); 5103fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5104fcf5ef2aSThomas Huth gen_set_label(l2); 5105fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5106fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5107fcf5ef2aSThomas Huth } 5108fcf5ef2aSThomas Huth 5109fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5110fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5111fcf5ef2aSThomas Huth { 5112fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5113fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5114fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5115fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5116fcf5ef2aSThomas Huth 5117fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5118fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5119fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5120fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5121fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5122fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5123fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5124fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5125fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5126fcf5ef2aSThomas Huth tcg_temp_free(t0); 5127fcf5ef2aSThomas Huth } 5128fcf5ef2aSThomas Huth 5129fcf5ef2aSThomas Huth /* maskg - maskg. */ 5130fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5131fcf5ef2aSThomas Huth { 5132fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5133fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5134fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5135fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5136fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5137fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5138fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5139fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5140fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5141fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5142fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5143fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5144fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5145fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5146fcf5ef2aSThomas Huth gen_set_label(l1); 5147fcf5ef2aSThomas Huth tcg_temp_free(t0); 5148fcf5ef2aSThomas Huth tcg_temp_free(t1); 5149fcf5ef2aSThomas Huth tcg_temp_free(t2); 5150fcf5ef2aSThomas Huth tcg_temp_free(t3); 5151fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5152fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5153fcf5ef2aSThomas Huth } 5154fcf5ef2aSThomas Huth 5155fcf5ef2aSThomas Huth /* maskir - maskir. */ 5156fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5157fcf5ef2aSThomas Huth { 5158fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5159fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5160fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5161fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5162fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5163fcf5ef2aSThomas Huth tcg_temp_free(t0); 5164fcf5ef2aSThomas Huth tcg_temp_free(t1); 5165fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5166fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5167fcf5ef2aSThomas Huth } 5168fcf5ef2aSThomas Huth 5169fcf5ef2aSThomas Huth /* mul - mul. */ 5170fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5171fcf5ef2aSThomas Huth { 5172fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5173fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5174fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5175fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5176fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5177fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5178fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5179fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5180fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5181fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5182fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5183fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5184fcf5ef2aSThomas Huth tcg_temp_free(t2); 5185fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5186fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5187fcf5ef2aSThomas Huth } 5188fcf5ef2aSThomas Huth 5189fcf5ef2aSThomas Huth /* mulo - mulo. */ 5190fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5191fcf5ef2aSThomas Huth { 5192fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5193fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5194fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5195fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5196fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5197fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5198fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5199fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5200fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5201fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5202fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5203fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5204fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5205fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5206fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5207fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5208fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5209fcf5ef2aSThomas Huth gen_set_label(l1); 5210fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5211fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5212fcf5ef2aSThomas Huth tcg_temp_free(t2); 5213fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5214fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5215fcf5ef2aSThomas Huth } 5216fcf5ef2aSThomas Huth 5217fcf5ef2aSThomas Huth /* nabs - nabs. */ 5218fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5219fcf5ef2aSThomas Huth { 5220fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5221fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5222fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 5223fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5224fcf5ef2aSThomas Huth tcg_gen_br(l2); 5225fcf5ef2aSThomas Huth gen_set_label(l1); 5226fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5227fcf5ef2aSThomas Huth gen_set_label(l2); 5228fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5229fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5230fcf5ef2aSThomas Huth } 5231fcf5ef2aSThomas Huth 5232fcf5ef2aSThomas Huth /* nabso - nabso. */ 5233fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5234fcf5ef2aSThomas Huth { 5235fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5236fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5237fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 5238fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5239fcf5ef2aSThomas Huth tcg_gen_br(l2); 5240fcf5ef2aSThomas Huth gen_set_label(l1); 5241fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5242fcf5ef2aSThomas Huth gen_set_label(l2); 5243fcf5ef2aSThomas Huth /* nabs never overflows */ 5244fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5245fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5246fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5247fcf5ef2aSThomas Huth } 5248fcf5ef2aSThomas Huth 5249fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5250fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5251fcf5ef2aSThomas Huth { 5252fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5253fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5254fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5255fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5256fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5257fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5258fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 5259fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5260fcf5ef2aSThomas Huth tcg_temp_free(t0); 5261fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5262fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5263fcf5ef2aSThomas Huth } 5264fcf5ef2aSThomas Huth 5265fcf5ef2aSThomas Huth /* rrib - rrib. */ 5266fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5267fcf5ef2aSThomas Huth { 5268fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5269fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5270fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5271fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5272fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5273fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5274fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5275fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5276fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5277fcf5ef2aSThomas Huth tcg_temp_free(t0); 5278fcf5ef2aSThomas Huth tcg_temp_free(t1); 5279fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5280fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5281fcf5ef2aSThomas Huth } 5282fcf5ef2aSThomas Huth 5283fcf5ef2aSThomas Huth /* sle - sle. */ 5284fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5285fcf5ef2aSThomas Huth { 5286fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5287fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5288fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5289fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5290fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5291fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5292fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5293fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5294fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5295fcf5ef2aSThomas Huth tcg_temp_free(t0); 5296fcf5ef2aSThomas Huth tcg_temp_free(t1); 5297fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5298fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5299fcf5ef2aSThomas Huth } 5300fcf5ef2aSThomas Huth 5301fcf5ef2aSThomas Huth /* sleq - sleq. */ 5302fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5303fcf5ef2aSThomas Huth { 5304fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5305fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5306fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5307fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5308fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5309fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5310fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5311fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5312fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5313fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5314fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5315fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5316fcf5ef2aSThomas Huth tcg_temp_free(t0); 5317fcf5ef2aSThomas Huth tcg_temp_free(t1); 5318fcf5ef2aSThomas Huth tcg_temp_free(t2); 5319fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5320fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5321fcf5ef2aSThomas Huth } 5322fcf5ef2aSThomas Huth 5323fcf5ef2aSThomas Huth /* sliq - sliq. */ 5324fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5325fcf5ef2aSThomas Huth { 5326fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5327fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5328fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5329fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5330fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5331fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5332fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5333fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5334fcf5ef2aSThomas Huth tcg_temp_free(t0); 5335fcf5ef2aSThomas Huth tcg_temp_free(t1); 5336fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5337fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5338fcf5ef2aSThomas Huth } 5339fcf5ef2aSThomas Huth 5340fcf5ef2aSThomas Huth /* slliq - slliq. */ 5341fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5342fcf5ef2aSThomas Huth { 5343fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5344fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5345fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5346fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5347fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5348fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5349fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5350fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5351fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5352fcf5ef2aSThomas Huth tcg_temp_free(t0); 5353fcf5ef2aSThomas Huth tcg_temp_free(t1); 5354fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5355fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5356fcf5ef2aSThomas Huth } 5357fcf5ef2aSThomas Huth 5358fcf5ef2aSThomas Huth /* sllq - sllq. */ 5359fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5360fcf5ef2aSThomas Huth { 5361fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5362fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5363fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5364fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5365fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5366fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5367fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5368fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5369fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5370fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5371fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5372fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5373fcf5ef2aSThomas Huth tcg_gen_br(l2); 5374fcf5ef2aSThomas Huth gen_set_label(l1); 5375fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5376fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5377fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5378fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5379fcf5ef2aSThomas Huth gen_set_label(l2); 5380fcf5ef2aSThomas Huth tcg_temp_free(t0); 5381fcf5ef2aSThomas Huth tcg_temp_free(t1); 5382fcf5ef2aSThomas Huth tcg_temp_free(t2); 5383fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5384fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5385fcf5ef2aSThomas Huth } 5386fcf5ef2aSThomas Huth 5387fcf5ef2aSThomas Huth /* slq - slq. */ 5388fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5389fcf5ef2aSThomas Huth { 5390fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5391fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5392fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5393fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5394fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5395fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5396fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5397fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5398fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5399fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5400fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5401fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5402fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5403fcf5ef2aSThomas Huth gen_set_label(l1); 5404fcf5ef2aSThomas Huth tcg_temp_free(t0); 5405fcf5ef2aSThomas Huth tcg_temp_free(t1); 5406fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5407fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5408fcf5ef2aSThomas Huth } 5409fcf5ef2aSThomas Huth 5410fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5411fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5412fcf5ef2aSThomas Huth { 5413fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5414fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5415fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5416fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5417fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5418fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5419fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5420fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5421fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5422fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5423fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5424fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5425fcf5ef2aSThomas Huth gen_set_label(l1); 5426fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5427fcf5ef2aSThomas Huth tcg_temp_free(t0); 5428fcf5ef2aSThomas Huth tcg_temp_free(t1); 5429fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5430fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5431fcf5ef2aSThomas Huth } 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth /* sraq - sraq. */ 5434fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5435fcf5ef2aSThomas Huth { 5436fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5437fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5438fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5439fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5440fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5441fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5442fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5443fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5444fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5445fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5446fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5447fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5448fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5449fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5450fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5451fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5452fcf5ef2aSThomas Huth gen_set_label(l1); 5453fcf5ef2aSThomas Huth tcg_temp_free(t0); 5454fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5455fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5456fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5457fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5458fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5459fcf5ef2aSThomas Huth gen_set_label(l2); 5460fcf5ef2aSThomas Huth tcg_temp_free(t1); 5461fcf5ef2aSThomas Huth tcg_temp_free(t2); 5462fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5463fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5464fcf5ef2aSThomas Huth } 5465fcf5ef2aSThomas Huth 5466fcf5ef2aSThomas Huth /* sre - sre. */ 5467fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5468fcf5ef2aSThomas Huth { 5469fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5470fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5471fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5472fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5473fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5474fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5475fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5476fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5477fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5478fcf5ef2aSThomas Huth tcg_temp_free(t0); 5479fcf5ef2aSThomas Huth tcg_temp_free(t1); 5480fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5481fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5482fcf5ef2aSThomas Huth } 5483fcf5ef2aSThomas Huth 5484fcf5ef2aSThomas Huth /* srea - srea. */ 5485fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5486fcf5ef2aSThomas Huth { 5487fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5488fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5489fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5490fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5491fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5492fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5493fcf5ef2aSThomas Huth tcg_temp_free(t0); 5494fcf5ef2aSThomas Huth tcg_temp_free(t1); 5495fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5496fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5497fcf5ef2aSThomas Huth } 5498fcf5ef2aSThomas Huth 5499fcf5ef2aSThomas Huth /* sreq */ 5500fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5501fcf5ef2aSThomas Huth { 5502fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5503fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5504fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5505fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5506fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5507fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5508fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5509fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5510fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5511fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5512fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5513fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5514fcf5ef2aSThomas Huth tcg_temp_free(t0); 5515fcf5ef2aSThomas Huth tcg_temp_free(t1); 5516fcf5ef2aSThomas Huth tcg_temp_free(t2); 5517fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5518fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5519fcf5ef2aSThomas Huth } 5520fcf5ef2aSThomas Huth 5521fcf5ef2aSThomas Huth /* sriq */ 5522fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5523fcf5ef2aSThomas Huth { 5524fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5525fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5526fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5527fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5528fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5529fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5530fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5531fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5532fcf5ef2aSThomas Huth tcg_temp_free(t0); 5533fcf5ef2aSThomas Huth tcg_temp_free(t1); 5534fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5535fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5536fcf5ef2aSThomas Huth } 5537fcf5ef2aSThomas Huth 5538fcf5ef2aSThomas Huth /* srliq */ 5539fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5540fcf5ef2aSThomas Huth { 5541fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5542fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5543fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5544fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5545fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5546fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5547fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5548fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5549fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5550fcf5ef2aSThomas Huth tcg_temp_free(t0); 5551fcf5ef2aSThomas Huth tcg_temp_free(t1); 5552fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5553fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5554fcf5ef2aSThomas Huth } 5555fcf5ef2aSThomas Huth 5556fcf5ef2aSThomas Huth /* srlq */ 5557fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5558fcf5ef2aSThomas Huth { 5559fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5560fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5561fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5562fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5563fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5564fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5565fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5566fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5567fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5568fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5569fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5570fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5571fcf5ef2aSThomas Huth tcg_gen_br(l2); 5572fcf5ef2aSThomas Huth gen_set_label(l1); 5573fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5574fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5575fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5576fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5577fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5578fcf5ef2aSThomas Huth gen_set_label(l2); 5579fcf5ef2aSThomas Huth tcg_temp_free(t0); 5580fcf5ef2aSThomas Huth tcg_temp_free(t1); 5581fcf5ef2aSThomas Huth tcg_temp_free(t2); 5582fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5583fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5584fcf5ef2aSThomas Huth } 5585fcf5ef2aSThomas Huth 5586fcf5ef2aSThomas Huth /* srq */ 5587fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5588fcf5ef2aSThomas Huth { 5589fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5590fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5591fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5592fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5593fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5594fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5595fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5596fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5597fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5598fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5599fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5600fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5601fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5602fcf5ef2aSThomas Huth gen_set_label(l1); 5603fcf5ef2aSThomas Huth tcg_temp_free(t0); 5604fcf5ef2aSThomas Huth tcg_temp_free(t1); 5605fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5606fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5607fcf5ef2aSThomas Huth } 5608fcf5ef2aSThomas Huth 5609fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5610fcf5ef2aSThomas Huth 5611fcf5ef2aSThomas Huth /* dsa */ 5612fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5613fcf5ef2aSThomas Huth { 5614fcf5ef2aSThomas Huth /* XXX: TODO */ 5615fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5616fcf5ef2aSThomas Huth } 5617fcf5ef2aSThomas Huth 5618fcf5ef2aSThomas Huth /* esa */ 5619fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5620fcf5ef2aSThomas Huth { 5621fcf5ef2aSThomas Huth /* XXX: TODO */ 5622fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5623fcf5ef2aSThomas Huth } 5624fcf5ef2aSThomas Huth 5625fcf5ef2aSThomas Huth /* mfrom */ 5626fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5627fcf5ef2aSThomas Huth { 5628fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5629fcf5ef2aSThomas Huth GEN_PRIV; 5630fcf5ef2aSThomas Huth #else 5631fcf5ef2aSThomas Huth CHK_SV; 5632fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5633fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5634fcf5ef2aSThomas Huth } 5635fcf5ef2aSThomas Huth 5636fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5637fcf5ef2aSThomas Huth 5638fcf5ef2aSThomas Huth /* tlbld */ 5639fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5640fcf5ef2aSThomas Huth { 5641fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5642fcf5ef2aSThomas Huth GEN_PRIV; 5643fcf5ef2aSThomas Huth #else 5644fcf5ef2aSThomas Huth CHK_SV; 5645fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5646fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5647fcf5ef2aSThomas Huth } 5648fcf5ef2aSThomas Huth 5649fcf5ef2aSThomas Huth /* tlbli */ 5650fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5651fcf5ef2aSThomas Huth { 5652fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5653fcf5ef2aSThomas Huth GEN_PRIV; 5654fcf5ef2aSThomas Huth #else 5655fcf5ef2aSThomas Huth CHK_SV; 5656fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5657fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5658fcf5ef2aSThomas Huth } 5659fcf5ef2aSThomas Huth 5660fcf5ef2aSThomas Huth /* 74xx TLB management */ 5661fcf5ef2aSThomas Huth 5662fcf5ef2aSThomas Huth /* tlbld */ 5663fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5664fcf5ef2aSThomas Huth { 5665fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5666fcf5ef2aSThomas Huth GEN_PRIV; 5667fcf5ef2aSThomas Huth #else 5668fcf5ef2aSThomas Huth CHK_SV; 5669fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5670fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5671fcf5ef2aSThomas Huth } 5672fcf5ef2aSThomas Huth 5673fcf5ef2aSThomas Huth /* tlbli */ 5674fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5675fcf5ef2aSThomas Huth { 5676fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5677fcf5ef2aSThomas Huth GEN_PRIV; 5678fcf5ef2aSThomas Huth #else 5679fcf5ef2aSThomas Huth CHK_SV; 5680fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5681fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5682fcf5ef2aSThomas Huth } 5683fcf5ef2aSThomas Huth 5684fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5685fcf5ef2aSThomas Huth 5686fcf5ef2aSThomas Huth /* clf */ 5687fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5688fcf5ef2aSThomas Huth { 5689fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5690fcf5ef2aSThomas Huth } 5691fcf5ef2aSThomas Huth 5692fcf5ef2aSThomas Huth /* cli */ 5693fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5694fcf5ef2aSThomas Huth { 5695fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5696fcf5ef2aSThomas Huth GEN_PRIV; 5697fcf5ef2aSThomas Huth #else 5698fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5699fcf5ef2aSThomas Huth CHK_SV; 5700fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5701fcf5ef2aSThomas Huth } 5702fcf5ef2aSThomas Huth 5703fcf5ef2aSThomas Huth /* dclst */ 5704fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5705fcf5ef2aSThomas Huth { 5706fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5707fcf5ef2aSThomas Huth } 5708fcf5ef2aSThomas Huth 5709fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5710fcf5ef2aSThomas Huth { 5711fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5712fcf5ef2aSThomas Huth GEN_PRIV; 5713fcf5ef2aSThomas Huth #else 5714fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5715fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5716fcf5ef2aSThomas Huth TCGv t0; 5717fcf5ef2aSThomas Huth 5718fcf5ef2aSThomas Huth CHK_SV; 5719fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5720fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5721e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 5722fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5723fcf5ef2aSThomas Huth tcg_temp_free(t0); 5724fcf5ef2aSThomas Huth if (ra != 0 && ra != rd) 5725fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5726fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5727fcf5ef2aSThomas Huth } 5728fcf5ef2aSThomas Huth 5729fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5730fcf5ef2aSThomas Huth { 5731fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5732fcf5ef2aSThomas Huth GEN_PRIV; 5733fcf5ef2aSThomas Huth #else 5734fcf5ef2aSThomas Huth TCGv t0; 5735fcf5ef2aSThomas Huth 5736fcf5ef2aSThomas Huth CHK_SV; 5737fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5738fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5739fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5740fcf5ef2aSThomas Huth tcg_temp_free(t0); 5741fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5742fcf5ef2aSThomas Huth } 5743fcf5ef2aSThomas Huth 5744fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5745fcf5ef2aSThomas Huth { 5746fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5747fcf5ef2aSThomas Huth GEN_PRIV; 5748fcf5ef2aSThomas Huth #else 5749fcf5ef2aSThomas Huth CHK_SV; 5750fcf5ef2aSThomas Huth 5751fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5752fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5753fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5754fcf5ef2aSThomas Huth } 5755fcf5ef2aSThomas Huth 5756fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5757fcf5ef2aSThomas Huth 5758fcf5ef2aSThomas Huth /* BookE specific instructions */ 5759fcf5ef2aSThomas Huth 5760fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5761fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5762fcf5ef2aSThomas Huth { 5763fcf5ef2aSThomas Huth /* XXX: TODO */ 5764fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5765fcf5ef2aSThomas Huth } 5766fcf5ef2aSThomas Huth 5767fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5768fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5769fcf5ef2aSThomas Huth { 5770fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5771fcf5ef2aSThomas Huth GEN_PRIV; 5772fcf5ef2aSThomas Huth #else 5773fcf5ef2aSThomas Huth TCGv t0; 5774fcf5ef2aSThomas Huth 5775fcf5ef2aSThomas Huth CHK_SV; 5776fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5777fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5778fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5779fcf5ef2aSThomas Huth tcg_temp_free(t0); 5780fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5781fcf5ef2aSThomas Huth } 5782fcf5ef2aSThomas Huth 5783fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5784fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5785fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5786fcf5ef2aSThomas Huth { 5787fcf5ef2aSThomas Huth TCGv t0, t1; 5788fcf5ef2aSThomas Huth 5789fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5790fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5791fcf5ef2aSThomas Huth 5792fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5793fcf5ef2aSThomas Huth case 0x05: 5794fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5795fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5796fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5797fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5798fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5799fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5800fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5801fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5802fcf5ef2aSThomas Huth break; 5803fcf5ef2aSThomas Huth case 0x04: 5804fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5805fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5806fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5807fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5808fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5809fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5810fcf5ef2aSThomas Huth break; 5811fcf5ef2aSThomas Huth case 0x01: 5812fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5813fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5814fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5815fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5816fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5817fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5818fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5819fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5820fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5821fcf5ef2aSThomas Huth break; 5822fcf5ef2aSThomas Huth case 0x00: 5823fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5824fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5825fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5826fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5827fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5828fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5829fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5830fcf5ef2aSThomas Huth break; 5831fcf5ef2aSThomas Huth case 0x0D: 5832fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5833fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5834fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5835fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5836fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5837fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5838fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5839fcf5ef2aSThomas Huth break; 5840fcf5ef2aSThomas Huth case 0x0C: 5841fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5842fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5843fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5844fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5845fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5846fcf5ef2aSThomas Huth break; 5847fcf5ef2aSThomas Huth } 5848fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5849fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5850fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5851fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5852fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5853fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5854fcf5ef2aSThomas Huth } else { 5855fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5856fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5857fcf5ef2aSThomas Huth } 5858fcf5ef2aSThomas Huth 5859fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5860fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5861fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5862fcf5ef2aSThomas Huth 5863fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5864fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5865fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5866fcf5ef2aSThomas Huth } 5867fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5868fcf5ef2aSThomas Huth /* Signed */ 5869fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5870fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5871fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5872fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5873fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5874fcf5ef2aSThomas Huth /* Saturate */ 5875fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5876fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5877fcf5ef2aSThomas Huth } 5878fcf5ef2aSThomas Huth } else { 5879fcf5ef2aSThomas Huth /* Unsigned */ 5880fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5881fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5882fcf5ef2aSThomas Huth /* Saturate */ 5883fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5884fcf5ef2aSThomas Huth } 5885fcf5ef2aSThomas Huth } 5886fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5887fcf5ef2aSThomas Huth /* Check overflow */ 5888fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5889fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5890fcf5ef2aSThomas Huth } 5891fcf5ef2aSThomas Huth gen_set_label(l1); 5892fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5893fcf5ef2aSThomas Huth } 5894fcf5ef2aSThomas Huth } else { 5895fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5896fcf5ef2aSThomas Huth } 5897fcf5ef2aSThomas Huth tcg_temp_free(t0); 5898fcf5ef2aSThomas Huth tcg_temp_free(t1); 5899fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5900fcf5ef2aSThomas Huth /* Update Rc0 */ 5901fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5902fcf5ef2aSThomas Huth } 5903fcf5ef2aSThomas Huth } 5904fcf5ef2aSThomas Huth 5905fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5906fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5907fcf5ef2aSThomas Huth { \ 5908fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5909fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5910fcf5ef2aSThomas Huth } 5911fcf5ef2aSThomas Huth 5912fcf5ef2aSThomas Huth /* macchw - macchw. */ 5913fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5914fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5915fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5916fcf5ef2aSThomas Huth /* macchws - macchws. */ 5917fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5918fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5919fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5920fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5921fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5922fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5923fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5924fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5925fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5926fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5927fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5928fcf5ef2aSThomas Huth /* machhw - machhw. */ 5929fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5930fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5931fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5932fcf5ef2aSThomas Huth /* machhws - machhws. */ 5933fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5934fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5935fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5936fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5937fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5938fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5939fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5940fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5941fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5942fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5943fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5944fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5945fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5946fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5947fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5948fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5949fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5950fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5951fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5952fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5953fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5954fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5955fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5956fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5957fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5958fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5959fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5960fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5961fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5962fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5963fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5964fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5965fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5966fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5967fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5968fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5969fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5970fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5971fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5972fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5973fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5974fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5975fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5976fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5977fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5978fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5979fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5980fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5981fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5982fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5983fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5984fcf5ef2aSThomas Huth 5985fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5986fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5987fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5988fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5989fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5990fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5991fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5992fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5993fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5994fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5995fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5996fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5997fcf5ef2aSThomas Huth 5998fcf5ef2aSThomas Huth /* mfdcr */ 5999fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6000fcf5ef2aSThomas Huth { 6001fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6002fcf5ef2aSThomas Huth GEN_PRIV; 6003fcf5ef2aSThomas Huth #else 6004fcf5ef2aSThomas Huth TCGv dcrn; 6005fcf5ef2aSThomas Huth 6006fcf5ef2aSThomas Huth CHK_SV; 6007fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6008fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6009fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6010fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6011fcf5ef2aSThomas Huth } 6012fcf5ef2aSThomas Huth 6013fcf5ef2aSThomas Huth /* mtdcr */ 6014fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6015fcf5ef2aSThomas Huth { 6016fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6017fcf5ef2aSThomas Huth GEN_PRIV; 6018fcf5ef2aSThomas Huth #else 6019fcf5ef2aSThomas Huth TCGv dcrn; 6020fcf5ef2aSThomas Huth 6021fcf5ef2aSThomas Huth CHK_SV; 6022fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6023fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6024fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6025fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6026fcf5ef2aSThomas Huth } 6027fcf5ef2aSThomas Huth 6028fcf5ef2aSThomas Huth /* mfdcrx */ 6029fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6030fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6031fcf5ef2aSThomas Huth { 6032fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6033fcf5ef2aSThomas Huth GEN_PRIV; 6034fcf5ef2aSThomas Huth #else 6035fcf5ef2aSThomas Huth CHK_SV; 6036fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6037fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6038fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6039fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6040fcf5ef2aSThomas Huth } 6041fcf5ef2aSThomas Huth 6042fcf5ef2aSThomas Huth /* mtdcrx */ 6043fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6044fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6045fcf5ef2aSThomas Huth { 6046fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6047fcf5ef2aSThomas Huth GEN_PRIV; 6048fcf5ef2aSThomas Huth #else 6049fcf5ef2aSThomas Huth CHK_SV; 6050fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6051fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6052fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6053fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6054fcf5ef2aSThomas Huth } 6055fcf5ef2aSThomas Huth 6056fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6057fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6058fcf5ef2aSThomas Huth { 6059fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6060fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6061fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6062fcf5ef2aSThomas Huth } 6063fcf5ef2aSThomas Huth 6064fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6065fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6066fcf5ef2aSThomas Huth { 6067fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6068fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6069fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6070fcf5ef2aSThomas Huth } 6071fcf5ef2aSThomas Huth 6072fcf5ef2aSThomas Huth /* dccci */ 6073fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6074fcf5ef2aSThomas Huth { 6075fcf5ef2aSThomas Huth CHK_SV; 6076fcf5ef2aSThomas Huth /* interpreted as no-op */ 6077fcf5ef2aSThomas Huth } 6078fcf5ef2aSThomas Huth 6079fcf5ef2aSThomas Huth /* dcread */ 6080fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6081fcf5ef2aSThomas Huth { 6082fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6083fcf5ef2aSThomas Huth GEN_PRIV; 6084fcf5ef2aSThomas Huth #else 6085fcf5ef2aSThomas Huth TCGv EA, val; 6086fcf5ef2aSThomas Huth 6087fcf5ef2aSThomas Huth CHK_SV; 6088fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6089fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6090fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6091fcf5ef2aSThomas Huth val = tcg_temp_new(); 6092fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6093fcf5ef2aSThomas Huth tcg_temp_free(val); 6094fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6095fcf5ef2aSThomas Huth tcg_temp_free(EA); 6096fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6097fcf5ef2aSThomas Huth } 6098fcf5ef2aSThomas Huth 6099fcf5ef2aSThomas Huth /* icbt */ 6100fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6101fcf5ef2aSThomas Huth { 6102fcf5ef2aSThomas Huth /* interpreted as no-op */ 6103fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6104fcf5ef2aSThomas Huth * but does not generate any exception 6105fcf5ef2aSThomas Huth */ 6106fcf5ef2aSThomas Huth } 6107fcf5ef2aSThomas Huth 6108fcf5ef2aSThomas Huth /* iccci */ 6109fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6110fcf5ef2aSThomas Huth { 6111fcf5ef2aSThomas Huth CHK_SV; 6112fcf5ef2aSThomas Huth /* interpreted as no-op */ 6113fcf5ef2aSThomas Huth } 6114fcf5ef2aSThomas Huth 6115fcf5ef2aSThomas Huth /* icread */ 6116fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6117fcf5ef2aSThomas Huth { 6118fcf5ef2aSThomas Huth CHK_SV; 6119fcf5ef2aSThomas Huth /* interpreted as no-op */ 6120fcf5ef2aSThomas Huth } 6121fcf5ef2aSThomas Huth 6122fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6123fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6124fcf5ef2aSThomas Huth { 6125fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6126fcf5ef2aSThomas Huth GEN_PRIV; 6127fcf5ef2aSThomas Huth #else 6128fcf5ef2aSThomas Huth CHK_SV; 6129fcf5ef2aSThomas Huth /* Restore CPU state */ 6130fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 6131fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6132fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6133fcf5ef2aSThomas Huth } 6134fcf5ef2aSThomas Huth 6135fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6136fcf5ef2aSThomas Huth { 6137fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6138fcf5ef2aSThomas Huth GEN_PRIV; 6139fcf5ef2aSThomas Huth #else 6140fcf5ef2aSThomas Huth CHK_SV; 6141fcf5ef2aSThomas Huth /* Restore CPU state */ 6142fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 6143fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6144fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6145fcf5ef2aSThomas Huth } 6146fcf5ef2aSThomas Huth 6147fcf5ef2aSThomas Huth /* BookE specific */ 6148fcf5ef2aSThomas Huth 6149fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6150fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6151fcf5ef2aSThomas Huth { 6152fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6153fcf5ef2aSThomas Huth GEN_PRIV; 6154fcf5ef2aSThomas Huth #else 6155fcf5ef2aSThomas Huth CHK_SV; 6156fcf5ef2aSThomas Huth /* Restore CPU state */ 6157fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 6158fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6159fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6160fcf5ef2aSThomas Huth } 6161fcf5ef2aSThomas Huth 6162fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6163fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6164fcf5ef2aSThomas Huth { 6165fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6166fcf5ef2aSThomas Huth GEN_PRIV; 6167fcf5ef2aSThomas Huth #else 6168fcf5ef2aSThomas Huth CHK_SV; 6169fcf5ef2aSThomas Huth /* Restore CPU state */ 6170fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 6171fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6172fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6173fcf5ef2aSThomas Huth } 6174fcf5ef2aSThomas Huth 6175fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6176fcf5ef2aSThomas Huth 6177fcf5ef2aSThomas Huth /* tlbre */ 6178fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6179fcf5ef2aSThomas Huth { 6180fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6181fcf5ef2aSThomas Huth GEN_PRIV; 6182fcf5ef2aSThomas Huth #else 6183fcf5ef2aSThomas Huth CHK_SV; 6184fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6185fcf5ef2aSThomas Huth case 0: 6186fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6187fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6188fcf5ef2aSThomas Huth break; 6189fcf5ef2aSThomas Huth case 1: 6190fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6191fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6192fcf5ef2aSThomas Huth break; 6193fcf5ef2aSThomas Huth default: 6194fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6195fcf5ef2aSThomas Huth break; 6196fcf5ef2aSThomas Huth } 6197fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6198fcf5ef2aSThomas Huth } 6199fcf5ef2aSThomas Huth 6200fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6201fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6202fcf5ef2aSThomas Huth { 6203fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6204fcf5ef2aSThomas Huth GEN_PRIV; 6205fcf5ef2aSThomas Huth #else 6206fcf5ef2aSThomas Huth TCGv t0; 6207fcf5ef2aSThomas Huth 6208fcf5ef2aSThomas Huth CHK_SV; 6209fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6210fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6211fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6212fcf5ef2aSThomas Huth tcg_temp_free(t0); 6213fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6214fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6215fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6216fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6217fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6218fcf5ef2aSThomas Huth gen_set_label(l1); 6219fcf5ef2aSThomas Huth } 6220fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6221fcf5ef2aSThomas Huth } 6222fcf5ef2aSThomas Huth 6223fcf5ef2aSThomas Huth /* tlbwe */ 6224fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6225fcf5ef2aSThomas Huth { 6226fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6227fcf5ef2aSThomas Huth GEN_PRIV; 6228fcf5ef2aSThomas Huth #else 6229fcf5ef2aSThomas Huth CHK_SV; 6230fcf5ef2aSThomas Huth 6231fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6232fcf5ef2aSThomas Huth case 0: 6233fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6234fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6235fcf5ef2aSThomas Huth break; 6236fcf5ef2aSThomas Huth case 1: 6237fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6238fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6239fcf5ef2aSThomas Huth break; 6240fcf5ef2aSThomas Huth default: 6241fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6242fcf5ef2aSThomas Huth break; 6243fcf5ef2aSThomas Huth } 6244fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6245fcf5ef2aSThomas Huth } 6246fcf5ef2aSThomas Huth 6247fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6248fcf5ef2aSThomas Huth 6249fcf5ef2aSThomas Huth /* tlbre */ 6250fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6251fcf5ef2aSThomas Huth { 6252fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6253fcf5ef2aSThomas Huth GEN_PRIV; 6254fcf5ef2aSThomas Huth #else 6255fcf5ef2aSThomas Huth CHK_SV; 6256fcf5ef2aSThomas Huth 6257fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6258fcf5ef2aSThomas Huth case 0: 6259fcf5ef2aSThomas Huth case 1: 6260fcf5ef2aSThomas Huth case 2: 6261fcf5ef2aSThomas Huth { 6262fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6263fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6264fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6265fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6266fcf5ef2aSThomas Huth } 6267fcf5ef2aSThomas Huth break; 6268fcf5ef2aSThomas Huth default: 6269fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6270fcf5ef2aSThomas Huth break; 6271fcf5ef2aSThomas Huth } 6272fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6273fcf5ef2aSThomas Huth } 6274fcf5ef2aSThomas Huth 6275fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6276fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6277fcf5ef2aSThomas Huth { 6278fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6279fcf5ef2aSThomas Huth GEN_PRIV; 6280fcf5ef2aSThomas Huth #else 6281fcf5ef2aSThomas Huth TCGv t0; 6282fcf5ef2aSThomas Huth 6283fcf5ef2aSThomas Huth CHK_SV; 6284fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6285fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6286fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6287fcf5ef2aSThomas Huth tcg_temp_free(t0); 6288fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6289fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6290fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6291fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6292fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6293fcf5ef2aSThomas Huth gen_set_label(l1); 6294fcf5ef2aSThomas Huth } 6295fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6296fcf5ef2aSThomas Huth } 6297fcf5ef2aSThomas Huth 6298fcf5ef2aSThomas Huth /* tlbwe */ 6299fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6300fcf5ef2aSThomas Huth { 6301fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6302fcf5ef2aSThomas Huth GEN_PRIV; 6303fcf5ef2aSThomas Huth #else 6304fcf5ef2aSThomas Huth CHK_SV; 6305fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6306fcf5ef2aSThomas Huth case 0: 6307fcf5ef2aSThomas Huth case 1: 6308fcf5ef2aSThomas Huth case 2: 6309fcf5ef2aSThomas Huth { 6310fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6311fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6312fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6313fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6314fcf5ef2aSThomas Huth } 6315fcf5ef2aSThomas Huth break; 6316fcf5ef2aSThomas Huth default: 6317fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6318fcf5ef2aSThomas Huth break; 6319fcf5ef2aSThomas Huth } 6320fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6321fcf5ef2aSThomas Huth } 6322fcf5ef2aSThomas Huth 6323fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6324fcf5ef2aSThomas Huth 6325fcf5ef2aSThomas Huth /* tlbre */ 6326fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6327fcf5ef2aSThomas Huth { 6328fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6329fcf5ef2aSThomas Huth GEN_PRIV; 6330fcf5ef2aSThomas Huth #else 6331fcf5ef2aSThomas Huth CHK_SV; 6332fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6333fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6334fcf5ef2aSThomas Huth } 6335fcf5ef2aSThomas Huth 6336fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6337fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6338fcf5ef2aSThomas Huth { 6339fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6340fcf5ef2aSThomas Huth GEN_PRIV; 6341fcf5ef2aSThomas Huth #else 6342fcf5ef2aSThomas Huth TCGv t0; 6343fcf5ef2aSThomas Huth 6344fcf5ef2aSThomas Huth CHK_SV; 6345fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6346fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6347fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6348fcf5ef2aSThomas Huth } else { 6349fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6350fcf5ef2aSThomas Huth } 6351fcf5ef2aSThomas Huth 6352fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6353fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6354fcf5ef2aSThomas Huth tcg_temp_free(t0); 6355fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6356fcf5ef2aSThomas Huth } 6357fcf5ef2aSThomas Huth 6358fcf5ef2aSThomas Huth /* tlbwe */ 6359fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6360fcf5ef2aSThomas Huth { 6361fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6362fcf5ef2aSThomas Huth GEN_PRIV; 6363fcf5ef2aSThomas Huth #else 6364fcf5ef2aSThomas Huth CHK_SV; 6365fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6366fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6367fcf5ef2aSThomas Huth } 6368fcf5ef2aSThomas Huth 6369fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6370fcf5ef2aSThomas Huth { 6371fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6372fcf5ef2aSThomas Huth GEN_PRIV; 6373fcf5ef2aSThomas Huth #else 6374fcf5ef2aSThomas Huth TCGv t0; 6375fcf5ef2aSThomas Huth 6376fcf5ef2aSThomas Huth CHK_SV; 6377fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6378fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6379fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6380fcf5ef2aSThomas Huth tcg_temp_free(t0); 6381fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6382fcf5ef2aSThomas Huth } 6383fcf5ef2aSThomas Huth 6384fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6385fcf5ef2aSThomas Huth { 6386fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6387fcf5ef2aSThomas Huth GEN_PRIV; 6388fcf5ef2aSThomas Huth #else 6389fcf5ef2aSThomas Huth TCGv t0; 6390fcf5ef2aSThomas Huth 6391fcf5ef2aSThomas Huth CHK_SV; 6392fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6393fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6394fcf5ef2aSThomas Huth 6395fcf5ef2aSThomas Huth switch((ctx->opcode >> 21) & 0x3) { 6396fcf5ef2aSThomas Huth case 0: 6397fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6398fcf5ef2aSThomas Huth break; 6399fcf5ef2aSThomas Huth case 1: 6400fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6401fcf5ef2aSThomas Huth break; 6402fcf5ef2aSThomas Huth case 3: 6403fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6404fcf5ef2aSThomas Huth break; 6405fcf5ef2aSThomas Huth default: 6406fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6407fcf5ef2aSThomas Huth break; 6408fcf5ef2aSThomas Huth } 6409fcf5ef2aSThomas Huth 6410fcf5ef2aSThomas Huth tcg_temp_free(t0); 6411fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6412fcf5ef2aSThomas Huth } 6413fcf5ef2aSThomas Huth 6414fcf5ef2aSThomas Huth 6415fcf5ef2aSThomas Huth /* wrtee */ 6416fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6417fcf5ef2aSThomas Huth { 6418fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6419fcf5ef2aSThomas Huth GEN_PRIV; 6420fcf5ef2aSThomas Huth #else 6421fcf5ef2aSThomas Huth TCGv t0; 6422fcf5ef2aSThomas Huth 6423fcf5ef2aSThomas Huth CHK_SV; 6424fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6425fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6426fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6427fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6428fcf5ef2aSThomas Huth tcg_temp_free(t0); 6429fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception 6430fcf5ef2aSThomas Huth * if we just set msr_ee to 1 6431fcf5ef2aSThomas Huth */ 6432fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6433fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6434fcf5ef2aSThomas Huth } 6435fcf5ef2aSThomas Huth 6436fcf5ef2aSThomas Huth /* wrteei */ 6437fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6438fcf5ef2aSThomas Huth { 6439fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6440fcf5ef2aSThomas Huth GEN_PRIV; 6441fcf5ef2aSThomas Huth #else 6442fcf5ef2aSThomas Huth CHK_SV; 6443fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6444fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6445fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6446fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6447fcf5ef2aSThomas Huth } else { 6448fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6449fcf5ef2aSThomas Huth } 6450fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6451fcf5ef2aSThomas Huth } 6452fcf5ef2aSThomas Huth 6453fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6454fcf5ef2aSThomas Huth 6455fcf5ef2aSThomas Huth /* dlmzb */ 6456fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6457fcf5ef2aSThomas Huth { 6458fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6459fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6460fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6461fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6462fcf5ef2aSThomas Huth } 6463fcf5ef2aSThomas Huth 6464fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6465fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6466fcf5ef2aSThomas Huth { 6467fcf5ef2aSThomas Huth /* interpreted as no-op */ 6468fcf5ef2aSThomas Huth } 6469fcf5ef2aSThomas Huth 6470fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6471fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6472fcf5ef2aSThomas Huth { 647327a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 647427a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 647527a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 647627a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 647727a3ea7eSBALATON Zoltan } 647827a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6479fcf5ef2aSThomas Huth } 6480fcf5ef2aSThomas Huth 6481fcf5ef2aSThomas Huth /* icbt */ 6482fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6483fcf5ef2aSThomas Huth { 6484fcf5ef2aSThomas Huth /* interpreted as no-op */ 6485fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6486fcf5ef2aSThomas Huth * but does not generate any exception 6487fcf5ef2aSThomas Huth */ 6488fcf5ef2aSThomas Huth } 6489fcf5ef2aSThomas Huth 6490fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6491fcf5ef2aSThomas Huth 6492fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6493fcf5ef2aSThomas Huth { 6494fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6495fcf5ef2aSThomas Huth GEN_PRIV; 6496fcf5ef2aSThomas Huth #else 6497ebca5e6dSCédric Le Goater CHK_HV; 64987af1e7b0SCédric Le Goater /* 64-bit server processors compliant with arch 2.x */ 64997af1e7b0SCédric Le Goater if (ctx->insns_flags & PPC_SEGMENT_64B) { 65007af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 65017af1e7b0SCédric Le Goater } else { 6502fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 65037af1e7b0SCédric Le Goater } 6504fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6505fcf5ef2aSThomas Huth } 6506fcf5ef2aSThomas Huth 6507fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6508fcf5ef2aSThomas Huth { 6509fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6510fcf5ef2aSThomas Huth GEN_PRIV; 6511fcf5ef2aSThomas Huth #else 6512ebca5e6dSCédric Le Goater CHK_HV; 65137af1e7b0SCédric Le Goater /* 64-bit server processors compliant with arch 2.x */ 65147af1e7b0SCédric Le Goater if (ctx->insns_flags & PPC_SEGMENT_64B) { 65157af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 65167af1e7b0SCédric Le Goater } else { 6517fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 65187af1e7b0SCédric Le Goater } 6519fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6520fcf5ef2aSThomas Huth } 6521fcf5ef2aSThomas Huth 65227af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 65237af1e7b0SCédric Le Goater { 65247af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 65257af1e7b0SCédric Le Goater GEN_PRIV; 65267af1e7b0SCédric Le Goater #else 65277af1e7b0SCédric Le Goater CHK_HV; 65287af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 65297af1e7b0SCédric Le Goater /* interpreted as no-op */ 65307af1e7b0SCédric Le Goater } 6531fcf5ef2aSThomas Huth 6532fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6533fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6534fcf5ef2aSThomas Huth { 6535fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6536fcf5ef2aSThomas Huth 6537fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6538fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6539fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6540fcf5ef2aSThomas Huth } 6541fcf5ef2aSThomas Huth 6542fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6543fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6544fcf5ef2aSThomas Huth { 6545fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6546fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6547fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6548fcf5ef2aSThomas Huth 6549fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6550fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6551fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6552fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6553fcf5ef2aSThomas Huth } else { 6554fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6555fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6556fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6557fcf5ef2aSThomas Huth } 6558fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6559fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6560fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6561fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6562fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6563fcf5ef2aSThomas Huth } 6564fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6565fcf5ef2aSThomas Huth 6566fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6567fcf5ef2aSThomas Huth { 6568fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6569fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6570fcf5ef2aSThomas Huth return; 6571fcf5ef2aSThomas Huth } 6572fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6573fcf5ef2aSThomas Huth } 6574fcf5ef2aSThomas Huth 6575fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6576fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6577fcf5ef2aSThomas Huth { \ 6578fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6579fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6580fcf5ef2aSThomas Huth return; \ 6581fcf5ef2aSThomas Huth } \ 6582fcf5ef2aSThomas Huth /* Because tbegin always fails in QEMU, these user \ 6583fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6584fcf5ef2aSThomas Huth * \ 6585fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6586fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6587fcf5ef2aSThomas Huth */ \ 6588fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6589fcf5ef2aSThomas Huth } 6590fcf5ef2aSThomas Huth 6591fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6592fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6593fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6594fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6595fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6596fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6597fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6598b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6599b8b4576eSSuraj Jitindar Singh { 6600b8b4576eSSuraj Jitindar Singh // Do Nothing 6601b8b4576eSSuraj Jitindar Singh } 6602fcf5ef2aSThomas Huth 660380b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 660480b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 660580b8c1eeSNikunj A Dadhania { \ 660680b8c1eeSNikunj A Dadhania /* Generate invalid exception until \ 660780b8c1eeSNikunj A Dadhania * we have an implementation of the copy \ 660880b8c1eeSNikunj A Dadhania * paste facility \ 660980b8c1eeSNikunj A Dadhania */ \ 661080b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 661180b8c1eeSNikunj A Dadhania } 661280b8c1eeSNikunj A Dadhania 661380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 661480b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 661580b8c1eeSNikunj A Dadhania 6616fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6617fcf5ef2aSThomas Huth { 6618fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6619fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6620fcf5ef2aSThomas Huth return; 6621fcf5ef2aSThomas Huth } 6622fcf5ef2aSThomas Huth /* Because tbegin always fails, the tcheck implementation 6623fcf5ef2aSThomas Huth * is simple: 6624fcf5ef2aSThomas Huth * 6625fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6626fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6627fcf5ef2aSThomas Huth */ 6628fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6629fcf5ef2aSThomas Huth } 6630fcf5ef2aSThomas Huth 6631fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6632fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6633fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6634fcf5ef2aSThomas Huth { \ 6635fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6636fcf5ef2aSThomas Huth } 6637fcf5ef2aSThomas Huth 6638fcf5ef2aSThomas Huth #else 6639fcf5ef2aSThomas Huth 6640fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6641fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6642fcf5ef2aSThomas Huth { \ 6643fcf5ef2aSThomas Huth CHK_SV; \ 6644fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6645fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6646fcf5ef2aSThomas Huth return; \ 6647fcf5ef2aSThomas Huth } \ 6648fcf5ef2aSThomas Huth /* Because tbegin always fails, the implementation is \ 6649fcf5ef2aSThomas Huth * simple: \ 6650fcf5ef2aSThomas Huth * \ 6651fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6652fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6653fcf5ef2aSThomas Huth */ \ 6654fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6655fcf5ef2aSThomas Huth } 6656fcf5ef2aSThomas Huth 6657fcf5ef2aSThomas Huth #endif 6658fcf5ef2aSThomas Huth 6659fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6660fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6661fcf5ef2aSThomas Huth 66621a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 66631a404c91SMark Cave-Ayland { 6664ef96e3aeSMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); 66651a404c91SMark Cave-Ayland } 66661a404c91SMark Cave-Ayland 66671a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 66681a404c91SMark Cave-Ayland { 6669ef96e3aeSMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); 66701a404c91SMark Cave-Ayland } 66711a404c91SMark Cave-Ayland 6672c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6673c4a18dbfSMark Cave-Ayland { 66747329fb62SMark Cave-Ayland #ifdef HOST_WORDS_BIGENDIAN 66757329fb62SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, 6676ef96e3aeSMark Cave-Ayland vsr[32 + regno].u64[(high ? 0 : 1)])); 66777329fb62SMark Cave-Ayland #else 66787329fb62SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, 6679ef96e3aeSMark Cave-Ayland vsr[32 + regno].u64[(high ? 1 : 0)])); 66807329fb62SMark Cave-Ayland #endif 6681c4a18dbfSMark Cave-Ayland } 6682c4a18dbfSMark Cave-Ayland 6683c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6684c4a18dbfSMark Cave-Ayland { 66857329fb62SMark Cave-Ayland #ifdef HOST_WORDS_BIGENDIAN 66867329fb62SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, 6687ef96e3aeSMark Cave-Ayland vsr[32 + regno].u64[(high ? 0 : 1)])); 66887329fb62SMark Cave-Ayland #else 66897329fb62SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, 6690ef96e3aeSMark Cave-Ayland vsr[32 + regno].u64[(high ? 1 : 0)])); 66917329fb62SMark Cave-Ayland #endif 6692c4a18dbfSMark Cave-Ayland } 6693c4a18dbfSMark Cave-Ayland 6694fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6695fcf5ef2aSThomas Huth 6696fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6697fcf5ef2aSThomas Huth 6698fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6699fcf5ef2aSThomas Huth 6700fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6701fcf5ef2aSThomas Huth 6702fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6703fcf5ef2aSThomas Huth 67045cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 67055cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 67065cb091a4SNikunj A Dadhania { 67075cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 67085cb091a4SNikunj A Dadhania case 0: /* lfdp */ 67095cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 67105cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 67115cb091a4SNikunj A Dadhania } 67125cb091a4SNikunj A Dadhania break; 67135cb091a4SNikunj A Dadhania case 2: /* lxsd */ 67145cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 67155cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 67165cb091a4SNikunj A Dadhania } 67175cb091a4SNikunj A Dadhania break; 67185cb091a4SNikunj A Dadhania case 3: /* lxssp */ 67195cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 67205cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 67215cb091a4SNikunj A Dadhania } 67225cb091a4SNikunj A Dadhania break; 67235cb091a4SNikunj A Dadhania } 67245cb091a4SNikunj A Dadhania return gen_invalid(ctx); 67255cb091a4SNikunj A Dadhania } 67265cb091a4SNikunj A Dadhania 6727d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6728e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6729e3001664SNikunj A Dadhania { 6730e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6731e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6732e3001664SNikunj A Dadhania case 1: /* lxv */ 6733d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6734d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6735d59ba583SNikunj A Dadhania } 6736e3001664SNikunj A Dadhania break; 6737e3001664SNikunj A Dadhania case 5: /* stxv */ 6738d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6739d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6740d59ba583SNikunj A Dadhania } 6741e3001664SNikunj A Dadhania break; 6742e3001664SNikunj A Dadhania } 6743e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6744e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6745e3001664SNikunj A Dadhania case 0: /* stfdp */ 6746e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6747e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6748e3001664SNikunj A Dadhania } 6749e3001664SNikunj A Dadhania break; 6750e3001664SNikunj A Dadhania case 2: /* stxsd */ 6751e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6752e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6753e3001664SNikunj A Dadhania } 6754e3001664SNikunj A Dadhania break; 6755e3001664SNikunj A Dadhania case 3: /* stxssp */ 6756e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6757e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6758e3001664SNikunj A Dadhania } 6759e3001664SNikunj A Dadhania break; 6760e3001664SNikunj A Dadhania } 6761e3001664SNikunj A Dadhania } 6762e3001664SNikunj A Dadhania return gen_invalid(ctx); 6763e3001664SNikunj A Dadhania } 6764e3001664SNikunj A Dadhania 6765fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6766fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6767fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6768fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6769fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6770fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6771fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6772fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6773fcf5ef2aSThomas Huth #endif 6774fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6775fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6776fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6777fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6778fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6779fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6780fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6781fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6782fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6783fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6784fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6785fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6786fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6787fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6788fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6789fcf5ef2aSThomas Huth #endif 6790fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6791fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6792fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6793fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6794fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6795fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6796fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 679780b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6798b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 679980b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6800fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6801fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6802fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6803fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6804fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6805fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6806fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6807fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6808fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6809fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6810fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6811fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6812fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6813fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6814fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6815fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6816fcf5ef2aSThomas Huth #endif 6817fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6818fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6819fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6820fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6821fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6822fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6823fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6824fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6825fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6826fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6827fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6828fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6829fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6830fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6831fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6832fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6833fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6834fcf5ef2aSThomas Huth #endif 6835fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6836fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6837fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6838fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6839fcf5ef2aSThomas Huth #endif 68405cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 68415cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6842d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6843e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6844fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6845fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6846fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6847fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6848fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6849fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6850c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6851fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6852fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6853fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6854fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6855a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6856a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6857fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6858fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6859fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6860fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6861a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6862a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6863fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6864fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6865fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6866fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6867fcf5ef2aSThomas Huth #endif 6868fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6869fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6870c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6871fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6872fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6873fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6874fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6875fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6876fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6877fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6878fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6879fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6880cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6881fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6882fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6883fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6884fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6885fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6886fcf5ef2aSThomas Huth #endif 6887fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6888fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6889fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6890fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6891fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6892fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6893fcf5ef2aSThomas Huth #endif 6894fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6895fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6896fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6897fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6898fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6899fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6900fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6901fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6902fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6903b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6904fcf5ef2aSThomas Huth #endif 6905fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6906fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6907fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 690850728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6909fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6910fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 691150728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6912fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 691350728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6914fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 691550728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6916fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6917fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 691850728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6919fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 692099d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6921fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6922fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 692350728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6924fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6925fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6926fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6927fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6928fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6929fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6930fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6931fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6932fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6933fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6934fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6935fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6936fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6937fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6938fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6939fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6940fcf5ef2aSThomas Huth #endif 6941fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6942fcf5ef2aSThomas Huth /* XXX Those instructions will need to be handled differently for 6943fcf5ef2aSThomas Huth * different ISA versions */ 6944fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6945fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6946c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 6947c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 6948fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6949fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6950fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6951fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6952a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 695362d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6954fcf5ef2aSThomas Huth #endif 6955fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6956fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6957fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6958fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6959fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6960fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6961fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6962fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6963fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6964fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6965fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6966fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6967fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6968fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6969fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6970fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6971fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6972fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6973fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6974fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6975fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6976fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6977fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6978fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6979fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6980fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6981fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6982fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6983fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6984fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6985fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6986fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6987fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6988fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6989fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6990fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6991fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6992fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6993fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6994fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6995fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6996fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6997fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6998fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6999fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7000fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7001fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7002fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7003fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7004fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7005fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7006fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7007fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7008fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7009fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7010fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7011fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7012fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7013fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7014fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7015fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7016fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7017fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7018fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7019fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7020fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7021fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7022fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7023fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7024fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7025fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7026fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7027fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7028fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7029fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7030fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7031fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7032fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7033fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7034fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7035fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7036fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7037fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7038fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7039fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7040fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7041fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7042fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7043fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7044fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7045fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7046fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7047fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7048fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 70497af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 70507af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7051fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7052fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7053fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7054fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7055fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 705627a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7057fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7058fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 70590c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 70600c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7061fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7062fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7063fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7064fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7065fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7066fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7067fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7068fcf5ef2aSThomas Huth PPC2_ISA300), 7069fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7070fcf5ef2aSThomas Huth #endif 7071fcf5ef2aSThomas Huth 7072fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7073fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7074fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7075fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7076fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7077fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7078fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7079fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7080fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7081fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7082fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7083fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7084fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7085fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7086fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 70874c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7088fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7089fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7090fcf5ef2aSThomas Huth 7091fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7092fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7093fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7094fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7095fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7096fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7097fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7098fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7099fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7100fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7101fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7102fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7103fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7104fcf5ef2aSThomas Huth 7105fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7106fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7107fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7108fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7109fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7110fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7111fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7112fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7113fcf5ef2aSThomas Huth 7114fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7115fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7116fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7117fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7118fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7119fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7120fcf5ef2aSThomas Huth 7121fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7122fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7123fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7124fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7125fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7126fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7127fcf5ef2aSThomas Huth #endif 7128fcf5ef2aSThomas Huth 7129fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7130fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7131fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7132fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7133fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7134fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7135fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7136fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7137fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7138fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7139fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7140fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7141fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7142fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7143fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7144fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7145fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7146fcf5ef2aSThomas Huth 7147fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7148fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7149fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7150fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7151fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7152fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7153fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7154fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7155fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7156fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7157fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7158fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7159fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7160fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7161fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7162fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7163fcf5ef2aSThomas Huth #endif 7164fcf5ef2aSThomas Huth 7165fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7166fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7167fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7168fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7169fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7170fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7171fcf5ef2aSThomas Huth PPC_64B) 7172fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7173fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7174fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7175fcf5ef2aSThomas Huth PPC_64B), \ 7176fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7177fcf5ef2aSThomas Huth PPC_64B), \ 7178fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7179fcf5ef2aSThomas Huth PPC_64B) 7180fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7181fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7182fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7183fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7184fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7185fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7186fcf5ef2aSThomas Huth #endif 7187fcf5ef2aSThomas Huth 7188fcf5ef2aSThomas Huth #undef GEN_LD 7189fcf5ef2aSThomas Huth #undef GEN_LDU 7190fcf5ef2aSThomas Huth #undef GEN_LDUX 7191fcf5ef2aSThomas Huth #undef GEN_LDX_E 7192fcf5ef2aSThomas Huth #undef GEN_LDS 7193fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 7194fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7195fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 7196fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7197fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7198fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7199fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7200fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7201fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 7202fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 7203fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 7204fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7205fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7206fcf5ef2aSThomas Huth 7207fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7208fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7209fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7210fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7211fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7212fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7213fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7214fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7215fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7216fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7217fcf5ef2aSThomas Huth 7218fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7219fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7220fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7221fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7222fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7223fcf5ef2aSThomas Huth #endif 7224fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7225fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7226fcf5ef2aSThomas Huth 722750728199SRoman Kapl /* External PID based load */ 722850728199SRoman Kapl #undef GEN_LDEPX 722950728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 723050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 723150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 723250728199SRoman Kapl 723350728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 723450728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 723550728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 723650728199SRoman Kapl #if defined(TARGET_PPC64) 723750728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 723850728199SRoman Kapl #endif 723950728199SRoman Kapl 7240fcf5ef2aSThomas Huth #undef GEN_ST 7241fcf5ef2aSThomas Huth #undef GEN_STU 7242fcf5ef2aSThomas Huth #undef GEN_STUX 7243fcf5ef2aSThomas Huth #undef GEN_STX_E 7244fcf5ef2aSThomas Huth #undef GEN_STS 7245fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 7246fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7247fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 7248fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7249fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 7250fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7251fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 72520123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7253fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 7254fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 7255fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 7256fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7257fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 7258fcf5ef2aSThomas Huth 7259fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7260fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7261fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7262fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7263fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7264fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7265fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7266fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7267fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7268fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7269fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7270fcf5ef2aSThomas Huth #endif 7271fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7272fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7273fcf5ef2aSThomas Huth 727450728199SRoman Kapl #undef GEN_STEPX 727550728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 727650728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 727750728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 727850728199SRoman Kapl 727950728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 728050728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 728150728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 728250728199SRoman Kapl #if defined(TARGET_PPC64) 728350728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 728450728199SRoman Kapl #endif 728550728199SRoman Kapl 7286fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7287fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7288fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7289fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7290fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7291fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7292fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7293fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7294fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7295fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7296fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7297fcf5ef2aSThomas Huth 7298fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7299fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7300fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7301fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7302fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7303fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7304fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7305fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7306fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7307fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7308fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7309fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7310fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7311fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7312fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7313fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7314fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7315fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7316fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7317fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7318fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7319fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7320fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7321fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7322fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7323fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7324fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7325fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7326fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7327fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7328fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7329fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7330fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7331fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7332fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7333fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7334fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7335fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7336fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7337fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7338fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7339fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7340fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7341fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7342fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7343fcf5ef2aSThomas Huth 7344fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7345fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7346fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7347fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7348fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7349fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7350fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7351fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7352fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7353fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7354fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7355fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7356fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7357fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7358fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7359fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7360fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7361fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7362fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7363fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7364fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7365fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7366fcf5ef2aSThomas Huth 7367fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 7368fcf5ef2aSThomas Huth 7369fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 7370fcf5ef2aSThomas Huth 7371fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 7372fcf5ef2aSThomas Huth 7373fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 7374fcf5ef2aSThomas Huth 7375fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 7376fcf5ef2aSThomas Huth }; 7377fcf5ef2aSThomas Huth 7378fcf5ef2aSThomas Huth #include "helper_regs.h" 73795b27a92dSPaolo Bonzini #include "translate_init.inc.c" 7380fcf5ef2aSThomas Huth 7381fcf5ef2aSThomas Huth /*****************************************************************************/ 7382fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 7383fcf5ef2aSThomas Huth void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 7384fcf5ef2aSThomas Huth int flags) 7385fcf5ef2aSThomas Huth { 7386fcf5ef2aSThomas Huth #define RGPL 4 7387fcf5ef2aSThomas Huth #define RFPL 4 7388fcf5ef2aSThomas Huth 7389fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7390fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 7391fcf5ef2aSThomas Huth int i; 7392fcf5ef2aSThomas Huth 7393fcf5ef2aSThomas Huth cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7394fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7395fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 7396fcf5ef2aSThomas Huth cs->cpu_index); 7397fcf5ef2aSThomas Huth cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7398fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 7399fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 7400fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 7401fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 7402fcf5ef2aSThomas Huth cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7403fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7404fcf5ef2aSThomas Huth " DECR %08" PRIu32 7405fcf5ef2aSThomas Huth #endif 7406fcf5ef2aSThomas Huth "\n", 7407fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7408fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7409fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 7410fcf5ef2aSThomas Huth #endif 7411fcf5ef2aSThomas Huth ); 7412fcf5ef2aSThomas Huth #endif 7413fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7414fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == 0) 7415fcf5ef2aSThomas Huth cpu_fprintf(f, "GPR%02d", i); 7416fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7417fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == (RGPL - 1)) 7418fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7419fcf5ef2aSThomas Huth } 7420fcf5ef2aSThomas Huth cpu_fprintf(f, "CR "); 7421fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 7422fcf5ef2aSThomas Huth cpu_fprintf(f, "%01x", env->crf[i]); 7423fcf5ef2aSThomas Huth cpu_fprintf(f, " ["); 7424fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 7425fcf5ef2aSThomas Huth char a = '-'; 7426fcf5ef2aSThomas Huth if (env->crf[i] & 0x08) 7427fcf5ef2aSThomas Huth a = 'L'; 7428fcf5ef2aSThomas Huth else if (env->crf[i] & 0x04) 7429fcf5ef2aSThomas Huth a = 'G'; 7430fcf5ef2aSThomas Huth else if (env->crf[i] & 0x02) 7431fcf5ef2aSThomas Huth a = 'E'; 7432fcf5ef2aSThomas Huth cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7433fcf5ef2aSThomas Huth } 7434fcf5ef2aSThomas Huth cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7435fcf5ef2aSThomas Huth env->reserve_addr); 7436685f1ce2SRichard Henderson 7437685f1ce2SRichard Henderson if (flags & CPU_DUMP_FPU) { 7438fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7439685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == 0) { 7440fcf5ef2aSThomas Huth cpu_fprintf(f, "FPR%02d", i); 7441685f1ce2SRichard Henderson } 7442ef96e3aeSMark Cave-Ayland cpu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7443685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == (RFPL - 1)) { 7444fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7445fcf5ef2aSThomas Huth } 7446685f1ce2SRichard Henderson } 7447fcf5ef2aSThomas Huth cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7448685f1ce2SRichard Henderson } 7449685f1ce2SRichard Henderson 7450fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7451fcf5ef2aSThomas Huth cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7452fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7453fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7454fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7455fcf5ef2aSThomas Huth 7456fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7457fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7458fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7459fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7460fcf5ef2aSThomas Huth 7461fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7462fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7463fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7464fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7465fcf5ef2aSThomas Huth 7466fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7467fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7468fcf5ef2aSThomas Huth env->excp_model == POWERPC_EXCP_POWER8) { 7469fcf5ef2aSThomas Huth cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7470fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7471fcf5ef2aSThomas Huth } 7472fcf5ef2aSThomas Huth #endif 7473fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 7474fcf5ef2aSThomas Huth cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7475fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7476fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7477fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7478fcf5ef2aSThomas Huth 7479fcf5ef2aSThomas Huth cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7480fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7481fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7482fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7483fcf5ef2aSThomas Huth 7484fcf5ef2aSThomas Huth cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7485fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7486fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7487fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7488fcf5ef2aSThomas Huth 7489fcf5ef2aSThomas Huth cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7490fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7491fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7492fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7493fcf5ef2aSThomas Huth 7494fcf5ef2aSThomas Huth /* FSL-specific */ 7495fcf5ef2aSThomas Huth cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7496fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7497fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7498fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7499fcf5ef2aSThomas Huth 7500fcf5ef2aSThomas Huth /* 7501fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7502fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7503fcf5ef2aSThomas Huth */ 7504fcf5ef2aSThomas Huth } 7505fcf5ef2aSThomas Huth 7506fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7507fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 7508fcf5ef2aSThomas Huth cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7509fcf5ef2aSThomas Huth } 7510fcf5ef2aSThomas Huth #endif 7511fcf5ef2aSThomas Huth 7512d801a61eSSuraj Jitindar Singh if (env->spr_cb[SPR_LPCR].name) 7513d801a61eSSuraj Jitindar Singh cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7514d801a61eSSuraj Jitindar Singh 75150941d728SDavid Gibson switch (env->mmu_model) { 7516fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7517fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7518fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7519fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7520fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 75210941d728SDavid Gibson case POWERPC_MMU_64B: 75220941d728SDavid Gibson case POWERPC_MMU_2_03: 75230941d728SDavid Gibson case POWERPC_MMU_2_06: 75240941d728SDavid Gibson case POWERPC_MMU_2_07: 75250941d728SDavid Gibson case POWERPC_MMU_3_00: 7526fcf5ef2aSThomas Huth #endif 75274f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 75284f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 75294f4f28ffSSuraj Jitindar Singh } 75304a7518e0SCédric Le Goater if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 75314a7518e0SCédric Le Goater cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 75324a7518e0SCédric Le Goater } 75334f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7534fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7535fcf5ef2aSThomas Huth break; 7536fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 7537fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7538fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7539fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7540fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7541fcf5ef2aSThomas Huth 7542fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7543fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7544fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7545fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7546fcf5ef2aSThomas Huth 7547fcf5ef2aSThomas Huth cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7548fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7549fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7550fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7551fcf5ef2aSThomas Huth break; 7552fcf5ef2aSThomas Huth default: 7553fcf5ef2aSThomas Huth break; 7554fcf5ef2aSThomas Huth } 7555fcf5ef2aSThomas Huth #endif 7556fcf5ef2aSThomas Huth 7557fcf5ef2aSThomas Huth #undef RGPL 7558fcf5ef2aSThomas Huth #undef RFPL 7559fcf5ef2aSThomas Huth } 7560fcf5ef2aSThomas Huth 7561fcf5ef2aSThomas Huth void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7562fcf5ef2aSThomas Huth fprintf_function cpu_fprintf, int flags) 7563fcf5ef2aSThomas Huth { 7564fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7565fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7566fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7567fcf5ef2aSThomas Huth int op1, op2, op3; 7568fcf5ef2aSThomas Huth 7569fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7570fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7571fcf5ef2aSThomas Huth handler = t1[op1]; 7572fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7573fcf5ef2aSThomas Huth t2 = ind_table(handler); 7574fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7575fcf5ef2aSThomas Huth handler = t2[op2]; 7576fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7577fcf5ef2aSThomas Huth t3 = ind_table(handler); 7578fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7579fcf5ef2aSThomas Huth handler = t3[op3]; 7580fcf5ef2aSThomas Huth if (handler->count == 0) 7581fcf5ef2aSThomas Huth continue; 7582fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7583fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7584fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7585fcf5ef2aSThomas Huth handler->oname, 7586fcf5ef2aSThomas Huth handler->count, handler->count); 7587fcf5ef2aSThomas Huth } 7588fcf5ef2aSThomas Huth } else { 7589fcf5ef2aSThomas Huth if (handler->count == 0) 7590fcf5ef2aSThomas Huth continue; 7591fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7592fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7593fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7594fcf5ef2aSThomas Huth handler->count, handler->count); 7595fcf5ef2aSThomas Huth } 7596fcf5ef2aSThomas Huth } 7597fcf5ef2aSThomas Huth } else { 7598fcf5ef2aSThomas Huth if (handler->count == 0) 7599fcf5ef2aSThomas Huth continue; 7600fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7601fcf5ef2aSThomas Huth " %" PRId64 "\n", 7602fcf5ef2aSThomas Huth op1, op1, handler->oname, 7603fcf5ef2aSThomas Huth handler->count, handler->count); 7604fcf5ef2aSThomas Huth } 7605fcf5ef2aSThomas Huth } 7606fcf5ef2aSThomas Huth #endif 7607fcf5ef2aSThomas Huth } 7608fcf5ef2aSThomas Huth 7609b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7610fcf5ef2aSThomas Huth { 7611b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 76129c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 7613b0c2d521SEmilio G. Cota int bound; 7614fcf5ef2aSThomas Huth 7615b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 7616b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 7617b0c2d521SEmilio G. Cota ctx->pr = msr_pr; 7618b0c2d521SEmilio G. Cota ctx->mem_idx = env->dmmu_idx; 7619b0c2d521SEmilio G. Cota ctx->dr = msr_dr; 7620fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7621b0c2d521SEmilio G. Cota ctx->hv = msr_hv || !env->has_hv_mode; 7622fcf5ef2aSThomas Huth #endif 7623b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7624b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7625b0c2d521SEmilio G. Cota ctx->access_type = -1; 7626b0c2d521SEmilio G. Cota ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7627b0c2d521SEmilio G. Cota ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7628b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 76290e3bf489SRoman Kapl ctx->flags = env->flags; 7630fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7631b0c2d521SEmilio G. Cota ctx->sf_mode = msr_is_64bit(env, env->msr); 7632b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7633fcf5ef2aSThomas Huth #endif 7634e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7635e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 7636e69ba2b4SDavid Gibson || (env->mmu_model & POWERPC_MMU_64B); 7637fcf5ef2aSThomas Huth 7638b0c2d521SEmilio G. Cota ctx->fpu_enabled = !!msr_fp; 7639fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7640b0c2d521SEmilio G. Cota ctx->spe_enabled = !!msr_spe; 7641fcf5ef2aSThomas Huth else 7642b0c2d521SEmilio G. Cota ctx->spe_enabled = false; 7643fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7644b0c2d521SEmilio G. Cota ctx->altivec_enabled = !!msr_vr; 7645fcf5ef2aSThomas Huth else 7646b0c2d521SEmilio G. Cota ctx->altivec_enabled = false; 7647fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7648b0c2d521SEmilio G. Cota ctx->vsx_enabled = !!msr_vsx; 7649fcf5ef2aSThomas Huth } else { 7650b0c2d521SEmilio G. Cota ctx->vsx_enabled = false; 7651fcf5ef2aSThomas Huth } 7652fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7653fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7654b0c2d521SEmilio G. Cota ctx->tm_enabled = !!msr_tm; 7655fcf5ef2aSThomas Huth } else { 7656b0c2d521SEmilio G. Cota ctx->tm_enabled = false; 7657fcf5ef2aSThomas Huth } 7658fcf5ef2aSThomas Huth #endif 7659b0c2d521SEmilio G. Cota ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7660fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7661b0c2d521SEmilio G. Cota ctx->singlestep_enabled = CPU_SINGLE_STEP; 7662fcf5ef2aSThomas Huth else 7663b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 7664fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7665b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 76660e3bf489SRoman Kapl if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 76670e3bf489SRoman Kapl ctx->singlestep_enabled = 0; 76680e3bf489SRoman Kapl target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 76690e3bf489SRoman Kapl if (dbcr0 & DBCR0_ICMP) { 76700e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_SINGLE_STEP; 76710e3bf489SRoman Kapl } 76720e3bf489SRoman Kapl if (dbcr0 & DBCR0_BRT) { 76730e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_BRANCH_STEP; 76740e3bf489SRoman Kapl } 76750e3bf489SRoman Kapl 76760e3bf489SRoman Kapl } 7677b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7678b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7679fcf5ef2aSThomas Huth } 7680fcf5ef2aSThomas Huth #if defined (DO_SINGLE_STEP) && 0 7681fcf5ef2aSThomas Huth /* Single step trace mode */ 7682fcf5ef2aSThomas Huth msr_se = 1; 7683fcf5ef2aSThomas Huth #endif 7684b0c2d521SEmilio G. Cota 7685b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7686b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7687fcf5ef2aSThomas Huth } 7688fcf5ef2aSThomas Huth 7689b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7690b0c2d521SEmilio G. Cota { 7691b0c2d521SEmilio G. Cota } 7692fcf5ef2aSThomas Huth 7693b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7694b0c2d521SEmilio G. Cota { 7695b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7696b0c2d521SEmilio G. Cota } 7697b0c2d521SEmilio G. Cota 7698b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7699b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 7700b0c2d521SEmilio G. Cota { 7701b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7702b0c2d521SEmilio G. Cota 7703b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 77042a8ceefcSEmilio G. Cota dcbase->is_jmp = DISAS_NORETURN; 7705fcf5ef2aSThomas Huth /* The address covered by the breakpoint must be included in 7706fcf5ef2aSThomas Huth [tb->pc, tb->pc + tb->size) in order to for it to be 7707fcf5ef2aSThomas Huth properly cleared -- thus we increment the PC here so that 7708fcf5ef2aSThomas Huth the logic setting tb->size below does the right thing. */ 7709b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7710b0c2d521SEmilio G. Cota return true; 7711fcf5ef2aSThomas Huth } 7712fcf5ef2aSThomas Huth 7713b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7714b0c2d521SEmilio G. Cota { 7715b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7716b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 7717b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 7718b0c2d521SEmilio G. Cota 7719fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7720fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7721b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7722b0c2d521SEmilio G. Cota 7723b0c2d521SEmilio G. Cota if (unlikely(need_byteswap(ctx))) { 7724b0c2d521SEmilio G. Cota ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); 7725fcf5ef2aSThomas Huth } else { 7726b0c2d521SEmilio G. Cota ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); 7727fcf5ef2aSThomas Huth } 7728fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7729b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7730b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7731b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 7732b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7733fcf5ef2aSThomas Huth table = env->opcodes; 7734b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 7735fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7736fcf5ef2aSThomas Huth table = ind_table(handler); 7737b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 7738fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7739fcf5ef2aSThomas Huth table = ind_table(handler); 7740b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 7741fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7742fcf5ef2aSThomas Huth table = ind_table(handler); 7743b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 7744fcf5ef2aSThomas Huth } 7745fcf5ef2aSThomas Huth } 7746fcf5ef2aSThomas Huth } 7747fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7748fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7749fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7750fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7751fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7752b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7753b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7754b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7755fcf5ef2aSThomas Huth } else { 7756fcf5ef2aSThomas Huth uint32_t inval; 7757fcf5ef2aSThomas Huth 7758b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7759b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 7760fcf5ef2aSThomas Huth inval = handler->inval2; 7761fcf5ef2aSThomas Huth } else { 7762fcf5ef2aSThomas Huth inval = handler->inval1; 7763fcf5ef2aSThomas Huth } 7764fcf5ef2aSThomas Huth 7765b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 7766fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7767fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7768b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 7769b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7770b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7771b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4); 7772b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7773b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 7774b0c2d521SEmilio G. Cota return; 7775fcf5ef2aSThomas Huth } 7776fcf5ef2aSThomas Huth } 7777b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 7778fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7779fcf5ef2aSThomas Huth handler->count++; 7780fcf5ef2aSThomas Huth #endif 7781fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7782b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7783b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7784b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 7785b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 7786b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 7787*e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 77880e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 7789fcf5ef2aSThomas Huth } 7790b0c2d521SEmilio G. Cota 7791fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7792b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7793b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7794b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7795fcf5ef2aSThomas Huth } 7796b0c2d521SEmilio G. Cota 7797b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7798b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 7799fcf5ef2aSThomas Huth } 7800b0c2d521SEmilio G. Cota 7801b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7802b0c2d521SEmilio G. Cota { 7803b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7804b0c2d521SEmilio G. Cota 7805b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 7806b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 7807b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7808b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7809b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 7810fcf5ef2aSThomas Huth } 7811fcf5ef2aSThomas Huth /* Generate the return instruction */ 781207ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7813fcf5ef2aSThomas Huth } 7814fcf5ef2aSThomas Huth } 7815b0c2d521SEmilio G. Cota 7816b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7817b0c2d521SEmilio G. Cota { 7818b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7819b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7820b0c2d521SEmilio G. Cota } 7821b0c2d521SEmilio G. Cota 7822b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7823b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7824b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7825b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7826b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 7827b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7828b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7829b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7830b0c2d521SEmilio G. Cota }; 7831b0c2d521SEmilio G. Cota 7832b0c2d521SEmilio G. Cota void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 7833b0c2d521SEmilio G. Cota { 7834b0c2d521SEmilio G. Cota DisasContext ctx; 7835b0c2d521SEmilio G. Cota 7836b0c2d521SEmilio G. Cota translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); 7837fcf5ef2aSThomas Huth } 7838fcf5ef2aSThomas Huth 7839fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7840fcf5ef2aSThomas Huth target_ulong *data) 7841fcf5ef2aSThomas Huth { 7842fcf5ef2aSThomas Huth env->nip = data[0]; 7843fcf5ef2aSThomas Huth } 7844