1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char *p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 125fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 131fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 133fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 135fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 137dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 139dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 143fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 144fcf5ef2aSThomas Huth "reserve_addr"); 145253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 146253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 147253ce7b2SNikunj A Dadhania "reserve_val"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 150fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 153efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 154efe843d8SDavid Gibson "access_type"); 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth /* internal defines */ 158fcf5ef2aSThomas Huth struct DisasContext { 159b6bac4bcSEmilio G. Cota DisasContextBase base; 1602c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 161fcf5ef2aSThomas Huth uint32_t opcode; 162fcf5ef2aSThomas Huth uint32_t exception; 163fcf5ef2aSThomas Huth /* Routine used to access memory */ 164fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 165fcf5ef2aSThomas Huth bool lazy_tlb_flush; 166fcf5ef2aSThomas Huth bool need_access_type; 167fcf5ef2aSThomas Huth int mem_idx; 168fcf5ef2aSThomas Huth int access_type; 169fcf5ef2aSThomas Huth /* Translation flags */ 17014776ab5STony Nguyen MemOp default_tcg_memop_mask; 171fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 172fcf5ef2aSThomas Huth bool sf_mode; 173fcf5ef2aSThomas Huth bool has_cfar; 174fcf5ef2aSThomas Huth #endif 175fcf5ef2aSThomas Huth bool fpu_enabled; 176fcf5ef2aSThomas Huth bool altivec_enabled; 177fcf5ef2aSThomas Huth bool vsx_enabled; 178fcf5ef2aSThomas Huth bool spe_enabled; 179fcf5ef2aSThomas Huth bool tm_enabled; 180c6fd28fdSSuraj Jitindar Singh bool gtse; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 189a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 190a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 191a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 192a9b5b3d0SRichard Henderson 193fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 194fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 197fcf5ef2aSThomas Huth return ctx->le_mode; 198fcf5ef2aSThomas Huth #else 199fcf5ef2aSThomas Huth return !ctx->le_mode; 200fcf5ef2aSThomas Huth #endif 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 204fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 206fcf5ef2aSThomas Huth #else 207fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 208fcf5ef2aSThomas Huth #endif 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth struct opc_handler_t { 211fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 212fcf5ef2aSThomas Huth uint32_t inval1; 213fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 214fcf5ef2aSThomas Huth uint32_t inval2; 215fcf5ef2aSThomas Huth /* instruction type */ 216fcf5ef2aSThomas Huth uint64_t type; 217fcf5ef2aSThomas Huth /* extended instruction type */ 218fcf5ef2aSThomas Huth uint64_t type2; 219fcf5ef2aSThomas Huth /* handler */ 220fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 221fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 222fcf5ef2aSThomas Huth const char *oname; 223fcf5ef2aSThomas Huth #endif 224fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 225fcf5ef2aSThomas Huth uint64_t count; 226fcf5ef2aSThomas Huth #endif 227fcf5ef2aSThomas Huth }; 228fcf5ef2aSThomas Huth 2290e3bf489SRoman Kapl /* SPR load/store helpers */ 2300e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2310e3bf489SRoman Kapl { 2320e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2330e3bf489SRoman Kapl } 2340e3bf489SRoman Kapl 2350e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2360e3bf489SRoman Kapl { 2370e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2380e3bf489SRoman Kapl } 2390e3bf489SRoman Kapl 240fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 241fcf5ef2aSThomas Huth { 242fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 243fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 244fcf5ef2aSThomas Huth ctx->access_type = access_type; 245fcf5ef2aSThomas Huth } 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth 248fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 249fcf5ef2aSThomas Huth { 250fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 251fcf5ef2aSThomas Huth nip = (uint32_t)nip; 252fcf5ef2aSThomas Huth } 253fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 254fcf5ef2aSThomas Huth } 255fcf5ef2aSThomas Huth 256fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 257fcf5ef2aSThomas Huth { 258fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 259fcf5ef2aSThomas Huth 260efe843d8SDavid Gibson /* 261efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 262efe843d8SDavid Gibson * faulting instruction 263fcf5ef2aSThomas Huth */ 264fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 2652c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 266fcf5ef2aSThomas Huth } 267fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 268fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 269fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 270fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 271fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2723d8a5b69SRichard Henderson ctx->exception = excp; 2733d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 274fcf5ef2aSThomas Huth } 275fcf5ef2aSThomas Huth 276fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 277fcf5ef2aSThomas Huth { 278fcf5ef2aSThomas Huth TCGv_i32 t0; 279fcf5ef2aSThomas Huth 280efe843d8SDavid Gibson /* 281efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 282efe843d8SDavid Gibson * faulting instruction 283fcf5ef2aSThomas Huth */ 284fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 2852c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 286fcf5ef2aSThomas Huth } 287fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 288fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 289fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2903d8a5b69SRichard Henderson ctx->exception = excp; 2913d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 292fcf5ef2aSThomas Huth } 293fcf5ef2aSThomas Huth 294fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 295fcf5ef2aSThomas Huth target_ulong nip) 296fcf5ef2aSThomas Huth { 297fcf5ef2aSThomas Huth TCGv_i32 t0; 298fcf5ef2aSThomas Huth 299fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 300fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 301fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 302fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3033d8a5b69SRichard Henderson ctx->exception = excp; 3043d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 305fcf5ef2aSThomas Huth } 306fcf5ef2aSThomas Huth 307f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 308f5b6daacSRichard Henderson { 309f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 310f5b6daacSRichard Henderson gen_io_start(); 311f5b6daacSRichard Henderson /* 312f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 313f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 314f5b6daacSRichard Henderson * decide if we need to return to the main loop. 315f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 316f5b6daacSRichard Henderson */ 317f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 318f5b6daacSRichard Henderson } 319f5b6daacSRichard Henderson } 320f5b6daacSRichard Henderson 321e150ac89SRoman Kapl /* 322e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 323e150ac89SRoman Kapl * SPR registers for this exception. 324e150ac89SRoman Kapl * 325e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 326e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3270e3bf489SRoman Kapl */ 328e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3290e3bf489SRoman Kapl { 3300e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3310e3bf489SRoman Kapl target_ulong dbsr = 0; 332e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3330e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 334e150ac89SRoman Kapl } else { 335e150ac89SRoman Kapl /* Must have been branch */ 3360e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3370e3bf489SRoman Kapl } 3380e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3390e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3400e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3410e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3420e3bf489SRoman Kapl tcg_temp_free(t0); 3430e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3440e3bf489SRoman Kapl } else { 345e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3460e3bf489SRoman Kapl } 3470e3bf489SRoman Kapl } 3480e3bf489SRoman Kapl 349fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 350fcf5ef2aSThomas Huth { 3512736fc61SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 3523d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 353fcf5ef2aSThomas Huth } 354fcf5ef2aSThomas Huth 355fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 356fcf5ef2aSThomas Huth { 357fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 358fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 359fcf5ef2aSThomas Huth } 360fcf5ef2aSThomas Huth 361fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 362fcf5ef2aSThomas Huth { 363fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 364fcf5ef2aSThomas Huth } 365fcf5ef2aSThomas Huth 366fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 367fcf5ef2aSThomas Huth { 368fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 369fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 370fcf5ef2aSThomas Huth } 371fcf5ef2aSThomas Huth 37237f219c8SBruno Larsen (billionai) /*****************************************************************************/ 37337f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 37437f219c8SBruno Larsen (billionai) 375a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 37637f219c8SBruno Larsen (billionai) { 37737f219c8SBruno Larsen (billionai) #if 0 37837f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 37937f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 38037f219c8SBruno Larsen (billionai) #endif 38137f219c8SBruno Larsen (billionai) } 38237f219c8SBruno Larsen (billionai) 38337f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 38437f219c8SBruno Larsen (billionai) 38537f219c8SBruno Larsen (billionai) /* 38637f219c8SBruno Larsen (billionai) * Generic callbacks: 38737f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 38837f219c8SBruno Larsen (billionai) */ 38937f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 39037f219c8SBruno Larsen (billionai) { 39137f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39337f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 39437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39537f219c8SBruno Larsen (billionai) #endif 39637f219c8SBruno Larsen (billionai) } 39737f219c8SBruno Larsen (billionai) 398a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 39937f219c8SBruno Larsen (billionai) { 40037f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 40137f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 40237f219c8SBruno Larsen (billionai) } 40337f219c8SBruno Larsen (billionai) 40437f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 40537f219c8SBruno Larsen (billionai) { 40637f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 40737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 40837f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 40937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 41037f219c8SBruno Larsen (billionai) #endif 41137f219c8SBruno Larsen (billionai) } 41237f219c8SBruno Larsen (billionai) 413a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 41437f219c8SBruno Larsen (billionai) { 41537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 41637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41737f219c8SBruno Larsen (billionai) } 41837f219c8SBruno Larsen (billionai) 41937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 420a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 42137f219c8SBruno Larsen (billionai) { 42237f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 42337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42437f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 42537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42837f219c8SBruno Larsen (billionai) #else 42937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43037f219c8SBruno Larsen (billionai) #endif 43137f219c8SBruno Larsen (billionai) } 43237f219c8SBruno Larsen (billionai) 433a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 43437f219c8SBruno Larsen (billionai) { 43537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 43737f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 43837f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 43937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 44037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 44237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 44337f219c8SBruno Larsen (billionai) } 44437f219c8SBruno Larsen (billionai) 445a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 44637f219c8SBruno Larsen (billionai) { 44737f219c8SBruno Larsen (billionai) } 44837f219c8SBruno Larsen (billionai) 44937f219c8SBruno Larsen (billionai) #endif 45037f219c8SBruno Larsen (billionai) 45137f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 45237f219c8SBruno Larsen (billionai) /* XER */ 453a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 45437f219c8SBruno Larsen (billionai) { 45537f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 45637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 45737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 45837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 45937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 46037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 46137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 46237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 46337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 46437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 46537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46637f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 46737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 46837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 47037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47137f219c8SBruno Larsen (billionai) } 47237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 47337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 47437f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 47537f219c8SBruno Larsen (billionai) } 47637f219c8SBruno Larsen (billionai) 477a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 47837f219c8SBruno Larsen (billionai) { 47937f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 48037f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 48137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 48237f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 48337f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 48437f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 48537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 48637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 48737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 48837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 48937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 49037f219c8SBruno Larsen (billionai) } 49137f219c8SBruno Larsen (billionai) 49237f219c8SBruno Larsen (billionai) /* LR */ 493a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 49437f219c8SBruno Larsen (billionai) { 49537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 49637f219c8SBruno Larsen (billionai) } 49737f219c8SBruno Larsen (billionai) 498a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 49937f219c8SBruno Larsen (billionai) { 50037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 50137f219c8SBruno Larsen (billionai) } 50237f219c8SBruno Larsen (billionai) 50337f219c8SBruno Larsen (billionai) /* CFAR */ 50437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 505a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 50637f219c8SBruno Larsen (billionai) { 50737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 50837f219c8SBruno Larsen (billionai) } 50937f219c8SBruno Larsen (billionai) 510a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 51137f219c8SBruno Larsen (billionai) { 51237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 51337f219c8SBruno Larsen (billionai) } 51437f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 51537f219c8SBruno Larsen (billionai) 51637f219c8SBruno Larsen (billionai) /* CTR */ 517a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 51837f219c8SBruno Larsen (billionai) { 51937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 52037f219c8SBruno Larsen (billionai) } 52137f219c8SBruno Larsen (billionai) 522a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 52337f219c8SBruno Larsen (billionai) { 52437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 52537f219c8SBruno Larsen (billionai) } 52637f219c8SBruno Larsen (billionai) 52737f219c8SBruno Larsen (billionai) /* User read access to SPR */ 52837f219c8SBruno Larsen (billionai) /* USPRx */ 52937f219c8SBruno Larsen (billionai) /* UMMCRx */ 53037f219c8SBruno Larsen (billionai) /* UPMCx */ 53137f219c8SBruno Larsen (billionai) /* USIA */ 53237f219c8SBruno Larsen (billionai) /* UDECR */ 533a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 53437f219c8SBruno Larsen (billionai) { 53537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 53637f219c8SBruno Larsen (billionai) } 53737f219c8SBruno Larsen (billionai) 53837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 539a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 54037f219c8SBruno Larsen (billionai) { 54137f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 54237f219c8SBruno Larsen (billionai) } 54337f219c8SBruno Larsen (billionai) #endif 54437f219c8SBruno Larsen (billionai) 54537f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 54637f219c8SBruno Larsen (billionai) /* DECR */ 54737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 548a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 54937f219c8SBruno Larsen (billionai) { 550f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55137f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 55237f219c8SBruno Larsen (billionai) } 55337f219c8SBruno Larsen (billionai) 554a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 55537f219c8SBruno Larsen (billionai) { 556f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55737f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 55837f219c8SBruno Larsen (billionai) } 55937f219c8SBruno Larsen (billionai) #endif 56037f219c8SBruno Larsen (billionai) 56137f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 56237f219c8SBruno Larsen (billionai) /* Time base */ 563a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 56437f219c8SBruno Larsen (billionai) { 565f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56637f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 56737f219c8SBruno Larsen (billionai) } 56837f219c8SBruno Larsen (billionai) 569a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 57037f219c8SBruno Larsen (billionai) { 571f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57237f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 57337f219c8SBruno Larsen (billionai) } 57437f219c8SBruno Larsen (billionai) 575a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 57637f219c8SBruno Larsen (billionai) { 57737f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 57837f219c8SBruno Larsen (billionai) } 57937f219c8SBruno Larsen (billionai) 580a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 58137f219c8SBruno Larsen (billionai) { 58237f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 58337f219c8SBruno Larsen (billionai) } 58437f219c8SBruno Larsen (billionai) 58537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 586a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 58737f219c8SBruno Larsen (billionai) { 588f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58937f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 59037f219c8SBruno Larsen (billionai) } 59137f219c8SBruno Larsen (billionai) 592a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 59337f219c8SBruno Larsen (billionai) { 594f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59537f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 59637f219c8SBruno Larsen (billionai) } 59737f219c8SBruno Larsen (billionai) 598a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 59937f219c8SBruno Larsen (billionai) { 60037f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 60137f219c8SBruno Larsen (billionai) } 60237f219c8SBruno Larsen (billionai) 603a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 60437f219c8SBruno Larsen (billionai) { 60537f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 60637f219c8SBruno Larsen (billionai) } 60737f219c8SBruno Larsen (billionai) 60837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 609a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 61037f219c8SBruno Larsen (billionai) { 611f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61237f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 61337f219c8SBruno Larsen (billionai) } 61437f219c8SBruno Larsen (billionai) 615a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 61637f219c8SBruno Larsen (billionai) { 617f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61837f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 61937f219c8SBruno Larsen (billionai) } 62037f219c8SBruno Larsen (billionai) 62137f219c8SBruno Larsen (billionai) /* HDECR */ 622a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 62337f219c8SBruno Larsen (billionai) { 624f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62537f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 62637f219c8SBruno Larsen (billionai) } 62737f219c8SBruno Larsen (billionai) 628a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 62937f219c8SBruno Larsen (billionai) { 630f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63137f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 63237f219c8SBruno Larsen (billionai) } 63337f219c8SBruno Larsen (billionai) 634a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 63537f219c8SBruno Larsen (billionai) { 636f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63737f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 63837f219c8SBruno Larsen (billionai) } 63937f219c8SBruno Larsen (billionai) 640a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 64137f219c8SBruno Larsen (billionai) { 642f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64337f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 64437f219c8SBruno Larsen (billionai) } 64537f219c8SBruno Larsen (billionai) 646a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 64737f219c8SBruno Larsen (billionai) { 648f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64937f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 65037f219c8SBruno Larsen (billionai) } 65137f219c8SBruno Larsen (billionai) 65237f219c8SBruno Larsen (billionai) #endif 65337f219c8SBruno Larsen (billionai) #endif 65437f219c8SBruno Larsen (billionai) 65537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 65637f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 65737f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 658a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 65937f219c8SBruno Larsen (billionai) { 66037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66237f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 66337f219c8SBruno Larsen (billionai) } 66437f219c8SBruno Larsen (billionai) 665a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 66637f219c8SBruno Larsen (billionai) { 66737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66937f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 67037f219c8SBruno Larsen (billionai) } 67137f219c8SBruno Larsen (billionai) 672a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 67337f219c8SBruno Larsen (billionai) { 67437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 67537f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 67637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67737f219c8SBruno Larsen (billionai) } 67837f219c8SBruno Larsen (billionai) 679a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 68037f219c8SBruno Larsen (billionai) { 68137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 68237f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 68337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68437f219c8SBruno Larsen (billionai) } 68537f219c8SBruno Larsen (billionai) 686a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 68737f219c8SBruno Larsen (billionai) { 68837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 68937f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 69037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69137f219c8SBruno Larsen (billionai) } 69237f219c8SBruno Larsen (billionai) 693a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 69437f219c8SBruno Larsen (billionai) { 69537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 69637f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 69737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69837f219c8SBruno Larsen (billionai) } 69937f219c8SBruno Larsen (billionai) 70037f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 70137f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 702a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 70337f219c8SBruno Larsen (billionai) { 70437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70637f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 70737f219c8SBruno Larsen (billionai) } 70837f219c8SBruno Larsen (billionai) 709a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 71037f219c8SBruno Larsen (billionai) { 71137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 71237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 71337f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 71437f219c8SBruno Larsen (billionai) } 71537f219c8SBruno Larsen (billionai) 716a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 71737f219c8SBruno Larsen (billionai) { 71837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 71937f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 72037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72137f219c8SBruno Larsen (billionai) } 72237f219c8SBruno Larsen (billionai) 723a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 72437f219c8SBruno Larsen (billionai) { 72537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 72637f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 72737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72837f219c8SBruno Larsen (billionai) } 72937f219c8SBruno Larsen (billionai) 730a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 73137f219c8SBruno Larsen (billionai) { 73237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 73337f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 73437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73537f219c8SBruno Larsen (billionai) } 73637f219c8SBruno Larsen (billionai) 737a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 73837f219c8SBruno Larsen (billionai) { 73937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 74037f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 74137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74237f219c8SBruno Larsen (billionai) } 74337f219c8SBruno Larsen (billionai) 74437f219c8SBruno Larsen (billionai) /* SDR1 */ 745a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 74637f219c8SBruno Larsen (billionai) { 74737f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 74837f219c8SBruno Larsen (billionai) } 74937f219c8SBruno Larsen (billionai) 75037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 75137f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 75237f219c8SBruno Larsen (billionai) /* PIDR */ 753a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 75437f219c8SBruno Larsen (billionai) { 75537f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 75637f219c8SBruno Larsen (billionai) } 75737f219c8SBruno Larsen (billionai) 758a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 75937f219c8SBruno Larsen (billionai) { 76037f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 76137f219c8SBruno Larsen (billionai) } 76237f219c8SBruno Larsen (billionai) 763a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 76437f219c8SBruno Larsen (billionai) { 76537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 76637f219c8SBruno Larsen (billionai) } 76737f219c8SBruno Larsen (billionai) 768a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 76937f219c8SBruno Larsen (billionai) { 77037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 77137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 77237f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 77337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 77437f219c8SBruno Larsen (billionai) } 775a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 77637f219c8SBruno Larsen (billionai) { 77737f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 77837f219c8SBruno Larsen (billionai) } 77937f219c8SBruno Larsen (billionai) 780a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 78137f219c8SBruno Larsen (billionai) { 78237f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 78337f219c8SBruno Larsen (billionai) } 78437f219c8SBruno Larsen (billionai) 78537f219c8SBruno Larsen (billionai) /* DPDES */ 786a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 78737f219c8SBruno Larsen (billionai) { 78837f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 78937f219c8SBruno Larsen (billionai) } 79037f219c8SBruno Larsen (billionai) 791a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 79237f219c8SBruno Larsen (billionai) { 79337f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 79437f219c8SBruno Larsen (billionai) } 79537f219c8SBruno Larsen (billionai) #endif 79637f219c8SBruno Larsen (billionai) #endif 79737f219c8SBruno Larsen (billionai) 79837f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 79937f219c8SBruno Larsen (billionai) /* RTC */ 800a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 80137f219c8SBruno Larsen (billionai) { 80237f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 80337f219c8SBruno Larsen (billionai) } 80437f219c8SBruno Larsen (billionai) 805a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 80637f219c8SBruno Larsen (billionai) { 80737f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 80837f219c8SBruno Larsen (billionai) } 80937f219c8SBruno Larsen (billionai) 81037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 811a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 81237f219c8SBruno Larsen (billionai) { 81337f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 81437f219c8SBruno Larsen (billionai) } 81537f219c8SBruno Larsen (billionai) 816a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 81737f219c8SBruno Larsen (billionai) { 81837f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 81937f219c8SBruno Larsen (billionai) } 82037f219c8SBruno Larsen (billionai) 821a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 82237f219c8SBruno Larsen (billionai) { 82337f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 82437f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 825*d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 82637f219c8SBruno Larsen (billionai) } 82737f219c8SBruno Larsen (billionai) #endif 82837f219c8SBruno Larsen (billionai) 82937f219c8SBruno Larsen (billionai) /* Unified bats */ 83037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 831a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 83237f219c8SBruno Larsen (billionai) { 83337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 83437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 83537f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 83637f219c8SBruno Larsen (billionai) } 83737f219c8SBruno Larsen (billionai) 838a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 83937f219c8SBruno Larsen (billionai) { 84037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 84137f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 84237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 84337f219c8SBruno Larsen (billionai) } 84437f219c8SBruno Larsen (billionai) 845a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 84637f219c8SBruno Larsen (billionai) { 84737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 84837f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 84937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 85037f219c8SBruno Larsen (billionai) } 85137f219c8SBruno Larsen (billionai) #endif 85237f219c8SBruno Larsen (billionai) 85337f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 85437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 855a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 85637f219c8SBruno Larsen (billionai) { 857f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85837f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 85937f219c8SBruno Larsen (billionai) } 86037f219c8SBruno Larsen (billionai) 861a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 86237f219c8SBruno Larsen (billionai) { 863f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86437f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 86537f219c8SBruno Larsen (billionai) } 86637f219c8SBruno Larsen (billionai) 867a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 86837f219c8SBruno Larsen (billionai) { 869f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 87137f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 87237f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 873*d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 87437f219c8SBruno Larsen (billionai) } 87537f219c8SBruno Larsen (billionai) 876a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 87737f219c8SBruno Larsen (billionai) { 878f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87937f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 88037f219c8SBruno Larsen (billionai) } 88137f219c8SBruno Larsen (billionai) 882a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 88337f219c8SBruno Larsen (billionai) { 884f5b6daacSRichard Henderson gen_icount_io_start(ctx); 88537f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 88637f219c8SBruno Larsen (billionai) } 88737f219c8SBruno Larsen (billionai) 888a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 88937f219c8SBruno Larsen (billionai) { 890f5b6daacSRichard Henderson gen_icount_io_start(ctx); 89137f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 89237f219c8SBruno Larsen (billionai) } 89337f219c8SBruno Larsen (billionai) #endif 89437f219c8SBruno Larsen (billionai) 89537f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 89637f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 89737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 898a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 89937f219c8SBruno Larsen (billionai) { 90037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 90137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 90237f219c8SBruno Larsen (billionai) } 90337f219c8SBruno Larsen (billionai) 904a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 90537f219c8SBruno Larsen (billionai) { 90637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 90737f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 90837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 90937f219c8SBruno Larsen (billionai) } 91037f219c8SBruno Larsen (billionai) 911a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 91237f219c8SBruno Larsen (billionai) { 91337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 91437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 91537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 91637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 91737f219c8SBruno Larsen (billionai) } 91837f219c8SBruno Larsen (billionai) #endif 91937f219c8SBruno Larsen (billionai) 92037f219c8SBruno Larsen (billionai) /* SPE specific registers */ 921a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 92237f219c8SBruno Larsen (billionai) { 92337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 92437f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92537f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 92637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92737f219c8SBruno Larsen (billionai) } 92837f219c8SBruno Larsen (billionai) 929a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 93037f219c8SBruno Larsen (billionai) { 93137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 93237f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 93337f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 93437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 93537f219c8SBruno Larsen (billionai) } 93637f219c8SBruno Larsen (billionai) 93737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 93837f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 939a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 94037f219c8SBruno Larsen (billionai) { 94137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 94237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 94337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 94437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 94537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 94637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 94737f219c8SBruno Larsen (billionai) } 94837f219c8SBruno Larsen (billionai) 949a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 95037f219c8SBruno Larsen (billionai) { 95137f219c8SBruno Larsen (billionai) int sprn_offs; 95237f219c8SBruno Larsen (billionai) 95337f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 95437f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 95537f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 95637f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 95737f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 95837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 95937f219c8SBruno Larsen (billionai) } else { 96037f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 96137f219c8SBruno Larsen (billionai) sprn, sprn); 96237f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 96337f219c8SBruno Larsen (billionai) return; 96437f219c8SBruno Larsen (billionai) } 96537f219c8SBruno Larsen (billionai) 96637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 96837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 96937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 97037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 97137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 97237f219c8SBruno Larsen (billionai) } 97337f219c8SBruno Larsen (billionai) #endif 97437f219c8SBruno Larsen (billionai) 97537f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 97637f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 977a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 97837f219c8SBruno Larsen (billionai) { 97937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 98037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 98137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 98237f219c8SBruno Larsen (billionai) 98337f219c8SBruno Larsen (billionai) /* 98437f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 98537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 98637f219c8SBruno Larsen (billionai) */ 98737f219c8SBruno Larsen (billionai) 98837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 98937f219c8SBruno Larsen (billionai) if (ctx->pr) { 99037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 99137f219c8SBruno Larsen (billionai) } else { 99237f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 99337f219c8SBruno Larsen (billionai) } 99437f219c8SBruno Larsen (billionai) 99537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 99637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 99737f219c8SBruno Larsen (billionai) 99837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 99937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 100037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 100137f219c8SBruno Larsen (billionai) 100237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 100337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 100437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 100537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 100637f219c8SBruno Larsen (billionai) 100737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 100837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 100937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 101037f219c8SBruno Larsen (billionai) } 101137f219c8SBruno Larsen (billionai) 1012a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 101337f219c8SBruno Larsen (billionai) { 101437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 101537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 101637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 101737f219c8SBruno Larsen (billionai) 101837f219c8SBruno Larsen (billionai) /* 101937f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 102037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 102137f219c8SBruno Larsen (billionai) */ 102237f219c8SBruno Larsen (billionai) 102337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 102437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 102537f219c8SBruno Larsen (billionai) 102637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 102737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 102837f219c8SBruno Larsen (billionai) 102937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 103037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 103137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 103237f219c8SBruno Larsen (billionai) 103337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 103437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 103537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 103637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 103737f219c8SBruno Larsen (billionai) 103837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 103937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 104037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 104137f219c8SBruno Larsen (billionai) } 104237f219c8SBruno Larsen (billionai) 1043a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 104437f219c8SBruno Larsen (billionai) { 104537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 104637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 104737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 104837f219c8SBruno Larsen (billionai) 104937f219c8SBruno Larsen (billionai) /* 105037f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 105137f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 105237f219c8SBruno Larsen (billionai) */ 105337f219c8SBruno Larsen (billionai) 105437f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 105537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 105637f219c8SBruno Larsen (billionai) 105737f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 105837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 105937f219c8SBruno Larsen (billionai) 106037f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 106137f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 106237f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 106337f219c8SBruno Larsen (billionai) 106437f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 106537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 106637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 106737f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 106837f219c8SBruno Larsen (billionai) 106937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107037f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 107137f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 107237f219c8SBruno Larsen (billionai) } 107337f219c8SBruno Larsen (billionai) #endif 107437f219c8SBruno Larsen (billionai) #endif 107537f219c8SBruno Larsen (billionai) 107637f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1077a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 107837f219c8SBruno Larsen (billionai) { 107937f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 108037f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 108137f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 108237f219c8SBruno Larsen (billionai) } 108337f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 108437f219c8SBruno Larsen (billionai) 108537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1086a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 108737f219c8SBruno Larsen (billionai) { 108837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108937f219c8SBruno Larsen (billionai) 109037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 109137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109337f219c8SBruno Larsen (billionai) } 109437f219c8SBruno Larsen (billionai) 1095a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 109637f219c8SBruno Larsen (billionai) { 109737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109837f219c8SBruno Larsen (billionai) 109937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 110037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 110137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 110237f219c8SBruno Larsen (billionai) } 110337f219c8SBruno Larsen (billionai) 1104a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 110537f219c8SBruno Larsen (billionai) { 110637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 110737f219c8SBruno Larsen (billionai) 110837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 110937f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 111037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 111137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 111237f219c8SBruno Larsen (billionai) } 111337f219c8SBruno Larsen (billionai) 1114a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 111537f219c8SBruno Larsen (billionai) { 111637f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 111737f219c8SBruno Larsen (billionai) } 111837f219c8SBruno Larsen (billionai) 1119a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 112037f219c8SBruno Larsen (billionai) { 112137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 112237f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 112337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 112437f219c8SBruno Larsen (billionai) } 1125a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 112637f219c8SBruno Larsen (billionai) { 112737f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 112837f219c8SBruno Larsen (billionai) } 1129a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 113037f219c8SBruno Larsen (billionai) { 113137f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 113237f219c8SBruno Larsen (billionai) } 113337f219c8SBruno Larsen (billionai) 113437f219c8SBruno Larsen (billionai) #endif 113537f219c8SBruno Larsen (billionai) 113637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1137a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 113837f219c8SBruno Larsen (billionai) { 113937f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 114037f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 114137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 114237f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 114337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 114437f219c8SBruno Larsen (billionai) tcg_temp_free(val); 114537f219c8SBruno Larsen (billionai) } 114637f219c8SBruno Larsen (billionai) 1147a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 114837f219c8SBruno Larsen (billionai) { 114937f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 115037f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 115137f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 115237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 115337f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 115437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 115537f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 115637f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 115737f219c8SBruno Larsen (billionai) } 115837f219c8SBruno Larsen (billionai) 115937f219c8SBruno Larsen (billionai) #endif 116037f219c8SBruno Larsen (billionai) 116137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 116237f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 116337f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116437f219c8SBruno Larsen (billionai) { 116537f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 116637f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 116737f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116837f219c8SBruno Larsen (billionai) 116937f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 117037f219c8SBruno Larsen (billionai) 117137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 117437f219c8SBruno Larsen (billionai) } 117537f219c8SBruno Larsen (billionai) 117637f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 117737f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 117837f219c8SBruno Larsen (billionai) { 117937f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 118037f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 118137f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 118237f219c8SBruno Larsen (billionai) 118337f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 118437f219c8SBruno Larsen (billionai) 118537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 118637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 118737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 118837f219c8SBruno Larsen (billionai) } 118937f219c8SBruno Larsen (billionai) 1190a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 119137f219c8SBruno Larsen (billionai) { 119237f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 119337f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119437f219c8SBruno Larsen (billionai) 119537f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119637f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 119737f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 119837f219c8SBruno Larsen (billionai) 119937f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 120037f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 120137f219c8SBruno Larsen (billionai) } 120237f219c8SBruno Larsen (billionai) 1203a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 120437f219c8SBruno Larsen (billionai) { 120537f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 120637f219c8SBruno Larsen (billionai) 120737f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 120837f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 120937f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 121037f219c8SBruno Larsen (billionai) 121137f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 121237f219c8SBruno Larsen (billionai) } 121337f219c8SBruno Larsen (billionai) 121437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1215a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 121637f219c8SBruno Larsen (billionai) { 121737f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 121837f219c8SBruno Larsen (billionai) 121937f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 122037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 122137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 122237f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 122337f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 122437f219c8SBruno Larsen (billionai) } 122537f219c8SBruno Larsen (billionai) 1226a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 122737f219c8SBruno Larsen (billionai) { 122837f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 122937f219c8SBruno Larsen (billionai) } 123037f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 123137f219c8SBruno Larsen (billionai) 1232a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 123337f219c8SBruno Larsen (billionai) { 123437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 123537f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123637f219c8SBruno Larsen (billionai) } 123737f219c8SBruno Larsen (billionai) 1238a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 123937f219c8SBruno Larsen (billionai) { 124037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 124137f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124237f219c8SBruno Larsen (billionai) } 124337f219c8SBruno Larsen (billionai) 1244a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 124537f219c8SBruno Larsen (billionai) { 124637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 124837f219c8SBruno Larsen (billionai) } 124937f219c8SBruno Larsen (billionai) 1250a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 125137f219c8SBruno Larsen (billionai) { 125237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 125437f219c8SBruno Larsen (billionai) } 125537f219c8SBruno Larsen (billionai) 1256a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 125737f219c8SBruno Larsen (billionai) { 125837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125937f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 126037f219c8SBruno Larsen (billionai) } 126137f219c8SBruno Larsen (billionai) 1262a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 126337f219c8SBruno Larsen (billionai) { 126437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 126537f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 126637f219c8SBruno Larsen (billionai) } 126737f219c8SBruno Larsen (billionai) 1268a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 126937f219c8SBruno Larsen (billionai) { 127037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127137f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 127237f219c8SBruno Larsen (billionai) } 127337f219c8SBruno Larsen (billionai) 1274a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 127537f219c8SBruno Larsen (billionai) { 127637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 127837f219c8SBruno Larsen (billionai) } 127937f219c8SBruno Larsen (billionai) 1280a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 128137f219c8SBruno Larsen (billionai) { 128237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 128337f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 128437f219c8SBruno Larsen (billionai) } 128537f219c8SBruno Larsen (billionai) 1286a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 128737f219c8SBruno Larsen (billionai) { 128837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 128937f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 129037f219c8SBruno Larsen (billionai) } 129137f219c8SBruno Larsen (billionai) #endif 129237f219c8SBruno Larsen (billionai) 1293fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1294fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1295fcf5ef2aSThomas Huth 1296fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1297fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1298fcf5ef2aSThomas Huth 1299fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1300fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1301fcf5ef2aSThomas Huth 1302fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1303fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1304fcf5ef2aSThomas Huth 1305fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1306fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1307fcf5ef2aSThomas Huth 1308fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1309fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1310fcf5ef2aSThomas Huth 1311fcf5ef2aSThomas Huth typedef struct opcode_t { 1312fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1313fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1314fcf5ef2aSThomas Huth unsigned char pad[4]; 1315fcf5ef2aSThomas Huth #endif 1316fcf5ef2aSThomas Huth opc_handler_t handler; 1317fcf5ef2aSThomas Huth const char *oname; 1318fcf5ef2aSThomas Huth } opcode_t; 1319fcf5ef2aSThomas Huth 1320fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1321fcf5ef2aSThomas Huth #define GEN_PRIV \ 1322fcf5ef2aSThomas Huth do { \ 1323fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1324fcf5ef2aSThomas Huth } while (0) 1325fcf5ef2aSThomas Huth 1326fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1327fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1328fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1329fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1330fcf5ef2aSThomas Huth #else 1331fcf5ef2aSThomas Huth #define CHK_HV \ 1332fcf5ef2aSThomas Huth do { \ 1333fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1334fcf5ef2aSThomas Huth GEN_PRIV; \ 1335fcf5ef2aSThomas Huth } \ 1336fcf5ef2aSThomas Huth } while (0) 1337fcf5ef2aSThomas Huth #define CHK_SV \ 1338fcf5ef2aSThomas Huth do { \ 1339fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1340fcf5ef2aSThomas Huth GEN_PRIV; \ 1341fcf5ef2aSThomas Huth } \ 1342fcf5ef2aSThomas Huth } while (0) 1343fcf5ef2aSThomas Huth #define CHK_HVRM \ 1344fcf5ef2aSThomas Huth do { \ 1345fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1346fcf5ef2aSThomas Huth GEN_PRIV; \ 1347fcf5ef2aSThomas Huth } \ 1348fcf5ef2aSThomas Huth } while (0) 1349fcf5ef2aSThomas Huth #endif 1350fcf5ef2aSThomas Huth 1351fcf5ef2aSThomas Huth #define CHK_NONE 1352fcf5ef2aSThomas Huth 1353fcf5ef2aSThomas Huth /*****************************************************************************/ 1354fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1355fcf5ef2aSThomas Huth 1356fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 1357fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1358fcf5ef2aSThomas Huth { \ 1359fcf5ef2aSThomas Huth .opc1 = op1, \ 1360fcf5ef2aSThomas Huth .opc2 = op2, \ 1361fcf5ef2aSThomas Huth .opc3 = op3, \ 1362fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1363fcf5ef2aSThomas Huth .handler = { \ 1364fcf5ef2aSThomas Huth .inval1 = invl, \ 1365fcf5ef2aSThomas Huth .type = _typ, \ 1366fcf5ef2aSThomas Huth .type2 = _typ2, \ 1367fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1368fcf5ef2aSThomas Huth .oname = stringify(name), \ 1369fcf5ef2aSThomas Huth }, \ 1370fcf5ef2aSThomas Huth .oname = stringify(name), \ 1371fcf5ef2aSThomas Huth } 1372fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1373fcf5ef2aSThomas Huth { \ 1374fcf5ef2aSThomas Huth .opc1 = op1, \ 1375fcf5ef2aSThomas Huth .opc2 = op2, \ 1376fcf5ef2aSThomas Huth .opc3 = op3, \ 1377fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1378fcf5ef2aSThomas Huth .handler = { \ 1379fcf5ef2aSThomas Huth .inval1 = invl1, \ 1380fcf5ef2aSThomas Huth .inval2 = invl2, \ 1381fcf5ef2aSThomas Huth .type = _typ, \ 1382fcf5ef2aSThomas Huth .type2 = _typ2, \ 1383fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1384fcf5ef2aSThomas Huth .oname = stringify(name), \ 1385fcf5ef2aSThomas Huth }, \ 1386fcf5ef2aSThomas Huth .oname = stringify(name), \ 1387fcf5ef2aSThomas Huth } 1388fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1389fcf5ef2aSThomas Huth { \ 1390fcf5ef2aSThomas Huth .opc1 = op1, \ 1391fcf5ef2aSThomas Huth .opc2 = op2, \ 1392fcf5ef2aSThomas Huth .opc3 = op3, \ 1393fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1394fcf5ef2aSThomas Huth .handler = { \ 1395fcf5ef2aSThomas Huth .inval1 = invl, \ 1396fcf5ef2aSThomas Huth .type = _typ, \ 1397fcf5ef2aSThomas Huth .type2 = _typ2, \ 1398fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1399fcf5ef2aSThomas Huth .oname = onam, \ 1400fcf5ef2aSThomas Huth }, \ 1401fcf5ef2aSThomas Huth .oname = onam, \ 1402fcf5ef2aSThomas Huth } 1403fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1404fcf5ef2aSThomas Huth { \ 1405fcf5ef2aSThomas Huth .opc1 = op1, \ 1406fcf5ef2aSThomas Huth .opc2 = op2, \ 1407fcf5ef2aSThomas Huth .opc3 = op3, \ 1408fcf5ef2aSThomas Huth .opc4 = op4, \ 1409fcf5ef2aSThomas Huth .handler = { \ 1410fcf5ef2aSThomas Huth .inval1 = invl, \ 1411fcf5ef2aSThomas Huth .type = _typ, \ 1412fcf5ef2aSThomas Huth .type2 = _typ2, \ 1413fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1414fcf5ef2aSThomas Huth .oname = stringify(name), \ 1415fcf5ef2aSThomas Huth }, \ 1416fcf5ef2aSThomas Huth .oname = stringify(name), \ 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1419fcf5ef2aSThomas Huth { \ 1420fcf5ef2aSThomas Huth .opc1 = op1, \ 1421fcf5ef2aSThomas Huth .opc2 = op2, \ 1422fcf5ef2aSThomas Huth .opc3 = op3, \ 1423fcf5ef2aSThomas Huth .opc4 = op4, \ 1424fcf5ef2aSThomas Huth .handler = { \ 1425fcf5ef2aSThomas Huth .inval1 = invl, \ 1426fcf5ef2aSThomas Huth .type = _typ, \ 1427fcf5ef2aSThomas Huth .type2 = _typ2, \ 1428fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1429fcf5ef2aSThomas Huth .oname = onam, \ 1430fcf5ef2aSThomas Huth }, \ 1431fcf5ef2aSThomas Huth .oname = onam, \ 1432fcf5ef2aSThomas Huth } 1433fcf5ef2aSThomas Huth #else 1434fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1435fcf5ef2aSThomas Huth { \ 1436fcf5ef2aSThomas Huth .opc1 = op1, \ 1437fcf5ef2aSThomas Huth .opc2 = op2, \ 1438fcf5ef2aSThomas Huth .opc3 = op3, \ 1439fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1440fcf5ef2aSThomas Huth .handler = { \ 1441fcf5ef2aSThomas Huth .inval1 = invl, \ 1442fcf5ef2aSThomas Huth .type = _typ, \ 1443fcf5ef2aSThomas Huth .type2 = _typ2, \ 1444fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1445fcf5ef2aSThomas Huth }, \ 1446fcf5ef2aSThomas Huth .oname = stringify(name), \ 1447fcf5ef2aSThomas Huth } 1448fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1449fcf5ef2aSThomas Huth { \ 1450fcf5ef2aSThomas Huth .opc1 = op1, \ 1451fcf5ef2aSThomas Huth .opc2 = op2, \ 1452fcf5ef2aSThomas Huth .opc3 = op3, \ 1453fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1454fcf5ef2aSThomas Huth .handler = { \ 1455fcf5ef2aSThomas Huth .inval1 = invl1, \ 1456fcf5ef2aSThomas Huth .inval2 = invl2, \ 1457fcf5ef2aSThomas Huth .type = _typ, \ 1458fcf5ef2aSThomas Huth .type2 = _typ2, \ 1459fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1460fcf5ef2aSThomas Huth }, \ 1461fcf5ef2aSThomas Huth .oname = stringify(name), \ 1462fcf5ef2aSThomas Huth } 1463fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1464fcf5ef2aSThomas Huth { \ 1465fcf5ef2aSThomas Huth .opc1 = op1, \ 1466fcf5ef2aSThomas Huth .opc2 = op2, \ 1467fcf5ef2aSThomas Huth .opc3 = op3, \ 1468fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1469fcf5ef2aSThomas Huth .handler = { \ 1470fcf5ef2aSThomas Huth .inval1 = invl, \ 1471fcf5ef2aSThomas Huth .type = _typ, \ 1472fcf5ef2aSThomas Huth .type2 = _typ2, \ 1473fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1474fcf5ef2aSThomas Huth }, \ 1475fcf5ef2aSThomas Huth .oname = onam, \ 1476fcf5ef2aSThomas Huth } 1477fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1478fcf5ef2aSThomas Huth { \ 1479fcf5ef2aSThomas Huth .opc1 = op1, \ 1480fcf5ef2aSThomas Huth .opc2 = op2, \ 1481fcf5ef2aSThomas Huth .opc3 = op3, \ 1482fcf5ef2aSThomas Huth .opc4 = op4, \ 1483fcf5ef2aSThomas Huth .handler = { \ 1484fcf5ef2aSThomas Huth .inval1 = invl, \ 1485fcf5ef2aSThomas Huth .type = _typ, \ 1486fcf5ef2aSThomas Huth .type2 = _typ2, \ 1487fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1488fcf5ef2aSThomas Huth }, \ 1489fcf5ef2aSThomas Huth .oname = stringify(name), \ 1490fcf5ef2aSThomas Huth } 1491fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1492fcf5ef2aSThomas Huth { \ 1493fcf5ef2aSThomas Huth .opc1 = op1, \ 1494fcf5ef2aSThomas Huth .opc2 = op2, \ 1495fcf5ef2aSThomas Huth .opc3 = op3, \ 1496fcf5ef2aSThomas Huth .opc4 = op4, \ 1497fcf5ef2aSThomas Huth .handler = { \ 1498fcf5ef2aSThomas Huth .inval1 = invl, \ 1499fcf5ef2aSThomas Huth .type = _typ, \ 1500fcf5ef2aSThomas Huth .type2 = _typ2, \ 1501fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1502fcf5ef2aSThomas Huth }, \ 1503fcf5ef2aSThomas Huth .oname = onam, \ 1504fcf5ef2aSThomas Huth } 1505fcf5ef2aSThomas Huth #endif 1506fcf5ef2aSThomas Huth 1507fcf5ef2aSThomas Huth /* Invalid instruction */ 1508fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1509fcf5ef2aSThomas Huth { 1510fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1511fcf5ef2aSThomas Huth } 1512fcf5ef2aSThomas Huth 1513fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1514fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1515fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1516fcf5ef2aSThomas Huth .type = PPC_NONE, 1517fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1518fcf5ef2aSThomas Huth .handler = gen_invalid, 1519fcf5ef2aSThomas Huth }; 1520fcf5ef2aSThomas Huth 1521fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1522fcf5ef2aSThomas Huth 1523fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1524fcf5ef2aSThomas Huth { 1525fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1526b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1527b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1528fcf5ef2aSThomas Huth 1529b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1530b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1531efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1532efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1533b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1534efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1535efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1536b62b3686Spbonzini@redhat.com 1537b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1538fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1539b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1540fcf5ef2aSThomas Huth 1541fcf5ef2aSThomas Huth tcg_temp_free(t0); 1542b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1543b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1544fcf5ef2aSThomas Huth } 1545fcf5ef2aSThomas Huth 1546fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1547fcf5ef2aSThomas Huth { 1548fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1549fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1550fcf5ef2aSThomas Huth tcg_temp_free(t0); 1551fcf5ef2aSThomas Huth } 1552fcf5ef2aSThomas Huth 1553fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1554fcf5ef2aSThomas Huth { 1555fcf5ef2aSThomas Huth TCGv t0, t1; 1556fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1557fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1558fcf5ef2aSThomas Huth if (s) { 1559fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1560fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1561fcf5ef2aSThomas Huth } else { 1562fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1563fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1564fcf5ef2aSThomas Huth } 1565fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1566fcf5ef2aSThomas Huth tcg_temp_free(t1); 1567fcf5ef2aSThomas Huth tcg_temp_free(t0); 1568fcf5ef2aSThomas Huth } 1569fcf5ef2aSThomas Huth 1570fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1571fcf5ef2aSThomas Huth { 1572fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1573fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1574fcf5ef2aSThomas Huth tcg_temp_free(t0); 1575fcf5ef2aSThomas Huth } 1576fcf5ef2aSThomas Huth 1577fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1578fcf5ef2aSThomas Huth { 1579fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1580fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1581fcf5ef2aSThomas Huth } else { 1582fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1583fcf5ef2aSThomas Huth } 1584fcf5ef2aSThomas Huth } 1585fcf5ef2aSThomas Huth 1586fcf5ef2aSThomas Huth /* cmp */ 1587fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1588fcf5ef2aSThomas Huth { 1589fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1590fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1591fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1592fcf5ef2aSThomas Huth } else { 1593fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1594fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1595fcf5ef2aSThomas Huth } 1596fcf5ef2aSThomas Huth } 1597fcf5ef2aSThomas Huth 1598fcf5ef2aSThomas Huth /* cmpi */ 1599fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1600fcf5ef2aSThomas Huth { 1601fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1602fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1603fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1604fcf5ef2aSThomas Huth } else { 1605fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1606fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1607fcf5ef2aSThomas Huth } 1608fcf5ef2aSThomas Huth } 1609fcf5ef2aSThomas Huth 1610fcf5ef2aSThomas Huth /* cmpl */ 1611fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1612fcf5ef2aSThomas Huth { 1613fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1614fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1615fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1616fcf5ef2aSThomas Huth } else { 1617fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1618fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1619fcf5ef2aSThomas Huth } 1620fcf5ef2aSThomas Huth } 1621fcf5ef2aSThomas Huth 1622fcf5ef2aSThomas Huth /* cmpli */ 1623fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1624fcf5ef2aSThomas Huth { 1625fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1626fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1627fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1628fcf5ef2aSThomas Huth } else { 1629fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1630fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1631fcf5ef2aSThomas Huth } 1632fcf5ef2aSThomas Huth } 1633fcf5ef2aSThomas Huth 1634fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1635fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1636fcf5ef2aSThomas Huth { 1637fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1638fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1639fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1640fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1641fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1642fcf5ef2aSThomas Huth 1643fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1644fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1645fcf5ef2aSThomas Huth 1646fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1647fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1648fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1649fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1650fcf5ef2aSThomas Huth 1651fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1652fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1653fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1654fcf5ef2aSThomas Huth 1655fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1656fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1657fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1658fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1659fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1660fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1661fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1662fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1663fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1664fcf5ef2aSThomas Huth } 1665efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1666fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1667fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1668fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1669fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth 1672fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1673fcf5ef2aSThomas Huth /* cmpeqb */ 1674fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1675fcf5ef2aSThomas Huth { 1676fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1677fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1678fcf5ef2aSThomas Huth } 1679fcf5ef2aSThomas Huth #endif 1680fcf5ef2aSThomas Huth 1681fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1682fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1683fcf5ef2aSThomas Huth { 1684fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1685fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1686fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1687fcf5ef2aSThomas Huth TCGv zr; 1688fcf5ef2aSThomas Huth 1689fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1690fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1691fcf5ef2aSThomas Huth 1692fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1693fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1694fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1695fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1696fcf5ef2aSThomas Huth tcg_temp_free(zr); 1697fcf5ef2aSThomas Huth tcg_temp_free(t0); 1698fcf5ef2aSThomas Huth } 1699fcf5ef2aSThomas Huth 1700fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1701fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1702fcf5ef2aSThomas Huth { 1703fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1704fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1705fcf5ef2aSThomas Huth } 1706fcf5ef2aSThomas Huth 1707fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1708fcf5ef2aSThomas Huth 1709fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1710fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1711fcf5ef2aSThomas Huth { 1712fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1713fcf5ef2aSThomas Huth 1714fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1715fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1716fcf5ef2aSThomas Huth if (sub) { 1717fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1718fcf5ef2aSThomas Huth } else { 1719fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1720fcf5ef2aSThomas Huth } 1721fcf5ef2aSThomas Huth tcg_temp_free(t0); 1722fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1723dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1724dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1725dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1726fcf5ef2aSThomas Huth } 1727dc0ad844SNikunj A Dadhania } else { 1728dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1729dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1730dc0ad844SNikunj A Dadhania } 173138a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1732dc0ad844SNikunj A Dadhania } 1733fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1734fcf5ef2aSThomas Huth } 1735fcf5ef2aSThomas Huth 17366b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 17376b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 17384c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 17396b10d008SNikunj A Dadhania { 17406b10d008SNikunj A Dadhania TCGv t0; 17416b10d008SNikunj A Dadhania 17426b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 17436b10d008SNikunj A Dadhania return; 17446b10d008SNikunj A Dadhania } 17456b10d008SNikunj A Dadhania 17466b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 174733903d0aSNikunj A Dadhania if (sub) { 174833903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 174933903d0aSNikunj A Dadhania } else { 17506b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 175133903d0aSNikunj A Dadhania } 17526b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 17534c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 17546b10d008SNikunj A Dadhania tcg_temp_free(t0); 17556b10d008SNikunj A Dadhania } 17566b10d008SNikunj A Dadhania 1757fcf5ef2aSThomas Huth /* Common add function */ 1758fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 17594c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 17604c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1761fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1762fcf5ef2aSThomas Huth { 1763fcf5ef2aSThomas Huth TCGv t0 = ret; 1764fcf5ef2aSThomas Huth 1765fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1766fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1767fcf5ef2aSThomas Huth } 1768fcf5ef2aSThomas Huth 1769fcf5ef2aSThomas Huth if (compute_ca) { 1770fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1771efe843d8SDavid Gibson /* 1772efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1773efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1774efe843d8SDavid Gibson * produce the carry into bit 32. 1775efe843d8SDavid Gibson */ 1776fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1777fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1778fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1779fcf5ef2aSThomas Huth if (add_ca) { 17804c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1781fcf5ef2aSThomas Huth } 17824c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1783fcf5ef2aSThomas Huth tcg_temp_free(t1); 17844c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 17856b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 17864c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 17876b10d008SNikunj A Dadhania } 1788fcf5ef2aSThomas Huth } else { 1789fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1790fcf5ef2aSThomas Huth if (add_ca) { 17914c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 17924c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1793fcf5ef2aSThomas Huth } else { 17944c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1795fcf5ef2aSThomas Huth } 17964c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1797fcf5ef2aSThomas Huth tcg_temp_free(zero); 1798fcf5ef2aSThomas Huth } 1799fcf5ef2aSThomas Huth } else { 1800fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1801fcf5ef2aSThomas Huth if (add_ca) { 18024c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1803fcf5ef2aSThomas Huth } 1804fcf5ef2aSThomas Huth } 1805fcf5ef2aSThomas Huth 1806fcf5ef2aSThomas Huth if (compute_ov) { 1807fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1808fcf5ef2aSThomas Huth } 1809fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1810fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1811fcf5ef2aSThomas Huth } 1812fcf5ef2aSThomas Huth 181311f4e8f8SRichard Henderson if (t0 != ret) { 1814fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1815fcf5ef2aSThomas Huth tcg_temp_free(t0); 1816fcf5ef2aSThomas Huth } 1817fcf5ef2aSThomas Huth } 1818fcf5ef2aSThomas Huth /* Add functions with two operands */ 18194c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1820fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1821fcf5ef2aSThomas Huth { \ 1822fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1823fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 18244c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1825fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1826fcf5ef2aSThomas Huth } 1827fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 18284c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1829fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1830fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1831fcf5ef2aSThomas Huth { \ 1832fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1833fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1834fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 18354c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1836fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1837fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1838fcf5ef2aSThomas Huth } 1839fcf5ef2aSThomas Huth 1840fcf5ef2aSThomas Huth /* add add. addo addo. */ 18414c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 18424c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1843fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 18444c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 18454c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1846fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 18474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 18484c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1849fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 18504c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 18514c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 18524c5920afSSuraj Jitindar Singh /* addex */ 18534c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1854fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 18554c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 18564c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1857fcf5ef2aSThomas Huth /* addi */ 1858fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 1859fcf5ef2aSThomas Huth { 1860fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1861fcf5ef2aSThomas Huth 1862fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1863fcf5ef2aSThomas Huth /* li case */ 1864fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 1865fcf5ef2aSThomas Huth } else { 1866fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1867fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 1868fcf5ef2aSThomas Huth } 1869fcf5ef2aSThomas Huth } 1870fcf5ef2aSThomas Huth /* addic addic.*/ 1871fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1872fcf5ef2aSThomas Huth { 1873fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1874fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 18754c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1876fcf5ef2aSThomas Huth tcg_temp_free(c); 1877fcf5ef2aSThomas Huth } 1878fcf5ef2aSThomas Huth 1879fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1880fcf5ef2aSThomas Huth { 1881fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1882fcf5ef2aSThomas Huth } 1883fcf5ef2aSThomas Huth 1884fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1885fcf5ef2aSThomas Huth { 1886fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1887fcf5ef2aSThomas Huth } 1888fcf5ef2aSThomas Huth 1889fcf5ef2aSThomas Huth /* addis */ 1890fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 1891fcf5ef2aSThomas Huth { 1892fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1893fcf5ef2aSThomas Huth 1894fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1895fcf5ef2aSThomas Huth /* lis case */ 1896fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 1897fcf5ef2aSThomas Huth } else { 1898fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1899fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 1900fcf5ef2aSThomas Huth } 1901fcf5ef2aSThomas Huth } 1902fcf5ef2aSThomas Huth 1903fcf5ef2aSThomas Huth /* addpcis */ 1904fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 1905fcf5ef2aSThomas Huth { 1906fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 1907fcf5ef2aSThomas Huth 1908b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 1909fcf5ef2aSThomas Huth } 1910fcf5ef2aSThomas Huth 1911fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1912fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1913fcf5ef2aSThomas Huth { 1914fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1915fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1916fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1917fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1918fcf5ef2aSThomas Huth 1919fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1920fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1921fcf5ef2aSThomas Huth if (sign) { 1922fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1923fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1924fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1925fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1926fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1927fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1928fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1929fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1930fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1931fcf5ef2aSThomas Huth } else { 1932fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1933fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1934fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1935fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1936fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1937fcf5ef2aSThomas Huth } 1938fcf5ef2aSThomas Huth if (compute_ov) { 1939fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1940c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1941c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1942c44027ffSNikunj A Dadhania } 1943fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1944fcf5ef2aSThomas Huth } 1945fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1946fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1947fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1948fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1949fcf5ef2aSThomas Huth 1950efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1951fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1952fcf5ef2aSThomas Huth } 1953efe843d8SDavid Gibson } 1954fcf5ef2aSThomas Huth /* Div functions */ 1955fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1956fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1957fcf5ef2aSThomas Huth { \ 1958fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1959fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1960fcf5ef2aSThomas Huth sign, compute_ov); \ 1961fcf5ef2aSThomas Huth } 1962fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1963fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1964fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1965fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1966fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1967fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1968fcf5ef2aSThomas Huth 1969fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1970fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1971fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1972fcf5ef2aSThomas Huth { \ 1973fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1974fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1975fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1976fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1977fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1978fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1979fcf5ef2aSThomas Huth } \ 1980fcf5ef2aSThomas Huth } 1981fcf5ef2aSThomas Huth 1982fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1983fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1984fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1985fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1986fcf5ef2aSThomas Huth 1987fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1988fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1989fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1990fcf5ef2aSThomas Huth { 1991fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1992fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1993fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1994fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1995fcf5ef2aSThomas Huth 1996fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1997fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1998fcf5ef2aSThomas Huth if (sign) { 1999fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2000fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2001fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2002fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2003fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2004fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2005fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2006fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 2007fcf5ef2aSThomas Huth } else { 2008fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 2009fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2010fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2011fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 2012fcf5ef2aSThomas Huth } 2013fcf5ef2aSThomas Huth if (compute_ov) { 2014fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 2015c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2016c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 2017c44027ffSNikunj A Dadhania } 2018fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2019fcf5ef2aSThomas Huth } 2020fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2021fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2022fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2023fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2024fcf5ef2aSThomas Huth 2025efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2026fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2027fcf5ef2aSThomas Huth } 2028efe843d8SDavid Gibson } 2029fcf5ef2aSThomas Huth 2030fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 2031fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2032fcf5ef2aSThomas Huth { \ 2033fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2034fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2035fcf5ef2aSThomas Huth sign, compute_ov); \ 2036fcf5ef2aSThomas Huth } 2037c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 2038fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 2039fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 2040c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 2041fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 2042fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 2043fcf5ef2aSThomas Huth 2044fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 2045fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 2046fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 2047fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 2048fcf5ef2aSThomas Huth #endif 2049fcf5ef2aSThomas Huth 2050fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 2051fcf5ef2aSThomas Huth TCGv arg2, int sign) 2052fcf5ef2aSThomas Huth { 2053fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2054fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2055fcf5ef2aSThomas Huth 2056fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2057fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2058fcf5ef2aSThomas Huth if (sign) { 2059fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2060fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2061fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2062fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2063fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2064fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2065fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2066fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2067fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2068fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 2069fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 2070fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2071fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2072fcf5ef2aSThomas Huth } else { 2073fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 2074fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 2075fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 2076fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 2077fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2078fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2079fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2080fcf5ef2aSThomas Huth } 2081fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2082fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2083fcf5ef2aSThomas Huth } 2084fcf5ef2aSThomas Huth 2085fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 2086fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2087fcf5ef2aSThomas Huth { \ 2088fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2089fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2090fcf5ef2aSThomas Huth sign); \ 2091fcf5ef2aSThomas Huth } 2092fcf5ef2aSThomas Huth 2093fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 2094fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 2095fcf5ef2aSThomas Huth 2096fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2097fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 2098fcf5ef2aSThomas Huth TCGv arg2, int sign) 2099fcf5ef2aSThomas Huth { 2100fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2101fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2102fcf5ef2aSThomas Huth 2103fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2104fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2105fcf5ef2aSThomas Huth if (sign) { 2106fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2107fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2108fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2109fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2110fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2111fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2112fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2113fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2114fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2115fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 2116fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2117fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2118fcf5ef2aSThomas Huth } else { 2119fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 2120fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2121fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2122fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2123fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2124fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2125fcf5ef2aSThomas Huth } 2126fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2127fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2128fcf5ef2aSThomas Huth } 2129fcf5ef2aSThomas Huth 2130fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2131fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2132fcf5ef2aSThomas Huth { \ 2133fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2134fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2135fcf5ef2aSThomas Huth sign); \ 2136fcf5ef2aSThomas Huth } 2137fcf5ef2aSThomas Huth 2138fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2139fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2140fcf5ef2aSThomas Huth #endif 2141fcf5ef2aSThomas Huth 2142fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2143fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2144fcf5ef2aSThomas Huth { 2145fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2146fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2147fcf5ef2aSThomas Huth 2148fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2149fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2150fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2151fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2152fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2153fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2154efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2155fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2156fcf5ef2aSThomas Huth } 2157efe843d8SDavid Gibson } 2158fcf5ef2aSThomas Huth 2159fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2160fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2161fcf5ef2aSThomas Huth { 2162fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2163fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2164fcf5ef2aSThomas Huth 2165fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2166fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2167fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2168fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2169fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2170fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2171efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2172fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2173fcf5ef2aSThomas Huth } 2174efe843d8SDavid Gibson } 2175fcf5ef2aSThomas Huth 2176fcf5ef2aSThomas Huth /* mullw mullw. */ 2177fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2178fcf5ef2aSThomas Huth { 2179fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2180fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2181fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2182fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2183fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2184fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2185fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2186fcf5ef2aSThomas Huth tcg_temp_free(t0); 2187fcf5ef2aSThomas Huth tcg_temp_free(t1); 2188fcf5ef2aSThomas Huth #else 2189fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2190fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2191fcf5ef2aSThomas Huth #endif 2192efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2193fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2194fcf5ef2aSThomas Huth } 2195efe843d8SDavid Gibson } 2196fcf5ef2aSThomas Huth 2197fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2198fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2199fcf5ef2aSThomas Huth { 2200fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2201fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2202fcf5ef2aSThomas Huth 2203fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2204fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2205fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2206fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2207fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2208fcf5ef2aSThomas Huth #else 2209fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2210fcf5ef2aSThomas Huth #endif 2211fcf5ef2aSThomas Huth 2212fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2213fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2214fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 221561aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 221661aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 221761aa9a69SNikunj A Dadhania } 2218fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2219fcf5ef2aSThomas Huth 2220fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2221fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2222efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2223fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2224fcf5ef2aSThomas Huth } 2225efe843d8SDavid Gibson } 2226fcf5ef2aSThomas Huth 2227fcf5ef2aSThomas Huth /* mulli */ 2228fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2229fcf5ef2aSThomas Huth { 2230fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2231fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2232fcf5ef2aSThomas Huth } 2233fcf5ef2aSThomas Huth 2234fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2235fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2236fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2237fcf5ef2aSThomas Huth { 2238fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2239fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2240fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2241fcf5ef2aSThomas Huth tcg_temp_free(lo); 2242fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2243fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2244fcf5ef2aSThomas Huth } 2245fcf5ef2aSThomas Huth } 2246fcf5ef2aSThomas Huth 2247fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2248fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2249fcf5ef2aSThomas Huth { 2250fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2251fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2252fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2253fcf5ef2aSThomas Huth tcg_temp_free(lo); 2254fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2255fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2256fcf5ef2aSThomas Huth } 2257fcf5ef2aSThomas Huth } 2258fcf5ef2aSThomas Huth 2259fcf5ef2aSThomas Huth /* mulld mulld. */ 2260fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2261fcf5ef2aSThomas Huth { 2262fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2263fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2264efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2265fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2266fcf5ef2aSThomas Huth } 2267efe843d8SDavid Gibson } 2268fcf5ef2aSThomas Huth 2269fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2270fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2271fcf5ef2aSThomas Huth { 2272fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2273fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2274fcf5ef2aSThomas Huth 2275fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2276fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2277fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2278fcf5ef2aSThomas Huth 2279fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2280fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 228161aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 228261aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 228361aa9a69SNikunj A Dadhania } 2284fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2285fcf5ef2aSThomas Huth 2286fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2287fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2288fcf5ef2aSThomas Huth 2289fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2290fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2291fcf5ef2aSThomas Huth } 2292fcf5ef2aSThomas Huth } 2293fcf5ef2aSThomas Huth #endif 2294fcf5ef2aSThomas Huth 2295fcf5ef2aSThomas Huth /* Common subf function */ 2296fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2297fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2298fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2299fcf5ef2aSThomas Huth { 2300fcf5ef2aSThomas Huth TCGv t0 = ret; 2301fcf5ef2aSThomas Huth 2302fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2303fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2304fcf5ef2aSThomas Huth } 2305fcf5ef2aSThomas Huth 2306fcf5ef2aSThomas Huth if (compute_ca) { 2307fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2308fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2309efe843d8SDavid Gibson /* 2310efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2311efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2312efe843d8SDavid Gibson * produce the carry into bit 32. 2313efe843d8SDavid Gibson */ 2314fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2315fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2316fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2317fcf5ef2aSThomas Huth if (add_ca) { 2318fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2319fcf5ef2aSThomas Huth } else { 2320fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2321fcf5ef2aSThomas Huth } 2322fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2323fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2324fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2325fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2326fcf5ef2aSThomas Huth tcg_temp_free(t1); 2327e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 232833903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 232933903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 233033903d0aSNikunj A Dadhania } 2331fcf5ef2aSThomas Huth } else if (add_ca) { 2332fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2333fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2334fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2335fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2336fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 23374c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2338fcf5ef2aSThomas Huth tcg_temp_free(zero); 2339fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2340fcf5ef2aSThomas Huth } else { 2341fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2342fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 23434c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2344fcf5ef2aSThomas Huth } 2345fcf5ef2aSThomas Huth } else if (add_ca) { 2346efe843d8SDavid Gibson /* 2347efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2348efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2349efe843d8SDavid Gibson */ 2350fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2351fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2352fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2353fcf5ef2aSThomas Huth } else { 2354fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2355fcf5ef2aSThomas Huth } 2356fcf5ef2aSThomas Huth 2357fcf5ef2aSThomas Huth if (compute_ov) { 2358fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2359fcf5ef2aSThomas Huth } 2360fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2361fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2362fcf5ef2aSThomas Huth } 2363fcf5ef2aSThomas Huth 236411f4e8f8SRichard Henderson if (t0 != ret) { 2365fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2366fcf5ef2aSThomas Huth tcg_temp_free(t0); 2367fcf5ef2aSThomas Huth } 2368fcf5ef2aSThomas Huth } 2369fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2370fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2371fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2372fcf5ef2aSThomas Huth { \ 2373fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2374fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2375fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2376fcf5ef2aSThomas Huth } 2377fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2378fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2379fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2380fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2381fcf5ef2aSThomas Huth { \ 2382fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2383fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2384fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2385fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2386fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2387fcf5ef2aSThomas Huth } 2388fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2389fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2390fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2391fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2392fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2393fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2394fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2395fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2396fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2397fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2398fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2399fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2400fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2401fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2402fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2403fcf5ef2aSThomas Huth 2404fcf5ef2aSThomas Huth /* subfic */ 2405fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2406fcf5ef2aSThomas Huth { 2407fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2408fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2409fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2410fcf5ef2aSThomas Huth tcg_temp_free(c); 2411fcf5ef2aSThomas Huth } 2412fcf5ef2aSThomas Huth 2413fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2414fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2415fcf5ef2aSThomas Huth { 2416fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2417fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2418fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2419fcf5ef2aSThomas Huth tcg_temp_free(zero); 2420fcf5ef2aSThomas Huth } 2421fcf5ef2aSThomas Huth 2422fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2423fcf5ef2aSThomas Huth { 24241480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 24251480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 24261480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 24271480d71cSNikunj A Dadhania } 2428fcf5ef2aSThomas Huth } 2429fcf5ef2aSThomas Huth 2430fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2431fcf5ef2aSThomas Huth { 2432fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2433fcf5ef2aSThomas Huth } 2434fcf5ef2aSThomas Huth 2435fcf5ef2aSThomas Huth /*** Integer logical ***/ 2436fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2437fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2438fcf5ef2aSThomas Huth { \ 2439fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2440fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2441fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2442fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2443fcf5ef2aSThomas Huth } 2444fcf5ef2aSThomas Huth 2445fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2446fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2447fcf5ef2aSThomas Huth { \ 2448fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2449fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2450fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2451fcf5ef2aSThomas Huth } 2452fcf5ef2aSThomas Huth 2453fcf5ef2aSThomas Huth /* and & and. */ 2454fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2455fcf5ef2aSThomas Huth /* andc & andc. */ 2456fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2457fcf5ef2aSThomas Huth 2458fcf5ef2aSThomas Huth /* andi. */ 2459fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2460fcf5ef2aSThomas Huth { 2461efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2462efe843d8SDavid Gibson UIMM(ctx->opcode)); 2463fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2464fcf5ef2aSThomas Huth } 2465fcf5ef2aSThomas Huth 2466fcf5ef2aSThomas Huth /* andis. */ 2467fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2468fcf5ef2aSThomas Huth { 2469efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2470efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2471fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2472fcf5ef2aSThomas Huth } 2473fcf5ef2aSThomas Huth 2474fcf5ef2aSThomas Huth /* cntlzw */ 2475fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2476fcf5ef2aSThomas Huth { 24779b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 24789b8514e5SRichard Henderson 24799b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 24809b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 24819b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 24829b8514e5SRichard Henderson tcg_temp_free_i32(t); 24839b8514e5SRichard Henderson 2484efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2485fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2486fcf5ef2aSThomas Huth } 2487efe843d8SDavid Gibson } 2488fcf5ef2aSThomas Huth 2489fcf5ef2aSThomas Huth /* cnttzw */ 2490fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2491fcf5ef2aSThomas Huth { 24929b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 24939b8514e5SRichard Henderson 24949b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 24959b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 24969b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 24979b8514e5SRichard Henderson tcg_temp_free_i32(t); 24989b8514e5SRichard Henderson 2499fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2500fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2501fcf5ef2aSThomas Huth } 2502fcf5ef2aSThomas Huth } 2503fcf5ef2aSThomas Huth 2504fcf5ef2aSThomas Huth /* eqv & eqv. */ 2505fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2506fcf5ef2aSThomas Huth /* extsb & extsb. */ 2507fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2508fcf5ef2aSThomas Huth /* extsh & extsh. */ 2509fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2510fcf5ef2aSThomas Huth /* nand & nand. */ 2511fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2512fcf5ef2aSThomas Huth /* nor & nor. */ 2513fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2514fcf5ef2aSThomas Huth 2515fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2516fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2517fcf5ef2aSThomas Huth { 2518fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2519fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2520fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2521fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2522fcf5ef2aSThomas Huth 2523fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2524b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2525fcf5ef2aSThomas Huth } 2526fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2527fcf5ef2aSThomas Huth 2528fcf5ef2aSThomas Huth /* or & or. */ 2529fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2530fcf5ef2aSThomas Huth { 2531fcf5ef2aSThomas Huth int rs, ra, rb; 2532fcf5ef2aSThomas Huth 2533fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2534fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2535fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2536fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2537fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2538efe843d8SDavid Gibson if (rs != rb) { 2539fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2540efe843d8SDavid Gibson } else { 2541fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2542efe843d8SDavid Gibson } 2543efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2544fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2545efe843d8SDavid Gibson } 2546fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2547fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2548fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2549fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2550fcf5ef2aSThomas Huth int prio = 0; 2551fcf5ef2aSThomas Huth 2552fcf5ef2aSThomas Huth switch (rs) { 2553fcf5ef2aSThomas Huth case 1: 2554fcf5ef2aSThomas Huth /* Set process priority to low */ 2555fcf5ef2aSThomas Huth prio = 2; 2556fcf5ef2aSThomas Huth break; 2557fcf5ef2aSThomas Huth case 6: 2558fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2559fcf5ef2aSThomas Huth prio = 3; 2560fcf5ef2aSThomas Huth break; 2561fcf5ef2aSThomas Huth case 2: 2562fcf5ef2aSThomas Huth /* Set process priority to normal */ 2563fcf5ef2aSThomas Huth prio = 4; 2564fcf5ef2aSThomas Huth break; 2565fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2566fcf5ef2aSThomas Huth case 31: 2567fcf5ef2aSThomas Huth if (!ctx->pr) { 2568fcf5ef2aSThomas Huth /* Set process priority to very low */ 2569fcf5ef2aSThomas Huth prio = 1; 2570fcf5ef2aSThomas Huth } 2571fcf5ef2aSThomas Huth break; 2572fcf5ef2aSThomas Huth case 5: 2573fcf5ef2aSThomas Huth if (!ctx->pr) { 2574fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2575fcf5ef2aSThomas Huth prio = 5; 2576fcf5ef2aSThomas Huth } 2577fcf5ef2aSThomas Huth break; 2578fcf5ef2aSThomas Huth case 3: 2579fcf5ef2aSThomas Huth if (!ctx->pr) { 2580fcf5ef2aSThomas Huth /* Set process priority to high */ 2581fcf5ef2aSThomas Huth prio = 6; 2582fcf5ef2aSThomas Huth } 2583fcf5ef2aSThomas Huth break; 2584fcf5ef2aSThomas Huth case 7: 2585fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2586fcf5ef2aSThomas Huth /* Set process priority to very high */ 2587fcf5ef2aSThomas Huth prio = 7; 2588fcf5ef2aSThomas Huth } 2589fcf5ef2aSThomas Huth break; 2590fcf5ef2aSThomas Huth #endif 2591fcf5ef2aSThomas Huth default: 2592fcf5ef2aSThomas Huth break; 2593fcf5ef2aSThomas Huth } 2594fcf5ef2aSThomas Huth if (prio) { 2595fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2596fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2597fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2598fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2599fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2600fcf5ef2aSThomas Huth tcg_temp_free(t0); 2601fcf5ef2aSThomas Huth } 2602fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2603efe843d8SDavid Gibson /* 2604efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2605efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2606efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2607efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2608fcf5ef2aSThomas Huth */ 2609fcf5ef2aSThomas Huth gen_pause(ctx); 2610fcf5ef2aSThomas Huth #endif 2611fcf5ef2aSThomas Huth #endif 2612fcf5ef2aSThomas Huth } 2613fcf5ef2aSThomas Huth } 2614fcf5ef2aSThomas Huth /* orc & orc. */ 2615fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2616fcf5ef2aSThomas Huth 2617fcf5ef2aSThomas Huth /* xor & xor. */ 2618fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2619fcf5ef2aSThomas Huth { 2620fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2621efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2622efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2623efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2624efe843d8SDavid Gibson } else { 2625fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2626efe843d8SDavid Gibson } 2627efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2628fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2629fcf5ef2aSThomas Huth } 2630efe843d8SDavid Gibson } 2631fcf5ef2aSThomas Huth 2632fcf5ef2aSThomas Huth /* ori */ 2633fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2634fcf5ef2aSThomas Huth { 2635fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2636fcf5ef2aSThomas Huth 2637fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2638fcf5ef2aSThomas Huth return; 2639fcf5ef2aSThomas Huth } 2640fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2641fcf5ef2aSThomas Huth } 2642fcf5ef2aSThomas Huth 2643fcf5ef2aSThomas Huth /* oris */ 2644fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2645fcf5ef2aSThomas Huth { 2646fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2647fcf5ef2aSThomas Huth 2648fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2649fcf5ef2aSThomas Huth /* NOP */ 2650fcf5ef2aSThomas Huth return; 2651fcf5ef2aSThomas Huth } 2652efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2653efe843d8SDavid Gibson uimm << 16); 2654fcf5ef2aSThomas Huth } 2655fcf5ef2aSThomas Huth 2656fcf5ef2aSThomas Huth /* xori */ 2657fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2658fcf5ef2aSThomas Huth { 2659fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2660fcf5ef2aSThomas Huth 2661fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2662fcf5ef2aSThomas Huth /* NOP */ 2663fcf5ef2aSThomas Huth return; 2664fcf5ef2aSThomas Huth } 2665fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2666fcf5ef2aSThomas Huth } 2667fcf5ef2aSThomas Huth 2668fcf5ef2aSThomas Huth /* xoris */ 2669fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2670fcf5ef2aSThomas Huth { 2671fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2672fcf5ef2aSThomas Huth 2673fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2674fcf5ef2aSThomas Huth /* NOP */ 2675fcf5ef2aSThomas Huth return; 2676fcf5ef2aSThomas Huth } 2677efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2678efe843d8SDavid Gibson uimm << 16); 2679fcf5ef2aSThomas Huth } 2680fcf5ef2aSThomas Huth 2681fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2682fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2683fcf5ef2aSThomas Huth { 2684fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2685fcf5ef2aSThomas Huth } 2686fcf5ef2aSThomas Huth 2687fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2688fcf5ef2aSThomas Huth { 268979770002SRichard Henderson #if defined(TARGET_PPC64) 2690fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 269179770002SRichard Henderson #else 269279770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 269379770002SRichard Henderson #endif 2694fcf5ef2aSThomas Huth } 2695fcf5ef2aSThomas Huth 2696fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2697fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2698fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2699fcf5ef2aSThomas Huth { 270079770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2701fcf5ef2aSThomas Huth } 2702fcf5ef2aSThomas Huth #endif 2703fcf5ef2aSThomas Huth 2704fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2705fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2706fcf5ef2aSThomas Huth { 2707fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2708fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2709fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2710fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2711fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2712fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2713fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2714fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2715fcf5ef2aSThomas Huth tcg_temp_free(t0); 2716fcf5ef2aSThomas Huth } 2717fcf5ef2aSThomas Huth 2718fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2719fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2720fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2721fcf5ef2aSThomas Huth { 2722fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2723fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2724fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2725fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2726fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2727fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2728fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2729fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2730fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2731fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2732fcf5ef2aSThomas Huth tcg_temp_free(t0); 2733fcf5ef2aSThomas Huth } 2734fcf5ef2aSThomas Huth #endif 2735fcf5ef2aSThomas Huth 2736fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2737fcf5ef2aSThomas Huth /* bpermd */ 2738fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2739fcf5ef2aSThomas Huth { 2740fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2741fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2742fcf5ef2aSThomas Huth } 2743fcf5ef2aSThomas Huth #endif 2744fcf5ef2aSThomas Huth 2745fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2746fcf5ef2aSThomas Huth /* extsw & extsw. */ 2747fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2748fcf5ef2aSThomas Huth 2749fcf5ef2aSThomas Huth /* cntlzd */ 2750fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2751fcf5ef2aSThomas Huth { 27529b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2753efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2754fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2755fcf5ef2aSThomas Huth } 2756efe843d8SDavid Gibson } 2757fcf5ef2aSThomas Huth 2758fcf5ef2aSThomas Huth /* cnttzd */ 2759fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2760fcf5ef2aSThomas Huth { 27619b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2762fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2763fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2764fcf5ef2aSThomas Huth } 2765fcf5ef2aSThomas Huth } 2766fcf5ef2aSThomas Huth 2767fcf5ef2aSThomas Huth /* darn */ 2768fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2769fcf5ef2aSThomas Huth { 2770fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2771fcf5ef2aSThomas Huth 27727e4357f6SRichard Henderson if (l > 2) { 27737e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 27747e4357f6SRichard Henderson } else { 2775f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2776fcf5ef2aSThomas Huth if (l == 0) { 2777fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 27787e4357f6SRichard Henderson } else { 2779fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2780fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 27817e4357f6SRichard Henderson } 2782fcf5ef2aSThomas Huth } 2783fcf5ef2aSThomas Huth } 2784fcf5ef2aSThomas Huth #endif 2785fcf5ef2aSThomas Huth 2786fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2787fcf5ef2aSThomas Huth 2788fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2789fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2790fcf5ef2aSThomas Huth { 2791fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2792fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2793fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2794fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2795fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2796fcf5ef2aSThomas Huth 2797fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2798fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2799fcf5ef2aSThomas Huth } else { 2800fcf5ef2aSThomas Huth target_ulong mask; 2801c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2802fcf5ef2aSThomas Huth TCGv t1; 2803fcf5ef2aSThomas Huth 2804fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2805fcf5ef2aSThomas Huth mb += 32; 2806fcf5ef2aSThomas Huth me += 32; 2807fcf5ef2aSThomas Huth #endif 2808fcf5ef2aSThomas Huth mask = MASK(mb, me); 2809fcf5ef2aSThomas Huth 2810c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2811c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2812c4f6a4a3SDaniele Buono mask_in_32b = false; 2813c4f6a4a3SDaniele Buono } 2814c4f6a4a3SDaniele Buono #endif 2815fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2816c4f6a4a3SDaniele Buono if (mask_in_32b) { 2817fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2818fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2819fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2820fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2821fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2822fcf5ef2aSThomas Huth } else { 2823fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2824fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2825fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2826fcf5ef2aSThomas Huth #else 2827fcf5ef2aSThomas Huth g_assert_not_reached(); 2828fcf5ef2aSThomas Huth #endif 2829fcf5ef2aSThomas Huth } 2830fcf5ef2aSThomas Huth 2831fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2832fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2833fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2834fcf5ef2aSThomas Huth tcg_temp_free(t1); 2835fcf5ef2aSThomas Huth } 2836fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2837fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2838fcf5ef2aSThomas Huth } 2839fcf5ef2aSThomas Huth } 2840fcf5ef2aSThomas Huth 2841fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2842fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2843fcf5ef2aSThomas Huth { 2844fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2845fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28467b4d326fSRichard Henderson int sh = SH(ctx->opcode); 28477b4d326fSRichard Henderson int mb = MB(ctx->opcode); 28487b4d326fSRichard Henderson int me = ME(ctx->opcode); 28497b4d326fSRichard Henderson int len = me - mb + 1; 28507b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2851fcf5ef2aSThomas Huth 28527b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 28537b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28547b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 28557b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2856fcf5ef2aSThomas Huth } else { 2857fcf5ef2aSThomas Huth target_ulong mask; 2858c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2859fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2860fcf5ef2aSThomas Huth mb += 32; 2861fcf5ef2aSThomas Huth me += 32; 2862fcf5ef2aSThomas Huth #endif 2863fcf5ef2aSThomas Huth mask = MASK(mb, me); 2864c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2865c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2866c4f6a4a3SDaniele Buono mask_in_32b = false; 2867c4f6a4a3SDaniele Buono } 2868c4f6a4a3SDaniele Buono #endif 2869c4f6a4a3SDaniele Buono if (mask_in_32b) { 28707b4d326fSRichard Henderson if (sh == 0) { 28717b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 287294f040aaSVitaly Chikunov } else { 2873fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2874fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2875fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2876fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2877fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2878fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 287994f040aaSVitaly Chikunov } 2880fcf5ef2aSThomas Huth } else { 2881fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2882fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2883fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2884fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2885fcf5ef2aSThomas Huth #else 2886fcf5ef2aSThomas Huth g_assert_not_reached(); 2887fcf5ef2aSThomas Huth #endif 2888fcf5ef2aSThomas Huth } 2889fcf5ef2aSThomas Huth } 2890fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2891fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2892fcf5ef2aSThomas Huth } 2893fcf5ef2aSThomas Huth } 2894fcf5ef2aSThomas Huth 2895fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2896fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2897fcf5ef2aSThomas Huth { 2898fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2899fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2900fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2901fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2902fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2903fcf5ef2aSThomas Huth target_ulong mask; 2904c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2905fcf5ef2aSThomas Huth 2906fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2907fcf5ef2aSThomas Huth mb += 32; 2908fcf5ef2aSThomas Huth me += 32; 2909fcf5ef2aSThomas Huth #endif 2910fcf5ef2aSThomas Huth mask = MASK(mb, me); 2911fcf5ef2aSThomas Huth 2912c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2913c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2914c4f6a4a3SDaniele Buono mask_in_32b = false; 2915c4f6a4a3SDaniele Buono } 2916c4f6a4a3SDaniele Buono #endif 2917c4f6a4a3SDaniele Buono if (mask_in_32b) { 2918fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2919fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2920fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2921fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2922fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2923fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2924fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2925fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2926fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2927fcf5ef2aSThomas Huth } else { 2928fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2929fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2930fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2931fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2932fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2933fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2934fcf5ef2aSThomas Huth #else 2935fcf5ef2aSThomas Huth g_assert_not_reached(); 2936fcf5ef2aSThomas Huth #endif 2937fcf5ef2aSThomas Huth } 2938fcf5ef2aSThomas Huth 2939fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2940fcf5ef2aSThomas Huth 2941fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2942fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2943fcf5ef2aSThomas Huth } 2944fcf5ef2aSThomas Huth } 2945fcf5ef2aSThomas Huth 2946fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2947fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2948fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2949fcf5ef2aSThomas Huth { \ 2950fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2951fcf5ef2aSThomas Huth } \ 2952fcf5ef2aSThomas Huth \ 2953fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2954fcf5ef2aSThomas Huth { \ 2955fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2956fcf5ef2aSThomas Huth } 2957fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2958fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2959fcf5ef2aSThomas Huth { \ 2960fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2961fcf5ef2aSThomas Huth } \ 2962fcf5ef2aSThomas Huth \ 2963fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2964fcf5ef2aSThomas Huth { \ 2965fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2966fcf5ef2aSThomas Huth } \ 2967fcf5ef2aSThomas Huth \ 2968fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2969fcf5ef2aSThomas Huth { \ 2970fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2971fcf5ef2aSThomas Huth } \ 2972fcf5ef2aSThomas Huth \ 2973fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2974fcf5ef2aSThomas Huth { \ 2975fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2976fcf5ef2aSThomas Huth } 2977fcf5ef2aSThomas Huth 2978fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2979fcf5ef2aSThomas Huth { 2980fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2981fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 29827b4d326fSRichard Henderson int len = me - mb + 1; 29837b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2984fcf5ef2aSThomas Huth 29857b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 29867b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 29877b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 29887b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2989fcf5ef2aSThomas Huth } else { 2990fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2991fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2992fcf5ef2aSThomas Huth } 2993fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2994fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2995fcf5ef2aSThomas Huth } 2996fcf5ef2aSThomas Huth } 2997fcf5ef2aSThomas Huth 2998fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2999fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 3000fcf5ef2aSThomas Huth { 3001fcf5ef2aSThomas Huth uint32_t sh, mb; 3002fcf5ef2aSThomas Huth 3003fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3004fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3005fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 3006fcf5ef2aSThomas Huth } 3007fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 3008fcf5ef2aSThomas Huth 3009fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 3010fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 3011fcf5ef2aSThomas Huth { 3012fcf5ef2aSThomas Huth uint32_t sh, me; 3013fcf5ef2aSThomas Huth 3014fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3015fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3016fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 3017fcf5ef2aSThomas Huth } 3018fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 3019fcf5ef2aSThomas Huth 3020fcf5ef2aSThomas Huth /* rldic - rldic. */ 3021fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 3022fcf5ef2aSThomas Huth { 3023fcf5ef2aSThomas Huth uint32_t sh, mb; 3024fcf5ef2aSThomas Huth 3025fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3026fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3027fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 3028fcf5ef2aSThomas Huth } 3029fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 3030fcf5ef2aSThomas Huth 3031fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 3032fcf5ef2aSThomas Huth { 3033fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3034fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3035fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3036fcf5ef2aSThomas Huth TCGv t0; 3037fcf5ef2aSThomas Huth 3038fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3039fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 3040fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 3041fcf5ef2aSThomas Huth tcg_temp_free(t0); 3042fcf5ef2aSThomas Huth 3043fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3044fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3045fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3046fcf5ef2aSThomas Huth } 3047fcf5ef2aSThomas Huth } 3048fcf5ef2aSThomas Huth 3049fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 3050fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 3051fcf5ef2aSThomas Huth { 3052fcf5ef2aSThomas Huth uint32_t mb; 3053fcf5ef2aSThomas Huth 3054fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3055fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 3056fcf5ef2aSThomas Huth } 3057fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 3058fcf5ef2aSThomas Huth 3059fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 3060fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 3061fcf5ef2aSThomas Huth { 3062fcf5ef2aSThomas Huth uint32_t me; 3063fcf5ef2aSThomas Huth 3064fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3065fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 3066fcf5ef2aSThomas Huth } 3067fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 3068fcf5ef2aSThomas Huth 3069fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 3070fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 3071fcf5ef2aSThomas Huth { 3072fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3073fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3074fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 3075fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 3076fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 3077fcf5ef2aSThomas Huth 3078fcf5ef2aSThomas Huth if (mb <= me) { 3079fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 3080fcf5ef2aSThomas Huth } else { 3081fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 3082fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3083fcf5ef2aSThomas Huth 3084fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 3085fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 3086fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 3087fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 3088fcf5ef2aSThomas Huth tcg_temp_free(t1); 3089fcf5ef2aSThomas Huth } 3090fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3091fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3092fcf5ef2aSThomas Huth } 3093fcf5ef2aSThomas Huth } 3094fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 3095fcf5ef2aSThomas Huth #endif 3096fcf5ef2aSThomas Huth 3097fcf5ef2aSThomas Huth /*** Integer shift ***/ 3098fcf5ef2aSThomas Huth 3099fcf5ef2aSThomas Huth /* slw & slw. */ 3100fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 3101fcf5ef2aSThomas Huth { 3102fcf5ef2aSThomas Huth TCGv t0, t1; 3103fcf5ef2aSThomas Huth 3104fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3105fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3106fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3107fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3108fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3109fcf5ef2aSThomas Huth #else 3110fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3111fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3112fcf5ef2aSThomas Huth #endif 3113fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3114fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3115fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3116fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3117fcf5ef2aSThomas Huth tcg_temp_free(t1); 3118fcf5ef2aSThomas Huth tcg_temp_free(t0); 3119fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 3120efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3121fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3122fcf5ef2aSThomas Huth } 3123efe843d8SDavid Gibson } 3124fcf5ef2aSThomas Huth 3125fcf5ef2aSThomas Huth /* sraw & sraw. */ 3126fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3127fcf5ef2aSThomas Huth { 3128fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3129fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3130efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3131fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3132fcf5ef2aSThomas Huth } 3133efe843d8SDavid Gibson } 3134fcf5ef2aSThomas Huth 3135fcf5ef2aSThomas Huth /* srawi & srawi. */ 3136fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3137fcf5ef2aSThomas Huth { 3138fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3139fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3140fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3141fcf5ef2aSThomas Huth if (sh == 0) { 3142fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3143fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3144af1c259fSSandipan Das if (is_isa300(ctx)) { 3145af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3146af1c259fSSandipan Das } 3147fcf5ef2aSThomas Huth } else { 3148fcf5ef2aSThomas Huth TCGv t0; 3149fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3150fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3151fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3152fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3153fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3154fcf5ef2aSThomas Huth tcg_temp_free(t0); 3155fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3156af1c259fSSandipan Das if (is_isa300(ctx)) { 3157af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3158af1c259fSSandipan Das } 3159fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3160fcf5ef2aSThomas Huth } 3161fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3162fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3163fcf5ef2aSThomas Huth } 3164fcf5ef2aSThomas Huth } 3165fcf5ef2aSThomas Huth 3166fcf5ef2aSThomas Huth /* srw & srw. */ 3167fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3168fcf5ef2aSThomas Huth { 3169fcf5ef2aSThomas Huth TCGv t0, t1; 3170fcf5ef2aSThomas Huth 3171fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3172fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3173fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3174fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3175fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3176fcf5ef2aSThomas Huth #else 3177fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3178fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3179fcf5ef2aSThomas Huth #endif 3180fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3181fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3182fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3183fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3184fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3185fcf5ef2aSThomas Huth tcg_temp_free(t1); 3186fcf5ef2aSThomas Huth tcg_temp_free(t0); 3187efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3188fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3189fcf5ef2aSThomas Huth } 3190efe843d8SDavid Gibson } 3191fcf5ef2aSThomas Huth 3192fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3193fcf5ef2aSThomas Huth /* sld & sld. */ 3194fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3195fcf5ef2aSThomas Huth { 3196fcf5ef2aSThomas Huth TCGv t0, t1; 3197fcf5ef2aSThomas Huth 3198fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3199fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3200fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3201fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3202fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3203fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3204fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3205fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3206fcf5ef2aSThomas Huth tcg_temp_free(t1); 3207fcf5ef2aSThomas Huth tcg_temp_free(t0); 3208efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3209fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3210fcf5ef2aSThomas Huth } 3211efe843d8SDavid Gibson } 3212fcf5ef2aSThomas Huth 3213fcf5ef2aSThomas Huth /* srad & srad. */ 3214fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3215fcf5ef2aSThomas Huth { 3216fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3217fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3218efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3219fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3220fcf5ef2aSThomas Huth } 3221efe843d8SDavid Gibson } 3222fcf5ef2aSThomas Huth /* sradi & sradi. */ 3223fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3224fcf5ef2aSThomas Huth { 3225fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3226fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3227fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3228fcf5ef2aSThomas Huth if (sh == 0) { 3229fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3230fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3231af1c259fSSandipan Das if (is_isa300(ctx)) { 3232af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3233af1c259fSSandipan Das } 3234fcf5ef2aSThomas Huth } else { 3235fcf5ef2aSThomas Huth TCGv t0; 3236fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3237fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3238fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3239fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3240fcf5ef2aSThomas Huth tcg_temp_free(t0); 3241fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3242af1c259fSSandipan Das if (is_isa300(ctx)) { 3243af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3244af1c259fSSandipan Das } 3245fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3246fcf5ef2aSThomas Huth } 3247fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3248fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3249fcf5ef2aSThomas Huth } 3250fcf5ef2aSThomas Huth } 3251fcf5ef2aSThomas Huth 3252fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3253fcf5ef2aSThomas Huth { 3254fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3255fcf5ef2aSThomas Huth } 3256fcf5ef2aSThomas Huth 3257fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3258fcf5ef2aSThomas Huth { 3259fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3260fcf5ef2aSThomas Huth } 3261fcf5ef2aSThomas Huth 3262fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3263fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3264fcf5ef2aSThomas Huth { 3265fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3266fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3267fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3268fcf5ef2aSThomas Huth 3269fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3270fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3271fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3272fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3273fcf5ef2aSThomas Huth } 3274fcf5ef2aSThomas Huth } 3275fcf5ef2aSThomas Huth 3276fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3277fcf5ef2aSThomas Huth { 3278fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3279fcf5ef2aSThomas Huth } 3280fcf5ef2aSThomas Huth 3281fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3282fcf5ef2aSThomas Huth { 3283fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3284fcf5ef2aSThomas Huth } 3285fcf5ef2aSThomas Huth 3286fcf5ef2aSThomas Huth /* srd & srd. */ 3287fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3288fcf5ef2aSThomas Huth { 3289fcf5ef2aSThomas Huth TCGv t0, t1; 3290fcf5ef2aSThomas Huth 3291fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3292fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3293fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3294fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3295fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3296fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3297fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3298fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3299fcf5ef2aSThomas Huth tcg_temp_free(t1); 3300fcf5ef2aSThomas Huth tcg_temp_free(t0); 3301efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3302fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3303fcf5ef2aSThomas Huth } 3304efe843d8SDavid Gibson } 3305fcf5ef2aSThomas Huth #endif 3306fcf5ef2aSThomas Huth 3307fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3308fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3309fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3310fcf5ef2aSThomas Huth target_long maskl) 3311fcf5ef2aSThomas Huth { 3312fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3313fcf5ef2aSThomas Huth 3314fcf5ef2aSThomas Huth simm &= ~maskl; 3315fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3316fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3317fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3318fcf5ef2aSThomas Huth } 3319fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3320fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3321fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3322fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3323fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3324fcf5ef2aSThomas Huth } 3325fcf5ef2aSThomas Huth } else { 3326fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3327fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3328fcf5ef2aSThomas Huth } else { 3329fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3330fcf5ef2aSThomas Huth } 3331fcf5ef2aSThomas Huth } 3332fcf5ef2aSThomas Huth } 3333fcf5ef2aSThomas Huth 3334fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3335fcf5ef2aSThomas Huth { 3336fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3337fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3338fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3339fcf5ef2aSThomas Huth } else { 3340fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3341fcf5ef2aSThomas Huth } 3342fcf5ef2aSThomas Huth } else { 3343fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3344fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3345fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3346fcf5ef2aSThomas Huth } 3347fcf5ef2aSThomas Huth } 3348fcf5ef2aSThomas Huth } 3349fcf5ef2aSThomas Huth 3350fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3351fcf5ef2aSThomas Huth { 3352fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3353fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3354fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3355fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3356fcf5ef2aSThomas Huth } else { 3357fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3358fcf5ef2aSThomas Huth } 3359fcf5ef2aSThomas Huth } 3360fcf5ef2aSThomas Huth 3361fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3362fcf5ef2aSThomas Huth target_long val) 3363fcf5ef2aSThomas Huth { 3364fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3365fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3366fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3367fcf5ef2aSThomas Huth } 3368fcf5ef2aSThomas Huth } 3369fcf5ef2aSThomas Huth 3370fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3371fcf5ef2aSThomas Huth { 3372fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3373fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3374fcf5ef2aSThomas Huth } 3375fcf5ef2aSThomas Huth 3376fcf5ef2aSThomas Huth /*** Integer load ***/ 3377fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3378fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3379fcf5ef2aSThomas Huth 3380fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3381fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3382fcf5ef2aSThomas Huth TCGv val, \ 3383fcf5ef2aSThomas Huth TCGv addr) \ 3384fcf5ef2aSThomas Huth { \ 3385fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3386fcf5ef2aSThomas Huth } 3387fcf5ef2aSThomas Huth 3388fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3389fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3390fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3391fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3392fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3393fcf5ef2aSThomas Huth 3394fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3395fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3396fcf5ef2aSThomas Huth 3397fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3398fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3399fcf5ef2aSThomas Huth TCGv_i64 val, \ 3400fcf5ef2aSThomas Huth TCGv addr) \ 3401fcf5ef2aSThomas Huth { \ 3402fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3403fcf5ef2aSThomas Huth } 3404fcf5ef2aSThomas Huth 3405fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3406fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3407fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3408fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3409fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3410fcf5ef2aSThomas Huth 3411fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3412fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3413fcf5ef2aSThomas Huth #endif 3414fcf5ef2aSThomas Huth 3415fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3416fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3417fcf5ef2aSThomas Huth TCGv val, \ 3418fcf5ef2aSThomas Huth TCGv addr) \ 3419fcf5ef2aSThomas Huth { \ 3420fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3421fcf5ef2aSThomas Huth } 3422fcf5ef2aSThomas Huth 3423fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3424fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3425fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3426fcf5ef2aSThomas Huth 3427fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3428fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3429fcf5ef2aSThomas Huth 3430fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3431fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3432fcf5ef2aSThomas Huth TCGv_i64 val, \ 3433fcf5ef2aSThomas Huth TCGv addr) \ 3434fcf5ef2aSThomas Huth { \ 3435fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3436fcf5ef2aSThomas Huth } 3437fcf5ef2aSThomas Huth 3438fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3439fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3440fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3441fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3442fcf5ef2aSThomas Huth 3443fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3444fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3445fcf5ef2aSThomas Huth #endif 3446fcf5ef2aSThomas Huth 3447fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 3448fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3449fcf5ef2aSThomas Huth { \ 3450fcf5ef2aSThomas Huth TCGv EA; \ 3451fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3452fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3453fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3454fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3455fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3456fcf5ef2aSThomas Huth } 3457fcf5ef2aSThomas Huth 3458fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 3459fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 3460fcf5ef2aSThomas Huth { \ 3461fcf5ef2aSThomas Huth TCGv EA; \ 3462fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3463fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3464fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3465fcf5ef2aSThomas Huth return; \ 3466fcf5ef2aSThomas Huth } \ 3467fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3468fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3469fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3470fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3471fcf5ef2aSThomas Huth else \ 3472fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3473fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3474fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3475fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3476fcf5ef2aSThomas Huth } 3477fcf5ef2aSThomas Huth 3478fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 3479fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3480fcf5ef2aSThomas Huth { \ 3481fcf5ef2aSThomas Huth TCGv EA; \ 3482fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3483fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3484fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3485fcf5ef2aSThomas Huth return; \ 3486fcf5ef2aSThomas Huth } \ 3487fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3488fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3489fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3490fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3491fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3492fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3493fcf5ef2aSThomas Huth } 3494fcf5ef2aSThomas Huth 3495fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3496fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3497fcf5ef2aSThomas Huth { \ 3498fcf5ef2aSThomas Huth TCGv EA; \ 3499fcf5ef2aSThomas Huth chk; \ 3500fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3501fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3502fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3503fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3504fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3505fcf5ef2aSThomas Huth } 3506fcf5ef2aSThomas Huth 3507fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3508fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3509fcf5ef2aSThomas Huth 3510fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3511fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3512fcf5ef2aSThomas Huth 3513fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 3514fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 3515fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 3516fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 3517fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 3518fcf5ef2aSThomas Huth 3519fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 3520fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 3521fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 3522fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 3523fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 3524fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 3525fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 3526fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 352750728199SRoman Kapl 352850728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 352950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 353050728199SRoman Kapl { \ 353150728199SRoman Kapl TCGv EA; \ 353250728199SRoman Kapl CHK_SV; \ 353350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 353450728199SRoman Kapl EA = tcg_temp_new(); \ 353550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 353650728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 353750728199SRoman Kapl tcg_temp_free(EA); \ 353850728199SRoman Kapl } 353950728199SRoman Kapl 354050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 354150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 354250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 354350728199SRoman Kapl #if defined(TARGET_PPC64) 354450728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 354550728199SRoman Kapl #endif 354650728199SRoman Kapl 3547fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3548fcf5ef2aSThomas Huth /* lwaux */ 3549fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 3550fcf5ef2aSThomas Huth /* lwax */ 3551fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 3552fcf5ef2aSThomas Huth /* ldux */ 3553fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 3554fcf5ef2aSThomas Huth /* ldx */ 3555fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 3556fcf5ef2aSThomas Huth 3557fcf5ef2aSThomas Huth /* CI load/store variants */ 3558fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3559fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3560fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3561fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3562fcf5ef2aSThomas Huth 3563fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 3564fcf5ef2aSThomas Huth { 3565fcf5ef2aSThomas Huth TCGv EA; 3566fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3567fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 3568fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 3569fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3570fcf5ef2aSThomas Huth return; 3571fcf5ef2aSThomas Huth } 3572fcf5ef2aSThomas Huth } 3573fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3574fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3575fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3576fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 3577fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 3578fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3579fcf5ef2aSThomas Huth } else { 3580fcf5ef2aSThomas Huth /* ld - ldu */ 3581fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3582fcf5ef2aSThomas Huth } 3583efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3584fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3585efe843d8SDavid Gibson } 3586fcf5ef2aSThomas Huth tcg_temp_free(EA); 3587fcf5ef2aSThomas Huth } 3588fcf5ef2aSThomas Huth 3589fcf5ef2aSThomas Huth /* lq */ 3590fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3591fcf5ef2aSThomas Huth { 3592fcf5ef2aSThomas Huth int ra, rd; 359394bf2658SRichard Henderson TCGv EA, hi, lo; 3594fcf5ef2aSThomas Huth 3595fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3596fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3597fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3598fcf5ef2aSThomas Huth 3599fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3600fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3601fcf5ef2aSThomas Huth return; 3602fcf5ef2aSThomas Huth } 3603fcf5ef2aSThomas Huth 3604fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3605fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3606fcf5ef2aSThomas Huth return; 3607fcf5ef2aSThomas Huth } 3608fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3609fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3610fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3611fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3612fcf5ef2aSThomas Huth return; 3613fcf5ef2aSThomas Huth } 3614fcf5ef2aSThomas Huth 3615fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3616fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3617fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3618fcf5ef2aSThomas Huth 361994bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 362094bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 362194bf2658SRichard Henderson hi = cpu_gpr[rd]; 362294bf2658SRichard Henderson 362394bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3624f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 362594bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 362694bf2658SRichard Henderson if (ctx->le_mode) { 362794bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 362894bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3629fcf5ef2aSThomas Huth } else { 363094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 363194bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 363294bf2658SRichard Henderson } 363394bf2658SRichard Henderson tcg_temp_free_i32(oi); 363494bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3635f34ec0f6SRichard Henderson } else { 363694bf2658SRichard Henderson /* Restart with exclusive lock. */ 363794bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 363894bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3639f34ec0f6SRichard Henderson } 364094bf2658SRichard Henderson } else if (ctx->le_mode) { 364194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3642fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 364394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 364494bf2658SRichard Henderson } else { 364594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 364694bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 364794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3648fcf5ef2aSThomas Huth } 3649fcf5ef2aSThomas Huth tcg_temp_free(EA); 3650fcf5ef2aSThomas Huth } 3651fcf5ef2aSThomas Huth #endif 3652fcf5ef2aSThomas Huth 3653fcf5ef2aSThomas Huth /*** Integer store ***/ 3654fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3655fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3656fcf5ef2aSThomas Huth { \ 3657fcf5ef2aSThomas Huth TCGv EA; \ 3658fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3659fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3660fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3661fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3662fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3663fcf5ef2aSThomas Huth } 3664fcf5ef2aSThomas Huth 3665fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3666fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3667fcf5ef2aSThomas Huth { \ 3668fcf5ef2aSThomas Huth TCGv EA; \ 3669fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3670fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3671fcf5ef2aSThomas Huth return; \ 3672fcf5ef2aSThomas Huth } \ 3673fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3674fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3675fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3676fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3677fcf5ef2aSThomas Huth else \ 3678fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3679fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3680fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3681fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3682fcf5ef2aSThomas Huth } 3683fcf5ef2aSThomas Huth 3684fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3685fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3686fcf5ef2aSThomas Huth { \ 3687fcf5ef2aSThomas Huth TCGv EA; \ 3688fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3689fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3690fcf5ef2aSThomas Huth return; \ 3691fcf5ef2aSThomas Huth } \ 3692fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3693fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3694fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3695fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3696fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3697fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3698fcf5ef2aSThomas Huth } 3699fcf5ef2aSThomas Huth 3700fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3701fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3702fcf5ef2aSThomas Huth { \ 3703fcf5ef2aSThomas Huth TCGv EA; \ 3704fcf5ef2aSThomas Huth chk; \ 3705fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3706fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3707fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3708fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3709fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3710fcf5ef2aSThomas Huth } 3711fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3712fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3713fcf5ef2aSThomas Huth 3714fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3715fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3716fcf5ef2aSThomas Huth 3717fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3718fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3719fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3720fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3721fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3722fcf5ef2aSThomas Huth 3723fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3724fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3725fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3726fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3727fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3728fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 372950728199SRoman Kapl 373050728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 373150728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 373250728199SRoman Kapl { \ 373350728199SRoman Kapl TCGv EA; \ 373450728199SRoman Kapl CHK_SV; \ 373550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 373650728199SRoman Kapl EA = tcg_temp_new(); \ 373750728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 373850728199SRoman Kapl tcg_gen_qemu_st_tl( \ 373950728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 374050728199SRoman Kapl tcg_temp_free(EA); \ 374150728199SRoman Kapl } 374250728199SRoman Kapl 374350728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 374450728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 374550728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 374650728199SRoman Kapl #if defined(TARGET_PPC64) 374750728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 374850728199SRoman Kapl #endif 374950728199SRoman Kapl 3750fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3751fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3752fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3753fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3754fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3755fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3756fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3757fcf5ef2aSThomas Huth 3758fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3759fcf5ef2aSThomas Huth { 3760fcf5ef2aSThomas Huth int rs; 3761fcf5ef2aSThomas Huth TCGv EA; 3762fcf5ef2aSThomas Huth 3763fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3764fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3765fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3766fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3767f89ced5fSRichard Henderson TCGv hi, lo; 3768fcf5ef2aSThomas Huth 3769fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3770fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3771fcf5ef2aSThomas Huth } 3772fcf5ef2aSThomas Huth 3773fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3774fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3775fcf5ef2aSThomas Huth return; 3776fcf5ef2aSThomas Huth } 3777fcf5ef2aSThomas Huth 3778fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3779fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3780fcf5ef2aSThomas Huth return; 3781fcf5ef2aSThomas Huth } 3782fcf5ef2aSThomas Huth 3783fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3784fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3785fcf5ef2aSThomas Huth return; 3786fcf5ef2aSThomas Huth } 3787fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3788fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3789fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3790fcf5ef2aSThomas Huth 3791f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3792f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3793f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3794f89ced5fSRichard Henderson 3795f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3796f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3797f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3798f89ced5fSRichard Henderson if (ctx->le_mode) { 3799f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3800f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3801fcf5ef2aSThomas Huth } else { 3802f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3803f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3804f89ced5fSRichard Henderson } 3805f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3806f34ec0f6SRichard Henderson } else { 3807f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3808f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3809f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3810f34ec0f6SRichard Henderson } 3811f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3812f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3813fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3814f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3815f89ced5fSRichard Henderson } else { 3816f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3817f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3818f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3819fcf5ef2aSThomas Huth } 3820fcf5ef2aSThomas Huth tcg_temp_free(EA); 3821fcf5ef2aSThomas Huth } else { 3822fcf5ef2aSThomas Huth /* std / stdu */ 3823fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3824fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3825fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3826fcf5ef2aSThomas Huth return; 3827fcf5ef2aSThomas Huth } 3828fcf5ef2aSThomas Huth } 3829fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3830fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3831fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3832fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3833efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3834fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3835efe843d8SDavid Gibson } 3836fcf5ef2aSThomas Huth tcg_temp_free(EA); 3837fcf5ef2aSThomas Huth } 3838fcf5ef2aSThomas Huth } 3839fcf5ef2aSThomas Huth #endif 3840fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3841fcf5ef2aSThomas Huth 3842fcf5ef2aSThomas Huth /* lhbrx */ 3843fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3844fcf5ef2aSThomas Huth 3845fcf5ef2aSThomas Huth /* lwbrx */ 3846fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3847fcf5ef2aSThomas Huth 3848fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3849fcf5ef2aSThomas Huth /* ldbrx */ 3850fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3851fcf5ef2aSThomas Huth /* stdbrx */ 3852fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3853fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3854fcf5ef2aSThomas Huth 3855fcf5ef2aSThomas Huth /* sthbrx */ 3856fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3857fcf5ef2aSThomas Huth /* stwbrx */ 3858fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3859fcf5ef2aSThomas Huth 3860fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3861fcf5ef2aSThomas Huth 3862fcf5ef2aSThomas Huth /* lmw */ 3863fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3864fcf5ef2aSThomas Huth { 3865fcf5ef2aSThomas Huth TCGv t0; 3866fcf5ef2aSThomas Huth TCGv_i32 t1; 3867fcf5ef2aSThomas Huth 3868fcf5ef2aSThomas Huth if (ctx->le_mode) { 3869fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3870fcf5ef2aSThomas Huth return; 3871fcf5ef2aSThomas Huth } 3872fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3873fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3874fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3875fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3876fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3877fcf5ef2aSThomas Huth tcg_temp_free(t0); 3878fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3879fcf5ef2aSThomas Huth } 3880fcf5ef2aSThomas Huth 3881fcf5ef2aSThomas Huth /* stmw */ 3882fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3883fcf5ef2aSThomas Huth { 3884fcf5ef2aSThomas Huth TCGv t0; 3885fcf5ef2aSThomas Huth TCGv_i32 t1; 3886fcf5ef2aSThomas Huth 3887fcf5ef2aSThomas Huth if (ctx->le_mode) { 3888fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3889fcf5ef2aSThomas Huth return; 3890fcf5ef2aSThomas Huth } 3891fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3892fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3893fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3894fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3895fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3896fcf5ef2aSThomas Huth tcg_temp_free(t0); 3897fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3898fcf5ef2aSThomas Huth } 3899fcf5ef2aSThomas Huth 3900fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3901fcf5ef2aSThomas Huth 3902fcf5ef2aSThomas Huth /* lswi */ 3903efe843d8SDavid Gibson /* 3904efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3905efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3906efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3907efe843d8SDavid Gibson * spec... 3908fcf5ef2aSThomas Huth */ 3909fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3910fcf5ef2aSThomas Huth { 3911fcf5ef2aSThomas Huth TCGv t0; 3912fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3913fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3914fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3915fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3916fcf5ef2aSThomas Huth int nr; 3917fcf5ef2aSThomas Huth 3918fcf5ef2aSThomas Huth if (ctx->le_mode) { 3919fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3920fcf5ef2aSThomas Huth return; 3921fcf5ef2aSThomas Huth } 3922efe843d8SDavid Gibson if (nb == 0) { 3923fcf5ef2aSThomas Huth nb = 32; 3924efe843d8SDavid Gibson } 3925f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3926fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3927fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3928fcf5ef2aSThomas Huth return; 3929fcf5ef2aSThomas Huth } 3930fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3931fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3932fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3933fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3934fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3935fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3936fcf5ef2aSThomas Huth tcg_temp_free(t0); 3937fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3938fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3939fcf5ef2aSThomas Huth } 3940fcf5ef2aSThomas Huth 3941fcf5ef2aSThomas Huth /* lswx */ 3942fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3943fcf5ef2aSThomas Huth { 3944fcf5ef2aSThomas Huth TCGv t0; 3945fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3946fcf5ef2aSThomas Huth 3947fcf5ef2aSThomas Huth if (ctx->le_mode) { 3948fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3949fcf5ef2aSThomas Huth return; 3950fcf5ef2aSThomas Huth } 3951fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3952fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3953fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3954fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3955fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3956fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3957fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3958fcf5ef2aSThomas Huth tcg_temp_free(t0); 3959fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3960fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3961fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3962fcf5ef2aSThomas Huth } 3963fcf5ef2aSThomas Huth 3964fcf5ef2aSThomas Huth /* stswi */ 3965fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3966fcf5ef2aSThomas Huth { 3967fcf5ef2aSThomas Huth TCGv t0; 3968fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3969fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3970fcf5ef2aSThomas Huth 3971fcf5ef2aSThomas Huth if (ctx->le_mode) { 3972fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3973fcf5ef2aSThomas Huth return; 3974fcf5ef2aSThomas Huth } 3975fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3976fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3977fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3978efe843d8SDavid Gibson if (nb == 0) { 3979fcf5ef2aSThomas Huth nb = 32; 3980efe843d8SDavid Gibson } 3981fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3982fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3983fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3984fcf5ef2aSThomas Huth tcg_temp_free(t0); 3985fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3986fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3987fcf5ef2aSThomas Huth } 3988fcf5ef2aSThomas Huth 3989fcf5ef2aSThomas Huth /* stswx */ 3990fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3991fcf5ef2aSThomas Huth { 3992fcf5ef2aSThomas Huth TCGv t0; 3993fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3994fcf5ef2aSThomas Huth 3995fcf5ef2aSThomas Huth if (ctx->le_mode) { 3996fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3997fcf5ef2aSThomas Huth return; 3998fcf5ef2aSThomas Huth } 3999fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4000fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4001fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4002fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4003fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 4004fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 4005fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4006fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4007fcf5ef2aSThomas Huth tcg_temp_free(t0); 4008fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4009fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4010fcf5ef2aSThomas Huth } 4011fcf5ef2aSThomas Huth 4012fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 4013fcf5ef2aSThomas Huth /* eieio */ 4014fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 4015fcf5ef2aSThomas Huth { 4016c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 4017c8fd8373SCédric Le Goater 4018c8fd8373SCédric Le Goater /* 4019c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 4020c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 4021c8fd8373SCédric Le Goater */ 4022c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 4023c8fd8373SCédric Le Goater /* 4024c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 4025c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 4026c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 4027c8fd8373SCédric Le Goater * complain to the user. 4028c8fd8373SCédric Le Goater */ 4029c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 4030c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 40312c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 4032c8fd8373SCédric Le Goater } else { 4033c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 4034c8fd8373SCédric Le Goater } 4035c8fd8373SCédric Le Goater } 4036c8fd8373SCédric Le Goater 4037c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 4038fcf5ef2aSThomas Huth } 4039fcf5ef2aSThomas Huth 4040fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4041fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 4042fcf5ef2aSThomas Huth { 4043fcf5ef2aSThomas Huth TCGv_i32 t; 4044fcf5ef2aSThomas Huth TCGLabel *l; 4045fcf5ef2aSThomas Huth 4046fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 4047fcf5ef2aSThomas Huth return; 4048fcf5ef2aSThomas Huth } 4049fcf5ef2aSThomas Huth l = gen_new_label(); 4050fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 4051fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4052fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 4053fcf5ef2aSThomas Huth if (global) { 4054fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 4055fcf5ef2aSThomas Huth } else { 4056fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 4057fcf5ef2aSThomas Huth } 4058fcf5ef2aSThomas Huth gen_set_label(l); 4059fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4060fcf5ef2aSThomas Huth } 4061fcf5ef2aSThomas Huth #else 4062fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 4063fcf5ef2aSThomas Huth #endif 4064fcf5ef2aSThomas Huth 4065fcf5ef2aSThomas Huth /* isync */ 4066fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 4067fcf5ef2aSThomas Huth { 4068fcf5ef2aSThomas Huth /* 4069fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 4070fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 4071fcf5ef2aSThomas Huth */ 4072fcf5ef2aSThomas Huth if (!ctx->pr) { 4073fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 4074fcf5ef2aSThomas Huth } 40754771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4076*d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4077fcf5ef2aSThomas Huth } 4078fcf5ef2aSThomas Huth 4079fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 4080fcf5ef2aSThomas Huth 408114776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 40822a4e6c1bSRichard Henderson { 40832a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 40842a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 40852a4e6c1bSRichard Henderson 40862a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 40872a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 40882a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 40892a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 40902a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 40912a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 40922a4e6c1bSRichard Henderson tcg_temp_free(t0); 40932a4e6c1bSRichard Henderson } 40942a4e6c1bSRichard Henderson 4095fcf5ef2aSThomas Huth #define LARX(name, memop) \ 4096fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4097fcf5ef2aSThomas Huth { \ 40982a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 4099fcf5ef2aSThomas Huth } 4100fcf5ef2aSThomas Huth 4101fcf5ef2aSThomas Huth /* lwarx */ 4102fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 4103fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 4104fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 4105fcf5ef2aSThomas Huth 410614776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 410720923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 410820923c1dSRichard Henderson { 410920923c1dSRichard Henderson TCGv t = tcg_temp_new(); 411020923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 411120923c1dSRichard Henderson TCGv u = tcg_temp_new(); 411220923c1dSRichard Henderson 411320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 411420923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 411520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 411620923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 411720923c1dSRichard Henderson 411820923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 411920923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 412020923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 412120923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 412220923c1dSRichard Henderson 412320923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 412420923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 412520923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 412620923c1dSRichard Henderson 412720923c1dSRichard Henderson tcg_temp_free(t); 412820923c1dSRichard Henderson tcg_temp_free(t2); 412920923c1dSRichard Henderson tcg_temp_free(u); 413020923c1dSRichard Henderson } 413120923c1dSRichard Henderson 413214776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 413320ba8504SRichard Henderson { 413420ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 413520ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 413620923c1dSRichard Henderson int rt = rD(ctx->opcode); 413720923c1dSRichard Henderson bool need_serial; 413820ba8504SRichard Henderson TCGv src, dst; 413920ba8504SRichard Henderson 414020ba8504SRichard Henderson gen_addr_register(ctx, EA); 414120923c1dSRichard Henderson dst = cpu_gpr[rt]; 414220923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 414320ba8504SRichard Henderson 414420923c1dSRichard Henderson need_serial = false; 414520ba8504SRichard Henderson memop |= MO_ALIGN; 414620ba8504SRichard Henderson switch (gpr_FC) { 414720ba8504SRichard Henderson case 0: /* Fetch and add */ 414820ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 414920ba8504SRichard Henderson break; 415020ba8504SRichard Henderson case 1: /* Fetch and xor */ 415120ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 415220ba8504SRichard Henderson break; 415320ba8504SRichard Henderson case 2: /* Fetch and or */ 415420ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 415520ba8504SRichard Henderson break; 415620ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 415720ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 415820ba8504SRichard Henderson break; 4159b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 4160b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 4161b8ce0f86SRichard Henderson break; 4162b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 4163b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 4164b8ce0f86SRichard Henderson break; 4165b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 4166b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 4167b8ce0f86SRichard Henderson break; 4168b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 4169b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 4170b8ce0f86SRichard Henderson break; 417120ba8504SRichard Henderson case 8: /* Swap */ 417220ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 417320ba8504SRichard Henderson break; 417420923c1dSRichard Henderson 417520923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 417620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 417720923c1dSRichard Henderson need_serial = true; 417820923c1dSRichard Henderson } else { 417920923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 418020923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 418120923c1dSRichard Henderson 418220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 418320923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 418420923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 418520923c1dSRichard Henderson } else { 418620923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 418720923c1dSRichard Henderson } 418820923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 418920923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 419020923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 419120923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 419220923c1dSRichard Henderson 419320923c1dSRichard Henderson tcg_temp_free(t0); 419420923c1dSRichard Henderson tcg_temp_free(t1); 419520923c1dSRichard Henderson } 419620ba8504SRichard Henderson break; 419720923c1dSRichard Henderson 419820923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 419920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 420020923c1dSRichard Henderson need_serial = true; 420120923c1dSRichard Henderson } else { 420220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 420320923c1dSRichard Henderson } 420420923c1dSRichard Henderson break; 420520923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 420620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 420720923c1dSRichard Henderson need_serial = true; 420820923c1dSRichard Henderson } else { 420920923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 421020923c1dSRichard Henderson } 421120923c1dSRichard Henderson break; 421220923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 421320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 421420923c1dSRichard Henderson need_serial = true; 421520923c1dSRichard Henderson } else { 421620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 421720923c1dSRichard Henderson } 421820923c1dSRichard Henderson break; 421920923c1dSRichard Henderson 422020ba8504SRichard Henderson default: 422120ba8504SRichard Henderson /* invoke data storage error handler */ 422220ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 422320ba8504SRichard Henderson } 422420ba8504SRichard Henderson tcg_temp_free(EA); 422520923c1dSRichard Henderson 422620923c1dSRichard Henderson if (need_serial) { 422720923c1dSRichard Henderson /* Restart with exclusive lock. */ 422820923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 422920923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 423020923c1dSRichard Henderson } 4231a68a6146SBalamuruhan S } 4232a68a6146SBalamuruhan S 423320ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 423420ba8504SRichard Henderson { 423520ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 423620ba8504SRichard Henderson } 423720ba8504SRichard Henderson 423820ba8504SRichard Henderson #ifdef TARGET_PPC64 423920ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 424020ba8504SRichard Henderson { 424120ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 424220ba8504SRichard Henderson } 4243a68a6146SBalamuruhan S #endif 4244a68a6146SBalamuruhan S 424514776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 42469deb041cSRichard Henderson { 42479deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 42489deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 42499deb041cSRichard Henderson TCGv src, discard; 42509deb041cSRichard Henderson 42519deb041cSRichard Henderson gen_addr_register(ctx, EA); 42529deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 42539deb041cSRichard Henderson discard = tcg_temp_new(); 42549deb041cSRichard Henderson 42559deb041cSRichard Henderson memop |= MO_ALIGN; 42569deb041cSRichard Henderson switch (gpr_FC) { 42579deb041cSRichard Henderson case 0: /* add and Store */ 42589deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 42599deb041cSRichard Henderson break; 42609deb041cSRichard Henderson case 1: /* xor and Store */ 42619deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 42629deb041cSRichard Henderson break; 42639deb041cSRichard Henderson case 2: /* Or and Store */ 42649deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 42659deb041cSRichard Henderson break; 42669deb041cSRichard Henderson case 3: /* 'and' and Store */ 42679deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 42689deb041cSRichard Henderson break; 42699deb041cSRichard Henderson case 4: /* Store max unsigned */ 4270b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4271b8ce0f86SRichard Henderson break; 42729deb041cSRichard Henderson case 5: /* Store max signed */ 4273b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4274b8ce0f86SRichard Henderson break; 42759deb041cSRichard Henderson case 6: /* Store min unsigned */ 4276b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4277b8ce0f86SRichard Henderson break; 42789deb041cSRichard Henderson case 7: /* Store min signed */ 4279b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4280b8ce0f86SRichard Henderson break; 42819deb041cSRichard Henderson case 24: /* Store twin */ 42827fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 42837fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 42847fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 42857fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 42867fbc2b20SRichard Henderson } else { 42877fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 42887fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 42897fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 42907fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 42917fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 42927fbc2b20SRichard Henderson 42937fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 42947fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 42957fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 42967fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 42977fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 42987fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 42997fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 43007fbc2b20SRichard Henderson 43017fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 43027fbc2b20SRichard Henderson tcg_temp_free(s2); 43037fbc2b20SRichard Henderson tcg_temp_free(s); 43047fbc2b20SRichard Henderson tcg_temp_free(t2); 43057fbc2b20SRichard Henderson tcg_temp_free(t); 43067fbc2b20SRichard Henderson } 43079deb041cSRichard Henderson break; 43089deb041cSRichard Henderson default: 43099deb041cSRichard Henderson /* invoke data storage error handler */ 43109deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 43119deb041cSRichard Henderson } 43129deb041cSRichard Henderson tcg_temp_free(discard); 43139deb041cSRichard Henderson tcg_temp_free(EA); 4314a3401188SBalamuruhan S } 4315a3401188SBalamuruhan S 43169deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 43179deb041cSRichard Henderson { 43189deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 43199deb041cSRichard Henderson } 43209deb041cSRichard Henderson 43219deb041cSRichard Henderson #ifdef TARGET_PPC64 43229deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 43239deb041cSRichard Henderson { 43249deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 43259deb041cSRichard Henderson } 4326a3401188SBalamuruhan S #endif 4327a3401188SBalamuruhan S 432814776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4329fcf5ef2aSThomas Huth { 4330253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4331253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4332d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4333d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4334fcf5ef2aSThomas Huth 4335d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4336d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4337d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4338d8b86898SRichard Henderson tcg_temp_free(t0); 4339253ce7b2SNikunj A Dadhania 4340253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4341253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4342253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4343253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4344253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4345253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4346253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4347253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4348253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4349253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4350253ce7b2SNikunj A Dadhania 4351fcf5ef2aSThomas Huth gen_set_label(l1); 43524771df23SNikunj A Dadhania 4353efe843d8SDavid Gibson /* 4354efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4355efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4356efe843d8SDavid Gibson */ 43574771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4358253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4359253ce7b2SNikunj A Dadhania 4360253ce7b2SNikunj A Dadhania gen_set_label(l2); 4361fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4362fcf5ef2aSThomas Huth } 4363fcf5ef2aSThomas Huth 4364fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4365fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4366fcf5ef2aSThomas Huth { \ 4367d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4368fcf5ef2aSThomas Huth } 4369fcf5ef2aSThomas Huth 4370fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4371fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4372fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4373fcf5ef2aSThomas Huth 4374fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4375fcf5ef2aSThomas Huth /* ldarx */ 4376fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4377fcf5ef2aSThomas Huth /* stdcx. */ 4378fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4379fcf5ef2aSThomas Huth 4380fcf5ef2aSThomas Huth /* lqarx */ 4381fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4382fcf5ef2aSThomas Huth { 4383fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 438494bf2658SRichard Henderson TCGv EA, hi, lo; 4385fcf5ef2aSThomas Huth 4386fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4387fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4388fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4389fcf5ef2aSThomas Huth return; 4390fcf5ef2aSThomas Huth } 4391fcf5ef2aSThomas Huth 4392fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 439394bf2658SRichard Henderson EA = tcg_temp_new(); 4394fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 439594bf2658SRichard Henderson 439694bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 439794bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 439894bf2658SRichard Henderson hi = cpu_gpr[rd]; 439994bf2658SRichard Henderson 440094bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4401f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 440294bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 440394bf2658SRichard Henderson if (ctx->le_mode) { 440494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 440594bf2658SRichard Henderson ctx->mem_idx)); 440694bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4407fcf5ef2aSThomas Huth } else { 440894bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 440994bf2658SRichard Henderson ctx->mem_idx)); 441094bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4411fcf5ef2aSThomas Huth } 441294bf2658SRichard Henderson tcg_temp_free_i32(oi); 441394bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4414f34ec0f6SRichard Henderson } else { 441594bf2658SRichard Henderson /* Restart with exclusive lock. */ 441694bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 441794bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 441894bf2658SRichard Henderson tcg_temp_free(EA); 441994bf2658SRichard Henderson return; 4420f34ec0f6SRichard Henderson } 442194bf2658SRichard Henderson } else if (ctx->le_mode) { 442294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4423fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4424fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 442594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 442694bf2658SRichard Henderson } else { 442794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 442894bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 442994bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 443094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 443194bf2658SRichard Henderson } 4432fcf5ef2aSThomas Huth tcg_temp_free(EA); 443394bf2658SRichard Henderson 443494bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 443594bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4436fcf5ef2aSThomas Huth } 4437fcf5ef2aSThomas Huth 4438fcf5ef2aSThomas Huth /* stqcx. */ 4439fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4440fcf5ef2aSThomas Huth { 44414a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 44424a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4443fcf5ef2aSThomas Huth 44444a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4445fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4446fcf5ef2aSThomas Huth return; 4447fcf5ef2aSThomas Huth } 44484a9b3c5dSRichard Henderson 4449fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 44504a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4451fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4452fcf5ef2aSThomas Huth 44534a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 44544a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 44554a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4456fcf5ef2aSThomas Huth 44574a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4458f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 44594a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 44604a9b3c5dSRichard Henderson if (ctx->le_mode) { 4461f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4462f34ec0f6SRichard Henderson EA, lo, hi, oi); 4463fcf5ef2aSThomas Huth } else { 4464f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4465f34ec0f6SRichard Henderson EA, lo, hi, oi); 4466fcf5ef2aSThomas Huth } 4467f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4468f34ec0f6SRichard Henderson } else { 44694a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 44704a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 44714a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4472f34ec0f6SRichard Henderson } 4473fcf5ef2aSThomas Huth tcg_temp_free(EA); 44744a9b3c5dSRichard Henderson } else { 44754a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 44764a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 44774a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 44784a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4479fcf5ef2aSThomas Huth 44804a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 44814a9b3c5dSRichard Henderson tcg_temp_free(EA); 44824a9b3c5dSRichard Henderson 44834a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 44844a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 44854a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 44864a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 44874a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 44884a9b3c5dSRichard Henderson 44894a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 44904a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 44914a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 44924a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 44934a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 44944a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 44954a9b3c5dSRichard Henderson 44964a9b3c5dSRichard Henderson /* Success */ 44974a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 44984a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 44994a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 45004a9b3c5dSRichard Henderson 45014a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 45024a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 45034a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 45044a9b3c5dSRichard Henderson 45054a9b3c5dSRichard Henderson gen_set_label(lab_fail); 45064a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 45074a9b3c5dSRichard Henderson 45084a9b3c5dSRichard Henderson gen_set_label(lab_over); 45094a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 45104a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 45114a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 45124a9b3c5dSRichard Henderson } 45134a9b3c5dSRichard Henderson } 4514fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4515fcf5ef2aSThomas Huth 4516fcf5ef2aSThomas Huth /* sync */ 4517fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4518fcf5ef2aSThomas Huth { 4519fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4520fcf5ef2aSThomas Huth 4521fcf5ef2aSThomas Huth /* 4522fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4523fcf5ef2aSThomas Huth * 4524fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4525fcf5ef2aSThomas Huth * 4526fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4527fcf5ef2aSThomas Huth * check MSR_PR as well. 4528fcf5ef2aSThomas Huth */ 4529fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4530fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4531fcf5ef2aSThomas Huth } 45324771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4533fcf5ef2aSThomas Huth } 4534fcf5ef2aSThomas Huth 4535fcf5ef2aSThomas Huth /* wait */ 4536fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4537fcf5ef2aSThomas Huth { 4538fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4539fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4540fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4541fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4542fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4543b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4544fcf5ef2aSThomas Huth } 4545fcf5ef2aSThomas Huth 4546fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4547fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4548fcf5ef2aSThomas Huth { 4549fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4550fcf5ef2aSThomas Huth GEN_PRIV; 4551fcf5ef2aSThomas Huth #else 4552fcf5ef2aSThomas Huth TCGv_i32 t; 4553fcf5ef2aSThomas Huth 4554fcf5ef2aSThomas Huth CHK_HV; 4555fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4556fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4557fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4558154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4559154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4560fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4561fcf5ef2aSThomas Huth } 4562fcf5ef2aSThomas Huth 4563fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4564fcf5ef2aSThomas Huth { 4565fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4566fcf5ef2aSThomas Huth GEN_PRIV; 4567fcf5ef2aSThomas Huth #else 4568fcf5ef2aSThomas Huth TCGv_i32 t; 4569fcf5ef2aSThomas Huth 4570fcf5ef2aSThomas Huth CHK_HV; 4571fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4572fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4573fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4574154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4575154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4576fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4577fcf5ef2aSThomas Huth } 4578fcf5ef2aSThomas Huth 4579cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4580cdee0e72SNikunj A Dadhania { 458121c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 458221c0d66aSBenjamin Herrenschmidt GEN_PRIV; 458321c0d66aSBenjamin Herrenschmidt #else 458421c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 458521c0d66aSBenjamin Herrenschmidt 458621c0d66aSBenjamin Herrenschmidt CHK_HV; 458721c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 458821c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 458921c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 459021c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 459121c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 459221c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4593cdee0e72SNikunj A Dadhania } 4594cdee0e72SNikunj A Dadhania 4595fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4596fcf5ef2aSThomas Huth { 4597fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4598fcf5ef2aSThomas Huth GEN_PRIV; 4599fcf5ef2aSThomas Huth #else 4600fcf5ef2aSThomas Huth TCGv_i32 t; 4601fcf5ef2aSThomas Huth 4602fcf5ef2aSThomas Huth CHK_HV; 4603fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4604fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4605fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4606154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4607154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4608fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4609fcf5ef2aSThomas Huth } 4610fcf5ef2aSThomas Huth 4611fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4612fcf5ef2aSThomas Huth { 4613fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4614fcf5ef2aSThomas Huth GEN_PRIV; 4615fcf5ef2aSThomas Huth #else 4616fcf5ef2aSThomas Huth TCGv_i32 t; 4617fcf5ef2aSThomas Huth 4618fcf5ef2aSThomas Huth CHK_HV; 4619fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4620fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4621fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4622154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4623154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4624fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4625fcf5ef2aSThomas Huth } 4626fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4627fcf5ef2aSThomas Huth 4628fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4629fcf5ef2aSThomas Huth { 4630fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4631efe843d8SDavid Gibson if (ctx->has_cfar) { 4632fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4633efe843d8SDavid Gibson } 4634fcf5ef2aSThomas Huth #endif 4635fcf5ef2aSThomas Huth } 4636fcf5ef2aSThomas Huth 4637fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4638fcf5ef2aSThomas Huth { 4639fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4640fcf5ef2aSThomas Huth return false; 4641fcf5ef2aSThomas Huth } 4642fcf5ef2aSThomas Huth 4643fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4644b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4645fcf5ef2aSThomas Huth #else 4646fcf5ef2aSThomas Huth return true; 4647fcf5ef2aSThomas Huth #endif 4648fcf5ef2aSThomas Huth } 4649fcf5ef2aSThomas Huth 46500e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 46510e3bf489SRoman Kapl { 46520e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 46530e3bf489SRoman Kapl if (unlikely(sse)) { 46540e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 46550e3bf489SRoman Kapl gen_debug_exception(ctx); 46560e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4657e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 46580e3bf489SRoman Kapl gen_exception(ctx, excp); 46590e3bf489SRoman Kapl } 46600e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 46610e3bf489SRoman Kapl } else { 46620e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 46630e3bf489SRoman Kapl } 46640e3bf489SRoman Kapl } 46650e3bf489SRoman Kapl 4666fcf5ef2aSThomas Huth /*** Branch ***/ 4667c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4668fcf5ef2aSThomas Huth { 4669fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4670fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4671fcf5ef2aSThomas Huth } 4672fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4673fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4674fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 467507ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4676fcf5ef2aSThomas Huth } else { 4677fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 46780e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4679fcf5ef2aSThomas Huth } 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth 4682fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4683fcf5ef2aSThomas Huth { 4684fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4685fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4686fcf5ef2aSThomas Huth } 4687fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4688fcf5ef2aSThomas Huth } 4689fcf5ef2aSThomas Huth 4690fcf5ef2aSThomas Huth /* b ba bl bla */ 4691fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4692fcf5ef2aSThomas Huth { 4693fcf5ef2aSThomas Huth target_ulong li, target; 4694fcf5ef2aSThomas Huth 4695fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 4696fcf5ef2aSThomas Huth /* sign extend LI */ 4697fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4698fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4699fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 47002c2bcb1bSRichard Henderson target = ctx->cia + li; 4701fcf5ef2aSThomas Huth } else { 4702fcf5ef2aSThomas Huth target = li; 4703fcf5ef2aSThomas Huth } 4704fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4705b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4706fcf5ef2aSThomas Huth } 47072c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4708fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 4709fcf5ef2aSThomas Huth } 4710fcf5ef2aSThomas Huth 4711fcf5ef2aSThomas Huth #define BCOND_IM 0 4712fcf5ef2aSThomas Huth #define BCOND_LR 1 4713fcf5ef2aSThomas Huth #define BCOND_CTR 2 4714fcf5ef2aSThomas Huth #define BCOND_TAR 3 4715fcf5ef2aSThomas Huth 4716c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4717fcf5ef2aSThomas Huth { 4718fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4719fcf5ef2aSThomas Huth TCGLabel *l1; 4720fcf5ef2aSThomas Huth TCGv target; 4721fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 47220e3bf489SRoman Kapl 4723fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4724fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4725efe843d8SDavid Gibson if (type == BCOND_CTR) { 4726fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4727efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4728fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4729efe843d8SDavid Gibson } else { 4730fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4731efe843d8SDavid Gibson } 4732fcf5ef2aSThomas Huth } else { 4733f764718dSRichard Henderson target = NULL; 4734fcf5ef2aSThomas Huth } 4735efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4736b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4737efe843d8SDavid Gibson } 4738fcf5ef2aSThomas Huth l1 = gen_new_label(); 4739fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4740fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4741fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4742fa200c95SGreg Kurz 4743fa200c95SGreg Kurz if (type == BCOND_CTR) { 4744fa200c95SGreg Kurz /* 4745fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4746fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4747fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 474815d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 474915d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 475015d68c5eSGreg Kurz * it basically useless and thus never used in real code. 475115d68c5eSGreg Kurz * 475215d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 475315d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 475415d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 475515d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 475615d68c5eSGreg Kurz * doing anything else harmful. 4757fa200c95SGreg Kurz */ 4758d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4759fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 47609acc95cdSGreg Kurz tcg_temp_free(temp); 47619acc95cdSGreg Kurz tcg_temp_free(target); 4762fcf5ef2aSThomas Huth return; 4763fcf5ef2aSThomas Huth } 4764fa200c95SGreg Kurz 4765fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4766fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4767fa200c95SGreg Kurz } else { 4768fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4769fa200c95SGreg Kurz } 4770fa200c95SGreg Kurz if (bo & 0x2) { 4771fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4772fa200c95SGreg Kurz } else { 4773fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4774fa200c95SGreg Kurz } 4775fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4776fa200c95SGreg Kurz } else { 4777fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4778fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4779fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4780fcf5ef2aSThomas Huth } else { 4781fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4782fcf5ef2aSThomas Huth } 4783fcf5ef2aSThomas Huth if (bo & 0x2) { 4784fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4785fcf5ef2aSThomas Huth } else { 4786fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4787fcf5ef2aSThomas Huth } 4788fa200c95SGreg Kurz } 4789fcf5ef2aSThomas Huth tcg_temp_free(temp); 4790fcf5ef2aSThomas Huth } 4791fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4792fcf5ef2aSThomas Huth /* Test CR */ 4793fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4794fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4795fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4796fcf5ef2aSThomas Huth 4797fcf5ef2aSThomas Huth if (bo & 0x8) { 4798fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4799fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4800fcf5ef2aSThomas Huth } else { 4801fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4802fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4803fcf5ef2aSThomas Huth } 4804fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4805fcf5ef2aSThomas Huth } 48062c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4807fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4808fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4809fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 48102c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4811fcf5ef2aSThomas Huth } else { 4812fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4813fcf5ef2aSThomas Huth } 4814fcf5ef2aSThomas Huth } else { 4815fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4816fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4817fcf5ef2aSThomas Huth } else { 4818fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4819fcf5ef2aSThomas Huth } 48200e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4821c4a2e3a9SRichard Henderson tcg_temp_free(target); 4822c4a2e3a9SRichard Henderson } 4823fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 48240e3bf489SRoman Kapl /* fallthrough case */ 4825fcf5ef2aSThomas Huth gen_set_label(l1); 4826b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4827fcf5ef2aSThomas Huth } 4828fcf5ef2aSThomas Huth } 4829fcf5ef2aSThomas Huth 4830fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4831fcf5ef2aSThomas Huth { 4832fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4833fcf5ef2aSThomas Huth } 4834fcf5ef2aSThomas Huth 4835fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4836fcf5ef2aSThomas Huth { 4837fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4838fcf5ef2aSThomas Huth } 4839fcf5ef2aSThomas Huth 4840fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4841fcf5ef2aSThomas Huth { 4842fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4843fcf5ef2aSThomas Huth } 4844fcf5ef2aSThomas Huth 4845fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4846fcf5ef2aSThomas Huth { 4847fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4848fcf5ef2aSThomas Huth } 4849fcf5ef2aSThomas Huth 4850fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4851fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4852fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4853fcf5ef2aSThomas Huth { \ 4854fcf5ef2aSThomas Huth uint8_t bitmask; \ 4855fcf5ef2aSThomas Huth int sh; \ 4856fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4857fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4858fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4859fcf5ef2aSThomas Huth if (sh > 0) \ 4860fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4861fcf5ef2aSThomas Huth else if (sh < 0) \ 4862fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4863fcf5ef2aSThomas Huth else \ 4864fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4865fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4866fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4867fcf5ef2aSThomas Huth if (sh > 0) \ 4868fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4869fcf5ef2aSThomas Huth else if (sh < 0) \ 4870fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4871fcf5ef2aSThomas Huth else \ 4872fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4873fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4874fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4875fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4876fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4877fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4878fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4879fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4880fcf5ef2aSThomas Huth } 4881fcf5ef2aSThomas Huth 4882fcf5ef2aSThomas Huth /* crand */ 4883fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4884fcf5ef2aSThomas Huth /* crandc */ 4885fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4886fcf5ef2aSThomas Huth /* creqv */ 4887fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4888fcf5ef2aSThomas Huth /* crnand */ 4889fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4890fcf5ef2aSThomas Huth /* crnor */ 4891fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4892fcf5ef2aSThomas Huth /* cror */ 4893fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4894fcf5ef2aSThomas Huth /* crorc */ 4895fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4896fcf5ef2aSThomas Huth /* crxor */ 4897fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4898fcf5ef2aSThomas Huth 4899fcf5ef2aSThomas Huth /* mcrf */ 4900fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4901fcf5ef2aSThomas Huth { 4902fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4903fcf5ef2aSThomas Huth } 4904fcf5ef2aSThomas Huth 4905fcf5ef2aSThomas Huth /*** System linkage ***/ 4906fcf5ef2aSThomas Huth 4907fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4908fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4909fcf5ef2aSThomas Huth { 4910fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4911fcf5ef2aSThomas Huth GEN_PRIV; 4912fcf5ef2aSThomas Huth #else 4913efe843d8SDavid Gibson /* 4914efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4915fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4916fcf5ef2aSThomas Huth */ 4917d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4918fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4919fcf5ef2aSThomas Huth return; 4920fcf5ef2aSThomas Huth } 4921fcf5ef2aSThomas Huth /* Restore CPU state */ 4922fcf5ef2aSThomas Huth CHK_SV; 4923f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49242c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4925fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 492659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4927fcf5ef2aSThomas Huth #endif 4928fcf5ef2aSThomas Huth } 4929fcf5ef2aSThomas Huth 4930fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4931fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4932fcf5ef2aSThomas Huth { 4933fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4934fcf5ef2aSThomas Huth GEN_PRIV; 4935fcf5ef2aSThomas Huth #else 4936fcf5ef2aSThomas Huth /* Restore CPU state */ 4937fcf5ef2aSThomas Huth CHK_SV; 4938f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49392c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4940fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 494159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4942fcf5ef2aSThomas Huth #endif 4943fcf5ef2aSThomas Huth } 4944fcf5ef2aSThomas Huth 49453c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 49463c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 49473c89b8d6SNicholas Piggin { 49483c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 49493c89b8d6SNicholas Piggin GEN_PRIV; 49503c89b8d6SNicholas Piggin #else 49513c89b8d6SNicholas Piggin /* Restore CPU state */ 49523c89b8d6SNicholas Piggin CHK_SV; 4953f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49542c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 49553c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 495659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 49573c89b8d6SNicholas Piggin #endif 49583c89b8d6SNicholas Piggin } 49593c89b8d6SNicholas Piggin #endif 49603c89b8d6SNicholas Piggin 4961fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4962fcf5ef2aSThomas Huth { 4963fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4964fcf5ef2aSThomas Huth GEN_PRIV; 4965fcf5ef2aSThomas Huth #else 4966fcf5ef2aSThomas Huth /* Restore CPU state */ 4967fcf5ef2aSThomas Huth CHK_HV; 4968fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 496959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4970fcf5ef2aSThomas Huth #endif 4971fcf5ef2aSThomas Huth } 4972fcf5ef2aSThomas Huth #endif 4973fcf5ef2aSThomas Huth 4974fcf5ef2aSThomas Huth /* sc */ 4975fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4976fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4977fcf5ef2aSThomas Huth #else 4978fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 49793c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4980fcf5ef2aSThomas Huth #endif 4981fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4982fcf5ef2aSThomas Huth { 4983fcf5ef2aSThomas Huth uint32_t lev; 4984fcf5ef2aSThomas Huth 4985fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4986fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4987fcf5ef2aSThomas Huth } 4988fcf5ef2aSThomas Huth 49893c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 49903c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 49913c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 49923c89b8d6SNicholas Piggin { 4993f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 49943c89b8d6SNicholas Piggin 4995f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 4996f43520e5SRichard Henderson if (ctx->exception == POWERPC_EXCP_NONE) { 49972c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 49983c89b8d6SNicholas Piggin } 4999f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 50003c89b8d6SNicholas Piggin 5001f43520e5SRichard Henderson /* This need not be exact, just not POWERPC_EXCP_NONE */ 5002f43520e5SRichard Henderson ctx->exception = POWERPC_SYSCALL_VECTORED; 50033c89b8d6SNicholas Piggin } 50043c89b8d6SNicholas Piggin #endif 50053c89b8d6SNicholas Piggin #endif 50063c89b8d6SNicholas Piggin 5007fcf5ef2aSThomas Huth /*** Trap ***/ 5008fcf5ef2aSThomas Huth 5009fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 5010fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 5011fcf5ef2aSThomas Huth { 5012fcf5ef2aSThomas Huth /* Trap never */ 5013fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 5014fcf5ef2aSThomas Huth return true; 5015fcf5ef2aSThomas Huth } 5016fcf5ef2aSThomas Huth /* Trap always */ 5017fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 5018fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 5019fcf5ef2aSThomas Huth return true; 5020fcf5ef2aSThomas Huth } 5021fcf5ef2aSThomas Huth return false; 5022fcf5ef2aSThomas Huth } 5023fcf5ef2aSThomas Huth 5024fcf5ef2aSThomas Huth /* tw */ 5025fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 5026fcf5ef2aSThomas Huth { 5027fcf5ef2aSThomas Huth TCGv_i32 t0; 5028fcf5ef2aSThomas Huth 5029fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5030fcf5ef2aSThomas Huth return; 5031fcf5ef2aSThomas Huth } 5032fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5033fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5034fcf5ef2aSThomas Huth t0); 5035fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5036fcf5ef2aSThomas Huth } 5037fcf5ef2aSThomas Huth 5038fcf5ef2aSThomas Huth /* twi */ 5039fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 5040fcf5ef2aSThomas Huth { 5041fcf5ef2aSThomas Huth TCGv t0; 5042fcf5ef2aSThomas Huth TCGv_i32 t1; 5043fcf5ef2aSThomas Huth 5044fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5045fcf5ef2aSThomas Huth return; 5046fcf5ef2aSThomas Huth } 5047fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5048fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5049fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5050fcf5ef2aSThomas Huth tcg_temp_free(t0); 5051fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5052fcf5ef2aSThomas Huth } 5053fcf5ef2aSThomas Huth 5054fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5055fcf5ef2aSThomas Huth /* td */ 5056fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 5057fcf5ef2aSThomas Huth { 5058fcf5ef2aSThomas Huth TCGv_i32 t0; 5059fcf5ef2aSThomas Huth 5060fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5061fcf5ef2aSThomas Huth return; 5062fcf5ef2aSThomas Huth } 5063fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5064fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5065fcf5ef2aSThomas Huth t0); 5066fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5067fcf5ef2aSThomas Huth } 5068fcf5ef2aSThomas Huth 5069fcf5ef2aSThomas Huth /* tdi */ 5070fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 5071fcf5ef2aSThomas Huth { 5072fcf5ef2aSThomas Huth TCGv t0; 5073fcf5ef2aSThomas Huth TCGv_i32 t1; 5074fcf5ef2aSThomas Huth 5075fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5076fcf5ef2aSThomas Huth return; 5077fcf5ef2aSThomas Huth } 5078fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5079fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5080fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5081fcf5ef2aSThomas Huth tcg_temp_free(t0); 5082fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5083fcf5ef2aSThomas Huth } 5084fcf5ef2aSThomas Huth #endif 5085fcf5ef2aSThomas Huth 5086fcf5ef2aSThomas Huth /*** Processor control ***/ 5087fcf5ef2aSThomas Huth 5088fcf5ef2aSThomas Huth /* mcrxr */ 5089fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 5090fcf5ef2aSThomas Huth { 5091fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5092fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 5093fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5094fcf5ef2aSThomas Huth 5095fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 5096fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 5097fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 5098fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 5099fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 5100fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 5101fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 5102fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 5103fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5104fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5105fcf5ef2aSThomas Huth 5106fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 5107fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5108fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5109fcf5ef2aSThomas Huth } 5110fcf5ef2aSThomas Huth 5111b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 5112b63d0434SNikunj A Dadhania /* mcrxrx */ 5113b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 5114b63d0434SNikunj A Dadhania { 5115b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 5116b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 5117b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5118b63d0434SNikunj A Dadhania 5119b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 5120b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 5121b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 5122b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 5123b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 5124b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 5125b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 5126b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 5127b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 5128b63d0434SNikunj A Dadhania tcg_temp_free(t0); 5129b63d0434SNikunj A Dadhania tcg_temp_free(t1); 5130b63d0434SNikunj A Dadhania } 5131b63d0434SNikunj A Dadhania #endif 5132b63d0434SNikunj A Dadhania 5133fcf5ef2aSThomas Huth /* mfcr mfocrf */ 5134fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 5135fcf5ef2aSThomas Huth { 5136fcf5ef2aSThomas Huth uint32_t crm, crn; 5137fcf5ef2aSThomas Huth 5138fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 5139fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5140fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 5141fcf5ef2aSThomas Huth crn = ctz32(crm); 5142fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 5143fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 5144fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 5145fcf5ef2aSThomas Huth } 5146fcf5ef2aSThomas Huth } else { 5147fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5148fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 5149fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5150fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 5151fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5152fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 5153fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5154fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 5155fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5156fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 5157fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5158fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 5159fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5160fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 5161fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5162fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 5163fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5164fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5165fcf5ef2aSThomas Huth } 5166fcf5ef2aSThomas Huth } 5167fcf5ef2aSThomas Huth 5168fcf5ef2aSThomas Huth /* mfmsr */ 5169fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 5170fcf5ef2aSThomas Huth { 5171fcf5ef2aSThomas Huth CHK_SV; 5172fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 5173fcf5ef2aSThomas Huth } 5174fcf5ef2aSThomas Huth 5175fcf5ef2aSThomas Huth /* mfspr */ 5176fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 5177fcf5ef2aSThomas Huth { 5178fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 5179fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5180fcf5ef2aSThomas Huth 5181fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5182fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5183fcf5ef2aSThomas Huth #else 5184fcf5ef2aSThomas Huth if (ctx->pr) { 5185fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5186fcf5ef2aSThomas Huth } else if (ctx->hv) { 5187fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 5188fcf5ef2aSThomas Huth } else { 5189fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 5190fcf5ef2aSThomas Huth } 5191fcf5ef2aSThomas Huth #endif 5192fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 5193fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 5194fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 5195fcf5ef2aSThomas Huth } else { 5196fcf5ef2aSThomas Huth /* Privilege exception */ 5197efe843d8SDavid Gibson /* 5198efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 5199fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 5200fcf5ef2aSThomas Huth * allowing userland application to read the PVR 5201fcf5ef2aSThomas Huth */ 5202fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 520331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 520431085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 52052c2bcb1bSRichard Henderson ctx->cia); 5206fcf5ef2aSThomas Huth } 5207fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5208fcf5ef2aSThomas Huth } 5209fcf5ef2aSThomas Huth } else { 5210fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5211fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5212fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5213fcf5ef2aSThomas Huth /* This is a nop */ 5214fcf5ef2aSThomas Huth return; 5215fcf5ef2aSThomas Huth } 5216fcf5ef2aSThomas Huth /* Not defined */ 521731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 521831085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 52192c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5220fcf5ef2aSThomas Huth 5221efe843d8SDavid Gibson /* 5222efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5223efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5224fcf5ef2aSThomas Huth */ 5225fcf5ef2aSThomas Huth if (sprn & 0x10) { 5226fcf5ef2aSThomas Huth if (ctx->pr) { 5227fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5228fcf5ef2aSThomas Huth } 5229fcf5ef2aSThomas Huth } else { 5230fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5231fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5232fcf5ef2aSThomas Huth } 5233fcf5ef2aSThomas Huth } 5234fcf5ef2aSThomas Huth } 5235fcf5ef2aSThomas Huth } 5236fcf5ef2aSThomas Huth 5237fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5238fcf5ef2aSThomas Huth { 5239fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5240fcf5ef2aSThomas Huth } 5241fcf5ef2aSThomas Huth 5242fcf5ef2aSThomas Huth /* mftb */ 5243fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5244fcf5ef2aSThomas Huth { 5245fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5246fcf5ef2aSThomas Huth } 5247fcf5ef2aSThomas Huth 5248fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5249fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5250fcf5ef2aSThomas Huth { 5251fcf5ef2aSThomas Huth uint32_t crm, crn; 5252fcf5ef2aSThomas Huth 5253fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5254fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5255fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5256fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5257fcf5ef2aSThomas Huth crn = ctz32(crm); 5258fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5259fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5260fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5261fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5262fcf5ef2aSThomas Huth } 5263fcf5ef2aSThomas Huth } else { 5264fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5265fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5266fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5267fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5268fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5269fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5270fcf5ef2aSThomas Huth } 5271fcf5ef2aSThomas Huth } 5272fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5273fcf5ef2aSThomas Huth } 5274fcf5ef2aSThomas Huth } 5275fcf5ef2aSThomas Huth 5276fcf5ef2aSThomas Huth /* mtmsr */ 5277fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5278fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5279fcf5ef2aSThomas Huth { 5280fcf5ef2aSThomas Huth CHK_SV; 5281fcf5ef2aSThomas Huth 5282fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5283f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5284fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 52855ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5286fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 52875ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5288efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5289efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 52905ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5291efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 52925ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 52935ed19506SNicholas Piggin 52945ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5295fcf5ef2aSThomas Huth tcg_temp_free(t0); 52965ed19506SNicholas Piggin tcg_temp_free(t1); 52975ed19506SNicholas Piggin 5298fcf5ef2aSThomas Huth } else { 5299efe843d8SDavid Gibson /* 5300efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5301efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5302efe843d8SDavid Gibson * ppc_store_msr 5303fcf5ef2aSThomas Huth */ 5304b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5305fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5306fcf5ef2aSThomas Huth } 53075ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5308*d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5309fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5310fcf5ef2aSThomas Huth } 5311fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5312fcf5ef2aSThomas Huth 5313fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5314fcf5ef2aSThomas Huth { 5315fcf5ef2aSThomas Huth CHK_SV; 5316fcf5ef2aSThomas Huth 5317fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5318f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5319fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 53205ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5321fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 53225ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5323efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5324efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 53255ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5326efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 53275ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 53285ed19506SNicholas Piggin 53295ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5330fcf5ef2aSThomas Huth tcg_temp_free(t0); 53315ed19506SNicholas Piggin tcg_temp_free(t1); 53325ed19506SNicholas Piggin 5333fcf5ef2aSThomas Huth } else { 5334fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5335fcf5ef2aSThomas Huth 5336efe843d8SDavid Gibson /* 5337efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5338efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5339efe843d8SDavid Gibson * ppc_store_msr 5340fcf5ef2aSThomas Huth */ 5341b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5342fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5343fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5344fcf5ef2aSThomas Huth #else 5345fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5346fcf5ef2aSThomas Huth #endif 5347fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5348fcf5ef2aSThomas Huth tcg_temp_free(msr); 5349fcf5ef2aSThomas Huth } 53505ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5351*d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5352fcf5ef2aSThomas Huth #endif 5353fcf5ef2aSThomas Huth } 5354fcf5ef2aSThomas Huth 5355fcf5ef2aSThomas Huth /* mtspr */ 5356fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5357fcf5ef2aSThomas Huth { 5358fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5359fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5360fcf5ef2aSThomas Huth 5361fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5362fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5363fcf5ef2aSThomas Huth #else 5364fcf5ef2aSThomas Huth if (ctx->pr) { 5365fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5366fcf5ef2aSThomas Huth } else if (ctx->hv) { 5367fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5368fcf5ef2aSThomas Huth } else { 5369fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5370fcf5ef2aSThomas Huth } 5371fcf5ef2aSThomas Huth #endif 5372fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5373fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5374fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5375fcf5ef2aSThomas Huth } else { 5376fcf5ef2aSThomas Huth /* Privilege exception */ 537731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 537831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 53792c2bcb1bSRichard Henderson ctx->cia); 5380fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5381fcf5ef2aSThomas Huth } 5382fcf5ef2aSThomas Huth } else { 5383fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5384fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5385fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5386fcf5ef2aSThomas Huth /* This is a nop */ 5387fcf5ef2aSThomas Huth return; 5388fcf5ef2aSThomas Huth } 5389fcf5ef2aSThomas Huth 5390fcf5ef2aSThomas Huth /* Not defined */ 539131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 539231085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 53932c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5394fcf5ef2aSThomas Huth 5395fcf5ef2aSThomas Huth 5396efe843d8SDavid Gibson /* 5397efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5398efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5399fcf5ef2aSThomas Huth */ 5400fcf5ef2aSThomas Huth if (sprn & 0x10) { 5401fcf5ef2aSThomas Huth if (ctx->pr) { 5402fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5403fcf5ef2aSThomas Huth } 5404fcf5ef2aSThomas Huth } else { 5405fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5406fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5407fcf5ef2aSThomas Huth } 5408fcf5ef2aSThomas Huth } 5409fcf5ef2aSThomas Huth } 5410fcf5ef2aSThomas Huth } 5411fcf5ef2aSThomas Huth 5412fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5413fcf5ef2aSThomas Huth /* setb */ 5414fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5415fcf5ef2aSThomas Huth { 5416fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5417fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5418fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5419fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5420fcf5ef2aSThomas Huth 5421fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5422fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5423fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5424fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5425fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5426fcf5ef2aSThomas Huth 5427fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5428fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5429fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5430fcf5ef2aSThomas Huth } 5431fcf5ef2aSThomas Huth #endif 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth /*** Cache management ***/ 5434fcf5ef2aSThomas Huth 5435fcf5ef2aSThomas Huth /* dcbf */ 5436fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5437fcf5ef2aSThomas Huth { 5438fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5439fcf5ef2aSThomas Huth TCGv t0; 5440fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5441fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5442fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5443fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5444fcf5ef2aSThomas Huth tcg_temp_free(t0); 5445fcf5ef2aSThomas Huth } 5446fcf5ef2aSThomas Huth 544750728199SRoman Kapl /* dcbfep (external PID dcbf) */ 544850728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 544950728199SRoman Kapl { 545050728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 545150728199SRoman Kapl TCGv t0; 545250728199SRoman Kapl CHK_SV; 545350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 545450728199SRoman Kapl t0 = tcg_temp_new(); 545550728199SRoman Kapl gen_addr_reg_index(ctx, t0); 545650728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 545750728199SRoman Kapl tcg_temp_free(t0); 545850728199SRoman Kapl } 545950728199SRoman Kapl 5460fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5461fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5462fcf5ef2aSThomas Huth { 5463fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5464fcf5ef2aSThomas Huth GEN_PRIV; 5465fcf5ef2aSThomas Huth #else 5466fcf5ef2aSThomas Huth TCGv EA, val; 5467fcf5ef2aSThomas Huth 5468fcf5ef2aSThomas Huth CHK_SV; 5469fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5470fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5471fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5472fcf5ef2aSThomas Huth val = tcg_temp_new(); 5473fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5474fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5475fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5476fcf5ef2aSThomas Huth tcg_temp_free(val); 5477fcf5ef2aSThomas Huth tcg_temp_free(EA); 5478fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5479fcf5ef2aSThomas Huth } 5480fcf5ef2aSThomas Huth 5481fcf5ef2aSThomas Huth /* dcdst */ 5482fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5483fcf5ef2aSThomas Huth { 5484fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5485fcf5ef2aSThomas Huth TCGv t0; 5486fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5487fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5488fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5489fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5490fcf5ef2aSThomas Huth tcg_temp_free(t0); 5491fcf5ef2aSThomas Huth } 5492fcf5ef2aSThomas Huth 549350728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 549450728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 549550728199SRoman Kapl { 549650728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 549750728199SRoman Kapl TCGv t0; 549850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 549950728199SRoman Kapl t0 = tcg_temp_new(); 550050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 550150728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 550250728199SRoman Kapl tcg_temp_free(t0); 550350728199SRoman Kapl } 550450728199SRoman Kapl 5505fcf5ef2aSThomas Huth /* dcbt */ 5506fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5507fcf5ef2aSThomas Huth { 5508efe843d8SDavid Gibson /* 5509efe843d8SDavid Gibson * interpreted as no-op 5510efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5511efe843d8SDavid Gibson * does not generate any exception 5512fcf5ef2aSThomas Huth */ 5513fcf5ef2aSThomas Huth } 5514fcf5ef2aSThomas Huth 551550728199SRoman Kapl /* dcbtep */ 551650728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 551750728199SRoman Kapl { 5518efe843d8SDavid Gibson /* 5519efe843d8SDavid Gibson * interpreted as no-op 5520efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5521efe843d8SDavid Gibson * does not generate any exception 552250728199SRoman Kapl */ 552350728199SRoman Kapl } 552450728199SRoman Kapl 5525fcf5ef2aSThomas Huth /* dcbtst */ 5526fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5527fcf5ef2aSThomas Huth { 5528efe843d8SDavid Gibson /* 5529efe843d8SDavid Gibson * interpreted as no-op 5530efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5531efe843d8SDavid Gibson * does not generate any exception 5532fcf5ef2aSThomas Huth */ 5533fcf5ef2aSThomas Huth } 5534fcf5ef2aSThomas Huth 553550728199SRoman Kapl /* dcbtstep */ 553650728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 553750728199SRoman Kapl { 5538efe843d8SDavid Gibson /* 5539efe843d8SDavid Gibson * interpreted as no-op 5540efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5541efe843d8SDavid Gibson * does not generate any exception 554250728199SRoman Kapl */ 554350728199SRoman Kapl } 554450728199SRoman Kapl 5545fcf5ef2aSThomas Huth /* dcbtls */ 5546fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5547fcf5ef2aSThomas Huth { 5548fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5549fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5550fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5551fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5552fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5553fcf5ef2aSThomas Huth tcg_temp_free(t0); 5554fcf5ef2aSThomas Huth } 5555fcf5ef2aSThomas Huth 5556fcf5ef2aSThomas Huth /* dcbz */ 5557fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5558fcf5ef2aSThomas Huth { 5559fcf5ef2aSThomas Huth TCGv tcgv_addr; 5560fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5561fcf5ef2aSThomas Huth 5562fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5563fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5564fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5565fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5566fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5567fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5568fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5569fcf5ef2aSThomas Huth } 5570fcf5ef2aSThomas Huth 557150728199SRoman Kapl /* dcbzep */ 557250728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 557350728199SRoman Kapl { 557450728199SRoman Kapl TCGv tcgv_addr; 557550728199SRoman Kapl TCGv_i32 tcgv_op; 557650728199SRoman Kapl 557750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 557850728199SRoman Kapl tcgv_addr = tcg_temp_new(); 557950728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 558050728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 558150728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 558250728199SRoman Kapl tcg_temp_free(tcgv_addr); 558350728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 558450728199SRoman Kapl } 558550728199SRoman Kapl 5586fcf5ef2aSThomas Huth /* dst / dstt */ 5587fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5588fcf5ef2aSThomas Huth { 5589fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5590fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5591fcf5ef2aSThomas Huth } else { 5592fcf5ef2aSThomas Huth /* interpreted as no-op */ 5593fcf5ef2aSThomas Huth } 5594fcf5ef2aSThomas Huth } 5595fcf5ef2aSThomas Huth 5596fcf5ef2aSThomas Huth /* dstst /dststt */ 5597fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5598fcf5ef2aSThomas Huth { 5599fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5600fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5601fcf5ef2aSThomas Huth } else { 5602fcf5ef2aSThomas Huth /* interpreted as no-op */ 5603fcf5ef2aSThomas Huth } 5604fcf5ef2aSThomas Huth 5605fcf5ef2aSThomas Huth } 5606fcf5ef2aSThomas Huth 5607fcf5ef2aSThomas Huth /* dss / dssall */ 5608fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5609fcf5ef2aSThomas Huth { 5610fcf5ef2aSThomas Huth /* interpreted as no-op */ 5611fcf5ef2aSThomas Huth } 5612fcf5ef2aSThomas Huth 5613fcf5ef2aSThomas Huth /* icbi */ 5614fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5615fcf5ef2aSThomas Huth { 5616fcf5ef2aSThomas Huth TCGv t0; 5617fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5618fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5619fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5620fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5621fcf5ef2aSThomas Huth tcg_temp_free(t0); 5622fcf5ef2aSThomas Huth } 5623fcf5ef2aSThomas Huth 562450728199SRoman Kapl /* icbiep */ 562550728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 562650728199SRoman Kapl { 562750728199SRoman Kapl TCGv t0; 562850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 562950728199SRoman Kapl t0 = tcg_temp_new(); 563050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 563150728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 563250728199SRoman Kapl tcg_temp_free(t0); 563350728199SRoman Kapl } 563450728199SRoman Kapl 5635fcf5ef2aSThomas Huth /* Optional: */ 5636fcf5ef2aSThomas Huth /* dcba */ 5637fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5638fcf5ef2aSThomas Huth { 5639efe843d8SDavid Gibson /* 5640efe843d8SDavid Gibson * interpreted as no-op 5641efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5642fcf5ef2aSThomas Huth * but does not generate any exception 5643fcf5ef2aSThomas Huth */ 5644fcf5ef2aSThomas Huth } 5645fcf5ef2aSThomas Huth 5646fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5647fcf5ef2aSThomas Huth /* Supervisor only: */ 5648fcf5ef2aSThomas Huth 5649fcf5ef2aSThomas Huth /* mfsr */ 5650fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5651fcf5ef2aSThomas Huth { 5652fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5653fcf5ef2aSThomas Huth GEN_PRIV; 5654fcf5ef2aSThomas Huth #else 5655fcf5ef2aSThomas Huth TCGv t0; 5656fcf5ef2aSThomas Huth 5657fcf5ef2aSThomas Huth CHK_SV; 5658fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5659fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5660fcf5ef2aSThomas Huth tcg_temp_free(t0); 5661fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5662fcf5ef2aSThomas Huth } 5663fcf5ef2aSThomas Huth 5664fcf5ef2aSThomas Huth /* mfsrin */ 5665fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5666fcf5ef2aSThomas Huth { 5667fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5668fcf5ef2aSThomas Huth GEN_PRIV; 5669fcf5ef2aSThomas Huth #else 5670fcf5ef2aSThomas Huth TCGv t0; 5671fcf5ef2aSThomas Huth 5672fcf5ef2aSThomas Huth CHK_SV; 5673fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5674e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5675fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5676fcf5ef2aSThomas Huth tcg_temp_free(t0); 5677fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5678fcf5ef2aSThomas Huth } 5679fcf5ef2aSThomas Huth 5680fcf5ef2aSThomas Huth /* mtsr */ 5681fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5682fcf5ef2aSThomas Huth { 5683fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5684fcf5ef2aSThomas Huth GEN_PRIV; 5685fcf5ef2aSThomas Huth #else 5686fcf5ef2aSThomas Huth TCGv t0; 5687fcf5ef2aSThomas Huth 5688fcf5ef2aSThomas Huth CHK_SV; 5689fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5690fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5691fcf5ef2aSThomas Huth tcg_temp_free(t0); 5692fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5693fcf5ef2aSThomas Huth } 5694fcf5ef2aSThomas Huth 5695fcf5ef2aSThomas Huth /* mtsrin */ 5696fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5697fcf5ef2aSThomas Huth { 5698fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5699fcf5ef2aSThomas Huth GEN_PRIV; 5700fcf5ef2aSThomas Huth #else 5701fcf5ef2aSThomas Huth TCGv t0; 5702fcf5ef2aSThomas Huth CHK_SV; 5703fcf5ef2aSThomas Huth 5704fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5705e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5706fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5707fcf5ef2aSThomas Huth tcg_temp_free(t0); 5708fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5709fcf5ef2aSThomas Huth } 5710fcf5ef2aSThomas Huth 5711fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5712fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5713fcf5ef2aSThomas Huth 5714fcf5ef2aSThomas Huth /* mfsr */ 5715fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5716fcf5ef2aSThomas Huth { 5717fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5718fcf5ef2aSThomas Huth GEN_PRIV; 5719fcf5ef2aSThomas Huth #else 5720fcf5ef2aSThomas Huth TCGv t0; 5721fcf5ef2aSThomas Huth 5722fcf5ef2aSThomas Huth CHK_SV; 5723fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5724fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5725fcf5ef2aSThomas Huth tcg_temp_free(t0); 5726fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5727fcf5ef2aSThomas Huth } 5728fcf5ef2aSThomas Huth 5729fcf5ef2aSThomas Huth /* mfsrin */ 5730fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5731fcf5ef2aSThomas Huth { 5732fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5733fcf5ef2aSThomas Huth GEN_PRIV; 5734fcf5ef2aSThomas Huth #else 5735fcf5ef2aSThomas Huth TCGv t0; 5736fcf5ef2aSThomas Huth 5737fcf5ef2aSThomas Huth CHK_SV; 5738fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5739e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5740fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5741fcf5ef2aSThomas Huth tcg_temp_free(t0); 5742fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5743fcf5ef2aSThomas Huth } 5744fcf5ef2aSThomas Huth 5745fcf5ef2aSThomas Huth /* mtsr */ 5746fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5747fcf5ef2aSThomas Huth { 5748fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5749fcf5ef2aSThomas Huth GEN_PRIV; 5750fcf5ef2aSThomas Huth #else 5751fcf5ef2aSThomas Huth TCGv t0; 5752fcf5ef2aSThomas Huth 5753fcf5ef2aSThomas Huth CHK_SV; 5754fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5755fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5756fcf5ef2aSThomas Huth tcg_temp_free(t0); 5757fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5758fcf5ef2aSThomas Huth } 5759fcf5ef2aSThomas Huth 5760fcf5ef2aSThomas Huth /* mtsrin */ 5761fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5762fcf5ef2aSThomas Huth { 5763fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5764fcf5ef2aSThomas Huth GEN_PRIV; 5765fcf5ef2aSThomas Huth #else 5766fcf5ef2aSThomas Huth TCGv t0; 5767fcf5ef2aSThomas Huth 5768fcf5ef2aSThomas Huth CHK_SV; 5769fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5770e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5771fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5772fcf5ef2aSThomas Huth tcg_temp_free(t0); 5773fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5774fcf5ef2aSThomas Huth } 5775fcf5ef2aSThomas Huth 5776fcf5ef2aSThomas Huth /* slbmte */ 5777fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5778fcf5ef2aSThomas Huth { 5779fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5780fcf5ef2aSThomas Huth GEN_PRIV; 5781fcf5ef2aSThomas Huth #else 5782fcf5ef2aSThomas Huth CHK_SV; 5783fcf5ef2aSThomas Huth 5784fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5785fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5786fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5787fcf5ef2aSThomas Huth } 5788fcf5ef2aSThomas Huth 5789fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5790fcf5ef2aSThomas Huth { 5791fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5792fcf5ef2aSThomas Huth GEN_PRIV; 5793fcf5ef2aSThomas Huth #else 5794fcf5ef2aSThomas Huth CHK_SV; 5795fcf5ef2aSThomas Huth 5796fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5797fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5798fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5799fcf5ef2aSThomas Huth } 5800fcf5ef2aSThomas Huth 5801fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5802fcf5ef2aSThomas Huth { 5803fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5804fcf5ef2aSThomas Huth GEN_PRIV; 5805fcf5ef2aSThomas Huth #else 5806fcf5ef2aSThomas Huth CHK_SV; 5807fcf5ef2aSThomas Huth 5808fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5809fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5810fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5811fcf5ef2aSThomas Huth } 5812fcf5ef2aSThomas Huth 5813fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5814fcf5ef2aSThomas Huth { 5815fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5816fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5817fcf5ef2aSThomas Huth #else 5818fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5819fcf5ef2aSThomas Huth 5820fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5821fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5822fcf5ef2aSThomas Huth return; 5823fcf5ef2aSThomas Huth } 5824fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5825fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5826fcf5ef2aSThomas Huth l1 = gen_new_label(); 5827fcf5ef2aSThomas Huth l2 = gen_new_label(); 5828fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5829fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5830efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5831fcf5ef2aSThomas Huth tcg_gen_br(l2); 5832fcf5ef2aSThomas Huth gen_set_label(l1); 5833fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5834fcf5ef2aSThomas Huth gen_set_label(l2); 5835fcf5ef2aSThomas Huth #endif 5836fcf5ef2aSThomas Huth } 5837fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5838fcf5ef2aSThomas Huth 5839fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5840fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5841fcf5ef2aSThomas Huth 5842fcf5ef2aSThomas Huth /* tlbia */ 5843fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5844fcf5ef2aSThomas Huth { 5845fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5846fcf5ef2aSThomas Huth GEN_PRIV; 5847fcf5ef2aSThomas Huth #else 5848fcf5ef2aSThomas Huth CHK_HV; 5849fcf5ef2aSThomas Huth 5850fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5851fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5852fcf5ef2aSThomas Huth } 5853fcf5ef2aSThomas Huth 5854fcf5ef2aSThomas Huth /* tlbiel */ 5855fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5856fcf5ef2aSThomas Huth { 5857fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5858fcf5ef2aSThomas Huth GEN_PRIV; 5859fcf5ef2aSThomas Huth #else 5860fcf5ef2aSThomas Huth CHK_SV; 5861fcf5ef2aSThomas Huth 5862fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5863fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5864fcf5ef2aSThomas Huth } 5865fcf5ef2aSThomas Huth 5866fcf5ef2aSThomas Huth /* tlbie */ 5867fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5868fcf5ef2aSThomas Huth { 5869fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5870fcf5ef2aSThomas Huth GEN_PRIV; 5871fcf5ef2aSThomas Huth #else 5872fcf5ef2aSThomas Huth TCGv_i32 t1; 5873c6fd28fdSSuraj Jitindar Singh 5874c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 587591c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5876c6fd28fdSSuraj Jitindar Singh } else { 5877c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5878c6fd28fdSSuraj Jitindar Singh } 5879fcf5ef2aSThomas Huth 5880fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5881fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5882fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5883fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5884fcf5ef2aSThomas Huth tcg_temp_free(t0); 5885fcf5ef2aSThomas Huth } else { 5886fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5887fcf5ef2aSThomas Huth } 5888fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5889fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5890fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5891fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5892fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5893fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5894fcf5ef2aSThomas Huth } 5895fcf5ef2aSThomas Huth 5896fcf5ef2aSThomas Huth /* tlbsync */ 5897fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5898fcf5ef2aSThomas Huth { 5899fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5900fcf5ef2aSThomas Huth GEN_PRIV; 5901fcf5ef2aSThomas Huth #else 590291c60f12SCédric Le Goater 590391c60f12SCédric Le Goater if (ctx->gtse) { 590491c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 590591c60f12SCédric Le Goater } else { 590691c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 590791c60f12SCédric Le Goater } 5908fcf5ef2aSThomas Huth 5909fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5910fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5911fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5912fcf5ef2aSThomas Huth } 5913fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5914fcf5ef2aSThomas Huth } 5915fcf5ef2aSThomas Huth 5916fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5917fcf5ef2aSThomas Huth /* slbia */ 5918fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5919fcf5ef2aSThomas Huth { 5920fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5921fcf5ef2aSThomas Huth GEN_PRIV; 5922fcf5ef2aSThomas Huth #else 59230418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 59240418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 59250418bf78SNicholas Piggin 5926fcf5ef2aSThomas Huth CHK_SV; 5927fcf5ef2aSThomas Huth 59280418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 59293119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5930fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5931fcf5ef2aSThomas Huth } 5932fcf5ef2aSThomas Huth 5933fcf5ef2aSThomas Huth /* slbie */ 5934fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5935fcf5ef2aSThomas Huth { 5936fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5937fcf5ef2aSThomas Huth GEN_PRIV; 5938fcf5ef2aSThomas Huth #else 5939fcf5ef2aSThomas Huth CHK_SV; 5940fcf5ef2aSThomas Huth 5941fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5942fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5943fcf5ef2aSThomas Huth } 5944a63f1dfcSNikunj A Dadhania 5945a63f1dfcSNikunj A Dadhania /* slbieg */ 5946a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5947a63f1dfcSNikunj A Dadhania { 5948a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5949a63f1dfcSNikunj A Dadhania GEN_PRIV; 5950a63f1dfcSNikunj A Dadhania #else 5951a63f1dfcSNikunj A Dadhania CHK_SV; 5952a63f1dfcSNikunj A Dadhania 5953a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5954a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5955a63f1dfcSNikunj A Dadhania } 5956a63f1dfcSNikunj A Dadhania 595762d897caSNikunj A Dadhania /* slbsync */ 595862d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 595962d897caSNikunj A Dadhania { 596062d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 596162d897caSNikunj A Dadhania GEN_PRIV; 596262d897caSNikunj A Dadhania #else 596362d897caSNikunj A Dadhania CHK_SV; 596462d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 596562d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 596662d897caSNikunj A Dadhania } 596762d897caSNikunj A Dadhania 5968fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5969fcf5ef2aSThomas Huth 5970fcf5ef2aSThomas Huth /*** External control ***/ 5971fcf5ef2aSThomas Huth /* Optional: */ 5972fcf5ef2aSThomas Huth 5973fcf5ef2aSThomas Huth /* eciwx */ 5974fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5975fcf5ef2aSThomas Huth { 5976fcf5ef2aSThomas Huth TCGv t0; 5977fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5978fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5979fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5980fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5981c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5982c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5983fcf5ef2aSThomas Huth tcg_temp_free(t0); 5984fcf5ef2aSThomas Huth } 5985fcf5ef2aSThomas Huth 5986fcf5ef2aSThomas Huth /* ecowx */ 5987fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5988fcf5ef2aSThomas Huth { 5989fcf5ef2aSThomas Huth TCGv t0; 5990fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5991fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5992fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5993fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5994c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5995c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5996fcf5ef2aSThomas Huth tcg_temp_free(t0); 5997fcf5ef2aSThomas Huth } 5998fcf5ef2aSThomas Huth 5999fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 6000fcf5ef2aSThomas Huth 6001fcf5ef2aSThomas Huth /* abs - abs. */ 6002fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 6003fcf5ef2aSThomas Huth { 6004fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6005fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6006fe21b785SRichard Henderson 6007fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6008efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6009fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6010fcf5ef2aSThomas Huth } 6011efe843d8SDavid Gibson } 6012fcf5ef2aSThomas Huth 6013fcf5ef2aSThomas Huth /* abso - abso. */ 6014fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 6015fcf5ef2aSThomas Huth { 6016fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6017fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6018fe21b785SRichard Henderson 6019fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 6020fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6021fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 6022efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6023fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6024fcf5ef2aSThomas Huth } 6025efe843d8SDavid Gibson } 6026fcf5ef2aSThomas Huth 6027fcf5ef2aSThomas Huth /* clcs */ 6028fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 6029fcf5ef2aSThomas Huth { 6030fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 6031fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6032fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6033fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 6034fcf5ef2aSThomas Huth } 6035fcf5ef2aSThomas Huth 6036fcf5ef2aSThomas Huth /* div - div. */ 6037fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 6038fcf5ef2aSThomas Huth { 6039fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6040fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6041efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6042fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6043fcf5ef2aSThomas Huth } 6044efe843d8SDavid Gibson } 6045fcf5ef2aSThomas Huth 6046fcf5ef2aSThomas Huth /* divo - divo. */ 6047fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 6048fcf5ef2aSThomas Huth { 6049fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6050fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6051efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6052fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6053fcf5ef2aSThomas Huth } 6054efe843d8SDavid Gibson } 6055fcf5ef2aSThomas Huth 6056fcf5ef2aSThomas Huth /* divs - divs. */ 6057fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 6058fcf5ef2aSThomas Huth { 6059fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6060fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6061efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6062fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6063fcf5ef2aSThomas Huth } 6064efe843d8SDavid Gibson } 6065fcf5ef2aSThomas Huth 6066fcf5ef2aSThomas Huth /* divso - divso. */ 6067fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 6068fcf5ef2aSThomas Huth { 6069fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 6070fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6071efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6072fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6073fcf5ef2aSThomas Huth } 6074efe843d8SDavid Gibson } 6075fcf5ef2aSThomas Huth 6076fcf5ef2aSThomas Huth /* doz - doz. */ 6077fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 6078fcf5ef2aSThomas Huth { 6079fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6080fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6081efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6082efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6083efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 6084efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 6085fcf5ef2aSThomas Huth tcg_gen_br(l2); 6086fcf5ef2aSThomas Huth gen_set_label(l1); 6087fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6088fcf5ef2aSThomas Huth gen_set_label(l2); 6089efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6090fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6091fcf5ef2aSThomas Huth } 6092efe843d8SDavid Gibson } 6093fcf5ef2aSThomas Huth 6094fcf5ef2aSThomas Huth /* dozo - dozo. */ 6095fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 6096fcf5ef2aSThomas Huth { 6097fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6098fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6099fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6100fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6101fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6102fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6103fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6104efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6105efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6106fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6107fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6108fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 6109fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6110fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 6111fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6112fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6113fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6114fcf5ef2aSThomas Huth tcg_gen_br(l2); 6115fcf5ef2aSThomas Huth gen_set_label(l1); 6116fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6117fcf5ef2aSThomas Huth gen_set_label(l2); 6118fcf5ef2aSThomas Huth tcg_temp_free(t0); 6119fcf5ef2aSThomas Huth tcg_temp_free(t1); 6120fcf5ef2aSThomas Huth tcg_temp_free(t2); 6121efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6122fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6123fcf5ef2aSThomas Huth } 6124efe843d8SDavid Gibson } 6125fcf5ef2aSThomas Huth 6126fcf5ef2aSThomas Huth /* dozi */ 6127fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 6128fcf5ef2aSThomas Huth { 6129fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 6130fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6131fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6132fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 6133fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 6134fcf5ef2aSThomas Huth tcg_gen_br(l2); 6135fcf5ef2aSThomas Huth gen_set_label(l1); 6136fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6137fcf5ef2aSThomas Huth gen_set_label(l2); 6138efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6139fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6140fcf5ef2aSThomas Huth } 6141efe843d8SDavid Gibson } 6142fcf5ef2aSThomas Huth 6143fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 6144fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 6145fcf5ef2aSThomas Huth { 6146fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6147fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 6148fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 6149fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 6150fcf5ef2aSThomas Huth 6151fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6152fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 6153fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6154fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 6155fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 6156fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 6157fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 6158efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6159fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 6160efe843d8SDavid Gibson } 6161fcf5ef2aSThomas Huth tcg_temp_free(t0); 6162fcf5ef2aSThomas Huth } 6163fcf5ef2aSThomas Huth 6164fcf5ef2aSThomas Huth /* maskg - maskg. */ 6165fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 6166fcf5ef2aSThomas Huth { 6167fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6168fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6169fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6170fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6171fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 6172fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 6173fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6174fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 6175fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 6176fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 6177fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 6178fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 6179fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 6180fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6181fcf5ef2aSThomas Huth gen_set_label(l1); 6182fcf5ef2aSThomas Huth tcg_temp_free(t0); 6183fcf5ef2aSThomas Huth tcg_temp_free(t1); 6184fcf5ef2aSThomas Huth tcg_temp_free(t2); 6185fcf5ef2aSThomas Huth tcg_temp_free(t3); 6186efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6187fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6188fcf5ef2aSThomas Huth } 6189efe843d8SDavid Gibson } 6190fcf5ef2aSThomas Huth 6191fcf5ef2aSThomas Huth /* maskir - maskir. */ 6192fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 6193fcf5ef2aSThomas Huth { 6194fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6195fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6196fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6197fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6198fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6199fcf5ef2aSThomas Huth tcg_temp_free(t0); 6200fcf5ef2aSThomas Huth tcg_temp_free(t1); 6201efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6202fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6203fcf5ef2aSThomas Huth } 6204efe843d8SDavid Gibson } 6205fcf5ef2aSThomas Huth 6206fcf5ef2aSThomas Huth /* mul - mul. */ 6207fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 6208fcf5ef2aSThomas Huth { 6209fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6210fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6211fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6212fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6213fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6214fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6215fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6216fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6217fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6218fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6219fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6220fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6221fcf5ef2aSThomas Huth tcg_temp_free(t2); 6222efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6223fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6224fcf5ef2aSThomas Huth } 6225efe843d8SDavid Gibson } 6226fcf5ef2aSThomas Huth 6227fcf5ef2aSThomas Huth /* mulo - mulo. */ 6228fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6229fcf5ef2aSThomas Huth { 6230fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6231fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6232fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6233fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6234fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6235fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6236fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6237fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6238fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6239fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6240fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6241fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6242fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6243fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6244fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6245fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6246fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6247fcf5ef2aSThomas Huth gen_set_label(l1); 6248fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6249fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6250fcf5ef2aSThomas Huth tcg_temp_free(t2); 6251efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6252fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6253fcf5ef2aSThomas Huth } 6254efe843d8SDavid Gibson } 6255fcf5ef2aSThomas Huth 6256fcf5ef2aSThomas Huth /* nabs - nabs. */ 6257fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6258fcf5ef2aSThomas Huth { 6259fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6260fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6261fe21b785SRichard Henderson 6262fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6263fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6264efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6265fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6266fcf5ef2aSThomas Huth } 6267efe843d8SDavid Gibson } 6268fcf5ef2aSThomas Huth 6269fcf5ef2aSThomas Huth /* nabso - nabso. */ 6270fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6271fcf5ef2aSThomas Huth { 6272fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6273fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6274fe21b785SRichard Henderson 6275fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6276fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6277fcf5ef2aSThomas Huth /* nabs never overflows */ 6278fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6279efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6280fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6281fcf5ef2aSThomas Huth } 6282efe843d8SDavid Gibson } 6283fcf5ef2aSThomas Huth 6284fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6285fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6286fcf5ef2aSThomas Huth { 6287fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6288fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6289fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6290fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6291fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6292fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6293efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6294efe843d8SDavid Gibson ~MASK(mb, me)); 6295fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6296fcf5ef2aSThomas Huth tcg_temp_free(t0); 6297efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6298fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6299fcf5ef2aSThomas Huth } 6300efe843d8SDavid Gibson } 6301fcf5ef2aSThomas Huth 6302fcf5ef2aSThomas Huth /* rrib - rrib. */ 6303fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6304fcf5ef2aSThomas Huth { 6305fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6306fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6307fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6308fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6309fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6310fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6311fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6312fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6313fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6314fcf5ef2aSThomas Huth tcg_temp_free(t0); 6315fcf5ef2aSThomas Huth tcg_temp_free(t1); 6316efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6317fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6318fcf5ef2aSThomas Huth } 6319efe843d8SDavid Gibson } 6320fcf5ef2aSThomas Huth 6321fcf5ef2aSThomas Huth /* sle - sle. */ 6322fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6323fcf5ef2aSThomas Huth { 6324fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6325fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6326fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6327fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6328fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6329fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6330fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6331fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6332fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6333fcf5ef2aSThomas Huth tcg_temp_free(t0); 6334fcf5ef2aSThomas Huth tcg_temp_free(t1); 6335efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6336fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6337fcf5ef2aSThomas Huth } 6338efe843d8SDavid Gibson } 6339fcf5ef2aSThomas Huth 6340fcf5ef2aSThomas Huth /* sleq - sleq. */ 6341fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6342fcf5ef2aSThomas Huth { 6343fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6344fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6345fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6346fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6347fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6348fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6349fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6350fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6351fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6352fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6353fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6354fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6355fcf5ef2aSThomas Huth tcg_temp_free(t0); 6356fcf5ef2aSThomas Huth tcg_temp_free(t1); 6357fcf5ef2aSThomas Huth tcg_temp_free(t2); 6358efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6359fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6360fcf5ef2aSThomas Huth } 6361efe843d8SDavid Gibson } 6362fcf5ef2aSThomas Huth 6363fcf5ef2aSThomas Huth /* sliq - sliq. */ 6364fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6365fcf5ef2aSThomas Huth { 6366fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6367fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6368fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6369fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6370fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6371fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6372fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6373fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6374fcf5ef2aSThomas Huth tcg_temp_free(t0); 6375fcf5ef2aSThomas Huth tcg_temp_free(t1); 6376efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6377fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6378fcf5ef2aSThomas Huth } 6379efe843d8SDavid Gibson } 6380fcf5ef2aSThomas Huth 6381fcf5ef2aSThomas Huth /* slliq - slliq. */ 6382fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6383fcf5ef2aSThomas Huth { 6384fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6385fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6386fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6387fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6388fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6389fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6390fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6391fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6392fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6393fcf5ef2aSThomas Huth tcg_temp_free(t0); 6394fcf5ef2aSThomas Huth tcg_temp_free(t1); 6395efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6396fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6397fcf5ef2aSThomas Huth } 6398efe843d8SDavid Gibson } 6399fcf5ef2aSThomas Huth 6400fcf5ef2aSThomas Huth /* sllq - sllq. */ 6401fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6402fcf5ef2aSThomas Huth { 6403fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6404fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6405fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6406fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6407fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6408fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6409fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6410fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6411fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6412fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6413fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6414fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6415fcf5ef2aSThomas Huth tcg_gen_br(l2); 6416fcf5ef2aSThomas Huth gen_set_label(l1); 6417fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6418fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6419fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6420fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6421fcf5ef2aSThomas Huth gen_set_label(l2); 6422fcf5ef2aSThomas Huth tcg_temp_free(t0); 6423fcf5ef2aSThomas Huth tcg_temp_free(t1); 6424fcf5ef2aSThomas Huth tcg_temp_free(t2); 6425efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6426fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6427fcf5ef2aSThomas Huth } 6428efe843d8SDavid Gibson } 6429fcf5ef2aSThomas Huth 6430fcf5ef2aSThomas Huth /* slq - slq. */ 6431fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6432fcf5ef2aSThomas Huth { 6433fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6434fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6435fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6436fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6437fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6438fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6439fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6440fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6441fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6442fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6443fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6444fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6445fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6446fcf5ef2aSThomas Huth gen_set_label(l1); 6447fcf5ef2aSThomas Huth tcg_temp_free(t0); 6448fcf5ef2aSThomas Huth tcg_temp_free(t1); 6449efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6450fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6451fcf5ef2aSThomas Huth } 6452efe843d8SDavid Gibson } 6453fcf5ef2aSThomas Huth 6454fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6455fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6456fcf5ef2aSThomas Huth { 6457fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6458fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6459fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6460fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6461fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6462fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6463fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6464fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6465fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6466fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6467fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6468fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6469fcf5ef2aSThomas Huth gen_set_label(l1); 6470fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6471fcf5ef2aSThomas Huth tcg_temp_free(t0); 6472fcf5ef2aSThomas Huth tcg_temp_free(t1); 6473efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6474fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6475fcf5ef2aSThomas Huth } 6476efe843d8SDavid Gibson } 6477fcf5ef2aSThomas Huth 6478fcf5ef2aSThomas Huth /* sraq - sraq. */ 6479fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6480fcf5ef2aSThomas Huth { 6481fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6482fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6483fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6484fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6485fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6486fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6487fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6488fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6489fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6490fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6491fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6492fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6493fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6494fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6495fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6496fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6497fcf5ef2aSThomas Huth gen_set_label(l1); 6498fcf5ef2aSThomas Huth tcg_temp_free(t0); 6499fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6500fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6501fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6502fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6503fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6504fcf5ef2aSThomas Huth gen_set_label(l2); 6505fcf5ef2aSThomas Huth tcg_temp_free(t1); 6506fcf5ef2aSThomas Huth tcg_temp_free(t2); 6507efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6508fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6509fcf5ef2aSThomas Huth } 6510efe843d8SDavid Gibson } 6511fcf5ef2aSThomas Huth 6512fcf5ef2aSThomas Huth /* sre - sre. */ 6513fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6514fcf5ef2aSThomas Huth { 6515fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6516fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6517fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6518fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6519fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6520fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6521fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6522fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6523fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6524fcf5ef2aSThomas Huth tcg_temp_free(t0); 6525fcf5ef2aSThomas Huth tcg_temp_free(t1); 6526efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6527fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6528fcf5ef2aSThomas Huth } 6529efe843d8SDavid Gibson } 6530fcf5ef2aSThomas Huth 6531fcf5ef2aSThomas Huth /* srea - srea. */ 6532fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6533fcf5ef2aSThomas Huth { 6534fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6535fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6536fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6537fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6538fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6539fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6540fcf5ef2aSThomas Huth tcg_temp_free(t0); 6541fcf5ef2aSThomas Huth tcg_temp_free(t1); 6542efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6543fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6544fcf5ef2aSThomas Huth } 6545efe843d8SDavid Gibson } 6546fcf5ef2aSThomas Huth 6547fcf5ef2aSThomas Huth /* sreq */ 6548fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6549fcf5ef2aSThomas Huth { 6550fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6551fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6552fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6553fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6554fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6555fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6556fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6557fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6558fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6559fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6560fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6561fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6562fcf5ef2aSThomas Huth tcg_temp_free(t0); 6563fcf5ef2aSThomas Huth tcg_temp_free(t1); 6564fcf5ef2aSThomas Huth tcg_temp_free(t2); 6565efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6566fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6567fcf5ef2aSThomas Huth } 6568efe843d8SDavid Gibson } 6569fcf5ef2aSThomas Huth 6570fcf5ef2aSThomas Huth /* sriq */ 6571fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6572fcf5ef2aSThomas Huth { 6573fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6574fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6575fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6576fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6577fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6578fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6579fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6580fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6581fcf5ef2aSThomas Huth tcg_temp_free(t0); 6582fcf5ef2aSThomas Huth tcg_temp_free(t1); 6583efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6584fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6585fcf5ef2aSThomas Huth } 6586efe843d8SDavid Gibson } 6587fcf5ef2aSThomas Huth 6588fcf5ef2aSThomas Huth /* srliq */ 6589fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6590fcf5ef2aSThomas Huth { 6591fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6592fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6593fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6594fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6595fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6596fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6597fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6598fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6599fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6600fcf5ef2aSThomas Huth tcg_temp_free(t0); 6601fcf5ef2aSThomas Huth tcg_temp_free(t1); 6602efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6603fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6604fcf5ef2aSThomas Huth } 6605efe843d8SDavid Gibson } 6606fcf5ef2aSThomas Huth 6607fcf5ef2aSThomas Huth /* srlq */ 6608fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6609fcf5ef2aSThomas Huth { 6610fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6611fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6612fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6613fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6614fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6615fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6616fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6617fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6618fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6619fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6620fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6621fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6622fcf5ef2aSThomas Huth tcg_gen_br(l2); 6623fcf5ef2aSThomas Huth gen_set_label(l1); 6624fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6625fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6626fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6627fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6628fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6629fcf5ef2aSThomas Huth gen_set_label(l2); 6630fcf5ef2aSThomas Huth tcg_temp_free(t0); 6631fcf5ef2aSThomas Huth tcg_temp_free(t1); 6632fcf5ef2aSThomas Huth tcg_temp_free(t2); 6633efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6634fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6635fcf5ef2aSThomas Huth } 6636efe843d8SDavid Gibson } 6637fcf5ef2aSThomas Huth 6638fcf5ef2aSThomas Huth /* srq */ 6639fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6640fcf5ef2aSThomas Huth { 6641fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6642fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6643fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6644fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6645fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6646fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6647fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6648fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6649fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6650fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6651fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6652fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6653fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6654fcf5ef2aSThomas Huth gen_set_label(l1); 6655fcf5ef2aSThomas Huth tcg_temp_free(t0); 6656fcf5ef2aSThomas Huth tcg_temp_free(t1); 6657efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6658fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6659fcf5ef2aSThomas Huth } 6660efe843d8SDavid Gibson } 6661fcf5ef2aSThomas Huth 6662fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6663fcf5ef2aSThomas Huth 6664fcf5ef2aSThomas Huth /* dsa */ 6665fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6666fcf5ef2aSThomas Huth { 6667fcf5ef2aSThomas Huth /* XXX: TODO */ 6668fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6669fcf5ef2aSThomas Huth } 6670fcf5ef2aSThomas Huth 6671fcf5ef2aSThomas Huth /* esa */ 6672fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6673fcf5ef2aSThomas Huth { 6674fcf5ef2aSThomas Huth /* XXX: TODO */ 6675fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6676fcf5ef2aSThomas Huth } 6677fcf5ef2aSThomas Huth 6678fcf5ef2aSThomas Huth /* mfrom */ 6679fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6680fcf5ef2aSThomas Huth { 6681fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6682fcf5ef2aSThomas Huth GEN_PRIV; 6683fcf5ef2aSThomas Huth #else 6684fcf5ef2aSThomas Huth CHK_SV; 6685fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6686fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6687fcf5ef2aSThomas Huth } 6688fcf5ef2aSThomas Huth 6689fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6690fcf5ef2aSThomas Huth 6691fcf5ef2aSThomas Huth /* tlbld */ 6692fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6693fcf5ef2aSThomas Huth { 6694fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6695fcf5ef2aSThomas Huth GEN_PRIV; 6696fcf5ef2aSThomas Huth #else 6697fcf5ef2aSThomas Huth CHK_SV; 6698fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6699fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6700fcf5ef2aSThomas Huth } 6701fcf5ef2aSThomas Huth 6702fcf5ef2aSThomas Huth /* tlbli */ 6703fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6704fcf5ef2aSThomas Huth { 6705fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6706fcf5ef2aSThomas Huth GEN_PRIV; 6707fcf5ef2aSThomas Huth #else 6708fcf5ef2aSThomas Huth CHK_SV; 6709fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6710fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6711fcf5ef2aSThomas Huth } 6712fcf5ef2aSThomas Huth 6713fcf5ef2aSThomas Huth /* 74xx TLB management */ 6714fcf5ef2aSThomas Huth 6715fcf5ef2aSThomas Huth /* tlbld */ 6716fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6717fcf5ef2aSThomas Huth { 6718fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6719fcf5ef2aSThomas Huth GEN_PRIV; 6720fcf5ef2aSThomas Huth #else 6721fcf5ef2aSThomas Huth CHK_SV; 6722fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6723fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6724fcf5ef2aSThomas Huth } 6725fcf5ef2aSThomas Huth 6726fcf5ef2aSThomas Huth /* tlbli */ 6727fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6728fcf5ef2aSThomas Huth { 6729fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6730fcf5ef2aSThomas Huth GEN_PRIV; 6731fcf5ef2aSThomas Huth #else 6732fcf5ef2aSThomas Huth CHK_SV; 6733fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6734fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6735fcf5ef2aSThomas Huth } 6736fcf5ef2aSThomas Huth 6737fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6738fcf5ef2aSThomas Huth 6739fcf5ef2aSThomas Huth /* clf */ 6740fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6741fcf5ef2aSThomas Huth { 6742fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6743fcf5ef2aSThomas Huth } 6744fcf5ef2aSThomas Huth 6745fcf5ef2aSThomas Huth /* cli */ 6746fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6747fcf5ef2aSThomas Huth { 6748fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6749fcf5ef2aSThomas Huth GEN_PRIV; 6750fcf5ef2aSThomas Huth #else 6751fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6752fcf5ef2aSThomas Huth CHK_SV; 6753fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6754fcf5ef2aSThomas Huth } 6755fcf5ef2aSThomas Huth 6756fcf5ef2aSThomas Huth /* dclst */ 6757fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6758fcf5ef2aSThomas Huth { 6759fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6760fcf5ef2aSThomas Huth } 6761fcf5ef2aSThomas Huth 6762fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6763fcf5ef2aSThomas Huth { 6764fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6765fcf5ef2aSThomas Huth GEN_PRIV; 6766fcf5ef2aSThomas Huth #else 6767fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6768fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6769fcf5ef2aSThomas Huth TCGv t0; 6770fcf5ef2aSThomas Huth 6771fcf5ef2aSThomas Huth CHK_SV; 6772fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6773fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6774e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6775fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6776fcf5ef2aSThomas Huth tcg_temp_free(t0); 6777efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6778fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6779efe843d8SDavid Gibson } 6780fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6781fcf5ef2aSThomas Huth } 6782fcf5ef2aSThomas Huth 6783fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6784fcf5ef2aSThomas Huth { 6785fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6786fcf5ef2aSThomas Huth GEN_PRIV; 6787fcf5ef2aSThomas Huth #else 6788fcf5ef2aSThomas Huth TCGv t0; 6789fcf5ef2aSThomas Huth 6790fcf5ef2aSThomas Huth CHK_SV; 6791fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6792fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6793fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6794fcf5ef2aSThomas Huth tcg_temp_free(t0); 6795fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6796fcf5ef2aSThomas Huth } 6797fcf5ef2aSThomas Huth 6798fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6799fcf5ef2aSThomas Huth { 6800fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6801fcf5ef2aSThomas Huth GEN_PRIV; 6802fcf5ef2aSThomas Huth #else 6803fcf5ef2aSThomas Huth CHK_SV; 6804fcf5ef2aSThomas Huth 6805fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 680659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6807fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6808fcf5ef2aSThomas Huth } 6809fcf5ef2aSThomas Huth 6810fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6811fcf5ef2aSThomas Huth 6812fcf5ef2aSThomas Huth /* BookE specific instructions */ 6813fcf5ef2aSThomas Huth 6814fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6815fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6816fcf5ef2aSThomas Huth { 6817fcf5ef2aSThomas Huth /* XXX: TODO */ 6818fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6819fcf5ef2aSThomas Huth } 6820fcf5ef2aSThomas Huth 6821fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6822fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6823fcf5ef2aSThomas Huth { 6824fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6825fcf5ef2aSThomas Huth GEN_PRIV; 6826fcf5ef2aSThomas Huth #else 6827fcf5ef2aSThomas Huth TCGv t0; 6828fcf5ef2aSThomas Huth 6829fcf5ef2aSThomas Huth CHK_SV; 6830fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6831fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6832fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6833fcf5ef2aSThomas Huth tcg_temp_free(t0); 6834fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6835fcf5ef2aSThomas Huth } 6836fcf5ef2aSThomas Huth 6837fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6838fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6839fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6840fcf5ef2aSThomas Huth { 6841fcf5ef2aSThomas Huth TCGv t0, t1; 6842fcf5ef2aSThomas Huth 6843fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6844fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6845fcf5ef2aSThomas Huth 6846fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6847fcf5ef2aSThomas Huth case 0x05: 6848fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6849fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6850fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6851fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6852fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6853fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6854fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6855fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6856fcf5ef2aSThomas Huth break; 6857fcf5ef2aSThomas Huth case 0x04: 6858fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6859fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6860fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6861fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6862fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6863fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6864fcf5ef2aSThomas Huth break; 6865fcf5ef2aSThomas Huth case 0x01: 6866fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6867fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6868fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6869fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6870fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6871fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6872fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6873fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6874fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6875fcf5ef2aSThomas Huth break; 6876fcf5ef2aSThomas Huth case 0x00: 6877fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6878fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6879fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6880fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6881fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6882fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6883fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6884fcf5ef2aSThomas Huth break; 6885fcf5ef2aSThomas Huth case 0x0D: 6886fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6887fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6888fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6889fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6890fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6891fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6892fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6893fcf5ef2aSThomas Huth break; 6894fcf5ef2aSThomas Huth case 0x0C: 6895fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6896fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6897fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6898fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6899fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6900fcf5ef2aSThomas Huth break; 6901fcf5ef2aSThomas Huth } 6902fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6903fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6904fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6905fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6906fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6907fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6908fcf5ef2aSThomas Huth } else { 6909fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6910fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6911fcf5ef2aSThomas Huth } 6912fcf5ef2aSThomas Huth 6913fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6914fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6915fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6916fcf5ef2aSThomas Huth 6917fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6918fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6919fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6920fcf5ef2aSThomas Huth } 6921fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6922fcf5ef2aSThomas Huth /* Signed */ 6923fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6924fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6925fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6926fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6927fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6928fcf5ef2aSThomas Huth /* Saturate */ 6929fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6930fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6931fcf5ef2aSThomas Huth } 6932fcf5ef2aSThomas Huth } else { 6933fcf5ef2aSThomas Huth /* Unsigned */ 6934fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6935fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6936fcf5ef2aSThomas Huth /* Saturate */ 6937fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6938fcf5ef2aSThomas Huth } 6939fcf5ef2aSThomas Huth } 6940fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6941fcf5ef2aSThomas Huth /* Check overflow */ 6942fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6943fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6944fcf5ef2aSThomas Huth } 6945fcf5ef2aSThomas Huth gen_set_label(l1); 6946fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6947fcf5ef2aSThomas Huth } 6948fcf5ef2aSThomas Huth } else { 6949fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6950fcf5ef2aSThomas Huth } 6951fcf5ef2aSThomas Huth tcg_temp_free(t0); 6952fcf5ef2aSThomas Huth tcg_temp_free(t1); 6953fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6954fcf5ef2aSThomas Huth /* Update Rc0 */ 6955fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6956fcf5ef2aSThomas Huth } 6957fcf5ef2aSThomas Huth } 6958fcf5ef2aSThomas Huth 6959fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6960fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6961fcf5ef2aSThomas Huth { \ 6962fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6963fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6964fcf5ef2aSThomas Huth } 6965fcf5ef2aSThomas Huth 6966fcf5ef2aSThomas Huth /* macchw - macchw. */ 6967fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6968fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6969fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6970fcf5ef2aSThomas Huth /* macchws - macchws. */ 6971fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6972fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6973fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6974fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6975fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6976fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6977fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6978fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6979fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6980fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6981fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6982fcf5ef2aSThomas Huth /* machhw - machhw. */ 6983fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6984fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6985fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6986fcf5ef2aSThomas Huth /* machhws - machhws. */ 6987fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6988fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6989fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6990fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6991fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6992fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6993fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6994fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6995fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6996fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6997fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6998fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6999fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 7000fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 7001fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 7002fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 7003fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 7004fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 7005fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 7006fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 7007fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 7008fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 7009fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 7010fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 7011fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 7012fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 7013fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 7014fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 7015fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 7016fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 7017fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 7018fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 7019fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 7020fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 7021fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 7022fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 7023fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 7024fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 7025fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 7026fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 7027fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 7028fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 7029fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 7030fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 7031fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 7032fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 7033fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 7034fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 7035fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 7036fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 7037fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 7038fcf5ef2aSThomas Huth 7039fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 7040fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 7041fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 7042fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 7043fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 7044fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 7045fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7046fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 7047fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7048fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 7049fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7050fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 7051fcf5ef2aSThomas Huth 7052fcf5ef2aSThomas Huth /* mfdcr */ 7053fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 7054fcf5ef2aSThomas Huth { 7055fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7056fcf5ef2aSThomas Huth GEN_PRIV; 7057fcf5ef2aSThomas Huth #else 7058fcf5ef2aSThomas Huth TCGv dcrn; 7059fcf5ef2aSThomas Huth 7060fcf5ef2aSThomas Huth CHK_SV; 7061fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7062fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 7063fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7064fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7065fcf5ef2aSThomas Huth } 7066fcf5ef2aSThomas Huth 7067fcf5ef2aSThomas Huth /* mtdcr */ 7068fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 7069fcf5ef2aSThomas Huth { 7070fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7071fcf5ef2aSThomas Huth GEN_PRIV; 7072fcf5ef2aSThomas Huth #else 7073fcf5ef2aSThomas Huth TCGv dcrn; 7074fcf5ef2aSThomas Huth 7075fcf5ef2aSThomas Huth CHK_SV; 7076fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7077fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 7078fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7079fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7080fcf5ef2aSThomas Huth } 7081fcf5ef2aSThomas Huth 7082fcf5ef2aSThomas Huth /* mfdcrx */ 7083fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7084fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 7085fcf5ef2aSThomas Huth { 7086fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7087fcf5ef2aSThomas Huth GEN_PRIV; 7088fcf5ef2aSThomas Huth #else 7089fcf5ef2aSThomas Huth CHK_SV; 7090fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7091fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7092fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7093fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7094fcf5ef2aSThomas Huth } 7095fcf5ef2aSThomas Huth 7096fcf5ef2aSThomas Huth /* mtdcrx */ 7097fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7098fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 7099fcf5ef2aSThomas Huth { 7100fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7101fcf5ef2aSThomas Huth GEN_PRIV; 7102fcf5ef2aSThomas Huth #else 7103fcf5ef2aSThomas Huth CHK_SV; 7104fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7105fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7106fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7107fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7108fcf5ef2aSThomas Huth } 7109fcf5ef2aSThomas Huth 7110fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 7111fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 7112fcf5ef2aSThomas Huth { 7113fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7114fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7115fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7116fcf5ef2aSThomas Huth } 7117fcf5ef2aSThomas Huth 7118fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 7119fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 7120fcf5ef2aSThomas Huth { 7121fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7122fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7123fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7124fcf5ef2aSThomas Huth } 7125fcf5ef2aSThomas Huth 7126fcf5ef2aSThomas Huth /* dccci */ 7127fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 7128fcf5ef2aSThomas Huth { 7129fcf5ef2aSThomas Huth CHK_SV; 7130fcf5ef2aSThomas Huth /* interpreted as no-op */ 7131fcf5ef2aSThomas Huth } 7132fcf5ef2aSThomas Huth 7133fcf5ef2aSThomas Huth /* dcread */ 7134fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 7135fcf5ef2aSThomas Huth { 7136fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7137fcf5ef2aSThomas Huth GEN_PRIV; 7138fcf5ef2aSThomas Huth #else 7139fcf5ef2aSThomas Huth TCGv EA, val; 7140fcf5ef2aSThomas Huth 7141fcf5ef2aSThomas Huth CHK_SV; 7142fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 7143fcf5ef2aSThomas Huth EA = tcg_temp_new(); 7144fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 7145fcf5ef2aSThomas Huth val = tcg_temp_new(); 7146fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 7147fcf5ef2aSThomas Huth tcg_temp_free(val); 7148fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 7149fcf5ef2aSThomas Huth tcg_temp_free(EA); 7150fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7151fcf5ef2aSThomas Huth } 7152fcf5ef2aSThomas Huth 7153fcf5ef2aSThomas Huth /* icbt */ 7154fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 7155fcf5ef2aSThomas Huth { 7156efe843d8SDavid Gibson /* 7157efe843d8SDavid Gibson * interpreted as no-op 7158efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7159efe843d8SDavid Gibson * does not generate any exception 7160fcf5ef2aSThomas Huth */ 7161fcf5ef2aSThomas Huth } 7162fcf5ef2aSThomas Huth 7163fcf5ef2aSThomas Huth /* iccci */ 7164fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 7165fcf5ef2aSThomas Huth { 7166fcf5ef2aSThomas Huth CHK_SV; 7167fcf5ef2aSThomas Huth /* interpreted as no-op */ 7168fcf5ef2aSThomas Huth } 7169fcf5ef2aSThomas Huth 7170fcf5ef2aSThomas Huth /* icread */ 7171fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 7172fcf5ef2aSThomas Huth { 7173fcf5ef2aSThomas Huth CHK_SV; 7174fcf5ef2aSThomas Huth /* interpreted as no-op */ 7175fcf5ef2aSThomas Huth } 7176fcf5ef2aSThomas Huth 7177fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 7178fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 7179fcf5ef2aSThomas Huth { 7180fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7181fcf5ef2aSThomas Huth GEN_PRIV; 7182fcf5ef2aSThomas Huth #else 7183fcf5ef2aSThomas Huth CHK_SV; 7184fcf5ef2aSThomas Huth /* Restore CPU state */ 7185fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 718659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7187fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7188fcf5ef2aSThomas Huth } 7189fcf5ef2aSThomas Huth 7190fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 7191fcf5ef2aSThomas Huth { 7192fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7193fcf5ef2aSThomas Huth GEN_PRIV; 7194fcf5ef2aSThomas Huth #else 7195fcf5ef2aSThomas Huth CHK_SV; 7196fcf5ef2aSThomas Huth /* Restore CPU state */ 7197fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 719859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7199fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7200fcf5ef2aSThomas Huth } 7201fcf5ef2aSThomas Huth 7202fcf5ef2aSThomas Huth /* BookE specific */ 7203fcf5ef2aSThomas Huth 7204fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7205fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 7206fcf5ef2aSThomas Huth { 7207fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7208fcf5ef2aSThomas Huth GEN_PRIV; 7209fcf5ef2aSThomas Huth #else 7210fcf5ef2aSThomas Huth CHK_SV; 7211fcf5ef2aSThomas Huth /* Restore CPU state */ 7212fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 721359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7214fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7215fcf5ef2aSThomas Huth } 7216fcf5ef2aSThomas Huth 7217fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7218fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 7219fcf5ef2aSThomas Huth { 7220fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7221fcf5ef2aSThomas Huth GEN_PRIV; 7222fcf5ef2aSThomas Huth #else 7223fcf5ef2aSThomas Huth CHK_SV; 7224fcf5ef2aSThomas Huth /* Restore CPU state */ 7225fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 722659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7227fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7228fcf5ef2aSThomas Huth } 7229fcf5ef2aSThomas Huth 7230fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7231fcf5ef2aSThomas Huth 7232fcf5ef2aSThomas Huth /* tlbre */ 7233fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7234fcf5ef2aSThomas Huth { 7235fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7236fcf5ef2aSThomas Huth GEN_PRIV; 7237fcf5ef2aSThomas Huth #else 7238fcf5ef2aSThomas Huth CHK_SV; 7239fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7240fcf5ef2aSThomas Huth case 0: 7241fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7242fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7243fcf5ef2aSThomas Huth break; 7244fcf5ef2aSThomas Huth case 1: 7245fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7246fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7247fcf5ef2aSThomas Huth break; 7248fcf5ef2aSThomas Huth default: 7249fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7250fcf5ef2aSThomas Huth break; 7251fcf5ef2aSThomas Huth } 7252fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7253fcf5ef2aSThomas Huth } 7254fcf5ef2aSThomas Huth 7255fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7256fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7257fcf5ef2aSThomas Huth { 7258fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7259fcf5ef2aSThomas Huth GEN_PRIV; 7260fcf5ef2aSThomas Huth #else 7261fcf5ef2aSThomas Huth TCGv t0; 7262fcf5ef2aSThomas Huth 7263fcf5ef2aSThomas Huth CHK_SV; 7264fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7265fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7266fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7267fcf5ef2aSThomas Huth tcg_temp_free(t0); 7268fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7269fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7270fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7271fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7272fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7273fcf5ef2aSThomas Huth gen_set_label(l1); 7274fcf5ef2aSThomas Huth } 7275fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7276fcf5ef2aSThomas Huth } 7277fcf5ef2aSThomas Huth 7278fcf5ef2aSThomas Huth /* tlbwe */ 7279fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7280fcf5ef2aSThomas Huth { 7281fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7282fcf5ef2aSThomas Huth GEN_PRIV; 7283fcf5ef2aSThomas Huth #else 7284fcf5ef2aSThomas Huth CHK_SV; 7285fcf5ef2aSThomas Huth 7286fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7287fcf5ef2aSThomas Huth case 0: 7288fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7289fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7290fcf5ef2aSThomas Huth break; 7291fcf5ef2aSThomas Huth case 1: 7292fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7293fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7294fcf5ef2aSThomas Huth break; 7295fcf5ef2aSThomas Huth default: 7296fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7297fcf5ef2aSThomas Huth break; 7298fcf5ef2aSThomas Huth } 7299fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7300fcf5ef2aSThomas Huth } 7301fcf5ef2aSThomas Huth 7302fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7303fcf5ef2aSThomas Huth 7304fcf5ef2aSThomas Huth /* tlbre */ 7305fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7306fcf5ef2aSThomas Huth { 7307fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7308fcf5ef2aSThomas Huth GEN_PRIV; 7309fcf5ef2aSThomas Huth #else 7310fcf5ef2aSThomas Huth CHK_SV; 7311fcf5ef2aSThomas Huth 7312fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7313fcf5ef2aSThomas Huth case 0: 7314fcf5ef2aSThomas Huth case 1: 7315fcf5ef2aSThomas Huth case 2: 7316fcf5ef2aSThomas Huth { 7317fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7318fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7319fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7320fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7321fcf5ef2aSThomas Huth } 7322fcf5ef2aSThomas Huth break; 7323fcf5ef2aSThomas Huth default: 7324fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7325fcf5ef2aSThomas Huth break; 7326fcf5ef2aSThomas Huth } 7327fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7328fcf5ef2aSThomas Huth } 7329fcf5ef2aSThomas Huth 7330fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7331fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7332fcf5ef2aSThomas Huth { 7333fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7334fcf5ef2aSThomas Huth GEN_PRIV; 7335fcf5ef2aSThomas Huth #else 7336fcf5ef2aSThomas Huth TCGv t0; 7337fcf5ef2aSThomas Huth 7338fcf5ef2aSThomas Huth CHK_SV; 7339fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7340fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7341fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7342fcf5ef2aSThomas Huth tcg_temp_free(t0); 7343fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7344fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7345fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7346fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7347fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7348fcf5ef2aSThomas Huth gen_set_label(l1); 7349fcf5ef2aSThomas Huth } 7350fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7351fcf5ef2aSThomas Huth } 7352fcf5ef2aSThomas Huth 7353fcf5ef2aSThomas Huth /* tlbwe */ 7354fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7355fcf5ef2aSThomas Huth { 7356fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7357fcf5ef2aSThomas Huth GEN_PRIV; 7358fcf5ef2aSThomas Huth #else 7359fcf5ef2aSThomas Huth CHK_SV; 7360fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7361fcf5ef2aSThomas Huth case 0: 7362fcf5ef2aSThomas Huth case 1: 7363fcf5ef2aSThomas Huth case 2: 7364fcf5ef2aSThomas Huth { 7365fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7366fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7367fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7368fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7369fcf5ef2aSThomas Huth } 7370fcf5ef2aSThomas Huth break; 7371fcf5ef2aSThomas Huth default: 7372fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7373fcf5ef2aSThomas Huth break; 7374fcf5ef2aSThomas Huth } 7375fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7376fcf5ef2aSThomas Huth } 7377fcf5ef2aSThomas Huth 7378fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7379fcf5ef2aSThomas Huth 7380fcf5ef2aSThomas Huth /* tlbre */ 7381fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7382fcf5ef2aSThomas Huth { 7383fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7384fcf5ef2aSThomas Huth GEN_PRIV; 7385fcf5ef2aSThomas Huth #else 7386fcf5ef2aSThomas Huth CHK_SV; 7387fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7388fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7389fcf5ef2aSThomas Huth } 7390fcf5ef2aSThomas Huth 7391fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7392fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7393fcf5ef2aSThomas Huth { 7394fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7395fcf5ef2aSThomas Huth GEN_PRIV; 7396fcf5ef2aSThomas Huth #else 7397fcf5ef2aSThomas Huth TCGv t0; 7398fcf5ef2aSThomas Huth 7399fcf5ef2aSThomas Huth CHK_SV; 7400fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7401fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7402fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7403fcf5ef2aSThomas Huth } else { 7404fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7405fcf5ef2aSThomas Huth } 7406fcf5ef2aSThomas Huth 7407fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7408fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7409fcf5ef2aSThomas Huth tcg_temp_free(t0); 7410fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7411fcf5ef2aSThomas Huth } 7412fcf5ef2aSThomas Huth 7413fcf5ef2aSThomas Huth /* tlbwe */ 7414fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7415fcf5ef2aSThomas Huth { 7416fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7417fcf5ef2aSThomas Huth GEN_PRIV; 7418fcf5ef2aSThomas Huth #else 7419fcf5ef2aSThomas Huth CHK_SV; 7420fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7421fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7422fcf5ef2aSThomas Huth } 7423fcf5ef2aSThomas Huth 7424fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7425fcf5ef2aSThomas Huth { 7426fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7427fcf5ef2aSThomas Huth GEN_PRIV; 7428fcf5ef2aSThomas Huth #else 7429fcf5ef2aSThomas Huth TCGv t0; 7430fcf5ef2aSThomas Huth 7431fcf5ef2aSThomas Huth CHK_SV; 7432fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7433fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7434fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7435fcf5ef2aSThomas Huth tcg_temp_free(t0); 7436fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7437fcf5ef2aSThomas Huth } 7438fcf5ef2aSThomas Huth 7439fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7440fcf5ef2aSThomas Huth { 7441fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7442fcf5ef2aSThomas Huth GEN_PRIV; 7443fcf5ef2aSThomas Huth #else 7444fcf5ef2aSThomas Huth TCGv t0; 7445fcf5ef2aSThomas Huth 7446fcf5ef2aSThomas Huth CHK_SV; 7447fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7448fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7449fcf5ef2aSThomas Huth 7450fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7451fcf5ef2aSThomas Huth case 0: 7452fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7453fcf5ef2aSThomas Huth break; 7454fcf5ef2aSThomas Huth case 1: 7455fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7456fcf5ef2aSThomas Huth break; 7457fcf5ef2aSThomas Huth case 3: 7458fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7459fcf5ef2aSThomas Huth break; 7460fcf5ef2aSThomas Huth default: 7461fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7462fcf5ef2aSThomas Huth break; 7463fcf5ef2aSThomas Huth } 7464fcf5ef2aSThomas Huth 7465fcf5ef2aSThomas Huth tcg_temp_free(t0); 7466fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7467fcf5ef2aSThomas Huth } 7468fcf5ef2aSThomas Huth 7469fcf5ef2aSThomas Huth 7470fcf5ef2aSThomas Huth /* wrtee */ 7471fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7472fcf5ef2aSThomas Huth { 7473fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7474fcf5ef2aSThomas Huth GEN_PRIV; 7475fcf5ef2aSThomas Huth #else 7476fcf5ef2aSThomas Huth TCGv t0; 7477fcf5ef2aSThomas Huth 7478fcf5ef2aSThomas Huth CHK_SV; 7479fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7480fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7481fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7482fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7483fcf5ef2aSThomas Huth tcg_temp_free(t0); 7484efe843d8SDavid Gibson /* 7485efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7486efe843d8SDavid Gibson * just set msr_ee to 1 7487fcf5ef2aSThomas Huth */ 7488*d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7489fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7490fcf5ef2aSThomas Huth } 7491fcf5ef2aSThomas Huth 7492fcf5ef2aSThomas Huth /* wrteei */ 7493fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7494fcf5ef2aSThomas Huth { 7495fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7496fcf5ef2aSThomas Huth GEN_PRIV; 7497fcf5ef2aSThomas Huth #else 7498fcf5ef2aSThomas Huth CHK_SV; 7499fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7500fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7501fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7502*d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7503fcf5ef2aSThomas Huth } else { 7504fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7505fcf5ef2aSThomas Huth } 7506fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7507fcf5ef2aSThomas Huth } 7508fcf5ef2aSThomas Huth 7509fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7510fcf5ef2aSThomas Huth 7511fcf5ef2aSThomas Huth /* dlmzb */ 7512fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7513fcf5ef2aSThomas Huth { 7514fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7515fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7516fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7517fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7518fcf5ef2aSThomas Huth } 7519fcf5ef2aSThomas Huth 7520fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7521fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7522fcf5ef2aSThomas Huth { 7523fcf5ef2aSThomas Huth /* interpreted as no-op */ 7524fcf5ef2aSThomas Huth } 7525fcf5ef2aSThomas Huth 7526fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7527fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7528fcf5ef2aSThomas Huth { 752927a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 753027a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 753127a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 753227a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 753327a3ea7eSBALATON Zoltan } 753427a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7535fcf5ef2aSThomas Huth } 7536fcf5ef2aSThomas Huth 7537fcf5ef2aSThomas Huth /* icbt */ 7538fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7539fcf5ef2aSThomas Huth { 7540efe843d8SDavid Gibson /* 7541efe843d8SDavid Gibson * interpreted as no-op 7542efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7543efe843d8SDavid Gibson * does not generate any exception 7544fcf5ef2aSThomas Huth */ 7545fcf5ef2aSThomas Huth } 7546fcf5ef2aSThomas Huth 7547fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7548fcf5ef2aSThomas Huth 7549fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7550fcf5ef2aSThomas Huth { 7551fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7552fcf5ef2aSThomas Huth GEN_PRIV; 7553fcf5ef2aSThomas Huth #else 7554ebca5e6dSCédric Le Goater CHK_HV; 7555d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 75567af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 75577af1e7b0SCédric Le Goater } else { 7558fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 75597af1e7b0SCédric Le Goater } 7560fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7561fcf5ef2aSThomas Huth } 7562fcf5ef2aSThomas Huth 7563fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7564fcf5ef2aSThomas Huth { 7565fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7566fcf5ef2aSThomas Huth GEN_PRIV; 7567fcf5ef2aSThomas Huth #else 7568ebca5e6dSCédric Le Goater CHK_HV; 7569d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 75707af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 75717af1e7b0SCédric Le Goater } else { 7572fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 75737af1e7b0SCédric Le Goater } 7574fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7575fcf5ef2aSThomas Huth } 7576fcf5ef2aSThomas Huth 75775ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 75785ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 75795ba7ba1dSCédric Le Goater { 75805ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 75815ba7ba1dSCédric Le Goater GEN_PRIV; 75825ba7ba1dSCédric Le Goater #else 75835ba7ba1dSCédric Le Goater CHK_SV; 75845ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 75855ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 75865ba7ba1dSCédric Le Goater } 75875ba7ba1dSCédric Le Goater 75885ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 75895ba7ba1dSCédric Le Goater { 75905ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 75915ba7ba1dSCédric Le Goater GEN_PRIV; 75925ba7ba1dSCédric Le Goater #else 75935ba7ba1dSCédric Le Goater CHK_SV; 75945ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 75955ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 75965ba7ba1dSCédric Le Goater } 75975ba7ba1dSCédric Le Goater #endif 75985ba7ba1dSCédric Le Goater 75997af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 76007af1e7b0SCédric Le Goater { 76017af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 76027af1e7b0SCédric Le Goater GEN_PRIV; 76037af1e7b0SCédric Le Goater #else 76047af1e7b0SCédric Le Goater CHK_HV; 76057af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 76067af1e7b0SCédric Le Goater /* interpreted as no-op */ 76077af1e7b0SCédric Le Goater } 7608fcf5ef2aSThomas Huth 7609fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7610fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7611fcf5ef2aSThomas Huth { 7612fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7613fcf5ef2aSThomas Huth 7614fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7615fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7616fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7617fcf5ef2aSThomas Huth } 7618fcf5ef2aSThomas Huth 7619fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7620fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7621fcf5ef2aSThomas Huth { 7622fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7623fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7624fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7625fcf5ef2aSThomas Huth 7626fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7627fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7628fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7629fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7630fcf5ef2aSThomas Huth } else { 7631fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7632fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7633fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7634fcf5ef2aSThomas Huth } 7635fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7636fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7637fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7638fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7639fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7640fcf5ef2aSThomas Huth } 7641fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7642fcf5ef2aSThomas Huth 7643fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7644fcf5ef2aSThomas Huth { 7645fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7646fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7647fcf5ef2aSThomas Huth return; 7648fcf5ef2aSThomas Huth } 7649fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7650fcf5ef2aSThomas Huth } 7651fcf5ef2aSThomas Huth 7652fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7653fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7654fcf5ef2aSThomas Huth { \ 7655fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7656fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7657fcf5ef2aSThomas Huth return; \ 7658fcf5ef2aSThomas Huth } \ 7659efe843d8SDavid Gibson /* \ 7660efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7661fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7662fcf5ef2aSThomas Huth * \ 7663fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7664fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7665fcf5ef2aSThomas Huth */ \ 7666fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7667fcf5ef2aSThomas Huth } 7668fcf5ef2aSThomas Huth 7669fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7670fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7671fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7672fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7673fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7674fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7675fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7676efe843d8SDavid Gibson 7677b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7678b8b4576eSSuraj Jitindar Singh { 7679efe843d8SDavid Gibson /* Do Nothing */ 7680b8b4576eSSuraj Jitindar Singh } 7681fcf5ef2aSThomas Huth 768280b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 768380b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 768480b8c1eeSNikunj A Dadhania { \ 7685efe843d8SDavid Gibson /* \ 7686efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7687efe843d8SDavid Gibson * implementation of the copy paste facility \ 768880b8c1eeSNikunj A Dadhania */ \ 768980b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 769080b8c1eeSNikunj A Dadhania } 769180b8c1eeSNikunj A Dadhania 769280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 769380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 769480b8c1eeSNikunj A Dadhania 7695fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7696fcf5ef2aSThomas Huth { 7697fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7698fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7699fcf5ef2aSThomas Huth return; 7700fcf5ef2aSThomas Huth } 7701efe843d8SDavid Gibson /* 7702efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7703efe843d8SDavid Gibson * simple: 7704fcf5ef2aSThomas Huth * 7705fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7706fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7707fcf5ef2aSThomas Huth */ 7708fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7709fcf5ef2aSThomas Huth } 7710fcf5ef2aSThomas Huth 7711fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7712fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7713fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7714fcf5ef2aSThomas Huth { \ 7715fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7716fcf5ef2aSThomas Huth } 7717fcf5ef2aSThomas Huth 7718fcf5ef2aSThomas Huth #else 7719fcf5ef2aSThomas Huth 7720fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7721fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7722fcf5ef2aSThomas Huth { \ 7723fcf5ef2aSThomas Huth CHK_SV; \ 7724fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7725fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7726fcf5ef2aSThomas Huth return; \ 7727fcf5ef2aSThomas Huth } \ 7728efe843d8SDavid Gibson /* \ 7729efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7730fcf5ef2aSThomas Huth * simple: \ 7731fcf5ef2aSThomas Huth * \ 7732fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7733fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7734fcf5ef2aSThomas Huth */ \ 7735fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7736fcf5ef2aSThomas Huth } 7737fcf5ef2aSThomas Huth 7738fcf5ef2aSThomas Huth #endif 7739fcf5ef2aSThomas Huth 7740fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7741fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7742fcf5ef2aSThomas Huth 77431a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 77441a404c91SMark Cave-Ayland { 7745e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 77461a404c91SMark Cave-Ayland } 77471a404c91SMark Cave-Ayland 77481a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 77491a404c91SMark Cave-Ayland { 7750e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 77511a404c91SMark Cave-Ayland } 77521a404c91SMark Cave-Ayland 7753c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7754c4a18dbfSMark Cave-Ayland { 775537da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7756c4a18dbfSMark Cave-Ayland } 7757c4a18dbfSMark Cave-Ayland 7758c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7759c4a18dbfSMark Cave-Ayland { 776037da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7761c4a18dbfSMark Cave-Ayland } 7762c4a18dbfSMark Cave-Ayland 7763139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7764fcf5ef2aSThomas Huth 7765139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7766fcf5ef2aSThomas Huth 7767139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7768fcf5ef2aSThomas Huth 7769139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7770fcf5ef2aSThomas Huth 7771139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7772fcf5ef2aSThomas Huth 77735cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 77745cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 77755cb091a4SNikunj A Dadhania { 77765cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 77775cb091a4SNikunj A Dadhania case 0: /* lfdp */ 77785cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 77795cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 77805cb091a4SNikunj A Dadhania } 77815cb091a4SNikunj A Dadhania break; 77825cb091a4SNikunj A Dadhania case 2: /* lxsd */ 77835cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 77845cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 77855cb091a4SNikunj A Dadhania } 77865cb091a4SNikunj A Dadhania break; 77875cb091a4SNikunj A Dadhania case 3: /* lxssp */ 77885cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 77895cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 77905cb091a4SNikunj A Dadhania } 77915cb091a4SNikunj A Dadhania break; 77925cb091a4SNikunj A Dadhania } 77935cb091a4SNikunj A Dadhania return gen_invalid(ctx); 77945cb091a4SNikunj A Dadhania } 77955cb091a4SNikunj A Dadhania 7796d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7797e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7798e3001664SNikunj A Dadhania { 7799e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7800e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7801e3001664SNikunj A Dadhania case 1: /* lxv */ 7802d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7803d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7804d59ba583SNikunj A Dadhania } 7805e3001664SNikunj A Dadhania break; 7806e3001664SNikunj A Dadhania case 5: /* stxv */ 7807d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7808d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7809d59ba583SNikunj A Dadhania } 7810e3001664SNikunj A Dadhania break; 7811e3001664SNikunj A Dadhania } 7812e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7813e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7814e3001664SNikunj A Dadhania case 0: /* stfdp */ 7815e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7816e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7817e3001664SNikunj A Dadhania } 7818e3001664SNikunj A Dadhania break; 7819e3001664SNikunj A Dadhania case 2: /* stxsd */ 7820e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7821e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7822e3001664SNikunj A Dadhania } 7823e3001664SNikunj A Dadhania break; 7824e3001664SNikunj A Dadhania case 3: /* stxssp */ 7825e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7826e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7827e3001664SNikunj A Dadhania } 7828e3001664SNikunj A Dadhania break; 7829e3001664SNikunj A Dadhania } 7830e3001664SNikunj A Dadhania } 7831e3001664SNikunj A Dadhania return gen_invalid(ctx); 7832e3001664SNikunj A Dadhania } 7833e3001664SNikunj A Dadhania 78349d69cfa2SLijun Pan #if defined(TARGET_PPC64) 78359d69cfa2SLijun Pan /* brd */ 78369d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 78379d69cfa2SLijun Pan { 78389d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 78399d69cfa2SLijun Pan } 78409d69cfa2SLijun Pan 78419d69cfa2SLijun Pan /* brw */ 78429d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 78439d69cfa2SLijun Pan { 78449d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 78459d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 78469d69cfa2SLijun Pan 78479d69cfa2SLijun Pan } 78489d69cfa2SLijun Pan 78499d69cfa2SLijun Pan /* brh */ 78509d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 78519d69cfa2SLijun Pan { 78529d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 78539d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 78549d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 78559d69cfa2SLijun Pan 78569d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 78579d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 78589d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 78599d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 78609d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 78619d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 78629d69cfa2SLijun Pan 78639d69cfa2SLijun Pan tcg_temp_free_i64(t0); 78649d69cfa2SLijun Pan tcg_temp_free_i64(t1); 78659d69cfa2SLijun Pan tcg_temp_free_i64(t2); 78669d69cfa2SLijun Pan } 78679d69cfa2SLijun Pan #endif 78689d69cfa2SLijun Pan 7869fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 78709d69cfa2SLijun Pan #if defined(TARGET_PPC64) 78719d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 78729d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 78739d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 78749d69cfa2SLijun Pan #endif 7875fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7876fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7877fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7878fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7879fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7880fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7881fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7882fcf5ef2aSThomas Huth #endif 7883fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7884fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7885fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7886fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7887fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7888fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7889fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7890fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7891fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7892fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7893fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7894fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7895fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7896fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7897fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7898fcf5ef2aSThomas Huth #endif 7899fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7900fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7901fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7902fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7903fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7904fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7905fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 790680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7907b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 790880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7909fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7910fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7911fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7912fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7913fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7914fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7915fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7916fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7917fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7918fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7919fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7920fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7921fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7922fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7923fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7924fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7925fcf5ef2aSThomas Huth #endif 7926fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7927fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7928fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7929fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7930fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7931fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7932fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7933fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7934fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7935fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7936fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7937fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7938fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7939fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7940fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7941fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7942fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7943fcf5ef2aSThomas Huth #endif 7944fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7945fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 7946fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7947fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7948fcf5ef2aSThomas Huth #endif 79495cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 79505cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7951d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7952e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7953fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7954fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7955fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7956fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7957fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7958fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7959c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7960fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7961fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7962fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7963fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7964a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7965a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7966fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7967fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7968fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7969fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7970a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7971a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7972fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7973fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7974fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7975fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7976fcf5ef2aSThomas Huth #endif 7977fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7978fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7979c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7980fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7981fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7982fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7983fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7984fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7985fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7986fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7987fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7988fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 79893c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 79903c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 79913c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 79923c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 79933c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 79943c89b8d6SNicholas Piggin #endif 7995cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7996fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7997fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7998fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7999fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8000fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 8001fcf5ef2aSThomas Huth #endif 80023c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 80033c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 80043c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 8005fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 8006fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8007fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8008fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 8009fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 8010fcf5ef2aSThomas Huth #endif 8011fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 8012fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 8013fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 8014fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 8015fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 8016fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 8017fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8018fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 8019fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 8020b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 8021fcf5ef2aSThomas Huth #endif 8022fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 8023fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 8024fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 802550728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8026fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 8027fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 802850728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8029fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 803050728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8031fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 803250728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8033fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 8034fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 803550728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8036fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 803799d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 8038fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 8039fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 804050728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8041fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 8042fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 8043fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 8044fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 8045fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 8046fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8047fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 8048fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 8049fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8050fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 8051fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 8052fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8053fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 8054fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 8055fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 8056fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 8057fcf5ef2aSThomas Huth #endif 8058fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 8059efe843d8SDavid Gibson /* 8060efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 8061efe843d8SDavid Gibson * different ISA versions 8062efe843d8SDavid Gibson */ 8063fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 8064fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 8065c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 8066c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 8067fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 8068fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8069fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 8070fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 8071a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 807262d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8073fcf5ef2aSThomas Huth #endif 8074fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 8075fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 8076fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 8077fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 8078fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 8079fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 8080fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 8081fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 8082fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 8083fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 8084fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 8085fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8086fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 8087fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 8088fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 8089fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 8090fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 8091fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 8092fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 8093fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8094fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 8095fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 8096fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 8097fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 8098fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 8099fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 8100fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 8101fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 8102fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 8103fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 8104fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 8105fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 8106fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 8107fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 8108fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 8109fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 8110fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 8111fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 8112fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 8113fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 8114fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 8115fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 8116fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 8117fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 8118fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 8119fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 8120fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 8121fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 8122fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 8123fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8124fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8125fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 8126fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 8127fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8128fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8129fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 8130fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 8131fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 8132fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 8133fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 8134fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 8135fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 8136fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 8137fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 8138fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 8139fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 8140fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 8141fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 8142fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 8143fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 8144fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 8145fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 8146fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 8147fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 8148fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 8149fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 8150fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 8151fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 8152fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 8153fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 8154fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 8155fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8156fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 8157fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8158fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 8159fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8160fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 8161fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8162fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 8163fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8164fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 8165fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 8166fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 8167fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 81687af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 81697af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 8170fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8171fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8172fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8173fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8174fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 817527a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8176fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8177fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 81780c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 81790c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8180fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8181fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8182fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8183fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8184fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8185fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8186fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8187fcf5ef2aSThomas Huth PPC2_ISA300), 8188fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 81895ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 81905ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 81915ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 81925ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8193fcf5ef2aSThomas Huth #endif 8194fcf5ef2aSThomas Huth 8195fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8196fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8197fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8198fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8199fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8200fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8201fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8202fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8203fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8204fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8205fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8206fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8207fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8208fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8209fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 82104c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8211fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8212fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8213fcf5ef2aSThomas Huth 8214fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8215fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8216fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8217fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8218fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8219fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8220fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8221fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8222fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8223fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8224fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8225fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8226fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8227fcf5ef2aSThomas Huth 8228fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8229fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8230fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8231fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8232fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8233fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8234fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8235fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8236fcf5ef2aSThomas Huth 8237fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8238fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8239fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8240fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8241fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8242fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8243fcf5ef2aSThomas Huth 8244fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8245fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8246fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8247fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8248fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8249fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8250fcf5ef2aSThomas Huth #endif 8251fcf5ef2aSThomas Huth 8252fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8253fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8254fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8255fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8256fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8257fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8258fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8259fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8260fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8261fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8262fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8263fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8264fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8265fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8266fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8267fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8268fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8269fcf5ef2aSThomas Huth 8270fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8271fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8272fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8273fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8274fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8275fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8276fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8277fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8278fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8279fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8280fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8281fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8282fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8283fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8284fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8285fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8286fcf5ef2aSThomas Huth #endif 8287fcf5ef2aSThomas Huth 8288fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8289fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8290fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8291fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8292fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8293fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8294fcf5ef2aSThomas Huth PPC_64B) 8295fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8296fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8297fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8298fcf5ef2aSThomas Huth PPC_64B), \ 8299fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8300fcf5ef2aSThomas Huth PPC_64B), \ 8301fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8302fcf5ef2aSThomas Huth PPC_64B) 8303fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8304fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8305fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8306fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8307fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8308fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8309fcf5ef2aSThomas Huth #endif 8310fcf5ef2aSThomas Huth 8311fcf5ef2aSThomas Huth #undef GEN_LD 8312fcf5ef2aSThomas Huth #undef GEN_LDU 8313fcf5ef2aSThomas Huth #undef GEN_LDUX 8314fcf5ef2aSThomas Huth #undef GEN_LDX_E 8315fcf5ef2aSThomas Huth #undef GEN_LDS 8316fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 8317fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8318fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 8319fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 8320fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 8321fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8322fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8323fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8324fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 8325fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 8326fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 8327fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 8328fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 8329fcf5ef2aSThomas Huth 8330fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 8331fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 8332fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 8333fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 8334fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8335fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 8336fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 8337fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 8338fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 8339fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8340fcf5ef2aSThomas Huth 8341fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8342fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8343fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8344fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8345fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8346fcf5ef2aSThomas Huth #endif 8347fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8348fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8349fcf5ef2aSThomas Huth 835050728199SRoman Kapl /* External PID based load */ 835150728199SRoman Kapl #undef GEN_LDEPX 835250728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 835350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 835450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 835550728199SRoman Kapl 835650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 835750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 835850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 835950728199SRoman Kapl #if defined(TARGET_PPC64) 836050728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 836150728199SRoman Kapl #endif 836250728199SRoman Kapl 8363fcf5ef2aSThomas Huth #undef GEN_ST 8364fcf5ef2aSThomas Huth #undef GEN_STU 8365fcf5ef2aSThomas Huth #undef GEN_STUX 8366fcf5ef2aSThomas Huth #undef GEN_STX_E 8367fcf5ef2aSThomas Huth #undef GEN_STS 8368fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8369fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8370fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8371fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8372fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8373fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8374fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 83750123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8376fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8377fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8378fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8379fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8380fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8381fcf5ef2aSThomas Huth 8382fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8383fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8384fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8385fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8386fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8387fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8388fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8389fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8390fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8391fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8392fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8393fcf5ef2aSThomas Huth #endif 8394fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8395fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8396fcf5ef2aSThomas Huth 839750728199SRoman Kapl #undef GEN_STEPX 839850728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 839950728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 840050728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 840150728199SRoman Kapl 840250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 840350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 840450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 840550728199SRoman Kapl #if defined(TARGET_PPC64) 840650728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 840750728199SRoman Kapl #endif 840850728199SRoman Kapl 8409fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8410fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8411fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8412fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8413fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8414fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8415fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8416fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8417fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8418fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8419fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8420fcf5ef2aSThomas Huth 8421fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8422fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8423fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8424fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8425fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8426fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8427fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8428fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8429fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8430fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8431fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8432fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8433fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8434fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8435fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8436fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8437fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8438fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8439fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8440fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8441fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8442fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8443fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8444fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8445fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8446fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8447fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8448fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8449fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8450fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8451fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8452fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8453fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8454fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8455fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8456fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8457fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8458fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8459fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8460fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8461fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8462fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8463fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8464fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8465fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8466fcf5ef2aSThomas Huth 8467fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8468fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8469fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8470fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8471fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8472fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8473fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8474fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8475fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8476fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8477fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8478fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8479fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8480fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8481fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8482fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8483fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8484fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8485fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8486fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8487fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8488fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8489fcf5ef2aSThomas Huth 8490139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8491fcf5ef2aSThomas Huth 8492139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8493fcf5ef2aSThomas Huth 8494139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8495fcf5ef2aSThomas Huth 8496139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8497fcf5ef2aSThomas Huth 8498139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8499fcf5ef2aSThomas Huth }; 8500fcf5ef2aSThomas Huth 85017468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 85027468e2c8SBruno Larsen (billionai) /* Opcode types */ 85037468e2c8SBruno Larsen (billionai) enum { 85047468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 85057468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 85067468e2c8SBruno Larsen (billionai) }; 85077468e2c8SBruno Larsen (billionai) 85087468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 85097468e2c8SBruno Larsen (billionai) 85107468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 85117468e2c8SBruno Larsen (billionai) { 85127468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 85137468e2c8SBruno Larsen (billionai) } 85147468e2c8SBruno Larsen (billionai) 85157468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 85167468e2c8SBruno Larsen (billionai) { 85177468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 85187468e2c8SBruno Larsen (billionai) } 85197468e2c8SBruno Larsen (billionai) 85207468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 85217468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 85227468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 85237468e2c8SBruno Larsen (billionai) { 85247468e2c8SBruno Larsen (billionai) int i; 85257468e2c8SBruno Larsen (billionai) 85267468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 85277468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 85287468e2c8SBruno Larsen (billionai) } 85297468e2c8SBruno Larsen (billionai) } 85307468e2c8SBruno Larsen (billionai) 85317468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 85327468e2c8SBruno Larsen (billionai) { 85337468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 85347468e2c8SBruno Larsen (billionai) 85357468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 85367468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 85377468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 85387468e2c8SBruno Larsen (billionai) 85397468e2c8SBruno Larsen (billionai) return 0; 85407468e2c8SBruno Larsen (billionai) } 85417468e2c8SBruno Larsen (billionai) 85427468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 85437468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 85447468e2c8SBruno Larsen (billionai) { 85457468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 85467468e2c8SBruno Larsen (billionai) return -1; 85477468e2c8SBruno Larsen (billionai) } 85487468e2c8SBruno Larsen (billionai) table[idx] = handler; 85497468e2c8SBruno Larsen (billionai) 85507468e2c8SBruno Larsen (billionai) return 0; 85517468e2c8SBruno Larsen (billionai) } 85527468e2c8SBruno Larsen (billionai) 85537468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 85547468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 85557468e2c8SBruno Larsen (billionai) { 85567468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 85577468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 85587468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 85597468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 85607468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 85617468e2c8SBruno Larsen (billionai) ppc_opcodes[idx]->oname, handler->oname); 85627468e2c8SBruno Larsen (billionai) #endif 85637468e2c8SBruno Larsen (billionai) return -1; 85647468e2c8SBruno Larsen (billionai) } 85657468e2c8SBruno Larsen (billionai) 85667468e2c8SBruno Larsen (billionai) return 0; 85677468e2c8SBruno Larsen (billionai) } 85687468e2c8SBruno Larsen (billionai) 85697468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 85707468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 85717468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 85727468e2c8SBruno Larsen (billionai) { 85737468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 85747468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 85757468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 85767468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 85777468e2c8SBruno Larsen (billionai) return -1; 85787468e2c8SBruno Larsen (billionai) } 85797468e2c8SBruno Larsen (billionai) } else { 85807468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 85817468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 85827468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 85837468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 85847468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 85857468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 85867468e2c8SBruno Larsen (billionai) #endif 85877468e2c8SBruno Larsen (billionai) return -1; 85887468e2c8SBruno Larsen (billionai) } 85897468e2c8SBruno Larsen (billionai) } 85907468e2c8SBruno Larsen (billionai) if (handler != NULL && 85917468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 85927468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 85937468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 85947468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 85957468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 85967468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 85977468e2c8SBruno Larsen (billionai) #endif 85987468e2c8SBruno Larsen (billionai) return -1; 85997468e2c8SBruno Larsen (billionai) } 86007468e2c8SBruno Larsen (billionai) 86017468e2c8SBruno Larsen (billionai) return 0; 86027468e2c8SBruno Larsen (billionai) } 86037468e2c8SBruno Larsen (billionai) 86047468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 86057468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86067468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86077468e2c8SBruno Larsen (billionai) { 86087468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 86097468e2c8SBruno Larsen (billionai) } 86107468e2c8SBruno Larsen (billionai) 86117468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 86127468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86137468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 86147468e2c8SBruno Larsen (billionai) { 86157468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 86167468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 86177468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 86187468e2c8SBruno Larsen (billionai) return -1; 86197468e2c8SBruno Larsen (billionai) } 86207468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 86217468e2c8SBruno Larsen (billionai) handler) < 0) { 86227468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 86237468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 86247468e2c8SBruno Larsen (billionai) return -1; 86257468e2c8SBruno Larsen (billionai) } 86267468e2c8SBruno Larsen (billionai) 86277468e2c8SBruno Larsen (billionai) return 0; 86287468e2c8SBruno Larsen (billionai) } 86297468e2c8SBruno Larsen (billionai) 86307468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 86317468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86327468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 86337468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86347468e2c8SBruno Larsen (billionai) { 86357468e2c8SBruno Larsen (billionai) opc_handler_t **table; 86367468e2c8SBruno Larsen (billionai) 86377468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 86387468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 86397468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 86407468e2c8SBruno Larsen (billionai) return -1; 86417468e2c8SBruno Larsen (billionai) } 86427468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 86437468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 86447468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 86457468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 86467468e2c8SBruno Larsen (billionai) return -1; 86477468e2c8SBruno Larsen (billionai) } 86487468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 86497468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 86507468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 86517468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 86527468e2c8SBruno Larsen (billionai) return -1; 86537468e2c8SBruno Larsen (billionai) } 86547468e2c8SBruno Larsen (billionai) return 0; 86557468e2c8SBruno Larsen (billionai) } 86567468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 86577468e2c8SBruno Larsen (billionai) { 86587468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 86597468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 86607468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 86617468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 86627468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 86637468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 86647468e2c8SBruno Larsen (billionai) return -1; 86657468e2c8SBruno Larsen (billionai) } 86667468e2c8SBruno Larsen (billionai) } else { 86677468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 86687468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 86697468e2c8SBruno Larsen (billionai) return -1; 86707468e2c8SBruno Larsen (billionai) } 86717468e2c8SBruno Larsen (billionai) } 86727468e2c8SBruno Larsen (billionai) } else { 86737468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 86747468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 86757468e2c8SBruno Larsen (billionai) return -1; 86767468e2c8SBruno Larsen (billionai) } 86777468e2c8SBruno Larsen (billionai) } 86787468e2c8SBruno Larsen (billionai) } else { 86797468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 86807468e2c8SBruno Larsen (billionai) return -1; 86817468e2c8SBruno Larsen (billionai) } 86827468e2c8SBruno Larsen (billionai) } 86837468e2c8SBruno Larsen (billionai) 86847468e2c8SBruno Larsen (billionai) return 0; 86857468e2c8SBruno Larsen (billionai) } 86867468e2c8SBruno Larsen (billionai) 86877468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 86887468e2c8SBruno Larsen (billionai) { 86897468e2c8SBruno Larsen (billionai) int i, count, tmp; 86907468e2c8SBruno Larsen (billionai) 86917468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 86927468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 86937468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 86947468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86957468e2c8SBruno Larsen (billionai) } 86967468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 86977468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 86987468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 86997468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 87007468e2c8SBruno Larsen (billionai) if (tmp == 0) { 87017468e2c8SBruno Larsen (billionai) free(table[i]); 87027468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 87037468e2c8SBruno Larsen (billionai) } else { 87047468e2c8SBruno Larsen (billionai) count++; 87057468e2c8SBruno Larsen (billionai) } 87067468e2c8SBruno Larsen (billionai) } else { 87077468e2c8SBruno Larsen (billionai) count++; 87087468e2c8SBruno Larsen (billionai) } 87097468e2c8SBruno Larsen (billionai) } 87107468e2c8SBruno Larsen (billionai) } 87117468e2c8SBruno Larsen (billionai) 87127468e2c8SBruno Larsen (billionai) return count; 87137468e2c8SBruno Larsen (billionai) } 87147468e2c8SBruno Larsen (billionai) 87157468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 87167468e2c8SBruno Larsen (billionai) { 87177468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 87187468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 87197468e2c8SBruno Larsen (billionai) } 87207468e2c8SBruno Larsen (billionai) } 87217468e2c8SBruno Larsen (billionai) 87227468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 87237468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 87247468e2c8SBruno Larsen (billionai) { 87257468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 87267468e2c8SBruno Larsen (billionai) opcode_t *opc; 87277468e2c8SBruno Larsen (billionai) 87287468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 87297468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 87307468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 87317468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 87327468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 87337468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 87347468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 87357468e2c8SBruno Larsen (billionai) opc->opc3); 87367468e2c8SBruno Larsen (billionai) return; 87377468e2c8SBruno Larsen (billionai) } 87387468e2c8SBruno Larsen (billionai) } 87397468e2c8SBruno Larsen (billionai) } 87407468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 87417468e2c8SBruno Larsen (billionai) fflush(stdout); 87427468e2c8SBruno Larsen (billionai) fflush(stderr); 87437468e2c8SBruno Larsen (billionai) } 87447468e2c8SBruno Larsen (billionai) 87457468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 87467468e2c8SBruno Larsen (billionai) { 87477468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 87487468e2c8SBruno Larsen (billionai) int i, j, k; 87497468e2c8SBruno Larsen (billionai) 87507468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 87517468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 87527468e2c8SBruno Larsen (billionai) continue; 87537468e2c8SBruno Larsen (billionai) } 87547468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 87557468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 87567468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 87577468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 87587468e2c8SBruno Larsen (billionai) continue; 87597468e2c8SBruno Larsen (billionai) } 87607468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 87617468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 87627468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 87637468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 87647468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 87657468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 87667468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 87677468e2c8SBruno Larsen (billionai) } 87687468e2c8SBruno Larsen (billionai) } 87697468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 87707468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 87717468e2c8SBruno Larsen (billionai) } 87727468e2c8SBruno Larsen (billionai) } 87737468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 87747468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 87757468e2c8SBruno Larsen (billionai) } 87767468e2c8SBruno Larsen (billionai) } 87777468e2c8SBruno Larsen (billionai) } 87787468e2c8SBruno Larsen (billionai) 87797468e2c8SBruno Larsen (billionai) #if defined(PPC_DUMP_CPU) 87807468e2c8SBruno Larsen (billionai) static void dump_ppc_insns(CPUPPCState *env) 87817468e2c8SBruno Larsen (billionai) { 87827468e2c8SBruno Larsen (billionai) opc_handler_t **table, *handler; 87837468e2c8SBruno Larsen (billionai) const char *p, *q; 87847468e2c8SBruno Larsen (billionai) uint8_t opc1, opc2, opc3, opc4; 87857468e2c8SBruno Larsen (billionai) 87867468e2c8SBruno Larsen (billionai) printf("Instructions set:\n"); 87877468e2c8SBruno Larsen (billionai) /* opc1 is 6 bits long */ 87887468e2c8SBruno Larsen (billionai) for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 87897468e2c8SBruno Larsen (billionai) table = env->opcodes; 87907468e2c8SBruno Larsen (billionai) handler = table[opc1]; 87917468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 87927468e2c8SBruno Larsen (billionai) /* opc2 is 5 bits long */ 87937468e2c8SBruno Larsen (billionai) for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 87947468e2c8SBruno Larsen (billionai) table = env->opcodes; 87957468e2c8SBruno Larsen (billionai) handler = env->opcodes[opc1]; 87967468e2c8SBruno Larsen (billionai) table = ind_table(handler); 87977468e2c8SBruno Larsen (billionai) handler = table[opc2]; 87987468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 87997468e2c8SBruno Larsen (billionai) table = ind_table(handler); 88007468e2c8SBruno Larsen (billionai) /* opc3 is 5 bits long */ 88017468e2c8SBruno Larsen (billionai) for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 88027468e2c8SBruno Larsen (billionai) opc3++) { 88037468e2c8SBruno Larsen (billionai) handler = table[opc3]; 88047468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 88057468e2c8SBruno Larsen (billionai) table = ind_table(handler); 88067468e2c8SBruno Larsen (billionai) /* opc4 is 5 bits long */ 88077468e2c8SBruno Larsen (billionai) for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 88087468e2c8SBruno Larsen (billionai) opc4++) { 88097468e2c8SBruno Larsen (billionai) handler = table[opc4]; 88107468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 88117468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x %02x -- " 88127468e2c8SBruno Larsen (billionai) "(%02d %04d %02d) : %s\n", 88137468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc4, 88147468e2c8SBruno Larsen (billionai) opc1, (opc3 << 5) | opc2, opc4, 88157468e2c8SBruno Larsen (billionai) handler->oname); 88167468e2c8SBruno Larsen (billionai) } 88177468e2c8SBruno Larsen (billionai) } 88187468e2c8SBruno Larsen (billionai) } else { 88197468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 88207468e2c8SBruno Larsen (billionai) /* Special hack to properly dump SPE insns */ 88217468e2c8SBruno Larsen (billionai) p = strchr(handler->oname, '_'); 88227468e2c8SBruno Larsen (billionai) if (p == NULL) { 88237468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x (%02d %04d) : " 88247468e2c8SBruno Larsen (billionai) "%s\n", 88257468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc1, 88267468e2c8SBruno Larsen (billionai) (opc3 << 5) | opc2, 88277468e2c8SBruno Larsen (billionai) handler->oname); 88287468e2c8SBruno Larsen (billionai) } else { 88297468e2c8SBruno Larsen (billionai) q = "speundef"; 88307468e2c8SBruno Larsen (billionai) if ((p - handler->oname) != strlen(q) 88317468e2c8SBruno Larsen (billionai) || (memcmp(handler->oname, q, strlen(q)) 88327468e2c8SBruno Larsen (billionai) != 0)) { 88337468e2c8SBruno Larsen (billionai) /* First instruction */ 88347468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x" 88357468e2c8SBruno Larsen (billionai) "(%02d %04d) : %.*s\n", 88367468e2c8SBruno Larsen (billionai) opc1, opc2 << 1, opc3, opc1, 88377468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1), 88387468e2c8SBruno Larsen (billionai) (int)(p - handler->oname), 88397468e2c8SBruno Larsen (billionai) handler->oname); 88407468e2c8SBruno Larsen (billionai) } 88417468e2c8SBruno Larsen (billionai) if (strcmp(p + 1, q) != 0) { 88427468e2c8SBruno Larsen (billionai) /* Second instruction */ 88437468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x " 88447468e2c8SBruno Larsen (billionai) "(%02d %04d) : %s\n", opc1, 88457468e2c8SBruno Larsen (billionai) (opc2 << 1) | 1, opc3, opc1, 88467468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1) | 1, 88477468e2c8SBruno Larsen (billionai) p + 1); 88487468e2c8SBruno Larsen (billionai) } 88497468e2c8SBruno Larsen (billionai) } 88507468e2c8SBruno Larsen (billionai) } 88517468e2c8SBruno Larsen (billionai) } 88527468e2c8SBruno Larsen (billionai) } 88537468e2c8SBruno Larsen (billionai) } else { 88547468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 88557468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 88567468e2c8SBruno Larsen (billionai) opc1, opc2, opc1, opc2, handler->oname); 88577468e2c8SBruno Larsen (billionai) } 88587468e2c8SBruno Larsen (billionai) } 88597468e2c8SBruno Larsen (billionai) } 88607468e2c8SBruno Larsen (billionai) } else { 88617468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 88627468e2c8SBruno Larsen (billionai) printf("INSN: %02x -- -- (%02d ----) : %s\n", 88637468e2c8SBruno Larsen (billionai) opc1, opc1, handler->oname); 88647468e2c8SBruno Larsen (billionai) } 88657468e2c8SBruno Larsen (billionai) } 88667468e2c8SBruno Larsen (billionai) } 88677468e2c8SBruno Larsen (billionai) } 88687468e2c8SBruno Larsen (billionai) #endif 88697468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 88707468e2c8SBruno Larsen (billionai) { 88717468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 88727468e2c8SBruno Larsen (billionai) 88737468e2c8SBruno Larsen (billionai) /* 88747468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 88757468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 88767468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 88777468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 88787468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 88797468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 88807468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 88817468e2c8SBruno Larsen (billionai) */ 88827468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 88837468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 88847468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 88857468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 88867468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 88877468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 88887468e2c8SBruno Larsen (billionai) } 88897468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 88907468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 88917468e2c8SBruno Larsen (billionai) return 0; 88927468e2c8SBruno Larsen (billionai) } 88937468e2c8SBruno Larsen (billionai) 88947468e2c8SBruno Larsen (billionai) 889511cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 8896fcf5ef2aSThomas Huth { 8897fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 8898fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 8899fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 8900fcf5ef2aSThomas Huth int op1, op2, op3; 8901fcf5ef2aSThomas Huth 8902fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 8903fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 8904fcf5ef2aSThomas Huth handler = t1[op1]; 8905fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 8906fcf5ef2aSThomas Huth t2 = ind_table(handler); 8907fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 8908fcf5ef2aSThomas Huth handler = t2[op2]; 8909fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 8910fcf5ef2aSThomas Huth t3 = ind_table(handler); 8911fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 8912fcf5ef2aSThomas Huth handler = t3[op3]; 8913efe843d8SDavid Gibson if (handler->count == 0) { 8914fcf5ef2aSThomas Huth continue; 8915efe843d8SDavid Gibson } 891611cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 8917fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 8918fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 8919fcf5ef2aSThomas Huth handler->oname, 8920fcf5ef2aSThomas Huth handler->count, handler->count); 8921fcf5ef2aSThomas Huth } 8922fcf5ef2aSThomas Huth } else { 8923efe843d8SDavid Gibson if (handler->count == 0) { 8924fcf5ef2aSThomas Huth continue; 8925efe843d8SDavid Gibson } 892611cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 8927fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 8928fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 8929fcf5ef2aSThomas Huth handler->count, handler->count); 8930fcf5ef2aSThomas Huth } 8931fcf5ef2aSThomas Huth } 8932fcf5ef2aSThomas Huth } else { 8933efe843d8SDavid Gibson if (handler->count == 0) { 8934fcf5ef2aSThomas Huth continue; 8935efe843d8SDavid Gibson } 893611cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 8937fcf5ef2aSThomas Huth " %" PRId64 "\n", 8938fcf5ef2aSThomas Huth op1, op1, handler->oname, 8939fcf5ef2aSThomas Huth handler->count, handler->count); 8940fcf5ef2aSThomas Huth } 8941fcf5ef2aSThomas Huth } 8942fcf5ef2aSThomas Huth #endif 8943fcf5ef2aSThomas Huth } 8944fcf5ef2aSThomas Huth 8945624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8946624cb07fSRichard Henderson { 8947624cb07fSRichard Henderson opc_handler_t **table, *handler; 8948624cb07fSRichard Henderson uint32_t inval; 8949624cb07fSRichard Henderson 8950624cb07fSRichard Henderson ctx->opcode = insn; 8951624cb07fSRichard Henderson 8952624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8953624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8954624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8955624cb07fSRichard Henderson 8956624cb07fSRichard Henderson table = cpu->opcodes; 8957624cb07fSRichard Henderson handler = table[opc1(insn)]; 8958624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8959624cb07fSRichard Henderson table = ind_table(handler); 8960624cb07fSRichard Henderson handler = table[opc2(insn)]; 8961624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8962624cb07fSRichard Henderson table = ind_table(handler); 8963624cb07fSRichard Henderson handler = table[opc3(insn)]; 8964624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8965624cb07fSRichard Henderson table = ind_table(handler); 8966624cb07fSRichard Henderson handler = table[opc4(insn)]; 8967624cb07fSRichard Henderson } 8968624cb07fSRichard Henderson } 8969624cb07fSRichard Henderson } 8970624cb07fSRichard Henderson 8971624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8972624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8973624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8974624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8975624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8976624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8977624cb07fSRichard Henderson insn, ctx->cia); 8978624cb07fSRichard Henderson return false; 8979624cb07fSRichard Henderson } 8980624cb07fSRichard Henderson 8981624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8982624cb07fSRichard Henderson && Rc(insn))) { 8983624cb07fSRichard Henderson inval = handler->inval2; 8984624cb07fSRichard Henderson } else { 8985624cb07fSRichard Henderson inval = handler->inval1; 8986624cb07fSRichard Henderson } 8987624cb07fSRichard Henderson 8988624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8989624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8990624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8991624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8992624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8993624cb07fSRichard Henderson insn, ctx->cia); 8994624cb07fSRichard Henderson return false; 8995624cb07fSRichard Henderson } 8996624cb07fSRichard Henderson 8997624cb07fSRichard Henderson handler->handler(ctx); 8998624cb07fSRichard Henderson return true; 8999624cb07fSRichard Henderson } 9000624cb07fSRichard Henderson 9001b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 9002fcf5ef2aSThomas Huth { 9003b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 90049c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 90052df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 9006b0c2d521SEmilio G. Cota int bound; 9007fcf5ef2aSThomas Huth 9008b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 9009b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 90102df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 9011d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 90122df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 90132df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 9014b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 9015b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 9016b0c2d521SEmilio G. Cota ctx->access_type = -1; 9017d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 90182df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 9019b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 90200e3bf489SRoman Kapl ctx->flags = env->flags; 9021fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 90222df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 9023b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 9024fcf5ef2aSThomas Huth #endif 9025e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 9026e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 9027d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 9028fcf5ef2aSThomas Huth 90292df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 90302df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 90312df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 90322df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 90332df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 9034f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 90352df4fe7aSRichard Henderson 9036b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 90372df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 90382df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 9039efe843d8SDavid Gibson } 90402df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 9041b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 9042efe843d8SDavid Gibson } 9043b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9044b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 9045fcf5ef2aSThomas Huth } 9046b0c2d521SEmilio G. Cota 9047b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 9048b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 9049fcf5ef2aSThomas Huth } 9050fcf5ef2aSThomas Huth 9051b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 9052b0c2d521SEmilio G. Cota { 9053b0c2d521SEmilio G. Cota } 9054fcf5ef2aSThomas Huth 9055b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 9056b0c2d521SEmilio G. Cota { 9057b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 9058b0c2d521SEmilio G. Cota } 9059b0c2d521SEmilio G. Cota 9060b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 9061b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 9062b0c2d521SEmilio G. Cota { 9063b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9064b0c2d521SEmilio G. Cota 90652736fc61SRichard Henderson gen_update_nip(ctx, ctx->base.pc_next); 9066b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9067efe843d8SDavid Gibson /* 9068efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 9069efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 9070efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 9071efe843d8SDavid Gibson * setting tb->size below does the right thing. 9072efe843d8SDavid Gibson */ 9073b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9074b0c2d521SEmilio G. Cota return true; 9075fcf5ef2aSThomas Huth } 9076fcf5ef2aSThomas Huth 9077b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 9078b0c2d521SEmilio G. Cota { 9079b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 908028876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 9081b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 9082624cb07fSRichard Henderson uint32_t insn; 9083624cb07fSRichard Henderson bool ok; 9084b0c2d521SEmilio G. Cota 9085fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 9086fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 9087b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 9088b0c2d521SEmilio G. Cota 90892c2bcb1bSRichard Henderson ctx->cia = ctx->base.pc_next; 9090624cb07fSRichard Henderson insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); 9091b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9092fcf5ef2aSThomas Huth 9093624cb07fSRichard Henderson ok = decode_legacy(cpu, ctx, insn); 9094624cb07fSRichard Henderson if (!ok) { 9095624cb07fSRichard Henderson gen_invalid(ctx); 9096fcf5ef2aSThomas Huth } 9097624cb07fSRichard Henderson 9098fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9099fcf5ef2aSThomas Huth handler->count++; 9100fcf5ef2aSThomas Huth #endif 91013d8a5b69SRichard Henderson 9102fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 9103b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 9104b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 91053d8a5b69SRichard Henderson ctx->exception != POWERPC_EXCP_BRANCH && 91063d8a5b69SRichard Henderson ctx->base.is_jmp != DISAS_NORETURN)) { 9107e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 91080e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 9109fcf5ef2aSThomas Huth } 9110b0c2d521SEmilio G. Cota 9111fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 9112b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 9113b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 9114b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 9115fcf5ef2aSThomas Huth } 9116b0c2d521SEmilio G. Cota 9117a9b5b3d0SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT) { 9118a9b5b3d0SRichard Henderson switch (ctx->exception) { 9119a9b5b3d0SRichard Henderson case POWERPC_EXCP_NONE: 9120a9b5b3d0SRichard Henderson break; 9121a9b5b3d0SRichard Henderson case POWERPC_EXCP_BRANCH: 9122a9b5b3d0SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 9123a9b5b3d0SRichard Henderson break; 9124a9b5b3d0SRichard Henderson default: 9125a9b5b3d0SRichard Henderson /* Every other ctx->exception should have set NORETURN. */ 9126a9b5b3d0SRichard Henderson g_assert_not_reached(); 9127a9b5b3d0SRichard Henderson } 91283d8a5b69SRichard Henderson } 9129fcf5ef2aSThomas Huth } 9130b0c2d521SEmilio G. Cota 9131b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 9132b0c2d521SEmilio G. Cota { 9133b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9134a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 9135a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 9136b0c2d521SEmilio G. Cota 9137a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 9138a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 91393d8a5b69SRichard Henderson return; 91403d8a5b69SRichard Henderson } 91413d8a5b69SRichard Henderson 9142a9b5b3d0SRichard Henderson /* Honor single stepping. */ 9143b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9144a9b5b3d0SRichard Henderson switch (is_jmp) { 9145a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 9146a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 9147a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 9148a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9149a9b5b3d0SRichard Henderson break; 9150a9b5b3d0SRichard Henderson case DISAS_EXIT: 9151a9b5b3d0SRichard Henderson case DISAS_CHAIN: 9152a9b5b3d0SRichard Henderson break; 9153a9b5b3d0SRichard Henderson default: 9154a9b5b3d0SRichard Henderson g_assert_not_reached(); 9155fcf5ef2aSThomas Huth } 9156a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 9157a9b5b3d0SRichard Henderson return; 9158a9b5b3d0SRichard Henderson } 9159a9b5b3d0SRichard Henderson 9160a9b5b3d0SRichard Henderson switch (is_jmp) { 9161a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 9162a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 9163a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 9164a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9165a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 9166a9b5b3d0SRichard Henderson break; 9167a9b5b3d0SRichard Henderson } 9168a9b5b3d0SRichard Henderson /* fall through */ 9169a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 9170a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9171a9b5b3d0SRichard Henderson /* fall through */ 9172a9b5b3d0SRichard Henderson case DISAS_CHAIN: 9173a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 9174a9b5b3d0SRichard Henderson break; 9175a9b5b3d0SRichard Henderson 9176a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 9177a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9178a9b5b3d0SRichard Henderson /* fall through */ 9179a9b5b3d0SRichard Henderson case DISAS_EXIT: 918007ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 9181a9b5b3d0SRichard Henderson break; 9182a9b5b3d0SRichard Henderson 9183a9b5b3d0SRichard Henderson default: 9184a9b5b3d0SRichard Henderson g_assert_not_reached(); 9185fcf5ef2aSThomas Huth } 9186fcf5ef2aSThomas Huth } 9187b0c2d521SEmilio G. Cota 9188b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 9189b0c2d521SEmilio G. Cota { 9190b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 9191b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 9192b0c2d521SEmilio G. Cota } 9193b0c2d521SEmilio G. Cota 9194b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 9195b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 9196b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 9197b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 9198b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 9199b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 9200b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 9201b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 9202b0c2d521SEmilio G. Cota }; 9203b0c2d521SEmilio G. Cota 92048b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 9205b0c2d521SEmilio G. Cota { 9206b0c2d521SEmilio G. Cota DisasContext ctx; 9207b0c2d521SEmilio G. Cota 92088b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 9209fcf5ef2aSThomas Huth } 9210fcf5ef2aSThomas Huth 9211fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 9212fcf5ef2aSThomas Huth target_ulong *data) 9213fcf5ef2aSThomas Huth { 9214fcf5ef2aSThomas Huth env->nip = data[0]; 9215fcf5ef2aSThomas Huth } 9216