1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39eeaaefe9SLeandro Lupori #include "power8-pmu.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44d53106c9SRichard Henderson #define HELPER_H "helper.h" 45d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 46d53106c9SRichard Henderson #undef HELPER_H 47d53106c9SRichard Henderson 48fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 49fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 50fcf5ef2aSThomas Huth 51fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 52efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 53fcf5ef2aSThomas Huth 54fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56fcf5ef2aSThomas Huth #else 57fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 58fcf5ef2aSThomas Huth #endif 59fcf5ef2aSThomas Huth /*****************************************************************************/ 60fcf5ef2aSThomas Huth /* Code translation helpers */ 61fcf5ef2aSThomas Huth 62fcf5ef2aSThomas Huth /* global register indexes */ 63fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 65fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 66fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 67fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 68fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 69fcf5ef2aSThomas Huth static TCGv cpu_nip; 70fcf5ef2aSThomas Huth static TCGv cpu_msr; 71fcf5ef2aSThomas Huth static TCGv cpu_ctr; 72fcf5ef2aSThomas Huth static TCGv cpu_lr; 73fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 74fcf5ef2aSThomas Huth static TCGv cpu_cfar; 75fcf5ef2aSThomas Huth #endif 76dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77fcf5ef2aSThomas Huth static TCGv cpu_reserve; 78392d328aSNicholas Piggin static TCGv cpu_reserve_length; 79253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 80894448aeSRichard Henderson static TCGv cpu_reserve_val2; 81fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 82fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 83fcf5ef2aSThomas Huth 84fcf5ef2aSThomas Huth void ppc_translate_init(void) 85fcf5ef2aSThomas Huth { 86fcf5ef2aSThomas Huth int i; 87fcf5ef2aSThomas Huth char *p; 88fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth p = cpu_reg_names; 91fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 92fcf5ef2aSThomas Huth 93fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 94fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 95fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 97fcf5ef2aSThomas Huth p += 5; 98fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 99fcf5ef2aSThomas Huth } 100fcf5ef2aSThomas Huth 101fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 103fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 107fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 108fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 110fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 111fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 112fcf5ef2aSThomas Huth } 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 124fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 127fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 128fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 129fcf5ef2aSThomas Huth #endif 130fcf5ef2aSThomas Huth 131fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 133fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 135fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 137fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 138fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 139dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 141dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 142dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 145fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 146fcf5ef2aSThomas Huth "reserve_addr"); 147392d328aSNicholas Piggin cpu_reserve_length = tcg_global_mem_new(cpu_env, 148392d328aSNicholas Piggin offsetof(CPUPPCState, 149392d328aSNicholas Piggin reserve_length), 150392d328aSNicholas Piggin "reserve_length"); 151253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 152253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 153253ce7b2SNikunj A Dadhania "reserve_val"); 154894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 156894448aeSRichard Henderson "reserve_val2"); 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 159fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 160fcf5ef2aSThomas Huth 161fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 163efe843d8SDavid Gibson "access_type"); 164fcf5ef2aSThomas Huth } 165fcf5ef2aSThomas Huth 166fcf5ef2aSThomas Huth /* internal defines */ 167fcf5ef2aSThomas Huth struct DisasContext { 168b6bac4bcSEmilio G. Cota DisasContextBase base; 1692c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 170fcf5ef2aSThomas Huth uint32_t opcode; 171fcf5ef2aSThomas Huth /* Routine used to access memory */ 172fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 173fcf5ef2aSThomas Huth bool lazy_tlb_flush; 174fcf5ef2aSThomas Huth bool need_access_type; 175fcf5ef2aSThomas Huth int mem_idx; 176fcf5ef2aSThomas Huth int access_type; 177fcf5ef2aSThomas Huth /* Translation flags */ 17814776ab5STony Nguyen MemOp default_tcg_memop_mask; 179fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 180fcf5ef2aSThomas Huth bool sf_mode; 181fcf5ef2aSThomas Huth bool has_cfar; 182fcf5ef2aSThomas Huth #endif 183fcf5ef2aSThomas Huth bool fpu_enabled; 184fcf5ef2aSThomas Huth bool altivec_enabled; 185fcf5ef2aSThomas Huth bool vsx_enabled; 186fcf5ef2aSThomas Huth bool spe_enabled; 187fcf5ef2aSThomas Huth bool tm_enabled; 188c6fd28fdSSuraj Jitindar Singh bool gtse; 1891db3632aSMatheus Ferst bool hr; 190f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 191f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1928b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1938b3d1c49SLeandro Lupori bool pmc_other; 19446d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 195fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196fcf5ef2aSThomas Huth int singlestep_enabled; 1970e3bf489SRoman Kapl uint32_t flags; 198fcf5ef2aSThomas Huth uint64_t insns_flags; 199fcf5ef2aSThomas Huth uint64_t insns_flags2; 200fcf5ef2aSThomas Huth }; 201fcf5ef2aSThomas Huth 202a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206a9b5b3d0SRichard Henderson 207fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 208fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 209fcf5ef2aSThomas Huth { 210ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 211fcf5ef2aSThomas Huth return ctx->le_mode; 212fcf5ef2aSThomas Huth #else 213fcf5ef2aSThomas Huth return !ctx->le_mode; 214fcf5ef2aSThomas Huth #endif 215fcf5ef2aSThomas Huth } 216fcf5ef2aSThomas Huth 217fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 218fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 219fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 220fcf5ef2aSThomas Huth #else 221fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 222fcf5ef2aSThomas Huth #endif 223fcf5ef2aSThomas Huth 224fcf5ef2aSThomas Huth struct opc_handler_t { 225fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226fcf5ef2aSThomas Huth uint32_t inval1; 227fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228fcf5ef2aSThomas Huth uint32_t inval2; 229fcf5ef2aSThomas Huth /* instruction type */ 230fcf5ef2aSThomas Huth uint64_t type; 231fcf5ef2aSThomas Huth /* extended instruction type */ 232fcf5ef2aSThomas Huth uint64_t type2; 233fcf5ef2aSThomas Huth /* handler */ 234fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 235fcf5ef2aSThomas Huth }; 236fcf5ef2aSThomas Huth 237b769d4c8SNicholas Piggin static inline bool gen_serialize(DisasContext *ctx) 238b769d4c8SNicholas Piggin { 239b769d4c8SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 240b769d4c8SNicholas Piggin /* Restart with exclusive lock. */ 241b769d4c8SNicholas Piggin gen_helper_exit_atomic(cpu_env); 242b769d4c8SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 243b769d4c8SNicholas Piggin return false; 244b769d4c8SNicholas Piggin } 245b769d4c8SNicholas Piggin return true; 246b769d4c8SNicholas Piggin } 247b769d4c8SNicholas Piggin 248b769d4c8SNicholas Piggin #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 249b769d4c8SNicholas Piggin static inline bool gen_serialize_core(DisasContext *ctx) 250b769d4c8SNicholas Piggin { 251b769d4c8SNicholas Piggin if (ctx->flags & POWERPC_FLAG_SMT) { 252b769d4c8SNicholas Piggin return gen_serialize(ctx); 253b769d4c8SNicholas Piggin } 254b769d4c8SNicholas Piggin 255b769d4c8SNicholas Piggin return true; 256b769d4c8SNicholas Piggin } 257b769d4c8SNicholas Piggin #endif 258b769d4c8SNicholas Piggin 2590e3bf489SRoman Kapl /* SPR load/store helpers */ 2600e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2610e3bf489SRoman Kapl { 2620e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2630e3bf489SRoman Kapl } 2640e3bf489SRoman Kapl 2650e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2660e3bf489SRoman Kapl { 2670e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2680e3bf489SRoman Kapl } 2690e3bf489SRoman Kapl 270fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 271fcf5ef2aSThomas Huth { 272fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 273fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 274fcf5ef2aSThomas Huth ctx->access_type = access_type; 275fcf5ef2aSThomas Huth } 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth 278fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 279fcf5ef2aSThomas Huth { 280fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 281fcf5ef2aSThomas Huth nip = (uint32_t)nip; 282fcf5ef2aSThomas Huth } 283fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 284fcf5ef2aSThomas Huth } 285fcf5ef2aSThomas Huth 286fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 287fcf5ef2aSThomas Huth { 288fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 289fcf5ef2aSThomas Huth 290efe843d8SDavid Gibson /* 291efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 292efe843d8SDavid Gibson * faulting instruction 293fcf5ef2aSThomas Huth */ 2942c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2957058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 2967058ff52SRichard Henderson t1 = tcg_constant_i32(error); 297fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 2983d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 299fcf5ef2aSThomas Huth } 300fcf5ef2aSThomas Huth 301fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 302fcf5ef2aSThomas Huth { 303fcf5ef2aSThomas Huth TCGv_i32 t0; 304fcf5ef2aSThomas Huth 305efe843d8SDavid Gibson /* 306efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 307efe843d8SDavid Gibson * faulting instruction 308fcf5ef2aSThomas Huth */ 3092c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 3107058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 311fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3123d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 313fcf5ef2aSThomas Huth } 314fcf5ef2aSThomas Huth 315fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 316fcf5ef2aSThomas Huth target_ulong nip) 317fcf5ef2aSThomas Huth { 318fcf5ef2aSThomas Huth TCGv_i32 t0; 319fcf5ef2aSThomas Huth 320fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 3217058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 322fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3233d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 324fcf5ef2aSThomas Huth } 325fcf5ef2aSThomas Huth 3262fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3272fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3282fdedcbcSMatheus Ferst { 329283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 3302fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3312fdedcbcSMatheus Ferst } 3322fdedcbcSMatheus Ferst #endif 3332fdedcbcSMatheus Ferst 334e150ac89SRoman Kapl /* 335e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 336e150ac89SRoman Kapl * SPR registers for this exception. 337e150ac89SRoman Kapl * 338e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 339e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3400e3bf489SRoman Kapl */ 341e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3420e3bf489SRoman Kapl { 3430e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3440e3bf489SRoman Kapl target_ulong dbsr = 0; 345e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3460e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 347e150ac89SRoman Kapl } else { 348e150ac89SRoman Kapl /* Must have been branch */ 3490e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3500e3bf489SRoman Kapl } 3510e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3520e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3530e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3540e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3550e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3560e3bf489SRoman Kapl } else { 357e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3580e3bf489SRoman Kapl } 3590e3bf489SRoman Kapl } 3600e3bf489SRoman Kapl 361fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 362fcf5ef2aSThomas Huth { 3639498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3643d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 365fcf5ef2aSThomas Huth } 366fcf5ef2aSThomas Huth 367fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 368fcf5ef2aSThomas Huth { 369fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 370fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 371fcf5ef2aSThomas Huth } 372fcf5ef2aSThomas Huth 373fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 374fcf5ef2aSThomas Huth { 375fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 376fcf5ef2aSThomas Huth } 377fcf5ef2aSThomas Huth 378fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 379fcf5ef2aSThomas Huth { 380fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 381fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 382fcf5ef2aSThomas Huth } 383fcf5ef2aSThomas Huth 38437f219c8SBruno Larsen (billionai) /*****************************************************************************/ 38537f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 38637f219c8SBruno Larsen (billionai) 387a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 38837f219c8SBruno Larsen (billionai) { 38937f219c8SBruno Larsen (billionai) #if 0 39037f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 39137f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 39237f219c8SBruno Larsen (billionai) #endif 39337f219c8SBruno Larsen (billionai) } 39437f219c8SBruno Larsen (billionai) 39537f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 39637f219c8SBruno Larsen (billionai) 39737f219c8SBruno Larsen (billionai) /* 39837f219c8SBruno Larsen (billionai) * Generic callbacks: 39937f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 40037f219c8SBruno Larsen (billionai) */ 40137f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 40237f219c8SBruno Larsen (billionai) { 40337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4047058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 40537f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 40637f219c8SBruno Larsen (billionai) #endif 40737f219c8SBruno Larsen (billionai) } 40837f219c8SBruno Larsen (billionai) 409a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 41037f219c8SBruno Larsen (billionai) { 41137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 41237f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 41337f219c8SBruno Larsen (billionai) } 41437f219c8SBruno Larsen (billionai) 41537f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 41637f219c8SBruno Larsen (billionai) { 41737f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4187058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 41937f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 42037f219c8SBruno Larsen (billionai) #endif 42137f219c8SBruno Larsen (billionai) } 42237f219c8SBruno Larsen (billionai) 423a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 42437f219c8SBruno Larsen (billionai) { 42537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 42637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42737f219c8SBruno Larsen (billionai) } 42837f219c8SBruno Larsen (billionai) 429a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43037f219c8SBruno Larsen (billionai) { 43137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43537f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43637f219c8SBruno Larsen (billionai) #else 43737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43837f219c8SBruno Larsen (billionai) #endif 43937f219c8SBruno Larsen (billionai) } 44037f219c8SBruno Larsen (billionai) 441c5d98a7bSNicholas Piggin static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 442fbda88f7SNicholas Piggin { 443488aad11SNicholas Piggin /* This does not implement >1 thread */ 444488aad11SNicholas Piggin TCGv t0 = tcg_temp_new(); 445488aad11SNicholas Piggin TCGv t1 = tcg_temp_new(); 446488aad11SNicholas Piggin tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 447488aad11SNicholas Piggin tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 448488aad11SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 449488aad11SNicholas Piggin gen_store_spr(sprn, t1); 450c5d98a7bSNicholas Piggin } 451c5d98a7bSNicholas Piggin 452c5d98a7bSNicholas Piggin void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 453c5d98a7bSNicholas Piggin { 454c5d98a7bSNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT)) { 455c5d98a7bSNicholas Piggin spr_write_CTRL_ST(ctx, sprn, gprn); 456c5d98a7bSNicholas Piggin goto out; 457c5d98a7bSNicholas Piggin } 458c5d98a7bSNicholas Piggin 459c5d98a7bSNicholas Piggin if (!gen_serialize(ctx)) { 460c5d98a7bSNicholas Piggin return; 461c5d98a7bSNicholas Piggin } 462c5d98a7bSNicholas Piggin 463c5d98a7bSNicholas Piggin gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 464c5d98a7bSNicholas Piggin cpu_gpr[gprn]); 465c5d98a7bSNicholas Piggin out: 466488aad11SNicholas Piggin spr_store_dump_spr(sprn); 467fbda88f7SNicholas Piggin 468fbda88f7SNicholas Piggin /* 469fbda88f7SNicholas Piggin * SPR_CTRL writes must force a new translation block, 470fbda88f7SNicholas Piggin * allowing the PMU to calculate the run latch events with 471fbda88f7SNicholas Piggin * more accuracy. 472fbda88f7SNicholas Piggin */ 473fbda88f7SNicholas Piggin ctx->base.is_jmp = DISAS_EXIT_UPDATE; 474fbda88f7SNicholas Piggin } 475fbda88f7SNicholas Piggin 476fbda88f7SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 477a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 47837f219c8SBruno Larsen (billionai) { 47937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 48037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 48137f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 48237f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 48337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 48437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 48537f219c8SBruno Larsen (billionai) } 48637f219c8SBruno Larsen (billionai) 487a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 48837f219c8SBruno Larsen (billionai) { 48937f219c8SBruno Larsen (billionai) } 49037f219c8SBruno Larsen (billionai) 49137f219c8SBruno Larsen (billionai) #endif 49237f219c8SBruno Larsen (billionai) 49337f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 49437f219c8SBruno Larsen (billionai) /* XER */ 495a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 49637f219c8SBruno Larsen (billionai) { 49737f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 49837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 49937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 50037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 50137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 50237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 50337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 50437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 50537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 50637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 50737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 50837f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 50937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 51037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 51137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 51237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 51337f219c8SBruno Larsen (billionai) } 51437f219c8SBruno Larsen (billionai) } 51537f219c8SBruno Larsen (billionai) 516a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 51737f219c8SBruno Larsen (billionai) { 51837f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 51937f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 52037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 52137f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 52237f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 52337f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 52437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 52537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 52637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 52737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 52837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 52937f219c8SBruno Larsen (billionai) } 53037f219c8SBruno Larsen (billionai) 53137f219c8SBruno Larsen (billionai) /* LR */ 532a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 53337f219c8SBruno Larsen (billionai) { 53437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 53537f219c8SBruno Larsen (billionai) } 53637f219c8SBruno Larsen (billionai) 537a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 53837f219c8SBruno Larsen (billionai) { 53937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 54037f219c8SBruno Larsen (billionai) } 54137f219c8SBruno Larsen (billionai) 54237f219c8SBruno Larsen (billionai) /* CFAR */ 54337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 544a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 54537f219c8SBruno Larsen (billionai) { 54637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 54737f219c8SBruno Larsen (billionai) } 54837f219c8SBruno Larsen (billionai) 549a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 55037f219c8SBruno Larsen (billionai) { 55137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 55237f219c8SBruno Larsen (billionai) } 55337f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 55437f219c8SBruno Larsen (billionai) 55537f219c8SBruno Larsen (billionai) /* CTR */ 556a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 55737f219c8SBruno Larsen (billionai) { 55837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 55937f219c8SBruno Larsen (billionai) } 56037f219c8SBruno Larsen (billionai) 561a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 56237f219c8SBruno Larsen (billionai) { 56337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 56437f219c8SBruno Larsen (billionai) } 56537f219c8SBruno Larsen (billionai) 56637f219c8SBruno Larsen (billionai) /* User read access to SPR */ 56737f219c8SBruno Larsen (billionai) /* USPRx */ 56837f219c8SBruno Larsen (billionai) /* UMMCRx */ 56937f219c8SBruno Larsen (billionai) /* UPMCx */ 57037f219c8SBruno Larsen (billionai) /* USIA */ 57137f219c8SBruno Larsen (billionai) /* UDECR */ 572a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 57337f219c8SBruno Larsen (billionai) { 57437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 57537f219c8SBruno Larsen (billionai) } 57637f219c8SBruno Larsen (billionai) 57737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 578a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 57937f219c8SBruno Larsen (billionai) { 58037f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 58137f219c8SBruno Larsen (billionai) } 58237f219c8SBruno Larsen (billionai) #endif 58337f219c8SBruno Larsen (billionai) 58437f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 58537f219c8SBruno Larsen (billionai) /* DECR */ 58637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 587a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 58837f219c8SBruno Larsen (billionai) { 589283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 59037f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 59137f219c8SBruno Larsen (billionai) } 59237f219c8SBruno Larsen (billionai) 593a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 59437f219c8SBruno Larsen (billionai) { 595283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 59637f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 59737f219c8SBruno Larsen (billionai) } 59837f219c8SBruno Larsen (billionai) #endif 59937f219c8SBruno Larsen (billionai) 60037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 60137f219c8SBruno Larsen (billionai) /* Time base */ 602a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 60337f219c8SBruno Larsen (billionai) { 604283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 60537f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 60637f219c8SBruno Larsen (billionai) } 60737f219c8SBruno Larsen (billionai) 608a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 60937f219c8SBruno Larsen (billionai) { 610283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 61137f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 61237f219c8SBruno Larsen (billionai) } 61337f219c8SBruno Larsen (billionai) 614a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 61537f219c8SBruno Larsen (billionai) { 61637f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 61737f219c8SBruno Larsen (billionai) } 61837f219c8SBruno Larsen (billionai) 619a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 62037f219c8SBruno Larsen (billionai) { 62137f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 62237f219c8SBruno Larsen (billionai) } 62337f219c8SBruno Larsen (billionai) 62437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 625a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 62637f219c8SBruno Larsen (billionai) { 627283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 62837f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 62937f219c8SBruno Larsen (billionai) } 63037f219c8SBruno Larsen (billionai) 631a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 63237f219c8SBruno Larsen (billionai) { 633283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 63437f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 63537f219c8SBruno Larsen (billionai) } 63637f219c8SBruno Larsen (billionai) 637a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 63837f219c8SBruno Larsen (billionai) { 63937f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 64037f219c8SBruno Larsen (billionai) } 64137f219c8SBruno Larsen (billionai) 642a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 64337f219c8SBruno Larsen (billionai) { 64437f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 64537f219c8SBruno Larsen (billionai) } 64637f219c8SBruno Larsen (billionai) 64737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 648a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 64937f219c8SBruno Larsen (billionai) { 650283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65137f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 65237f219c8SBruno Larsen (billionai) } 65337f219c8SBruno Larsen (billionai) 654a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 65537f219c8SBruno Larsen (billionai) { 656283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65737f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 65837f219c8SBruno Larsen (billionai) } 65937f219c8SBruno Larsen (billionai) 66037f219c8SBruno Larsen (billionai) /* HDECR */ 661a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 66237f219c8SBruno Larsen (billionai) { 663283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 66437f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 66537f219c8SBruno Larsen (billionai) } 66637f219c8SBruno Larsen (billionai) 667a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 66837f219c8SBruno Larsen (billionai) { 669283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67037f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 67137f219c8SBruno Larsen (billionai) } 67237f219c8SBruno Larsen (billionai) 673a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 67437f219c8SBruno Larsen (billionai) { 675283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67637f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 67737f219c8SBruno Larsen (billionai) } 67837f219c8SBruno Larsen (billionai) 679a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 68037f219c8SBruno Larsen (billionai) { 681283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 68237f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 685a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 68637f219c8SBruno Larsen (billionai) { 687283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 68837f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 68937f219c8SBruno Larsen (billionai) } 69037f219c8SBruno Larsen (billionai) 69137f219c8SBruno Larsen (billionai) #endif 69237f219c8SBruno Larsen (billionai) #endif 69337f219c8SBruno Larsen (billionai) 69437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 69537f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 69637f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 697a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 69837f219c8SBruno Larsen (billionai) { 69937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 70237f219c8SBruno Larsen (billionai) } 70337f219c8SBruno Larsen (billionai) 704a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 70537f219c8SBruno Larsen (billionai) { 70637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70837f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 70937f219c8SBruno Larsen (billionai) } 71037f219c8SBruno Larsen (billionai) 711a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 71237f219c8SBruno Larsen (billionai) { 7137058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 71437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 71537f219c8SBruno Larsen (billionai) } 71637f219c8SBruno Larsen (billionai) 717a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 71837f219c8SBruno Larsen (billionai) { 7197058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 72037f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 72137f219c8SBruno Larsen (billionai) } 72237f219c8SBruno Larsen (billionai) 723a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 72437f219c8SBruno Larsen (billionai) { 7257058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 72637f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 729a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 73037f219c8SBruno Larsen (billionai) { 7317058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 73237f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) } 73437f219c8SBruno Larsen (billionai) 73537f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 73637f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 737a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 73837f219c8SBruno Larsen (billionai) { 73937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74137f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 74237f219c8SBruno Larsen (billionai) } 74337f219c8SBruno Larsen (billionai) 744a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74837f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 74937f219c8SBruno Larsen (billionai) } 75037f219c8SBruno Larsen (billionai) 751a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 75237f219c8SBruno Larsen (billionai) { 7537058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 75437f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 75537f219c8SBruno Larsen (billionai) } 75637f219c8SBruno Larsen (billionai) 757a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 75837f219c8SBruno Larsen (billionai) { 7597058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 76037f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 76137f219c8SBruno Larsen (billionai) } 76237f219c8SBruno Larsen (billionai) 763a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 76437f219c8SBruno Larsen (billionai) { 7657058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 76637f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 76737f219c8SBruno Larsen (billionai) } 76837f219c8SBruno Larsen (billionai) 769a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 77037f219c8SBruno Larsen (billionai) { 7717058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 77237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 77337f219c8SBruno Larsen (billionai) } 77437f219c8SBruno Larsen (billionai) 77537f219c8SBruno Larsen (billionai) /* SDR1 */ 776a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 77737f219c8SBruno Larsen (billionai) { 77837f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 77937f219c8SBruno Larsen (billionai) } 78037f219c8SBruno Larsen (billionai) 78137f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 78237f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 78337f219c8SBruno Larsen (billionai) /* PIDR */ 784a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 78537f219c8SBruno Larsen (billionai) { 78637f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 78737f219c8SBruno Larsen (billionai) } 78837f219c8SBruno Larsen (billionai) 789a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 79037f219c8SBruno Larsen (billionai) { 79137f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 79237f219c8SBruno Larsen (billionai) } 79337f219c8SBruno Larsen (billionai) 794a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 79537f219c8SBruno Larsen (billionai) { 79637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 79737f219c8SBruno Larsen (billionai) } 79837f219c8SBruno Larsen (billionai) 799a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 80037f219c8SBruno Larsen (billionai) { 80137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 80237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 80337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 80437f219c8SBruno Larsen (billionai) } 805a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 80637f219c8SBruno Larsen (billionai) { 80737f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 80837f219c8SBruno Larsen (billionai) } 80937f219c8SBruno Larsen (billionai) 810a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 81137f219c8SBruno Larsen (billionai) { 81237f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 81337f219c8SBruno Larsen (billionai) } 81437f219c8SBruno Larsen (billionai) 81537f219c8SBruno Larsen (billionai) /* DPDES */ 816a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 81737f219c8SBruno Larsen (billionai) { 818*d24e80b2SNicholas Piggin if (!gen_serialize_core(ctx)) { 819*d24e80b2SNicholas Piggin return; 820*d24e80b2SNicholas Piggin } 821*d24e80b2SNicholas Piggin 82237f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 82337f219c8SBruno Larsen (billionai) } 82437f219c8SBruno Larsen (billionai) 825a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 82637f219c8SBruno Larsen (billionai) { 827*d24e80b2SNicholas Piggin if (!gen_serialize_core(ctx)) { 828*d24e80b2SNicholas Piggin return; 829*d24e80b2SNicholas Piggin } 830*d24e80b2SNicholas Piggin 83137f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 83237f219c8SBruno Larsen (billionai) } 83337f219c8SBruno Larsen (billionai) #endif 83437f219c8SBruno Larsen (billionai) #endif 83537f219c8SBruno Larsen (billionai) 83637f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 83737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 838a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 83937f219c8SBruno Larsen (billionai) { 840283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 84137f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84237f219c8SBruno Larsen (billionai) } 84337f219c8SBruno Larsen (billionai) 844a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84537f219c8SBruno Larsen (billionai) { 846283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 84737f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 84837f219c8SBruno Larsen (billionai) } 84937f219c8SBruno Larsen (billionai) 850a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85137f219c8SBruno Larsen (billionai) { 852283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 85337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85437f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85537f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 856d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 85737f219c8SBruno Larsen (billionai) } 85837f219c8SBruno Larsen (billionai) 859a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86037f219c8SBruno Larsen (billionai) { 861283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 86237f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86337f219c8SBruno Larsen (billionai) } 86437f219c8SBruno Larsen (billionai) 865cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 866cbd8f17dSCédric Le Goater { 867283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 868cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 869cbd8f17dSCédric Le Goater } 870cbd8f17dSCédric Le Goater 871cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 872cbd8f17dSCédric Le Goater { 873283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 874cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 875cbd8f17dSCédric Le Goater } 876cbd8f17dSCédric Le Goater 877dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 878dd69d140SCédric Le Goater { 879dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 880dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 88147822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 882dd69d140SCédric Le Goater } 883dd69d140SCédric Le Goater 884a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 88537f219c8SBruno Larsen (billionai) { 886283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 88737f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 88837f219c8SBruno Larsen (billionai) } 88937f219c8SBruno Larsen (billionai) 890a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 89137f219c8SBruno Larsen (billionai) { 892283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 89337f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 89437f219c8SBruno Larsen (billionai) } 89537f219c8SBruno Larsen (billionai) #endif 89637f219c8SBruno Larsen (billionai) 897328c95fcSCédric Le Goater /* PIR */ 89837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 899a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 90037f219c8SBruno Larsen (billionai) { 90137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90437f219c8SBruno Larsen (billionai) } 90537f219c8SBruno Larsen (billionai) #endif 90637f219c8SBruno Larsen (billionai) 90737f219c8SBruno Larsen (billionai) /* SPE specific registers */ 908a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 90937f219c8SBruno Larsen (billionai) { 91037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91137f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91237f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91337f219c8SBruno Larsen (billionai) } 91437f219c8SBruno Larsen (billionai) 915a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91637f219c8SBruno Larsen (billionai) { 91737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91837f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 91937f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92037f219c8SBruno Larsen (billionai) } 92137f219c8SBruno Larsen (billionai) 92237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92337f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 924a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92537f219c8SBruno Larsen (billionai) { 92637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 92837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 92937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93137f219c8SBruno Larsen (billionai) } 93237f219c8SBruno Larsen (billionai) 933a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93437f219c8SBruno Larsen (billionai) { 93537f219c8SBruno Larsen (billionai) int sprn_offs; 93637f219c8SBruno Larsen (billionai) 93737f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 93837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 93937f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94037f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94137f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94237f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94337f219c8SBruno Larsen (billionai) } else { 9448e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9458e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9468e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 94737f219c8SBruno Larsen (billionai) return; 94837f219c8SBruno Larsen (billionai) } 94937f219c8SBruno Larsen (billionai) 95037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95537f219c8SBruno Larsen (billionai) } 95637f219c8SBruno Larsen (billionai) #endif 95737f219c8SBruno Larsen (billionai) 95837f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 95937f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 960a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96137f219c8SBruno Larsen (billionai) { 96237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96337f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96437f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96537f219c8SBruno Larsen (billionai) 96637f219c8SBruno Larsen (billionai) /* 96737f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 96837f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 96937f219c8SBruno Larsen (billionai) */ 97037f219c8SBruno Larsen (billionai) 97137f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97237f219c8SBruno Larsen (billionai) if (ctx->pr) { 97337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97437f219c8SBruno Larsen (billionai) } else { 97537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97637f219c8SBruno Larsen (billionai) } 97737f219c8SBruno Larsen (billionai) 97837f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 97937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98037f219c8SBruno Larsen (billionai) 98137f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98237f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98337f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98437f219c8SBruno Larsen (billionai) 98537f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 98737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 98837f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 98937f219c8SBruno Larsen (billionai) } 99037f219c8SBruno Larsen (billionai) 991a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 99237f219c8SBruno Larsen (billionai) { 99337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 99437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 99537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 99637f219c8SBruno Larsen (billionai) 99737f219c8SBruno Larsen (billionai) /* 99837f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 99937f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100037f219c8SBruno Larsen (billionai) */ 100137f219c8SBruno Larsen (billionai) 100237f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 100437f219c8SBruno Larsen (billionai) 100537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 100637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 100737f219c8SBruno Larsen (billionai) 100837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 100937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101137f219c8SBruno Larsen (billionai) 101237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 101437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 101537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 101637f219c8SBruno Larsen (billionai) } 101737f219c8SBruno Larsen (billionai) 1018a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 101937f219c8SBruno Larsen (billionai) { 102037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 102137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 102237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 102337f219c8SBruno Larsen (billionai) 102437f219c8SBruno Larsen (billionai) /* 102537f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 102637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 102737f219c8SBruno Larsen (billionai) */ 102837f219c8SBruno Larsen (billionai) 102937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 103037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 103137f219c8SBruno Larsen (billionai) 103237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 103337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 103437f219c8SBruno Larsen (billionai) 103537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 103637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 103737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 103837f219c8SBruno Larsen (billionai) 103937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 104037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 104137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 104237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 104337f219c8SBruno Larsen (billionai) } 104437f219c8SBruno Larsen (billionai) #endif 104537f219c8SBruno Larsen (billionai) #endif 104637f219c8SBruno Larsen (billionai) 104737f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1048a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 104937f219c8SBruno Larsen (billionai) { 105037f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 105137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 105237f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 105337f219c8SBruno Larsen (billionai) } 105437f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 105537f219c8SBruno Larsen (billionai) 105637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1057a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 105837f219c8SBruno Larsen (billionai) { 105937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106037f219c8SBruno Larsen (billionai) 106137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 106237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 106337f219c8SBruno Larsen (billionai) } 106437f219c8SBruno Larsen (billionai) 1065a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 106637f219c8SBruno Larsen (billionai) { 106737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106837f219c8SBruno Larsen (billionai) 106937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 107037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107137f219c8SBruno Larsen (billionai) } 107237f219c8SBruno Larsen (billionai) 1073a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 107437f219c8SBruno Larsen (billionai) { 107537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107637f219c8SBruno Larsen (billionai) 107737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 107837f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 107937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108037f219c8SBruno Larsen (billionai) } 108137f219c8SBruno Larsen (billionai) 1082a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 108337f219c8SBruno Larsen (billionai) { 108437f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 108537f219c8SBruno Larsen (billionai) } 108637f219c8SBruno Larsen (billionai) 1087a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 108837f219c8SBruno Larsen (billionai) { 10897058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 109037f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 109137f219c8SBruno Larsen (billionai) } 10927058ff52SRichard Henderson 1093a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 109437f219c8SBruno Larsen (billionai) { 109537f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 109637f219c8SBruno Larsen (billionai) } 10977058ff52SRichard Henderson 1098a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 109937f219c8SBruno Larsen (billionai) { 110037f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 110137f219c8SBruno Larsen (billionai) } 110237f219c8SBruno Larsen (billionai) 110337f219c8SBruno Larsen (billionai) #endif 110437f219c8SBruno Larsen (billionai) 110537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1106a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 110737f219c8SBruno Larsen (billionai) { 110837f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 110937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 111037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 111137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 111237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 111337f219c8SBruno Larsen (billionai) } 111437f219c8SBruno Larsen (billionai) 1115a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 111637f219c8SBruno Larsen (billionai) { 111737f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 111837f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 111937f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 112037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 112137f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 112237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 112337f219c8SBruno Larsen (billionai) } 112437f219c8SBruno Larsen (billionai) 112537f219c8SBruno Larsen (billionai) #endif 112637f219c8SBruno Larsen (billionai) 112737f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 112837f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 112937f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 113037f219c8SBruno Larsen (billionai) { 11317058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11327058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11337058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 113437f219c8SBruno Larsen (billionai) 113537f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 113637f219c8SBruno Larsen (billionai) } 113737f219c8SBruno Larsen (billionai) 113837f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 113937f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114037f219c8SBruno Larsen (billionai) { 11417058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11427058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11437058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 114437f219c8SBruno Larsen (billionai) 114537f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 114637f219c8SBruno Larsen (billionai) } 114737f219c8SBruno Larsen (billionai) 1148a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 114937f219c8SBruno Larsen (billionai) { 115037f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 115137f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 115237f219c8SBruno Larsen (billionai) 115337f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 115437f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 115537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 115637f219c8SBruno Larsen (billionai) } 115737f219c8SBruno Larsen (billionai) 1158a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 115937f219c8SBruno Larsen (billionai) { 116037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 116137f219c8SBruno Larsen (billionai) 116237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 116337f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 116437f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 116537f219c8SBruno Larsen (billionai) } 116637f219c8SBruno Larsen (billionai) 116737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1168a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 116937f219c8SBruno Larsen (billionai) { 117037f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 117137f219c8SBruno Larsen (billionai) 117237f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 117337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 117437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 117537f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 117637f219c8SBruno Larsen (billionai) } 117737f219c8SBruno Larsen (billionai) 1178a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 117937f219c8SBruno Larsen (billionai) { 118037f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 118137f219c8SBruno Larsen (billionai) } 118237f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 118337f219c8SBruno Larsen (billionai) 1184a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 118537f219c8SBruno Larsen (billionai) { 118637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 118737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 118837f219c8SBruno Larsen (billionai) } 118937f219c8SBruno Larsen (billionai) 1190a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 119137f219c8SBruno Larsen (billionai) { 119237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 119337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 119437f219c8SBruno Larsen (billionai) } 119537f219c8SBruno Larsen (billionai) 1196a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 119737f219c8SBruno Larsen (billionai) { 119837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 119937f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 120037f219c8SBruno Larsen (billionai) } 120137f219c8SBruno Larsen (billionai) 1202a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 120337f219c8SBruno Larsen (billionai) { 120437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 120537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 120637f219c8SBruno Larsen (billionai) } 120737f219c8SBruno Larsen (billionai) 1208a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 120937f219c8SBruno Larsen (billionai) { 121037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121137f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 121237f219c8SBruno Larsen (billionai) } 121337f219c8SBruno Larsen (billionai) 1214a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 121537f219c8SBruno Larsen (billionai) { 121637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121737f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 121837f219c8SBruno Larsen (billionai) } 121937f219c8SBruno Larsen (billionai) 1220a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 122137f219c8SBruno Larsen (billionai) { 122237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 122337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122437f219c8SBruno Larsen (billionai) } 122537f219c8SBruno Larsen (billionai) 1226a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 122737f219c8SBruno Larsen (billionai) { 122837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 122937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123037f219c8SBruno Larsen (billionai) } 123137f219c8SBruno Larsen (billionai) 1232a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 123337f219c8SBruno Larsen (billionai) { 123437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123537f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 123637f219c8SBruno Larsen (billionai) } 123737f219c8SBruno Larsen (billionai) 1238a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 123937f219c8SBruno Larsen (billionai) { 124037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124137f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 124237f219c8SBruno Larsen (billionai) } 1243395b5d5bSNicholas Miehlbradt 1244395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1245395b5d5bSNicholas Miehlbradt { 1246395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1247395b5d5bSNicholas Miehlbradt 1248395b5d5bSNicholas Miehlbradt /* 1249395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1250395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1251395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1252395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1253395b5d5bSNicholas Miehlbradt * 1254395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1255395b5d5bSNicholas Miehlbradt */ 1256395b5d5bSNicholas Miehlbradt 1257395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1258395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1259395b5d5bSNicholas Miehlbradt } 126037f219c8SBruno Larsen (billionai) #endif 126137f219c8SBruno Larsen (billionai) 1262fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1263fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1264fcf5ef2aSThomas Huth 1265fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1266fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1267fcf5ef2aSThomas Huth 1268fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1269fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1270fcf5ef2aSThomas Huth 1271fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1272fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1273fcf5ef2aSThomas Huth 1274fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1275fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1276fcf5ef2aSThomas Huth 1277fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1278fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1279fcf5ef2aSThomas Huth 1280fcf5ef2aSThomas Huth typedef struct opcode_t { 1281fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1282fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1283fcf5ef2aSThomas Huth unsigned char pad[4]; 1284fcf5ef2aSThomas Huth #endif 1285fcf5ef2aSThomas Huth opc_handler_t handler; 1286fcf5ef2aSThomas Huth const char *oname; 1287fcf5ef2aSThomas Huth } opcode_t; 1288fcf5ef2aSThomas Huth 12899f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 12909f0cf041SMatheus Ferst { 12919f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 12929f0cf041SMatheus Ferst } 12939f0cf041SMatheus Ferst 1294fcf5ef2aSThomas Huth /* Helpers for priv. check */ 12959f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1296fcf5ef2aSThomas Huth do { \ 12979f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1298fcf5ef2aSThomas Huth } while (0) 1299fcf5ef2aSThomas Huth 1300fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 13019f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 13029f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 13039f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1304fcf5ef2aSThomas Huth #else 13059f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1306fcf5ef2aSThomas Huth do { \ 1307fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 13089f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1309fcf5ef2aSThomas Huth } \ 1310fcf5ef2aSThomas Huth } while (0) 13119f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1312fcf5ef2aSThomas Huth do { \ 1313fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13149f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1315fcf5ef2aSThomas Huth } \ 1316fcf5ef2aSThomas Huth } while (0) 13179f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1318fcf5ef2aSThomas Huth do { \ 1319fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13209f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1321fcf5ef2aSThomas Huth } \ 1322fcf5ef2aSThomas Huth } while (0) 1323fcf5ef2aSThomas Huth #endif 1324fcf5ef2aSThomas Huth 13259f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1326fcf5ef2aSThomas Huth 1327fcf5ef2aSThomas Huth /*****************************************************************************/ 1328fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1329fcf5ef2aSThomas Huth 1330fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1331fcf5ef2aSThomas Huth { \ 1332fcf5ef2aSThomas Huth .opc1 = op1, \ 1333fcf5ef2aSThomas Huth .opc2 = op2, \ 1334fcf5ef2aSThomas Huth .opc3 = op3, \ 1335fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1336fcf5ef2aSThomas Huth .handler = { \ 1337fcf5ef2aSThomas Huth .inval1 = invl, \ 1338fcf5ef2aSThomas Huth .type = _typ, \ 1339fcf5ef2aSThomas Huth .type2 = _typ2, \ 1340fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1341fcf5ef2aSThomas Huth }, \ 1342fcf5ef2aSThomas Huth .oname = stringify(name), \ 1343fcf5ef2aSThomas Huth } 1344fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1345fcf5ef2aSThomas Huth { \ 1346fcf5ef2aSThomas Huth .opc1 = op1, \ 1347fcf5ef2aSThomas Huth .opc2 = op2, \ 1348fcf5ef2aSThomas Huth .opc3 = op3, \ 1349fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1350fcf5ef2aSThomas Huth .handler = { \ 1351fcf5ef2aSThomas Huth .inval1 = invl1, \ 1352fcf5ef2aSThomas Huth .inval2 = invl2, \ 1353fcf5ef2aSThomas Huth .type = _typ, \ 1354fcf5ef2aSThomas Huth .type2 = _typ2, \ 1355fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1356fcf5ef2aSThomas Huth }, \ 1357fcf5ef2aSThomas Huth .oname = stringify(name), \ 1358fcf5ef2aSThomas Huth } 1359fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1360fcf5ef2aSThomas Huth { \ 1361fcf5ef2aSThomas Huth .opc1 = op1, \ 1362fcf5ef2aSThomas Huth .opc2 = op2, \ 1363fcf5ef2aSThomas Huth .opc3 = op3, \ 1364fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1365fcf5ef2aSThomas Huth .handler = { \ 1366fcf5ef2aSThomas Huth .inval1 = invl, \ 1367fcf5ef2aSThomas Huth .type = _typ, \ 1368fcf5ef2aSThomas Huth .type2 = _typ2, \ 1369fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1370fcf5ef2aSThomas Huth }, \ 1371fcf5ef2aSThomas Huth .oname = onam, \ 1372fcf5ef2aSThomas Huth } 1373fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1374fcf5ef2aSThomas Huth { \ 1375fcf5ef2aSThomas Huth .opc1 = op1, \ 1376fcf5ef2aSThomas Huth .opc2 = op2, \ 1377fcf5ef2aSThomas Huth .opc3 = op3, \ 1378fcf5ef2aSThomas Huth .opc4 = op4, \ 1379fcf5ef2aSThomas Huth .handler = { \ 1380fcf5ef2aSThomas Huth .inval1 = invl, \ 1381fcf5ef2aSThomas Huth .type = _typ, \ 1382fcf5ef2aSThomas Huth .type2 = _typ2, \ 1383fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1384fcf5ef2aSThomas Huth }, \ 1385fcf5ef2aSThomas Huth .oname = stringify(name), \ 1386fcf5ef2aSThomas Huth } 1387fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1388fcf5ef2aSThomas Huth { \ 1389fcf5ef2aSThomas Huth .opc1 = op1, \ 1390fcf5ef2aSThomas Huth .opc2 = op2, \ 1391fcf5ef2aSThomas Huth .opc3 = op3, \ 1392fcf5ef2aSThomas Huth .opc4 = op4, \ 1393fcf5ef2aSThomas Huth .handler = { \ 1394fcf5ef2aSThomas Huth .inval1 = invl, \ 1395fcf5ef2aSThomas Huth .type = _typ, \ 1396fcf5ef2aSThomas Huth .type2 = _typ2, \ 1397fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1398fcf5ef2aSThomas Huth }, \ 1399fcf5ef2aSThomas Huth .oname = onam, \ 1400fcf5ef2aSThomas Huth } 1401fcf5ef2aSThomas Huth 1402fcf5ef2aSThomas Huth /* Invalid instruction */ 1403fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1404fcf5ef2aSThomas Huth { 1405fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1406fcf5ef2aSThomas Huth } 1407fcf5ef2aSThomas Huth 1408fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1409fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1410fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1411fcf5ef2aSThomas Huth .type = PPC_NONE, 1412fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1413fcf5ef2aSThomas Huth .handler = gen_invalid, 1414fcf5ef2aSThomas Huth }; 1415fcf5ef2aSThomas Huth 1416fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1417fcf5ef2aSThomas Huth 1418fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1419fcf5ef2aSThomas Huth { 1420fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1421b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1422b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1423fcf5ef2aSThomas Huth 1424b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1425b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1426efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1427efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1428b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1429efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1430efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1431b62b3686Spbonzini@redhat.com 1432b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1433fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1434b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1435fcf5ef2aSThomas Huth } 1436fcf5ef2aSThomas Huth 1437fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1438fcf5ef2aSThomas Huth { 14397058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1440fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1441fcf5ef2aSThomas Huth } 1442fcf5ef2aSThomas Huth 1443fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1444fcf5ef2aSThomas Huth { 1445fcf5ef2aSThomas Huth TCGv t0, t1; 1446fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1447fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1448fcf5ef2aSThomas Huth if (s) { 1449fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1450fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1451fcf5ef2aSThomas Huth } else { 1452fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1453fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1454fcf5ef2aSThomas Huth } 1455fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1456fcf5ef2aSThomas Huth } 1457fcf5ef2aSThomas Huth 1458fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1459fcf5ef2aSThomas Huth { 14607058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1461fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1462fcf5ef2aSThomas Huth } 1463fcf5ef2aSThomas Huth 1464fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1465fcf5ef2aSThomas Huth { 1466fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1467fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1468fcf5ef2aSThomas Huth } else { 1469fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1470fcf5ef2aSThomas Huth } 1471fcf5ef2aSThomas Huth } 1472fcf5ef2aSThomas Huth 1473fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1474fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1475fcf5ef2aSThomas Huth { 1476fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1477fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1478fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1479fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1480fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1481fcf5ef2aSThomas Huth 1482fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1483fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1484fcf5ef2aSThomas Huth 1485fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1486fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1487fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1488fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1489fcf5ef2aSThomas Huth 1490fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1491fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1492fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1493fcf5ef2aSThomas Huth 1494fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1495fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1496fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1497fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1498fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1499fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1500fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1501fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1502fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1503fcf5ef2aSThomas Huth } 1504efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1505fcf5ef2aSThomas Huth } 1506fcf5ef2aSThomas Huth 1507fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1508fcf5ef2aSThomas Huth /* cmpeqb */ 1509fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1510fcf5ef2aSThomas Huth { 1511fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1512fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1513fcf5ef2aSThomas Huth } 1514fcf5ef2aSThomas Huth #endif 1515fcf5ef2aSThomas Huth 1516fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1517fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1518fcf5ef2aSThomas Huth { 1519fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1520fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1521fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1522fcf5ef2aSThomas Huth TCGv zr; 1523fcf5ef2aSThomas Huth 1524fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1525fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1526fcf5ef2aSThomas Huth 15277058ff52SRichard Henderson zr = tcg_constant_tl(0); 1528fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1529fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1530fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1531fcf5ef2aSThomas Huth } 1532fcf5ef2aSThomas Huth 1533fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1534fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1535fcf5ef2aSThomas Huth { 1536fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1537fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1538fcf5ef2aSThomas Huth } 1539fcf5ef2aSThomas Huth 1540fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1541fcf5ef2aSThomas Huth 1542fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1543fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1544fcf5ef2aSThomas Huth { 1545fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1546fcf5ef2aSThomas Huth 1547fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1548fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1549fcf5ef2aSThomas Huth if (sub) { 1550fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1551fcf5ef2aSThomas Huth } else { 1552fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1553fcf5ef2aSThomas Huth } 1554fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1555dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1556dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1557dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1558fcf5ef2aSThomas Huth } 1559dc0ad844SNikunj A Dadhania } else { 1560dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1561dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1562dc0ad844SNikunj A Dadhania } 156338a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1564dc0ad844SNikunj A Dadhania } 1565fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1566fcf5ef2aSThomas Huth } 1567fcf5ef2aSThomas Huth 15686b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15696b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15704c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15716b10d008SNikunj A Dadhania { 15726b10d008SNikunj A Dadhania TCGv t0; 15736b10d008SNikunj A Dadhania 15746b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 15756b10d008SNikunj A Dadhania return; 15766b10d008SNikunj A Dadhania } 15776b10d008SNikunj A Dadhania 15786b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 157933903d0aSNikunj A Dadhania if (sub) { 158033903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 158133903d0aSNikunj A Dadhania } else { 15826b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 158333903d0aSNikunj A Dadhania } 15846b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 15854c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 15866b10d008SNikunj A Dadhania } 15876b10d008SNikunj A Dadhania 1588fcf5ef2aSThomas Huth /* Common add function */ 1589fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 15904c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 15914c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1592fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1593fcf5ef2aSThomas Huth { 1594fcf5ef2aSThomas Huth TCGv t0 = ret; 1595fcf5ef2aSThomas Huth 1596fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1597fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1598fcf5ef2aSThomas Huth } 1599fcf5ef2aSThomas Huth 1600fcf5ef2aSThomas Huth if (compute_ca) { 1601fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1602efe843d8SDavid Gibson /* 1603efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1604efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1605efe843d8SDavid Gibson * produce the carry into bit 32. 1606efe843d8SDavid Gibson */ 1607fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1608fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1609fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1610fcf5ef2aSThomas Huth if (add_ca) { 16114c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1612fcf5ef2aSThomas Huth } 16134c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 16144c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16156b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16164c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16176b10d008SNikunj A Dadhania } 1618fcf5ef2aSThomas Huth } else { 16197058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 1620fcf5ef2aSThomas Huth if (add_ca) { 16214c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16224c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1623fcf5ef2aSThomas Huth } else { 16244c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1625fcf5ef2aSThomas Huth } 16264c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1627fcf5ef2aSThomas Huth } 1628fcf5ef2aSThomas Huth } else { 1629fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1630fcf5ef2aSThomas Huth if (add_ca) { 16314c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1632fcf5ef2aSThomas Huth } 1633fcf5ef2aSThomas Huth } 1634fcf5ef2aSThomas Huth 1635fcf5ef2aSThomas Huth if (compute_ov) { 1636fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1637fcf5ef2aSThomas Huth } 1638fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1639fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1640fcf5ef2aSThomas Huth } 1641fcf5ef2aSThomas Huth 164211f4e8f8SRichard Henderson if (t0 != ret) { 1643fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1644fcf5ef2aSThomas Huth } 1645fcf5ef2aSThomas Huth } 1646fcf5ef2aSThomas Huth /* Add functions with two operands */ 16474c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1648fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1649fcf5ef2aSThomas Huth { \ 1650fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1651fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16524c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1653fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1654fcf5ef2aSThomas Huth } 1655fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16564c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1657fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1658fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1659fcf5ef2aSThomas Huth { \ 16607058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 1661fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1662fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16634c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1664fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1665fcf5ef2aSThomas Huth } 1666fcf5ef2aSThomas Huth 1667fcf5ef2aSThomas Huth /* add add. addo addo. */ 16684c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16694c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1670fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16714c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16724c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1673fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 16744c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 16754c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1676fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 16774c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 16784c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 16794c5920afSSuraj Jitindar Singh /* addex */ 16804c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1681fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 16824c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 16834c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1684fcf5ef2aSThomas Huth /* addic addic.*/ 1685fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1686fcf5ef2aSThomas Huth { 16877058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1688fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 16894c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1690fcf5ef2aSThomas Huth } 1691fcf5ef2aSThomas Huth 1692fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1693fcf5ef2aSThomas Huth { 1694fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1695fcf5ef2aSThomas Huth } 1696fcf5ef2aSThomas Huth 1697fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1698fcf5ef2aSThomas Huth { 1699fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1700fcf5ef2aSThomas Huth } 1701fcf5ef2aSThomas Huth 1702fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1703fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1704fcf5ef2aSThomas Huth { 1705fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1706fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1707fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1708fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1709fcf5ef2aSThomas Huth 1710fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1711fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1712fcf5ef2aSThomas Huth if (sign) { 1713fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1714fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1715fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1716fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1717fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1718fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1719fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1720fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1721fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1722fcf5ef2aSThomas Huth } else { 1723fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1724fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1725fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1726fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1727fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1728fcf5ef2aSThomas Huth } 1729fcf5ef2aSThomas Huth if (compute_ov) { 1730fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1731c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1732c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1733c44027ffSNikunj A Dadhania } 1734fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1735fcf5ef2aSThomas Huth } 1736fcf5ef2aSThomas Huth 1737efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1738fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1739fcf5ef2aSThomas Huth } 1740efe843d8SDavid Gibson } 1741fcf5ef2aSThomas Huth /* Div functions */ 1742fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1743fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1744fcf5ef2aSThomas Huth { \ 1745fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1746fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1747fcf5ef2aSThomas Huth sign, compute_ov); \ 1748fcf5ef2aSThomas Huth } 1749fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1750fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1751fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1752fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1753fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1754fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1755fcf5ef2aSThomas Huth 1756fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1757fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1758fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1759fcf5ef2aSThomas Huth { \ 17607058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1761fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1762fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1763fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1764fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1765fcf5ef2aSThomas Huth } \ 1766fcf5ef2aSThomas Huth } 1767fcf5ef2aSThomas Huth 1768fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1769fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1770fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1771fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1772fcf5ef2aSThomas Huth 1773fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1774fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1775fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1776fcf5ef2aSThomas Huth { 1777fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1778fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1779fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1780fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1781fcf5ef2aSThomas Huth 1782fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1783fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1784fcf5ef2aSThomas Huth if (sign) { 1785fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1786fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1787fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1788fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1789fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1790fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1791fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1792fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1793fcf5ef2aSThomas Huth } else { 1794fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1795fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1796fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1797fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1798fcf5ef2aSThomas Huth } 1799fcf5ef2aSThomas Huth if (compute_ov) { 1800fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1801c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1802c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1803c44027ffSNikunj A Dadhania } 1804fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1805fcf5ef2aSThomas Huth } 1806fcf5ef2aSThomas Huth 1807efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1808fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1809fcf5ef2aSThomas Huth } 1810efe843d8SDavid Gibson } 1811fcf5ef2aSThomas Huth 1812fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1813fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1814fcf5ef2aSThomas Huth { \ 1815fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1816fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1817fcf5ef2aSThomas Huth sign, compute_ov); \ 1818fcf5ef2aSThomas Huth } 1819c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1820fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1821fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1822c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1823fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1824fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1825fcf5ef2aSThomas Huth 1826fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1827fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1828fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1829fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1830fcf5ef2aSThomas Huth #endif 1831fcf5ef2aSThomas Huth 1832fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1833fcf5ef2aSThomas Huth TCGv arg2, int sign) 1834fcf5ef2aSThomas Huth { 1835fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1836fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1837fcf5ef2aSThomas Huth 1838fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1839fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1840fcf5ef2aSThomas Huth if (sign) { 1841fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1842fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1843fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1844fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1845fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1846fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1847fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1848fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1849fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1850fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1851fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1852fcf5ef2aSThomas Huth } else { 18537058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(1); 18547058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(0); 1855fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1856a253231fSRichard Henderson tcg_gen_remu_i32(t0, t0, t1); 1857a253231fSRichard Henderson tcg_gen_extu_i32_tl(ret, t0); 1858fcf5ef2aSThomas Huth } 1859fcf5ef2aSThomas Huth } 1860fcf5ef2aSThomas Huth 1861fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1862fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1863fcf5ef2aSThomas Huth { \ 1864fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1865fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1866fcf5ef2aSThomas Huth sign); \ 1867fcf5ef2aSThomas Huth } 1868fcf5ef2aSThomas Huth 1869fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1870fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1871fcf5ef2aSThomas Huth 1872fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1873fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1874fcf5ef2aSThomas Huth TCGv arg2, int sign) 1875fcf5ef2aSThomas Huth { 1876fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1877fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1878fcf5ef2aSThomas Huth 1879fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1880fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1881fcf5ef2aSThomas Huth if (sign) { 1882fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1883fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1884fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1885fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1886fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1887fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1888fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1889fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1890fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1891fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1892fcf5ef2aSThomas Huth } else { 18937058ff52SRichard Henderson TCGv_i64 t2 = tcg_constant_i64(1); 18947058ff52SRichard Henderson TCGv_i64 t3 = tcg_constant_i64(0); 1895fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1896fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1897fcf5ef2aSThomas Huth } 1898fcf5ef2aSThomas Huth } 1899fcf5ef2aSThomas Huth 1900fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1901fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1902fcf5ef2aSThomas Huth { \ 1903fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1904fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1905fcf5ef2aSThomas Huth sign); \ 1906fcf5ef2aSThomas Huth } 1907fcf5ef2aSThomas Huth 1908fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1909fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1910fcf5ef2aSThomas Huth #endif 1911fcf5ef2aSThomas Huth 1912fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1913fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1914fcf5ef2aSThomas Huth { 1915fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1916fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1917fcf5ef2aSThomas Huth 1918fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1919fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1920fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1921fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1922efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1923fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1924fcf5ef2aSThomas Huth } 1925efe843d8SDavid Gibson } 1926fcf5ef2aSThomas Huth 1927fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1928fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1929fcf5ef2aSThomas Huth { 1930fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1931fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1932fcf5ef2aSThomas Huth 1933fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1934fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1935fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1936fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1937efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1938fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1939fcf5ef2aSThomas Huth } 1940efe843d8SDavid Gibson } 1941fcf5ef2aSThomas Huth 1942fcf5ef2aSThomas Huth /* mullw mullw. */ 1943fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1944fcf5ef2aSThomas Huth { 1945fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1946fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1947fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1948fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1949fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1950fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1951fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1952fcf5ef2aSThomas Huth #else 1953fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1954fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1955fcf5ef2aSThomas Huth #endif 1956efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1957fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1958fcf5ef2aSThomas Huth } 1959efe843d8SDavid Gibson } 1960fcf5ef2aSThomas Huth 1961fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1962fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1963fcf5ef2aSThomas Huth { 1964fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1965fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1966fcf5ef2aSThomas Huth 1967fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1968fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1969fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1970fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1971fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1972fcf5ef2aSThomas Huth #else 1973fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1974fcf5ef2aSThomas Huth #endif 1975fcf5ef2aSThomas Huth 1976fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1977fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1978fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 197961aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 198061aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 198161aa9a69SNikunj A Dadhania } 1982fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1983fcf5ef2aSThomas Huth 1984efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1985fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1986fcf5ef2aSThomas Huth } 1987efe843d8SDavid Gibson } 1988fcf5ef2aSThomas Huth 1989fcf5ef2aSThomas Huth /* mulli */ 1990fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1991fcf5ef2aSThomas Huth { 1992fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1993fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1994fcf5ef2aSThomas Huth } 1995fcf5ef2aSThomas Huth 1996fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1997fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1998fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1999fcf5ef2aSThomas Huth { 2000fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2001fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2002fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2003fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2004fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2005fcf5ef2aSThomas Huth } 2006fcf5ef2aSThomas Huth } 2007fcf5ef2aSThomas Huth 2008fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2009fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2010fcf5ef2aSThomas Huth { 2011fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2012fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2013fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2014fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2015fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2016fcf5ef2aSThomas Huth } 2017fcf5ef2aSThomas Huth } 2018fcf5ef2aSThomas Huth 2019fcf5ef2aSThomas Huth /* mulld mulld. */ 2020fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2021fcf5ef2aSThomas Huth { 2022fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2023fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2024efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2025fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2026fcf5ef2aSThomas Huth } 2027efe843d8SDavid Gibson } 2028fcf5ef2aSThomas Huth 2029fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2030fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2031fcf5ef2aSThomas Huth { 2032fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2033fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2034fcf5ef2aSThomas Huth 2035fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2036fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2037fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2038fcf5ef2aSThomas Huth 2039fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2040fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 204161aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 204261aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 204361aa9a69SNikunj A Dadhania } 2044fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2045fcf5ef2aSThomas Huth 2046fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2047fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2048fcf5ef2aSThomas Huth } 2049fcf5ef2aSThomas Huth } 2050fcf5ef2aSThomas Huth #endif 2051fcf5ef2aSThomas Huth 2052fcf5ef2aSThomas Huth /* Common subf function */ 2053fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2054fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2055fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2056fcf5ef2aSThomas Huth { 2057fcf5ef2aSThomas Huth TCGv t0 = ret; 2058fcf5ef2aSThomas Huth 2059fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2060fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2061fcf5ef2aSThomas Huth } 2062fcf5ef2aSThomas Huth 2063fcf5ef2aSThomas Huth if (compute_ca) { 2064fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2065fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2066efe843d8SDavid Gibson /* 2067efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2068efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2069efe843d8SDavid Gibson * produce the carry into bit 32. 2070efe843d8SDavid Gibson */ 2071fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2072fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2073fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2074fcf5ef2aSThomas Huth if (add_ca) { 2075fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2076fcf5ef2aSThomas Huth } else { 2077fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2078fcf5ef2aSThomas Huth } 2079fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2080fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2081fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2082e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 208333903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 208433903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 208533903d0aSNikunj A Dadhania } 2086fcf5ef2aSThomas Huth } else if (add_ca) { 2087fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2088fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 20897058ff52SRichard Henderson zero = tcg_constant_tl(0); 2090fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2091fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 20924c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2093fcf5ef2aSThomas Huth } else { 2094fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2095fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 20964c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2097fcf5ef2aSThomas Huth } 2098fcf5ef2aSThomas Huth } else if (add_ca) { 2099efe843d8SDavid Gibson /* 2100efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2101efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2102efe843d8SDavid Gibson */ 2103fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2104fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2105fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2106fcf5ef2aSThomas Huth } else { 2107fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2108fcf5ef2aSThomas Huth } 2109fcf5ef2aSThomas Huth 2110fcf5ef2aSThomas Huth if (compute_ov) { 2111fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2112fcf5ef2aSThomas Huth } 2113fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2114fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2115fcf5ef2aSThomas Huth } 2116fcf5ef2aSThomas Huth 211711f4e8f8SRichard Henderson if (t0 != ret) { 2118fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2119fcf5ef2aSThomas Huth } 2120fcf5ef2aSThomas Huth } 2121fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2122fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2123fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2124fcf5ef2aSThomas Huth { \ 2125fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2126fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2127fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2128fcf5ef2aSThomas Huth } 2129fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2130fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2131fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2132fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2133fcf5ef2aSThomas Huth { \ 21347058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 2135fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2136fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2137fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2138fcf5ef2aSThomas Huth } 2139fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2140fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2141fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2142fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2143fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2144fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2145fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2146fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2147fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2148fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2149fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2150fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2151fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2152fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2153fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2154fcf5ef2aSThomas Huth 2155fcf5ef2aSThomas Huth /* subfic */ 2156fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2157fcf5ef2aSThomas Huth { 21587058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2159fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2160fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2161fcf5ef2aSThomas Huth } 2162fcf5ef2aSThomas Huth 2163fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2164fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2165fcf5ef2aSThomas Huth { 21667058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 2167fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2168fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2169fcf5ef2aSThomas Huth } 2170fcf5ef2aSThomas Huth 2171fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2172fcf5ef2aSThomas Huth { 21731480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 21741480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 21751480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 21761480d71cSNikunj A Dadhania } 2177fcf5ef2aSThomas Huth } 2178fcf5ef2aSThomas Huth 2179fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2180fcf5ef2aSThomas Huth { 2181fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2182fcf5ef2aSThomas Huth } 2183fcf5ef2aSThomas Huth 2184fcf5ef2aSThomas Huth /*** Integer logical ***/ 2185fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2186fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2187fcf5ef2aSThomas Huth { \ 2188fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2189fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2190fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2191fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2192fcf5ef2aSThomas Huth } 2193fcf5ef2aSThomas Huth 2194fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2195fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2196fcf5ef2aSThomas Huth { \ 2197fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2198fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2199fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2200fcf5ef2aSThomas Huth } 2201fcf5ef2aSThomas Huth 2202fcf5ef2aSThomas Huth /* and & and. */ 2203fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2204fcf5ef2aSThomas Huth /* andc & andc. */ 2205fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2206fcf5ef2aSThomas Huth 2207fcf5ef2aSThomas Huth /* andi. */ 2208fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2209fcf5ef2aSThomas Huth { 2210efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2211efe843d8SDavid Gibson UIMM(ctx->opcode)); 2212fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2213fcf5ef2aSThomas Huth } 2214fcf5ef2aSThomas Huth 2215fcf5ef2aSThomas Huth /* andis. */ 2216fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2217fcf5ef2aSThomas Huth { 2218efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2219efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2220fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2221fcf5ef2aSThomas Huth } 2222fcf5ef2aSThomas Huth 2223fcf5ef2aSThomas Huth /* cntlzw */ 2224fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2225fcf5ef2aSThomas Huth { 22269b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22279b8514e5SRichard Henderson 22289b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22299b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22309b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22319b8514e5SRichard Henderson 2232efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2233fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2234fcf5ef2aSThomas Huth } 2235efe843d8SDavid Gibson } 2236fcf5ef2aSThomas Huth 2237fcf5ef2aSThomas Huth /* cnttzw */ 2238fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2239fcf5ef2aSThomas Huth { 22409b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22419b8514e5SRichard Henderson 22429b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22439b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22449b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22459b8514e5SRichard Henderson 2246fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2247fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2248fcf5ef2aSThomas Huth } 2249fcf5ef2aSThomas Huth } 2250fcf5ef2aSThomas Huth 2251fcf5ef2aSThomas Huth /* eqv & eqv. */ 2252fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2253fcf5ef2aSThomas Huth /* extsb & extsb. */ 2254fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2255fcf5ef2aSThomas Huth /* extsh & extsh. */ 2256fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2257fcf5ef2aSThomas Huth /* nand & nand. */ 2258fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2259fcf5ef2aSThomas Huth /* nor & nor. */ 2260fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2261fcf5ef2aSThomas Huth 2262fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2263fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2264fcf5ef2aSThomas Huth { 22657058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(0); 2266fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2267fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2268fcf5ef2aSThomas Huth 2269fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2270b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2271fcf5ef2aSThomas Huth } 2272fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2273fcf5ef2aSThomas Huth 2274fcf5ef2aSThomas Huth /* or & or. */ 2275fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2276fcf5ef2aSThomas Huth { 2277fcf5ef2aSThomas Huth int rs, ra, rb; 2278fcf5ef2aSThomas Huth 2279fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2280fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2281fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2282fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2283fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2284efe843d8SDavid Gibson if (rs != rb) { 2285fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2286efe843d8SDavid Gibson } else { 2287fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2288efe843d8SDavid Gibson } 2289efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2290fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2291efe843d8SDavid Gibson } 2292fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2293fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2294fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2295fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2296fcf5ef2aSThomas Huth int prio = 0; 2297fcf5ef2aSThomas Huth 2298fcf5ef2aSThomas Huth switch (rs) { 2299fcf5ef2aSThomas Huth case 1: 2300fcf5ef2aSThomas Huth /* Set process priority to low */ 2301fcf5ef2aSThomas Huth prio = 2; 2302fcf5ef2aSThomas Huth break; 2303fcf5ef2aSThomas Huth case 6: 2304fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2305fcf5ef2aSThomas Huth prio = 3; 2306fcf5ef2aSThomas Huth break; 2307fcf5ef2aSThomas Huth case 2: 2308fcf5ef2aSThomas Huth /* Set process priority to normal */ 2309fcf5ef2aSThomas Huth prio = 4; 2310fcf5ef2aSThomas Huth break; 2311fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2312fcf5ef2aSThomas Huth case 31: 2313fcf5ef2aSThomas Huth if (!ctx->pr) { 2314fcf5ef2aSThomas Huth /* Set process priority to very low */ 2315fcf5ef2aSThomas Huth prio = 1; 2316fcf5ef2aSThomas Huth } 2317fcf5ef2aSThomas Huth break; 2318fcf5ef2aSThomas Huth case 5: 2319fcf5ef2aSThomas Huth if (!ctx->pr) { 2320fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2321fcf5ef2aSThomas Huth prio = 5; 2322fcf5ef2aSThomas Huth } 2323fcf5ef2aSThomas Huth break; 2324fcf5ef2aSThomas Huth case 3: 2325fcf5ef2aSThomas Huth if (!ctx->pr) { 2326fcf5ef2aSThomas Huth /* Set process priority to high */ 2327fcf5ef2aSThomas Huth prio = 6; 2328fcf5ef2aSThomas Huth } 2329fcf5ef2aSThomas Huth break; 2330fcf5ef2aSThomas Huth case 7: 2331fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2332fcf5ef2aSThomas Huth /* Set process priority to very high */ 2333fcf5ef2aSThomas Huth prio = 7; 2334fcf5ef2aSThomas Huth } 2335fcf5ef2aSThomas Huth break; 2336fcf5ef2aSThomas Huth #endif 2337fcf5ef2aSThomas Huth default: 2338fcf5ef2aSThomas Huth break; 2339fcf5ef2aSThomas Huth } 2340fcf5ef2aSThomas Huth if (prio) { 2341fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2342fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2343fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2344fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2345fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2346fcf5ef2aSThomas Huth } 2347fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2348efe843d8SDavid Gibson /* 2349efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2350efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2351efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2352efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2353fcf5ef2aSThomas Huth */ 2354fcf5ef2aSThomas Huth gen_pause(ctx); 2355fcf5ef2aSThomas Huth #endif 2356fcf5ef2aSThomas Huth #endif 2357fcf5ef2aSThomas Huth } 2358fcf5ef2aSThomas Huth } 2359fcf5ef2aSThomas Huth /* orc & orc. */ 2360fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2361fcf5ef2aSThomas Huth 2362fcf5ef2aSThomas Huth /* xor & xor. */ 2363fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2364fcf5ef2aSThomas Huth { 2365fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2366efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2367efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2368efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2369efe843d8SDavid Gibson } else { 2370fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2371efe843d8SDavid Gibson } 2372efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2373fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2374fcf5ef2aSThomas Huth } 2375efe843d8SDavid Gibson } 2376fcf5ef2aSThomas Huth 2377fcf5ef2aSThomas Huth /* ori */ 2378fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2379fcf5ef2aSThomas Huth { 2380fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2381fcf5ef2aSThomas Huth 2382fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2383fcf5ef2aSThomas Huth return; 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2386fcf5ef2aSThomas Huth } 2387fcf5ef2aSThomas Huth 2388fcf5ef2aSThomas Huth /* oris */ 2389fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2390fcf5ef2aSThomas Huth { 2391fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2392fcf5ef2aSThomas Huth 2393fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2394fcf5ef2aSThomas Huth /* NOP */ 2395fcf5ef2aSThomas Huth return; 2396fcf5ef2aSThomas Huth } 2397efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2398efe843d8SDavid Gibson uimm << 16); 2399fcf5ef2aSThomas Huth } 2400fcf5ef2aSThomas Huth 2401fcf5ef2aSThomas Huth /* xori */ 2402fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2403fcf5ef2aSThomas Huth { 2404fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2405fcf5ef2aSThomas Huth 2406fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2407fcf5ef2aSThomas Huth /* NOP */ 2408fcf5ef2aSThomas Huth return; 2409fcf5ef2aSThomas Huth } 2410fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2411fcf5ef2aSThomas Huth } 2412fcf5ef2aSThomas Huth 2413fcf5ef2aSThomas Huth /* xoris */ 2414fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2415fcf5ef2aSThomas Huth { 2416fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2417fcf5ef2aSThomas Huth 2418fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2419fcf5ef2aSThomas Huth /* NOP */ 2420fcf5ef2aSThomas Huth return; 2421fcf5ef2aSThomas Huth } 2422efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2423efe843d8SDavid Gibson uimm << 16); 2424fcf5ef2aSThomas Huth } 2425fcf5ef2aSThomas Huth 2426fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2427fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2428fcf5ef2aSThomas Huth { 2429fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2430fcf5ef2aSThomas Huth } 2431fcf5ef2aSThomas Huth 2432fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2433fcf5ef2aSThomas Huth { 243479770002SRichard Henderson #if defined(TARGET_PPC64) 2435fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 243679770002SRichard Henderson #else 243779770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 243879770002SRichard Henderson #endif 2439fcf5ef2aSThomas Huth } 2440fcf5ef2aSThomas Huth 2441fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2442fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2443fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2444fcf5ef2aSThomas Huth { 244579770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2446fcf5ef2aSThomas Huth } 2447fcf5ef2aSThomas Huth #endif 2448fcf5ef2aSThomas Huth 2449fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2450fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2451fcf5ef2aSThomas Huth { 2452fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2453fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2454fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2455fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2456fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2457fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2458fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2459fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2460fcf5ef2aSThomas Huth } 2461fcf5ef2aSThomas Huth 2462fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2463fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2464fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2465fcf5ef2aSThomas Huth { 2466fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2467fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2468fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2469fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2470fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2471fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2472fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2473fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2474fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2475fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2476fcf5ef2aSThomas Huth } 2477fcf5ef2aSThomas Huth #endif 2478fcf5ef2aSThomas Huth 2479fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2480fcf5ef2aSThomas Huth /* bpermd */ 2481fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2482fcf5ef2aSThomas Huth { 2483fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2484fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2485fcf5ef2aSThomas Huth } 2486fcf5ef2aSThomas Huth #endif 2487fcf5ef2aSThomas Huth 2488fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2489fcf5ef2aSThomas Huth /* extsw & extsw. */ 2490fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2491fcf5ef2aSThomas Huth 2492fcf5ef2aSThomas Huth /* cntlzd */ 2493fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2494fcf5ef2aSThomas Huth { 24959b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2496efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2497fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2498fcf5ef2aSThomas Huth } 2499efe843d8SDavid Gibson } 2500fcf5ef2aSThomas Huth 2501fcf5ef2aSThomas Huth /* cnttzd */ 2502fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2503fcf5ef2aSThomas Huth { 25049b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2505fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2506fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2507fcf5ef2aSThomas Huth } 2508fcf5ef2aSThomas Huth } 2509fcf5ef2aSThomas Huth 2510fcf5ef2aSThomas Huth /* darn */ 2511fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2512fcf5ef2aSThomas Huth { 2513fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2514fcf5ef2aSThomas Huth 25157e4357f6SRichard Henderson if (l > 2) { 25167e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25177e4357f6SRichard Henderson } else { 2518283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 2519fcf5ef2aSThomas Huth if (l == 0) { 2520fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25217e4357f6SRichard Henderson } else { 2522fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2523fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25247e4357f6SRichard Henderson } 2525fcf5ef2aSThomas Huth } 2526fcf5ef2aSThomas Huth } 2527fcf5ef2aSThomas Huth #endif 2528fcf5ef2aSThomas Huth 2529fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2530fcf5ef2aSThomas Huth 2531fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2532fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2533fcf5ef2aSThomas Huth { 2534fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2535fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2536fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2537fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2538fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2539fcf5ef2aSThomas Huth 2540fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2541fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2542fcf5ef2aSThomas Huth } else { 2543fcf5ef2aSThomas Huth target_ulong mask; 2544c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2545fcf5ef2aSThomas Huth TCGv t1; 2546fcf5ef2aSThomas Huth 2547fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2548fcf5ef2aSThomas Huth mb += 32; 2549fcf5ef2aSThomas Huth me += 32; 2550fcf5ef2aSThomas Huth #endif 2551fcf5ef2aSThomas Huth mask = MASK(mb, me); 2552fcf5ef2aSThomas Huth 2553c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2554c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2555c4f6a4a3SDaniele Buono mask_in_32b = false; 2556c4f6a4a3SDaniele Buono } 2557c4f6a4a3SDaniele Buono #endif 2558fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2559c4f6a4a3SDaniele Buono if (mask_in_32b) { 2560fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2561fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2562fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2563fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2564fcf5ef2aSThomas Huth } else { 2565fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2566fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2567fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2568fcf5ef2aSThomas Huth #else 2569fcf5ef2aSThomas Huth g_assert_not_reached(); 2570fcf5ef2aSThomas Huth #endif 2571fcf5ef2aSThomas Huth } 2572fcf5ef2aSThomas Huth 2573fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2574fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2575fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2576fcf5ef2aSThomas Huth } 2577fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2578fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2579fcf5ef2aSThomas Huth } 2580fcf5ef2aSThomas Huth } 2581fcf5ef2aSThomas Huth 2582fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2583fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2584fcf5ef2aSThomas Huth { 2585fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2586fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 25877b4d326fSRichard Henderson int sh = SH(ctx->opcode); 25887b4d326fSRichard Henderson int mb = MB(ctx->opcode); 25897b4d326fSRichard Henderson int me = ME(ctx->opcode); 25907b4d326fSRichard Henderson int len = me - mb + 1; 25917b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2592fcf5ef2aSThomas Huth 25937b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 25947b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 25957b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 25967b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2597fcf5ef2aSThomas Huth } else { 2598fcf5ef2aSThomas Huth target_ulong mask; 2599c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2600fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2601fcf5ef2aSThomas Huth mb += 32; 2602fcf5ef2aSThomas Huth me += 32; 2603fcf5ef2aSThomas Huth #endif 2604fcf5ef2aSThomas Huth mask = MASK(mb, me); 2605c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2606c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2607c4f6a4a3SDaniele Buono mask_in_32b = false; 2608c4f6a4a3SDaniele Buono } 2609c4f6a4a3SDaniele Buono #endif 2610c4f6a4a3SDaniele Buono if (mask_in_32b) { 26117b4d326fSRichard Henderson if (sh == 0) { 26127b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 261394f040aaSVitaly Chikunov } else { 2614fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2615fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2616fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2617fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2618fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 261994f040aaSVitaly Chikunov } 2620fcf5ef2aSThomas Huth } else { 2621fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2622fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2623fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2624fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2625fcf5ef2aSThomas Huth #else 2626fcf5ef2aSThomas Huth g_assert_not_reached(); 2627fcf5ef2aSThomas Huth #endif 2628fcf5ef2aSThomas Huth } 2629fcf5ef2aSThomas Huth } 2630fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2631fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2632fcf5ef2aSThomas Huth } 2633fcf5ef2aSThomas Huth } 2634fcf5ef2aSThomas Huth 2635fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2636fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2637fcf5ef2aSThomas Huth { 2638fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2639fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2640fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2641fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2642fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2643fcf5ef2aSThomas Huth target_ulong mask; 2644c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2645fcf5ef2aSThomas Huth 2646fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2647fcf5ef2aSThomas Huth mb += 32; 2648fcf5ef2aSThomas Huth me += 32; 2649fcf5ef2aSThomas Huth #endif 2650fcf5ef2aSThomas Huth mask = MASK(mb, me); 2651fcf5ef2aSThomas Huth 2652c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2653c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2654c4f6a4a3SDaniele Buono mask_in_32b = false; 2655c4f6a4a3SDaniele Buono } 2656c4f6a4a3SDaniele Buono #endif 2657c4f6a4a3SDaniele Buono if (mask_in_32b) { 2658fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2659fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2660fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2661fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2662fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2663fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2664fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2665fcf5ef2aSThomas Huth } else { 2666fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2667fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2668fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2669fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2670fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2671fcf5ef2aSThomas Huth #else 2672fcf5ef2aSThomas Huth g_assert_not_reached(); 2673fcf5ef2aSThomas Huth #endif 2674fcf5ef2aSThomas Huth } 2675fcf5ef2aSThomas Huth 2676fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2677fcf5ef2aSThomas Huth 2678fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2679fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2680fcf5ef2aSThomas Huth } 2681fcf5ef2aSThomas Huth } 2682fcf5ef2aSThomas Huth 2683fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2684fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2685fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2686fcf5ef2aSThomas Huth { \ 2687fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2688fcf5ef2aSThomas Huth } \ 2689fcf5ef2aSThomas Huth \ 2690fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2691fcf5ef2aSThomas Huth { \ 2692fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2693fcf5ef2aSThomas Huth } 2694fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2695fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2696fcf5ef2aSThomas Huth { \ 2697fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2698fcf5ef2aSThomas Huth } \ 2699fcf5ef2aSThomas Huth \ 2700fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2701fcf5ef2aSThomas Huth { \ 2702fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2703fcf5ef2aSThomas Huth } \ 2704fcf5ef2aSThomas Huth \ 2705fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2706fcf5ef2aSThomas Huth { \ 2707fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2708fcf5ef2aSThomas Huth } \ 2709fcf5ef2aSThomas Huth \ 2710fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2711fcf5ef2aSThomas Huth { \ 2712fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2713fcf5ef2aSThomas Huth } 2714fcf5ef2aSThomas Huth 2715fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2716fcf5ef2aSThomas Huth { 2717fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2718fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27197b4d326fSRichard Henderson int len = me - mb + 1; 27207b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2721fcf5ef2aSThomas Huth 27227b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27237b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27247b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27257b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2726fcf5ef2aSThomas Huth } else { 2727fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2728fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2729fcf5ef2aSThomas Huth } 2730fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2731fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2732fcf5ef2aSThomas Huth } 2733fcf5ef2aSThomas Huth } 2734fcf5ef2aSThomas Huth 2735fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2736fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2737fcf5ef2aSThomas Huth { 2738fcf5ef2aSThomas Huth uint32_t sh, mb; 2739fcf5ef2aSThomas Huth 2740fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2741fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2742fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2743fcf5ef2aSThomas Huth } 2744fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2745fcf5ef2aSThomas Huth 2746fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2747fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2748fcf5ef2aSThomas Huth { 2749fcf5ef2aSThomas Huth uint32_t sh, me; 2750fcf5ef2aSThomas Huth 2751fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2752fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2753fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2754fcf5ef2aSThomas Huth } 2755fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2756fcf5ef2aSThomas Huth 2757fcf5ef2aSThomas Huth /* rldic - rldic. */ 2758fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2759fcf5ef2aSThomas Huth { 2760fcf5ef2aSThomas Huth uint32_t sh, mb; 2761fcf5ef2aSThomas Huth 2762fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2763fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2764fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2765fcf5ef2aSThomas Huth } 2766fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2767fcf5ef2aSThomas Huth 2768fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2769fcf5ef2aSThomas Huth { 2770fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2771fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2772fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2773fcf5ef2aSThomas Huth TCGv t0; 2774fcf5ef2aSThomas Huth 2775fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2776fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2777fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2778fcf5ef2aSThomas Huth 2779fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2780fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2781fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2782fcf5ef2aSThomas Huth } 2783fcf5ef2aSThomas Huth } 2784fcf5ef2aSThomas Huth 2785fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2786fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2787fcf5ef2aSThomas Huth { 2788fcf5ef2aSThomas Huth uint32_t mb; 2789fcf5ef2aSThomas Huth 2790fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2791fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2792fcf5ef2aSThomas Huth } 2793fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2794fcf5ef2aSThomas Huth 2795fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2796fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2797fcf5ef2aSThomas Huth { 2798fcf5ef2aSThomas Huth uint32_t me; 2799fcf5ef2aSThomas Huth 2800fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2801fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2802fcf5ef2aSThomas Huth } 2803fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2804fcf5ef2aSThomas Huth 2805fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2806fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2807fcf5ef2aSThomas Huth { 2808fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2809fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2810fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2811fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2812fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2813fcf5ef2aSThomas Huth 2814fcf5ef2aSThomas Huth if (mb <= me) { 2815fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2816fcf5ef2aSThomas Huth } else { 2817fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2818fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2819fcf5ef2aSThomas Huth 2820fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2821fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2822fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2823fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2824fcf5ef2aSThomas Huth } 2825fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2826fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2827fcf5ef2aSThomas Huth } 2828fcf5ef2aSThomas Huth } 2829fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2830fcf5ef2aSThomas Huth #endif 2831fcf5ef2aSThomas Huth 2832fcf5ef2aSThomas Huth /*** Integer shift ***/ 2833fcf5ef2aSThomas Huth 2834fcf5ef2aSThomas Huth /* slw & slw. */ 2835fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2836fcf5ef2aSThomas Huth { 2837fcf5ef2aSThomas Huth TCGv t0, t1; 2838fcf5ef2aSThomas Huth 2839fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2840fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2841fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2842fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2843fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2844fcf5ef2aSThomas Huth #else 2845fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2846fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2847fcf5ef2aSThomas Huth #endif 2848fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2849fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2850fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2851fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2852fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2853efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2854fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2855fcf5ef2aSThomas Huth } 2856efe843d8SDavid Gibson } 2857fcf5ef2aSThomas Huth 2858fcf5ef2aSThomas Huth /* sraw & sraw. */ 2859fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2860fcf5ef2aSThomas Huth { 2861fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2862fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2863efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2864fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2865fcf5ef2aSThomas Huth } 2866efe843d8SDavid Gibson } 2867fcf5ef2aSThomas Huth 2868fcf5ef2aSThomas Huth /* srawi & srawi. */ 2869fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2870fcf5ef2aSThomas Huth { 2871fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2872fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2873fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2874fcf5ef2aSThomas Huth if (sh == 0) { 2875fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2876fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2877af1c259fSSandipan Das if (is_isa300(ctx)) { 2878af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2879af1c259fSSandipan Das } 2880fcf5ef2aSThomas Huth } else { 2881fcf5ef2aSThomas Huth TCGv t0; 2882fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2883fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2884fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2885fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2886fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2887fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2888af1c259fSSandipan Das if (is_isa300(ctx)) { 2889af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2890af1c259fSSandipan Das } 2891fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2892fcf5ef2aSThomas Huth } 2893fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2894fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2895fcf5ef2aSThomas Huth } 2896fcf5ef2aSThomas Huth } 2897fcf5ef2aSThomas Huth 2898fcf5ef2aSThomas Huth /* srw & srw. */ 2899fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2900fcf5ef2aSThomas Huth { 2901fcf5ef2aSThomas Huth TCGv t0, t1; 2902fcf5ef2aSThomas Huth 2903fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2904fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2905fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2906fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2907fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2908fcf5ef2aSThomas Huth #else 2909fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2910fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2911fcf5ef2aSThomas Huth #endif 2912fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2913fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2914fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2915fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2916fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2917efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2918fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2919fcf5ef2aSThomas Huth } 2920efe843d8SDavid Gibson } 2921fcf5ef2aSThomas Huth 2922fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2923fcf5ef2aSThomas Huth /* sld & sld. */ 2924fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2925fcf5ef2aSThomas Huth { 2926fcf5ef2aSThomas Huth TCGv t0, t1; 2927fcf5ef2aSThomas Huth 2928fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2929fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2930fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2931fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2932fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2933fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2934fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2935fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2936efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2937fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2938fcf5ef2aSThomas Huth } 2939efe843d8SDavid Gibson } 2940fcf5ef2aSThomas Huth 2941fcf5ef2aSThomas Huth /* srad & srad. */ 2942fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2943fcf5ef2aSThomas Huth { 2944fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2945fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2946efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2947fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2948fcf5ef2aSThomas Huth } 2949efe843d8SDavid Gibson } 2950fcf5ef2aSThomas Huth /* sradi & sradi. */ 2951fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2952fcf5ef2aSThomas Huth { 2953fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2954fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2955fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2956fcf5ef2aSThomas Huth if (sh == 0) { 2957fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2958fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2959af1c259fSSandipan Das if (is_isa300(ctx)) { 2960af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2961af1c259fSSandipan Das } 2962fcf5ef2aSThomas Huth } else { 2963fcf5ef2aSThomas Huth TCGv t0; 2964fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2965fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2966fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2967fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2968fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2969af1c259fSSandipan Das if (is_isa300(ctx)) { 2970af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2971af1c259fSSandipan Das } 2972fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2973fcf5ef2aSThomas Huth } 2974fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2975fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2976fcf5ef2aSThomas Huth } 2977fcf5ef2aSThomas Huth } 2978fcf5ef2aSThomas Huth 2979fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2980fcf5ef2aSThomas Huth { 2981fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2982fcf5ef2aSThomas Huth } 2983fcf5ef2aSThomas Huth 2984fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2985fcf5ef2aSThomas Huth { 2986fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2987fcf5ef2aSThomas Huth } 2988fcf5ef2aSThomas Huth 2989fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2990fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2991fcf5ef2aSThomas Huth { 2992fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2993fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2994fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2995fcf5ef2aSThomas Huth 2996fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2997fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2998fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2999fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3000fcf5ef2aSThomas Huth } 3001fcf5ef2aSThomas Huth } 3002fcf5ef2aSThomas Huth 3003fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3004fcf5ef2aSThomas Huth { 3005fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3006fcf5ef2aSThomas Huth } 3007fcf5ef2aSThomas Huth 3008fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3009fcf5ef2aSThomas Huth { 3010fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3011fcf5ef2aSThomas Huth } 3012fcf5ef2aSThomas Huth 3013fcf5ef2aSThomas Huth /* srd & srd. */ 3014fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3015fcf5ef2aSThomas Huth { 3016fcf5ef2aSThomas Huth TCGv t0, t1; 3017fcf5ef2aSThomas Huth 3018fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3019fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3020fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3021fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3022fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3023fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3024fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3025fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3026efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3027fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3028fcf5ef2aSThomas Huth } 3029efe843d8SDavid Gibson } 3030fcf5ef2aSThomas Huth #endif 3031fcf5ef2aSThomas Huth 3032fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3033fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3034fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3035fcf5ef2aSThomas Huth target_long maskl) 3036fcf5ef2aSThomas Huth { 3037fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3038fcf5ef2aSThomas Huth 3039fcf5ef2aSThomas Huth simm &= ~maskl; 3040fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3041fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3042fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3043fcf5ef2aSThomas Huth } 3044fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3045fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3046fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3047fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3048fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3049fcf5ef2aSThomas Huth } 3050fcf5ef2aSThomas Huth } else { 3051fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3052fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3053fcf5ef2aSThomas Huth } else { 3054fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3055fcf5ef2aSThomas Huth } 3056fcf5ef2aSThomas Huth } 3057fcf5ef2aSThomas Huth } 3058fcf5ef2aSThomas Huth 3059fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3060fcf5ef2aSThomas Huth { 3061fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3062fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3063fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3064fcf5ef2aSThomas Huth } else { 3065fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3066fcf5ef2aSThomas Huth } 3067fcf5ef2aSThomas Huth } else { 3068fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3069fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3070fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3071fcf5ef2aSThomas Huth } 3072fcf5ef2aSThomas Huth } 3073fcf5ef2aSThomas Huth } 3074fcf5ef2aSThomas Huth 3075fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3076fcf5ef2aSThomas Huth { 3077fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3078fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3079fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3080fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3081fcf5ef2aSThomas Huth } else { 3082fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth } 3085fcf5ef2aSThomas Huth 3086fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3087fcf5ef2aSThomas Huth target_long val) 3088fcf5ef2aSThomas Huth { 3089fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3090fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3091fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3092fcf5ef2aSThomas Huth } 3093fcf5ef2aSThomas Huth } 3094fcf5ef2aSThomas Huth 3095fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3096fcf5ef2aSThomas Huth { 3097fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3098fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3099fcf5ef2aSThomas Huth } 3100fcf5ef2aSThomas Huth 3101eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3102eb63efd9SFernando Eckhardt Valle { 3103eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3104eb63efd9SFernando Eckhardt Valle if (ra) { 3105eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3106eb63efd9SFernando Eckhardt Valle } else { 3107eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3108eb63efd9SFernando Eckhardt Valle } 3109eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3110eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3111eb63efd9SFernando Eckhardt Valle } 3112eb63efd9SFernando Eckhardt Valle return ea; 3113eb63efd9SFernando Eckhardt Valle } 3114eb63efd9SFernando Eckhardt Valle 3115fcf5ef2aSThomas Huth /*** Integer load ***/ 3116fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3117fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3118fcf5ef2aSThomas Huth 3119fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3120fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3121fcf5ef2aSThomas Huth TCGv val, \ 3122fcf5ef2aSThomas Huth TCGv addr) \ 3123fcf5ef2aSThomas Huth { \ 3124fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3125fcf5ef2aSThomas Huth } 3126fcf5ef2aSThomas Huth 3127fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3128fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3129fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3130fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3131fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3132fcf5ef2aSThomas Huth 3133fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3134fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3135fcf5ef2aSThomas Huth 3136fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3137fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3138fcf5ef2aSThomas Huth TCGv_i64 val, \ 3139fcf5ef2aSThomas Huth TCGv addr) \ 3140fcf5ef2aSThomas Huth { \ 3141fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3142fcf5ef2aSThomas Huth } 3143fcf5ef2aSThomas Huth 3144fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3145fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3146fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3147fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3148fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3149fcf5ef2aSThomas Huth 3150fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3151fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3152fcf5ef2aSThomas Huth #endif 3153fcf5ef2aSThomas Huth 3154fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3155fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3156fcf5ef2aSThomas Huth TCGv val, \ 3157fcf5ef2aSThomas Huth TCGv addr) \ 3158fcf5ef2aSThomas Huth { \ 3159fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3160fcf5ef2aSThomas Huth } 3161fcf5ef2aSThomas Huth 3162e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3163fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3164e8f4c8d6SRichard Henderson #endif 3165fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3166fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3167fcf5ef2aSThomas Huth 3168fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3169fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3170fcf5ef2aSThomas Huth 3171fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3172fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3173fcf5ef2aSThomas Huth TCGv_i64 val, \ 3174fcf5ef2aSThomas Huth TCGv addr) \ 3175fcf5ef2aSThomas Huth { \ 3176fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3177fcf5ef2aSThomas Huth } 3178fcf5ef2aSThomas Huth 3179fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3180fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3181fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3182fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3183fcf5ef2aSThomas Huth 3184fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3185fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3186fcf5ef2aSThomas Huth #endif 3187fcf5ef2aSThomas Huth 3188fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3189fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3190fcf5ef2aSThomas Huth { \ 3191fcf5ef2aSThomas Huth TCGv EA; \ 31929f0cf041SMatheus Ferst chk(ctx); \ 3193fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3194fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3195fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3196fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3197fcf5ef2aSThomas Huth } 3198fcf5ef2aSThomas Huth 3199fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3200fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3201fcf5ef2aSThomas Huth 3202fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3203fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3204fcf5ef2aSThomas Huth 320550728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 320650728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 320750728199SRoman Kapl { \ 320850728199SRoman Kapl TCGv EA; \ 32099f0cf041SMatheus Ferst CHK_SV(ctx); \ 321050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 321150728199SRoman Kapl EA = tcg_temp_new(); \ 321250728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 321350728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 321450728199SRoman Kapl } 321550728199SRoman Kapl 321650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 321750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 321850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 321950728199SRoman Kapl #if defined(TARGET_PPC64) 3220fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 322150728199SRoman Kapl #endif 322250728199SRoman Kapl 3223fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3224fcf5ef2aSThomas Huth /* CI load/store variants */ 3225fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3226fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3227fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3228fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3229fcf5ef2aSThomas Huth #endif 3230fcf5ef2aSThomas Huth 3231fcf5ef2aSThomas Huth /*** Integer store ***/ 3232fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3233fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3234fcf5ef2aSThomas Huth { \ 3235fcf5ef2aSThomas Huth TCGv EA; \ 32369f0cf041SMatheus Ferst chk(ctx); \ 3237fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3238fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3239fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3240fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3241fcf5ef2aSThomas Huth } 3242fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3243fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3244fcf5ef2aSThomas Huth 3245fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3246fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3247fcf5ef2aSThomas Huth 324850728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 324950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 325050728199SRoman Kapl { \ 325150728199SRoman Kapl TCGv EA; \ 32529f0cf041SMatheus Ferst CHK_SV(ctx); \ 325350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 325450728199SRoman Kapl EA = tcg_temp_new(); \ 325550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 325650728199SRoman Kapl tcg_gen_qemu_st_tl( \ 325750728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 325850728199SRoman Kapl } 325950728199SRoman Kapl 326050728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 326150728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 326250728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 326350728199SRoman Kapl #if defined(TARGET_PPC64) 3264fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 326550728199SRoman Kapl #endif 326650728199SRoman Kapl 3267fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3268fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3269fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3270fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3271fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3272fcf5ef2aSThomas Huth #endif 3273fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3274fcf5ef2aSThomas Huth 3275fcf5ef2aSThomas Huth /* lhbrx */ 3276fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3277fcf5ef2aSThomas Huth 3278fcf5ef2aSThomas Huth /* lwbrx */ 3279fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3280fcf5ef2aSThomas Huth 3281fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3282fcf5ef2aSThomas Huth /* ldbrx */ 3283fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3284fcf5ef2aSThomas Huth /* stdbrx */ 3285fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3286fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3287fcf5ef2aSThomas Huth 3288fcf5ef2aSThomas Huth /* sthbrx */ 3289fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3290fcf5ef2aSThomas Huth /* stwbrx */ 3291fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3292fcf5ef2aSThomas Huth 3293fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3294fcf5ef2aSThomas Huth 3295fcf5ef2aSThomas Huth /* lmw */ 3296fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3297fcf5ef2aSThomas Huth { 3298fcf5ef2aSThomas Huth TCGv t0; 3299fcf5ef2aSThomas Huth TCGv_i32 t1; 3300fcf5ef2aSThomas Huth 3301fcf5ef2aSThomas Huth if (ctx->le_mode) { 3302fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3303fcf5ef2aSThomas Huth return; 3304fcf5ef2aSThomas Huth } 3305fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3306fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33077058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 3308fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3309fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3310fcf5ef2aSThomas Huth } 3311fcf5ef2aSThomas Huth 3312fcf5ef2aSThomas Huth /* stmw */ 3313fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3314fcf5ef2aSThomas Huth { 3315fcf5ef2aSThomas Huth TCGv t0; 3316fcf5ef2aSThomas Huth TCGv_i32 t1; 3317fcf5ef2aSThomas Huth 3318fcf5ef2aSThomas Huth if (ctx->le_mode) { 3319fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3320fcf5ef2aSThomas Huth return; 3321fcf5ef2aSThomas Huth } 3322fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3323fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33247058ff52SRichard Henderson t1 = tcg_constant_i32(rS(ctx->opcode)); 3325fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3326fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3327fcf5ef2aSThomas Huth } 3328fcf5ef2aSThomas Huth 3329fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3330fcf5ef2aSThomas Huth 3331fcf5ef2aSThomas Huth /* lswi */ 3332efe843d8SDavid Gibson /* 3333efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3334efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3335efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3336efe843d8SDavid Gibson * spec... 3337fcf5ef2aSThomas Huth */ 3338fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3339fcf5ef2aSThomas Huth { 3340fcf5ef2aSThomas Huth TCGv t0; 3341fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3342fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3343fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3344fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3345fcf5ef2aSThomas Huth int nr; 3346fcf5ef2aSThomas Huth 3347fcf5ef2aSThomas Huth if (ctx->le_mode) { 3348fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3349fcf5ef2aSThomas Huth return; 3350fcf5ef2aSThomas Huth } 3351efe843d8SDavid Gibson if (nb == 0) { 3352fcf5ef2aSThomas Huth nb = 32; 3353efe843d8SDavid Gibson } 3354f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3355fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3356fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3357fcf5ef2aSThomas Huth return; 3358fcf5ef2aSThomas Huth } 3359fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3360fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3361fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 33627058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 33637058ff52SRichard Henderson t2 = tcg_constant_i32(start); 3364fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3365fcf5ef2aSThomas Huth } 3366fcf5ef2aSThomas Huth 3367fcf5ef2aSThomas Huth /* lswx */ 3368fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3369fcf5ef2aSThomas Huth { 3370fcf5ef2aSThomas Huth TCGv t0; 3371fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3372fcf5ef2aSThomas Huth 3373fcf5ef2aSThomas Huth if (ctx->le_mode) { 3374fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3375fcf5ef2aSThomas Huth return; 3376fcf5ef2aSThomas Huth } 3377fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3378fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3379fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 33807058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 33817058ff52SRichard Henderson t2 = tcg_constant_i32(rA(ctx->opcode)); 33827058ff52SRichard Henderson t3 = tcg_constant_i32(rB(ctx->opcode)); 3383fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3384fcf5ef2aSThomas Huth } 3385fcf5ef2aSThomas Huth 3386fcf5ef2aSThomas Huth /* stswi */ 3387fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3388fcf5ef2aSThomas Huth { 3389fcf5ef2aSThomas Huth TCGv t0; 3390fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3391fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3392fcf5ef2aSThomas Huth 3393fcf5ef2aSThomas Huth if (ctx->le_mode) { 3394fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3395fcf5ef2aSThomas Huth return; 3396fcf5ef2aSThomas Huth } 3397fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3398fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3399fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3400efe843d8SDavid Gibson if (nb == 0) { 3401fcf5ef2aSThomas Huth nb = 32; 3402efe843d8SDavid Gibson } 34037058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 34047058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3405fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3406fcf5ef2aSThomas Huth } 3407fcf5ef2aSThomas Huth 3408fcf5ef2aSThomas Huth /* stswx */ 3409fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3410fcf5ef2aSThomas Huth { 3411fcf5ef2aSThomas Huth TCGv t0; 3412fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3413fcf5ef2aSThomas Huth 3414fcf5ef2aSThomas Huth if (ctx->le_mode) { 3415fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3416fcf5ef2aSThomas Huth return; 3417fcf5ef2aSThomas Huth } 3418fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3419fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3420fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3421fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3422fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3423fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 34247058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3425fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3426fcf5ef2aSThomas Huth } 3427fcf5ef2aSThomas Huth 3428fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3429fcf5ef2aSThomas Huth /* eieio */ 3430fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3431fcf5ef2aSThomas Huth { 3432fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3433fcb830afSNicholas Piggin 3434fcb830afSNicholas Piggin /* 3435fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3436fcb830afSNicholas Piggin * operations in the set: 3437fcb830afSNicholas Piggin * - loads from CI memory. 3438fcb830afSNicholas Piggin * - stores to CI memory. 3439fcb830afSNicholas Piggin * - stores to WT memory. 3440fcb830afSNicholas Piggin * 3441fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3442fcb830afSNicholas Piggin * - stores to cacheble memory. 3443fcb830afSNicholas Piggin * 3444fcb830afSNicholas Piggin * It also serializes instructions: 3445fcb830afSNicholas Piggin * - dcbt and dcbst. 3446fcb830afSNicholas Piggin * 3447fcb830afSNicholas Piggin * It separately serializes: 3448fcb830afSNicholas Piggin * - tlbie and tlbsync. 3449fcb830afSNicholas Piggin * 3450fcb830afSNicholas Piggin * And separately serializes: 3451fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3452fcb830afSNicholas Piggin * 3453fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3454fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3455fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3456fcb830afSNicholas Piggin * serialization. 3457fcb830afSNicholas Piggin */ 3458c8fd8373SCédric Le Goater 3459c8fd8373SCédric Le Goater /* 3460c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3461c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3462c8fd8373SCédric Le Goater */ 3463c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3464c8fd8373SCédric Le Goater /* 3465c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3466c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3467c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3468c8fd8373SCédric Le Goater * complain to the user. 3469c8fd8373SCédric Le Goater */ 3470c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3471c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 34722c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3473c8fd8373SCédric Le Goater } else { 3474c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3475c8fd8373SCédric Le Goater } 3476c8fd8373SCédric Le Goater } 3477c8fd8373SCédric Le Goater 3478c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3479fcf5ef2aSThomas Huth } 3480fcf5ef2aSThomas Huth 3481fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3482fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3483fcf5ef2aSThomas Huth { 3484fcf5ef2aSThomas Huth TCGv_i32 t; 3485fcf5ef2aSThomas Huth TCGLabel *l; 3486fcf5ef2aSThomas Huth 3487fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3488fcf5ef2aSThomas Huth return; 3489fcf5ef2aSThomas Huth } 3490fcf5ef2aSThomas Huth l = gen_new_label(); 3491fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3492fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3493fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3494fcf5ef2aSThomas Huth if (global) { 3495fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3496fcf5ef2aSThomas Huth } else { 3497fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3498fcf5ef2aSThomas Huth } 3499fcf5ef2aSThomas Huth gen_set_label(l); 3500fcf5ef2aSThomas Huth } 3501fcf5ef2aSThomas Huth #else 3502fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3503fcf5ef2aSThomas Huth #endif 3504fcf5ef2aSThomas Huth 3505fcf5ef2aSThomas Huth /* isync */ 3506fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3507fcf5ef2aSThomas Huth { 3508fcf5ef2aSThomas Huth /* 3509fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3510fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3511fcf5ef2aSThomas Huth */ 3512fcf5ef2aSThomas Huth if (!ctx->pr) { 3513fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3514fcf5ef2aSThomas Huth } 35154771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3516d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3517fcf5ef2aSThomas Huth } 3518fcf5ef2aSThomas Huth 3519fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3520fcf5ef2aSThomas Huth 352114776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 35222a4e6c1bSRichard Henderson { 35232a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 35242a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 35252a4e6c1bSRichard Henderson 35262a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 35272a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 35282a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 35292a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 3530392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 35312a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 35322a4e6c1bSRichard Henderson } 35332a4e6c1bSRichard Henderson 3534fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3535fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3536fcf5ef2aSThomas Huth { \ 35372a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3538fcf5ef2aSThomas Huth } 3539fcf5ef2aSThomas Huth 3540fcf5ef2aSThomas Huth /* lwarx */ 3541fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3542fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3543fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3544fcf5ef2aSThomas Huth 354514776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 354620923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 354720923c1dSRichard Henderson { 354820923c1dSRichard Henderson TCGv t = tcg_temp_new(); 354920923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 355020923c1dSRichard Henderson TCGv u = tcg_temp_new(); 355120923c1dSRichard Henderson 355220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 355320923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 355420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 355520923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 355620923c1dSRichard Henderson 355720923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 355820923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 355920923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 356020923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 356120923c1dSRichard Henderson 356220923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 356320923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 356420923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 356520923c1dSRichard Henderson } 356620923c1dSRichard Henderson 356714776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 356820ba8504SRichard Henderson { 356920ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 357020ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 357120923c1dSRichard Henderson int rt = rD(ctx->opcode); 357220923c1dSRichard Henderson bool need_serial; 357320ba8504SRichard Henderson TCGv src, dst; 357420ba8504SRichard Henderson 357520ba8504SRichard Henderson gen_addr_register(ctx, EA); 357620923c1dSRichard Henderson dst = cpu_gpr[rt]; 357720923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 357820ba8504SRichard Henderson 357920923c1dSRichard Henderson need_serial = false; 358020ba8504SRichard Henderson memop |= MO_ALIGN; 358120ba8504SRichard Henderson switch (gpr_FC) { 358220ba8504SRichard Henderson case 0: /* Fetch and add */ 358320ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 358420ba8504SRichard Henderson break; 358520ba8504SRichard Henderson case 1: /* Fetch and xor */ 358620ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 358720ba8504SRichard Henderson break; 358820ba8504SRichard Henderson case 2: /* Fetch and or */ 358920ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 359020ba8504SRichard Henderson break; 359120ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 359220ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 359320ba8504SRichard Henderson break; 3594b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3595b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3596b8ce0f86SRichard Henderson break; 3597b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3598b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3599b8ce0f86SRichard Henderson break; 3600b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3601b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3602b8ce0f86SRichard Henderson break; 3603b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3604b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3605b8ce0f86SRichard Henderson break; 360620ba8504SRichard Henderson case 8: /* Swap */ 360720ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 360820ba8504SRichard Henderson break; 360920923c1dSRichard Henderson 361020923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 361120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 361220923c1dSRichard Henderson need_serial = true; 361320923c1dSRichard Henderson } else { 361420923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 361520923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 361620923c1dSRichard Henderson 361720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 361820923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 361920923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 362020923c1dSRichard Henderson } else { 362120923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 362220923c1dSRichard Henderson } 362320923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 362420923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 362520923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 362620923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 362720923c1dSRichard Henderson } 362820ba8504SRichard Henderson break; 362920923c1dSRichard Henderson 363020923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 363120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 363220923c1dSRichard Henderson need_serial = true; 363320923c1dSRichard Henderson } else { 363420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 363520923c1dSRichard Henderson } 363620923c1dSRichard Henderson break; 363720923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 363820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 363920923c1dSRichard Henderson need_serial = true; 364020923c1dSRichard Henderson } else { 364120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 364220923c1dSRichard Henderson } 364320923c1dSRichard Henderson break; 364420923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 364520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 364620923c1dSRichard Henderson need_serial = true; 364720923c1dSRichard Henderson } else { 364820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 364920923c1dSRichard Henderson } 365020923c1dSRichard Henderson break; 365120923c1dSRichard Henderson 365220ba8504SRichard Henderson default: 365320ba8504SRichard Henderson /* invoke data storage error handler */ 365420ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 365520ba8504SRichard Henderson } 365620923c1dSRichard Henderson 365720923c1dSRichard Henderson if (need_serial) { 365820923c1dSRichard Henderson /* Restart with exclusive lock. */ 365920923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 366020923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 366120923c1dSRichard Henderson } 3662a68a6146SBalamuruhan S } 3663a68a6146SBalamuruhan S 366420ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 366520ba8504SRichard Henderson { 366620ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 366720ba8504SRichard Henderson } 366820ba8504SRichard Henderson 366920ba8504SRichard Henderson #ifdef TARGET_PPC64 367020ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 367120ba8504SRichard Henderson { 3672fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 367320ba8504SRichard Henderson } 3674a68a6146SBalamuruhan S #endif 3675a68a6146SBalamuruhan S 367614776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 36779deb041cSRichard Henderson { 36789deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 36799deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 36809deb041cSRichard Henderson TCGv src, discard; 36819deb041cSRichard Henderson 36829deb041cSRichard Henderson gen_addr_register(ctx, EA); 36839deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 36849deb041cSRichard Henderson discard = tcg_temp_new(); 36859deb041cSRichard Henderson 36869deb041cSRichard Henderson memop |= MO_ALIGN; 36879deb041cSRichard Henderson switch (gpr_FC) { 36889deb041cSRichard Henderson case 0: /* add and Store */ 36899deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36909deb041cSRichard Henderson break; 36919deb041cSRichard Henderson case 1: /* xor and Store */ 36929deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36939deb041cSRichard Henderson break; 36949deb041cSRichard Henderson case 2: /* Or and Store */ 36959deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36969deb041cSRichard Henderson break; 36979deb041cSRichard Henderson case 3: /* 'and' and Store */ 36989deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36999deb041cSRichard Henderson break; 37009deb041cSRichard Henderson case 4: /* Store max unsigned */ 3701b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3702b8ce0f86SRichard Henderson break; 37039deb041cSRichard Henderson case 5: /* Store max signed */ 3704b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3705b8ce0f86SRichard Henderson break; 37069deb041cSRichard Henderson case 6: /* Store min unsigned */ 3707b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3708b8ce0f86SRichard Henderson break; 37099deb041cSRichard Henderson case 7: /* Store min signed */ 3710b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3711b8ce0f86SRichard Henderson break; 37129deb041cSRichard Henderson case 24: /* Store twin */ 37137fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 37147fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 37157fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 37167fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 37177fbc2b20SRichard Henderson } else { 37187fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 37197fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 37207fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 37217fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 37227fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 37237fbc2b20SRichard Henderson 37247fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 37257fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 37267fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 37277fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 37287fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 37297fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 37307fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 37317fbc2b20SRichard Henderson } 37329deb041cSRichard Henderson break; 37339deb041cSRichard Henderson default: 37349deb041cSRichard Henderson /* invoke data storage error handler */ 37359deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 37369deb041cSRichard Henderson } 3737a3401188SBalamuruhan S } 3738a3401188SBalamuruhan S 37399deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 37409deb041cSRichard Henderson { 37419deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 37429deb041cSRichard Henderson } 37439deb041cSRichard Henderson 37449deb041cSRichard Henderson #ifdef TARGET_PPC64 37459deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 37469deb041cSRichard Henderson { 3747fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 37489deb041cSRichard Henderson } 3749a3401188SBalamuruhan S #endif 3750a3401188SBalamuruhan S 375114776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3752fcf5ef2aSThomas Huth { 375321ee07e7SNicholas Piggin TCGLabel *lfail; 375421ee07e7SNicholas Piggin TCGv EA; 375521ee07e7SNicholas Piggin TCGv cr0; 375621ee07e7SNicholas Piggin TCGv t0; 375721ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3758fcf5ef2aSThomas Huth 375921ee07e7SNicholas Piggin lfail = gen_new_label(); 376021ee07e7SNicholas Piggin EA = tcg_temp_new(); 376121ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3762253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 376321ee07e7SNicholas Piggin 376421ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 376521ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 376621ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 376721ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 376821ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 376921ee07e7SNicholas Piggin 3770253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 377121ee07e7SNicholas Piggin cpu_gpr[rs], ctx->mem_idx, 3772253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3773253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3774253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 377521ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3776253ce7b2SNikunj A Dadhania 377721ee07e7SNicholas Piggin gen_set_label(lfail); 377821ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3779fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3780fcf5ef2aSThomas Huth } 3781fcf5ef2aSThomas Huth 3782fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3783fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3784fcf5ef2aSThomas Huth { \ 3785d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3786fcf5ef2aSThomas Huth } 3787fcf5ef2aSThomas Huth 3788fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3789fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3790fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3791fcf5ef2aSThomas Huth 3792fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3793fcf5ef2aSThomas Huth /* ldarx */ 3794fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3795fcf5ef2aSThomas Huth /* stdcx. */ 3796fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3797fcf5ef2aSThomas Huth 3798fcf5ef2aSThomas Huth /* lqarx */ 3799fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3800fcf5ef2aSThomas Huth { 3801fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 380294bf2658SRichard Henderson TCGv EA, hi, lo; 380357b38ffdSRichard Henderson TCGv_i128 t16; 3804fcf5ef2aSThomas Huth 3805fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3806fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3807fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3808fcf5ef2aSThomas Huth return; 3809fcf5ef2aSThomas Huth } 3810fcf5ef2aSThomas Huth 3811fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 381294bf2658SRichard Henderson EA = tcg_temp_new(); 3813fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 381494bf2658SRichard Henderson 381594bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 381694bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 381794bf2658SRichard Henderson hi = cpu_gpr[rd]; 381894bf2658SRichard Henderson 381957b38ffdSRichard Henderson t16 = tcg_temp_new_i128(); 382057b38ffdSRichard Henderson tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 382157b38ffdSRichard Henderson tcg_gen_extr_i128_i64(lo, hi, t16); 382294bf2658SRichard Henderson 3823e025e8f5SNicholas Piggin tcg_gen_mov_tl(cpu_reserve, EA); 3824392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, 16); 382594bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 382694bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3827fcf5ef2aSThomas Huth } 3828fcf5ef2aSThomas Huth 3829fcf5ef2aSThomas Huth /* stqcx. */ 3830fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3831fcf5ef2aSThomas Huth { 383221ee07e7SNicholas Piggin TCGLabel *lfail; 3833894448aeSRichard Henderson TCGv EA, t0, t1; 383421ee07e7SNicholas Piggin TCGv cr0; 3835894448aeSRichard Henderson TCGv_i128 cmp, val; 383621ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3837fcf5ef2aSThomas Huth 38384a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3839fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3840fcf5ef2aSThomas Huth return; 3841fcf5ef2aSThomas Huth } 38424a9b3c5dSRichard Henderson 384321ee07e7SNicholas Piggin lfail = gen_new_label(); 38444a9b3c5dSRichard Henderson EA = tcg_temp_new(); 384521ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3846fcf5ef2aSThomas Huth 384721ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 384821ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 384921ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 385021ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 385121ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 38524a9b3c5dSRichard Henderson 3853894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 3854894448aeSRichard Henderson val = tcg_temp_new_i128(); 38554a9b3c5dSRichard Henderson 3856894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 38574a9b3c5dSRichard Henderson 3858894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3859894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 38604a9b3c5dSRichard Henderson 3861894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3862894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 3863894448aeSRichard Henderson 3864894448aeSRichard Henderson t0 = tcg_temp_new(); 3865894448aeSRichard Henderson t1 = tcg_temp_new(); 3866894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 3867894448aeSRichard Henderson 3868894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3869894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3870894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 3871894448aeSRichard Henderson 3872894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3873894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 387421ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3875894448aeSRichard Henderson 387621ee07e7SNicholas Piggin gen_set_label(lfail); 387721ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 38784a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 38794a9b3c5dSRichard Henderson } 3880fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3881fcf5ef2aSThomas Huth 3882fcf5ef2aSThomas Huth /* sync */ 3883fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3884fcf5ef2aSThomas Huth { 388503abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 3886fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3887fcf5ef2aSThomas Huth 388803abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 388903abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 389003abfd90SNicholas Piggin } 389103abfd90SNicholas Piggin 3892fcf5ef2aSThomas Huth /* 3893fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3894fcf5ef2aSThomas Huth * 3895fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3896fcf5ef2aSThomas Huth * 3897fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3898fcf5ef2aSThomas Huth * check MSR_PR as well. 3899fcf5ef2aSThomas Huth */ 3900fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3901fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3902fcf5ef2aSThomas Huth } 390303abfd90SNicholas Piggin 390403abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 3905fcf5ef2aSThomas Huth } 3906fcf5ef2aSThomas Huth 3907fcf5ef2aSThomas Huth /* wait */ 3908fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3909fcf5ef2aSThomas Huth { 39100c9717ffSNicholas Piggin uint32_t wc; 39110c9717ffSNicholas Piggin 39120c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 39130c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 39140c9717ffSNicholas Piggin 39150c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 39160c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 39170c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39180c9717ffSNicholas Piggin } else { 39190c9717ffSNicholas Piggin wc = 0; 39200c9717ffSNicholas Piggin } 39210c9717ffSNicholas Piggin 39220c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 39230c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 39240c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39250c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 39260c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 39270c9717ffSNicholas Piggin 39280c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 39290c9717ffSNicholas Piggin if (wc == 3) { 39300c9717ffSNicholas Piggin gen_invalid(ctx); 39310c9717ffSNicholas Piggin return; 39320c9717ffSNicholas Piggin } 39330c9717ffSNicholas Piggin 39340c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 39350c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 39360c9717ffSNicholas Piggin gen_invalid(ctx); 39370c9717ffSNicholas Piggin return; 39380c9717ffSNicholas Piggin } 39390c9717ffSNicholas Piggin 39400c9717ffSNicholas Piggin } else { /* ISA300 */ 39410c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 39420c9717ffSNicholas Piggin if (wc > 0) { 39430c9717ffSNicholas Piggin gen_invalid(ctx); 39440c9717ffSNicholas Piggin return; 39450c9717ffSNicholas Piggin } 39460c9717ffSNicholas Piggin } 39470c9717ffSNicholas Piggin 39480c9717ffSNicholas Piggin } else { 39490c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 39500c9717ffSNicholas Piggin gen_invalid(ctx); 39510c9717ffSNicholas Piggin return; 39520c9717ffSNicholas Piggin } 39530c9717ffSNicholas Piggin 39540c9717ffSNicholas Piggin /* 39550c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 39560c9717ffSNicholas Piggin * to occur. 39570c9717ffSNicholas Piggin */ 39580c9717ffSNicholas Piggin if (wc == 0) { 39597058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(1); 3960fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3961fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3962fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3963b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3964fcf5ef2aSThomas Huth } 3965fcf5ef2aSThomas Huth 39660c9717ffSNicholas Piggin /* 39670c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 39680c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 39690c9717ffSNicholas Piggin * 39700c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 39710c9717ffSNicholas Piggin * no-ops. 39720c9717ffSNicholas Piggin * 39730c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 39740c9717ffSNicholas Piggin * 39750c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 39760c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 39770c9717ffSNicholas Piggin * 39780c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 39790c9717ffSNicholas Piggin * 39800c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 39810c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 39820c9717ffSNicholas Piggin * can be implemented as a no-op. 39830c9717ffSNicholas Piggin * 39840c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 39850c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 39860c9717ffSNicholas Piggin * no-op. 39870c9717ffSNicholas Piggin * 39880c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 39890c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 39900c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 39910c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 39920c9717ffSNicholas Piggin * (if suboptimal). 39930c9717ffSNicholas Piggin */ 39940c9717ffSNicholas Piggin } 39950c9717ffSNicholas Piggin 3996fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3997fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3998fcf5ef2aSThomas Huth { 3999fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40009f0cf041SMatheus Ferst GEN_PRIV(ctx); 4001fcf5ef2aSThomas Huth #else 4002fcf5ef2aSThomas Huth TCGv_i32 t; 4003fcf5ef2aSThomas Huth 40049f0cf041SMatheus Ferst CHK_HV(ctx); 40057058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_DOZE); 4006fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4007154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4008154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4009fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4010fcf5ef2aSThomas Huth } 4011fcf5ef2aSThomas Huth 4012fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4013fcf5ef2aSThomas Huth { 4014fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40159f0cf041SMatheus Ferst GEN_PRIV(ctx); 4016fcf5ef2aSThomas Huth #else 4017fcf5ef2aSThomas Huth TCGv_i32 t; 4018fcf5ef2aSThomas Huth 40199f0cf041SMatheus Ferst CHK_HV(ctx); 40207058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_NAP); 4021fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4022154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4023154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4024fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4025fcf5ef2aSThomas Huth } 4026fcf5ef2aSThomas Huth 4027cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4028cdee0e72SNikunj A Dadhania { 402921c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 40309f0cf041SMatheus Ferst GEN_PRIV(ctx); 403121c0d66aSBenjamin Herrenschmidt #else 403221c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 403321c0d66aSBenjamin Herrenschmidt 40349f0cf041SMatheus Ferst CHK_HV(ctx); 40357058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_STOP); 403621c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 403721c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 403821c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 403921c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4040cdee0e72SNikunj A Dadhania } 4041cdee0e72SNikunj A Dadhania 4042fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4043fcf5ef2aSThomas Huth { 4044fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40459f0cf041SMatheus Ferst GEN_PRIV(ctx); 4046fcf5ef2aSThomas Huth #else 4047fcf5ef2aSThomas Huth TCGv_i32 t; 4048fcf5ef2aSThomas Huth 40499f0cf041SMatheus Ferst CHK_HV(ctx); 40507058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_SLEEP); 4051fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4052154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4053154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4054fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4055fcf5ef2aSThomas Huth } 4056fcf5ef2aSThomas Huth 4057fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4058fcf5ef2aSThomas Huth { 4059fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40609f0cf041SMatheus Ferst GEN_PRIV(ctx); 4061fcf5ef2aSThomas Huth #else 4062fcf5ef2aSThomas Huth TCGv_i32 t; 4063fcf5ef2aSThomas Huth 40649f0cf041SMatheus Ferst CHK_HV(ctx); 40657058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_RVWINKLE); 4066fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4067154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4068154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4069fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4070fcf5ef2aSThomas Huth } 4071fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4072fcf5ef2aSThomas Huth 4073fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4074fcf5ef2aSThomas Huth { 4075fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4076efe843d8SDavid Gibson if (ctx->has_cfar) { 4077fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4078efe843d8SDavid Gibson } 4079fcf5ef2aSThomas Huth #endif 4080fcf5ef2aSThomas Huth } 4081fcf5ef2aSThomas Huth 408246d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 408346d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 408446d396bdSDaniel Henrique Barboza { 408546d396bdSDaniel Henrique Barboza /* 408646d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 408746d396bdSDaniel Henrique Barboza * instructions. 408846d396bdSDaniel Henrique Barboza */ 408946d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 409046d396bdSDaniel Henrique Barboza return; 409146d396bdSDaniel Henrique Barboza } 409246d396bdSDaniel Henrique Barboza 409346d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4094eeaaefe9SLeandro Lupori TCGLabel *l; 4095eeaaefe9SLeandro Lupori TCGv t0; 4096eeaaefe9SLeandro Lupori 409746d396bdSDaniel Henrique Barboza /* 409846d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 409946d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 410046d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 410146d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 410246d396bdSDaniel Henrique Barboza */ 4103283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 410446d396bdSDaniel Henrique Barboza 4105eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4106eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4107eeaaefe9SLeandro Lupori l = gen_new_label(); 4108eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4109eeaaefe9SLeandro Lupori 4110eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4111eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4112eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4113eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4114eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4115eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4116eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4117eeaaefe9SLeandro Lupori } 4118eeaaefe9SLeandro Lupori 4119eeaaefe9SLeandro Lupori gen_set_label(l); 4120eeaaefe9SLeandro Lupori } else { 412146d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4122eeaaefe9SLeandro Lupori } 412346d396bdSDaniel Henrique Barboza #else 412446d396bdSDaniel Henrique Barboza /* 412546d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 412646d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 412746d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 412846d396bdSDaniel Henrique Barboza */ 412946d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 413046d396bdSDaniel Henrique Barboza 413146d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 413246d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 413346d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 413446d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 413546d396bdSDaniel Henrique Barboza } 413646d396bdSDaniel Henrique Barboza #else 413746d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 413846d396bdSDaniel Henrique Barboza { 413946d396bdSDaniel Henrique Barboza return; 414046d396bdSDaniel Henrique Barboza } 414146d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 414246d396bdSDaniel Henrique Barboza 4143fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4144fcf5ef2aSThomas Huth { 41456e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4146fcf5ef2aSThomas Huth } 4147fcf5ef2aSThomas Huth 41480e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 41490e3bf489SRoman Kapl { 41509498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 41510e3bf489SRoman Kapl gen_debug_exception(ctx); 41520e3bf489SRoman Kapl } else { 415346d396bdSDaniel Henrique Barboza /* 415446d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 415546d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 415646d396bdSDaniel Henrique Barboza */ 415746d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 415846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 415946d396bdSDaniel Henrique Barboza } 416046d396bdSDaniel Henrique Barboza 41610e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 41620e3bf489SRoman Kapl } 41630e3bf489SRoman Kapl } 41640e3bf489SRoman Kapl 4165fcf5ef2aSThomas Huth /*** Branch ***/ 4166c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4167fcf5ef2aSThomas Huth { 4168fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4169fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4170fcf5ef2aSThomas Huth } 4171fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 417246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4173fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4174fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 417507ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4176fcf5ef2aSThomas Huth } else { 4177fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 41780e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4179fcf5ef2aSThomas Huth } 4180fcf5ef2aSThomas Huth } 4181fcf5ef2aSThomas Huth 4182fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4183fcf5ef2aSThomas Huth { 4184fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4185fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4186fcf5ef2aSThomas Huth } 4187fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4188fcf5ef2aSThomas Huth } 4189fcf5ef2aSThomas Huth 4190fcf5ef2aSThomas Huth /* b ba bl bla */ 4191fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4192fcf5ef2aSThomas Huth { 4193fcf5ef2aSThomas Huth target_ulong li, target; 4194fcf5ef2aSThomas Huth 4195fcf5ef2aSThomas Huth /* sign extend LI */ 4196fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4197fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4198fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 41992c2bcb1bSRichard Henderson target = ctx->cia + li; 4200fcf5ef2aSThomas Huth } else { 4201fcf5ef2aSThomas Huth target = li; 4202fcf5ef2aSThomas Huth } 4203fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4204b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4205fcf5ef2aSThomas Huth } 42062c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4207fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 42086086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4209fcf5ef2aSThomas Huth } 4210fcf5ef2aSThomas Huth 4211fcf5ef2aSThomas Huth #define BCOND_IM 0 4212fcf5ef2aSThomas Huth #define BCOND_LR 1 4213fcf5ef2aSThomas Huth #define BCOND_CTR 2 4214fcf5ef2aSThomas Huth #define BCOND_TAR 3 4215fcf5ef2aSThomas Huth 4216c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4217fcf5ef2aSThomas Huth { 4218fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4219fcf5ef2aSThomas Huth TCGLabel *l1; 4220fcf5ef2aSThomas Huth TCGv target; 42210e3bf489SRoman Kapl 4222fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 42239723281fSRichard Henderson target = tcg_temp_new(); 4224efe843d8SDavid Gibson if (type == BCOND_CTR) { 4225fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4226efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4227fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4228efe843d8SDavid Gibson } else { 4229fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4230efe843d8SDavid Gibson } 4231fcf5ef2aSThomas Huth } else { 4232f764718dSRichard Henderson target = NULL; 4233fcf5ef2aSThomas Huth } 4234efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4235b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4236efe843d8SDavid Gibson } 4237fcf5ef2aSThomas Huth l1 = gen_new_label(); 4238fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4239fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4240fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4241fa200c95SGreg Kurz 4242fa200c95SGreg Kurz if (type == BCOND_CTR) { 4243fa200c95SGreg Kurz /* 4244fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4245fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4246fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 424715d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 424815d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 424915d68c5eSGreg Kurz * it basically useless and thus never used in real code. 425015d68c5eSGreg Kurz * 425115d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 425215d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 425315d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 425415d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 425515d68c5eSGreg Kurz * doing anything else harmful. 4256fa200c95SGreg Kurz */ 4257d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4258fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4259fcf5ef2aSThomas Huth return; 4260fcf5ef2aSThomas Huth } 4261fa200c95SGreg Kurz 4262fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4263fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4264fa200c95SGreg Kurz } else { 4265fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4266fa200c95SGreg Kurz } 4267fa200c95SGreg Kurz if (bo & 0x2) { 4268fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4269fa200c95SGreg Kurz } else { 4270fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4271fa200c95SGreg Kurz } 4272fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4273fa200c95SGreg Kurz } else { 4274fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4275fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4276fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4277fcf5ef2aSThomas Huth } else { 4278fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4279fcf5ef2aSThomas Huth } 4280fcf5ef2aSThomas Huth if (bo & 0x2) { 4281fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4282fcf5ef2aSThomas Huth } else { 4283fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4284fcf5ef2aSThomas Huth } 4285fa200c95SGreg Kurz } 4286fcf5ef2aSThomas Huth } 4287fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4288fcf5ef2aSThomas Huth /* Test CR */ 4289fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4290fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4291fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4292fcf5ef2aSThomas Huth 4293fcf5ef2aSThomas Huth if (bo & 0x8) { 4294fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4295fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4296fcf5ef2aSThomas Huth } else { 4297fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4298fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4299fcf5ef2aSThomas Huth } 4300fcf5ef2aSThomas Huth } 43012c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4302fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4303fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4304fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43052c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4306fcf5ef2aSThomas Huth } else { 4307fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4308fcf5ef2aSThomas Huth } 4309fcf5ef2aSThomas Huth } else { 4310fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4311fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4312fcf5ef2aSThomas Huth } else { 4313fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4314fcf5ef2aSThomas Huth } 43150e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4316c4a2e3a9SRichard Henderson } 4317fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 43180e3bf489SRoman Kapl /* fallthrough case */ 4319fcf5ef2aSThomas Huth gen_set_label(l1); 4320b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4321fcf5ef2aSThomas Huth } 43226086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4323fcf5ef2aSThomas Huth } 4324fcf5ef2aSThomas Huth 4325fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4326fcf5ef2aSThomas Huth { 4327fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4328fcf5ef2aSThomas Huth } 4329fcf5ef2aSThomas Huth 4330fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4331fcf5ef2aSThomas Huth { 4332fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4333fcf5ef2aSThomas Huth } 4334fcf5ef2aSThomas Huth 4335fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4336fcf5ef2aSThomas Huth { 4337fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4338fcf5ef2aSThomas Huth } 4339fcf5ef2aSThomas Huth 4340fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4341fcf5ef2aSThomas Huth { 4342fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4343fcf5ef2aSThomas Huth } 4344fcf5ef2aSThomas Huth 4345fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4346fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4347fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4348fcf5ef2aSThomas Huth { \ 4349fcf5ef2aSThomas Huth uint8_t bitmask; \ 4350fcf5ef2aSThomas Huth int sh; \ 4351fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4352fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4353fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4354fcf5ef2aSThomas Huth if (sh > 0) \ 4355fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4356fcf5ef2aSThomas Huth else if (sh < 0) \ 4357fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4358fcf5ef2aSThomas Huth else \ 4359fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4360fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4361fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4362fcf5ef2aSThomas Huth if (sh > 0) \ 4363fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4364fcf5ef2aSThomas Huth else if (sh < 0) \ 4365fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4366fcf5ef2aSThomas Huth else \ 4367fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4368fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4369fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4370fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4371fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4372fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4373fcf5ef2aSThomas Huth } 4374fcf5ef2aSThomas Huth 4375fcf5ef2aSThomas Huth /* crand */ 4376fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4377fcf5ef2aSThomas Huth /* crandc */ 4378fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4379fcf5ef2aSThomas Huth /* creqv */ 4380fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4381fcf5ef2aSThomas Huth /* crnand */ 4382fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4383fcf5ef2aSThomas Huth /* crnor */ 4384fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4385fcf5ef2aSThomas Huth /* cror */ 4386fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4387fcf5ef2aSThomas Huth /* crorc */ 4388fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4389fcf5ef2aSThomas Huth /* crxor */ 4390fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4391fcf5ef2aSThomas Huth 4392fcf5ef2aSThomas Huth /* mcrf */ 4393fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4394fcf5ef2aSThomas Huth { 4395fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4396fcf5ef2aSThomas Huth } 4397fcf5ef2aSThomas Huth 4398fcf5ef2aSThomas Huth /*** System linkage ***/ 4399fcf5ef2aSThomas Huth 4400fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4401fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4402fcf5ef2aSThomas Huth { 4403fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44049f0cf041SMatheus Ferst GEN_PRIV(ctx); 4405fcf5ef2aSThomas Huth #else 4406efe843d8SDavid Gibson /* 4407efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4408fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4409fcf5ef2aSThomas Huth */ 4410d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4411fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4412fcf5ef2aSThomas Huth return; 4413fcf5ef2aSThomas Huth } 4414fcf5ef2aSThomas Huth /* Restore CPU state */ 44159f0cf041SMatheus Ferst CHK_SV(ctx); 4416283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44172c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4418fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 441959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4420fcf5ef2aSThomas Huth #endif 4421fcf5ef2aSThomas Huth } 4422fcf5ef2aSThomas Huth 4423fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4424fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4425fcf5ef2aSThomas Huth { 4426fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44279f0cf041SMatheus Ferst GEN_PRIV(ctx); 4428fcf5ef2aSThomas Huth #else 4429fcf5ef2aSThomas Huth /* Restore CPU state */ 44309f0cf041SMatheus Ferst CHK_SV(ctx); 4431283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44322c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4433fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 443459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4435fcf5ef2aSThomas Huth #endif 4436fcf5ef2aSThomas Huth } 4437fcf5ef2aSThomas Huth 44383c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44393c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 44403c89b8d6SNicholas Piggin { 44413c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 44429f0cf041SMatheus Ferst GEN_PRIV(ctx); 44433c89b8d6SNicholas Piggin #else 44443c89b8d6SNicholas Piggin /* Restore CPU state */ 44459f0cf041SMatheus Ferst CHK_SV(ctx); 4446283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44472c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 44483c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 444959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 44503c89b8d6SNicholas Piggin #endif 44513c89b8d6SNicholas Piggin } 44523c89b8d6SNicholas Piggin #endif 44533c89b8d6SNicholas Piggin 4454fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4455fcf5ef2aSThomas Huth { 4456fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44579f0cf041SMatheus Ferst GEN_PRIV(ctx); 4458fcf5ef2aSThomas Huth #else 4459fcf5ef2aSThomas Huth /* Restore CPU state */ 44609f0cf041SMatheus Ferst CHK_HV(ctx); 4461fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 446259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4463fcf5ef2aSThomas Huth #endif 4464fcf5ef2aSThomas Huth } 4465fcf5ef2aSThomas Huth #endif 4466fcf5ef2aSThomas Huth 4467fcf5ef2aSThomas Huth /* sc */ 4468fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4469fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4470fcf5ef2aSThomas Huth #else 4471fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 44723c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4473fcf5ef2aSThomas Huth #endif 4474fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4475fcf5ef2aSThomas Huth { 4476fcf5ef2aSThomas Huth uint32_t lev; 4477fcf5ef2aSThomas Huth 4478984eda58SNicholas Piggin /* 4479984eda58SNicholas Piggin * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4480984eda58SNicholas Piggin * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4481984eda58SNicholas Piggin * for Ultravisor which TCG does not support, so just ignore the top 6. 4482984eda58SNicholas Piggin */ 4483984eda58SNicholas Piggin lev = (ctx->opcode >> 5) & 0x1; 4484fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4485fcf5ef2aSThomas Huth } 4486fcf5ef2aSThomas Huth 44873c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 44883c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44893c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 44903c89b8d6SNicholas Piggin { 4491f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 44923c89b8d6SNicholas Piggin 4493f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 44942c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4495f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 44963c89b8d6SNicholas Piggin 44977a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 44983c89b8d6SNicholas Piggin } 44993c89b8d6SNicholas Piggin #endif 45003c89b8d6SNicholas Piggin #endif 45013c89b8d6SNicholas Piggin 4502fcf5ef2aSThomas Huth /*** Trap ***/ 4503fcf5ef2aSThomas Huth 4504fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4505fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4506fcf5ef2aSThomas Huth { 4507fcf5ef2aSThomas Huth /* Trap never */ 4508fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4509fcf5ef2aSThomas Huth return true; 4510fcf5ef2aSThomas Huth } 4511fcf5ef2aSThomas Huth /* Trap always */ 4512fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4513fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4514fcf5ef2aSThomas Huth return true; 4515fcf5ef2aSThomas Huth } 4516fcf5ef2aSThomas Huth return false; 4517fcf5ef2aSThomas Huth } 4518fcf5ef2aSThomas Huth 4519fcf5ef2aSThomas Huth /* tw */ 4520fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4521fcf5ef2aSThomas Huth { 4522fcf5ef2aSThomas Huth TCGv_i32 t0; 4523fcf5ef2aSThomas Huth 4524fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4525fcf5ef2aSThomas Huth return; 4526fcf5ef2aSThomas Huth } 45277058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4528fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4529fcf5ef2aSThomas Huth t0); 4530fcf5ef2aSThomas Huth } 4531fcf5ef2aSThomas Huth 4532fcf5ef2aSThomas Huth /* twi */ 4533fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4534fcf5ef2aSThomas Huth { 4535fcf5ef2aSThomas Huth TCGv t0; 4536fcf5ef2aSThomas Huth TCGv_i32 t1; 4537fcf5ef2aSThomas Huth 4538fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4539fcf5ef2aSThomas Huth return; 4540fcf5ef2aSThomas Huth } 45417058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45427058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4543fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4544fcf5ef2aSThomas Huth } 4545fcf5ef2aSThomas Huth 4546fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4547fcf5ef2aSThomas Huth /* td */ 4548fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4549fcf5ef2aSThomas Huth { 4550fcf5ef2aSThomas Huth TCGv_i32 t0; 4551fcf5ef2aSThomas Huth 4552fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4553fcf5ef2aSThomas Huth return; 4554fcf5ef2aSThomas Huth } 45557058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4556fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4557fcf5ef2aSThomas Huth t0); 4558fcf5ef2aSThomas Huth } 4559fcf5ef2aSThomas Huth 4560fcf5ef2aSThomas Huth /* tdi */ 4561fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4562fcf5ef2aSThomas Huth { 4563fcf5ef2aSThomas Huth TCGv t0; 4564fcf5ef2aSThomas Huth TCGv_i32 t1; 4565fcf5ef2aSThomas Huth 4566fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4567fcf5ef2aSThomas Huth return; 4568fcf5ef2aSThomas Huth } 45697058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45707058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4571fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4572fcf5ef2aSThomas Huth } 4573fcf5ef2aSThomas Huth #endif 4574fcf5ef2aSThomas Huth 4575fcf5ef2aSThomas Huth /*** Processor control ***/ 4576fcf5ef2aSThomas Huth 4577fcf5ef2aSThomas Huth /* mcrxr */ 4578fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4579fcf5ef2aSThomas Huth { 4580fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4581fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4582fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4583fcf5ef2aSThomas Huth 4584fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4585fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4586fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4587fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4588fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4589fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4590fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4591fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4592fcf5ef2aSThomas Huth 4593fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4594fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4595fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4596fcf5ef2aSThomas Huth } 4597fcf5ef2aSThomas Huth 4598b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4599b63d0434SNikunj A Dadhania /* mcrxrx */ 4600b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4601b63d0434SNikunj A Dadhania { 4602b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4603b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4604b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4605b63d0434SNikunj A Dadhania 4606b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4607b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4608b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4609b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4610b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4611b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4612b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4613b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4614b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4615b63d0434SNikunj A Dadhania } 4616b63d0434SNikunj A Dadhania #endif 4617b63d0434SNikunj A Dadhania 4618fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4619fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4620fcf5ef2aSThomas Huth { 4621fcf5ef2aSThomas Huth uint32_t crm, crn; 4622fcf5ef2aSThomas Huth 4623fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4624fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4625fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4626fcf5ef2aSThomas Huth crn = ctz32(crm); 4627fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4628fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4629fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4630fcf5ef2aSThomas Huth } 4631fcf5ef2aSThomas Huth } else { 4632fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4633fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4634fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4635fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4636fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4637fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4638fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4639fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4640fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4641fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4642fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4643fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4644fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4645fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4646fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4647fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4648fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4649fcf5ef2aSThomas Huth } 4650fcf5ef2aSThomas Huth } 4651fcf5ef2aSThomas Huth 4652fcf5ef2aSThomas Huth /* mfmsr */ 4653fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4654fcf5ef2aSThomas Huth { 46559f0cf041SMatheus Ferst CHK_SV(ctx); 4656fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4657fcf5ef2aSThomas Huth } 4658fcf5ef2aSThomas Huth 4659fcf5ef2aSThomas Huth /* mfspr */ 4660fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4661fcf5ef2aSThomas Huth { 4662fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4663fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4664fcf5ef2aSThomas Huth 4665fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4666fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4667fcf5ef2aSThomas Huth #else 4668fcf5ef2aSThomas Huth if (ctx->pr) { 4669fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4670fcf5ef2aSThomas Huth } else if (ctx->hv) { 4671fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4672fcf5ef2aSThomas Huth } else { 4673fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4674fcf5ef2aSThomas Huth } 4675fcf5ef2aSThomas Huth #endif 4676fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4677fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4678fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4679fcf5ef2aSThomas Huth } else { 4680fcf5ef2aSThomas Huth /* Privilege exception */ 4681efe843d8SDavid Gibson /* 4682efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4683fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4684fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4685fcf5ef2aSThomas Huth */ 4686fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 468731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 468831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 46892c2bcb1bSRichard Henderson ctx->cia); 4690fcf5ef2aSThomas Huth } 4691fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4692fcf5ef2aSThomas Huth } 4693fcf5ef2aSThomas Huth } else { 4694fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4695fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4696fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4697fcf5ef2aSThomas Huth /* This is a nop */ 4698fcf5ef2aSThomas Huth return; 4699fcf5ef2aSThomas Huth } 4700fcf5ef2aSThomas Huth /* Not defined */ 470131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 470231085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 47032c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4704fcf5ef2aSThomas Huth 4705efe843d8SDavid Gibson /* 4706efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4707efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4708fcf5ef2aSThomas Huth */ 4709fcf5ef2aSThomas Huth if (sprn & 0x10) { 4710fcf5ef2aSThomas Huth if (ctx->pr) { 47111315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4712fcf5ef2aSThomas Huth } 4713fcf5ef2aSThomas Huth } else { 4714fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 47151315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4716fcf5ef2aSThomas Huth } 4717fcf5ef2aSThomas Huth } 4718fcf5ef2aSThomas Huth } 4719fcf5ef2aSThomas Huth } 4720fcf5ef2aSThomas Huth 4721fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4722fcf5ef2aSThomas Huth { 4723fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4724fcf5ef2aSThomas Huth } 4725fcf5ef2aSThomas Huth 4726fcf5ef2aSThomas Huth /* mftb */ 4727fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4728fcf5ef2aSThomas Huth { 4729fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4730fcf5ef2aSThomas Huth } 4731fcf5ef2aSThomas Huth 4732fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4733fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4734fcf5ef2aSThomas Huth { 4735fcf5ef2aSThomas Huth uint32_t crm, crn; 4736fcf5ef2aSThomas Huth 4737fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4738fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4739fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4740fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4741fcf5ef2aSThomas Huth crn = ctz32(crm); 4742fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4743fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4744fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4745fcf5ef2aSThomas Huth } 4746fcf5ef2aSThomas Huth } else { 4747fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4748fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4749fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4750fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4751fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4752fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4753fcf5ef2aSThomas Huth } 4754fcf5ef2aSThomas Huth } 4755fcf5ef2aSThomas Huth } 4756fcf5ef2aSThomas Huth } 4757fcf5ef2aSThomas Huth 4758fcf5ef2aSThomas Huth /* mtmsr */ 4759fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4760fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4761fcf5ef2aSThomas Huth { 4762caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4763caf590ddSNicholas Piggin gen_invalid(ctx); 4764caf590ddSNicholas Piggin return; 4765caf590ddSNicholas Piggin } 4766caf590ddSNicholas Piggin 47679f0cf041SMatheus Ferst CHK_SV(ctx); 4768fcf5ef2aSThomas Huth 4769fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 47706fa5726bSMatheus Ferst TCGv t0, t1; 47716fa5726bSMatheus Ferst target_ulong mask; 47726fa5726bSMatheus Ferst 47736fa5726bSMatheus Ferst t0 = tcg_temp_new(); 47746fa5726bSMatheus Ferst t1 = tcg_temp_new(); 47756fa5726bSMatheus Ferst 4776283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 47776fa5726bSMatheus Ferst 4778fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 47795ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 47806fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4781fcf5ef2aSThomas Huth } else { 47826fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 47836fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 47846fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4785efe843d8SDavid Gibson /* 4786efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4787efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4788efe843d8SDavid Gibson * ppc_store_msr 4789fcf5ef2aSThomas Huth */ 4790b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4791fcf5ef2aSThomas Huth } 47926fa5726bSMatheus Ferst 47936fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 47946fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 47956fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 47966fa5726bSMatheus Ferst 47976fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 47986fa5726bSMatheus Ferst 47995ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4800d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4801fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4802fcf5ef2aSThomas Huth } 4803fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4804fcf5ef2aSThomas Huth 4805fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4806fcf5ef2aSThomas Huth { 48079f0cf041SMatheus Ferst CHK_SV(ctx); 4808fcf5ef2aSThomas Huth 4809fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48106fa5726bSMatheus Ferst TCGv t0, t1; 48116fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 48126fa5726bSMatheus Ferst 48136fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48146fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48156fa5726bSMatheus Ferst 4816283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 4817fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48185ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48196fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4820fcf5ef2aSThomas Huth } else { 48216fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 48226fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4823fcf5ef2aSThomas Huth 4824efe843d8SDavid Gibson /* 4825efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4826efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4827efe843d8SDavid Gibson * ppc_store_msr 4828fcf5ef2aSThomas Huth */ 4829b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4830fcf5ef2aSThomas Huth } 48316fa5726bSMatheus Ferst 48326fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48336fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48346fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48356fa5726bSMatheus Ferst 48366fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48376fa5726bSMatheus Ferst 48385ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4839d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4840fcf5ef2aSThomas Huth #endif 4841fcf5ef2aSThomas Huth } 4842fcf5ef2aSThomas Huth 4843fcf5ef2aSThomas Huth /* mtspr */ 4844fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4845fcf5ef2aSThomas Huth { 4846fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4847fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4848fcf5ef2aSThomas Huth 4849fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4850fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4851fcf5ef2aSThomas Huth #else 4852fcf5ef2aSThomas Huth if (ctx->pr) { 4853fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4854fcf5ef2aSThomas Huth } else if (ctx->hv) { 4855fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4856fcf5ef2aSThomas Huth } else { 4857fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4858fcf5ef2aSThomas Huth } 4859fcf5ef2aSThomas Huth #endif 4860fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4861fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4862fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4863fcf5ef2aSThomas Huth } else { 4864fcf5ef2aSThomas Huth /* Privilege exception */ 486531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 486631085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48672c2bcb1bSRichard Henderson ctx->cia); 4868fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4869fcf5ef2aSThomas Huth } 4870fcf5ef2aSThomas Huth } else { 4871fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4872fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4873fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4874fcf5ef2aSThomas Huth /* This is a nop */ 4875fcf5ef2aSThomas Huth return; 4876fcf5ef2aSThomas Huth } 4877fcf5ef2aSThomas Huth 4878fcf5ef2aSThomas Huth /* Not defined */ 487931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 488031085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 48812c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4882fcf5ef2aSThomas Huth 4883fcf5ef2aSThomas Huth 4884efe843d8SDavid Gibson /* 4885efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4886efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4887fcf5ef2aSThomas Huth */ 4888fcf5ef2aSThomas Huth if (sprn & 0x10) { 4889fcf5ef2aSThomas Huth if (ctx->pr) { 48901315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4891fcf5ef2aSThomas Huth } 4892fcf5ef2aSThomas Huth } else { 4893fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 48941315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4895fcf5ef2aSThomas Huth } 4896fcf5ef2aSThomas Huth } 4897fcf5ef2aSThomas Huth } 4898fcf5ef2aSThomas Huth } 4899fcf5ef2aSThomas Huth 4900fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4901fcf5ef2aSThomas Huth /* setb */ 4902fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4903fcf5ef2aSThomas Huth { 4904fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 49056f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 49066f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 4907fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4908fcf5ef2aSThomas Huth 4909fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4910fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4911fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4912fcf5ef2aSThomas Huth } 4913fcf5ef2aSThomas Huth #endif 4914fcf5ef2aSThomas Huth 4915fcf5ef2aSThomas Huth /*** Cache management ***/ 4916fcf5ef2aSThomas Huth 4917fcf5ef2aSThomas Huth /* dcbf */ 4918fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4919fcf5ef2aSThomas Huth { 4920fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4921fcf5ef2aSThomas Huth TCGv t0; 4922fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4923fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4924fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4925fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4926fcf5ef2aSThomas Huth } 4927fcf5ef2aSThomas Huth 492850728199SRoman Kapl /* dcbfep (external PID dcbf) */ 492950728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 493050728199SRoman Kapl { 493150728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 493250728199SRoman Kapl TCGv t0; 49339f0cf041SMatheus Ferst CHK_SV(ctx); 493450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 493550728199SRoman Kapl t0 = tcg_temp_new(); 493650728199SRoman Kapl gen_addr_reg_index(ctx, t0); 493750728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 493850728199SRoman Kapl } 493950728199SRoman Kapl 4940fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4941fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4942fcf5ef2aSThomas Huth { 4943fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 49449f0cf041SMatheus Ferst GEN_PRIV(ctx); 4945fcf5ef2aSThomas Huth #else 4946fcf5ef2aSThomas Huth TCGv EA, val; 4947fcf5ef2aSThomas Huth 49489f0cf041SMatheus Ferst CHK_SV(ctx); 4949fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4950fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4951fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4952fcf5ef2aSThomas Huth val = tcg_temp_new(); 4953fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4954fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4955fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4956fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4957fcf5ef2aSThomas Huth } 4958fcf5ef2aSThomas Huth 4959fcf5ef2aSThomas Huth /* dcdst */ 4960fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4961fcf5ef2aSThomas Huth { 4962fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4963fcf5ef2aSThomas Huth TCGv t0; 4964fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4965fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4966fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4967fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4968fcf5ef2aSThomas Huth } 4969fcf5ef2aSThomas Huth 497050728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 497150728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 497250728199SRoman Kapl { 497350728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 497450728199SRoman Kapl TCGv t0; 497550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 497650728199SRoman Kapl t0 = tcg_temp_new(); 497750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 497850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 497950728199SRoman Kapl } 498050728199SRoman Kapl 4981fcf5ef2aSThomas Huth /* dcbt */ 4982fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4983fcf5ef2aSThomas Huth { 4984efe843d8SDavid Gibson /* 4985efe843d8SDavid Gibson * interpreted as no-op 4986efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4987efe843d8SDavid Gibson * does not generate any exception 4988fcf5ef2aSThomas Huth */ 4989fcf5ef2aSThomas Huth } 4990fcf5ef2aSThomas Huth 499150728199SRoman Kapl /* dcbtep */ 499250728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 499350728199SRoman Kapl { 4994efe843d8SDavid Gibson /* 4995efe843d8SDavid Gibson * interpreted as no-op 4996efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4997efe843d8SDavid Gibson * does not generate any exception 499850728199SRoman Kapl */ 499950728199SRoman Kapl } 500050728199SRoman Kapl 5001fcf5ef2aSThomas Huth /* dcbtst */ 5002fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5003fcf5ef2aSThomas Huth { 5004efe843d8SDavid Gibson /* 5005efe843d8SDavid Gibson * interpreted as no-op 5006efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5007efe843d8SDavid Gibson * does not generate any exception 5008fcf5ef2aSThomas Huth */ 5009fcf5ef2aSThomas Huth } 5010fcf5ef2aSThomas Huth 501150728199SRoman Kapl /* dcbtstep */ 501250728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 501350728199SRoman Kapl { 5014efe843d8SDavid Gibson /* 5015efe843d8SDavid Gibson * interpreted as no-op 5016efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5017efe843d8SDavid Gibson * does not generate any exception 501850728199SRoman Kapl */ 501950728199SRoman Kapl } 502050728199SRoman Kapl 5021fcf5ef2aSThomas Huth /* dcbtls */ 5022fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5023fcf5ef2aSThomas Huth { 5024fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5025fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5026fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5027fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5028fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5029fcf5ef2aSThomas Huth } 5030fcf5ef2aSThomas Huth 5031e64645baSBernhard Beschow /* dcblc */ 5032e64645baSBernhard Beschow static void gen_dcblc(DisasContext *ctx) 5033e64645baSBernhard Beschow { 5034e64645baSBernhard Beschow /* 5035e64645baSBernhard Beschow * interpreted as no-op 5036e64645baSBernhard Beschow */ 5037e64645baSBernhard Beschow } 5038e64645baSBernhard Beschow 5039fcf5ef2aSThomas Huth /* dcbz */ 5040fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5041fcf5ef2aSThomas Huth { 5042fcf5ef2aSThomas Huth TCGv tcgv_addr; 5043fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5044fcf5ef2aSThomas Huth 5045fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5046fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 50477058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5048fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5049fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5050fcf5ef2aSThomas Huth } 5051fcf5ef2aSThomas Huth 505250728199SRoman Kapl /* dcbzep */ 505350728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 505450728199SRoman Kapl { 505550728199SRoman Kapl TCGv tcgv_addr; 505650728199SRoman Kapl TCGv_i32 tcgv_op; 505750728199SRoman Kapl 505850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 505950728199SRoman Kapl tcgv_addr = tcg_temp_new(); 50607058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 506150728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 506250728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 506350728199SRoman Kapl } 506450728199SRoman Kapl 5065fcf5ef2aSThomas Huth /* dst / dstt */ 5066fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5067fcf5ef2aSThomas Huth { 5068fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5069fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5070fcf5ef2aSThomas Huth } else { 5071fcf5ef2aSThomas Huth /* interpreted as no-op */ 5072fcf5ef2aSThomas Huth } 5073fcf5ef2aSThomas Huth } 5074fcf5ef2aSThomas Huth 5075fcf5ef2aSThomas Huth /* dstst /dststt */ 5076fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5077fcf5ef2aSThomas Huth { 5078fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5079fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5080fcf5ef2aSThomas Huth } else { 5081fcf5ef2aSThomas Huth /* interpreted as no-op */ 5082fcf5ef2aSThomas Huth } 5083fcf5ef2aSThomas Huth 5084fcf5ef2aSThomas Huth } 5085fcf5ef2aSThomas Huth 5086fcf5ef2aSThomas Huth /* dss / dssall */ 5087fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5088fcf5ef2aSThomas Huth { 5089fcf5ef2aSThomas Huth /* interpreted as no-op */ 5090fcf5ef2aSThomas Huth } 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth /* icbi */ 5093fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5094fcf5ef2aSThomas Huth { 5095fcf5ef2aSThomas Huth TCGv t0; 5096fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5097fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5098fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5099fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5100fcf5ef2aSThomas Huth } 5101fcf5ef2aSThomas Huth 510250728199SRoman Kapl /* icbiep */ 510350728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 510450728199SRoman Kapl { 510550728199SRoman Kapl TCGv t0; 510650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 510750728199SRoman Kapl t0 = tcg_temp_new(); 510850728199SRoman Kapl gen_addr_reg_index(ctx, t0); 510950728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 511050728199SRoman Kapl } 511150728199SRoman Kapl 5112fcf5ef2aSThomas Huth /* Optional: */ 5113fcf5ef2aSThomas Huth /* dcba */ 5114fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5115fcf5ef2aSThomas Huth { 5116efe843d8SDavid Gibson /* 5117efe843d8SDavid Gibson * interpreted as no-op 5118efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5119fcf5ef2aSThomas Huth * but does not generate any exception 5120fcf5ef2aSThomas Huth */ 5121fcf5ef2aSThomas Huth } 5122fcf5ef2aSThomas Huth 5123fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5124fcf5ef2aSThomas Huth /* Supervisor only: */ 5125fcf5ef2aSThomas Huth 5126fcf5ef2aSThomas Huth /* mfsr */ 5127fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5128fcf5ef2aSThomas Huth { 5129fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51309f0cf041SMatheus Ferst GEN_PRIV(ctx); 5131fcf5ef2aSThomas Huth #else 5132fcf5ef2aSThomas Huth TCGv t0; 5133fcf5ef2aSThomas Huth 51349f0cf041SMatheus Ferst CHK_SV(ctx); 51357058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5136fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5137fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5138fcf5ef2aSThomas Huth } 5139fcf5ef2aSThomas Huth 5140fcf5ef2aSThomas Huth /* mfsrin */ 5141fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5142fcf5ef2aSThomas Huth { 5143fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51449f0cf041SMatheus Ferst GEN_PRIV(ctx); 5145fcf5ef2aSThomas Huth #else 5146fcf5ef2aSThomas Huth TCGv t0; 5147fcf5ef2aSThomas Huth 51489f0cf041SMatheus Ferst CHK_SV(ctx); 5149fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5150e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5151fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5152fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5153fcf5ef2aSThomas Huth } 5154fcf5ef2aSThomas Huth 5155fcf5ef2aSThomas Huth /* mtsr */ 5156fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5157fcf5ef2aSThomas Huth { 5158fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51599f0cf041SMatheus Ferst GEN_PRIV(ctx); 5160fcf5ef2aSThomas Huth #else 5161fcf5ef2aSThomas Huth TCGv t0; 5162fcf5ef2aSThomas Huth 51639f0cf041SMatheus Ferst CHK_SV(ctx); 51647058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5165fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5166fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5167fcf5ef2aSThomas Huth } 5168fcf5ef2aSThomas Huth 5169fcf5ef2aSThomas Huth /* mtsrin */ 5170fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5171fcf5ef2aSThomas Huth { 5172fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51739f0cf041SMatheus Ferst GEN_PRIV(ctx); 5174fcf5ef2aSThomas Huth #else 5175fcf5ef2aSThomas Huth TCGv t0; 51769f0cf041SMatheus Ferst CHK_SV(ctx); 5177fcf5ef2aSThomas Huth 5178fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5179e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5180fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5181fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5182fcf5ef2aSThomas Huth } 5183fcf5ef2aSThomas Huth 5184fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5185fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5186fcf5ef2aSThomas Huth 5187fcf5ef2aSThomas Huth /* mfsr */ 5188fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5189fcf5ef2aSThomas Huth { 5190fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51919f0cf041SMatheus Ferst GEN_PRIV(ctx); 5192fcf5ef2aSThomas Huth #else 5193fcf5ef2aSThomas Huth TCGv t0; 5194fcf5ef2aSThomas Huth 51959f0cf041SMatheus Ferst CHK_SV(ctx); 51967058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5197fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5198fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5199fcf5ef2aSThomas Huth } 5200fcf5ef2aSThomas Huth 5201fcf5ef2aSThomas Huth /* mfsrin */ 5202fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5203fcf5ef2aSThomas Huth { 5204fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52059f0cf041SMatheus Ferst GEN_PRIV(ctx); 5206fcf5ef2aSThomas Huth #else 5207fcf5ef2aSThomas Huth TCGv t0; 5208fcf5ef2aSThomas Huth 52099f0cf041SMatheus Ferst CHK_SV(ctx); 5210fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5211e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5212fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5213fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5214fcf5ef2aSThomas Huth } 5215fcf5ef2aSThomas Huth 5216fcf5ef2aSThomas Huth /* mtsr */ 5217fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5218fcf5ef2aSThomas Huth { 5219fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52209f0cf041SMatheus Ferst GEN_PRIV(ctx); 5221fcf5ef2aSThomas Huth #else 5222fcf5ef2aSThomas Huth TCGv t0; 5223fcf5ef2aSThomas Huth 52249f0cf041SMatheus Ferst CHK_SV(ctx); 52257058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5226fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5227fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5228fcf5ef2aSThomas Huth } 5229fcf5ef2aSThomas Huth 5230fcf5ef2aSThomas Huth /* mtsrin */ 5231fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5232fcf5ef2aSThomas Huth { 5233fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52349f0cf041SMatheus Ferst GEN_PRIV(ctx); 5235fcf5ef2aSThomas Huth #else 5236fcf5ef2aSThomas Huth TCGv t0; 5237fcf5ef2aSThomas Huth 52389f0cf041SMatheus Ferst CHK_SV(ctx); 5239fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5240e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5241fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5242fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5243fcf5ef2aSThomas Huth } 5244fcf5ef2aSThomas Huth 5245fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5246fcf5ef2aSThomas Huth 5247fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5248fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5249fcf5ef2aSThomas Huth 5250fcf5ef2aSThomas Huth /* tlbia */ 5251fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5252fcf5ef2aSThomas Huth { 5253fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52549f0cf041SMatheus Ferst GEN_PRIV(ctx); 5255fcf5ef2aSThomas Huth #else 52569f0cf041SMatheus Ferst CHK_HV(ctx); 5257fcf5ef2aSThomas Huth 5258fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5259fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5260fcf5ef2aSThomas Huth } 5261fcf5ef2aSThomas Huth 5262fcf5ef2aSThomas Huth /* tlbsync */ 5263fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5264fcf5ef2aSThomas Huth { 5265fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52669f0cf041SMatheus Ferst GEN_PRIV(ctx); 5267fcf5ef2aSThomas Huth #else 526891c60f12SCédric Le Goater 526991c60f12SCédric Le Goater if (ctx->gtse) { 52709f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 527191c60f12SCédric Le Goater } else { 52729f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 527391c60f12SCédric Le Goater } 5274fcf5ef2aSThomas Huth 5275fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5276fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5277fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5278fcf5ef2aSThomas Huth } 5279fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5280fcf5ef2aSThomas Huth } 5281fcf5ef2aSThomas Huth 5282fcf5ef2aSThomas Huth /*** External control ***/ 5283fcf5ef2aSThomas Huth /* Optional: */ 5284fcf5ef2aSThomas Huth 5285fcf5ef2aSThomas Huth /* eciwx */ 5286fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5287fcf5ef2aSThomas Huth { 5288fcf5ef2aSThomas Huth TCGv t0; 5289fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5290fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5291fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5292fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5293c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5294c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5295fcf5ef2aSThomas Huth } 5296fcf5ef2aSThomas Huth 5297fcf5ef2aSThomas Huth /* ecowx */ 5298fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5299fcf5ef2aSThomas Huth { 5300fcf5ef2aSThomas Huth TCGv t0; 5301fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5302fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5303fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5304fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5305c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5306c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5307fcf5ef2aSThomas Huth } 5308fcf5ef2aSThomas Huth 5309fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5310fcf5ef2aSThomas Huth 5311fcf5ef2aSThomas Huth /* tlbld */ 5312fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5313fcf5ef2aSThomas Huth { 5314fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53159f0cf041SMatheus Ferst GEN_PRIV(ctx); 5316fcf5ef2aSThomas Huth #else 53179f0cf041SMatheus Ferst CHK_SV(ctx); 5318fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5319fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5320fcf5ef2aSThomas Huth } 5321fcf5ef2aSThomas Huth 5322fcf5ef2aSThomas Huth /* tlbli */ 5323fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5324fcf5ef2aSThomas Huth { 5325fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53269f0cf041SMatheus Ferst GEN_PRIV(ctx); 5327fcf5ef2aSThomas Huth #else 53289f0cf041SMatheus Ferst CHK_SV(ctx); 5329fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5330fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5331fcf5ef2aSThomas Huth } 5332fcf5ef2aSThomas Huth 5333fcf5ef2aSThomas Huth /* BookE specific instructions */ 5334fcf5ef2aSThomas Huth 5335fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5336fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5337fcf5ef2aSThomas Huth { 5338fcf5ef2aSThomas Huth /* XXX: TODO */ 5339fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5340fcf5ef2aSThomas Huth } 5341fcf5ef2aSThomas Huth 5342fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5343fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5344fcf5ef2aSThomas Huth { 5345fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53469f0cf041SMatheus Ferst GEN_PRIV(ctx); 5347fcf5ef2aSThomas Huth #else 5348fcf5ef2aSThomas Huth TCGv t0; 5349fcf5ef2aSThomas Huth 53509f0cf041SMatheus Ferst CHK_SV(ctx); 5351fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5352fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5353fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5354fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5355fcf5ef2aSThomas Huth } 5356fcf5ef2aSThomas Huth 5357fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5358fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5359fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5360fcf5ef2aSThomas Huth { 5361fcf5ef2aSThomas Huth TCGv t0, t1; 5362fcf5ef2aSThomas Huth 53639723281fSRichard Henderson t0 = tcg_temp_new(); 53649723281fSRichard Henderson t1 = tcg_temp_new(); 5365fcf5ef2aSThomas Huth 5366fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5367fcf5ef2aSThomas Huth case 0x05: 5368fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5369fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5370fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5371fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5372fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5373fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5374fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5375fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5376fcf5ef2aSThomas Huth break; 5377fcf5ef2aSThomas Huth case 0x04: 5378fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5379fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5380fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5381fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5382fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5383fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5384fcf5ef2aSThomas Huth break; 5385fcf5ef2aSThomas Huth case 0x01: 5386fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5387fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5388fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5389fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5390fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5391fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5392fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5393fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5394fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5395fcf5ef2aSThomas Huth break; 5396fcf5ef2aSThomas Huth case 0x00: 5397fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5398fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5399fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5400fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5401fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5402fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5403fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5404fcf5ef2aSThomas Huth break; 5405fcf5ef2aSThomas Huth case 0x0D: 5406fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5407fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5408fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5409fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5410fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5411fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5412fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5413fcf5ef2aSThomas Huth break; 5414fcf5ef2aSThomas Huth case 0x0C: 5415fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5416fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5417fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5418fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5419fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5420fcf5ef2aSThomas Huth break; 5421fcf5ef2aSThomas Huth } 5422fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5423fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5424fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5425fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5426fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5427fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5428fcf5ef2aSThomas Huth } else { 5429fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5430fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5431fcf5ef2aSThomas Huth } 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5434fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5435fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5436fcf5ef2aSThomas Huth 5437fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5438fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5439fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5440fcf5ef2aSThomas Huth } 5441fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5442fcf5ef2aSThomas Huth /* Signed */ 5443fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5444fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5445fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5446fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5447fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5448fcf5ef2aSThomas Huth /* Saturate */ 5449fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5450fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5451fcf5ef2aSThomas Huth } 5452fcf5ef2aSThomas Huth } else { 5453fcf5ef2aSThomas Huth /* Unsigned */ 5454fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5455fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5456fcf5ef2aSThomas Huth /* Saturate */ 5457fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5458fcf5ef2aSThomas Huth } 5459fcf5ef2aSThomas Huth } 5460fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5461fcf5ef2aSThomas Huth /* Check overflow */ 5462fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5463fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5464fcf5ef2aSThomas Huth } 5465fcf5ef2aSThomas Huth gen_set_label(l1); 5466fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5467fcf5ef2aSThomas Huth } 5468fcf5ef2aSThomas Huth } else { 5469fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5470fcf5ef2aSThomas Huth } 5471fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5472fcf5ef2aSThomas Huth /* Update Rc0 */ 5473fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5474fcf5ef2aSThomas Huth } 5475fcf5ef2aSThomas Huth } 5476fcf5ef2aSThomas Huth 5477fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5478fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5479fcf5ef2aSThomas Huth { \ 5480fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5481fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5482fcf5ef2aSThomas Huth } 5483fcf5ef2aSThomas Huth 5484fcf5ef2aSThomas Huth /* macchw - macchw. */ 5485fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5486fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5487fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5488fcf5ef2aSThomas Huth /* macchws - macchws. */ 5489fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5490fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5491fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5492fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5493fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5494fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5495fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5496fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5497fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5498fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5499fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5500fcf5ef2aSThomas Huth /* machhw - machhw. */ 5501fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5502fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5503fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5504fcf5ef2aSThomas Huth /* machhws - machhws. */ 5505fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5506fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5507fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5508fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5509fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5510fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5511fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5512fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5513fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5514fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5515fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5516fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5517fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5518fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5519fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5520fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5521fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5522fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5523fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5524fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5525fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5526fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5527fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5528fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5529fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5530fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5531fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5532fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5533fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5534fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5535fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5536fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5537fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5538fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5539fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5540fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5541fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5542fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5543fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5544fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5545fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5546fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5547fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5548fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5550fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5552fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5554fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5556fcf5ef2aSThomas Huth 5557fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5559fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5561fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5563fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5565fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5567fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5569fcf5ef2aSThomas Huth 5570fcf5ef2aSThomas Huth /* mfdcr */ 5571fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5572fcf5ef2aSThomas Huth { 5573fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55749f0cf041SMatheus Ferst GEN_PRIV(ctx); 5575fcf5ef2aSThomas Huth #else 5576fcf5ef2aSThomas Huth TCGv dcrn; 5577fcf5ef2aSThomas Huth 55789f0cf041SMatheus Ferst CHK_SV(ctx); 55797058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5580fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5581fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5582fcf5ef2aSThomas Huth } 5583fcf5ef2aSThomas Huth 5584fcf5ef2aSThomas Huth /* mtdcr */ 5585fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5586fcf5ef2aSThomas Huth { 5587fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55889f0cf041SMatheus Ferst GEN_PRIV(ctx); 5589fcf5ef2aSThomas Huth #else 5590fcf5ef2aSThomas Huth TCGv dcrn; 5591fcf5ef2aSThomas Huth 55929f0cf041SMatheus Ferst CHK_SV(ctx); 55937058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5594fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5595fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5596fcf5ef2aSThomas Huth } 5597fcf5ef2aSThomas Huth 5598fcf5ef2aSThomas Huth /* mfdcrx */ 5599fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5600fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5601fcf5ef2aSThomas Huth { 5602fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56039f0cf041SMatheus Ferst GEN_PRIV(ctx); 5604fcf5ef2aSThomas Huth #else 56059f0cf041SMatheus Ferst CHK_SV(ctx); 5606fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5607fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5608fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5609fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5610fcf5ef2aSThomas Huth } 5611fcf5ef2aSThomas Huth 5612fcf5ef2aSThomas Huth /* mtdcrx */ 5613fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5614fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5615fcf5ef2aSThomas Huth { 5616fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56179f0cf041SMatheus Ferst GEN_PRIV(ctx); 5618fcf5ef2aSThomas Huth #else 56199f0cf041SMatheus Ferst CHK_SV(ctx); 5620fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5621fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5622fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5623fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5624fcf5ef2aSThomas Huth } 5625fcf5ef2aSThomas Huth 5626fcf5ef2aSThomas Huth /* dccci */ 5627fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5628fcf5ef2aSThomas Huth { 56299f0cf041SMatheus Ferst CHK_SV(ctx); 5630fcf5ef2aSThomas Huth /* interpreted as no-op */ 5631fcf5ef2aSThomas Huth } 5632fcf5ef2aSThomas Huth 5633fcf5ef2aSThomas Huth /* dcread */ 5634fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5635fcf5ef2aSThomas Huth { 5636fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56379f0cf041SMatheus Ferst GEN_PRIV(ctx); 5638fcf5ef2aSThomas Huth #else 5639fcf5ef2aSThomas Huth TCGv EA, val; 5640fcf5ef2aSThomas Huth 56419f0cf041SMatheus Ferst CHK_SV(ctx); 5642fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5643fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5644fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5645fcf5ef2aSThomas Huth val = tcg_temp_new(); 5646fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5647fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5648fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5649fcf5ef2aSThomas Huth } 5650fcf5ef2aSThomas Huth 5651fcf5ef2aSThomas Huth /* icbt */ 5652fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5653fcf5ef2aSThomas Huth { 5654efe843d8SDavid Gibson /* 5655efe843d8SDavid Gibson * interpreted as no-op 5656efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5657efe843d8SDavid Gibson * does not generate any exception 5658fcf5ef2aSThomas Huth */ 5659fcf5ef2aSThomas Huth } 5660fcf5ef2aSThomas Huth 5661fcf5ef2aSThomas Huth /* iccci */ 5662fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5663fcf5ef2aSThomas Huth { 56649f0cf041SMatheus Ferst CHK_SV(ctx); 5665fcf5ef2aSThomas Huth /* interpreted as no-op */ 5666fcf5ef2aSThomas Huth } 5667fcf5ef2aSThomas Huth 5668fcf5ef2aSThomas Huth /* icread */ 5669fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5670fcf5ef2aSThomas Huth { 56719f0cf041SMatheus Ferst CHK_SV(ctx); 5672fcf5ef2aSThomas Huth /* interpreted as no-op */ 5673fcf5ef2aSThomas Huth } 5674fcf5ef2aSThomas Huth 5675fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5676fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5677fcf5ef2aSThomas Huth { 5678fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56799f0cf041SMatheus Ferst GEN_PRIV(ctx); 5680fcf5ef2aSThomas Huth #else 56819f0cf041SMatheus Ferst CHK_SV(ctx); 5682fcf5ef2aSThomas Huth /* Restore CPU state */ 5683fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 568459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5685fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5686fcf5ef2aSThomas Huth } 5687fcf5ef2aSThomas Huth 5688fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5689fcf5ef2aSThomas Huth { 5690fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56919f0cf041SMatheus Ferst GEN_PRIV(ctx); 5692fcf5ef2aSThomas Huth #else 56939f0cf041SMatheus Ferst CHK_SV(ctx); 5694fcf5ef2aSThomas Huth /* Restore CPU state */ 5695fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 569659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5697fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5698fcf5ef2aSThomas Huth } 5699fcf5ef2aSThomas Huth 5700fcf5ef2aSThomas Huth /* BookE specific */ 5701fcf5ef2aSThomas Huth 5702fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5703fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5704fcf5ef2aSThomas Huth { 5705fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57069f0cf041SMatheus Ferst GEN_PRIV(ctx); 5707fcf5ef2aSThomas Huth #else 57089f0cf041SMatheus Ferst CHK_SV(ctx); 5709fcf5ef2aSThomas Huth /* Restore CPU state */ 5710fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 571159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5712fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5713fcf5ef2aSThomas Huth } 5714fcf5ef2aSThomas Huth 5715fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5716fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5717fcf5ef2aSThomas Huth { 5718fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57199f0cf041SMatheus Ferst GEN_PRIV(ctx); 5720fcf5ef2aSThomas Huth #else 57219f0cf041SMatheus Ferst CHK_SV(ctx); 5722fcf5ef2aSThomas Huth /* Restore CPU state */ 5723fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 572459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5725fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5726fcf5ef2aSThomas Huth } 5727fcf5ef2aSThomas Huth 5728fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5729fcf5ef2aSThomas Huth 5730fcf5ef2aSThomas Huth /* tlbre */ 5731fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5732fcf5ef2aSThomas Huth { 5733fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57349f0cf041SMatheus Ferst GEN_PRIV(ctx); 5735fcf5ef2aSThomas Huth #else 57369f0cf041SMatheus Ferst CHK_SV(ctx); 5737fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5738fcf5ef2aSThomas Huth case 0: 5739fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5740fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5741fcf5ef2aSThomas Huth break; 5742fcf5ef2aSThomas Huth case 1: 5743fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5744fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5745fcf5ef2aSThomas Huth break; 5746fcf5ef2aSThomas Huth default: 5747fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5748fcf5ef2aSThomas Huth break; 5749fcf5ef2aSThomas Huth } 5750fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5751fcf5ef2aSThomas Huth } 5752fcf5ef2aSThomas Huth 5753fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5754fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5755fcf5ef2aSThomas Huth { 5756fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57579f0cf041SMatheus Ferst GEN_PRIV(ctx); 5758fcf5ef2aSThomas Huth #else 5759fcf5ef2aSThomas Huth TCGv t0; 5760fcf5ef2aSThomas Huth 57619f0cf041SMatheus Ferst CHK_SV(ctx); 5762fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5763fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5764fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5765fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5766fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5767fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5768fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5769fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5770fcf5ef2aSThomas Huth gen_set_label(l1); 5771fcf5ef2aSThomas Huth } 5772fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5773fcf5ef2aSThomas Huth } 5774fcf5ef2aSThomas Huth 5775fcf5ef2aSThomas Huth /* tlbwe */ 5776fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5777fcf5ef2aSThomas Huth { 5778fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57799f0cf041SMatheus Ferst GEN_PRIV(ctx); 5780fcf5ef2aSThomas Huth #else 57819f0cf041SMatheus Ferst CHK_SV(ctx); 5782fcf5ef2aSThomas Huth 5783fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5784fcf5ef2aSThomas Huth case 0: 5785fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5786fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5787fcf5ef2aSThomas Huth break; 5788fcf5ef2aSThomas Huth case 1: 5789fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5790fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5791fcf5ef2aSThomas Huth break; 5792fcf5ef2aSThomas Huth default: 5793fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5794fcf5ef2aSThomas Huth break; 5795fcf5ef2aSThomas Huth } 5796fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5797fcf5ef2aSThomas Huth } 5798fcf5ef2aSThomas Huth 5799fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5800fcf5ef2aSThomas Huth 5801fcf5ef2aSThomas Huth /* tlbre */ 5802fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5803fcf5ef2aSThomas Huth { 5804fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58059f0cf041SMatheus Ferst GEN_PRIV(ctx); 5806fcf5ef2aSThomas Huth #else 58079f0cf041SMatheus Ferst CHK_SV(ctx); 5808fcf5ef2aSThomas Huth 5809fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5810fcf5ef2aSThomas Huth case 0: 5811fcf5ef2aSThomas Huth case 1: 5812fcf5ef2aSThomas Huth case 2: 5813fcf5ef2aSThomas Huth { 58147058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5815fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5816fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5817fcf5ef2aSThomas Huth } 5818fcf5ef2aSThomas Huth break; 5819fcf5ef2aSThomas Huth default: 5820fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5821fcf5ef2aSThomas Huth break; 5822fcf5ef2aSThomas Huth } 5823fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5824fcf5ef2aSThomas Huth } 5825fcf5ef2aSThomas Huth 5826fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5827fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5828fcf5ef2aSThomas Huth { 5829fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58309f0cf041SMatheus Ferst GEN_PRIV(ctx); 5831fcf5ef2aSThomas Huth #else 5832fcf5ef2aSThomas Huth TCGv t0; 5833fcf5ef2aSThomas Huth 58349f0cf041SMatheus Ferst CHK_SV(ctx); 5835fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5836fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5837fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5838fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5839fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5840fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5841fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5842fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5843fcf5ef2aSThomas Huth gen_set_label(l1); 5844fcf5ef2aSThomas Huth } 5845fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5846fcf5ef2aSThomas Huth } 5847fcf5ef2aSThomas Huth 5848fcf5ef2aSThomas Huth /* tlbwe */ 5849fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5850fcf5ef2aSThomas Huth { 5851fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58529f0cf041SMatheus Ferst GEN_PRIV(ctx); 5853fcf5ef2aSThomas Huth #else 58549f0cf041SMatheus Ferst CHK_SV(ctx); 5855fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5856fcf5ef2aSThomas Huth case 0: 5857fcf5ef2aSThomas Huth case 1: 5858fcf5ef2aSThomas Huth case 2: 5859fcf5ef2aSThomas Huth { 58607058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5861fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5862fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5863fcf5ef2aSThomas Huth } 5864fcf5ef2aSThomas Huth break; 5865fcf5ef2aSThomas Huth default: 5866fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5867fcf5ef2aSThomas Huth break; 5868fcf5ef2aSThomas Huth } 5869fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5870fcf5ef2aSThomas Huth } 5871fcf5ef2aSThomas Huth 5872fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5873fcf5ef2aSThomas Huth 5874fcf5ef2aSThomas Huth /* tlbre */ 5875fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5876fcf5ef2aSThomas Huth { 5877fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58789f0cf041SMatheus Ferst GEN_PRIV(ctx); 5879fcf5ef2aSThomas Huth #else 58809f0cf041SMatheus Ferst CHK_SV(ctx); 5881fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5882fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5883fcf5ef2aSThomas Huth } 5884fcf5ef2aSThomas Huth 5885fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5886fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5887fcf5ef2aSThomas Huth { 5888fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58899f0cf041SMatheus Ferst GEN_PRIV(ctx); 5890fcf5ef2aSThomas Huth #else 5891fcf5ef2aSThomas Huth TCGv t0; 5892fcf5ef2aSThomas Huth 58939f0cf041SMatheus Ferst CHK_SV(ctx); 5894fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5895fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 58969d15d8e1SRichard Henderson tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5897fcf5ef2aSThomas Huth } else { 58989d15d8e1SRichard Henderson t0 = cpu_gpr[rB(ctx->opcode)]; 5899fcf5ef2aSThomas Huth } 5900fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5901fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5902fcf5ef2aSThomas Huth } 5903fcf5ef2aSThomas Huth 5904fcf5ef2aSThomas Huth /* tlbwe */ 5905fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5906fcf5ef2aSThomas Huth { 5907fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59089f0cf041SMatheus Ferst GEN_PRIV(ctx); 5909fcf5ef2aSThomas Huth #else 59109f0cf041SMatheus Ferst CHK_SV(ctx); 5911fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5912fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5913fcf5ef2aSThomas Huth } 5914fcf5ef2aSThomas Huth 5915fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5916fcf5ef2aSThomas Huth { 5917fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59189f0cf041SMatheus Ferst GEN_PRIV(ctx); 5919fcf5ef2aSThomas Huth #else 5920fcf5ef2aSThomas Huth TCGv t0; 5921fcf5ef2aSThomas Huth 59229f0cf041SMatheus Ferst CHK_SV(ctx); 5923fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5924fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5925fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5926fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5927fcf5ef2aSThomas Huth } 5928fcf5ef2aSThomas Huth 5929fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5930fcf5ef2aSThomas Huth { 5931fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59329f0cf041SMatheus Ferst GEN_PRIV(ctx); 5933fcf5ef2aSThomas Huth #else 5934fcf5ef2aSThomas Huth TCGv t0; 5935fcf5ef2aSThomas Huth 59369f0cf041SMatheus Ferst CHK_SV(ctx); 5937fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5938fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5939fcf5ef2aSThomas Huth 5940fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 5941fcf5ef2aSThomas Huth case 0: 5942fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 5943fcf5ef2aSThomas Huth break; 5944fcf5ef2aSThomas Huth case 1: 5945fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 5946fcf5ef2aSThomas Huth break; 5947fcf5ef2aSThomas Huth case 3: 5948fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 5949fcf5ef2aSThomas Huth break; 5950fcf5ef2aSThomas Huth default: 5951fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5952fcf5ef2aSThomas Huth break; 5953fcf5ef2aSThomas Huth } 5954fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5955fcf5ef2aSThomas Huth } 5956fcf5ef2aSThomas Huth 5957fcf5ef2aSThomas Huth /* wrtee */ 5958fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 5959fcf5ef2aSThomas Huth { 5960fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59619f0cf041SMatheus Ferst GEN_PRIV(ctx); 5962fcf5ef2aSThomas Huth #else 5963fcf5ef2aSThomas Huth TCGv t0; 5964fcf5ef2aSThomas Huth 59659f0cf041SMatheus Ferst CHK_SV(ctx); 5966fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5967fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5968fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5969fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 59702fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5971efe843d8SDavid Gibson /* 5972efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 5973efe843d8SDavid Gibson * just set msr_ee to 1 5974fcf5ef2aSThomas Huth */ 5975d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5976fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5977fcf5ef2aSThomas Huth } 5978fcf5ef2aSThomas Huth 5979fcf5ef2aSThomas Huth /* wrteei */ 5980fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 5981fcf5ef2aSThomas Huth { 5982fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59839f0cf041SMatheus Ferst GEN_PRIV(ctx); 5984fcf5ef2aSThomas Huth #else 59859f0cf041SMatheus Ferst CHK_SV(ctx); 5986fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 5987fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 59882fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5989fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 5990d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5991fcf5ef2aSThomas Huth } else { 5992fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5993fcf5ef2aSThomas Huth } 5994fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5995fcf5ef2aSThomas Huth } 5996fcf5ef2aSThomas Huth 5997fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 5998fcf5ef2aSThomas Huth 5999fcf5ef2aSThomas Huth /* dlmzb */ 6000fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6001fcf5ef2aSThomas Huth { 60027058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6003fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6004fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6005fcf5ef2aSThomas Huth } 6006fcf5ef2aSThomas Huth 6007fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6008fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6009fcf5ef2aSThomas Huth { 6010fcf5ef2aSThomas Huth /* interpreted as no-op */ 6011fcf5ef2aSThomas Huth } 6012fcf5ef2aSThomas Huth 6013fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6014fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6015fcf5ef2aSThomas Huth { 601627a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 601727a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 601827a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 601927a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 602027a3ea7eSBALATON Zoltan } 602127a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6022fcf5ef2aSThomas Huth } 6023fcf5ef2aSThomas Huth 6024fcf5ef2aSThomas Huth /* icbt */ 6025fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6026fcf5ef2aSThomas Huth { 6027efe843d8SDavid Gibson /* 6028efe843d8SDavid Gibson * interpreted as no-op 6029efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6030efe843d8SDavid Gibson * does not generate any exception 6031fcf5ef2aSThomas Huth */ 6032fcf5ef2aSThomas Huth } 6033fcf5ef2aSThomas Huth 6034fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6035fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6036fcf5ef2aSThomas Huth { 6037fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6038fcf5ef2aSThomas Huth 6039fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6040fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6041fcf5ef2aSThomas Huth } 6042fcf5ef2aSThomas Huth 6043fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6044fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6045fcf5ef2aSThomas Huth { 6046fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6047fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6048fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6049fcf5ef2aSThomas Huth 6050fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6051fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6052fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6053fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6054fcf5ef2aSThomas Huth } else { 6055fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6056fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6057fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6058fcf5ef2aSThomas Huth } 6059fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6060fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6061fcf5ef2aSThomas Huth } 6062fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6063fcf5ef2aSThomas Huth 6064fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6065fcf5ef2aSThomas Huth { 6066fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6067fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6068fcf5ef2aSThomas Huth return; 6069fcf5ef2aSThomas Huth } 6070fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6071fcf5ef2aSThomas Huth } 6072fcf5ef2aSThomas Huth 6073fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6074fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6075fcf5ef2aSThomas Huth { \ 6076fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6077fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6078fcf5ef2aSThomas Huth return; \ 6079fcf5ef2aSThomas Huth } \ 6080efe843d8SDavid Gibson /* \ 6081efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6082fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6083fcf5ef2aSThomas Huth * \ 6084fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6085fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6086fcf5ef2aSThomas Huth */ \ 6087fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6088fcf5ef2aSThomas Huth } 6089fcf5ef2aSThomas Huth 6090fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6091fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6092fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6093fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6094fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6095fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6096fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6097efe843d8SDavid Gibson 6098b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6099b8b4576eSSuraj Jitindar Singh { 6100efe843d8SDavid Gibson /* Do Nothing */ 6101b8b4576eSSuraj Jitindar Singh } 6102fcf5ef2aSThomas Huth 610380b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 610480b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 610580b8c1eeSNikunj A Dadhania { \ 6106efe843d8SDavid Gibson /* \ 6107efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6108efe843d8SDavid Gibson * implementation of the copy paste facility \ 610980b8c1eeSNikunj A Dadhania */ \ 611080b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 611180b8c1eeSNikunj A Dadhania } 611280b8c1eeSNikunj A Dadhania 611380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 611480b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 611580b8c1eeSNikunj A Dadhania 6116fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6117fcf5ef2aSThomas Huth { 6118fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6119fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6120fcf5ef2aSThomas Huth return; 6121fcf5ef2aSThomas Huth } 6122efe843d8SDavid Gibson /* 6123efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6124efe843d8SDavid Gibson * simple: 6125fcf5ef2aSThomas Huth * 6126fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6127fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6128fcf5ef2aSThomas Huth */ 6129fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6130fcf5ef2aSThomas Huth } 6131fcf5ef2aSThomas Huth 6132fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6133fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6134fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6135fcf5ef2aSThomas Huth { \ 61369f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6137fcf5ef2aSThomas Huth } 6138fcf5ef2aSThomas Huth 6139fcf5ef2aSThomas Huth #else 6140fcf5ef2aSThomas Huth 6141fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6142fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6143fcf5ef2aSThomas Huth { \ 61449f0cf041SMatheus Ferst CHK_SV(ctx); \ 6145fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6146fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6147fcf5ef2aSThomas Huth return; \ 6148fcf5ef2aSThomas Huth } \ 6149efe843d8SDavid Gibson /* \ 6150efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6151fcf5ef2aSThomas Huth * simple: \ 6152fcf5ef2aSThomas Huth * \ 6153fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6154fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6155fcf5ef2aSThomas Huth */ \ 6156fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6157fcf5ef2aSThomas Huth } 6158fcf5ef2aSThomas Huth 6159fcf5ef2aSThomas Huth #endif 6160fcf5ef2aSThomas Huth 6161fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6162fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6163fcf5ef2aSThomas Huth 61641a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 61651a404c91SMark Cave-Ayland { 6166e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 61671a404c91SMark Cave-Ayland } 61681a404c91SMark Cave-Ayland 61691a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 61701a404c91SMark Cave-Ayland { 6171e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 61724b65b6e7SVíctor Colombo /* 61734b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 61744b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 61754b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 61764b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 61774b65b6e7SVíctor Colombo * to be 0. 61784b65b6e7SVíctor Colombo */ 61794b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 61801a404c91SMark Cave-Ayland } 61811a404c91SMark Cave-Ayland 6182c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6183c4a18dbfSMark Cave-Ayland { 618437da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6185c4a18dbfSMark Cave-Ayland } 6186c4a18dbfSMark Cave-Ayland 6187c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6188c4a18dbfSMark Cave-Ayland { 618937da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6190c4a18dbfSMark Cave-Ayland } 6191c4a18dbfSMark Cave-Ayland 6192c9826ae9SRichard Henderson /* 6193f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6194f2aabda8SRichard Henderson */ 6195d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6196d39b2cc7SLuis Pires { 6197d39b2cc7SLuis Pires return x * 2; 6198d39b2cc7SLuis Pires } 6199d39b2cc7SLuis Pires 6200f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6201f2aabda8SRichard Henderson { 6202f2aabda8SRichard Henderson return x * 4; 6203f2aabda8SRichard Henderson } 6204f2aabda8SRichard Henderson 6205e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6206e10271e1SMatheus Ferst { 6207e10271e1SMatheus Ferst return x * 16; 6208e10271e1SMatheus Ferst } 6209e10271e1SMatheus Ferst 6210670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6211670f1da3SVíctor Colombo { 6212670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6213670f1da3SVíctor Colombo } 6214670f1da3SVíctor Colombo 6215f2aabda8SRichard Henderson /* 6216c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6217c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6218c9826ae9SRichard Henderson * proper variable. 6219c9826ae9SRichard Henderson */ 6220c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6221c9826ae9SRichard Henderson do { \ 6222c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6223c9826ae9SRichard Henderson return false; \ 6224c9826ae9SRichard Henderson } \ 6225c9826ae9SRichard Henderson } while (0) 6226c9826ae9SRichard Henderson 6227c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6228c9826ae9SRichard Henderson do { \ 6229c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6230c9826ae9SRichard Henderson return false; \ 6231c9826ae9SRichard Henderson } \ 6232c9826ae9SRichard Henderson } while (0) 6233c9826ae9SRichard Henderson 6234c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6235c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6236c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6237c9826ae9SRichard Henderson #else 6238c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6239c9826ae9SRichard Henderson #endif 6240c9826ae9SRichard Henderson 6241e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6242e2205a46SBruno Larsen do { \ 6243e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6244e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6245e2205a46SBruno Larsen return true; \ 6246e2205a46SBruno Larsen } \ 6247e2205a46SBruno Larsen } while (0) 6248e2205a46SBruno Larsen 62498226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 62508226cb2dSBruno Larsen (billionai) do { \ 62518226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 62528226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 62538226cb2dSBruno Larsen (billionai) return true; \ 62548226cb2dSBruno Larsen (billionai) } \ 62558226cb2dSBruno Larsen (billionai) } while (0) 62568226cb2dSBruno Larsen (billionai) 625786057426SFernando Valle #define REQUIRE_FPU(ctx) \ 625886057426SFernando Valle do { \ 625986057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 626086057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 626186057426SFernando Valle return true; \ 626286057426SFernando Valle } \ 626386057426SFernando Valle } while (0) 626486057426SFernando Valle 6265fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6266fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6267fc34e81aSMatheus Ferst do { \ 6268fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6269fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6270fc34e81aSMatheus Ferst return true; \ 6271fc34e81aSMatheus Ferst } \ 6272fc34e81aSMatheus Ferst } while (0) 6273fc34e81aSMatheus Ferst 6274fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6275fc34e81aSMatheus Ferst do { \ 6276e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6277fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6278fc34e81aSMatheus Ferst return true; \ 6279fc34e81aSMatheus Ferst } \ 6280fc34e81aSMatheus Ferst } while (0) 6281fc34e81aSMatheus Ferst #else 6282fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6283fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6284fc34e81aSMatheus Ferst #endif 6285fc34e81aSMatheus Ferst 6286f2aabda8SRichard Henderson /* 6287f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6288f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6289f2aabda8SRichard Henderson */ 6290f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6291f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6292f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 629319f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 629419f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 629519f0862dSLuis Pires { \ 629619f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 629719f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 629819f0862dSLuis Pires } 629919f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 630019f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 630119f0862dSLuis Pires { \ 630219f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 630319f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 630419f0862dSLuis Pires } 6305f2aabda8SRichard Henderson 6306f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6307f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6308f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 630919f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 631019f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 631119f0862dSLuis Pires { \ 631219f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 631319f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 631419f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 631519f0862dSLuis Pires } 6316f2aabda8SRichard Henderson 6317f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6318f2aabda8SRichard Henderson 6319f2aabda8SRichard Henderson 632099082815SRichard Henderson #include "decode-insn32.c.inc" 632199082815SRichard Henderson #include "decode-insn64.c.inc" 6322565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6323565cb109SGustavo Romero 6324725b2d4dSFernando Eckhardt Valle /* 6325725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6326725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6327725b2d4dSFernando Eckhardt Valle */ 6328725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6329725b2d4dSFernando Eckhardt Valle { 6330725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6331725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6332725b2d4dSFernando Eckhardt Valle d->si = a->si; 6333725b2d4dSFernando Eckhardt Valle if (a->r) { 6334725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6335725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6336725b2d4dSFernando Eckhardt Valle return false; 6337725b2d4dSFernando Eckhardt Valle } 6338725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6339725b2d4dSFernando Eckhardt Valle } 6340725b2d4dSFernando Eckhardt Valle return true; 6341725b2d4dSFernando Eckhardt Valle } 6342725b2d4dSFernando Eckhardt Valle 634399082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 634499082815SRichard Henderson 6345139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6346fcf5ef2aSThomas Huth 6347139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6348fcf5ef2aSThomas Huth 6349139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6350fcf5ef2aSThomas Huth 6351139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6352fcf5ef2aSThomas Huth 6353139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6354fcf5ef2aSThomas Huth 63551f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 63561f26c751SDaniel Henrique Barboza 635798f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 635898f43417SMatheus Ferst 6359016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6360016b6e1dSLeandro Lupori 636120e2d04eSLeandro Lupori /* Handles lfdp */ 63625cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 63635cb091a4SNikunj A Dadhania { 636420e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 63655cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 63665cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 63675cb091a4SNikunj A Dadhania } 63685cb091a4SNikunj A Dadhania } 63695cb091a4SNikunj A Dadhania return gen_invalid(ctx); 63705cb091a4SNikunj A Dadhania } 63715cb091a4SNikunj A Dadhania 637220e2d04eSLeandro Lupori /* Handles stfdp */ 6373e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6374e3001664SNikunj A Dadhania { 637520e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 637620e2d04eSLeandro Lupori /* stfdp */ 6377e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6378e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6379e3001664SNikunj A Dadhania } 6380e3001664SNikunj A Dadhania } 6381e3001664SNikunj A Dadhania return gen_invalid(ctx); 6382e3001664SNikunj A Dadhania } 6383e3001664SNikunj A Dadhania 63849d69cfa2SLijun Pan #if defined(TARGET_PPC64) 63859d69cfa2SLijun Pan /* brd */ 63869d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 63879d69cfa2SLijun Pan { 63889d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 63899d69cfa2SLijun Pan } 63909d69cfa2SLijun Pan 63919d69cfa2SLijun Pan /* brw */ 63929d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 63939d69cfa2SLijun Pan { 63949d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 63959d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 63969d69cfa2SLijun Pan 63979d69cfa2SLijun Pan } 63989d69cfa2SLijun Pan 63999d69cfa2SLijun Pan /* brh */ 64009d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 64019d69cfa2SLijun Pan { 6402491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 64039d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 64049d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 64059d69cfa2SLijun Pan 64069d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6407491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6408491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 64099d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 64109d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 64119d69cfa2SLijun Pan } 64129d69cfa2SLijun Pan #endif 64139d69cfa2SLijun Pan 6414fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 64159d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64169d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 64179d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 64189d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 64199d69cfa2SLijun Pan #endif 6420fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6421fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6422fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6423fcf5ef2aSThomas Huth #endif 6424fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6425fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6426fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6427fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6428fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6429fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6430fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6431fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6432fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6433fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6434fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6435fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6436fcf5ef2aSThomas Huth #endif 6437fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6438fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6439fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6440fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6441fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6442fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6443fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 644480b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6445b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 644680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6447fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6448fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6449fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6450fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6451fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6452fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6453fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6454fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6455fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6456fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6457fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6458fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6459fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6460fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6461fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6462fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6463fcf5ef2aSThomas Huth #endif 6464fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6465fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6466fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6467fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6468fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6469fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6470fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6471fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6472fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6473fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6474fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6475fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6476fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6477fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6478fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6479fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6480fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6481fcf5ef2aSThomas Huth #endif 64825cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 64835cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 648472b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6485e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6486fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6487fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6488fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6489fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6490fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6491fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6492c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6493fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6494fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6495fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6496fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6497a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6498a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6499fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6500fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6501fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6502fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6503a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6504a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6505fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6506fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6507fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6508fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6509fcf5ef2aSThomas Huth #endif 6510fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 65110c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 65120c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 65130c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6514fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6515fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6516fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6517fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6518fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6519fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6520fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6521fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6522fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 65233c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 65243c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65253c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65263c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65273c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 65283c89b8d6SNicholas Piggin #endif 6529cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6530fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6531fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6532fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6533fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6534fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6535fcf5ef2aSThomas Huth #endif 65363c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65373c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 65383c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6539fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6540fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6541fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6542fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6543fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6544fcf5ef2aSThomas Huth #endif 6545fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6546fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6547fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6548fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6549fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6550fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6551fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6552fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6553fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6554b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6555fcf5ef2aSThomas Huth #endif 6556fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6557fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6558fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 655950728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6560fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6561fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 656250728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6563fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 656450728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6565fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 656650728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6567fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6568e64645baSBernhard Beschow GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6569fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 657050728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6571fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 657299d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6573fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6574fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 657550728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6576fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6577fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6578fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6579fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6580fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6581fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6582fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6583fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6584fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6585fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6586fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6587fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6588fcf5ef2aSThomas Huth #endif 6589fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6590efe843d8SDavid Gibson /* 6591efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6592efe843d8SDavid Gibson * different ISA versions 6593efe843d8SDavid Gibson */ 6594fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6595fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6596fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6597fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6598fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6599fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6600fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6601fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6602fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6603fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6604fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6605fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6606fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6607fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6608fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6609fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6610fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6611fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6612fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6613fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6614fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6615fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6616fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6617fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6618fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6619fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6620fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6621fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6622fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6623fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6624fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6625fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6626fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6627fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6628fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6629fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6630fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6631fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6632fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6633fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6634fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 663527a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6636fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6637fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 66380c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 66390c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6640fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6641fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6642fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6643fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6644fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6645fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6646fcf5ef2aSThomas Huth PPC2_ISA300), 6647fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6648fcf5ef2aSThomas Huth #endif 6649fcf5ef2aSThomas Huth 6650fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6651fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6652fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6653fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6654fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6655fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6656fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6657fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6658fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6659fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6660fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6661fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6662fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6663fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6664fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 66654c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6666fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6667fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6668fcf5ef2aSThomas Huth 6669fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6670fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6671fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6672fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6673fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6674fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6675fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6676fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6677fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6678fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6679fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6680fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6681fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6682fcf5ef2aSThomas Huth 6683fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6684fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6685fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6686fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6687fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6688fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6689fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6690fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6691fcf5ef2aSThomas Huth 6692fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6693fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6694fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6695fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6696fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6697fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6698fcf5ef2aSThomas Huth 6699fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6700fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6701fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6702fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6703fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6704fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6705fcf5ef2aSThomas Huth #endif 6706fcf5ef2aSThomas Huth 6707fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6708fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6709fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6710fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6711fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6712fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6713fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6714fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6715fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6716fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6717fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6718fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6719fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6720fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6721fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6722fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6723fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6724fcf5ef2aSThomas Huth 6725fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6726fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6727fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6728fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6729fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6730fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6731fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6732fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6733fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6734fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6735fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6736fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6737fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6738fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6739fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6740fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6741fcf5ef2aSThomas Huth #endif 6742fcf5ef2aSThomas Huth 6743fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6744fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6745fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6746fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6747fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6748fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6749fcf5ef2aSThomas Huth PPC_64B) 6750fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6751fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6752fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6753fcf5ef2aSThomas Huth PPC_64B), \ 6754fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6755fcf5ef2aSThomas Huth PPC_64B), \ 6756fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6757fcf5ef2aSThomas Huth PPC_64B) 6758fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6759fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6760fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6761fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6762fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6763fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6764fcf5ef2aSThomas Huth #endif 6765fcf5ef2aSThomas Huth 6766fcf5ef2aSThomas Huth #undef GEN_LDX_E 6767fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6768fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6769fcf5ef2aSThomas Huth 6770fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6771fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6772fcf5ef2aSThomas Huth 6773fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6774fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6775fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6776fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6777fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6778fcf5ef2aSThomas Huth #endif 6779fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6780fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6781fcf5ef2aSThomas Huth 678250728199SRoman Kapl /* External PID based load */ 678350728199SRoman Kapl #undef GEN_LDEPX 678450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 678550728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 678650728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 678750728199SRoman Kapl 678850728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 678950728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 679050728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 679150728199SRoman Kapl #if defined(TARGET_PPC64) 6792fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 679350728199SRoman Kapl #endif 679450728199SRoman Kapl 6795fcf5ef2aSThomas Huth #undef GEN_STX_E 6796fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 67970123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6798fcf5ef2aSThomas Huth 6799fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6800fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6801fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6802fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6803fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6804fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6805fcf5ef2aSThomas Huth #endif 6806fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6807fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6808fcf5ef2aSThomas Huth 680950728199SRoman Kapl #undef GEN_STEPX 681050728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 681150728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 681250728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 681350728199SRoman Kapl 681450728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 681550728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 681650728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 681750728199SRoman Kapl #if defined(TARGET_PPC64) 6818fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 681950728199SRoman Kapl #endif 682050728199SRoman Kapl 6821fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6822fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6823fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6824fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6825fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6826fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6827fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6828fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6829fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6830fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6831fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6832fcf5ef2aSThomas Huth 6833fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6834fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6835fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6836fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6837fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6838fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6839fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6840fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6841fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6842fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6843fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6844fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6845fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6846fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6847fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6848fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6849fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6850fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6851fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6852fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6853fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6854fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6855fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6856fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6857fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6858fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6859fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6860fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6861fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6862fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6863fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6864fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6865fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6866fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6867fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6868fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6869fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6870fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6871fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6872fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6873fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6874fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6875fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6876fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6877fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6878fcf5ef2aSThomas Huth 6879fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6880fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6881fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6882fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6883fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6884fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6885fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6886fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6887fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6888fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6889fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6890fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6891fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6892fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6893fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6894fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6895fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6896fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6897fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6898fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6899fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6900fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6901fcf5ef2aSThomas Huth 6902139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 6903fcf5ef2aSThomas Huth 6904139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 6905fcf5ef2aSThomas Huth 6906139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 6907fcf5ef2aSThomas Huth 6908139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 6909fcf5ef2aSThomas Huth }; 6910fcf5ef2aSThomas Huth 69117468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 69127468e2c8SBruno Larsen (billionai) /* Opcode types */ 69137468e2c8SBruno Larsen (billionai) enum { 69147468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 69157468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 69167468e2c8SBruno Larsen (billionai) }; 69177468e2c8SBruno Larsen (billionai) 69187468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 69197468e2c8SBruno Larsen (billionai) 69207468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 69217468e2c8SBruno Larsen (billionai) { 69227468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 69237468e2c8SBruno Larsen (billionai) } 69247468e2c8SBruno Larsen (billionai) 69257468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 69267468e2c8SBruno Larsen (billionai) { 69277468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 69287468e2c8SBruno Larsen (billionai) } 69297468e2c8SBruno Larsen (billionai) 69307468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 69317468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 69327468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 69337468e2c8SBruno Larsen (billionai) { 69347468e2c8SBruno Larsen (billionai) int i; 69357468e2c8SBruno Larsen (billionai) 69367468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 69377468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 69387468e2c8SBruno Larsen (billionai) } 69397468e2c8SBruno Larsen (billionai) } 69407468e2c8SBruno Larsen (billionai) 69417468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 69427468e2c8SBruno Larsen (billionai) { 69437468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 69447468e2c8SBruno Larsen (billionai) 69457468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 69467468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 69477468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 69487468e2c8SBruno Larsen (billionai) 69497468e2c8SBruno Larsen (billionai) return 0; 69507468e2c8SBruno Larsen (billionai) } 69517468e2c8SBruno Larsen (billionai) 69527468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 69537468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69547468e2c8SBruno Larsen (billionai) { 69557468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 69567468e2c8SBruno Larsen (billionai) return -1; 69577468e2c8SBruno Larsen (billionai) } 69587468e2c8SBruno Larsen (billionai) table[idx] = handler; 69597468e2c8SBruno Larsen (billionai) 69607468e2c8SBruno Larsen (billionai) return 0; 69617468e2c8SBruno Larsen (billionai) } 69627468e2c8SBruno Larsen (billionai) 69637468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 69647468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 69657468e2c8SBruno Larsen (billionai) { 69667468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 69677468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 69687468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 69697468e2c8SBruno Larsen (billionai) return -1; 69707468e2c8SBruno Larsen (billionai) } 69717468e2c8SBruno Larsen (billionai) 69727468e2c8SBruno Larsen (billionai) return 0; 69737468e2c8SBruno Larsen (billionai) } 69747468e2c8SBruno Larsen (billionai) 69757468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 69767468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69777468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69787468e2c8SBruno Larsen (billionai) { 69797468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 69807468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 69817468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 69827468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 69837468e2c8SBruno Larsen (billionai) return -1; 69847468e2c8SBruno Larsen (billionai) } 69857468e2c8SBruno Larsen (billionai) } else { 69867468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 69877468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 69887468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 69897468e2c8SBruno Larsen (billionai) return -1; 69907468e2c8SBruno Larsen (billionai) } 69917468e2c8SBruno Larsen (billionai) } 69927468e2c8SBruno Larsen (billionai) if (handler != NULL && 69937468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 69947468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 69957468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 69967468e2c8SBruno Larsen (billionai) return -1; 69977468e2c8SBruno Larsen (billionai) } 69987468e2c8SBruno Larsen (billionai) 69997468e2c8SBruno Larsen (billionai) return 0; 70007468e2c8SBruno Larsen (billionai) } 70017468e2c8SBruno Larsen (billionai) 70027468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 70037468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70047468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70057468e2c8SBruno Larsen (billionai) { 70067468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 70077468e2c8SBruno Larsen (billionai) } 70087468e2c8SBruno Larsen (billionai) 70097468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 70107468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70117468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 70127468e2c8SBruno Larsen (billionai) { 70137468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70147468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70157468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70167468e2c8SBruno Larsen (billionai) return -1; 70177468e2c8SBruno Larsen (billionai) } 70187468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 70197468e2c8SBruno Larsen (billionai) handler) < 0) { 70207468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70217468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70227468e2c8SBruno Larsen (billionai) return -1; 70237468e2c8SBruno Larsen (billionai) } 70247468e2c8SBruno Larsen (billionai) 70257468e2c8SBruno Larsen (billionai) return 0; 70267468e2c8SBruno Larsen (billionai) } 70277468e2c8SBruno Larsen (billionai) 70287468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 70297468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70307468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 70317468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70327468e2c8SBruno Larsen (billionai) { 70337468e2c8SBruno Larsen (billionai) opc_handler_t **table; 70347468e2c8SBruno Larsen (billionai) 70357468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70367468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70377468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70387468e2c8SBruno Larsen (billionai) return -1; 70397468e2c8SBruno Larsen (billionai) } 70407468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 70417468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 70427468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 70437468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70447468e2c8SBruno Larsen (billionai) return -1; 70457468e2c8SBruno Larsen (billionai) } 70467468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 70477468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 70487468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70497468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 70507468e2c8SBruno Larsen (billionai) return -1; 70517468e2c8SBruno Larsen (billionai) } 70527468e2c8SBruno Larsen (billionai) return 0; 70537468e2c8SBruno Larsen (billionai) } 70547468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 70557468e2c8SBruno Larsen (billionai) { 70567468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 70577468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 70587468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 70597468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70607468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 70617468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 70627468e2c8SBruno Larsen (billionai) return -1; 70637468e2c8SBruno Larsen (billionai) } 70647468e2c8SBruno Larsen (billionai) } else { 70657468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70667468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 70677468e2c8SBruno Larsen (billionai) return -1; 70687468e2c8SBruno Larsen (billionai) } 70697468e2c8SBruno Larsen (billionai) } 70707468e2c8SBruno Larsen (billionai) } else { 70717468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 70727468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 70737468e2c8SBruno Larsen (billionai) return -1; 70747468e2c8SBruno Larsen (billionai) } 70757468e2c8SBruno Larsen (billionai) } 70767468e2c8SBruno Larsen (billionai) } else { 70777468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 70787468e2c8SBruno Larsen (billionai) return -1; 70797468e2c8SBruno Larsen (billionai) } 70807468e2c8SBruno Larsen (billionai) } 70817468e2c8SBruno Larsen (billionai) 70827468e2c8SBruno Larsen (billionai) return 0; 70837468e2c8SBruno Larsen (billionai) } 70847468e2c8SBruno Larsen (billionai) 70857468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 70867468e2c8SBruno Larsen (billionai) { 70877468e2c8SBruno Larsen (billionai) int i, count, tmp; 70887468e2c8SBruno Larsen (billionai) 70897468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 70907468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 70917468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 70927468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 70937468e2c8SBruno Larsen (billionai) } 70947468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 70957468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 70967468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 70977468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 70987468e2c8SBruno Larsen (billionai) if (tmp == 0) { 70997468e2c8SBruno Larsen (billionai) free(table[i]); 71007468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71017468e2c8SBruno Larsen (billionai) } else { 71027468e2c8SBruno Larsen (billionai) count++; 71037468e2c8SBruno Larsen (billionai) } 71047468e2c8SBruno Larsen (billionai) } else { 71057468e2c8SBruno Larsen (billionai) count++; 71067468e2c8SBruno Larsen (billionai) } 71077468e2c8SBruno Larsen (billionai) } 71087468e2c8SBruno Larsen (billionai) } 71097468e2c8SBruno Larsen (billionai) 71107468e2c8SBruno Larsen (billionai) return count; 71117468e2c8SBruno Larsen (billionai) } 71127468e2c8SBruno Larsen (billionai) 71137468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 71147468e2c8SBruno Larsen (billionai) { 71157468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 71167468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 71177468e2c8SBruno Larsen (billionai) } 71187468e2c8SBruno Larsen (billionai) } 71197468e2c8SBruno Larsen (billionai) 71207468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71217468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 71227468e2c8SBruno Larsen (billionai) { 71237468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 71247468e2c8SBruno Larsen (billionai) opcode_t *opc; 71257468e2c8SBruno Larsen (billionai) 71267468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 71277468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 71287468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 71297468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 71307468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 71317468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 71327468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 71337468e2c8SBruno Larsen (billionai) opc->opc3); 71347468e2c8SBruno Larsen (billionai) return; 71357468e2c8SBruno Larsen (billionai) } 71367468e2c8SBruno Larsen (billionai) } 71377468e2c8SBruno Larsen (billionai) } 71387468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 71397468e2c8SBruno Larsen (billionai) fflush(stdout); 71407468e2c8SBruno Larsen (billionai) fflush(stderr); 71417468e2c8SBruno Larsen (billionai) } 71427468e2c8SBruno Larsen (billionai) 71437468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 71447468e2c8SBruno Larsen (billionai) { 71457468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 71467468e2c8SBruno Larsen (billionai) int i, j, k; 71477468e2c8SBruno Larsen (billionai) 71487468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 71497468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 71507468e2c8SBruno Larsen (billionai) continue; 71517468e2c8SBruno Larsen (billionai) } 71527468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 71537468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 71547468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 71557468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 71567468e2c8SBruno Larsen (billionai) continue; 71577468e2c8SBruno Larsen (billionai) } 71587468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 71597468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 71607468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 71617468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 71627468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 71637468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 71647468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71657468e2c8SBruno Larsen (billionai) } 71667468e2c8SBruno Larsen (billionai) } 71677468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 71687468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71697468e2c8SBruno Larsen (billionai) } 71707468e2c8SBruno Larsen (billionai) } 71717468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 71727468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71737468e2c8SBruno Larsen (billionai) } 71747468e2c8SBruno Larsen (billionai) } 71757468e2c8SBruno Larsen (billionai) } 71767468e2c8SBruno Larsen (billionai) 71777468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 71787468e2c8SBruno Larsen (billionai) { 71797468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 71807468e2c8SBruno Larsen (billionai) 71817468e2c8SBruno Larsen (billionai) /* 71827468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 71837468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 71847468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 71857468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 71867468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 71877468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 71887468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 71897468e2c8SBruno Larsen (billionai) */ 71907468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 71917468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 71927468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 71937468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 71947468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 71957468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 71967468e2c8SBruno Larsen (billionai) } 71977468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 71987468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 71997468e2c8SBruno Larsen (billionai) return 0; 72007468e2c8SBruno Larsen (billionai) } 72017468e2c8SBruno Larsen (billionai) 7202624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7203624cb07fSRichard Henderson { 7204624cb07fSRichard Henderson opc_handler_t **table, *handler; 7205624cb07fSRichard Henderson uint32_t inval; 7206624cb07fSRichard Henderson 7207624cb07fSRichard Henderson ctx->opcode = insn; 7208624cb07fSRichard Henderson 7209624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7210624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7211624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7212624cb07fSRichard Henderson 7213624cb07fSRichard Henderson table = cpu->opcodes; 7214624cb07fSRichard Henderson handler = table[opc1(insn)]; 7215624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7216624cb07fSRichard Henderson table = ind_table(handler); 7217624cb07fSRichard Henderson handler = table[opc2(insn)]; 7218624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7219624cb07fSRichard Henderson table = ind_table(handler); 7220624cb07fSRichard Henderson handler = table[opc3(insn)]; 7221624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7222624cb07fSRichard Henderson table = ind_table(handler); 7223624cb07fSRichard Henderson handler = table[opc4(insn)]; 7224624cb07fSRichard Henderson } 7225624cb07fSRichard Henderson } 7226624cb07fSRichard Henderson } 7227624cb07fSRichard Henderson 7228624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7229624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7230624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7231624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7232624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7233624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7234624cb07fSRichard Henderson insn, ctx->cia); 7235624cb07fSRichard Henderson return false; 7236624cb07fSRichard Henderson } 7237624cb07fSRichard Henderson 7238624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7239624cb07fSRichard Henderson && Rc(insn))) { 7240624cb07fSRichard Henderson inval = handler->inval2; 7241624cb07fSRichard Henderson } else { 7242624cb07fSRichard Henderson inval = handler->inval1; 7243624cb07fSRichard Henderson } 7244624cb07fSRichard Henderson 7245624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7246624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7247624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7248624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7249624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7250624cb07fSRichard Henderson insn, ctx->cia); 7251624cb07fSRichard Henderson return false; 7252624cb07fSRichard Henderson } 7253624cb07fSRichard Henderson 7254624cb07fSRichard Henderson handler->handler(ctx); 7255624cb07fSRichard Henderson return true; 7256624cb07fSRichard Henderson } 7257624cb07fSRichard Henderson 7258b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7259fcf5ef2aSThomas Huth { 7260b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 72619c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 72622df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7263fcf5ef2aSThomas Huth 7264b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 72652df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7266d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 72672df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 72682df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7269b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7270b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7271b0c2d521SEmilio G. Cota ctx->access_type = -1; 7272d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 72732df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7274b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 72750e3bf489SRoman Kapl ctx->flags = env->flags; 7276fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72772df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7278b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7279fcf5ef2aSThomas Huth #endif 7280e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7281d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7282fcf5ef2aSThomas Huth 72832df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 72842df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 72852df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 72862df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 72872df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7288f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 72891db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7290f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7291f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 72928b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 72938b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 729446d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 72952df4fe7aSRichard Henderson 7296b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 72972df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 72982df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 72999498d103SRichard Henderson ctx->base.max_insns = 1; 7300efe843d8SDavid Gibson } 73012df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7302b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7303efe843d8SDavid Gibson } 730413b45575SRichard Henderson } 7305fcf5ef2aSThomas Huth 7306b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7307b0c2d521SEmilio G. Cota { 7308b0c2d521SEmilio G. Cota } 7309fcf5ef2aSThomas Huth 7310b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7311b0c2d521SEmilio G. Cota { 7312b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7313b0c2d521SEmilio G. Cota } 7314b0c2d521SEmilio G. Cota 731599082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 731699082815SRichard Henderson { 731799082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 731899082815SRichard Henderson return opc1(insn) == 1; 731999082815SRichard Henderson } 732099082815SRichard Henderson 7321b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7322b0c2d521SEmilio G. Cota { 7323b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 732428876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7325b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 732699082815SRichard Henderson target_ulong pc; 7327624cb07fSRichard Henderson uint32_t insn; 7328624cb07fSRichard Henderson bool ok; 7329b0c2d521SEmilio G. Cota 7330fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7331fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7332b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7333b0c2d521SEmilio G. Cota 733499082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 73354e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 733699082815SRichard Henderson ctx->base.pc_next = pc += 4; 7337fcf5ef2aSThomas Huth 733899082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 733999082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 734099082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 734199082815SRichard Henderson } else if ((pc & 63) == 0) { 734299082815SRichard Henderson /* 734399082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 734499082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 734599082815SRichard Henderson * 64-byte address boundary (system alignment error). 734699082815SRichard Henderson */ 734799082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 734899082815SRichard Henderson ok = true; 734999082815SRichard Henderson } else { 73504e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 73514e116893SIlya Leoshkevich need_byteswap(ctx)); 735299082815SRichard Henderson ctx->base.pc_next = pc += 4; 735399082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 735499082815SRichard Henderson } 7355624cb07fSRichard Henderson if (!ok) { 7356624cb07fSRichard Henderson gen_invalid(ctx); 7357fcf5ef2aSThomas Huth } 7358624cb07fSRichard Henderson 735964a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 736099082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 736164a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 736264a0f644SRichard Henderson } 7363fcf5ef2aSThomas Huth } 7364b0c2d521SEmilio G. Cota 7365b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7366b0c2d521SEmilio G. Cota { 7367b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7368a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7369a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7370b0c2d521SEmilio G. Cota 7371a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7372a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 73733d8a5b69SRichard Henderson return; 73743d8a5b69SRichard Henderson } 73753d8a5b69SRichard Henderson 7376a9b5b3d0SRichard Henderson /* Honor single stepping. */ 73779498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 73789498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7379a9b5b3d0SRichard Henderson switch (is_jmp) { 7380a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7381a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7382a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7383a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7384a9b5b3d0SRichard Henderson break; 7385a9b5b3d0SRichard Henderson case DISAS_EXIT: 7386a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7387a9b5b3d0SRichard Henderson break; 7388a9b5b3d0SRichard Henderson default: 7389a9b5b3d0SRichard Henderson g_assert_not_reached(); 7390fcf5ef2aSThomas Huth } 739113b45575SRichard Henderson 7392a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7393a9b5b3d0SRichard Henderson return; 7394a9b5b3d0SRichard Henderson } 7395a9b5b3d0SRichard Henderson 7396a9b5b3d0SRichard Henderson switch (is_jmp) { 7397a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7398a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 739946d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7400a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7401a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7402a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7403a9b5b3d0SRichard Henderson break; 7404a9b5b3d0SRichard Henderson } 7405a9b5b3d0SRichard Henderson /* fall through */ 7406a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7407a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7408a9b5b3d0SRichard Henderson /* fall through */ 7409a9b5b3d0SRichard Henderson case DISAS_CHAIN: 741046d396bdSDaniel Henrique Barboza /* 741146d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 741246d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 741346d396bdSDaniel Henrique Barboza */ 741446d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 741546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 741646d396bdSDaniel Henrique Barboza } 741746d396bdSDaniel Henrique Barboza 7418a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7419a9b5b3d0SRichard Henderson break; 7420a9b5b3d0SRichard Henderson 7421a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7422a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7423a9b5b3d0SRichard Henderson /* fall through */ 7424a9b5b3d0SRichard Henderson case DISAS_EXIT: 742546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 742607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7427a9b5b3d0SRichard Henderson break; 7428a9b5b3d0SRichard Henderson 7429a9b5b3d0SRichard Henderson default: 7430a9b5b3d0SRichard Henderson g_assert_not_reached(); 7431fcf5ef2aSThomas Huth } 7432fcf5ef2aSThomas Huth } 7433b0c2d521SEmilio G. Cota 74348eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 74358eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7436b0c2d521SEmilio G. Cota { 74378eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 74388eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7439b0c2d521SEmilio G. Cota } 7440b0c2d521SEmilio G. Cota 7441b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7442b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7443b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7444b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7445b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7446b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7447b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7448b0c2d521SEmilio G. Cota }; 7449b0c2d521SEmilio G. Cota 7450597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7451306c8721SRichard Henderson target_ulong pc, void *host_pc) 7452b0c2d521SEmilio G. Cota { 7453b0c2d521SEmilio G. Cota DisasContext ctx; 7454b0c2d521SEmilio G. Cota 7455306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7456fcf5ef2aSThomas Huth } 7457