1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33b6bac4bcSEmilio G. Cota #include "exec/translator.h" 34fcf5ef2aSThomas Huth #include "exec/log.h" 35f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3699e964efSFabiano Rosas #include "spr_common.h" 37eeaaefe9SLeandro Lupori #include "power8-pmu.h" 38fcf5ef2aSThomas Huth 393e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 403e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 41fcf5ef2aSThomas Huth 42d53106c9SRichard Henderson #define HELPER_H "helper.h" 43d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 44d53106c9SRichard Henderson #undef HELPER_H 45d53106c9SRichard Henderson 46fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 47fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 50efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76392d328aSNicholas Piggin static TCGv cpu_reserve_length; 77253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 78*cdab53ddSNicholas Piggin #if defined(TARGET_PPC64) 79894448aeSRichard Henderson static TCGv cpu_reserve_val2; 80*cdab53ddSNicholas Piggin #endif 81fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 82fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 83fcf5ef2aSThomas Huth 84fcf5ef2aSThomas Huth void ppc_translate_init(void) 85fcf5ef2aSThomas Huth { 86fcf5ef2aSThomas Huth int i; 87fcf5ef2aSThomas Huth char *p; 88fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth p = cpu_reg_names; 91fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 92fcf5ef2aSThomas Huth 93fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 94fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 95fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 97fcf5ef2aSThomas Huth p += 5; 98fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 99fcf5ef2aSThomas Huth } 100fcf5ef2aSThomas Huth 101fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 103fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 107fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 108fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 110fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 111fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 112fcf5ef2aSThomas Huth } 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 124fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 127fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 128fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 129fcf5ef2aSThomas Huth #endif 130fcf5ef2aSThomas Huth 131fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 133fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 135fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 137fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 138fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 139dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 141dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 142dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 145fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 146fcf5ef2aSThomas Huth "reserve_addr"); 147392d328aSNicholas Piggin cpu_reserve_length = tcg_global_mem_new(cpu_env, 148392d328aSNicholas Piggin offsetof(CPUPPCState, 149392d328aSNicholas Piggin reserve_length), 150392d328aSNicholas Piggin "reserve_length"); 151253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 152253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 153253ce7b2SNikunj A Dadhania "reserve_val"); 154*cdab53ddSNicholas Piggin #if defined(TARGET_PPC64) 155894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 156894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 157894448aeSRichard Henderson "reserve_val2"); 158*cdab53ddSNicholas Piggin #endif 159fcf5ef2aSThomas Huth 160fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 161fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 162fcf5ef2aSThomas Huth 163fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 164efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 165efe843d8SDavid Gibson "access_type"); 166fcf5ef2aSThomas Huth } 167fcf5ef2aSThomas Huth 168fcf5ef2aSThomas Huth /* internal defines */ 169fcf5ef2aSThomas Huth struct DisasContext { 170b6bac4bcSEmilio G. Cota DisasContextBase base; 1712c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 172fcf5ef2aSThomas Huth uint32_t opcode; 173fcf5ef2aSThomas Huth /* Routine used to access memory */ 174fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 175fcf5ef2aSThomas Huth bool lazy_tlb_flush; 176fcf5ef2aSThomas Huth bool need_access_type; 177fcf5ef2aSThomas Huth int mem_idx; 178fcf5ef2aSThomas Huth int access_type; 179fcf5ef2aSThomas Huth /* Translation flags */ 18014776ab5STony Nguyen MemOp default_tcg_memop_mask; 181fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 182fcf5ef2aSThomas Huth bool sf_mode; 183fcf5ef2aSThomas Huth bool has_cfar; 184fcf5ef2aSThomas Huth #endif 185fcf5ef2aSThomas Huth bool fpu_enabled; 186fcf5ef2aSThomas Huth bool altivec_enabled; 187fcf5ef2aSThomas Huth bool vsx_enabled; 188fcf5ef2aSThomas Huth bool spe_enabled; 189fcf5ef2aSThomas Huth bool tm_enabled; 190c6fd28fdSSuraj Jitindar Singh bool gtse; 1911db3632aSMatheus Ferst bool hr; 192f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 193f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1948b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1958b3d1c49SLeandro Lupori bool pmc_other; 19646d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 197fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 198fcf5ef2aSThomas Huth int singlestep_enabled; 1990e3bf489SRoman Kapl uint32_t flags; 200fcf5ef2aSThomas Huth uint64_t insns_flags; 201fcf5ef2aSThomas Huth uint64_t insns_flags2; 202fcf5ef2aSThomas Huth }; 203fcf5ef2aSThomas Huth 204a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 205a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 206a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 207a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 208a9b5b3d0SRichard Henderson 209fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 210fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 211fcf5ef2aSThomas Huth { 212ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 213fcf5ef2aSThomas Huth return ctx->le_mode; 214fcf5ef2aSThomas Huth #else 215fcf5ef2aSThomas Huth return !ctx->le_mode; 216fcf5ef2aSThomas Huth #endif 217fcf5ef2aSThomas Huth } 218fcf5ef2aSThomas Huth 219fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 220fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 221fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 222fcf5ef2aSThomas Huth #else 223fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 224fcf5ef2aSThomas Huth #endif 225fcf5ef2aSThomas Huth 226fcf5ef2aSThomas Huth struct opc_handler_t { 227fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 228fcf5ef2aSThomas Huth uint32_t inval1; 229fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 230fcf5ef2aSThomas Huth uint32_t inval2; 231fcf5ef2aSThomas Huth /* instruction type */ 232fcf5ef2aSThomas Huth uint64_t type; 233fcf5ef2aSThomas Huth /* extended instruction type */ 234fcf5ef2aSThomas Huth uint64_t type2; 235fcf5ef2aSThomas Huth /* handler */ 236fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 237fcf5ef2aSThomas Huth }; 238fcf5ef2aSThomas Huth 239b769d4c8SNicholas Piggin static inline bool gen_serialize(DisasContext *ctx) 240b769d4c8SNicholas Piggin { 241b769d4c8SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 242b769d4c8SNicholas Piggin /* Restart with exclusive lock. */ 243b769d4c8SNicholas Piggin gen_helper_exit_atomic(cpu_env); 244b769d4c8SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 245b769d4c8SNicholas Piggin return false; 246b769d4c8SNicholas Piggin } 247b769d4c8SNicholas Piggin return true; 248b769d4c8SNicholas Piggin } 249b769d4c8SNicholas Piggin 250b769d4c8SNicholas Piggin #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2513401ea3cSNicholas Piggin static inline bool gen_serialize_core_lpar(DisasContext *ctx) 252b769d4c8SNicholas Piggin { 2533401ea3cSNicholas Piggin if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 254b769d4c8SNicholas Piggin return gen_serialize(ctx); 255b769d4c8SNicholas Piggin } 256b769d4c8SNicholas Piggin 257b769d4c8SNicholas Piggin return true; 258b769d4c8SNicholas Piggin } 259b769d4c8SNicholas Piggin #endif 260b769d4c8SNicholas Piggin 2610e3bf489SRoman Kapl /* SPR load/store helpers */ 2620e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2630e3bf489SRoman Kapl { 2640e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2650e3bf489SRoman Kapl } 2660e3bf489SRoman Kapl 2670e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2680e3bf489SRoman Kapl { 2690e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2700e3bf489SRoman Kapl } 2710e3bf489SRoman Kapl 272fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 273fcf5ef2aSThomas Huth { 274fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 275fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 276fcf5ef2aSThomas Huth ctx->access_type = access_type; 277fcf5ef2aSThomas Huth } 278fcf5ef2aSThomas Huth } 279fcf5ef2aSThomas Huth 280fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 281fcf5ef2aSThomas Huth { 282fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 283fcf5ef2aSThomas Huth nip = (uint32_t)nip; 284fcf5ef2aSThomas Huth } 285fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 286fcf5ef2aSThomas Huth } 287fcf5ef2aSThomas Huth 288fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 289fcf5ef2aSThomas Huth { 290fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 291fcf5ef2aSThomas Huth 292efe843d8SDavid Gibson /* 293efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 294efe843d8SDavid Gibson * faulting instruction 295fcf5ef2aSThomas Huth */ 2962c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2977058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 2987058ff52SRichard Henderson t1 = tcg_constant_i32(error); 299fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 3003d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 301fcf5ef2aSThomas Huth } 302fcf5ef2aSThomas Huth 303fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 304fcf5ef2aSThomas Huth { 305fcf5ef2aSThomas Huth TCGv_i32 t0; 306fcf5ef2aSThomas Huth 307efe843d8SDavid Gibson /* 308efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 309efe843d8SDavid Gibson * faulting instruction 310fcf5ef2aSThomas Huth */ 3112c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 3127058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 313fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3143d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 315fcf5ef2aSThomas Huth } 316fcf5ef2aSThomas Huth 317fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 318fcf5ef2aSThomas Huth target_ulong nip) 319fcf5ef2aSThomas Huth { 320fcf5ef2aSThomas Huth TCGv_i32 t0; 321fcf5ef2aSThomas Huth 322fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 3237058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 324fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3253d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 326fcf5ef2aSThomas Huth } 327fcf5ef2aSThomas Huth 3282fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3292fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3302fdedcbcSMatheus Ferst { 331283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 3322fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3332fdedcbcSMatheus Ferst } 3342fdedcbcSMatheus Ferst #endif 3352fdedcbcSMatheus Ferst 336e150ac89SRoman Kapl /* 337e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 338e150ac89SRoman Kapl * SPR registers for this exception. 339e150ac89SRoman Kapl * 340e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 341e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3420e3bf489SRoman Kapl */ 343a11e3a15SNicholas Piggin static void gen_debug_exception(DisasContext *ctx, bool rfi_type) 3440e3bf489SRoman Kapl { 34514895384SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 3460e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3470e3bf489SRoman Kapl target_ulong dbsr = 0; 348e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3490e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 350e150ac89SRoman Kapl } else { 351e150ac89SRoman Kapl /* Must have been branch */ 3520e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3530e3bf489SRoman Kapl } 3540e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3550e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3560e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3570e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 35814895384SNicholas Piggin gen_helper_raise_exception(cpu_env, 35914895384SNicholas Piggin tcg_constant_i32(POWERPC_EXCP_DEBUG)); 3603d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 36114895384SNicholas Piggin } else { 362a11e3a15SNicholas Piggin if (!rfi_type) { /* BookS does not single step rfi type instructions */ 36314895384SNicholas Piggin TCGv t0 = tcg_temp_new(); 36414895384SNicholas Piggin tcg_gen_movi_tl(t0, ctx->cia); 36514895384SNicholas Piggin gen_helper_book3s_trace(cpu_env, t0); 36614895384SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 36714895384SNicholas Piggin } 368a11e3a15SNicholas Piggin } 36914895384SNicholas Piggin #endif 370fcf5ef2aSThomas Huth } 371fcf5ef2aSThomas Huth 372fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 373fcf5ef2aSThomas Huth { 374fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 375fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 376fcf5ef2aSThomas Huth } 377fcf5ef2aSThomas Huth 378fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 379fcf5ef2aSThomas Huth { 380fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 381fcf5ef2aSThomas Huth } 382fcf5ef2aSThomas Huth 383fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 384fcf5ef2aSThomas Huth { 385fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 386fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 387fcf5ef2aSThomas Huth } 388fcf5ef2aSThomas Huth 38937f219c8SBruno Larsen (billionai) /*****************************************************************************/ 39037f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 39137f219c8SBruno Larsen (billionai) 392a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 39337f219c8SBruno Larsen (billionai) { 39437f219c8SBruno Larsen (billionai) #if 0 39537f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 39637f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 39737f219c8SBruno Larsen (billionai) #endif 39837f219c8SBruno Larsen (billionai) } 39937f219c8SBruno Larsen (billionai) 40037f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 40137f219c8SBruno Larsen (billionai) 40237f219c8SBruno Larsen (billionai) /* 40337f219c8SBruno Larsen (billionai) * Generic callbacks: 40437f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 40537f219c8SBruno Larsen (billionai) */ 40637f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 40737f219c8SBruno Larsen (billionai) { 40837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4097058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 41037f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 41137f219c8SBruno Larsen (billionai) #endif 41237f219c8SBruno Larsen (billionai) } 41337f219c8SBruno Larsen (billionai) 414a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 41537f219c8SBruno Larsen (billionai) { 41637f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 41737f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 41837f219c8SBruno Larsen (billionai) } 41937f219c8SBruno Larsen (billionai) 42037f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 42137f219c8SBruno Larsen (billionai) { 42237f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4237058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 42437f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 42537f219c8SBruno Larsen (billionai) #endif 42637f219c8SBruno Larsen (billionai) } 42737f219c8SBruno Larsen (billionai) 428a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 42937f219c8SBruno Larsen (billionai) { 43037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 43137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43237f219c8SBruno Larsen (billionai) } 43337f219c8SBruno Larsen (billionai) 434a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43537f219c8SBruno Larsen (billionai) { 43637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43837f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44037f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 44137f219c8SBruno Larsen (billionai) #else 44237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 44337f219c8SBruno Larsen (billionai) #endif 44437f219c8SBruno Larsen (billionai) } 44537f219c8SBruno Larsen (billionai) 4469cdfd1b9SNicholas Piggin void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 4479cdfd1b9SNicholas Piggin { 4489cdfd1b9SNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT)) { 4499cdfd1b9SNicholas Piggin spr_write_generic(ctx, sprn, gprn); 4509cdfd1b9SNicholas Piggin return; 4519cdfd1b9SNicholas Piggin } 4529cdfd1b9SNicholas Piggin 4539cdfd1b9SNicholas Piggin if (!gen_serialize(ctx)) { 4549cdfd1b9SNicholas Piggin return; 4559cdfd1b9SNicholas Piggin } 4569cdfd1b9SNicholas Piggin 4579cdfd1b9SNicholas Piggin gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn), 4589cdfd1b9SNicholas Piggin cpu_gpr[gprn]); 4599cdfd1b9SNicholas Piggin spr_store_dump_spr(sprn); 4609cdfd1b9SNicholas Piggin } 4619cdfd1b9SNicholas Piggin 462c5d98a7bSNicholas Piggin static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 463fbda88f7SNicholas Piggin { 464488aad11SNicholas Piggin /* This does not implement >1 thread */ 465488aad11SNicholas Piggin TCGv t0 = tcg_temp_new(); 466488aad11SNicholas Piggin TCGv t1 = tcg_temp_new(); 467488aad11SNicholas Piggin tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 468488aad11SNicholas Piggin tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 469488aad11SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 470488aad11SNicholas Piggin gen_store_spr(sprn, t1); 471c5d98a7bSNicholas Piggin } 472c5d98a7bSNicholas Piggin 473c5d98a7bSNicholas Piggin void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 474c5d98a7bSNicholas Piggin { 4753401ea3cSNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 4763401ea3cSNicholas Piggin /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 477c5d98a7bSNicholas Piggin spr_write_CTRL_ST(ctx, sprn, gprn); 478c5d98a7bSNicholas Piggin goto out; 479c5d98a7bSNicholas Piggin } 480c5d98a7bSNicholas Piggin 481c5d98a7bSNicholas Piggin if (!gen_serialize(ctx)) { 482c5d98a7bSNicholas Piggin return; 483c5d98a7bSNicholas Piggin } 484c5d98a7bSNicholas Piggin 485c5d98a7bSNicholas Piggin gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 486c5d98a7bSNicholas Piggin cpu_gpr[gprn]); 487c5d98a7bSNicholas Piggin out: 488488aad11SNicholas Piggin spr_store_dump_spr(sprn); 489fbda88f7SNicholas Piggin 490fbda88f7SNicholas Piggin /* 491fbda88f7SNicholas Piggin * SPR_CTRL writes must force a new translation block, 492fbda88f7SNicholas Piggin * allowing the PMU to calculate the run latch events with 493fbda88f7SNicholas Piggin * more accuracy. 494fbda88f7SNicholas Piggin */ 495fbda88f7SNicholas Piggin ctx->base.is_jmp = DISAS_EXIT_UPDATE; 496fbda88f7SNicholas Piggin } 497fbda88f7SNicholas Piggin 498fbda88f7SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 499a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 50037f219c8SBruno Larsen (billionai) { 50137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 50237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 50337f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 50437f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 50537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 50637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 50737f219c8SBruno Larsen (billionai) } 50837f219c8SBruno Larsen (billionai) 509a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 51037f219c8SBruno Larsen (billionai) { 51137f219c8SBruno Larsen (billionai) } 51237f219c8SBruno Larsen (billionai) 51337f219c8SBruno Larsen (billionai) #endif 51437f219c8SBruno Larsen (billionai) 51537f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 51637f219c8SBruno Larsen (billionai) /* XER */ 517a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 51837f219c8SBruno Larsen (billionai) { 51937f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 52037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 52137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 52237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 52337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 52437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 52537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 52637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 52737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 52837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 52937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 53037f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 53137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 53237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 53337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 53437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 53537f219c8SBruno Larsen (billionai) } 53637f219c8SBruno Larsen (billionai) } 53737f219c8SBruno Larsen (billionai) 538a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 53937f219c8SBruno Larsen (billionai) { 54037f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 54137f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 54237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 54337f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 54437f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 54537f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 54637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 54737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 54837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 54937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 55037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 55137f219c8SBruno Larsen (billionai) } 55237f219c8SBruno Larsen (billionai) 55337f219c8SBruno Larsen (billionai) /* LR */ 554a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 55537f219c8SBruno Larsen (billionai) { 55637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 55737f219c8SBruno Larsen (billionai) } 55837f219c8SBruno Larsen (billionai) 559a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 56037f219c8SBruno Larsen (billionai) { 56137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 56237f219c8SBruno Larsen (billionai) } 56337f219c8SBruno Larsen (billionai) 56437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 56514192307SNicholas Piggin /* Debug facilities */ 56614192307SNicholas Piggin /* CFAR */ 567a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 56837f219c8SBruno Larsen (billionai) { 56937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 57037f219c8SBruno Larsen (billionai) } 57137f219c8SBruno Larsen (billionai) 572a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 57337f219c8SBruno Larsen (billionai) { 57437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 57537f219c8SBruno Larsen (billionai) } 57614192307SNicholas Piggin 57714192307SNicholas Piggin /* Breakpoint */ 57814192307SNicholas Piggin void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) 57914192307SNicholas Piggin { 58014192307SNicholas Piggin translator_io_start(&ctx->base); 58114192307SNicholas Piggin gen_helper_store_ciabr(cpu_env, cpu_gpr[gprn]); 58214192307SNicholas Piggin } 583d5ee641cSNicholas Piggin 584d5ee641cSNicholas Piggin /* Watchpoint */ 585d5ee641cSNicholas Piggin void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) 586d5ee641cSNicholas Piggin { 587d5ee641cSNicholas Piggin translator_io_start(&ctx->base); 588d5ee641cSNicholas Piggin gen_helper_store_dawr0(cpu_env, cpu_gpr[gprn]); 589d5ee641cSNicholas Piggin } 590d5ee641cSNicholas Piggin 591d5ee641cSNicholas Piggin void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) 592d5ee641cSNicholas Piggin { 593d5ee641cSNicholas Piggin translator_io_start(&ctx->base); 594d5ee641cSNicholas Piggin gen_helper_store_dawrx0(cpu_env, cpu_gpr[gprn]); 595d5ee641cSNicholas Piggin } 59637f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 59737f219c8SBruno Larsen (billionai) 59837f219c8SBruno Larsen (billionai) /* CTR */ 599a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 60037f219c8SBruno Larsen (billionai) { 60137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 60237f219c8SBruno Larsen (billionai) } 60337f219c8SBruno Larsen (billionai) 604a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 60537f219c8SBruno Larsen (billionai) { 60637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 60737f219c8SBruno Larsen (billionai) } 60837f219c8SBruno Larsen (billionai) 60937f219c8SBruno Larsen (billionai) /* User read access to SPR */ 61037f219c8SBruno Larsen (billionai) /* USPRx */ 61137f219c8SBruno Larsen (billionai) /* UMMCRx */ 61237f219c8SBruno Larsen (billionai) /* UPMCx */ 61337f219c8SBruno Larsen (billionai) /* USIA */ 61437f219c8SBruno Larsen (billionai) /* UDECR */ 615a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 61637f219c8SBruno Larsen (billionai) { 61737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 61837f219c8SBruno Larsen (billionai) } 61937f219c8SBruno Larsen (billionai) 62037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 621a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 62237f219c8SBruno Larsen (billionai) { 62337f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 62437f219c8SBruno Larsen (billionai) } 62537f219c8SBruno Larsen (billionai) #endif 62637f219c8SBruno Larsen (billionai) 62737f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 62837f219c8SBruno Larsen (billionai) /* DECR */ 62937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 630a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 63137f219c8SBruno Larsen (billionai) { 632283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 63337f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 63437f219c8SBruno Larsen (billionai) } 63537f219c8SBruno Larsen (billionai) 636a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 63737f219c8SBruno Larsen (billionai) { 638283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 63937f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 64037f219c8SBruno Larsen (billionai) } 64137f219c8SBruno Larsen (billionai) #endif 64237f219c8SBruno Larsen (billionai) 64337f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 64437f219c8SBruno Larsen (billionai) /* Time base */ 645a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 64637f219c8SBruno Larsen (billionai) { 647283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 64837f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 64937f219c8SBruno Larsen (billionai) } 65037f219c8SBruno Larsen (billionai) 651a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 65237f219c8SBruno Larsen (billionai) { 653283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65437f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) 657a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 66037f219c8SBruno Larsen (billionai) } 66137f219c8SBruno Larsen (billionai) 662a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 66337f219c8SBruno Larsen (billionai) { 66437f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 66537f219c8SBruno Larsen (billionai) } 66637f219c8SBruno Larsen (billionai) 66737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 668a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 66937f219c8SBruno Larsen (billionai) { 670283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67137f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 67237f219c8SBruno Larsen (billionai) } 67337f219c8SBruno Larsen (billionai) 674a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 67537f219c8SBruno Larsen (billionai) { 676283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67737f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 67837f219c8SBruno Larsen (billionai) } 67937f219c8SBruno Larsen (billionai) 680a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 68137f219c8SBruno Larsen (billionai) { 68237f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 685a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 68637f219c8SBruno Larsen (billionai) { 68737f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 68837f219c8SBruno Larsen (billionai) } 68937f219c8SBruno Larsen (billionai) 69037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 691a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 69237f219c8SBruno Larsen (billionai) { 693283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 69437f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 69537f219c8SBruno Larsen (billionai) } 69637f219c8SBruno Larsen (billionai) 697a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 69837f219c8SBruno Larsen (billionai) { 699283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 70037f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 70137f219c8SBruno Larsen (billionai) } 70237f219c8SBruno Larsen (billionai) 70337f219c8SBruno Larsen (billionai) /* HDECR */ 704a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 70537f219c8SBruno Larsen (billionai) { 706283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 70737f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 70837f219c8SBruno Larsen (billionai) } 70937f219c8SBruno Larsen (billionai) 710a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 71137f219c8SBruno Larsen (billionai) { 712283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 71337f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 71437f219c8SBruno Larsen (billionai) } 71537f219c8SBruno Larsen (billionai) 716a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 71737f219c8SBruno Larsen (billionai) { 718283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 71937f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) 722a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 72337f219c8SBruno Larsen (billionai) { 724283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 72537f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) } 72737f219c8SBruno Larsen (billionai) 728a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 72937f219c8SBruno Larsen (billionai) { 730283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 73137f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 73237f219c8SBruno Larsen (billionai) } 73337f219c8SBruno Larsen (billionai) 73437f219c8SBruno Larsen (billionai) #endif 73537f219c8SBruno Larsen (billionai) #endif 73637f219c8SBruno Larsen (billionai) 73737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 73837f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 73937f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 740a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 74137f219c8SBruno Larsen (billionai) { 74237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 74537f219c8SBruno Larsen (billionai) } 74637f219c8SBruno Larsen (billionai) 747a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 74837f219c8SBruno Larsen (billionai) { 74937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 75037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 75137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 75237f219c8SBruno Larsen (billionai) } 75337f219c8SBruno Larsen (billionai) 754a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 75537f219c8SBruno Larsen (billionai) { 7567058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 75737f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 75837f219c8SBruno Larsen (billionai) } 75937f219c8SBruno Larsen (billionai) 760a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 76137f219c8SBruno Larsen (billionai) { 7627058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 76337f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 76437f219c8SBruno Larsen (billionai) } 76537f219c8SBruno Larsen (billionai) 766a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 76737f219c8SBruno Larsen (billionai) { 7687058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 76937f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 772a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 77337f219c8SBruno Larsen (billionai) { 7747058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 77537f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 77637f219c8SBruno Larsen (billionai) } 77737f219c8SBruno Larsen (billionai) 77837f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 77937f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 780a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 78137f219c8SBruno Larsen (billionai) { 78237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 78337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 78437f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 78537f219c8SBruno Larsen (billionai) } 78637f219c8SBruno Larsen (billionai) 787a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 78837f219c8SBruno Larsen (billionai) { 78937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 79037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 79137f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 79237f219c8SBruno Larsen (billionai) } 79337f219c8SBruno Larsen (billionai) 794a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 79537f219c8SBruno Larsen (billionai) { 7967058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 79737f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 79837f219c8SBruno Larsen (billionai) } 79937f219c8SBruno Larsen (billionai) 800a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 80137f219c8SBruno Larsen (billionai) { 8027058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 80337f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 80437f219c8SBruno Larsen (billionai) } 80537f219c8SBruno Larsen (billionai) 806a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 80737f219c8SBruno Larsen (billionai) { 8087058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 80937f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 81037f219c8SBruno Larsen (billionai) } 81137f219c8SBruno Larsen (billionai) 812a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 81337f219c8SBruno Larsen (billionai) { 8147058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 81537f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 81637f219c8SBruno Larsen (billionai) } 81737f219c8SBruno Larsen (billionai) 81837f219c8SBruno Larsen (billionai) /* SDR1 */ 819a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 82037f219c8SBruno Larsen (billionai) { 82137f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 82237f219c8SBruno Larsen (billionai) } 82337f219c8SBruno Larsen (billionai) 82437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 82537f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 82637f219c8SBruno Larsen (billionai) /* PIDR */ 827a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 82837f219c8SBruno Larsen (billionai) { 82937f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 83037f219c8SBruno Larsen (billionai) } 83137f219c8SBruno Larsen (billionai) 832a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 83337f219c8SBruno Larsen (billionai) { 83437f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) 837a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 83837f219c8SBruno Larsen (billionai) { 83937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 84037f219c8SBruno Larsen (billionai) } 84137f219c8SBruno Larsen (billionai) 842a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 84337f219c8SBruno Larsen (billionai) { 84437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 84537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 84637f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 84737f219c8SBruno Larsen (billionai) } 848a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 84937f219c8SBruno Larsen (billionai) { 85037f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 85137f219c8SBruno Larsen (billionai) } 85237f219c8SBruno Larsen (billionai) 853a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 85437f219c8SBruno Larsen (billionai) { 85537f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 85637f219c8SBruno Larsen (billionai) } 85737f219c8SBruno Larsen (billionai) 85837f219c8SBruno Larsen (billionai) /* DPDES */ 859a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 86037f219c8SBruno Larsen (billionai) { 8613401ea3cSNicholas Piggin if (!gen_serialize_core_lpar(ctx)) { 862d24e80b2SNicholas Piggin return; 863d24e80b2SNicholas Piggin } 864d24e80b2SNicholas Piggin 86537f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 86637f219c8SBruno Larsen (billionai) } 86737f219c8SBruno Larsen (billionai) 868a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 86937f219c8SBruno Larsen (billionai) { 8703401ea3cSNicholas Piggin if (!gen_serialize_core_lpar(ctx)) { 871d24e80b2SNicholas Piggin return; 872d24e80b2SNicholas Piggin } 873d24e80b2SNicholas Piggin 87437f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 87537f219c8SBruno Larsen (billionai) } 87637f219c8SBruno Larsen (billionai) #endif 87737f219c8SBruno Larsen (billionai) #endif 87837f219c8SBruno Larsen (billionai) 87937f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 88037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 881a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 88237f219c8SBruno Larsen (billionai) { 883283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 88437f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 88537f219c8SBruno Larsen (billionai) } 88637f219c8SBruno Larsen (billionai) 887a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 88837f219c8SBruno Larsen (billionai) { 889283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 89037f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 89137f219c8SBruno Larsen (billionai) } 89237f219c8SBruno Larsen (billionai) 893a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 89437f219c8SBruno Larsen (billionai) { 895283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 89637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 89737f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 89837f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 899d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 90037f219c8SBruno Larsen (billionai) } 90137f219c8SBruno Larsen (billionai) 902a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 90337f219c8SBruno Larsen (billionai) { 904283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 90537f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 90637f219c8SBruno Larsen (billionai) } 90737f219c8SBruno Larsen (billionai) 908cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 909cbd8f17dSCédric Le Goater { 910283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 911cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 912cbd8f17dSCédric Le Goater } 913cbd8f17dSCédric Le Goater 914cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 915cbd8f17dSCédric Le Goater { 916283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 917cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 918cbd8f17dSCédric Le Goater } 919cbd8f17dSCédric Le Goater 920dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 921dd69d140SCédric Le Goater { 922dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 923dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 92447822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 925dd69d140SCédric Le Goater } 926dd69d140SCédric Le Goater 927a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 92837f219c8SBruno Larsen (billionai) { 929283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 93037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 93137f219c8SBruno Larsen (billionai) } 93237f219c8SBruno Larsen (billionai) 933a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 93437f219c8SBruno Larsen (billionai) { 935283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 93637f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 93737f219c8SBruno Larsen (billionai) } 93837f219c8SBruno Larsen (billionai) #endif 93937f219c8SBruno Larsen (billionai) 940328c95fcSCédric Le Goater /* PIR */ 94137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 942a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 94337f219c8SBruno Larsen (billionai) { 94437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 94537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 94637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 94737f219c8SBruno Larsen (billionai) } 94837f219c8SBruno Larsen (billionai) #endif 94937f219c8SBruno Larsen (billionai) 95037f219c8SBruno Larsen (billionai) /* SPE specific registers */ 951a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 95237f219c8SBruno Larsen (billionai) { 95337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 95437f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 95537f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 95637f219c8SBruno Larsen (billionai) } 95737f219c8SBruno Larsen (billionai) 958a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 95937f219c8SBruno Larsen (billionai) { 96037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 96137f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 96237f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 96337f219c8SBruno Larsen (billionai) } 96437f219c8SBruno Larsen (billionai) 96537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 96637f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 967a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 96837f219c8SBruno Larsen (billionai) { 96937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 97137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 97237f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 97337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 97437f219c8SBruno Larsen (billionai) } 97537f219c8SBruno Larsen (billionai) 976a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 97737f219c8SBruno Larsen (billionai) { 97837f219c8SBruno Larsen (billionai) int sprn_offs; 97937f219c8SBruno Larsen (billionai) 98037f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 98137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 98237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 98337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 98437f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 98537f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 98637f219c8SBruno Larsen (billionai) } else { 9878e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9888e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9898e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 99037f219c8SBruno Larsen (billionai) return; 99137f219c8SBruno Larsen (billionai) } 99237f219c8SBruno Larsen (billionai) 99337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 99437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 99537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 99637f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 99737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 99837f219c8SBruno Larsen (billionai) } 99937f219c8SBruno Larsen (billionai) #endif 100037f219c8SBruno Larsen (billionai) 100137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 100237f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1003a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 100437f219c8SBruno Larsen (billionai) { 100537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100837f219c8SBruno Larsen (billionai) 100937f219c8SBruno Larsen (billionai) /* 101037f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 101137f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 101237f219c8SBruno Larsen (billionai) */ 101337f219c8SBruno Larsen (billionai) 101437f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 101537f219c8SBruno Larsen (billionai) if (ctx->pr) { 101637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 101737f219c8SBruno Larsen (billionai) } else { 101837f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101937f219c8SBruno Larsen (billionai) } 102037f219c8SBruno Larsen (billionai) 102137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 102237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 102337f219c8SBruno Larsen (billionai) 102437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 102537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 102637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 102737f219c8SBruno Larsen (billionai) 102837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 102937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 103037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 103137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 103237f219c8SBruno Larsen (billionai) } 103337f219c8SBruno Larsen (billionai) 1034a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 103537f219c8SBruno Larsen (billionai) { 103637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103937f219c8SBruno Larsen (billionai) 104037f219c8SBruno Larsen (billionai) /* 104137f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 104237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 104337f219c8SBruno Larsen (billionai) */ 104437f219c8SBruno Larsen (billionai) 104537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104737f219c8SBruno Larsen (billionai) 104837f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 105037f219c8SBruno Larsen (billionai) 105137f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 105237f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 105337f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 105437f219c8SBruno Larsen (billionai) 105537f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 105837f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 105937f219c8SBruno Larsen (billionai) } 106037f219c8SBruno Larsen (billionai) 1061a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 106237f219c8SBruno Larsen (billionai) { 106337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 106537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 106637f219c8SBruno Larsen (billionai) 106737f219c8SBruno Larsen (billionai) /* 106837f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 106937f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 107037f219c8SBruno Larsen (billionai) */ 107137f219c8SBruno Larsen (billionai) 107237f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 107337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 107437f219c8SBruno Larsen (billionai) 107537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 107637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 107737f219c8SBruno Larsen (billionai) 107837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 107937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 108037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 108137f219c8SBruno Larsen (billionai) 108237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 108337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 108437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 108537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 108637f219c8SBruno Larsen (billionai) } 108737f219c8SBruno Larsen (billionai) #endif 108837f219c8SBruno Larsen (billionai) #endif 108937f219c8SBruno Larsen (billionai) 109037f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1091a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 109237f219c8SBruno Larsen (billionai) { 109337f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 109437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 109537f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 109637f219c8SBruno Larsen (billionai) } 109737f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 109837f219c8SBruno Larsen (billionai) 109937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1100a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 110137f219c8SBruno Larsen (billionai) { 110237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 110337f219c8SBruno Larsen (billionai) 110437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 110537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 110637f219c8SBruno Larsen (billionai) } 110737f219c8SBruno Larsen (billionai) 1108a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 110937f219c8SBruno Larsen (billionai) { 111037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 111137f219c8SBruno Larsen (billionai) 111237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 111337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 111437f219c8SBruno Larsen (billionai) } 111537f219c8SBruno Larsen (billionai) 1116a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 111737f219c8SBruno Larsen (billionai) { 111837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 111937f219c8SBruno Larsen (billionai) 112037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 112137f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 112237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 112337f219c8SBruno Larsen (billionai) } 112437f219c8SBruno Larsen (billionai) 1125a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 112637f219c8SBruno Larsen (billionai) { 112737f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 112837f219c8SBruno Larsen (billionai) } 112937f219c8SBruno Larsen (billionai) 1130a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 113137f219c8SBruno Larsen (billionai) { 11327058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 113337f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 113437f219c8SBruno Larsen (billionai) } 11357058ff52SRichard Henderson 1136a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 113737f219c8SBruno Larsen (billionai) { 113837f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 113937f219c8SBruno Larsen (billionai) } 11407058ff52SRichard Henderson 1141a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 114237f219c8SBruno Larsen (billionai) { 114337f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 114437f219c8SBruno Larsen (billionai) } 114537f219c8SBruno Larsen (billionai) 114637f219c8SBruno Larsen (billionai) #endif 114737f219c8SBruno Larsen (billionai) 114837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1149a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 115037f219c8SBruno Larsen (billionai) { 115137f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 115237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 115337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 115437f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 115537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 115637f219c8SBruno Larsen (billionai) } 115737f219c8SBruno Larsen (billionai) 1158a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 115937f219c8SBruno Larsen (billionai) { 116037f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 116137f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 116237f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 116337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 116437f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 116537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 116637f219c8SBruno Larsen (billionai) } 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) #endif 116937f219c8SBruno Larsen (billionai) 117037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 117137f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 117237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 117337f219c8SBruno Larsen (billionai) { 11747058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11757058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11767058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 117737f219c8SBruno Larsen (billionai) 117837f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 117937f219c8SBruno Larsen (billionai) } 118037f219c8SBruno Larsen (billionai) 118137f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 118237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 118337f219c8SBruno Larsen (billionai) { 11847058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11857058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11867058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 118737f219c8SBruno Larsen (billionai) 118837f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 118937f219c8SBruno Larsen (billionai) } 119037f219c8SBruno Larsen (billionai) 1191a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 119237f219c8SBruno Larsen (billionai) { 119337f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 119437f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119537f219c8SBruno Larsen (billionai) 119637f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 119837f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 119937f219c8SBruno Larsen (billionai) } 120037f219c8SBruno Larsen (billionai) 1201a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 120237f219c8SBruno Larsen (billionai) { 120337f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 120437f219c8SBruno Larsen (billionai) 120537f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 120637f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 120737f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 120837f219c8SBruno Larsen (billionai) } 120937f219c8SBruno Larsen (billionai) 121037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1211a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 121237f219c8SBruno Larsen (billionai) { 121337f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 121437f219c8SBruno Larsen (billionai) 121537f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 121637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 121737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 121837f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 121937f219c8SBruno Larsen (billionai) } 122037f219c8SBruno Larsen (billionai) 1221b25f2ffaSNicholas Piggin void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1222b25f2ffaSNicholas Piggin { 1223b25f2ffaSNicholas Piggin gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1224b25f2ffaSNicholas Piggin } 1225b25f2ffaSNicholas Piggin 1226b25f2ffaSNicholas Piggin void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1227b25f2ffaSNicholas Piggin { 1228b25f2ffaSNicholas Piggin gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1229b25f2ffaSNicholas Piggin } 1230b25f2ffaSNicholas Piggin 1231a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 123237f219c8SBruno Larsen (billionai) { 1233c32654afSNicholas Piggin translator_io_start(&ctx->base); 123437f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 123537f219c8SBruno Larsen (billionai) } 123637f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 123737f219c8SBruno Larsen (billionai) 1238a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 123937f219c8SBruno Larsen (billionai) { 124037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 124137f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 124237f219c8SBruno Larsen (billionai) } 124337f219c8SBruno Larsen (billionai) 1244a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 124537f219c8SBruno Larsen (billionai) { 124637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 124737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124837f219c8SBruno Larsen (billionai) } 124937f219c8SBruno Larsen (billionai) 1250a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 125137f219c8SBruno Larsen (billionai) { 125237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125437f219c8SBruno Larsen (billionai) } 125537f219c8SBruno Larsen (billionai) 1256a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 125737f219c8SBruno Larsen (billionai) { 125837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126037f219c8SBruno Larsen (billionai) } 126137f219c8SBruno Larsen (billionai) 1262a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 126337f219c8SBruno Larsen (billionai) { 126437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 126537f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 126637f219c8SBruno Larsen (billionai) } 126737f219c8SBruno Larsen (billionai) 1268a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 126937f219c8SBruno Larsen (billionai) { 127037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 127137f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 127237f219c8SBruno Larsen (billionai) } 127337f219c8SBruno Larsen (billionai) 1274a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 127537f219c8SBruno Larsen (billionai) { 127637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 127837f219c8SBruno Larsen (billionai) } 127937f219c8SBruno Larsen (billionai) 1280a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 128137f219c8SBruno Larsen (billionai) { 128237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 128337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 128437f219c8SBruno Larsen (billionai) } 128537f219c8SBruno Larsen (billionai) 1286a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 128737f219c8SBruno Larsen (billionai) { 128837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 128937f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 129037f219c8SBruno Larsen (billionai) } 129137f219c8SBruno Larsen (billionai) 1292a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 129337f219c8SBruno Larsen (billionai) { 129437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 129537f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 129637f219c8SBruno Larsen (billionai) } 1297395b5d5bSNicholas Miehlbradt 1298395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1299395b5d5bSNicholas Miehlbradt { 1300395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1301395b5d5bSNicholas Miehlbradt 1302395b5d5bSNicholas Miehlbradt /* 1303395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1304395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1305395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1306395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1307395b5d5bSNicholas Miehlbradt * 1308395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1309395b5d5bSNicholas Miehlbradt */ 1310395b5d5bSNicholas Miehlbradt 1311395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1312395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1313395b5d5bSNicholas Miehlbradt } 131437f219c8SBruno Larsen (billionai) #endif 131537f219c8SBruno Larsen (billionai) 1316fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1317fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1318fcf5ef2aSThomas Huth 1319fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1320fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1321fcf5ef2aSThomas Huth 1322fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1323fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1324fcf5ef2aSThomas Huth 1325fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1326fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1327fcf5ef2aSThomas Huth 1328fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1329fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1330fcf5ef2aSThomas Huth 1331fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1332fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1333fcf5ef2aSThomas Huth 1334fcf5ef2aSThomas Huth typedef struct opcode_t { 1335fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1336fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1337fcf5ef2aSThomas Huth unsigned char pad[4]; 1338fcf5ef2aSThomas Huth #endif 1339fcf5ef2aSThomas Huth opc_handler_t handler; 1340fcf5ef2aSThomas Huth const char *oname; 1341fcf5ef2aSThomas Huth } opcode_t; 1342fcf5ef2aSThomas Huth 13439f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 13449f0cf041SMatheus Ferst { 13459f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 13469f0cf041SMatheus Ferst } 13479f0cf041SMatheus Ferst 1348fcf5ef2aSThomas Huth /* Helpers for priv. check */ 13499f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1350fcf5ef2aSThomas Huth do { \ 13519f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1352fcf5ef2aSThomas Huth } while (0) 1353fcf5ef2aSThomas Huth 1354fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 13559f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 13569f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 13579f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1358fcf5ef2aSThomas Huth #else 13599f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1360fcf5ef2aSThomas Huth do { \ 1361fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 13629f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1363fcf5ef2aSThomas Huth } \ 1364fcf5ef2aSThomas Huth } while (0) 13659f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1366fcf5ef2aSThomas Huth do { \ 1367fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13689f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1369fcf5ef2aSThomas Huth } \ 1370fcf5ef2aSThomas Huth } while (0) 13719f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1372fcf5ef2aSThomas Huth do { \ 1373fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13749f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1375fcf5ef2aSThomas Huth } \ 1376fcf5ef2aSThomas Huth } while (0) 1377fcf5ef2aSThomas Huth #endif 1378fcf5ef2aSThomas Huth 13799f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1380fcf5ef2aSThomas Huth 1381fcf5ef2aSThomas Huth /*****************************************************************************/ 1382fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1383fcf5ef2aSThomas Huth 1384fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1385fcf5ef2aSThomas Huth { \ 1386fcf5ef2aSThomas Huth .opc1 = op1, \ 1387fcf5ef2aSThomas Huth .opc2 = op2, \ 1388fcf5ef2aSThomas Huth .opc3 = op3, \ 1389fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1390fcf5ef2aSThomas Huth .handler = { \ 1391fcf5ef2aSThomas Huth .inval1 = invl, \ 1392fcf5ef2aSThomas Huth .type = _typ, \ 1393fcf5ef2aSThomas Huth .type2 = _typ2, \ 1394fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1395fcf5ef2aSThomas Huth }, \ 1396fcf5ef2aSThomas Huth .oname = stringify(name), \ 1397fcf5ef2aSThomas Huth } 1398fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1399fcf5ef2aSThomas Huth { \ 1400fcf5ef2aSThomas Huth .opc1 = op1, \ 1401fcf5ef2aSThomas Huth .opc2 = op2, \ 1402fcf5ef2aSThomas Huth .opc3 = op3, \ 1403fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1404fcf5ef2aSThomas Huth .handler = { \ 1405fcf5ef2aSThomas Huth .inval1 = invl1, \ 1406fcf5ef2aSThomas Huth .inval2 = invl2, \ 1407fcf5ef2aSThomas Huth .type = _typ, \ 1408fcf5ef2aSThomas Huth .type2 = _typ2, \ 1409fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1410fcf5ef2aSThomas Huth }, \ 1411fcf5ef2aSThomas Huth .oname = stringify(name), \ 1412fcf5ef2aSThomas Huth } 1413fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1414fcf5ef2aSThomas Huth { \ 1415fcf5ef2aSThomas Huth .opc1 = op1, \ 1416fcf5ef2aSThomas Huth .opc2 = op2, \ 1417fcf5ef2aSThomas Huth .opc3 = op3, \ 1418fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1419fcf5ef2aSThomas Huth .handler = { \ 1420fcf5ef2aSThomas Huth .inval1 = invl, \ 1421fcf5ef2aSThomas Huth .type = _typ, \ 1422fcf5ef2aSThomas Huth .type2 = _typ2, \ 1423fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1424fcf5ef2aSThomas Huth }, \ 1425fcf5ef2aSThomas Huth .oname = onam, \ 1426fcf5ef2aSThomas Huth } 1427fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1428fcf5ef2aSThomas Huth { \ 1429fcf5ef2aSThomas Huth .opc1 = op1, \ 1430fcf5ef2aSThomas Huth .opc2 = op2, \ 1431fcf5ef2aSThomas Huth .opc3 = op3, \ 1432fcf5ef2aSThomas Huth .opc4 = op4, \ 1433fcf5ef2aSThomas Huth .handler = { \ 1434fcf5ef2aSThomas Huth .inval1 = invl, \ 1435fcf5ef2aSThomas Huth .type = _typ, \ 1436fcf5ef2aSThomas Huth .type2 = _typ2, \ 1437fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1438fcf5ef2aSThomas Huth }, \ 1439fcf5ef2aSThomas Huth .oname = stringify(name), \ 1440fcf5ef2aSThomas Huth } 1441fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1442fcf5ef2aSThomas Huth { \ 1443fcf5ef2aSThomas Huth .opc1 = op1, \ 1444fcf5ef2aSThomas Huth .opc2 = op2, \ 1445fcf5ef2aSThomas Huth .opc3 = op3, \ 1446fcf5ef2aSThomas Huth .opc4 = op4, \ 1447fcf5ef2aSThomas Huth .handler = { \ 1448fcf5ef2aSThomas Huth .inval1 = invl, \ 1449fcf5ef2aSThomas Huth .type = _typ, \ 1450fcf5ef2aSThomas Huth .type2 = _typ2, \ 1451fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1452fcf5ef2aSThomas Huth }, \ 1453fcf5ef2aSThomas Huth .oname = onam, \ 1454fcf5ef2aSThomas Huth } 1455fcf5ef2aSThomas Huth 1456fcf5ef2aSThomas Huth /* Invalid instruction */ 1457fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1458fcf5ef2aSThomas Huth { 1459fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1460fcf5ef2aSThomas Huth } 1461fcf5ef2aSThomas Huth 1462fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1463fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1464fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1465fcf5ef2aSThomas Huth .type = PPC_NONE, 1466fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1467fcf5ef2aSThomas Huth .handler = gen_invalid, 1468fcf5ef2aSThomas Huth }; 1469fcf5ef2aSThomas Huth 1470fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1471fcf5ef2aSThomas Huth 1472fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1473fcf5ef2aSThomas Huth { 1474fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1475b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1476b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1477fcf5ef2aSThomas Huth 1478b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1479b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1480efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1481efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1482b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1483efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1484efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1485b62b3686Spbonzini@redhat.com 1486b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1487fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1488b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1489fcf5ef2aSThomas Huth } 1490fcf5ef2aSThomas Huth 1491fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1492fcf5ef2aSThomas Huth { 14937058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1494fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1495fcf5ef2aSThomas Huth } 1496fcf5ef2aSThomas Huth 1497fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1498fcf5ef2aSThomas Huth { 1499fcf5ef2aSThomas Huth TCGv t0, t1; 1500fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1501fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1502fcf5ef2aSThomas Huth if (s) { 1503fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1504fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1505fcf5ef2aSThomas Huth } else { 1506fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1507fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1508fcf5ef2aSThomas Huth } 1509fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1510fcf5ef2aSThomas Huth } 1511fcf5ef2aSThomas Huth 1512fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1513fcf5ef2aSThomas Huth { 15147058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1515fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1516fcf5ef2aSThomas Huth } 1517fcf5ef2aSThomas Huth 1518fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1519fcf5ef2aSThomas Huth { 1520fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1521fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1522fcf5ef2aSThomas Huth } else { 1523fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1524fcf5ef2aSThomas Huth } 1525fcf5ef2aSThomas Huth } 1526fcf5ef2aSThomas Huth 1527fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1528fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1529fcf5ef2aSThomas Huth { 1530fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1531fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1532fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1533fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1534fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1535fcf5ef2aSThomas Huth 1536fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1537fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1538fcf5ef2aSThomas Huth 1539fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1540fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1541fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1542fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1543fcf5ef2aSThomas Huth 1544fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1545fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1546fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1547fcf5ef2aSThomas Huth 1548fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1549fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1550fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1551fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1552fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1553fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1554fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1555fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1556fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1557fcf5ef2aSThomas Huth } 1558efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1559fcf5ef2aSThomas Huth } 1560fcf5ef2aSThomas Huth 1561fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1562fcf5ef2aSThomas Huth /* cmpeqb */ 1563fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1564fcf5ef2aSThomas Huth { 1565fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1566fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1567fcf5ef2aSThomas Huth } 1568fcf5ef2aSThomas Huth #endif 1569fcf5ef2aSThomas Huth 1570fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1571fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1572fcf5ef2aSThomas Huth { 1573fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1574fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1575fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1576fcf5ef2aSThomas Huth TCGv zr; 1577fcf5ef2aSThomas Huth 1578fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1579fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1580fcf5ef2aSThomas Huth 15817058ff52SRichard Henderson zr = tcg_constant_tl(0); 1582fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1583fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1584fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1585fcf5ef2aSThomas Huth } 1586fcf5ef2aSThomas Huth 1587fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1588fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1589fcf5ef2aSThomas Huth { 1590fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1591fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1592fcf5ef2aSThomas Huth } 1593fcf5ef2aSThomas Huth 1594fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1595fcf5ef2aSThomas Huth 1596fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1597fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1598fcf5ef2aSThomas Huth { 1599fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1600fcf5ef2aSThomas Huth 1601fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1602fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1603fcf5ef2aSThomas Huth if (sub) { 1604fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1605fcf5ef2aSThomas Huth } else { 1606fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1607fcf5ef2aSThomas Huth } 1608fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1609dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1610dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1611dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1612fcf5ef2aSThomas Huth } 1613dc0ad844SNikunj A Dadhania } else { 1614dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1615dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1616dc0ad844SNikunj A Dadhania } 161738a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1618dc0ad844SNikunj A Dadhania } 1619fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1620fcf5ef2aSThomas Huth } 1621fcf5ef2aSThomas Huth 16226b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 16236b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 16244c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 16256b10d008SNikunj A Dadhania { 16266b10d008SNikunj A Dadhania TCGv t0; 16276b10d008SNikunj A Dadhania 16286b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16296b10d008SNikunj A Dadhania return; 16306b10d008SNikunj A Dadhania } 16316b10d008SNikunj A Dadhania 16326b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 163333903d0aSNikunj A Dadhania if (sub) { 163433903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 163533903d0aSNikunj A Dadhania } else { 16366b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 163733903d0aSNikunj A Dadhania } 16386b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16394c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16406b10d008SNikunj A Dadhania } 16416b10d008SNikunj A Dadhania 1642fcf5ef2aSThomas Huth /* Common add function */ 1643fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16444c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16454c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1646fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1647fcf5ef2aSThomas Huth { 1648fcf5ef2aSThomas Huth TCGv t0 = ret; 1649fcf5ef2aSThomas Huth 1650fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1651fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1652fcf5ef2aSThomas Huth } 1653fcf5ef2aSThomas Huth 1654fcf5ef2aSThomas Huth if (compute_ca) { 1655fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1656efe843d8SDavid Gibson /* 1657efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1658efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1659efe843d8SDavid Gibson * produce the carry into bit 32. 1660efe843d8SDavid Gibson */ 1661fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1662fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1663fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1664fcf5ef2aSThomas Huth if (add_ca) { 16654c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1666fcf5ef2aSThomas Huth } 16674c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 16684c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16696b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16704c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16716b10d008SNikunj A Dadhania } 1672fcf5ef2aSThomas Huth } else { 16737058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 1674fcf5ef2aSThomas Huth if (add_ca) { 16754c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16764c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1677fcf5ef2aSThomas Huth } else { 16784c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1679fcf5ef2aSThomas Huth } 16804c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1681fcf5ef2aSThomas Huth } 1682fcf5ef2aSThomas Huth } else { 1683fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1684fcf5ef2aSThomas Huth if (add_ca) { 16854c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1686fcf5ef2aSThomas Huth } 1687fcf5ef2aSThomas Huth } 1688fcf5ef2aSThomas Huth 1689fcf5ef2aSThomas Huth if (compute_ov) { 1690fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1691fcf5ef2aSThomas Huth } 1692fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1693fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1694fcf5ef2aSThomas Huth } 1695fcf5ef2aSThomas Huth 169611f4e8f8SRichard Henderson if (t0 != ret) { 1697fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1698fcf5ef2aSThomas Huth } 1699fcf5ef2aSThomas Huth } 1700fcf5ef2aSThomas Huth /* Add functions with two operands */ 17014c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1702fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1703fcf5ef2aSThomas Huth { \ 1704fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1705fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 17064c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1707fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1708fcf5ef2aSThomas Huth } 1709fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 17104c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1711fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1712fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1713fcf5ef2aSThomas Huth { \ 17147058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 1715fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1716fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 17174c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1718fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1719fcf5ef2aSThomas Huth } 1720fcf5ef2aSThomas Huth 1721fcf5ef2aSThomas Huth /* add add. addo addo. */ 17224c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17234c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1724fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17254c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17264c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1727fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17284c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17294c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1730fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17314c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17324c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17334c5920afSSuraj Jitindar Singh /* addex */ 17344c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1735fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17364c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17374c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1738fcf5ef2aSThomas Huth /* addic addic.*/ 1739fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1740fcf5ef2aSThomas Huth { 17417058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1742fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17434c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1744fcf5ef2aSThomas Huth } 1745fcf5ef2aSThomas Huth 1746fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1747fcf5ef2aSThomas Huth { 1748fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1749fcf5ef2aSThomas Huth } 1750fcf5ef2aSThomas Huth 1751fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1752fcf5ef2aSThomas Huth { 1753fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1754fcf5ef2aSThomas Huth } 1755fcf5ef2aSThomas Huth 1756fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1757fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1758fcf5ef2aSThomas Huth { 1759fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1760fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1761fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1762fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1763fcf5ef2aSThomas Huth 1764fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1765fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1766fcf5ef2aSThomas Huth if (sign) { 1767fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1768fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1769fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1770fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1771fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1772fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1773fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1774fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1775fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1776fcf5ef2aSThomas Huth } else { 1777fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1778fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1779fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1780fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1781fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1782fcf5ef2aSThomas Huth } 1783fcf5ef2aSThomas Huth if (compute_ov) { 1784fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1785c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1786c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1787c44027ffSNikunj A Dadhania } 1788fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1789fcf5ef2aSThomas Huth } 1790fcf5ef2aSThomas Huth 1791efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1792fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1793fcf5ef2aSThomas Huth } 1794efe843d8SDavid Gibson } 1795fcf5ef2aSThomas Huth /* Div functions */ 1796fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1797fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1798fcf5ef2aSThomas Huth { \ 1799fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1800fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1801fcf5ef2aSThomas Huth sign, compute_ov); \ 1802fcf5ef2aSThomas Huth } 1803fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1804fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1805fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1806fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1807fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1808fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1809fcf5ef2aSThomas Huth 1810fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1811fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1812fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1813fcf5ef2aSThomas Huth { \ 18147058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1815fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1816fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1817fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1818fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1819fcf5ef2aSThomas Huth } \ 1820fcf5ef2aSThomas Huth } 1821fcf5ef2aSThomas Huth 1822fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1823fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1824fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1825fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1826fcf5ef2aSThomas Huth 1827fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1828fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1829fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1830fcf5ef2aSThomas Huth { 1831fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1832fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1833fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1834fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1835fcf5ef2aSThomas Huth 1836fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1837fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1838fcf5ef2aSThomas Huth if (sign) { 1839fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1840fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1841fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1842fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1843fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1844fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1845fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1846fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1847fcf5ef2aSThomas Huth } else { 1848fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1849fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1850fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1851fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1852fcf5ef2aSThomas Huth } 1853fcf5ef2aSThomas Huth if (compute_ov) { 1854fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1855c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1856c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1857c44027ffSNikunj A Dadhania } 1858fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1859fcf5ef2aSThomas Huth } 1860fcf5ef2aSThomas Huth 1861efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1862fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1863fcf5ef2aSThomas Huth } 1864efe843d8SDavid Gibson } 1865fcf5ef2aSThomas Huth 1866fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1867fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1868fcf5ef2aSThomas Huth { \ 1869fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1870fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1871fcf5ef2aSThomas Huth sign, compute_ov); \ 1872fcf5ef2aSThomas Huth } 1873c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1874fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1875fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1876c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1877fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1878fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1879fcf5ef2aSThomas Huth 1880fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1881fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1882fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1883fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1884fcf5ef2aSThomas Huth #endif 1885fcf5ef2aSThomas Huth 1886fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1887fcf5ef2aSThomas Huth TCGv arg2, int sign) 1888fcf5ef2aSThomas Huth { 1889fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1890fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1891fcf5ef2aSThomas Huth 1892fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1893fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1894fcf5ef2aSThomas Huth if (sign) { 1895fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1896fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1897fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1898fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1899fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1900fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1901fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1902fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1903fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1904fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1905fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1906fcf5ef2aSThomas Huth } else { 19077058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(1); 19087058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(0); 1909fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1910a253231fSRichard Henderson tcg_gen_remu_i32(t0, t0, t1); 1911a253231fSRichard Henderson tcg_gen_extu_i32_tl(ret, t0); 1912fcf5ef2aSThomas Huth } 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth 1915fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1916fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1917fcf5ef2aSThomas Huth { \ 1918fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1919fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1920fcf5ef2aSThomas Huth sign); \ 1921fcf5ef2aSThomas Huth } 1922fcf5ef2aSThomas Huth 1923fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1924fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1925fcf5ef2aSThomas Huth 1926fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1927fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1928fcf5ef2aSThomas Huth TCGv arg2, int sign) 1929fcf5ef2aSThomas Huth { 1930fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1931fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1932fcf5ef2aSThomas Huth 1933fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1934fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1935fcf5ef2aSThomas Huth if (sign) { 1936fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1937fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1938fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1939fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1940fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1941fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1942fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1943fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1944fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1945fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1946fcf5ef2aSThomas Huth } else { 19477058ff52SRichard Henderson TCGv_i64 t2 = tcg_constant_i64(1); 19487058ff52SRichard Henderson TCGv_i64 t3 = tcg_constant_i64(0); 1949fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1950fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1951fcf5ef2aSThomas Huth } 1952fcf5ef2aSThomas Huth } 1953fcf5ef2aSThomas Huth 1954fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1955fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1956fcf5ef2aSThomas Huth { \ 1957fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1958fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1959fcf5ef2aSThomas Huth sign); \ 1960fcf5ef2aSThomas Huth } 1961fcf5ef2aSThomas Huth 1962fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1963fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1964fcf5ef2aSThomas Huth #endif 1965fcf5ef2aSThomas Huth 1966fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1967fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1968fcf5ef2aSThomas Huth { 1969fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1970fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1971fcf5ef2aSThomas Huth 1972fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1973fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1974fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1975fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1976efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1977fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1978fcf5ef2aSThomas Huth } 1979efe843d8SDavid Gibson } 1980fcf5ef2aSThomas Huth 1981fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1982fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1983fcf5ef2aSThomas Huth { 1984fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1985fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1986fcf5ef2aSThomas Huth 1987fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1988fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1989fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1990fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1991efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1992fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1993fcf5ef2aSThomas Huth } 1994efe843d8SDavid Gibson } 1995fcf5ef2aSThomas Huth 1996fcf5ef2aSThomas Huth /* mullw mullw. */ 1997fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1998fcf5ef2aSThomas Huth { 1999fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2000fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2001fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2002fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2003fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2004fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2005fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2006fcf5ef2aSThomas Huth #else 2007fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2008fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2009fcf5ef2aSThomas Huth #endif 2010efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2011fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2012fcf5ef2aSThomas Huth } 2013efe843d8SDavid Gibson } 2014fcf5ef2aSThomas Huth 2015fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2016fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2017fcf5ef2aSThomas Huth { 2018fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2019fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2020fcf5ef2aSThomas Huth 2021fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2022fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2023fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2024fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2025fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2026fcf5ef2aSThomas Huth #else 2027fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2028fcf5ef2aSThomas Huth #endif 2029fcf5ef2aSThomas Huth 2030fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2031fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2032fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 203361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 203461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 203561aa9a69SNikunj A Dadhania } 2036fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2037fcf5ef2aSThomas Huth 2038efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2039fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2040fcf5ef2aSThomas Huth } 2041efe843d8SDavid Gibson } 2042fcf5ef2aSThomas Huth 2043fcf5ef2aSThomas Huth /* mulli */ 2044fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2045fcf5ef2aSThomas Huth { 2046fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2047fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2048fcf5ef2aSThomas Huth } 2049fcf5ef2aSThomas Huth 2050fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2051fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2052fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2053fcf5ef2aSThomas Huth { 2054fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2055fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2056fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2057fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2058fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2059fcf5ef2aSThomas Huth } 2060fcf5ef2aSThomas Huth } 2061fcf5ef2aSThomas Huth 2062fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2063fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2064fcf5ef2aSThomas Huth { 2065fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2066fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2067fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2068fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2069fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2070fcf5ef2aSThomas Huth } 2071fcf5ef2aSThomas Huth } 2072fcf5ef2aSThomas Huth 2073fcf5ef2aSThomas Huth /* mulld mulld. */ 2074fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2075fcf5ef2aSThomas Huth { 2076fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2077fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2078efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2079fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2080fcf5ef2aSThomas Huth } 2081efe843d8SDavid Gibson } 2082fcf5ef2aSThomas Huth 2083fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2084fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2085fcf5ef2aSThomas Huth { 2086fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2087fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2088fcf5ef2aSThomas Huth 2089fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2090fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2091fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2092fcf5ef2aSThomas Huth 2093fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2094fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 209561aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 209661aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 209761aa9a69SNikunj A Dadhania } 2098fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2099fcf5ef2aSThomas Huth 2100fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2101fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2102fcf5ef2aSThomas Huth } 2103fcf5ef2aSThomas Huth } 2104fcf5ef2aSThomas Huth #endif 2105fcf5ef2aSThomas Huth 2106fcf5ef2aSThomas Huth /* Common subf function */ 2107fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2108fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2109fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2110fcf5ef2aSThomas Huth { 2111fcf5ef2aSThomas Huth TCGv t0 = ret; 2112fcf5ef2aSThomas Huth 2113fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2114fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2115fcf5ef2aSThomas Huth } 2116fcf5ef2aSThomas Huth 2117fcf5ef2aSThomas Huth if (compute_ca) { 2118fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2119fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2120efe843d8SDavid Gibson /* 2121efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2122efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2123efe843d8SDavid Gibson * produce the carry into bit 32. 2124efe843d8SDavid Gibson */ 2125fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2126fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2127fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2128fcf5ef2aSThomas Huth if (add_ca) { 2129fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2130fcf5ef2aSThomas Huth } else { 2131fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2132fcf5ef2aSThomas Huth } 2133fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2134fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2135fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2136e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 213733903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 213833903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 213933903d0aSNikunj A Dadhania } 2140fcf5ef2aSThomas Huth } else if (add_ca) { 2141fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2142fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 21437058ff52SRichard Henderson zero = tcg_constant_tl(0); 2144fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2145fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21464c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2147fcf5ef2aSThomas Huth } else { 2148fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2149fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21504c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2151fcf5ef2aSThomas Huth } 2152fcf5ef2aSThomas Huth } else if (add_ca) { 2153efe843d8SDavid Gibson /* 2154efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2155efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2156efe843d8SDavid Gibson */ 2157fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2158fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2159fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2160fcf5ef2aSThomas Huth } else { 2161fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2162fcf5ef2aSThomas Huth } 2163fcf5ef2aSThomas Huth 2164fcf5ef2aSThomas Huth if (compute_ov) { 2165fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2166fcf5ef2aSThomas Huth } 2167fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2168fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2169fcf5ef2aSThomas Huth } 2170fcf5ef2aSThomas Huth 217111f4e8f8SRichard Henderson if (t0 != ret) { 2172fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2173fcf5ef2aSThomas Huth } 2174fcf5ef2aSThomas Huth } 2175fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2176fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2177fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2178fcf5ef2aSThomas Huth { \ 2179fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2180fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2181fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2182fcf5ef2aSThomas Huth } 2183fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2184fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2185fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2186fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2187fcf5ef2aSThomas Huth { \ 21887058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 2189fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2190fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2191fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2192fcf5ef2aSThomas Huth } 2193fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2194fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2195fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2196fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2197fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2198fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2199fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2200fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2201fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2202fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2203fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2204fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2205fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2206fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2207fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2208fcf5ef2aSThomas Huth 2209fcf5ef2aSThomas Huth /* subfic */ 2210fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2211fcf5ef2aSThomas Huth { 22127058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2213fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2214fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2215fcf5ef2aSThomas Huth } 2216fcf5ef2aSThomas Huth 2217fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2218fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2219fcf5ef2aSThomas Huth { 22207058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 2221fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2222fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2223fcf5ef2aSThomas Huth } 2224fcf5ef2aSThomas Huth 2225fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2226fcf5ef2aSThomas Huth { 22271480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22281480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22291480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22301480d71cSNikunj A Dadhania } 2231fcf5ef2aSThomas Huth } 2232fcf5ef2aSThomas Huth 2233fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2234fcf5ef2aSThomas Huth { 2235fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2236fcf5ef2aSThomas Huth } 2237fcf5ef2aSThomas Huth 2238fcf5ef2aSThomas Huth /*** Integer logical ***/ 2239fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2240fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2241fcf5ef2aSThomas Huth { \ 2242fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2243fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2244fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2245fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2246fcf5ef2aSThomas Huth } 2247fcf5ef2aSThomas Huth 2248fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2249fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2250fcf5ef2aSThomas Huth { \ 2251fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2252fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2253fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2254fcf5ef2aSThomas Huth } 2255fcf5ef2aSThomas Huth 2256fcf5ef2aSThomas Huth /* and & and. */ 2257fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2258fcf5ef2aSThomas Huth /* andc & andc. */ 2259fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2260fcf5ef2aSThomas Huth 2261fcf5ef2aSThomas Huth /* andi. */ 2262fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2263fcf5ef2aSThomas Huth { 2264efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2265efe843d8SDavid Gibson UIMM(ctx->opcode)); 2266fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2267fcf5ef2aSThomas Huth } 2268fcf5ef2aSThomas Huth 2269fcf5ef2aSThomas Huth /* andis. */ 2270fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2271fcf5ef2aSThomas Huth { 2272efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2273efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2274fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2275fcf5ef2aSThomas Huth } 2276fcf5ef2aSThomas Huth 2277fcf5ef2aSThomas Huth /* cntlzw */ 2278fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2279fcf5ef2aSThomas Huth { 22809b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22819b8514e5SRichard Henderson 22829b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22839b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22849b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22859b8514e5SRichard Henderson 2286efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2287fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2288fcf5ef2aSThomas Huth } 2289efe843d8SDavid Gibson } 2290fcf5ef2aSThomas Huth 2291fcf5ef2aSThomas Huth /* cnttzw */ 2292fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2293fcf5ef2aSThomas Huth { 22949b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22959b8514e5SRichard Henderson 22969b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22979b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22989b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22999b8514e5SRichard Henderson 2300fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2301fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2302fcf5ef2aSThomas Huth } 2303fcf5ef2aSThomas Huth } 2304fcf5ef2aSThomas Huth 2305fcf5ef2aSThomas Huth /* eqv & eqv. */ 2306fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2307fcf5ef2aSThomas Huth /* extsb & extsb. */ 2308fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2309fcf5ef2aSThomas Huth /* extsh & extsh. */ 2310fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2311fcf5ef2aSThomas Huth /* nand & nand. */ 2312fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2313fcf5ef2aSThomas Huth /* nor & nor. */ 2314fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2315fcf5ef2aSThomas Huth 2316fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2317fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2318fcf5ef2aSThomas Huth { 23197058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(0); 2320fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2321fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2322fcf5ef2aSThomas Huth 2323fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2324b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2325fcf5ef2aSThomas Huth } 2326fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2327fcf5ef2aSThomas Huth 2328fcf5ef2aSThomas Huth /* or & or. */ 2329fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2330fcf5ef2aSThomas Huth { 2331fcf5ef2aSThomas Huth int rs, ra, rb; 2332fcf5ef2aSThomas Huth 2333fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2334fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2335fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2336fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2337fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2338efe843d8SDavid Gibson if (rs != rb) { 2339fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2340efe843d8SDavid Gibson } else { 2341fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2342efe843d8SDavid Gibson } 2343efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2344fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2345efe843d8SDavid Gibson } 2346fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2347fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2348fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2349fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2350fcf5ef2aSThomas Huth int prio = 0; 2351fcf5ef2aSThomas Huth 2352fcf5ef2aSThomas Huth switch (rs) { 2353fcf5ef2aSThomas Huth case 1: 2354fcf5ef2aSThomas Huth /* Set process priority to low */ 2355fcf5ef2aSThomas Huth prio = 2; 2356fcf5ef2aSThomas Huth break; 2357fcf5ef2aSThomas Huth case 6: 2358fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2359fcf5ef2aSThomas Huth prio = 3; 2360fcf5ef2aSThomas Huth break; 2361fcf5ef2aSThomas Huth case 2: 2362fcf5ef2aSThomas Huth /* Set process priority to normal */ 2363fcf5ef2aSThomas Huth prio = 4; 2364fcf5ef2aSThomas Huth break; 2365fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2366fcf5ef2aSThomas Huth case 31: 2367fcf5ef2aSThomas Huth if (!ctx->pr) { 2368fcf5ef2aSThomas Huth /* Set process priority to very low */ 2369fcf5ef2aSThomas Huth prio = 1; 2370fcf5ef2aSThomas Huth } 2371fcf5ef2aSThomas Huth break; 2372fcf5ef2aSThomas Huth case 5: 2373fcf5ef2aSThomas Huth if (!ctx->pr) { 2374fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2375fcf5ef2aSThomas Huth prio = 5; 2376fcf5ef2aSThomas Huth } 2377fcf5ef2aSThomas Huth break; 2378fcf5ef2aSThomas Huth case 3: 2379fcf5ef2aSThomas Huth if (!ctx->pr) { 2380fcf5ef2aSThomas Huth /* Set process priority to high */ 2381fcf5ef2aSThomas Huth prio = 6; 2382fcf5ef2aSThomas Huth } 2383fcf5ef2aSThomas Huth break; 2384fcf5ef2aSThomas Huth case 7: 2385fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2386fcf5ef2aSThomas Huth /* Set process priority to very high */ 2387fcf5ef2aSThomas Huth prio = 7; 2388fcf5ef2aSThomas Huth } 2389fcf5ef2aSThomas Huth break; 2390fcf5ef2aSThomas Huth #endif 2391fcf5ef2aSThomas Huth default: 2392fcf5ef2aSThomas Huth break; 2393fcf5ef2aSThomas Huth } 2394fcf5ef2aSThomas Huth if (prio) { 2395fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2396fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2397fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2398fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2399fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2400fcf5ef2aSThomas Huth } 2401fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2402efe843d8SDavid Gibson /* 2403efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2404efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2405efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2406efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2407fcf5ef2aSThomas Huth */ 2408fcf5ef2aSThomas Huth gen_pause(ctx); 2409fcf5ef2aSThomas Huth #endif 2410fcf5ef2aSThomas Huth #endif 2411fcf5ef2aSThomas Huth } 2412fcf5ef2aSThomas Huth } 2413fcf5ef2aSThomas Huth /* orc & orc. */ 2414fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2415fcf5ef2aSThomas Huth 2416fcf5ef2aSThomas Huth /* xor & xor. */ 2417fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2418fcf5ef2aSThomas Huth { 2419fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2420efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2421efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2422efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2423efe843d8SDavid Gibson } else { 2424fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2425efe843d8SDavid Gibson } 2426efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2427fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2428fcf5ef2aSThomas Huth } 2429efe843d8SDavid Gibson } 2430fcf5ef2aSThomas Huth 2431fcf5ef2aSThomas Huth /* ori */ 2432fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2433fcf5ef2aSThomas Huth { 2434fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2435fcf5ef2aSThomas Huth 2436fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2437fcf5ef2aSThomas Huth return; 2438fcf5ef2aSThomas Huth } 2439fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2440fcf5ef2aSThomas Huth } 2441fcf5ef2aSThomas Huth 2442fcf5ef2aSThomas Huth /* oris */ 2443fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2444fcf5ef2aSThomas Huth { 2445fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2446fcf5ef2aSThomas Huth 2447fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2448fcf5ef2aSThomas Huth /* NOP */ 2449fcf5ef2aSThomas Huth return; 2450fcf5ef2aSThomas Huth } 2451efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2452efe843d8SDavid Gibson uimm << 16); 2453fcf5ef2aSThomas Huth } 2454fcf5ef2aSThomas Huth 2455fcf5ef2aSThomas Huth /* xori */ 2456fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2457fcf5ef2aSThomas Huth { 2458fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2459fcf5ef2aSThomas Huth 2460fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2461fcf5ef2aSThomas Huth /* NOP */ 2462fcf5ef2aSThomas Huth return; 2463fcf5ef2aSThomas Huth } 2464fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2465fcf5ef2aSThomas Huth } 2466fcf5ef2aSThomas Huth 2467fcf5ef2aSThomas Huth /* xoris */ 2468fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2469fcf5ef2aSThomas Huth { 2470fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2471fcf5ef2aSThomas Huth 2472fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2473fcf5ef2aSThomas Huth /* NOP */ 2474fcf5ef2aSThomas Huth return; 2475fcf5ef2aSThomas Huth } 2476efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2477efe843d8SDavid Gibson uimm << 16); 2478fcf5ef2aSThomas Huth } 2479fcf5ef2aSThomas Huth 2480fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2481fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2482fcf5ef2aSThomas Huth { 2483fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2484fcf5ef2aSThomas Huth } 2485fcf5ef2aSThomas Huth 2486fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2487fcf5ef2aSThomas Huth { 248879770002SRichard Henderson #if defined(TARGET_PPC64) 2489fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 249079770002SRichard Henderson #else 249179770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 249279770002SRichard Henderson #endif 2493fcf5ef2aSThomas Huth } 2494fcf5ef2aSThomas Huth 2495fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2496fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2497fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2498fcf5ef2aSThomas Huth { 249979770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2500fcf5ef2aSThomas Huth } 2501fcf5ef2aSThomas Huth #endif 2502fcf5ef2aSThomas Huth 2503fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2504fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2505fcf5ef2aSThomas Huth { 2506fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2507fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2508fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2509fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2510fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2511fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2512fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2513fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2514fcf5ef2aSThomas Huth } 2515fcf5ef2aSThomas Huth 2516fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2517fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2518fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2519fcf5ef2aSThomas Huth { 2520fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2521fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2522fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2523fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2524fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2525fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2526fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2527fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2528fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2529fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2530fcf5ef2aSThomas Huth } 2531fcf5ef2aSThomas Huth #endif 2532fcf5ef2aSThomas Huth 2533fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2534fcf5ef2aSThomas Huth /* bpermd */ 2535fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2536fcf5ef2aSThomas Huth { 2537fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2538fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2539fcf5ef2aSThomas Huth } 2540fcf5ef2aSThomas Huth #endif 2541fcf5ef2aSThomas Huth 2542fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2543fcf5ef2aSThomas Huth /* extsw & extsw. */ 2544fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2545fcf5ef2aSThomas Huth 2546fcf5ef2aSThomas Huth /* cntlzd */ 2547fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2548fcf5ef2aSThomas Huth { 25499b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2550efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2551fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2552fcf5ef2aSThomas Huth } 2553efe843d8SDavid Gibson } 2554fcf5ef2aSThomas Huth 2555fcf5ef2aSThomas Huth /* cnttzd */ 2556fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2557fcf5ef2aSThomas Huth { 25589b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2559fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2560fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2561fcf5ef2aSThomas Huth } 2562fcf5ef2aSThomas Huth } 2563fcf5ef2aSThomas Huth 2564fcf5ef2aSThomas Huth /* darn */ 2565fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2566fcf5ef2aSThomas Huth { 2567fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2568fcf5ef2aSThomas Huth 25697e4357f6SRichard Henderson if (l > 2) { 25707e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25717e4357f6SRichard Henderson } else { 2572283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 2573fcf5ef2aSThomas Huth if (l == 0) { 2574fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25757e4357f6SRichard Henderson } else { 2576fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2577fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25787e4357f6SRichard Henderson } 2579fcf5ef2aSThomas Huth } 2580fcf5ef2aSThomas Huth } 2581fcf5ef2aSThomas Huth #endif 2582fcf5ef2aSThomas Huth 2583fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2584fcf5ef2aSThomas Huth 2585fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2586fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2587fcf5ef2aSThomas Huth { 2588fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2589fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2590fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2591fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2592fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2593fcf5ef2aSThomas Huth 2594fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2595fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2596fcf5ef2aSThomas Huth } else { 2597fcf5ef2aSThomas Huth target_ulong mask; 2598c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2599fcf5ef2aSThomas Huth TCGv t1; 2600fcf5ef2aSThomas Huth 2601fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2602fcf5ef2aSThomas Huth mb += 32; 2603fcf5ef2aSThomas Huth me += 32; 2604fcf5ef2aSThomas Huth #endif 2605fcf5ef2aSThomas Huth mask = MASK(mb, me); 2606fcf5ef2aSThomas Huth 2607c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2608c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2609c4f6a4a3SDaniele Buono mask_in_32b = false; 2610c4f6a4a3SDaniele Buono } 2611c4f6a4a3SDaniele Buono #endif 2612fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2613c4f6a4a3SDaniele Buono if (mask_in_32b) { 2614fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2615fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2616fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2617fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2618fcf5ef2aSThomas Huth } else { 2619fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2620fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2621fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2622fcf5ef2aSThomas Huth #else 2623fcf5ef2aSThomas Huth g_assert_not_reached(); 2624fcf5ef2aSThomas Huth #endif 2625fcf5ef2aSThomas Huth } 2626fcf5ef2aSThomas Huth 2627fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2628fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2629fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2630fcf5ef2aSThomas Huth } 2631fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2632fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2633fcf5ef2aSThomas Huth } 2634fcf5ef2aSThomas Huth } 2635fcf5ef2aSThomas Huth 2636fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2637fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2638fcf5ef2aSThomas Huth { 2639fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2640fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26417b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26427b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26437b4d326fSRichard Henderson int me = ME(ctx->opcode); 26447b4d326fSRichard Henderson int len = me - mb + 1; 26457b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2646fcf5ef2aSThomas Huth 26477b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26487b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26497b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26507b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2651fcf5ef2aSThomas Huth } else { 2652fcf5ef2aSThomas Huth target_ulong mask; 2653c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2654fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2655fcf5ef2aSThomas Huth mb += 32; 2656fcf5ef2aSThomas Huth me += 32; 2657fcf5ef2aSThomas Huth #endif 2658fcf5ef2aSThomas Huth mask = MASK(mb, me); 2659c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2660c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2661c4f6a4a3SDaniele Buono mask_in_32b = false; 2662c4f6a4a3SDaniele Buono } 2663c4f6a4a3SDaniele Buono #endif 2664c4f6a4a3SDaniele Buono if (mask_in_32b) { 26657b4d326fSRichard Henderson if (sh == 0) { 26667b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 266794f040aaSVitaly Chikunov } else { 2668fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2669fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2670fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2671fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2672fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 267394f040aaSVitaly Chikunov } 2674fcf5ef2aSThomas Huth } else { 2675fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2676fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2677fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2678fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2679fcf5ef2aSThomas Huth #else 2680fcf5ef2aSThomas Huth g_assert_not_reached(); 2681fcf5ef2aSThomas Huth #endif 2682fcf5ef2aSThomas Huth } 2683fcf5ef2aSThomas Huth } 2684fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2685fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2686fcf5ef2aSThomas Huth } 2687fcf5ef2aSThomas Huth } 2688fcf5ef2aSThomas Huth 2689fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2690fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2691fcf5ef2aSThomas Huth { 2692fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2693fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2694fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2695fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2696fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2697fcf5ef2aSThomas Huth target_ulong mask; 2698c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2699fcf5ef2aSThomas Huth 2700fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2701fcf5ef2aSThomas Huth mb += 32; 2702fcf5ef2aSThomas Huth me += 32; 2703fcf5ef2aSThomas Huth #endif 2704fcf5ef2aSThomas Huth mask = MASK(mb, me); 2705fcf5ef2aSThomas Huth 2706c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2707c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2708c4f6a4a3SDaniele Buono mask_in_32b = false; 2709c4f6a4a3SDaniele Buono } 2710c4f6a4a3SDaniele Buono #endif 2711c4f6a4a3SDaniele Buono if (mask_in_32b) { 2712fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2713fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2714fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2715fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2716fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2717fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2718fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2719fcf5ef2aSThomas Huth } else { 2720fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2721fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2722fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2723fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2724fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2725fcf5ef2aSThomas Huth #else 2726fcf5ef2aSThomas Huth g_assert_not_reached(); 2727fcf5ef2aSThomas Huth #endif 2728fcf5ef2aSThomas Huth } 2729fcf5ef2aSThomas Huth 2730fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2731fcf5ef2aSThomas Huth 2732fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2733fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2734fcf5ef2aSThomas Huth } 2735fcf5ef2aSThomas Huth } 2736fcf5ef2aSThomas Huth 2737fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2738fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2739fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2740fcf5ef2aSThomas Huth { \ 2741fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2742fcf5ef2aSThomas Huth } \ 2743fcf5ef2aSThomas Huth \ 2744fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2745fcf5ef2aSThomas Huth { \ 2746fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2747fcf5ef2aSThomas Huth } 2748fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2749fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2750fcf5ef2aSThomas Huth { \ 2751fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2752fcf5ef2aSThomas Huth } \ 2753fcf5ef2aSThomas Huth \ 2754fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2755fcf5ef2aSThomas Huth { \ 2756fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2757fcf5ef2aSThomas Huth } \ 2758fcf5ef2aSThomas Huth \ 2759fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2760fcf5ef2aSThomas Huth { \ 2761fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2762fcf5ef2aSThomas Huth } \ 2763fcf5ef2aSThomas Huth \ 2764fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2765fcf5ef2aSThomas Huth { \ 2766fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2767fcf5ef2aSThomas Huth } 2768fcf5ef2aSThomas Huth 2769fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2770fcf5ef2aSThomas Huth { 2771fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2772fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27737b4d326fSRichard Henderson int len = me - mb + 1; 27747b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2775fcf5ef2aSThomas Huth 27767b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27777b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27787b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27797b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2780fcf5ef2aSThomas Huth } else { 2781fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2782fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2783fcf5ef2aSThomas Huth } 2784fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2785fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2786fcf5ef2aSThomas Huth } 2787fcf5ef2aSThomas Huth } 2788fcf5ef2aSThomas Huth 2789fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2790fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2791fcf5ef2aSThomas Huth { 2792fcf5ef2aSThomas Huth uint32_t sh, mb; 2793fcf5ef2aSThomas Huth 2794fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2795fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2796fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2797fcf5ef2aSThomas Huth } 2798fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2799fcf5ef2aSThomas Huth 2800fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2801fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2802fcf5ef2aSThomas Huth { 2803fcf5ef2aSThomas Huth uint32_t sh, me; 2804fcf5ef2aSThomas Huth 2805fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2806fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2807fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2808fcf5ef2aSThomas Huth } 2809fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2810fcf5ef2aSThomas Huth 2811fcf5ef2aSThomas Huth /* rldic - rldic. */ 2812fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2813fcf5ef2aSThomas Huth { 2814fcf5ef2aSThomas Huth uint32_t sh, mb; 2815fcf5ef2aSThomas Huth 2816fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2817fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2818fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2819fcf5ef2aSThomas Huth } 2820fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2821fcf5ef2aSThomas Huth 2822fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2823fcf5ef2aSThomas Huth { 2824fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2825fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2826fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2827fcf5ef2aSThomas Huth TCGv t0; 2828fcf5ef2aSThomas Huth 2829fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2830fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2831fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2832fcf5ef2aSThomas Huth 2833fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2834fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2835fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2836fcf5ef2aSThomas Huth } 2837fcf5ef2aSThomas Huth } 2838fcf5ef2aSThomas Huth 2839fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2840fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2841fcf5ef2aSThomas Huth { 2842fcf5ef2aSThomas Huth uint32_t mb; 2843fcf5ef2aSThomas Huth 2844fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2845fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2846fcf5ef2aSThomas Huth } 2847fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2848fcf5ef2aSThomas Huth 2849fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2850fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2851fcf5ef2aSThomas Huth { 2852fcf5ef2aSThomas Huth uint32_t me; 2853fcf5ef2aSThomas Huth 2854fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2855fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2856fcf5ef2aSThomas Huth } 2857fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2858fcf5ef2aSThomas Huth 2859fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2860fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2861fcf5ef2aSThomas Huth { 2862fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2863fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2864fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2865fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2866fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2867fcf5ef2aSThomas Huth 2868fcf5ef2aSThomas Huth if (mb <= me) { 2869fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2870fcf5ef2aSThomas Huth } else { 2871fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2872fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2873fcf5ef2aSThomas Huth 2874fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2875fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2876fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2877fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2878fcf5ef2aSThomas Huth } 2879fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2880fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2881fcf5ef2aSThomas Huth } 2882fcf5ef2aSThomas Huth } 2883fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2884fcf5ef2aSThomas Huth #endif 2885fcf5ef2aSThomas Huth 2886fcf5ef2aSThomas Huth /*** Integer shift ***/ 2887fcf5ef2aSThomas Huth 2888fcf5ef2aSThomas Huth /* slw & slw. */ 2889fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2890fcf5ef2aSThomas Huth { 2891fcf5ef2aSThomas Huth TCGv t0, t1; 2892fcf5ef2aSThomas Huth 2893fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2894fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2895fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2896fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2897fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2898fcf5ef2aSThomas Huth #else 2899fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2900fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2901fcf5ef2aSThomas Huth #endif 2902fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2903fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2904fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2905fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2906fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2907efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2908fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2909fcf5ef2aSThomas Huth } 2910efe843d8SDavid Gibson } 2911fcf5ef2aSThomas Huth 2912fcf5ef2aSThomas Huth /* sraw & sraw. */ 2913fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2914fcf5ef2aSThomas Huth { 2915fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2916fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2917efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2918fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2919fcf5ef2aSThomas Huth } 2920efe843d8SDavid Gibson } 2921fcf5ef2aSThomas Huth 2922fcf5ef2aSThomas Huth /* srawi & srawi. */ 2923fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2924fcf5ef2aSThomas Huth { 2925fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2926fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2927fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2928fcf5ef2aSThomas Huth if (sh == 0) { 2929fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2930fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2931af1c259fSSandipan Das if (is_isa300(ctx)) { 2932af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2933af1c259fSSandipan Das } 2934fcf5ef2aSThomas Huth } else { 2935fcf5ef2aSThomas Huth TCGv t0; 2936fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2937fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2938fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2939fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2940fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2941fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2942af1c259fSSandipan Das if (is_isa300(ctx)) { 2943af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2944af1c259fSSandipan Das } 2945fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2946fcf5ef2aSThomas Huth } 2947fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2948fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2949fcf5ef2aSThomas Huth } 2950fcf5ef2aSThomas Huth } 2951fcf5ef2aSThomas Huth 2952fcf5ef2aSThomas Huth /* srw & srw. */ 2953fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2954fcf5ef2aSThomas Huth { 2955fcf5ef2aSThomas Huth TCGv t0, t1; 2956fcf5ef2aSThomas Huth 2957fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2958fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2959fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2960fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2961fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2962fcf5ef2aSThomas Huth #else 2963fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2964fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2965fcf5ef2aSThomas Huth #endif 2966fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2967fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2968fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2969fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2970fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2971efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2972fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2973fcf5ef2aSThomas Huth } 2974efe843d8SDavid Gibson } 2975fcf5ef2aSThomas Huth 2976fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2977fcf5ef2aSThomas Huth /* sld & sld. */ 2978fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2979fcf5ef2aSThomas Huth { 2980fcf5ef2aSThomas Huth TCGv t0, t1; 2981fcf5ef2aSThomas Huth 2982fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2983fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2984fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2985fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2986fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2987fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2988fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2989fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2990efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2991fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2992fcf5ef2aSThomas Huth } 2993efe843d8SDavid Gibson } 2994fcf5ef2aSThomas Huth 2995fcf5ef2aSThomas Huth /* srad & srad. */ 2996fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2997fcf5ef2aSThomas Huth { 2998fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2999fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3000efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3001fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3002fcf5ef2aSThomas Huth } 3003efe843d8SDavid Gibson } 3004fcf5ef2aSThomas Huth /* sradi & sradi. */ 3005fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3006fcf5ef2aSThomas Huth { 3007fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3008fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3009fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3010fcf5ef2aSThomas Huth if (sh == 0) { 3011fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3012fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3013af1c259fSSandipan Das if (is_isa300(ctx)) { 3014af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3015af1c259fSSandipan Das } 3016fcf5ef2aSThomas Huth } else { 3017fcf5ef2aSThomas Huth TCGv t0; 3018fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3019fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3020fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3021fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3022fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3023af1c259fSSandipan Das if (is_isa300(ctx)) { 3024af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3025af1c259fSSandipan Das } 3026fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3027fcf5ef2aSThomas Huth } 3028fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3029fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3030fcf5ef2aSThomas Huth } 3031fcf5ef2aSThomas Huth } 3032fcf5ef2aSThomas Huth 3033fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3034fcf5ef2aSThomas Huth { 3035fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3036fcf5ef2aSThomas Huth } 3037fcf5ef2aSThomas Huth 3038fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3039fcf5ef2aSThomas Huth { 3040fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3041fcf5ef2aSThomas Huth } 3042fcf5ef2aSThomas Huth 3043fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3044fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3045fcf5ef2aSThomas Huth { 3046fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3047fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3048fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3049fcf5ef2aSThomas Huth 3050fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3051fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3052fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3053fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3054fcf5ef2aSThomas Huth } 3055fcf5ef2aSThomas Huth } 3056fcf5ef2aSThomas Huth 3057fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3058fcf5ef2aSThomas Huth { 3059fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3060fcf5ef2aSThomas Huth } 3061fcf5ef2aSThomas Huth 3062fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3063fcf5ef2aSThomas Huth { 3064fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3065fcf5ef2aSThomas Huth } 3066fcf5ef2aSThomas Huth 3067fcf5ef2aSThomas Huth /* srd & srd. */ 3068fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3069fcf5ef2aSThomas Huth { 3070fcf5ef2aSThomas Huth TCGv t0, t1; 3071fcf5ef2aSThomas Huth 3072fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3073fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3074fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3075fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3076fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3077fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3078fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3079fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3080efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3081fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3082fcf5ef2aSThomas Huth } 3083efe843d8SDavid Gibson } 3084fcf5ef2aSThomas Huth #endif 3085fcf5ef2aSThomas Huth 3086fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3087fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3088fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3089fcf5ef2aSThomas Huth target_long maskl) 3090fcf5ef2aSThomas Huth { 3091fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3092fcf5ef2aSThomas Huth 3093fcf5ef2aSThomas Huth simm &= ~maskl; 3094fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3095fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3096fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3097fcf5ef2aSThomas Huth } 3098fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3099fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3100fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3101fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3102fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3103fcf5ef2aSThomas Huth } 3104fcf5ef2aSThomas Huth } else { 3105fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3106fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3107fcf5ef2aSThomas Huth } else { 3108fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3109fcf5ef2aSThomas Huth } 3110fcf5ef2aSThomas Huth } 3111fcf5ef2aSThomas Huth } 3112fcf5ef2aSThomas Huth 3113fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3114fcf5ef2aSThomas Huth { 3115fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3116fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3117fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3118fcf5ef2aSThomas Huth } else { 3119fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3120fcf5ef2aSThomas Huth } 3121fcf5ef2aSThomas Huth } else { 3122fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3123fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3124fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3125fcf5ef2aSThomas Huth } 3126fcf5ef2aSThomas Huth } 3127fcf5ef2aSThomas Huth } 3128fcf5ef2aSThomas Huth 3129fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3130fcf5ef2aSThomas Huth { 3131fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3132fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3133fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3134fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3135fcf5ef2aSThomas Huth } else { 3136fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3137fcf5ef2aSThomas Huth } 3138fcf5ef2aSThomas Huth } 3139fcf5ef2aSThomas Huth 3140fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3141fcf5ef2aSThomas Huth target_long val) 3142fcf5ef2aSThomas Huth { 3143fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3144fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3145fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3146fcf5ef2aSThomas Huth } 3147fcf5ef2aSThomas Huth } 3148fcf5ef2aSThomas Huth 3149fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3150fcf5ef2aSThomas Huth { 3151fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3152fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3153fcf5ef2aSThomas Huth } 3154fcf5ef2aSThomas Huth 3155eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3156eb63efd9SFernando Eckhardt Valle { 3157eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3158eb63efd9SFernando Eckhardt Valle if (ra) { 3159eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3160eb63efd9SFernando Eckhardt Valle } else { 3161eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3162eb63efd9SFernando Eckhardt Valle } 3163eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3164eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3165eb63efd9SFernando Eckhardt Valle } 3166eb63efd9SFernando Eckhardt Valle return ea; 3167eb63efd9SFernando Eckhardt Valle } 3168eb63efd9SFernando Eckhardt Valle 3169fcf5ef2aSThomas Huth /*** Integer load ***/ 3170fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3171fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3172fcf5ef2aSThomas Huth 3173fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3174fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3175fcf5ef2aSThomas Huth TCGv val, \ 3176fcf5ef2aSThomas Huth TCGv addr) \ 3177fcf5ef2aSThomas Huth { \ 3178fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3179fcf5ef2aSThomas Huth } 3180fcf5ef2aSThomas Huth 3181fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3182fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3183fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3184fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3185fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3186fcf5ef2aSThomas Huth 3187fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3188fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3189fcf5ef2aSThomas Huth 3190fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3191fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3192fcf5ef2aSThomas Huth TCGv_i64 val, \ 3193fcf5ef2aSThomas Huth TCGv addr) \ 3194fcf5ef2aSThomas Huth { \ 3195fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3196fcf5ef2aSThomas Huth } 3197fcf5ef2aSThomas Huth 3198fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3199fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3200fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3201fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3202fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3203fcf5ef2aSThomas Huth 3204fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3205fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3206fcf5ef2aSThomas Huth #endif 3207fcf5ef2aSThomas Huth 3208fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3209fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3210fcf5ef2aSThomas Huth TCGv val, \ 3211fcf5ef2aSThomas Huth TCGv addr) \ 3212fcf5ef2aSThomas Huth { \ 3213fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3214fcf5ef2aSThomas Huth } 3215fcf5ef2aSThomas Huth 3216e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3217fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3218e8f4c8d6SRichard Henderson #endif 3219fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3220fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3221fcf5ef2aSThomas Huth 3222fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3223fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3224fcf5ef2aSThomas Huth 3225fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3226fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3227fcf5ef2aSThomas Huth TCGv_i64 val, \ 3228fcf5ef2aSThomas Huth TCGv addr) \ 3229fcf5ef2aSThomas Huth { \ 3230fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3231fcf5ef2aSThomas Huth } 3232fcf5ef2aSThomas Huth 3233fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3234fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3235fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3236fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3237fcf5ef2aSThomas Huth 3238fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3239fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3240fcf5ef2aSThomas Huth #endif 3241fcf5ef2aSThomas Huth 3242fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3243fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3244fcf5ef2aSThomas Huth { \ 3245fcf5ef2aSThomas Huth TCGv EA; \ 32469f0cf041SMatheus Ferst chk(ctx); \ 3247fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3248fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3249fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3250fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3251fcf5ef2aSThomas Huth } 3252fcf5ef2aSThomas Huth 3253fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3254fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3255fcf5ef2aSThomas Huth 3256fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3257fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3258fcf5ef2aSThomas Huth 325950728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 326050728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 326150728199SRoman Kapl { \ 326250728199SRoman Kapl TCGv EA; \ 32639f0cf041SMatheus Ferst CHK_SV(ctx); \ 326450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 326550728199SRoman Kapl EA = tcg_temp_new(); \ 326650728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 326750728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 326850728199SRoman Kapl } 326950728199SRoman Kapl 327050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 327150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 327250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 327350728199SRoman Kapl #if defined(TARGET_PPC64) 3274fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 327550728199SRoman Kapl #endif 327650728199SRoman Kapl 3277fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3278fcf5ef2aSThomas Huth /* CI load/store variants */ 3279fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3280fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3281fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3282fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3283fcf5ef2aSThomas Huth #endif 3284fcf5ef2aSThomas Huth 3285fcf5ef2aSThomas Huth /*** Integer store ***/ 3286fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3287fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3288fcf5ef2aSThomas Huth { \ 3289fcf5ef2aSThomas Huth TCGv EA; \ 32909f0cf041SMatheus Ferst chk(ctx); \ 3291fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3292fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3293fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3294fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3295fcf5ef2aSThomas Huth } 3296fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3297fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3298fcf5ef2aSThomas Huth 3299fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3300fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3301fcf5ef2aSThomas Huth 330250728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 330350728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 330450728199SRoman Kapl { \ 330550728199SRoman Kapl TCGv EA; \ 33069f0cf041SMatheus Ferst CHK_SV(ctx); \ 330750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 330850728199SRoman Kapl EA = tcg_temp_new(); \ 330950728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 331050728199SRoman Kapl tcg_gen_qemu_st_tl( \ 331150728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 331250728199SRoman Kapl } 331350728199SRoman Kapl 331450728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 331550728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 331650728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 331750728199SRoman Kapl #if defined(TARGET_PPC64) 3318fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 331950728199SRoman Kapl #endif 332050728199SRoman Kapl 3321fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3322fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3323fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3324fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3325fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3326fcf5ef2aSThomas Huth #endif 3327fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3328fcf5ef2aSThomas Huth 3329fcf5ef2aSThomas Huth /* lhbrx */ 3330fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3331fcf5ef2aSThomas Huth 3332fcf5ef2aSThomas Huth /* lwbrx */ 3333fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3334fcf5ef2aSThomas Huth 3335fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3336fcf5ef2aSThomas Huth /* ldbrx */ 3337fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3338fcf5ef2aSThomas Huth /* stdbrx */ 3339fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3340fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3341fcf5ef2aSThomas Huth 3342fcf5ef2aSThomas Huth /* sthbrx */ 3343fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3344fcf5ef2aSThomas Huth /* stwbrx */ 3345fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3346fcf5ef2aSThomas Huth 3347fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3348fcf5ef2aSThomas Huth 3349fcf5ef2aSThomas Huth /* lmw */ 3350fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3351fcf5ef2aSThomas Huth { 3352fcf5ef2aSThomas Huth TCGv t0; 3353fcf5ef2aSThomas Huth TCGv_i32 t1; 3354fcf5ef2aSThomas Huth 3355fcf5ef2aSThomas Huth if (ctx->le_mode) { 3356fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3357fcf5ef2aSThomas Huth return; 3358fcf5ef2aSThomas Huth } 3359fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3360fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33617058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 3362fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3363fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3364fcf5ef2aSThomas Huth } 3365fcf5ef2aSThomas Huth 3366fcf5ef2aSThomas Huth /* stmw */ 3367fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3368fcf5ef2aSThomas Huth { 3369fcf5ef2aSThomas Huth TCGv t0; 3370fcf5ef2aSThomas Huth TCGv_i32 t1; 3371fcf5ef2aSThomas Huth 3372fcf5ef2aSThomas Huth if (ctx->le_mode) { 3373fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3374fcf5ef2aSThomas Huth return; 3375fcf5ef2aSThomas Huth } 3376fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3377fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33787058ff52SRichard Henderson t1 = tcg_constant_i32(rS(ctx->opcode)); 3379fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3380fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3381fcf5ef2aSThomas Huth } 3382fcf5ef2aSThomas Huth 3383fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3384fcf5ef2aSThomas Huth 3385fcf5ef2aSThomas Huth /* lswi */ 3386efe843d8SDavid Gibson /* 3387efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3388efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3389efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3390efe843d8SDavid Gibson * spec... 3391fcf5ef2aSThomas Huth */ 3392fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3393fcf5ef2aSThomas Huth { 3394fcf5ef2aSThomas Huth TCGv t0; 3395fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3396fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3397fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3398fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3399fcf5ef2aSThomas Huth int nr; 3400fcf5ef2aSThomas Huth 3401fcf5ef2aSThomas Huth if (ctx->le_mode) { 3402fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3403fcf5ef2aSThomas Huth return; 3404fcf5ef2aSThomas Huth } 3405efe843d8SDavid Gibson if (nb == 0) { 3406fcf5ef2aSThomas Huth nb = 32; 3407efe843d8SDavid Gibson } 3408f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3409fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3410fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3411fcf5ef2aSThomas Huth return; 3412fcf5ef2aSThomas Huth } 3413fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3414fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3415fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 34167058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 34177058ff52SRichard Henderson t2 = tcg_constant_i32(start); 3418fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3419fcf5ef2aSThomas Huth } 3420fcf5ef2aSThomas Huth 3421fcf5ef2aSThomas Huth /* lswx */ 3422fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3423fcf5ef2aSThomas Huth { 3424fcf5ef2aSThomas Huth TCGv t0; 3425fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3426fcf5ef2aSThomas Huth 3427fcf5ef2aSThomas Huth if (ctx->le_mode) { 3428fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3429fcf5ef2aSThomas Huth return; 3430fcf5ef2aSThomas Huth } 3431fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3432fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3433fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 34347058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 34357058ff52SRichard Henderson t2 = tcg_constant_i32(rA(ctx->opcode)); 34367058ff52SRichard Henderson t3 = tcg_constant_i32(rB(ctx->opcode)); 3437fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3438fcf5ef2aSThomas Huth } 3439fcf5ef2aSThomas Huth 3440fcf5ef2aSThomas Huth /* stswi */ 3441fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3442fcf5ef2aSThomas Huth { 3443fcf5ef2aSThomas Huth TCGv t0; 3444fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3445fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3446fcf5ef2aSThomas Huth 3447fcf5ef2aSThomas Huth if (ctx->le_mode) { 3448fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3449fcf5ef2aSThomas Huth return; 3450fcf5ef2aSThomas Huth } 3451fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3452fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3453fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3454efe843d8SDavid Gibson if (nb == 0) { 3455fcf5ef2aSThomas Huth nb = 32; 3456efe843d8SDavid Gibson } 34577058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 34587058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3459fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3460fcf5ef2aSThomas Huth } 3461fcf5ef2aSThomas Huth 3462fcf5ef2aSThomas Huth /* stswx */ 3463fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3464fcf5ef2aSThomas Huth { 3465fcf5ef2aSThomas Huth TCGv t0; 3466fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3467fcf5ef2aSThomas Huth 3468fcf5ef2aSThomas Huth if (ctx->le_mode) { 3469fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3470fcf5ef2aSThomas Huth return; 3471fcf5ef2aSThomas Huth } 3472fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3473fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3474fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3475fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3476fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3477fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 34787058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3479fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3480fcf5ef2aSThomas Huth } 3481fcf5ef2aSThomas Huth 3482fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3483fcf5ef2aSThomas Huth /* eieio */ 3484fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3485fcf5ef2aSThomas Huth { 3486fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3487fcb830afSNicholas Piggin 3488fcb830afSNicholas Piggin /* 3489fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3490fcb830afSNicholas Piggin * operations in the set: 3491fcb830afSNicholas Piggin * - loads from CI memory. 3492fcb830afSNicholas Piggin * - stores to CI memory. 3493fcb830afSNicholas Piggin * - stores to WT memory. 3494fcb830afSNicholas Piggin * 3495fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3496fcb830afSNicholas Piggin * - stores to cacheble memory. 3497fcb830afSNicholas Piggin * 3498fcb830afSNicholas Piggin * It also serializes instructions: 3499fcb830afSNicholas Piggin * - dcbt and dcbst. 3500fcb830afSNicholas Piggin * 3501fcb830afSNicholas Piggin * It separately serializes: 3502fcb830afSNicholas Piggin * - tlbie and tlbsync. 3503fcb830afSNicholas Piggin * 3504fcb830afSNicholas Piggin * And separately serializes: 3505fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3506fcb830afSNicholas Piggin * 3507fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3508fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3509fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3510fcb830afSNicholas Piggin * serialization. 3511fcb830afSNicholas Piggin */ 3512c8fd8373SCédric Le Goater 3513c8fd8373SCédric Le Goater /* 3514c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3515c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3516c8fd8373SCédric Le Goater */ 3517c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3518c8fd8373SCédric Le Goater /* 3519c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3520c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3521c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3522c8fd8373SCédric Le Goater * complain to the user. 3523c8fd8373SCédric Le Goater */ 3524c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3525c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 35262c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3527c8fd8373SCédric Le Goater } else { 3528c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3529c8fd8373SCédric Le Goater } 3530c8fd8373SCédric Le Goater } 3531c8fd8373SCédric Le Goater 3532c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3533fcf5ef2aSThomas Huth } 3534fcf5ef2aSThomas Huth 3535fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3536fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3537fcf5ef2aSThomas Huth { 3538fcf5ef2aSThomas Huth TCGv_i32 t; 3539fcf5ef2aSThomas Huth TCGLabel *l; 3540fcf5ef2aSThomas Huth 3541fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3542fcf5ef2aSThomas Huth return; 3543fcf5ef2aSThomas Huth } 3544fcf5ef2aSThomas Huth l = gen_new_label(); 3545fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3546fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3547fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3548fcf5ef2aSThomas Huth if (global) { 3549fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3550fcf5ef2aSThomas Huth } else { 3551fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3552fcf5ef2aSThomas Huth } 3553fcf5ef2aSThomas Huth gen_set_label(l); 3554fcf5ef2aSThomas Huth } 3555fcf5ef2aSThomas Huth #else 3556fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3557fcf5ef2aSThomas Huth #endif 3558fcf5ef2aSThomas Huth 3559fcf5ef2aSThomas Huth /* isync */ 3560fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3561fcf5ef2aSThomas Huth { 3562fcf5ef2aSThomas Huth /* 3563fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3564fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3565fcf5ef2aSThomas Huth */ 3566fcf5ef2aSThomas Huth if (!ctx->pr) { 3567fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3568fcf5ef2aSThomas Huth } 35694771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3570d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3571fcf5ef2aSThomas Huth } 3572fcf5ef2aSThomas Huth 3573fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3574fcf5ef2aSThomas Huth 357514776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 35762a4e6c1bSRichard Henderson { 35772a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 35782a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 35792a4e6c1bSRichard Henderson 35802a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 35812a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 35822a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 35832a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 3584392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 35852a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 35862a4e6c1bSRichard Henderson } 35872a4e6c1bSRichard Henderson 3588fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3589fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3590fcf5ef2aSThomas Huth { \ 35912a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3592fcf5ef2aSThomas Huth } 3593fcf5ef2aSThomas Huth 3594fcf5ef2aSThomas Huth /* lwarx */ 3595fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3596fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3597fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3598fcf5ef2aSThomas Huth 359914776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 360020923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 360120923c1dSRichard Henderson { 360220923c1dSRichard Henderson TCGv t = tcg_temp_new(); 360320923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 360420923c1dSRichard Henderson TCGv u = tcg_temp_new(); 360520923c1dSRichard Henderson 360620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 360720923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 360820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 360920923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 361020923c1dSRichard Henderson 361120923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 361220923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 361320923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 361420923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 361520923c1dSRichard Henderson 361620923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 361720923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 361820923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 361920923c1dSRichard Henderson } 362020923c1dSRichard Henderson 362114776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 362220ba8504SRichard Henderson { 362320ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 362420ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 362520923c1dSRichard Henderson int rt = rD(ctx->opcode); 362620923c1dSRichard Henderson bool need_serial; 362720ba8504SRichard Henderson TCGv src, dst; 362820ba8504SRichard Henderson 362920ba8504SRichard Henderson gen_addr_register(ctx, EA); 363020923c1dSRichard Henderson dst = cpu_gpr[rt]; 363120923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 363220ba8504SRichard Henderson 363320923c1dSRichard Henderson need_serial = false; 363420ba8504SRichard Henderson memop |= MO_ALIGN; 363520ba8504SRichard Henderson switch (gpr_FC) { 363620ba8504SRichard Henderson case 0: /* Fetch and add */ 363720ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 363820ba8504SRichard Henderson break; 363920ba8504SRichard Henderson case 1: /* Fetch and xor */ 364020ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 364120ba8504SRichard Henderson break; 364220ba8504SRichard Henderson case 2: /* Fetch and or */ 364320ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 364420ba8504SRichard Henderson break; 364520ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 364620ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 364720ba8504SRichard Henderson break; 3648b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3649b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3650b8ce0f86SRichard Henderson break; 3651b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3652b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3653b8ce0f86SRichard Henderson break; 3654b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3655b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3656b8ce0f86SRichard Henderson break; 3657b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3658b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3659b8ce0f86SRichard Henderson break; 366020ba8504SRichard Henderson case 8: /* Swap */ 366120ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 366220ba8504SRichard Henderson break; 366320923c1dSRichard Henderson 366420923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 366520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 366620923c1dSRichard Henderson need_serial = true; 366720923c1dSRichard Henderson } else { 366820923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 366920923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 367020923c1dSRichard Henderson 367120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 367220923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 367320923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 367420923c1dSRichard Henderson } else { 367520923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 367620923c1dSRichard Henderson } 367720923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 367820923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 367920923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 368020923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 368120923c1dSRichard Henderson } 368220ba8504SRichard Henderson break; 368320923c1dSRichard Henderson 368420923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 368520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 368620923c1dSRichard Henderson need_serial = true; 368720923c1dSRichard Henderson } else { 368820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 368920923c1dSRichard Henderson } 369020923c1dSRichard Henderson break; 369120923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 369220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 369320923c1dSRichard Henderson need_serial = true; 369420923c1dSRichard Henderson } else { 369520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 369620923c1dSRichard Henderson } 369720923c1dSRichard Henderson break; 369820923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 369920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 370020923c1dSRichard Henderson need_serial = true; 370120923c1dSRichard Henderson } else { 370220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 370320923c1dSRichard Henderson } 370420923c1dSRichard Henderson break; 370520923c1dSRichard Henderson 370620ba8504SRichard Henderson default: 370720ba8504SRichard Henderson /* invoke data storage error handler */ 370820ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 370920ba8504SRichard Henderson } 371020923c1dSRichard Henderson 371120923c1dSRichard Henderson if (need_serial) { 371220923c1dSRichard Henderson /* Restart with exclusive lock. */ 371320923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 371420923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 371520923c1dSRichard Henderson } 3716a68a6146SBalamuruhan S } 3717a68a6146SBalamuruhan S 371820ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 371920ba8504SRichard Henderson { 372020ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 372120ba8504SRichard Henderson } 372220ba8504SRichard Henderson 372320ba8504SRichard Henderson #ifdef TARGET_PPC64 372420ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 372520ba8504SRichard Henderson { 3726fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 372720ba8504SRichard Henderson } 3728a68a6146SBalamuruhan S #endif 3729a68a6146SBalamuruhan S 373014776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 37319deb041cSRichard Henderson { 37329deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 37339deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 37349deb041cSRichard Henderson TCGv src, discard; 37359deb041cSRichard Henderson 37369deb041cSRichard Henderson gen_addr_register(ctx, EA); 37379deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 37389deb041cSRichard Henderson discard = tcg_temp_new(); 37399deb041cSRichard Henderson 37409deb041cSRichard Henderson memop |= MO_ALIGN; 37419deb041cSRichard Henderson switch (gpr_FC) { 37429deb041cSRichard Henderson case 0: /* add and Store */ 37439deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37449deb041cSRichard Henderson break; 37459deb041cSRichard Henderson case 1: /* xor and Store */ 37469deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37479deb041cSRichard Henderson break; 37489deb041cSRichard Henderson case 2: /* Or and Store */ 37499deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37509deb041cSRichard Henderson break; 37519deb041cSRichard Henderson case 3: /* 'and' and Store */ 37529deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37539deb041cSRichard Henderson break; 37549deb041cSRichard Henderson case 4: /* Store max unsigned */ 3755b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3756b8ce0f86SRichard Henderson break; 37579deb041cSRichard Henderson case 5: /* Store max signed */ 3758b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3759b8ce0f86SRichard Henderson break; 37609deb041cSRichard Henderson case 6: /* Store min unsigned */ 3761b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3762b8ce0f86SRichard Henderson break; 37639deb041cSRichard Henderson case 7: /* Store min signed */ 3764b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3765b8ce0f86SRichard Henderson break; 37669deb041cSRichard Henderson case 24: /* Store twin */ 37677fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 37687fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 37697fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 37707fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 37717fbc2b20SRichard Henderson } else { 37727fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 37737fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 37747fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 37757fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 37767fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 37777fbc2b20SRichard Henderson 37787fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 37797fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 37807fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 37817fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 37827fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 37837fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 37847fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 37857fbc2b20SRichard Henderson } 37869deb041cSRichard Henderson break; 37879deb041cSRichard Henderson default: 37889deb041cSRichard Henderson /* invoke data storage error handler */ 37899deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 37909deb041cSRichard Henderson } 3791a3401188SBalamuruhan S } 3792a3401188SBalamuruhan S 37939deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 37949deb041cSRichard Henderson { 37959deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 37969deb041cSRichard Henderson } 37979deb041cSRichard Henderson 37989deb041cSRichard Henderson #ifdef TARGET_PPC64 37999deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 38009deb041cSRichard Henderson { 3801fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 38029deb041cSRichard Henderson } 3803a3401188SBalamuruhan S #endif 3804a3401188SBalamuruhan S 380514776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3806fcf5ef2aSThomas Huth { 380721ee07e7SNicholas Piggin TCGLabel *lfail; 380821ee07e7SNicholas Piggin TCGv EA; 380921ee07e7SNicholas Piggin TCGv cr0; 381021ee07e7SNicholas Piggin TCGv t0; 381121ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3812fcf5ef2aSThomas Huth 381321ee07e7SNicholas Piggin lfail = gen_new_label(); 381421ee07e7SNicholas Piggin EA = tcg_temp_new(); 381521ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3816253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 381721ee07e7SNicholas Piggin 381821ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 381921ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 382021ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 382121ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 382221ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 382321ee07e7SNicholas Piggin 3824253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 382521ee07e7SNicholas Piggin cpu_gpr[rs], ctx->mem_idx, 3826253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3827253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3828253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 382921ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3830253ce7b2SNikunj A Dadhania 383121ee07e7SNicholas Piggin gen_set_label(lfail); 383221ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3833fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3834fcf5ef2aSThomas Huth } 3835fcf5ef2aSThomas Huth 3836fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3837fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3838fcf5ef2aSThomas Huth { \ 3839d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3840fcf5ef2aSThomas Huth } 3841fcf5ef2aSThomas Huth 3842fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3843fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3844fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3845fcf5ef2aSThomas Huth 3846fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3847fcf5ef2aSThomas Huth /* ldarx */ 3848fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3849fcf5ef2aSThomas Huth /* stdcx. */ 3850fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3851fcf5ef2aSThomas Huth 3852fcf5ef2aSThomas Huth /* lqarx */ 3853fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3854fcf5ef2aSThomas Huth { 3855fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 385694bf2658SRichard Henderson TCGv EA, hi, lo; 385757b38ffdSRichard Henderson TCGv_i128 t16; 3858fcf5ef2aSThomas Huth 3859fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3860fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3861fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3862fcf5ef2aSThomas Huth return; 3863fcf5ef2aSThomas Huth } 3864fcf5ef2aSThomas Huth 3865fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 386694bf2658SRichard Henderson EA = tcg_temp_new(); 3867fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 386894bf2658SRichard Henderson 386994bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 387094bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 387194bf2658SRichard Henderson hi = cpu_gpr[rd]; 387294bf2658SRichard Henderson 387357b38ffdSRichard Henderson t16 = tcg_temp_new_i128(); 387457b38ffdSRichard Henderson tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 387557b38ffdSRichard Henderson tcg_gen_extr_i128_i64(lo, hi, t16); 387694bf2658SRichard Henderson 3877e025e8f5SNicholas Piggin tcg_gen_mov_tl(cpu_reserve, EA); 3878392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, 16); 387994bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 388094bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3881fcf5ef2aSThomas Huth } 3882fcf5ef2aSThomas Huth 3883fcf5ef2aSThomas Huth /* stqcx. */ 3884fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3885fcf5ef2aSThomas Huth { 388621ee07e7SNicholas Piggin TCGLabel *lfail; 3887894448aeSRichard Henderson TCGv EA, t0, t1; 388821ee07e7SNicholas Piggin TCGv cr0; 3889894448aeSRichard Henderson TCGv_i128 cmp, val; 389021ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3891fcf5ef2aSThomas Huth 38924a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3893fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3894fcf5ef2aSThomas Huth return; 3895fcf5ef2aSThomas Huth } 38964a9b3c5dSRichard Henderson 389721ee07e7SNicholas Piggin lfail = gen_new_label(); 38984a9b3c5dSRichard Henderson EA = tcg_temp_new(); 389921ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3900fcf5ef2aSThomas Huth 390121ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 390221ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 390321ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 390421ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 390521ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 39064a9b3c5dSRichard Henderson 3907894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 3908894448aeSRichard Henderson val = tcg_temp_new_i128(); 39094a9b3c5dSRichard Henderson 3910894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 39114a9b3c5dSRichard Henderson 3912894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3913894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 39144a9b3c5dSRichard Henderson 3915894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3916894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 3917894448aeSRichard Henderson 3918894448aeSRichard Henderson t0 = tcg_temp_new(); 3919894448aeSRichard Henderson t1 = tcg_temp_new(); 3920894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 3921894448aeSRichard Henderson 3922894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3923894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3924894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 3925894448aeSRichard Henderson 3926894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3927894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 392821ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3929894448aeSRichard Henderson 393021ee07e7SNicholas Piggin gen_set_label(lfail); 393121ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 39324a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 39334a9b3c5dSRichard Henderson } 3934fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3935fcf5ef2aSThomas Huth 3936fcf5ef2aSThomas Huth /* sync */ 3937fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3938fcf5ef2aSThomas Huth { 393903abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 3940fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3941fcf5ef2aSThomas Huth 394203abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 394303abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 394403abfd90SNicholas Piggin } 394503abfd90SNicholas Piggin 3946fcf5ef2aSThomas Huth /* 3947fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3948fcf5ef2aSThomas Huth * 3949fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3950fcf5ef2aSThomas Huth * 3951fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3952fcf5ef2aSThomas Huth * check MSR_PR as well. 3953fcf5ef2aSThomas Huth */ 3954fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3955fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3956fcf5ef2aSThomas Huth } 395703abfd90SNicholas Piggin 395803abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 3959fcf5ef2aSThomas Huth } 3960fcf5ef2aSThomas Huth 3961fcf5ef2aSThomas Huth /* wait */ 3962fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3963fcf5ef2aSThomas Huth { 39640c9717ffSNicholas Piggin uint32_t wc; 39650c9717ffSNicholas Piggin 39660c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 39670c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 39680c9717ffSNicholas Piggin 39690c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 39700c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 39710c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39720c9717ffSNicholas Piggin } else { 39730c9717ffSNicholas Piggin wc = 0; 39740c9717ffSNicholas Piggin } 39750c9717ffSNicholas Piggin 39760c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 39770c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 39780c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39790c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 39800c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 39810c9717ffSNicholas Piggin 39820c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 39830c9717ffSNicholas Piggin if (wc == 3) { 39840c9717ffSNicholas Piggin gen_invalid(ctx); 39850c9717ffSNicholas Piggin return; 39860c9717ffSNicholas Piggin } 39870c9717ffSNicholas Piggin 39880c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 39890c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 39900c9717ffSNicholas Piggin gen_invalid(ctx); 39910c9717ffSNicholas Piggin return; 39920c9717ffSNicholas Piggin } 39930c9717ffSNicholas Piggin 39940c9717ffSNicholas Piggin } else { /* ISA300 */ 39950c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 39960c9717ffSNicholas Piggin if (wc > 0) { 39970c9717ffSNicholas Piggin gen_invalid(ctx); 39980c9717ffSNicholas Piggin return; 39990c9717ffSNicholas Piggin } 40000c9717ffSNicholas Piggin } 40010c9717ffSNicholas Piggin 40020c9717ffSNicholas Piggin } else { 40030c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 40040c9717ffSNicholas Piggin gen_invalid(ctx); 40050c9717ffSNicholas Piggin return; 40060c9717ffSNicholas Piggin } 40070c9717ffSNicholas Piggin 40080c9717ffSNicholas Piggin /* 40090c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 40100c9717ffSNicholas Piggin * to occur. 40110c9717ffSNicholas Piggin */ 40120c9717ffSNicholas Piggin if (wc == 0) { 40137058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(1); 4014fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4015fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4016fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4017b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4018fcf5ef2aSThomas Huth } 4019fcf5ef2aSThomas Huth 40200c9717ffSNicholas Piggin /* 40210c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 40220c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 40230c9717ffSNicholas Piggin * 40240c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 40250c9717ffSNicholas Piggin * no-ops. 40260c9717ffSNicholas Piggin * 40270c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 40280c9717ffSNicholas Piggin * 40290c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 40300c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 40310c9717ffSNicholas Piggin * 40320c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 40330c9717ffSNicholas Piggin * 40340c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 40350c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 40360c9717ffSNicholas Piggin * can be implemented as a no-op. 40370c9717ffSNicholas Piggin * 40380c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 40390c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 40400c9717ffSNicholas Piggin * no-op. 40410c9717ffSNicholas Piggin * 40420c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 40430c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 40440c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 40450c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 40460c9717ffSNicholas Piggin * (if suboptimal). 40470c9717ffSNicholas Piggin */ 40480c9717ffSNicholas Piggin } 40490c9717ffSNicholas Piggin 4050fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4051fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4052fcf5ef2aSThomas Huth { 4053fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40549f0cf041SMatheus Ferst GEN_PRIV(ctx); 4055fcf5ef2aSThomas Huth #else 4056fcf5ef2aSThomas Huth TCGv_i32 t; 4057fcf5ef2aSThomas Huth 40589f0cf041SMatheus Ferst CHK_HV(ctx); 4059c32654afSNicholas Piggin translator_io_start(&ctx->base); 40607058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_DOZE); 4061fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4062154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4063154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4064fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4065fcf5ef2aSThomas Huth } 4066fcf5ef2aSThomas Huth 4067fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4068fcf5ef2aSThomas Huth { 4069fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40709f0cf041SMatheus Ferst GEN_PRIV(ctx); 4071fcf5ef2aSThomas Huth #else 4072fcf5ef2aSThomas Huth TCGv_i32 t; 4073fcf5ef2aSThomas Huth 40749f0cf041SMatheus Ferst CHK_HV(ctx); 4075c32654afSNicholas Piggin translator_io_start(&ctx->base); 40767058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_NAP); 4077fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4078154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4079154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4080fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4081fcf5ef2aSThomas Huth } 4082fcf5ef2aSThomas Huth 4083cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4084cdee0e72SNikunj A Dadhania { 408521c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 40869f0cf041SMatheus Ferst GEN_PRIV(ctx); 408721c0d66aSBenjamin Herrenschmidt #else 408821c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 408921c0d66aSBenjamin Herrenschmidt 40909f0cf041SMatheus Ferst CHK_HV(ctx); 4091c32654afSNicholas Piggin translator_io_start(&ctx->base); 40927058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_STOP); 409321c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 409421c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 409521c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 409621c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4097cdee0e72SNikunj A Dadhania } 4098cdee0e72SNikunj A Dadhania 4099fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4100fcf5ef2aSThomas Huth { 4101fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41029f0cf041SMatheus Ferst GEN_PRIV(ctx); 4103fcf5ef2aSThomas Huth #else 4104fcf5ef2aSThomas Huth TCGv_i32 t; 4105fcf5ef2aSThomas Huth 41069f0cf041SMatheus Ferst CHK_HV(ctx); 4107c32654afSNicholas Piggin translator_io_start(&ctx->base); 41087058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_SLEEP); 4109fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4110154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4111154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4112fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4113fcf5ef2aSThomas Huth } 4114fcf5ef2aSThomas Huth 4115fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4116fcf5ef2aSThomas Huth { 4117fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41189f0cf041SMatheus Ferst GEN_PRIV(ctx); 4119fcf5ef2aSThomas Huth #else 4120fcf5ef2aSThomas Huth TCGv_i32 t; 4121fcf5ef2aSThomas Huth 41229f0cf041SMatheus Ferst CHK_HV(ctx); 4123c32654afSNicholas Piggin translator_io_start(&ctx->base); 41247058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_RVWINKLE); 4125fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4126154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4127154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4128fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4129fcf5ef2aSThomas Huth } 4130fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4131fcf5ef2aSThomas Huth 4132fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4133fcf5ef2aSThomas Huth { 4134fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4135efe843d8SDavid Gibson if (ctx->has_cfar) { 4136fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4137efe843d8SDavid Gibson } 4138fcf5ef2aSThomas Huth #endif 4139fcf5ef2aSThomas Huth } 4140fcf5ef2aSThomas Huth 414146d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 414246d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 414346d396bdSDaniel Henrique Barboza { 414446d396bdSDaniel Henrique Barboza /* 414546d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 414646d396bdSDaniel Henrique Barboza * instructions. 414746d396bdSDaniel Henrique Barboza */ 414846d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 414946d396bdSDaniel Henrique Barboza return; 415046d396bdSDaniel Henrique Barboza } 415146d396bdSDaniel Henrique Barboza 415246d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4153eeaaefe9SLeandro Lupori TCGLabel *l; 4154eeaaefe9SLeandro Lupori TCGv t0; 4155eeaaefe9SLeandro Lupori 415646d396bdSDaniel Henrique Barboza /* 415746d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 415846d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 415946d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 416046d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 416146d396bdSDaniel Henrique Barboza */ 4162283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 416346d396bdSDaniel Henrique Barboza 4164eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4165eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4166eeaaefe9SLeandro Lupori l = gen_new_label(); 4167eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4168eeaaefe9SLeandro Lupori 4169eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4170eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4171eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4172eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4173eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4174eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4175eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4176eeaaefe9SLeandro Lupori } 4177eeaaefe9SLeandro Lupori 4178eeaaefe9SLeandro Lupori gen_set_label(l); 4179eeaaefe9SLeandro Lupori } else { 418046d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4181eeaaefe9SLeandro Lupori } 418246d396bdSDaniel Henrique Barboza #else 418346d396bdSDaniel Henrique Barboza /* 418446d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 418546d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 418646d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 418746d396bdSDaniel Henrique Barboza */ 418846d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 418946d396bdSDaniel Henrique Barboza 419046d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 419146d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 419246d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 419346d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 419446d396bdSDaniel Henrique Barboza } 419546d396bdSDaniel Henrique Barboza #else 419646d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 419746d396bdSDaniel Henrique Barboza { 419846d396bdSDaniel Henrique Barboza return; 419946d396bdSDaniel Henrique Barboza } 420046d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 420146d396bdSDaniel Henrique Barboza 4202fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4203fcf5ef2aSThomas Huth { 42042e718e66SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 42052e718e66SRichard Henderson return false; 42062e718e66SRichard Henderson } 42076e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4208fcf5ef2aSThomas Huth } 4209fcf5ef2aSThomas Huth 42100e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 42110e3bf489SRoman Kapl { 42129498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 421314895384SNicholas Piggin gen_debug_exception(ctx, false); 42140e3bf489SRoman Kapl } else { 421546d396bdSDaniel Henrique Barboza /* 421646d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 421746d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 421846d396bdSDaniel Henrique Barboza */ 421946d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 422046d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 422146d396bdSDaniel Henrique Barboza } 422246d396bdSDaniel Henrique Barboza 42230e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 42240e3bf489SRoman Kapl } 42250e3bf489SRoman Kapl } 42260e3bf489SRoman Kapl 4227fcf5ef2aSThomas Huth /*** Branch ***/ 4228c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4229fcf5ef2aSThomas Huth { 4230fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4231fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4232fcf5ef2aSThomas Huth } 4233fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 423446d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4235fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4236fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 423707ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4238fcf5ef2aSThomas Huth } else { 4239fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 42400e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4241fcf5ef2aSThomas Huth } 4242fcf5ef2aSThomas Huth } 4243fcf5ef2aSThomas Huth 4244fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4245fcf5ef2aSThomas Huth { 4246fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4247fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4248fcf5ef2aSThomas Huth } 4249fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4250fcf5ef2aSThomas Huth } 4251fcf5ef2aSThomas Huth 4252fcf5ef2aSThomas Huth /* b ba bl bla */ 4253fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4254fcf5ef2aSThomas Huth { 4255fcf5ef2aSThomas Huth target_ulong li, target; 4256fcf5ef2aSThomas Huth 4257fcf5ef2aSThomas Huth /* sign extend LI */ 4258fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4259fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4260fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42612c2bcb1bSRichard Henderson target = ctx->cia + li; 4262fcf5ef2aSThomas Huth } else { 4263fcf5ef2aSThomas Huth target = li; 4264fcf5ef2aSThomas Huth } 4265fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4266b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4267fcf5ef2aSThomas Huth } 42682c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4269fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 42706086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4271fcf5ef2aSThomas Huth } 4272fcf5ef2aSThomas Huth 4273fcf5ef2aSThomas Huth #define BCOND_IM 0 4274fcf5ef2aSThomas Huth #define BCOND_LR 1 4275fcf5ef2aSThomas Huth #define BCOND_CTR 2 4276fcf5ef2aSThomas Huth #define BCOND_TAR 3 4277fcf5ef2aSThomas Huth 4278c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4279fcf5ef2aSThomas Huth { 4280fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4281fcf5ef2aSThomas Huth TCGLabel *l1; 4282fcf5ef2aSThomas Huth TCGv target; 42830e3bf489SRoman Kapl 4284fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 42859723281fSRichard Henderson target = tcg_temp_new(); 4286efe843d8SDavid Gibson if (type == BCOND_CTR) { 4287fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4288efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4289fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4290efe843d8SDavid Gibson } else { 4291fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4292efe843d8SDavid Gibson } 4293fcf5ef2aSThomas Huth } else { 4294f764718dSRichard Henderson target = NULL; 4295fcf5ef2aSThomas Huth } 4296efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4297b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4298efe843d8SDavid Gibson } 4299fcf5ef2aSThomas Huth l1 = gen_new_label(); 4300fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4301fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4302fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4303fa200c95SGreg Kurz 4304fa200c95SGreg Kurz if (type == BCOND_CTR) { 4305fa200c95SGreg Kurz /* 4306fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4307fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4308fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 430915d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 431015d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 431115d68c5eSGreg Kurz * it basically useless and thus never used in real code. 431215d68c5eSGreg Kurz * 431315d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 431415d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 431515d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 431615d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 431715d68c5eSGreg Kurz * doing anything else harmful. 4318fa200c95SGreg Kurz */ 4319d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4320fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4321fcf5ef2aSThomas Huth return; 4322fcf5ef2aSThomas Huth } 4323fa200c95SGreg Kurz 4324fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4325fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4326fa200c95SGreg Kurz } else { 4327fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4328fa200c95SGreg Kurz } 4329fa200c95SGreg Kurz if (bo & 0x2) { 4330fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4331fa200c95SGreg Kurz } else { 4332fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4333fa200c95SGreg Kurz } 4334fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4335fa200c95SGreg Kurz } else { 4336fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4337fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4338fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4339fcf5ef2aSThomas Huth } else { 4340fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4341fcf5ef2aSThomas Huth } 4342fcf5ef2aSThomas Huth if (bo & 0x2) { 4343fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4344fcf5ef2aSThomas Huth } else { 4345fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4346fcf5ef2aSThomas Huth } 4347fa200c95SGreg Kurz } 4348fcf5ef2aSThomas Huth } 4349fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4350fcf5ef2aSThomas Huth /* Test CR */ 4351fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4352fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4353fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4354fcf5ef2aSThomas Huth 4355fcf5ef2aSThomas Huth if (bo & 0x8) { 4356fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4357fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4358fcf5ef2aSThomas Huth } else { 4359fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4360fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4361fcf5ef2aSThomas Huth } 4362fcf5ef2aSThomas Huth } 43632c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4364fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4365fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4366fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43672c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4368fcf5ef2aSThomas Huth } else { 4369fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4370fcf5ef2aSThomas Huth } 4371fcf5ef2aSThomas Huth } else { 4372fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4373fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4374fcf5ef2aSThomas Huth } else { 4375fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4376fcf5ef2aSThomas Huth } 43770e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4378c4a2e3a9SRichard Henderson } 4379fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 43800e3bf489SRoman Kapl /* fallthrough case */ 4381fcf5ef2aSThomas Huth gen_set_label(l1); 4382b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4383fcf5ef2aSThomas Huth } 43846086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4385fcf5ef2aSThomas Huth } 4386fcf5ef2aSThomas Huth 4387fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4388fcf5ef2aSThomas Huth { 4389fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4390fcf5ef2aSThomas Huth } 4391fcf5ef2aSThomas Huth 4392fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4393fcf5ef2aSThomas Huth { 4394fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4395fcf5ef2aSThomas Huth } 4396fcf5ef2aSThomas Huth 4397fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4398fcf5ef2aSThomas Huth { 4399fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4400fcf5ef2aSThomas Huth } 4401fcf5ef2aSThomas Huth 4402fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4403fcf5ef2aSThomas Huth { 4404fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4405fcf5ef2aSThomas Huth } 4406fcf5ef2aSThomas Huth 4407fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4408fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4409fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4410fcf5ef2aSThomas Huth { \ 4411fcf5ef2aSThomas Huth uint8_t bitmask; \ 4412fcf5ef2aSThomas Huth int sh; \ 4413fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4414fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4415fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4416fcf5ef2aSThomas Huth if (sh > 0) \ 4417fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4418fcf5ef2aSThomas Huth else if (sh < 0) \ 4419fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4420fcf5ef2aSThomas Huth else \ 4421fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4422fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4423fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4424fcf5ef2aSThomas Huth if (sh > 0) \ 4425fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4426fcf5ef2aSThomas Huth else if (sh < 0) \ 4427fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4428fcf5ef2aSThomas Huth else \ 4429fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4430fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4431fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4432fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4433fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4434fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4435fcf5ef2aSThomas Huth } 4436fcf5ef2aSThomas Huth 4437fcf5ef2aSThomas Huth /* crand */ 4438fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4439fcf5ef2aSThomas Huth /* crandc */ 4440fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4441fcf5ef2aSThomas Huth /* creqv */ 4442fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4443fcf5ef2aSThomas Huth /* crnand */ 4444fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4445fcf5ef2aSThomas Huth /* crnor */ 4446fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4447fcf5ef2aSThomas Huth /* cror */ 4448fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4449fcf5ef2aSThomas Huth /* crorc */ 4450fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4451fcf5ef2aSThomas Huth /* crxor */ 4452fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4453fcf5ef2aSThomas Huth 4454fcf5ef2aSThomas Huth /* mcrf */ 4455fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4456fcf5ef2aSThomas Huth { 4457fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4458fcf5ef2aSThomas Huth } 4459fcf5ef2aSThomas Huth 4460fcf5ef2aSThomas Huth /*** System linkage ***/ 4461fcf5ef2aSThomas Huth 4462fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4463fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4464fcf5ef2aSThomas Huth { 4465fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44669f0cf041SMatheus Ferst GEN_PRIV(ctx); 4467fcf5ef2aSThomas Huth #else 4468efe843d8SDavid Gibson /* 4469efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4470fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4471fcf5ef2aSThomas Huth */ 4472d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4473fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4474fcf5ef2aSThomas Huth return; 4475fcf5ef2aSThomas Huth } 4476fcf5ef2aSThomas Huth /* Restore CPU state */ 44779f0cf041SMatheus Ferst CHK_SV(ctx); 4478283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44792c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4480fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 448159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4482fcf5ef2aSThomas Huth #endif 4483fcf5ef2aSThomas Huth } 4484fcf5ef2aSThomas Huth 4485fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4486fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4487fcf5ef2aSThomas Huth { 4488fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44899f0cf041SMatheus Ferst GEN_PRIV(ctx); 4490fcf5ef2aSThomas Huth #else 4491fcf5ef2aSThomas Huth /* Restore CPU state */ 44929f0cf041SMatheus Ferst CHK_SV(ctx); 4493283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44942c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4495fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 449659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4497fcf5ef2aSThomas Huth #endif 4498fcf5ef2aSThomas Huth } 4499fcf5ef2aSThomas Huth 45003c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45013c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 45023c89b8d6SNicholas Piggin { 45033c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 45049f0cf041SMatheus Ferst GEN_PRIV(ctx); 45053c89b8d6SNicholas Piggin #else 45063c89b8d6SNicholas Piggin /* Restore CPU state */ 45079f0cf041SMatheus Ferst CHK_SV(ctx); 4508283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 45092c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 45103c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 451159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 45123c89b8d6SNicholas Piggin #endif 45133c89b8d6SNicholas Piggin } 45143c89b8d6SNicholas Piggin #endif 45153c89b8d6SNicholas Piggin 4516fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4517fcf5ef2aSThomas Huth { 4518fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 45199f0cf041SMatheus Ferst GEN_PRIV(ctx); 4520fcf5ef2aSThomas Huth #else 4521fcf5ef2aSThomas Huth /* Restore CPU state */ 45229f0cf041SMatheus Ferst CHK_HV(ctx); 4523c32654afSNicholas Piggin translator_io_start(&ctx->base); 4524fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 452559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4526fcf5ef2aSThomas Huth #endif 4527fcf5ef2aSThomas Huth } 4528fcf5ef2aSThomas Huth #endif 4529fcf5ef2aSThomas Huth 4530fcf5ef2aSThomas Huth /* sc */ 4531fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4532fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4533fcf5ef2aSThomas Huth #else 4534fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4535fcf5ef2aSThomas Huth #endif 4536fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4537fcf5ef2aSThomas Huth { 4538fcf5ef2aSThomas Huth uint32_t lev; 4539fcf5ef2aSThomas Huth 4540984eda58SNicholas Piggin /* 4541984eda58SNicholas Piggin * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4542984eda58SNicholas Piggin * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4543984eda58SNicholas Piggin * for Ultravisor which TCG does not support, so just ignore the top 6. 4544984eda58SNicholas Piggin */ 4545984eda58SNicholas Piggin lev = (ctx->opcode >> 5) & 0x1; 4546fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4547fcf5ef2aSThomas Huth } 4548fcf5ef2aSThomas Huth 45493c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 45503c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45513c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 45523c89b8d6SNicholas Piggin { 4553f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 45543c89b8d6SNicholas Piggin 4555f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 45562c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4557f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 45583c89b8d6SNicholas Piggin 45597a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 45603c89b8d6SNicholas Piggin } 45613c89b8d6SNicholas Piggin #endif 45623c89b8d6SNicholas Piggin #endif 45633c89b8d6SNicholas Piggin 4564fcf5ef2aSThomas Huth /*** Trap ***/ 4565fcf5ef2aSThomas Huth 4566fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4567fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4568fcf5ef2aSThomas Huth { 4569fcf5ef2aSThomas Huth /* Trap never */ 4570fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4571fcf5ef2aSThomas Huth return true; 4572fcf5ef2aSThomas Huth } 4573fcf5ef2aSThomas Huth /* Trap always */ 4574fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4575fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4576fcf5ef2aSThomas Huth return true; 4577fcf5ef2aSThomas Huth } 4578fcf5ef2aSThomas Huth return false; 4579fcf5ef2aSThomas Huth } 4580fcf5ef2aSThomas Huth 4581fcf5ef2aSThomas Huth /* tw */ 4582fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4583fcf5ef2aSThomas Huth { 4584fcf5ef2aSThomas Huth TCGv_i32 t0; 4585fcf5ef2aSThomas Huth 4586fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4587fcf5ef2aSThomas Huth return; 4588fcf5ef2aSThomas Huth } 45897058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4590fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4591fcf5ef2aSThomas Huth t0); 4592fcf5ef2aSThomas Huth } 4593fcf5ef2aSThomas Huth 4594fcf5ef2aSThomas Huth /* twi */ 4595fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4596fcf5ef2aSThomas Huth { 4597fcf5ef2aSThomas Huth TCGv t0; 4598fcf5ef2aSThomas Huth TCGv_i32 t1; 4599fcf5ef2aSThomas Huth 4600fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4601fcf5ef2aSThomas Huth return; 4602fcf5ef2aSThomas Huth } 46037058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 46047058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4605fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4606fcf5ef2aSThomas Huth } 4607fcf5ef2aSThomas Huth 4608fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4609fcf5ef2aSThomas Huth /* td */ 4610fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4611fcf5ef2aSThomas Huth { 4612fcf5ef2aSThomas Huth TCGv_i32 t0; 4613fcf5ef2aSThomas Huth 4614fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4615fcf5ef2aSThomas Huth return; 4616fcf5ef2aSThomas Huth } 46177058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4618fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4619fcf5ef2aSThomas Huth t0); 4620fcf5ef2aSThomas Huth } 4621fcf5ef2aSThomas Huth 4622fcf5ef2aSThomas Huth /* tdi */ 4623fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4624fcf5ef2aSThomas Huth { 4625fcf5ef2aSThomas Huth TCGv t0; 4626fcf5ef2aSThomas Huth TCGv_i32 t1; 4627fcf5ef2aSThomas Huth 4628fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4629fcf5ef2aSThomas Huth return; 4630fcf5ef2aSThomas Huth } 46317058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 46327058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4633fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4634fcf5ef2aSThomas Huth } 4635fcf5ef2aSThomas Huth #endif 4636fcf5ef2aSThomas Huth 4637fcf5ef2aSThomas Huth /*** Processor control ***/ 4638fcf5ef2aSThomas Huth 4639fcf5ef2aSThomas Huth /* mcrxr */ 4640fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4641fcf5ef2aSThomas Huth { 4642fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4643fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4644fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4645fcf5ef2aSThomas Huth 4646fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4647fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4648fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4649fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4650fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4651fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4652fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4653fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4654fcf5ef2aSThomas Huth 4655fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4656fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4657fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4658fcf5ef2aSThomas Huth } 4659fcf5ef2aSThomas Huth 4660b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4661b63d0434SNikunj A Dadhania /* mcrxrx */ 4662b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4663b63d0434SNikunj A Dadhania { 4664b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4665b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4666b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4667b63d0434SNikunj A Dadhania 4668b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4669b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4670b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4671b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4672b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4673b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4674b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4675b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4676b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4677b63d0434SNikunj A Dadhania } 4678b63d0434SNikunj A Dadhania #endif 4679b63d0434SNikunj A Dadhania 4680fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4681fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4682fcf5ef2aSThomas Huth { 4683fcf5ef2aSThomas Huth uint32_t crm, crn; 4684fcf5ef2aSThomas Huth 4685fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4686fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4687fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4688fcf5ef2aSThomas Huth crn = ctz32(crm); 4689fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4690fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4691fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4692fcf5ef2aSThomas Huth } 4693fcf5ef2aSThomas Huth } else { 4694fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4695fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4696fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4697fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4698fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4699fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4700fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4701fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4702fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4703fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4704fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4705fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4706fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4707fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4708fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4709fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4710fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4711fcf5ef2aSThomas Huth } 4712fcf5ef2aSThomas Huth } 4713fcf5ef2aSThomas Huth 4714fcf5ef2aSThomas Huth /* mfmsr */ 4715fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4716fcf5ef2aSThomas Huth { 47179f0cf041SMatheus Ferst CHK_SV(ctx); 4718fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4719fcf5ef2aSThomas Huth } 4720fcf5ef2aSThomas Huth 4721fcf5ef2aSThomas Huth /* mfspr */ 4722fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4723fcf5ef2aSThomas Huth { 4724fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4725fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4726fcf5ef2aSThomas Huth 4727fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4728fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4729fcf5ef2aSThomas Huth #else 4730fcf5ef2aSThomas Huth if (ctx->pr) { 4731fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4732fcf5ef2aSThomas Huth } else if (ctx->hv) { 4733fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4734fcf5ef2aSThomas Huth } else { 4735fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4736fcf5ef2aSThomas Huth } 4737fcf5ef2aSThomas Huth #endif 4738fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4739fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4740fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4741fcf5ef2aSThomas Huth } else { 4742fcf5ef2aSThomas Huth /* Privilege exception */ 4743efe843d8SDavid Gibson /* 4744efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4745fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4746fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4747fcf5ef2aSThomas Huth */ 4748fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 474931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 475031085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 47512c2bcb1bSRichard Henderson ctx->cia); 4752fcf5ef2aSThomas Huth } 4753fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4754fcf5ef2aSThomas Huth } 4755fcf5ef2aSThomas Huth } else { 4756fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4757fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4758fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4759fcf5ef2aSThomas Huth /* This is a nop */ 4760fcf5ef2aSThomas Huth return; 4761fcf5ef2aSThomas Huth } 4762fcf5ef2aSThomas Huth /* Not defined */ 476331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 476431085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 47652c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4766fcf5ef2aSThomas Huth 4767efe843d8SDavid Gibson /* 4768efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4769efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4770fcf5ef2aSThomas Huth */ 4771fcf5ef2aSThomas Huth if (sprn & 0x10) { 4772fcf5ef2aSThomas Huth if (ctx->pr) { 47731315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4774fcf5ef2aSThomas Huth } 4775fcf5ef2aSThomas Huth } else { 4776fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 47771315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4778fcf5ef2aSThomas Huth } 4779fcf5ef2aSThomas Huth } 4780fcf5ef2aSThomas Huth } 4781fcf5ef2aSThomas Huth } 4782fcf5ef2aSThomas Huth 4783fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4784fcf5ef2aSThomas Huth { 4785fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4786fcf5ef2aSThomas Huth } 4787fcf5ef2aSThomas Huth 4788fcf5ef2aSThomas Huth /* mftb */ 4789fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4790fcf5ef2aSThomas Huth { 4791fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4792fcf5ef2aSThomas Huth } 4793fcf5ef2aSThomas Huth 4794fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4795fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4796fcf5ef2aSThomas Huth { 4797fcf5ef2aSThomas Huth uint32_t crm, crn; 4798fcf5ef2aSThomas Huth 4799fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4800fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4801fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4802fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4803fcf5ef2aSThomas Huth crn = ctz32(crm); 4804fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4805fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4806fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4807fcf5ef2aSThomas Huth } 4808fcf5ef2aSThomas Huth } else { 4809fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4810fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4811fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4812fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4813fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4814fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4815fcf5ef2aSThomas Huth } 4816fcf5ef2aSThomas Huth } 4817fcf5ef2aSThomas Huth } 4818fcf5ef2aSThomas Huth } 4819fcf5ef2aSThomas Huth 4820fcf5ef2aSThomas Huth /* mtmsr */ 4821fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4822fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4823fcf5ef2aSThomas Huth { 4824caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4825caf590ddSNicholas Piggin gen_invalid(ctx); 4826caf590ddSNicholas Piggin return; 4827caf590ddSNicholas Piggin } 4828caf590ddSNicholas Piggin 48299f0cf041SMatheus Ferst CHK_SV(ctx); 4830fcf5ef2aSThomas Huth 4831fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48326fa5726bSMatheus Ferst TCGv t0, t1; 48336fa5726bSMatheus Ferst target_ulong mask; 48346fa5726bSMatheus Ferst 48356fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48366fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48376fa5726bSMatheus Ferst 4838283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 48396fa5726bSMatheus Ferst 4840fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48415ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48426fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4843fcf5ef2aSThomas Huth } else { 48446fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 48456fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 48466fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4847efe843d8SDavid Gibson /* 4848efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4849efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4850efe843d8SDavid Gibson * ppc_store_msr 4851fcf5ef2aSThomas Huth */ 4852b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4853fcf5ef2aSThomas Huth } 48546fa5726bSMatheus Ferst 48556fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48566fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48576fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48586fa5726bSMatheus Ferst 48596fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48606fa5726bSMatheus Ferst 48615ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4862d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4863fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4864fcf5ef2aSThomas Huth } 4865fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4866fcf5ef2aSThomas Huth 4867fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4868fcf5ef2aSThomas Huth { 48699f0cf041SMatheus Ferst CHK_SV(ctx); 4870fcf5ef2aSThomas Huth 4871fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48726fa5726bSMatheus Ferst TCGv t0, t1; 48736fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 48746fa5726bSMatheus Ferst 48756fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48766fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48776fa5726bSMatheus Ferst 4878283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 4879fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48805ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48816fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4882fcf5ef2aSThomas Huth } else { 48836fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 48846fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4885fcf5ef2aSThomas Huth 4886efe843d8SDavid Gibson /* 4887efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4888efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4889efe843d8SDavid Gibson * ppc_store_msr 4890fcf5ef2aSThomas Huth */ 4891b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4892fcf5ef2aSThomas Huth } 48936fa5726bSMatheus Ferst 48946fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48956fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48966fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48976fa5726bSMatheus Ferst 48986fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48996fa5726bSMatheus Ferst 49005ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4901d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4902fcf5ef2aSThomas Huth #endif 4903fcf5ef2aSThomas Huth } 4904fcf5ef2aSThomas Huth 4905fcf5ef2aSThomas Huth /* mtspr */ 4906fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4907fcf5ef2aSThomas Huth { 4908fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4909fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4910fcf5ef2aSThomas Huth 4911fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4912fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4913fcf5ef2aSThomas Huth #else 4914fcf5ef2aSThomas Huth if (ctx->pr) { 4915fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4916fcf5ef2aSThomas Huth } else if (ctx->hv) { 4917fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4918fcf5ef2aSThomas Huth } else { 4919fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4920fcf5ef2aSThomas Huth } 4921fcf5ef2aSThomas Huth #endif 4922fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4923fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4924fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4925fcf5ef2aSThomas Huth } else { 4926fcf5ef2aSThomas Huth /* Privilege exception */ 492731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 492831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 49292c2bcb1bSRichard Henderson ctx->cia); 4930fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4931fcf5ef2aSThomas Huth } 4932fcf5ef2aSThomas Huth } else { 4933fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4934fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4935fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4936fcf5ef2aSThomas Huth /* This is a nop */ 4937fcf5ef2aSThomas Huth return; 4938fcf5ef2aSThomas Huth } 4939fcf5ef2aSThomas Huth 4940fcf5ef2aSThomas Huth /* Not defined */ 494131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 494231085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 49432c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4944fcf5ef2aSThomas Huth 4945fcf5ef2aSThomas Huth 4946efe843d8SDavid Gibson /* 4947efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4948efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4949fcf5ef2aSThomas Huth */ 4950fcf5ef2aSThomas Huth if (sprn & 0x10) { 4951fcf5ef2aSThomas Huth if (ctx->pr) { 49521315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4953fcf5ef2aSThomas Huth } 4954fcf5ef2aSThomas Huth } else { 4955fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 49561315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4957fcf5ef2aSThomas Huth } 4958fcf5ef2aSThomas Huth } 4959fcf5ef2aSThomas Huth } 4960fcf5ef2aSThomas Huth } 4961fcf5ef2aSThomas Huth 4962fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4963fcf5ef2aSThomas Huth /* setb */ 4964fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4965fcf5ef2aSThomas Huth { 4966fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 49676f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 49686f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 4969fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4970fcf5ef2aSThomas Huth 4971fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4972fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4973fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4974fcf5ef2aSThomas Huth } 4975fcf5ef2aSThomas Huth #endif 4976fcf5ef2aSThomas Huth 4977fcf5ef2aSThomas Huth /*** Cache management ***/ 4978fcf5ef2aSThomas Huth 4979fcf5ef2aSThomas Huth /* dcbf */ 4980fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4981fcf5ef2aSThomas Huth { 4982fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4983fcf5ef2aSThomas Huth TCGv t0; 4984fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4985fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4986fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4987fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4988fcf5ef2aSThomas Huth } 4989fcf5ef2aSThomas Huth 499050728199SRoman Kapl /* dcbfep (external PID dcbf) */ 499150728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 499250728199SRoman Kapl { 499350728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 499450728199SRoman Kapl TCGv t0; 49959f0cf041SMatheus Ferst CHK_SV(ctx); 499650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 499750728199SRoman Kapl t0 = tcg_temp_new(); 499850728199SRoman Kapl gen_addr_reg_index(ctx, t0); 499950728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 500050728199SRoman Kapl } 500150728199SRoman Kapl 5002fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5003fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5004fcf5ef2aSThomas Huth { 5005fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 50069f0cf041SMatheus Ferst GEN_PRIV(ctx); 5007fcf5ef2aSThomas Huth #else 5008fcf5ef2aSThomas Huth TCGv EA, val; 5009fcf5ef2aSThomas Huth 50109f0cf041SMatheus Ferst CHK_SV(ctx); 5011fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5012fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5013fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5014fcf5ef2aSThomas Huth val = tcg_temp_new(); 5015fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5016fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5017fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5018fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5019fcf5ef2aSThomas Huth } 5020fcf5ef2aSThomas Huth 5021fcf5ef2aSThomas Huth /* dcdst */ 5022fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5023fcf5ef2aSThomas Huth { 5024fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5025fcf5ef2aSThomas Huth TCGv t0; 5026fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5027fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5028fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5029fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5030fcf5ef2aSThomas Huth } 5031fcf5ef2aSThomas Huth 503250728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 503350728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 503450728199SRoman Kapl { 503550728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 503650728199SRoman Kapl TCGv t0; 503750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 503850728199SRoman Kapl t0 = tcg_temp_new(); 503950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 504050728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 504150728199SRoman Kapl } 504250728199SRoman Kapl 5043fcf5ef2aSThomas Huth /* dcbt */ 5044fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5045fcf5ef2aSThomas Huth { 5046efe843d8SDavid Gibson /* 5047efe843d8SDavid Gibson * interpreted as no-op 5048efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5049efe843d8SDavid Gibson * does not generate any exception 5050fcf5ef2aSThomas Huth */ 5051fcf5ef2aSThomas Huth } 5052fcf5ef2aSThomas Huth 505350728199SRoman Kapl /* dcbtep */ 505450728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 505550728199SRoman Kapl { 5056efe843d8SDavid Gibson /* 5057efe843d8SDavid Gibson * interpreted as no-op 5058efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5059efe843d8SDavid Gibson * does not generate any exception 506050728199SRoman Kapl */ 506150728199SRoman Kapl } 506250728199SRoman Kapl 5063fcf5ef2aSThomas Huth /* dcbtst */ 5064fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5065fcf5ef2aSThomas Huth { 5066efe843d8SDavid Gibson /* 5067efe843d8SDavid Gibson * interpreted as no-op 5068efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5069efe843d8SDavid Gibson * does not generate any exception 5070fcf5ef2aSThomas Huth */ 5071fcf5ef2aSThomas Huth } 5072fcf5ef2aSThomas Huth 507350728199SRoman Kapl /* dcbtstep */ 507450728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 507550728199SRoman Kapl { 5076efe843d8SDavid Gibson /* 5077efe843d8SDavid Gibson * interpreted as no-op 5078efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5079efe843d8SDavid Gibson * does not generate any exception 508050728199SRoman Kapl */ 508150728199SRoman Kapl } 508250728199SRoman Kapl 5083fcf5ef2aSThomas Huth /* dcbtls */ 5084fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5085fcf5ef2aSThomas Huth { 5086fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5087fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5088fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5089fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5090fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5091fcf5ef2aSThomas Huth } 5092fcf5ef2aSThomas Huth 5093e64645baSBernhard Beschow /* dcblc */ 5094e64645baSBernhard Beschow static void gen_dcblc(DisasContext *ctx) 5095e64645baSBernhard Beschow { 5096e64645baSBernhard Beschow /* 5097e64645baSBernhard Beschow * interpreted as no-op 5098e64645baSBernhard Beschow */ 5099e64645baSBernhard Beschow } 5100e64645baSBernhard Beschow 5101fcf5ef2aSThomas Huth /* dcbz */ 5102fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5103fcf5ef2aSThomas Huth { 5104fcf5ef2aSThomas Huth TCGv tcgv_addr; 5105fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5106fcf5ef2aSThomas Huth 5107fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5108fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 51097058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5110fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5111fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5112fcf5ef2aSThomas Huth } 5113fcf5ef2aSThomas Huth 511450728199SRoman Kapl /* dcbzep */ 511550728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 511650728199SRoman Kapl { 511750728199SRoman Kapl TCGv tcgv_addr; 511850728199SRoman Kapl TCGv_i32 tcgv_op; 511950728199SRoman Kapl 512050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 512150728199SRoman Kapl tcgv_addr = tcg_temp_new(); 51227058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 512350728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 512450728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 512550728199SRoman Kapl } 512650728199SRoman Kapl 5127fcf5ef2aSThomas Huth /* dst / dstt */ 5128fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5129fcf5ef2aSThomas Huth { 5130fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5131fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5132fcf5ef2aSThomas Huth } else { 5133fcf5ef2aSThomas Huth /* interpreted as no-op */ 5134fcf5ef2aSThomas Huth } 5135fcf5ef2aSThomas Huth } 5136fcf5ef2aSThomas Huth 5137fcf5ef2aSThomas Huth /* dstst /dststt */ 5138fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5139fcf5ef2aSThomas Huth { 5140fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5141fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5142fcf5ef2aSThomas Huth } else { 5143fcf5ef2aSThomas Huth /* interpreted as no-op */ 5144fcf5ef2aSThomas Huth } 5145fcf5ef2aSThomas Huth 5146fcf5ef2aSThomas Huth } 5147fcf5ef2aSThomas Huth 5148fcf5ef2aSThomas Huth /* dss / dssall */ 5149fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5150fcf5ef2aSThomas Huth { 5151fcf5ef2aSThomas Huth /* interpreted as no-op */ 5152fcf5ef2aSThomas Huth } 5153fcf5ef2aSThomas Huth 5154fcf5ef2aSThomas Huth /* icbi */ 5155fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5156fcf5ef2aSThomas Huth { 5157fcf5ef2aSThomas Huth TCGv t0; 5158fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5159fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5160fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5161fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5162fcf5ef2aSThomas Huth } 5163fcf5ef2aSThomas Huth 516450728199SRoman Kapl /* icbiep */ 516550728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 516650728199SRoman Kapl { 516750728199SRoman Kapl TCGv t0; 516850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 516950728199SRoman Kapl t0 = tcg_temp_new(); 517050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 517150728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 517250728199SRoman Kapl } 517350728199SRoman Kapl 5174fcf5ef2aSThomas Huth /* Optional: */ 5175fcf5ef2aSThomas Huth /* dcba */ 5176fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5177fcf5ef2aSThomas Huth { 5178efe843d8SDavid Gibson /* 5179efe843d8SDavid Gibson * interpreted as no-op 5180efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5181fcf5ef2aSThomas Huth * but does not generate any exception 5182fcf5ef2aSThomas Huth */ 5183fcf5ef2aSThomas Huth } 5184fcf5ef2aSThomas Huth 5185fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5186fcf5ef2aSThomas Huth /* Supervisor only: */ 5187fcf5ef2aSThomas Huth 5188fcf5ef2aSThomas Huth /* mfsr */ 5189fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5190fcf5ef2aSThomas Huth { 5191fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51929f0cf041SMatheus Ferst GEN_PRIV(ctx); 5193fcf5ef2aSThomas Huth #else 5194fcf5ef2aSThomas Huth TCGv t0; 5195fcf5ef2aSThomas Huth 51969f0cf041SMatheus Ferst CHK_SV(ctx); 51977058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5198fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5199fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5200fcf5ef2aSThomas Huth } 5201fcf5ef2aSThomas Huth 5202fcf5ef2aSThomas Huth /* mfsrin */ 5203fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5204fcf5ef2aSThomas Huth { 5205fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52069f0cf041SMatheus Ferst GEN_PRIV(ctx); 5207fcf5ef2aSThomas Huth #else 5208fcf5ef2aSThomas Huth TCGv t0; 5209fcf5ef2aSThomas Huth 52109f0cf041SMatheus Ferst CHK_SV(ctx); 5211fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5212e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5213fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5214fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5215fcf5ef2aSThomas Huth } 5216fcf5ef2aSThomas Huth 5217fcf5ef2aSThomas Huth /* mtsr */ 5218fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5219fcf5ef2aSThomas Huth { 5220fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52219f0cf041SMatheus Ferst GEN_PRIV(ctx); 5222fcf5ef2aSThomas Huth #else 5223fcf5ef2aSThomas Huth TCGv t0; 5224fcf5ef2aSThomas Huth 52259f0cf041SMatheus Ferst CHK_SV(ctx); 52267058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5227fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5228fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5229fcf5ef2aSThomas Huth } 5230fcf5ef2aSThomas Huth 5231fcf5ef2aSThomas Huth /* mtsrin */ 5232fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5233fcf5ef2aSThomas Huth { 5234fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52359f0cf041SMatheus Ferst GEN_PRIV(ctx); 5236fcf5ef2aSThomas Huth #else 5237fcf5ef2aSThomas Huth TCGv t0; 52389f0cf041SMatheus Ferst CHK_SV(ctx); 5239fcf5ef2aSThomas Huth 5240fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5241e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5242fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5243fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5244fcf5ef2aSThomas Huth } 5245fcf5ef2aSThomas Huth 5246fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5247fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5248fcf5ef2aSThomas Huth 5249fcf5ef2aSThomas Huth /* mfsr */ 5250fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5251fcf5ef2aSThomas Huth { 5252fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52539f0cf041SMatheus Ferst GEN_PRIV(ctx); 5254fcf5ef2aSThomas Huth #else 5255fcf5ef2aSThomas Huth TCGv t0; 5256fcf5ef2aSThomas Huth 52579f0cf041SMatheus Ferst CHK_SV(ctx); 52587058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5259fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5260fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5261fcf5ef2aSThomas Huth } 5262fcf5ef2aSThomas Huth 5263fcf5ef2aSThomas Huth /* mfsrin */ 5264fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5265fcf5ef2aSThomas Huth { 5266fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52679f0cf041SMatheus Ferst GEN_PRIV(ctx); 5268fcf5ef2aSThomas Huth #else 5269fcf5ef2aSThomas Huth TCGv t0; 5270fcf5ef2aSThomas Huth 52719f0cf041SMatheus Ferst CHK_SV(ctx); 5272fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5273e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5274fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5275fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5276fcf5ef2aSThomas Huth } 5277fcf5ef2aSThomas Huth 5278fcf5ef2aSThomas Huth /* mtsr */ 5279fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5280fcf5ef2aSThomas Huth { 5281fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52829f0cf041SMatheus Ferst GEN_PRIV(ctx); 5283fcf5ef2aSThomas Huth #else 5284fcf5ef2aSThomas Huth TCGv t0; 5285fcf5ef2aSThomas Huth 52869f0cf041SMatheus Ferst CHK_SV(ctx); 52877058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5288fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5289fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5290fcf5ef2aSThomas Huth } 5291fcf5ef2aSThomas Huth 5292fcf5ef2aSThomas Huth /* mtsrin */ 5293fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5294fcf5ef2aSThomas Huth { 5295fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52969f0cf041SMatheus Ferst GEN_PRIV(ctx); 5297fcf5ef2aSThomas Huth #else 5298fcf5ef2aSThomas Huth TCGv t0; 5299fcf5ef2aSThomas Huth 53009f0cf041SMatheus Ferst CHK_SV(ctx); 5301fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5302e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5303fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5304fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5305fcf5ef2aSThomas Huth } 5306fcf5ef2aSThomas Huth 5307fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5308fcf5ef2aSThomas Huth 5309fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5310fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5311fcf5ef2aSThomas Huth 5312fcf5ef2aSThomas Huth /* tlbia */ 5313fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5314fcf5ef2aSThomas Huth { 5315fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53169f0cf041SMatheus Ferst GEN_PRIV(ctx); 5317fcf5ef2aSThomas Huth #else 53189f0cf041SMatheus Ferst CHK_HV(ctx); 5319fcf5ef2aSThomas Huth 5320fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5321fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5322fcf5ef2aSThomas Huth } 5323fcf5ef2aSThomas Huth 5324fcf5ef2aSThomas Huth /* tlbsync */ 5325fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5326fcf5ef2aSThomas Huth { 5327fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53289f0cf041SMatheus Ferst GEN_PRIV(ctx); 5329fcf5ef2aSThomas Huth #else 533091c60f12SCédric Le Goater 533191c60f12SCédric Le Goater if (ctx->gtse) { 53329f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 533391c60f12SCédric Le Goater } else { 53349f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 533591c60f12SCédric Le Goater } 5336fcf5ef2aSThomas Huth 5337fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5338fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5339fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5340fcf5ef2aSThomas Huth } 5341fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5342fcf5ef2aSThomas Huth } 5343fcf5ef2aSThomas Huth 5344fcf5ef2aSThomas Huth /*** External control ***/ 5345fcf5ef2aSThomas Huth /* Optional: */ 5346fcf5ef2aSThomas Huth 5347fcf5ef2aSThomas Huth /* eciwx */ 5348fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5349fcf5ef2aSThomas Huth { 5350fcf5ef2aSThomas Huth TCGv t0; 5351fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5352fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5353fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5354fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5355c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5356c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5357fcf5ef2aSThomas Huth } 5358fcf5ef2aSThomas Huth 5359fcf5ef2aSThomas Huth /* ecowx */ 5360fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5361fcf5ef2aSThomas Huth { 5362fcf5ef2aSThomas Huth TCGv t0; 5363fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5364fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5365fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5366fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5367c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5368c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5369fcf5ef2aSThomas Huth } 5370fcf5ef2aSThomas Huth 5371fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5372fcf5ef2aSThomas Huth 5373fcf5ef2aSThomas Huth /* tlbld */ 5374fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5375fcf5ef2aSThomas Huth { 5376fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53779f0cf041SMatheus Ferst GEN_PRIV(ctx); 5378fcf5ef2aSThomas Huth #else 53799f0cf041SMatheus Ferst CHK_SV(ctx); 5380fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5381fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5382fcf5ef2aSThomas Huth } 5383fcf5ef2aSThomas Huth 5384fcf5ef2aSThomas Huth /* tlbli */ 5385fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5386fcf5ef2aSThomas Huth { 5387fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53889f0cf041SMatheus Ferst GEN_PRIV(ctx); 5389fcf5ef2aSThomas Huth #else 53909f0cf041SMatheus Ferst CHK_SV(ctx); 5391fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5392fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5393fcf5ef2aSThomas Huth } 5394fcf5ef2aSThomas Huth 5395fcf5ef2aSThomas Huth /* BookE specific instructions */ 5396fcf5ef2aSThomas Huth 5397fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5398fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5399fcf5ef2aSThomas Huth { 5400fcf5ef2aSThomas Huth /* XXX: TODO */ 5401fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5402fcf5ef2aSThomas Huth } 5403fcf5ef2aSThomas Huth 5404fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5405fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5406fcf5ef2aSThomas Huth { 5407fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54089f0cf041SMatheus Ferst GEN_PRIV(ctx); 5409fcf5ef2aSThomas Huth #else 5410fcf5ef2aSThomas Huth TCGv t0; 5411fcf5ef2aSThomas Huth 54129f0cf041SMatheus Ferst CHK_SV(ctx); 5413fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5414fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5415fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5416fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5417fcf5ef2aSThomas Huth } 5418fcf5ef2aSThomas Huth 5419fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5420fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5421fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5422fcf5ef2aSThomas Huth { 5423fcf5ef2aSThomas Huth TCGv t0, t1; 5424fcf5ef2aSThomas Huth 54259723281fSRichard Henderson t0 = tcg_temp_new(); 54269723281fSRichard Henderson t1 = tcg_temp_new(); 5427fcf5ef2aSThomas Huth 5428fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5429fcf5ef2aSThomas Huth case 0x05: 5430fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5431fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5432fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5433fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5434fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5435fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5436fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5437fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5438fcf5ef2aSThomas Huth break; 5439fcf5ef2aSThomas Huth case 0x04: 5440fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5441fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5442fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5443fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5444fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5445fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5446fcf5ef2aSThomas Huth break; 5447fcf5ef2aSThomas Huth case 0x01: 5448fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5449fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5450fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5451fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5452fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5453fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5454fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5455fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5456fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5457fcf5ef2aSThomas Huth break; 5458fcf5ef2aSThomas Huth case 0x00: 5459fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5460fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5461fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5462fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5463fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5464fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5465fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5466fcf5ef2aSThomas Huth break; 5467fcf5ef2aSThomas Huth case 0x0D: 5468fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5469fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5470fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5471fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5472fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5473fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5474fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5475fcf5ef2aSThomas Huth break; 5476fcf5ef2aSThomas Huth case 0x0C: 5477fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5478fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5479fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5480fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5481fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5482fcf5ef2aSThomas Huth break; 5483fcf5ef2aSThomas Huth } 5484fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5485fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5486fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5487fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5488fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5489fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5490fcf5ef2aSThomas Huth } else { 5491fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5492fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5493fcf5ef2aSThomas Huth } 5494fcf5ef2aSThomas Huth 5495fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5496fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5497fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5498fcf5ef2aSThomas Huth 5499fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5500fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5501fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5502fcf5ef2aSThomas Huth } 5503fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5504fcf5ef2aSThomas Huth /* Signed */ 5505fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5506fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5507fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5508fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5509fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5510fcf5ef2aSThomas Huth /* Saturate */ 5511fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5512fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5513fcf5ef2aSThomas Huth } 5514fcf5ef2aSThomas Huth } else { 5515fcf5ef2aSThomas Huth /* Unsigned */ 5516fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5517fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5518fcf5ef2aSThomas Huth /* Saturate */ 5519fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5520fcf5ef2aSThomas Huth } 5521fcf5ef2aSThomas Huth } 5522fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5523fcf5ef2aSThomas Huth /* Check overflow */ 5524fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5525fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5526fcf5ef2aSThomas Huth } 5527fcf5ef2aSThomas Huth gen_set_label(l1); 5528fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5529fcf5ef2aSThomas Huth } 5530fcf5ef2aSThomas Huth } else { 5531fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5532fcf5ef2aSThomas Huth } 5533fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5534fcf5ef2aSThomas Huth /* Update Rc0 */ 5535fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5536fcf5ef2aSThomas Huth } 5537fcf5ef2aSThomas Huth } 5538fcf5ef2aSThomas Huth 5539fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5540fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5541fcf5ef2aSThomas Huth { \ 5542fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5543fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5544fcf5ef2aSThomas Huth } 5545fcf5ef2aSThomas Huth 5546fcf5ef2aSThomas Huth /* macchw - macchw. */ 5547fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5548fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5550fcf5ef2aSThomas Huth /* macchws - macchws. */ 5551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5552fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5554fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5556fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5558fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5560fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5562fcf5ef2aSThomas Huth /* machhw - machhw. */ 5563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5564fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5566fcf5ef2aSThomas Huth /* machhws - machhws. */ 5567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5568fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5570fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5572fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5574fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5576fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5578fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5580fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5582fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5583fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5584fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5585fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5586fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5587fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5588fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5589fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5590fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5591fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5592fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5593fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5594fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5595fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5596fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5597fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5598fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5599fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5600fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5601fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5602fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5603fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5604fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5605fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5606fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5607fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5608fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5609fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5610fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5611fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5612fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5613fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5614fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5615fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5616fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5617fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5618fcf5ef2aSThomas Huth 5619fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5620fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5621fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5622fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5623fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5624fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5625fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5626fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5627fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5628fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5629fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5630fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5631fcf5ef2aSThomas Huth 5632fcf5ef2aSThomas Huth /* mfdcr */ 5633fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5634fcf5ef2aSThomas Huth { 5635fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56369f0cf041SMatheus Ferst GEN_PRIV(ctx); 5637fcf5ef2aSThomas Huth #else 5638fcf5ef2aSThomas Huth TCGv dcrn; 5639fcf5ef2aSThomas Huth 56409f0cf041SMatheus Ferst CHK_SV(ctx); 56417058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5642fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5643fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5644fcf5ef2aSThomas Huth } 5645fcf5ef2aSThomas Huth 5646fcf5ef2aSThomas Huth /* mtdcr */ 5647fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5648fcf5ef2aSThomas Huth { 5649fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56509f0cf041SMatheus Ferst GEN_PRIV(ctx); 5651fcf5ef2aSThomas Huth #else 5652fcf5ef2aSThomas Huth TCGv dcrn; 5653fcf5ef2aSThomas Huth 56549f0cf041SMatheus Ferst CHK_SV(ctx); 56557058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5656fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5657fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5658fcf5ef2aSThomas Huth } 5659fcf5ef2aSThomas Huth 5660fcf5ef2aSThomas Huth /* mfdcrx */ 5661fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5662fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5663fcf5ef2aSThomas Huth { 5664fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56659f0cf041SMatheus Ferst GEN_PRIV(ctx); 5666fcf5ef2aSThomas Huth #else 56679f0cf041SMatheus Ferst CHK_SV(ctx); 5668fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5669fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5670fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5671fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5672fcf5ef2aSThomas Huth } 5673fcf5ef2aSThomas Huth 5674fcf5ef2aSThomas Huth /* mtdcrx */ 5675fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5676fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5677fcf5ef2aSThomas Huth { 5678fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56799f0cf041SMatheus Ferst GEN_PRIV(ctx); 5680fcf5ef2aSThomas Huth #else 56819f0cf041SMatheus Ferst CHK_SV(ctx); 5682fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5683fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5684fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5685fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5686fcf5ef2aSThomas Huth } 5687fcf5ef2aSThomas Huth 5688fcf5ef2aSThomas Huth /* dccci */ 5689fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5690fcf5ef2aSThomas Huth { 56919f0cf041SMatheus Ferst CHK_SV(ctx); 5692fcf5ef2aSThomas Huth /* interpreted as no-op */ 5693fcf5ef2aSThomas Huth } 5694fcf5ef2aSThomas Huth 5695fcf5ef2aSThomas Huth /* dcread */ 5696fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5697fcf5ef2aSThomas Huth { 5698fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56999f0cf041SMatheus Ferst GEN_PRIV(ctx); 5700fcf5ef2aSThomas Huth #else 5701fcf5ef2aSThomas Huth TCGv EA, val; 5702fcf5ef2aSThomas Huth 57039f0cf041SMatheus Ferst CHK_SV(ctx); 5704fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5705fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5706fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5707fcf5ef2aSThomas Huth val = tcg_temp_new(); 5708fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5709fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5710fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5711fcf5ef2aSThomas Huth } 5712fcf5ef2aSThomas Huth 5713fcf5ef2aSThomas Huth /* icbt */ 5714fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5715fcf5ef2aSThomas Huth { 5716efe843d8SDavid Gibson /* 5717efe843d8SDavid Gibson * interpreted as no-op 5718efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5719efe843d8SDavid Gibson * does not generate any exception 5720fcf5ef2aSThomas Huth */ 5721fcf5ef2aSThomas Huth } 5722fcf5ef2aSThomas Huth 5723fcf5ef2aSThomas Huth /* iccci */ 5724fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5725fcf5ef2aSThomas Huth { 57269f0cf041SMatheus Ferst CHK_SV(ctx); 5727fcf5ef2aSThomas Huth /* interpreted as no-op */ 5728fcf5ef2aSThomas Huth } 5729fcf5ef2aSThomas Huth 5730fcf5ef2aSThomas Huth /* icread */ 5731fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5732fcf5ef2aSThomas Huth { 57339f0cf041SMatheus Ferst CHK_SV(ctx); 5734fcf5ef2aSThomas Huth /* interpreted as no-op */ 5735fcf5ef2aSThomas Huth } 5736fcf5ef2aSThomas Huth 5737fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5738fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5739fcf5ef2aSThomas Huth { 5740fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57419f0cf041SMatheus Ferst GEN_PRIV(ctx); 5742fcf5ef2aSThomas Huth #else 57439f0cf041SMatheus Ferst CHK_SV(ctx); 5744fcf5ef2aSThomas Huth /* Restore CPU state */ 5745fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 574659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5747fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5748fcf5ef2aSThomas Huth } 5749fcf5ef2aSThomas Huth 5750fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5751fcf5ef2aSThomas Huth { 5752fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57539f0cf041SMatheus Ferst GEN_PRIV(ctx); 5754fcf5ef2aSThomas Huth #else 57559f0cf041SMatheus Ferst CHK_SV(ctx); 5756fcf5ef2aSThomas Huth /* Restore CPU state */ 5757fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 575859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5759fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5760fcf5ef2aSThomas Huth } 5761fcf5ef2aSThomas Huth 5762fcf5ef2aSThomas Huth /* BookE specific */ 5763fcf5ef2aSThomas Huth 5764fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5765fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5766fcf5ef2aSThomas Huth { 5767fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57689f0cf041SMatheus Ferst GEN_PRIV(ctx); 5769fcf5ef2aSThomas Huth #else 57709f0cf041SMatheus Ferst CHK_SV(ctx); 5771fcf5ef2aSThomas Huth /* Restore CPU state */ 5772fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 577359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5774fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5775fcf5ef2aSThomas Huth } 5776fcf5ef2aSThomas Huth 5777fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5778fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5779fcf5ef2aSThomas Huth { 5780fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57819f0cf041SMatheus Ferst GEN_PRIV(ctx); 5782fcf5ef2aSThomas Huth #else 57839f0cf041SMatheus Ferst CHK_SV(ctx); 5784fcf5ef2aSThomas Huth /* Restore CPU state */ 5785fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 578659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5787fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5788fcf5ef2aSThomas Huth } 5789fcf5ef2aSThomas Huth 5790fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5791fcf5ef2aSThomas Huth 5792fcf5ef2aSThomas Huth /* tlbre */ 5793fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5794fcf5ef2aSThomas Huth { 5795fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57969f0cf041SMatheus Ferst GEN_PRIV(ctx); 5797fcf5ef2aSThomas Huth #else 57989f0cf041SMatheus Ferst CHK_SV(ctx); 5799fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5800fcf5ef2aSThomas Huth case 0: 5801fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5802fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5803fcf5ef2aSThomas Huth break; 5804fcf5ef2aSThomas Huth case 1: 5805fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5806fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5807fcf5ef2aSThomas Huth break; 5808fcf5ef2aSThomas Huth default: 5809fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5810fcf5ef2aSThomas Huth break; 5811fcf5ef2aSThomas Huth } 5812fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5813fcf5ef2aSThomas Huth } 5814fcf5ef2aSThomas Huth 5815fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5816fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5817fcf5ef2aSThomas Huth { 5818fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58199f0cf041SMatheus Ferst GEN_PRIV(ctx); 5820fcf5ef2aSThomas Huth #else 5821fcf5ef2aSThomas Huth TCGv t0; 5822fcf5ef2aSThomas Huth 58239f0cf041SMatheus Ferst CHK_SV(ctx); 5824fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5825fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5826fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5827fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5828fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5829fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5830fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5831fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5832fcf5ef2aSThomas Huth gen_set_label(l1); 5833fcf5ef2aSThomas Huth } 5834fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5835fcf5ef2aSThomas Huth } 5836fcf5ef2aSThomas Huth 5837fcf5ef2aSThomas Huth /* tlbwe */ 5838fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5839fcf5ef2aSThomas Huth { 5840fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58419f0cf041SMatheus Ferst GEN_PRIV(ctx); 5842fcf5ef2aSThomas Huth #else 58439f0cf041SMatheus Ferst CHK_SV(ctx); 5844fcf5ef2aSThomas Huth 5845fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5846fcf5ef2aSThomas Huth case 0: 5847fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5848fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5849fcf5ef2aSThomas Huth break; 5850fcf5ef2aSThomas Huth case 1: 5851fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5852fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5853fcf5ef2aSThomas Huth break; 5854fcf5ef2aSThomas Huth default: 5855fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5856fcf5ef2aSThomas Huth break; 5857fcf5ef2aSThomas Huth } 5858fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5859fcf5ef2aSThomas Huth } 5860fcf5ef2aSThomas Huth 5861fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5862fcf5ef2aSThomas Huth 5863fcf5ef2aSThomas Huth /* tlbre */ 5864fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5865fcf5ef2aSThomas Huth { 5866fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58679f0cf041SMatheus Ferst GEN_PRIV(ctx); 5868fcf5ef2aSThomas Huth #else 58699f0cf041SMatheus Ferst CHK_SV(ctx); 5870fcf5ef2aSThomas Huth 5871fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5872fcf5ef2aSThomas Huth case 0: 5873fcf5ef2aSThomas Huth case 1: 5874fcf5ef2aSThomas Huth case 2: 5875fcf5ef2aSThomas Huth { 58767058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5877fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5878fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5879fcf5ef2aSThomas Huth } 5880fcf5ef2aSThomas Huth break; 5881fcf5ef2aSThomas Huth default: 5882fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5883fcf5ef2aSThomas Huth break; 5884fcf5ef2aSThomas Huth } 5885fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5886fcf5ef2aSThomas Huth } 5887fcf5ef2aSThomas Huth 5888fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5889fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5890fcf5ef2aSThomas Huth { 5891fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58929f0cf041SMatheus Ferst GEN_PRIV(ctx); 5893fcf5ef2aSThomas Huth #else 5894fcf5ef2aSThomas Huth TCGv t0; 5895fcf5ef2aSThomas Huth 58969f0cf041SMatheus Ferst CHK_SV(ctx); 5897fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5898fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5899fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5900fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5901fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5902fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5903fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5904fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5905fcf5ef2aSThomas Huth gen_set_label(l1); 5906fcf5ef2aSThomas Huth } 5907fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5908fcf5ef2aSThomas Huth } 5909fcf5ef2aSThomas Huth 5910fcf5ef2aSThomas Huth /* tlbwe */ 5911fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5912fcf5ef2aSThomas Huth { 5913fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59149f0cf041SMatheus Ferst GEN_PRIV(ctx); 5915fcf5ef2aSThomas Huth #else 59169f0cf041SMatheus Ferst CHK_SV(ctx); 5917fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5918fcf5ef2aSThomas Huth case 0: 5919fcf5ef2aSThomas Huth case 1: 5920fcf5ef2aSThomas Huth case 2: 5921fcf5ef2aSThomas Huth { 59227058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5923fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5924fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5925fcf5ef2aSThomas Huth } 5926fcf5ef2aSThomas Huth break; 5927fcf5ef2aSThomas Huth default: 5928fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5929fcf5ef2aSThomas Huth break; 5930fcf5ef2aSThomas Huth } 5931fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5932fcf5ef2aSThomas Huth } 5933fcf5ef2aSThomas Huth 5934fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5935fcf5ef2aSThomas Huth 5936fcf5ef2aSThomas Huth /* tlbre */ 5937fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5938fcf5ef2aSThomas Huth { 5939fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59409f0cf041SMatheus Ferst GEN_PRIV(ctx); 5941fcf5ef2aSThomas Huth #else 59429f0cf041SMatheus Ferst CHK_SV(ctx); 5943fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5944fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5945fcf5ef2aSThomas Huth } 5946fcf5ef2aSThomas Huth 5947fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5948fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5949fcf5ef2aSThomas Huth { 5950fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59519f0cf041SMatheus Ferst GEN_PRIV(ctx); 5952fcf5ef2aSThomas Huth #else 5953fcf5ef2aSThomas Huth TCGv t0; 5954fcf5ef2aSThomas Huth 59559f0cf041SMatheus Ferst CHK_SV(ctx); 5956fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5957fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 59589d15d8e1SRichard Henderson tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5959fcf5ef2aSThomas Huth } else { 59609d15d8e1SRichard Henderson t0 = cpu_gpr[rB(ctx->opcode)]; 5961fcf5ef2aSThomas Huth } 5962fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5963fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5964fcf5ef2aSThomas Huth } 5965fcf5ef2aSThomas Huth 5966fcf5ef2aSThomas Huth /* tlbwe */ 5967fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5968fcf5ef2aSThomas Huth { 5969fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59709f0cf041SMatheus Ferst GEN_PRIV(ctx); 5971fcf5ef2aSThomas Huth #else 59729f0cf041SMatheus Ferst CHK_SV(ctx); 5973fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5974fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5975fcf5ef2aSThomas Huth } 5976fcf5ef2aSThomas Huth 5977fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5978fcf5ef2aSThomas Huth { 5979fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59809f0cf041SMatheus Ferst GEN_PRIV(ctx); 5981fcf5ef2aSThomas Huth #else 5982fcf5ef2aSThomas Huth TCGv t0; 5983fcf5ef2aSThomas Huth 59849f0cf041SMatheus Ferst CHK_SV(ctx); 5985fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5986fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5987fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5988fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5989fcf5ef2aSThomas Huth } 5990fcf5ef2aSThomas Huth 5991fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5992fcf5ef2aSThomas Huth { 5993fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59949f0cf041SMatheus Ferst GEN_PRIV(ctx); 5995fcf5ef2aSThomas Huth #else 5996fcf5ef2aSThomas Huth TCGv t0; 5997fcf5ef2aSThomas Huth 59989f0cf041SMatheus Ferst CHK_SV(ctx); 5999fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6000fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6001fcf5ef2aSThomas Huth 6002fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 6003fcf5ef2aSThomas Huth case 0: 6004fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6005fcf5ef2aSThomas Huth break; 6006fcf5ef2aSThomas Huth case 1: 6007fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6008fcf5ef2aSThomas Huth break; 6009fcf5ef2aSThomas Huth case 3: 6010fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6011fcf5ef2aSThomas Huth break; 6012fcf5ef2aSThomas Huth default: 6013fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6014fcf5ef2aSThomas Huth break; 6015fcf5ef2aSThomas Huth } 6016fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6017fcf5ef2aSThomas Huth } 6018fcf5ef2aSThomas Huth 6019fcf5ef2aSThomas Huth /* wrtee */ 6020fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6021fcf5ef2aSThomas Huth { 6022fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60239f0cf041SMatheus Ferst GEN_PRIV(ctx); 6024fcf5ef2aSThomas Huth #else 6025fcf5ef2aSThomas Huth TCGv t0; 6026fcf5ef2aSThomas Huth 60279f0cf041SMatheus Ferst CHK_SV(ctx); 6028fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6029fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6030fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6031fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 60322fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6033efe843d8SDavid Gibson /* 6034efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6035efe843d8SDavid Gibson * just set msr_ee to 1 6036fcf5ef2aSThomas Huth */ 6037d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6038fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6039fcf5ef2aSThomas Huth } 6040fcf5ef2aSThomas Huth 6041fcf5ef2aSThomas Huth /* wrteei */ 6042fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6043fcf5ef2aSThomas Huth { 6044fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60459f0cf041SMatheus Ferst GEN_PRIV(ctx); 6046fcf5ef2aSThomas Huth #else 60479f0cf041SMatheus Ferst CHK_SV(ctx); 6048fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6049fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 60502fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6051fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6052d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6053fcf5ef2aSThomas Huth } else { 6054fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6055fcf5ef2aSThomas Huth } 6056fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6057fcf5ef2aSThomas Huth } 6058fcf5ef2aSThomas Huth 6059fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6060fcf5ef2aSThomas Huth 6061fcf5ef2aSThomas Huth /* dlmzb */ 6062fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6063fcf5ef2aSThomas Huth { 60647058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6065fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6066fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6067fcf5ef2aSThomas Huth } 6068fcf5ef2aSThomas Huth 6069fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6070fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6071fcf5ef2aSThomas Huth { 6072fcf5ef2aSThomas Huth /* interpreted as no-op */ 6073fcf5ef2aSThomas Huth } 6074fcf5ef2aSThomas Huth 6075fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6076fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6077fcf5ef2aSThomas Huth { 607827a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 607927a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 608027a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 608127a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 608227a3ea7eSBALATON Zoltan } 608327a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6084fcf5ef2aSThomas Huth } 6085fcf5ef2aSThomas Huth 6086fcf5ef2aSThomas Huth /* icbt */ 6087fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6088fcf5ef2aSThomas Huth { 6089efe843d8SDavid Gibson /* 6090efe843d8SDavid Gibson * interpreted as no-op 6091efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6092efe843d8SDavid Gibson * does not generate any exception 6093fcf5ef2aSThomas Huth */ 6094fcf5ef2aSThomas Huth } 6095fcf5ef2aSThomas Huth 6096fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6097fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6098fcf5ef2aSThomas Huth { 6099fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6100fcf5ef2aSThomas Huth 6101fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6102fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6103fcf5ef2aSThomas Huth } 6104fcf5ef2aSThomas Huth 6105fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6106fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6107fcf5ef2aSThomas Huth { 6108fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6109fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6110fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6111fcf5ef2aSThomas Huth 6112fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6113fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6114fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6115fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6116fcf5ef2aSThomas Huth } else { 6117fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6118fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6119fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6120fcf5ef2aSThomas Huth } 6121fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6122fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6123fcf5ef2aSThomas Huth } 6124fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6125fcf5ef2aSThomas Huth 6126fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6127fcf5ef2aSThomas Huth { 6128fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6129fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6130fcf5ef2aSThomas Huth return; 6131fcf5ef2aSThomas Huth } 6132fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6133fcf5ef2aSThomas Huth } 6134fcf5ef2aSThomas Huth 6135fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6136fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6137fcf5ef2aSThomas Huth { \ 6138fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6139fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6140fcf5ef2aSThomas Huth return; \ 6141fcf5ef2aSThomas Huth } \ 6142efe843d8SDavid Gibson /* \ 6143efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6144fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6145fcf5ef2aSThomas Huth * \ 6146fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6147fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6148fcf5ef2aSThomas Huth */ \ 6149fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6150fcf5ef2aSThomas Huth } 6151fcf5ef2aSThomas Huth 6152fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6153fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6154fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6155fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6156fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6157fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6158fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6159efe843d8SDavid Gibson 6160b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6161b8b4576eSSuraj Jitindar Singh { 6162efe843d8SDavid Gibson /* Do Nothing */ 6163b8b4576eSSuraj Jitindar Singh } 6164fcf5ef2aSThomas Huth 616580b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 616680b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 616780b8c1eeSNikunj A Dadhania { \ 6168efe843d8SDavid Gibson /* \ 6169efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6170efe843d8SDavid Gibson * implementation of the copy paste facility \ 617180b8c1eeSNikunj A Dadhania */ \ 617280b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 617380b8c1eeSNikunj A Dadhania } 617480b8c1eeSNikunj A Dadhania 617580b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 617680b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 617780b8c1eeSNikunj A Dadhania 6178fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6179fcf5ef2aSThomas Huth { 6180fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6181fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6182fcf5ef2aSThomas Huth return; 6183fcf5ef2aSThomas Huth } 6184efe843d8SDavid Gibson /* 6185efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6186efe843d8SDavid Gibson * simple: 6187fcf5ef2aSThomas Huth * 6188fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6189fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6190fcf5ef2aSThomas Huth */ 6191fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6192fcf5ef2aSThomas Huth } 6193fcf5ef2aSThomas Huth 6194fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6195fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6196fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6197fcf5ef2aSThomas Huth { \ 61989f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6199fcf5ef2aSThomas Huth } 6200fcf5ef2aSThomas Huth 6201fcf5ef2aSThomas Huth #else 6202fcf5ef2aSThomas Huth 6203fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6204fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6205fcf5ef2aSThomas Huth { \ 62069f0cf041SMatheus Ferst CHK_SV(ctx); \ 6207fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6208fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6209fcf5ef2aSThomas Huth return; \ 6210fcf5ef2aSThomas Huth } \ 6211efe843d8SDavid Gibson /* \ 6212efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6213fcf5ef2aSThomas Huth * simple: \ 6214fcf5ef2aSThomas Huth * \ 6215fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6216fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6217fcf5ef2aSThomas Huth */ \ 6218fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6219fcf5ef2aSThomas Huth } 6220fcf5ef2aSThomas Huth 6221fcf5ef2aSThomas Huth #endif 6222fcf5ef2aSThomas Huth 6223fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6224fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6225fcf5ef2aSThomas Huth 62261a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 62271a404c91SMark Cave-Ayland { 6228e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 62291a404c91SMark Cave-Ayland } 62301a404c91SMark Cave-Ayland 62311a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 62321a404c91SMark Cave-Ayland { 6233e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 62344b65b6e7SVíctor Colombo /* 62354b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 62364b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 62374b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 62384b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 62394b65b6e7SVíctor Colombo * to be 0. 62404b65b6e7SVíctor Colombo */ 62414b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 62421a404c91SMark Cave-Ayland } 62431a404c91SMark Cave-Ayland 6244c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6245c4a18dbfSMark Cave-Ayland { 624637da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6247c4a18dbfSMark Cave-Ayland } 6248c4a18dbfSMark Cave-Ayland 6249c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6250c4a18dbfSMark Cave-Ayland { 625137da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6252c4a18dbfSMark Cave-Ayland } 6253c4a18dbfSMark Cave-Ayland 6254c9826ae9SRichard Henderson /* 6255f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6256f2aabda8SRichard Henderson */ 6257d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6258d39b2cc7SLuis Pires { 6259d39b2cc7SLuis Pires return x * 2; 6260d39b2cc7SLuis Pires } 6261d39b2cc7SLuis Pires 6262f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6263f2aabda8SRichard Henderson { 6264f2aabda8SRichard Henderson return x * 4; 6265f2aabda8SRichard Henderson } 6266f2aabda8SRichard Henderson 6267e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6268e10271e1SMatheus Ferst { 6269e10271e1SMatheus Ferst return x * 16; 6270e10271e1SMatheus Ferst } 6271e10271e1SMatheus Ferst 6272670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6273670f1da3SVíctor Colombo { 6274670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6275670f1da3SVíctor Colombo } 6276670f1da3SVíctor Colombo 6277f2aabda8SRichard Henderson /* 6278c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6279c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6280c9826ae9SRichard Henderson * proper variable. 6281c9826ae9SRichard Henderson */ 6282c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6283c9826ae9SRichard Henderson do { \ 6284c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6285c9826ae9SRichard Henderson return false; \ 6286c9826ae9SRichard Henderson } \ 6287c9826ae9SRichard Henderson } while (0) 6288c9826ae9SRichard Henderson 6289c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6290c9826ae9SRichard Henderson do { \ 6291c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6292c9826ae9SRichard Henderson return false; \ 6293c9826ae9SRichard Henderson } \ 6294c9826ae9SRichard Henderson } while (0) 6295c9826ae9SRichard Henderson 6296c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6297c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6298c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6299c9826ae9SRichard Henderson #else 6300c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6301c9826ae9SRichard Henderson #endif 6302c9826ae9SRichard Henderson 6303e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6304e2205a46SBruno Larsen do { \ 6305e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6306e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6307e2205a46SBruno Larsen return true; \ 6308e2205a46SBruno Larsen } \ 6309e2205a46SBruno Larsen } while (0) 6310e2205a46SBruno Larsen 63118226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 63128226cb2dSBruno Larsen (billionai) do { \ 63138226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 63148226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 63158226cb2dSBruno Larsen (billionai) return true; \ 63168226cb2dSBruno Larsen (billionai) } \ 63178226cb2dSBruno Larsen (billionai) } while (0) 63188226cb2dSBruno Larsen (billionai) 631986057426SFernando Valle #define REQUIRE_FPU(ctx) \ 632086057426SFernando Valle do { \ 632186057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 632286057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 632386057426SFernando Valle return true; \ 632486057426SFernando Valle } \ 632586057426SFernando Valle } while (0) 632686057426SFernando Valle 6327fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6328fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6329fc34e81aSMatheus Ferst do { \ 6330fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6331fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6332fc34e81aSMatheus Ferst return true; \ 6333fc34e81aSMatheus Ferst } \ 6334fc34e81aSMatheus Ferst } while (0) 6335fc34e81aSMatheus Ferst 6336fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6337fc34e81aSMatheus Ferst do { \ 6338e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6339fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6340fc34e81aSMatheus Ferst return true; \ 6341fc34e81aSMatheus Ferst } \ 6342fc34e81aSMatheus Ferst } while (0) 6343fc34e81aSMatheus Ferst #else 6344fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6345fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6346fc34e81aSMatheus Ferst #endif 6347fc34e81aSMatheus Ferst 6348f2aabda8SRichard Henderson /* 6349f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6350f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6351f2aabda8SRichard Henderson */ 6352f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6353f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6354f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 635519f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 635619f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 635719f0862dSLuis Pires { \ 635819f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 635919f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 636019f0862dSLuis Pires } 636119f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 636219f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 636319f0862dSLuis Pires { \ 636419f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 636519f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 636619f0862dSLuis Pires } 6367f2aabda8SRichard Henderson 6368f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6369f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6370f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 637119f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 637219f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 637319f0862dSLuis Pires { \ 637419f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 637519f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 637619f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 637719f0862dSLuis Pires } 6378f2aabda8SRichard Henderson 6379f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6380f2aabda8SRichard Henderson 6381f2aabda8SRichard Henderson 638299082815SRichard Henderson #include "decode-insn32.c.inc" 638399082815SRichard Henderson #include "decode-insn64.c.inc" 6384565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6385565cb109SGustavo Romero 6386725b2d4dSFernando Eckhardt Valle /* 6387725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6388725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6389725b2d4dSFernando Eckhardt Valle */ 6390725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6391725b2d4dSFernando Eckhardt Valle { 6392725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6393725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6394725b2d4dSFernando Eckhardt Valle d->si = a->si; 6395725b2d4dSFernando Eckhardt Valle if (a->r) { 6396725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6397725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6398725b2d4dSFernando Eckhardt Valle return false; 6399725b2d4dSFernando Eckhardt Valle } 6400725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6401725b2d4dSFernando Eckhardt Valle } 6402725b2d4dSFernando Eckhardt Valle return true; 6403725b2d4dSFernando Eckhardt Valle } 6404725b2d4dSFernando Eckhardt Valle 640599082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 640699082815SRichard Henderson 6407139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6408fcf5ef2aSThomas Huth 6409139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6410fcf5ef2aSThomas Huth 6411139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6412fcf5ef2aSThomas Huth 6413139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6414fcf5ef2aSThomas Huth 6415139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6416fcf5ef2aSThomas Huth 64171f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 64181f26c751SDaniel Henrique Barboza 641998f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 642098f43417SMatheus Ferst 6421016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6422016b6e1dSLeandro Lupori 642320e2d04eSLeandro Lupori /* Handles lfdp */ 64245cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 64255cb091a4SNikunj A Dadhania { 642620e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 64275cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 64285cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 64295cb091a4SNikunj A Dadhania } 64305cb091a4SNikunj A Dadhania } 64315cb091a4SNikunj A Dadhania return gen_invalid(ctx); 64325cb091a4SNikunj A Dadhania } 64335cb091a4SNikunj A Dadhania 643420e2d04eSLeandro Lupori /* Handles stfdp */ 6435e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6436e3001664SNikunj A Dadhania { 643720e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 643820e2d04eSLeandro Lupori /* stfdp */ 6439e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6440e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6441e3001664SNikunj A Dadhania } 6442e3001664SNikunj A Dadhania } 6443e3001664SNikunj A Dadhania return gen_invalid(ctx); 6444e3001664SNikunj A Dadhania } 6445e3001664SNikunj A Dadhania 64469d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64479d69cfa2SLijun Pan /* brd */ 64489d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 64499d69cfa2SLijun Pan { 64509d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64519d69cfa2SLijun Pan } 64529d69cfa2SLijun Pan 64539d69cfa2SLijun Pan /* brw */ 64549d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 64559d69cfa2SLijun Pan { 64569d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64579d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 64589d69cfa2SLijun Pan 64599d69cfa2SLijun Pan } 64609d69cfa2SLijun Pan 64619d69cfa2SLijun Pan /* brh */ 64629d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 64639d69cfa2SLijun Pan { 6464491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 64659d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 64669d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 64679d69cfa2SLijun Pan 64689d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6469491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6470491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 64719d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 64729d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 64739d69cfa2SLijun Pan } 64749d69cfa2SLijun Pan #endif 64759d69cfa2SLijun Pan 6476fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 64779d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64789d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 64799d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 64809d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 64819d69cfa2SLijun Pan #endif 6482fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6483fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6484fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6485fcf5ef2aSThomas Huth #endif 6486fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6487fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6488fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6489fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6490fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6491fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6492fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6493fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6494fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6495fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6496fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6497fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6498fcf5ef2aSThomas Huth #endif 6499fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6500fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6501fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6502fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6503fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6504fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6505fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 650680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6507b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 650880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6509fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6510fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6511fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6512fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6513fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6514fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6515fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6516fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6517fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6518fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6519fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6520fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6521fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6522fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6523fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6524fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6525fcf5ef2aSThomas Huth #endif 6526fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6527fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6528fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6529fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6530fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6531fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6532fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6533fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6534fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6535fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6536fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6537fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6538fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6539fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6540fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6541fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6542fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6543fcf5ef2aSThomas Huth #endif 65445cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 65455cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 654672b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6547e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6548fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6549fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6550fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6551fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6552fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6553fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6554c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6555fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6556fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6557fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6558fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6559a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6560a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6561fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6562fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6563fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6564fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6565a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6566a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6567fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6568fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6569fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6570fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6571fcf5ef2aSThomas Huth #endif 6572fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 65730c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 65740c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 65750c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6576fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6577fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6578fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6579fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6580fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6581fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6582fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6583fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6584fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 65853c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 65863c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65873c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65883c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65893c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 65903c89b8d6SNicholas Piggin #endif 6591cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6592fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6593fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6594fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6595fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6596fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6597fcf5ef2aSThomas Huth #endif 65983c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65993c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 66003c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6601fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6602fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6603fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6604fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6605fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6606fcf5ef2aSThomas Huth #endif 6607fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6608fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6609fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6610fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6611fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6612fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6613fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6614fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6615fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6616b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6617fcf5ef2aSThomas Huth #endif 6618fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6619fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6620fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 662150728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6622fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6623fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 662450728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6625fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 662650728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6627fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 662850728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6629fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6630e64645baSBernhard Beschow GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6631fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 663250728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6633fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 663499d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6635fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6636fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 663750728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6638fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6639fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6640fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6641fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6642fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6643fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6644fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6645fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6646fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6647fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6648fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6649fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6650fcf5ef2aSThomas Huth #endif 6651fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6652efe843d8SDavid Gibson /* 6653efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6654efe843d8SDavid Gibson * different ISA versions 6655efe843d8SDavid Gibson */ 6656fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6657fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6658fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6659fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6660fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6661fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6662fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6663fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6664fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6665fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6666fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6667fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6668fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6669fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6670fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6671fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6672fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6673fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6674fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6675fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6676fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6677fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6678fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6679fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6680fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6681fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6682fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6683fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6684fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6685fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6686fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6687fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6688fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6689fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6690fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6691fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6692fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6693fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6694fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6695fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6696fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 669727a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6698fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6699fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 67000c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 67010c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6702fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6703fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6704fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6705fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6706fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6707fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6708fcf5ef2aSThomas Huth PPC2_ISA300), 6709fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6710fcf5ef2aSThomas Huth #endif 6711fcf5ef2aSThomas Huth 6712fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6713fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6714fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6715fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6716fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6717fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6718fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6719fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6720fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6721fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6722fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6723fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6724fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6725fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6726fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 67274c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6728fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6729fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6730fcf5ef2aSThomas Huth 6731fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6732fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6733fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6734fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6735fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6736fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6737fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6738fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6739fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6740fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6741fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6742fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6743fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6744fcf5ef2aSThomas Huth 6745fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6746fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6747fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6748fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6749fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6750fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6751fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6752fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6753fcf5ef2aSThomas Huth 6754fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6755fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6756fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6757fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6758fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6759fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6760fcf5ef2aSThomas Huth 6761fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6762fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6763fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6764fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6765fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6766fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6767fcf5ef2aSThomas Huth #endif 6768fcf5ef2aSThomas Huth 6769fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6770fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6771fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6772fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6773fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6774fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6775fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6776fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6777fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6778fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6779fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6780fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6781fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6782fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6783fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6784fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6785fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6786fcf5ef2aSThomas Huth 6787fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6788fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6789fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6790fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6791fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6792fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6793fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6794fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6795fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6796fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6797fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6798fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6799fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6800fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6801fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6802fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6803fcf5ef2aSThomas Huth #endif 6804fcf5ef2aSThomas Huth 6805fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6806fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6807fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6808fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6809fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6810fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6811fcf5ef2aSThomas Huth PPC_64B) 6812fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6813fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6814fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6815fcf5ef2aSThomas Huth PPC_64B), \ 6816fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6817fcf5ef2aSThomas Huth PPC_64B), \ 6818fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6819fcf5ef2aSThomas Huth PPC_64B) 6820fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6821fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6822fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6823fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6824fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6825fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6826fcf5ef2aSThomas Huth #endif 6827fcf5ef2aSThomas Huth 6828fcf5ef2aSThomas Huth #undef GEN_LDX_E 6829fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6830fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6831fcf5ef2aSThomas Huth 6832fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6833fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6834fcf5ef2aSThomas Huth 6835fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6836fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6837fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6838fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6839fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6840fcf5ef2aSThomas Huth #endif 6841fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6842fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6843fcf5ef2aSThomas Huth 684450728199SRoman Kapl /* External PID based load */ 684550728199SRoman Kapl #undef GEN_LDEPX 684650728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 684750728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 684850728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 684950728199SRoman Kapl 685050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 685150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 685250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 685350728199SRoman Kapl #if defined(TARGET_PPC64) 6854fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 685550728199SRoman Kapl #endif 685650728199SRoman Kapl 6857fcf5ef2aSThomas Huth #undef GEN_STX_E 6858fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 68590123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6860fcf5ef2aSThomas Huth 6861fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6862fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6863fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6864fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6865fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6866fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6867fcf5ef2aSThomas Huth #endif 6868fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6869fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6870fcf5ef2aSThomas Huth 687150728199SRoman Kapl #undef GEN_STEPX 687250728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 687350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 687450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 687550728199SRoman Kapl 687650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 687750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 687850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 687950728199SRoman Kapl #if defined(TARGET_PPC64) 6880fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 688150728199SRoman Kapl #endif 688250728199SRoman Kapl 6883fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6884fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6885fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6886fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6887fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6888fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6889fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6890fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6891fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6892fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6893fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6894fcf5ef2aSThomas Huth 6895fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6896fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6897fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6898fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6899fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6900fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6901fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6902fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6903fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6904fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6905fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6906fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6907fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6908fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6909fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6910fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6911fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6912fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6913fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6914fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6915fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6916fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6917fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6918fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6919fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6920fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6921fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6922fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6923fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6924fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6925fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6926fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6927fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6928fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6929fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6930fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6931fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6932fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6933fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6934fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6935fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6936fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6937fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6938fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6939fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6940fcf5ef2aSThomas Huth 6941fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6942fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6943fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6944fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6945fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6946fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6947fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6948fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6949fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6950fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6951fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6952fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6953fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6954fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6955fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6956fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6957fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6958fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6959fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6960fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6961fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6962fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6963fcf5ef2aSThomas Huth 6964139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 6965fcf5ef2aSThomas Huth 6966139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 6967fcf5ef2aSThomas Huth 6968139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 6969fcf5ef2aSThomas Huth 6970139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 6971fcf5ef2aSThomas Huth }; 6972fcf5ef2aSThomas Huth 69737468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 69747468e2c8SBruno Larsen (billionai) /* Opcode types */ 69757468e2c8SBruno Larsen (billionai) enum { 69767468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 69777468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 69787468e2c8SBruno Larsen (billionai) }; 69797468e2c8SBruno Larsen (billionai) 69807468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 69817468e2c8SBruno Larsen (billionai) 69827468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 69837468e2c8SBruno Larsen (billionai) { 69847468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 69857468e2c8SBruno Larsen (billionai) } 69867468e2c8SBruno Larsen (billionai) 69877468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 69887468e2c8SBruno Larsen (billionai) { 69897468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 69907468e2c8SBruno Larsen (billionai) } 69917468e2c8SBruno Larsen (billionai) 69927468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 69937468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 69947468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 69957468e2c8SBruno Larsen (billionai) { 69967468e2c8SBruno Larsen (billionai) int i; 69977468e2c8SBruno Larsen (billionai) 69987468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 69997468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 70007468e2c8SBruno Larsen (billionai) } 70017468e2c8SBruno Larsen (billionai) } 70027468e2c8SBruno Larsen (billionai) 70037468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 70047468e2c8SBruno Larsen (billionai) { 70057468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 70067468e2c8SBruno Larsen (billionai) 70077468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 70087468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 70097468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 70107468e2c8SBruno Larsen (billionai) 70117468e2c8SBruno Larsen (billionai) return 0; 70127468e2c8SBruno Larsen (billionai) } 70137468e2c8SBruno Larsen (billionai) 70147468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 70157468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70167468e2c8SBruno Larsen (billionai) { 70177468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 70187468e2c8SBruno Larsen (billionai) return -1; 70197468e2c8SBruno Larsen (billionai) } 70207468e2c8SBruno Larsen (billionai) table[idx] = handler; 70217468e2c8SBruno Larsen (billionai) 70227468e2c8SBruno Larsen (billionai) return 0; 70237468e2c8SBruno Larsen (billionai) } 70247468e2c8SBruno Larsen (billionai) 70257468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 70267468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 70277468e2c8SBruno Larsen (billionai) { 70287468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 70297468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 70307468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 70317468e2c8SBruno Larsen (billionai) return -1; 70327468e2c8SBruno Larsen (billionai) } 70337468e2c8SBruno Larsen (billionai) 70347468e2c8SBruno Larsen (billionai) return 0; 70357468e2c8SBruno Larsen (billionai) } 70367468e2c8SBruno Larsen (billionai) 70377468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 70387468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70397468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70407468e2c8SBruno Larsen (billionai) { 70417468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 70427468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 70437468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 70447468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 70457468e2c8SBruno Larsen (billionai) return -1; 70467468e2c8SBruno Larsen (billionai) } 70477468e2c8SBruno Larsen (billionai) } else { 70487468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 70497468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 70507468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 70517468e2c8SBruno Larsen (billionai) return -1; 70527468e2c8SBruno Larsen (billionai) } 70537468e2c8SBruno Larsen (billionai) } 70547468e2c8SBruno Larsen (billionai) if (handler != NULL && 70557468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 70567468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 70577468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 70587468e2c8SBruno Larsen (billionai) return -1; 70597468e2c8SBruno Larsen (billionai) } 70607468e2c8SBruno Larsen (billionai) 70617468e2c8SBruno Larsen (billionai) return 0; 70627468e2c8SBruno Larsen (billionai) } 70637468e2c8SBruno Larsen (billionai) 70647468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 70657468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70667468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70677468e2c8SBruno Larsen (billionai) { 70687468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 70697468e2c8SBruno Larsen (billionai) } 70707468e2c8SBruno Larsen (billionai) 70717468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 70727468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70737468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 70747468e2c8SBruno Larsen (billionai) { 70757468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70767468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70777468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70787468e2c8SBruno Larsen (billionai) return -1; 70797468e2c8SBruno Larsen (billionai) } 70807468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 70817468e2c8SBruno Larsen (billionai) handler) < 0) { 70827468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70837468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70847468e2c8SBruno Larsen (billionai) return -1; 70857468e2c8SBruno Larsen (billionai) } 70867468e2c8SBruno Larsen (billionai) 70877468e2c8SBruno Larsen (billionai) return 0; 70887468e2c8SBruno Larsen (billionai) } 70897468e2c8SBruno Larsen (billionai) 70907468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 70917468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70927468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 70937468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70947468e2c8SBruno Larsen (billionai) { 70957468e2c8SBruno Larsen (billionai) opc_handler_t **table; 70967468e2c8SBruno Larsen (billionai) 70977468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70987468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70997468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 71007468e2c8SBruno Larsen (billionai) return -1; 71017468e2c8SBruno Larsen (billionai) } 71027468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 71037468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 71047468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 71057468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 71067468e2c8SBruno Larsen (billionai) return -1; 71077468e2c8SBruno Larsen (billionai) } 71087468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 71097468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 71107468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 71117468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 71127468e2c8SBruno Larsen (billionai) return -1; 71137468e2c8SBruno Larsen (billionai) } 71147468e2c8SBruno Larsen (billionai) return 0; 71157468e2c8SBruno Larsen (billionai) } 71167468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 71177468e2c8SBruno Larsen (billionai) { 71187468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 71197468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 71207468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 71217468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 71227468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 71237468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 71247468e2c8SBruno Larsen (billionai) return -1; 71257468e2c8SBruno Larsen (billionai) } 71267468e2c8SBruno Larsen (billionai) } else { 71277468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 71287468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 71297468e2c8SBruno Larsen (billionai) return -1; 71307468e2c8SBruno Larsen (billionai) } 71317468e2c8SBruno Larsen (billionai) } 71327468e2c8SBruno Larsen (billionai) } else { 71337468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 71347468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 71357468e2c8SBruno Larsen (billionai) return -1; 71367468e2c8SBruno Larsen (billionai) } 71377468e2c8SBruno Larsen (billionai) } 71387468e2c8SBruno Larsen (billionai) } else { 71397468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 71407468e2c8SBruno Larsen (billionai) return -1; 71417468e2c8SBruno Larsen (billionai) } 71427468e2c8SBruno Larsen (billionai) } 71437468e2c8SBruno Larsen (billionai) 71447468e2c8SBruno Larsen (billionai) return 0; 71457468e2c8SBruno Larsen (billionai) } 71467468e2c8SBruno Larsen (billionai) 71477468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 71487468e2c8SBruno Larsen (billionai) { 71497468e2c8SBruno Larsen (billionai) int i, count, tmp; 71507468e2c8SBruno Larsen (billionai) 71517468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 71527468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 71537468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 71547468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71557468e2c8SBruno Larsen (billionai) } 71567468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 71577468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 71587468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 71597468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 71607468e2c8SBruno Larsen (billionai) if (tmp == 0) { 71617468e2c8SBruno Larsen (billionai) free(table[i]); 71627468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71637468e2c8SBruno Larsen (billionai) } else { 71647468e2c8SBruno Larsen (billionai) count++; 71657468e2c8SBruno Larsen (billionai) } 71667468e2c8SBruno Larsen (billionai) } else { 71677468e2c8SBruno Larsen (billionai) count++; 71687468e2c8SBruno Larsen (billionai) } 71697468e2c8SBruno Larsen (billionai) } 71707468e2c8SBruno Larsen (billionai) } 71717468e2c8SBruno Larsen (billionai) 71727468e2c8SBruno Larsen (billionai) return count; 71737468e2c8SBruno Larsen (billionai) } 71747468e2c8SBruno Larsen (billionai) 71757468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 71767468e2c8SBruno Larsen (billionai) { 71777468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 71787468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 71797468e2c8SBruno Larsen (billionai) } 71807468e2c8SBruno Larsen (billionai) } 71817468e2c8SBruno Larsen (billionai) 71827468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71837468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 71847468e2c8SBruno Larsen (billionai) { 71857468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 71867468e2c8SBruno Larsen (billionai) opcode_t *opc; 71877468e2c8SBruno Larsen (billionai) 71887468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 71897468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 71907468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 71917468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 71927468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 71937468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 71947468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 71957468e2c8SBruno Larsen (billionai) opc->opc3); 71967468e2c8SBruno Larsen (billionai) return; 71977468e2c8SBruno Larsen (billionai) } 71987468e2c8SBruno Larsen (billionai) } 71997468e2c8SBruno Larsen (billionai) } 72007468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 72017468e2c8SBruno Larsen (billionai) fflush(stdout); 72027468e2c8SBruno Larsen (billionai) fflush(stderr); 72037468e2c8SBruno Larsen (billionai) } 72047468e2c8SBruno Larsen (billionai) 72057468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 72067468e2c8SBruno Larsen (billionai) { 72077468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 72087468e2c8SBruno Larsen (billionai) int i, j, k; 72097468e2c8SBruno Larsen (billionai) 72107468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 72117468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 72127468e2c8SBruno Larsen (billionai) continue; 72137468e2c8SBruno Larsen (billionai) } 72147468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 72157468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 72167468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 72177468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 72187468e2c8SBruno Larsen (billionai) continue; 72197468e2c8SBruno Larsen (billionai) } 72207468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 72217468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 72227468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 72237468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 72247468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 72257468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 72267468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 72277468e2c8SBruno Larsen (billionai) } 72287468e2c8SBruno Larsen (billionai) } 72297468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 72307468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 72317468e2c8SBruno Larsen (billionai) } 72327468e2c8SBruno Larsen (billionai) } 72337468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 72347468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 72357468e2c8SBruno Larsen (billionai) } 72367468e2c8SBruno Larsen (billionai) } 72377468e2c8SBruno Larsen (billionai) } 72387468e2c8SBruno Larsen (billionai) 72397468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 72407468e2c8SBruno Larsen (billionai) { 72417468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 72427468e2c8SBruno Larsen (billionai) 72437468e2c8SBruno Larsen (billionai) /* 72447468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 72457468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 72467468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 72477468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 72487468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 72497468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 72507468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 72517468e2c8SBruno Larsen (billionai) */ 72527468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 72537468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 72547468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 72557468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 72567468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 72577468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 72587468e2c8SBruno Larsen (billionai) } 72597468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 72607468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 72617468e2c8SBruno Larsen (billionai) return 0; 72627468e2c8SBruno Larsen (billionai) } 72637468e2c8SBruno Larsen (billionai) 7264624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7265624cb07fSRichard Henderson { 7266624cb07fSRichard Henderson opc_handler_t **table, *handler; 7267624cb07fSRichard Henderson uint32_t inval; 7268624cb07fSRichard Henderson 7269624cb07fSRichard Henderson ctx->opcode = insn; 7270624cb07fSRichard Henderson 7271624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7272624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7273624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7274624cb07fSRichard Henderson 7275624cb07fSRichard Henderson table = cpu->opcodes; 7276624cb07fSRichard Henderson handler = table[opc1(insn)]; 7277624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7278624cb07fSRichard Henderson table = ind_table(handler); 7279624cb07fSRichard Henderson handler = table[opc2(insn)]; 7280624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7281624cb07fSRichard Henderson table = ind_table(handler); 7282624cb07fSRichard Henderson handler = table[opc3(insn)]; 7283624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7284624cb07fSRichard Henderson table = ind_table(handler); 7285624cb07fSRichard Henderson handler = table[opc4(insn)]; 7286624cb07fSRichard Henderson } 7287624cb07fSRichard Henderson } 7288624cb07fSRichard Henderson } 7289624cb07fSRichard Henderson 7290624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7291624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7292624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7293624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7294624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7295624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7296624cb07fSRichard Henderson insn, ctx->cia); 7297624cb07fSRichard Henderson return false; 7298624cb07fSRichard Henderson } 7299624cb07fSRichard Henderson 7300624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7301624cb07fSRichard Henderson && Rc(insn))) { 7302624cb07fSRichard Henderson inval = handler->inval2; 7303624cb07fSRichard Henderson } else { 7304624cb07fSRichard Henderson inval = handler->inval1; 7305624cb07fSRichard Henderson } 7306624cb07fSRichard Henderson 7307624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7308624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7309624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7310624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7311624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7312624cb07fSRichard Henderson insn, ctx->cia); 7313624cb07fSRichard Henderson return false; 7314624cb07fSRichard Henderson } 7315624cb07fSRichard Henderson 7316624cb07fSRichard Henderson handler->handler(ctx); 7317624cb07fSRichard Henderson return true; 7318624cb07fSRichard Henderson } 7319624cb07fSRichard Henderson 7320b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7321fcf5ef2aSThomas Huth { 7322b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 73239c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 73242df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7325fcf5ef2aSThomas Huth 7326b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 73272df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7328d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 73292df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 73302df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7331b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7332b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7333b0c2d521SEmilio G. Cota ctx->access_type = -1; 7334d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 73352df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7336b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 73370e3bf489SRoman Kapl ctx->flags = env->flags; 7338fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 73392df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7340b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7341fcf5ef2aSThomas Huth #endif 7342e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7343d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7344fcf5ef2aSThomas Huth 73452df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 73462df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 73472df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 73482df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 73492df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7350f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 73511db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7352f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7353f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 73548b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 73558b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 735646d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 73572df4fe7aSRichard Henderson 7358b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 73592df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 73602df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 73619498d103SRichard Henderson ctx->base.max_insns = 1; 7362efe843d8SDavid Gibson } 73632df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7364b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7365efe843d8SDavid Gibson } 736613b45575SRichard Henderson } 7367fcf5ef2aSThomas Huth 7368b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7369b0c2d521SEmilio G. Cota { 7370b0c2d521SEmilio G. Cota } 7371fcf5ef2aSThomas Huth 7372b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7373b0c2d521SEmilio G. Cota { 7374b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7375b0c2d521SEmilio G. Cota } 7376b0c2d521SEmilio G. Cota 737799082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 737899082815SRichard Henderson { 737999082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 738099082815SRichard Henderson return opc1(insn) == 1; 738199082815SRichard Henderson } 738299082815SRichard Henderson 7383b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7384b0c2d521SEmilio G. Cota { 7385b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 738628876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7387b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 738899082815SRichard Henderson target_ulong pc; 7389624cb07fSRichard Henderson uint32_t insn; 7390624cb07fSRichard Henderson bool ok; 7391b0c2d521SEmilio G. Cota 7392fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7393fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7394b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7395b0c2d521SEmilio G. Cota 739699082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 73974e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 739899082815SRichard Henderson ctx->base.pc_next = pc += 4; 7399fcf5ef2aSThomas Huth 740099082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 740199082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 740299082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 740399082815SRichard Henderson } else if ((pc & 63) == 0) { 740499082815SRichard Henderson /* 740599082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 740699082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 740799082815SRichard Henderson * 64-byte address boundary (system alignment error). 740899082815SRichard Henderson */ 740999082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 741099082815SRichard Henderson ok = true; 741199082815SRichard Henderson } else { 74124e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 74134e116893SIlya Leoshkevich need_byteswap(ctx)); 741499082815SRichard Henderson ctx->base.pc_next = pc += 4; 741599082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 741699082815SRichard Henderson } 7417624cb07fSRichard Henderson if (!ok) { 7418624cb07fSRichard Henderson gen_invalid(ctx); 7419fcf5ef2aSThomas Huth } 7420624cb07fSRichard Henderson 742164a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 742299082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 742364a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 742464a0f644SRichard Henderson } 7425fcf5ef2aSThomas Huth } 7426b0c2d521SEmilio G. Cota 7427b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7428b0c2d521SEmilio G. Cota { 7429b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7430a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7431a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7432b0c2d521SEmilio G. Cota 7433a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7434a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 74353d8a5b69SRichard Henderson return; 74363d8a5b69SRichard Henderson } 74373d8a5b69SRichard Henderson 7438a9b5b3d0SRichard Henderson /* Honor single stepping. */ 743998a18f4dSNicholas Piggin if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 7440a11e3a15SNicholas Piggin bool rfi_type = false; 7441a11e3a15SNicholas Piggin 7442a9b5b3d0SRichard Henderson switch (is_jmp) { 7443a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7444a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7445a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7446a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7447a9b5b3d0SRichard Henderson break; 7448a9b5b3d0SRichard Henderson case DISAS_EXIT: 7449a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7450a11e3a15SNicholas Piggin /* 7451a11e3a15SNicholas Piggin * This is a heuristic, to put it kindly. The rfi class of 7452a11e3a15SNicholas Piggin * instructions are among the few outside branches that change 7453a11e3a15SNicholas Piggin * NIP without taking an interrupt. Single step trace interrupts 7454a11e3a15SNicholas Piggin * do not fire on completion of these instructions. 7455a11e3a15SNicholas Piggin */ 7456a11e3a15SNicholas Piggin rfi_type = true; 7457a9b5b3d0SRichard Henderson break; 7458a9b5b3d0SRichard Henderson default: 7459a9b5b3d0SRichard Henderson g_assert_not_reached(); 7460fcf5ef2aSThomas Huth } 746113b45575SRichard Henderson 7462a11e3a15SNicholas Piggin gen_debug_exception(ctx, rfi_type); 7463a9b5b3d0SRichard Henderson return; 7464a9b5b3d0SRichard Henderson } 7465a9b5b3d0SRichard Henderson 7466a9b5b3d0SRichard Henderson switch (is_jmp) { 7467a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7468a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 746946d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7470a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7471a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7472a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7473a9b5b3d0SRichard Henderson break; 7474a9b5b3d0SRichard Henderson } 7475a9b5b3d0SRichard Henderson /* fall through */ 7476a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7477a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7478a9b5b3d0SRichard Henderson /* fall through */ 7479a9b5b3d0SRichard Henderson case DISAS_CHAIN: 748046d396bdSDaniel Henrique Barboza /* 748146d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 748246d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 748346d396bdSDaniel Henrique Barboza */ 748446d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 748546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 748646d396bdSDaniel Henrique Barboza } 748746d396bdSDaniel Henrique Barboza 7488a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7489a9b5b3d0SRichard Henderson break; 7490a9b5b3d0SRichard Henderson 7491a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7492a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7493a9b5b3d0SRichard Henderson /* fall through */ 7494a9b5b3d0SRichard Henderson case DISAS_EXIT: 749546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 749607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7497a9b5b3d0SRichard Henderson break; 7498a9b5b3d0SRichard Henderson 7499a9b5b3d0SRichard Henderson default: 7500a9b5b3d0SRichard Henderson g_assert_not_reached(); 7501fcf5ef2aSThomas Huth } 7502fcf5ef2aSThomas Huth } 7503b0c2d521SEmilio G. Cota 75048eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 75058eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7506b0c2d521SEmilio G. Cota { 75078eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 75088eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7509b0c2d521SEmilio G. Cota } 7510b0c2d521SEmilio G. Cota 7511b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7512b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7513b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7514b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7515b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7516b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7517b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7518b0c2d521SEmilio G. Cota }; 7519b0c2d521SEmilio G. Cota 7520597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7521306c8721SRichard Henderson target_ulong pc, void *host_pc) 7522b0c2d521SEmilio G. Cota { 7523b0c2d521SEmilio G. Cota DisasContext ctx; 7524b0c2d521SEmilio G. Cota 7525306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7526fcf5ef2aSThomas Huth } 7527