1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50fcf5ef2aSThomas Huth 51fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 53fcf5ef2aSThomas Huth #else 54fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 55fcf5ef2aSThomas Huth #endif 56fcf5ef2aSThomas Huth /*****************************************************************************/ 57fcf5ef2aSThomas Huth /* Code translation helpers */ 58fcf5ef2aSThomas Huth 59fcf5ef2aSThomas Huth /* global register indexes */ 60fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 61fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 62fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 63fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 64fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 65fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 66fcf5ef2aSThomas Huth static TCGv cpu_nip; 67fcf5ef2aSThomas Huth static TCGv cpu_msr; 68fcf5ef2aSThomas Huth static TCGv cpu_ctr; 69fcf5ef2aSThomas Huth static TCGv cpu_lr; 70fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 71fcf5ef2aSThomas Huth static TCGv cpu_cfar; 72fcf5ef2aSThomas Huth #endif 73dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 74fcf5ef2aSThomas Huth static TCGv cpu_reserve; 75253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 76fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 77fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth void ppc_translate_init(void) 82fcf5ef2aSThomas Huth { 83fcf5ef2aSThomas Huth int i; 84fcf5ef2aSThomas Huth char *p; 85fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 86fcf5ef2aSThomas Huth 87fcf5ef2aSThomas Huth p = cpu_reg_names; 88fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 91fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 92fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 93fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 94fcf5ef2aSThomas Huth p += 5; 95fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 96fcf5ef2aSThomas Huth } 97fcf5ef2aSThomas Huth 98fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 99fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 100fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 101fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 102fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 103fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 105fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 106fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 107fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 108fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth } 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 112fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 124fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 125fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 126fcf5ef2aSThomas Huth #endif 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 130fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 132fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 134fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 135fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 136dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 138dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 139dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 142fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 143fcf5ef2aSThomas Huth "reserve_addr"); 144253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 145253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 146253ce7b2SNikunj A Dadhania "reserve_val"); 147fcf5ef2aSThomas Huth 148fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 149fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 152efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 153efe843d8SDavid Gibson "access_type"); 154fcf5ef2aSThomas Huth } 155fcf5ef2aSThomas Huth 156fcf5ef2aSThomas Huth /* internal defines */ 157fcf5ef2aSThomas Huth struct DisasContext { 158b6bac4bcSEmilio G. Cota DisasContextBase base; 1592c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 160fcf5ef2aSThomas Huth uint32_t opcode; 161fcf5ef2aSThomas Huth /* Routine used to access memory */ 162fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 163fcf5ef2aSThomas Huth bool lazy_tlb_flush; 164fcf5ef2aSThomas Huth bool need_access_type; 165fcf5ef2aSThomas Huth int mem_idx; 166fcf5ef2aSThomas Huth int access_type; 167fcf5ef2aSThomas Huth /* Translation flags */ 16814776ab5STony Nguyen MemOp default_tcg_memop_mask; 169fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 170fcf5ef2aSThomas Huth bool sf_mode; 171fcf5ef2aSThomas Huth bool has_cfar; 172fcf5ef2aSThomas Huth #endif 173fcf5ef2aSThomas Huth bool fpu_enabled; 174fcf5ef2aSThomas Huth bool altivec_enabled; 175fcf5ef2aSThomas Huth bool vsx_enabled; 176fcf5ef2aSThomas Huth bool spe_enabled; 177fcf5ef2aSThomas Huth bool tm_enabled; 178c6fd28fdSSuraj Jitindar Singh bool gtse; 179fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 180fcf5ef2aSThomas Huth int singlestep_enabled; 1810e3bf489SRoman Kapl uint32_t flags; 182fcf5ef2aSThomas Huth uint64_t insns_flags; 183fcf5ef2aSThomas Huth uint64_t insns_flags2; 184fcf5ef2aSThomas Huth }; 185fcf5ef2aSThomas Huth 186a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 187a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 188a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 189a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 190a9b5b3d0SRichard Henderson 191fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 192fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 193fcf5ef2aSThomas Huth { 194fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 195fcf5ef2aSThomas Huth return ctx->le_mode; 196fcf5ef2aSThomas Huth #else 197fcf5ef2aSThomas Huth return !ctx->le_mode; 198fcf5ef2aSThomas Huth #endif 199fcf5ef2aSThomas Huth } 200fcf5ef2aSThomas Huth 201fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 202fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 203fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 204fcf5ef2aSThomas Huth #else 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 206fcf5ef2aSThomas Huth #endif 207fcf5ef2aSThomas Huth 208fcf5ef2aSThomas Huth struct opc_handler_t { 209fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 210fcf5ef2aSThomas Huth uint32_t inval1; 211fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 212fcf5ef2aSThomas Huth uint32_t inval2; 213fcf5ef2aSThomas Huth /* instruction type */ 214fcf5ef2aSThomas Huth uint64_t type; 215fcf5ef2aSThomas Huth /* extended instruction type */ 216fcf5ef2aSThomas Huth uint64_t type2; 217fcf5ef2aSThomas Huth /* handler */ 218fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 219fcf5ef2aSThomas Huth }; 220fcf5ef2aSThomas Huth 2210e3bf489SRoman Kapl /* SPR load/store helpers */ 2220e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2230e3bf489SRoman Kapl { 2240e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2250e3bf489SRoman Kapl } 2260e3bf489SRoman Kapl 2270e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2280e3bf489SRoman Kapl { 2290e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2300e3bf489SRoman Kapl } 2310e3bf489SRoman Kapl 232fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 233fcf5ef2aSThomas Huth { 234fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 235fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 236fcf5ef2aSThomas Huth ctx->access_type = access_type; 237fcf5ef2aSThomas Huth } 238fcf5ef2aSThomas Huth } 239fcf5ef2aSThomas Huth 240fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 241fcf5ef2aSThomas Huth { 242fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 243fcf5ef2aSThomas Huth nip = (uint32_t)nip; 244fcf5ef2aSThomas Huth } 245fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth 248fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 249fcf5ef2aSThomas Huth { 250fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 251fcf5ef2aSThomas Huth 252efe843d8SDavid Gibson /* 253efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 254efe843d8SDavid Gibson * faulting instruction 255fcf5ef2aSThomas Huth */ 2562c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 257fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 258fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 259fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 260fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 261fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2623d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 263fcf5ef2aSThomas Huth } 264fcf5ef2aSThomas Huth 265fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 266fcf5ef2aSThomas Huth { 267fcf5ef2aSThomas Huth TCGv_i32 t0; 268fcf5ef2aSThomas Huth 269efe843d8SDavid Gibson /* 270efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 271efe843d8SDavid Gibson * faulting instruction 272fcf5ef2aSThomas Huth */ 2732c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 274fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 275fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 276fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2773d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 278fcf5ef2aSThomas Huth } 279fcf5ef2aSThomas Huth 280fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 281fcf5ef2aSThomas Huth target_ulong nip) 282fcf5ef2aSThomas Huth { 283fcf5ef2aSThomas Huth TCGv_i32 t0; 284fcf5ef2aSThomas Huth 285fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 286fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 287fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 288fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2893d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 290fcf5ef2aSThomas Huth } 291fcf5ef2aSThomas Huth 292f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 293f5b6daacSRichard Henderson { 294f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 295f5b6daacSRichard Henderson gen_io_start(); 296f5b6daacSRichard Henderson /* 297f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 298f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 299f5b6daacSRichard Henderson * decide if we need to return to the main loop. 300f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 301f5b6daacSRichard Henderson */ 302f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 303f5b6daacSRichard Henderson } 304f5b6daacSRichard Henderson } 305f5b6daacSRichard Henderson 306e150ac89SRoman Kapl /* 307e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 308e150ac89SRoman Kapl * SPR registers for this exception. 309e150ac89SRoman Kapl * 310e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 311e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3120e3bf489SRoman Kapl */ 313e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3140e3bf489SRoman Kapl { 3150e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3160e3bf489SRoman Kapl target_ulong dbsr = 0; 317e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3180e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 319e150ac89SRoman Kapl } else { 320e150ac89SRoman Kapl /* Must have been branch */ 3210e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3220e3bf489SRoman Kapl } 3230e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3240e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3250e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3260e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3270e3bf489SRoman Kapl tcg_temp_free(t0); 3280e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3290e3bf489SRoman Kapl } else { 330e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3310e3bf489SRoman Kapl } 3320e3bf489SRoman Kapl } 3330e3bf489SRoman Kapl 334fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 335fcf5ef2aSThomas Huth { 3362736fc61SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 3373d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 338fcf5ef2aSThomas Huth } 339fcf5ef2aSThomas Huth 340fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341fcf5ef2aSThomas Huth { 342fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 343fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344fcf5ef2aSThomas Huth } 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347fcf5ef2aSThomas Huth { 348fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349fcf5ef2aSThomas Huth } 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352fcf5ef2aSThomas Huth { 353fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 354fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 35737f219c8SBruno Larsen (billionai) /*****************************************************************************/ 35837f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 35937f219c8SBruno Larsen (billionai) 360a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36137f219c8SBruno Larsen (billionai) { 36237f219c8SBruno Larsen (billionai) #if 0 36337f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36437f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36537f219c8SBruno Larsen (billionai) #endif 36637f219c8SBruno Larsen (billionai) } 36737f219c8SBruno Larsen (billionai) 36837f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 36937f219c8SBruno Larsen (billionai) 37037f219c8SBruno Larsen (billionai) /* 37137f219c8SBruno Larsen (billionai) * Generic callbacks: 37237f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37337f219c8SBruno Larsen (billionai) */ 37437f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37537f219c8SBruno Larsen (billionai) { 37637f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 37837f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 37937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38037f219c8SBruno Larsen (billionai) #endif 38137f219c8SBruno Larsen (billionai) } 38237f219c8SBruno Larsen (billionai) 383a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38437f219c8SBruno Larsen (billionai) { 38537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38737f219c8SBruno Larsen (billionai) } 38837f219c8SBruno Larsen (billionai) 38937f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39037f219c8SBruno Larsen (billionai) { 39137f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39337f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39537f219c8SBruno Larsen (billionai) #endif 39637f219c8SBruno Larsen (billionai) } 39737f219c8SBruno Larsen (billionai) 398a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 39937f219c8SBruno Larsen (billionai) { 40037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40237f219c8SBruno Larsen (billionai) } 40337f219c8SBruno Larsen (billionai) 40437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 405a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 40637f219c8SBruno Larsen (billionai) { 40737f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 40837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 40937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 41037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 41137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 41237f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41337f219c8SBruno Larsen (billionai) #else 41437f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 41537f219c8SBruno Larsen (billionai) #endif 41637f219c8SBruno Larsen (billionai) } 41737f219c8SBruno Larsen (billionai) 418a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 41937f219c8SBruno Larsen (billionai) { 42037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 42237f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 42337f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 42437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 42537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 42837f219c8SBruno Larsen (billionai) } 42937f219c8SBruno Larsen (billionai) 430a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 43137f219c8SBruno Larsen (billionai) { 43237f219c8SBruno Larsen (billionai) } 43337f219c8SBruno Larsen (billionai) 43437f219c8SBruno Larsen (billionai) #endif 43537f219c8SBruno Larsen (billionai) 43637f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 43737f219c8SBruno Larsen (billionai) /* XER */ 438a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 43937f219c8SBruno Larsen (billionai) { 44037f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 44137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 44437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 44537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 44637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 44737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 44837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 44937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 45037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45137f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 45237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 45337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 45537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45637f219c8SBruno Larsen (billionai) } 45737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 45937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 46037f219c8SBruno Larsen (billionai) } 46137f219c8SBruno Larsen (billionai) 462a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 46337f219c8SBruno Larsen (billionai) { 46437f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 46537f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 46637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 46737f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 46837f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 46937f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 47037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 47137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 47237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 47337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 47437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 47537f219c8SBruno Larsen (billionai) } 47637f219c8SBruno Larsen (billionai) 47737f219c8SBruno Larsen (billionai) /* LR */ 478a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 47937f219c8SBruno Larsen (billionai) { 48037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 48137f219c8SBruno Larsen (billionai) } 48237f219c8SBruno Larsen (billionai) 483a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 48437f219c8SBruno Larsen (billionai) { 48537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 48637f219c8SBruno Larsen (billionai) } 48737f219c8SBruno Larsen (billionai) 48837f219c8SBruno Larsen (billionai) /* CFAR */ 48937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 490a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 49137f219c8SBruno Larsen (billionai) { 49237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 49337f219c8SBruno Larsen (billionai) } 49437f219c8SBruno Larsen (billionai) 495a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 49637f219c8SBruno Larsen (billionai) { 49737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 49837f219c8SBruno Larsen (billionai) } 49937f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 50037f219c8SBruno Larsen (billionai) 50137f219c8SBruno Larsen (billionai) /* CTR */ 502a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 50337f219c8SBruno Larsen (billionai) { 50437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 50537f219c8SBruno Larsen (billionai) } 50637f219c8SBruno Larsen (billionai) 507a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 50837f219c8SBruno Larsen (billionai) { 50937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 51037f219c8SBruno Larsen (billionai) } 51137f219c8SBruno Larsen (billionai) 51237f219c8SBruno Larsen (billionai) /* User read access to SPR */ 51337f219c8SBruno Larsen (billionai) /* USPRx */ 51437f219c8SBruno Larsen (billionai) /* UMMCRx */ 51537f219c8SBruno Larsen (billionai) /* UPMCx */ 51637f219c8SBruno Larsen (billionai) /* USIA */ 51737f219c8SBruno Larsen (billionai) /* UDECR */ 518a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 51937f219c8SBruno Larsen (billionai) { 52037f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 52137f219c8SBruno Larsen (billionai) } 52237f219c8SBruno Larsen (billionai) 52337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 524a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 52537f219c8SBruno Larsen (billionai) { 52637f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 52737f219c8SBruno Larsen (billionai) } 52837f219c8SBruno Larsen (billionai) #endif 52937f219c8SBruno Larsen (billionai) 53037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 53137f219c8SBruno Larsen (billionai) /* DECR */ 53237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 533a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 53437f219c8SBruno Larsen (billionai) { 535f5b6daacSRichard Henderson gen_icount_io_start(ctx); 53637f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 53737f219c8SBruno Larsen (billionai) } 53837f219c8SBruno Larsen (billionai) 539a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 54037f219c8SBruno Larsen (billionai) { 541f5b6daacSRichard Henderson gen_icount_io_start(ctx); 54237f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 54337f219c8SBruno Larsen (billionai) } 54437f219c8SBruno Larsen (billionai) #endif 54537f219c8SBruno Larsen (billionai) 54637f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 54737f219c8SBruno Larsen (billionai) /* Time base */ 548a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 54937f219c8SBruno Larsen (billionai) { 550f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55137f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 55237f219c8SBruno Larsen (billionai) } 55337f219c8SBruno Larsen (billionai) 554a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 55537f219c8SBruno Larsen (billionai) { 556f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55737f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 55837f219c8SBruno Larsen (billionai) } 55937f219c8SBruno Larsen (billionai) 560a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 56137f219c8SBruno Larsen (billionai) { 56237f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 56337f219c8SBruno Larsen (billionai) } 56437f219c8SBruno Larsen (billionai) 565a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 56637f219c8SBruno Larsen (billionai) { 56737f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 56837f219c8SBruno Larsen (billionai) } 56937f219c8SBruno Larsen (billionai) 57037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 571a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 57237f219c8SBruno Larsen (billionai) { 573f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57437f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 57537f219c8SBruno Larsen (billionai) } 57637f219c8SBruno Larsen (billionai) 577a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 57837f219c8SBruno Larsen (billionai) { 579f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58037f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 58137f219c8SBruno Larsen (billionai) } 58237f219c8SBruno Larsen (billionai) 583a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 58437f219c8SBruno Larsen (billionai) { 58537f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 58637f219c8SBruno Larsen (billionai) } 58737f219c8SBruno Larsen (billionai) 588a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 58937f219c8SBruno Larsen (billionai) { 59037f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 59137f219c8SBruno Larsen (billionai) } 59237f219c8SBruno Larsen (billionai) 59337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 594a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 59537f219c8SBruno Larsen (billionai) { 596f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59737f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 59837f219c8SBruno Larsen (billionai) } 59937f219c8SBruno Larsen (billionai) 600a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 60137f219c8SBruno Larsen (billionai) { 602f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60337f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 60437f219c8SBruno Larsen (billionai) } 60537f219c8SBruno Larsen (billionai) 60637f219c8SBruno Larsen (billionai) /* HDECR */ 607a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 60837f219c8SBruno Larsen (billionai) { 609f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61037f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 61137f219c8SBruno Larsen (billionai) } 61237f219c8SBruno Larsen (billionai) 613a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 61437f219c8SBruno Larsen (billionai) { 615f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61637f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 61737f219c8SBruno Larsen (billionai) } 61837f219c8SBruno Larsen (billionai) 619a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 62037f219c8SBruno Larsen (billionai) { 621f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62237f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 62337f219c8SBruno Larsen (billionai) } 62437f219c8SBruno Larsen (billionai) 625a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 62637f219c8SBruno Larsen (billionai) { 627f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62837f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 62937f219c8SBruno Larsen (billionai) } 63037f219c8SBruno Larsen (billionai) 631a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 63237f219c8SBruno Larsen (billionai) { 633f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63437f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 63537f219c8SBruno Larsen (billionai) } 63637f219c8SBruno Larsen (billionai) 63737f219c8SBruno Larsen (billionai) #endif 63837f219c8SBruno Larsen (billionai) #endif 63937f219c8SBruno Larsen (billionai) 64037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 64137f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 64237f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 643a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 64437f219c8SBruno Larsen (billionai) { 64537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 64637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 64737f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 64837f219c8SBruno Larsen (billionai) } 64937f219c8SBruno Larsen (billionai) 650a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 65137f219c8SBruno Larsen (billionai) { 65237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 65337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 65437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) 657a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 66037f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66237f219c8SBruno Larsen (billionai) } 66337f219c8SBruno Larsen (billionai) 664a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 66537f219c8SBruno Larsen (billionai) { 66637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 66737f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66937f219c8SBruno Larsen (billionai) } 67037f219c8SBruno Larsen (billionai) 671a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 67237f219c8SBruno Larsen (billionai) { 67337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 67437f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 67537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67637f219c8SBruno Larsen (billionai) } 67737f219c8SBruno Larsen (billionai) 678a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 67937f219c8SBruno Larsen (billionai) { 68037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 68137f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 68537f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 68637f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 687a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 68837f219c8SBruno Larsen (billionai) { 68937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69137f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 69237f219c8SBruno Larsen (billionai) } 69337f219c8SBruno Larsen (billionai) 694a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 69537f219c8SBruno Larsen (billionai) { 69637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69837f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 69937f219c8SBruno Larsen (billionai) } 70037f219c8SBruno Larsen (billionai) 701a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 70237f219c8SBruno Larsen (billionai) { 70337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 70437f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 70537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) 708a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 70937f219c8SBruno Larsen (billionai) { 71037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 71137f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) 715a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 71637f219c8SBruno Larsen (billionai) { 71737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 71837f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 71937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) 722a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 72337f219c8SBruno Larsen (billionai) { 72437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 72537f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 72937f219c8SBruno Larsen (billionai) /* SDR1 */ 730a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 73137f219c8SBruno Larsen (billionai) { 73237f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) } 73437f219c8SBruno Larsen (billionai) 73537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 73637f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 73737f219c8SBruno Larsen (billionai) /* PIDR */ 738a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 73937f219c8SBruno Larsen (billionai) { 74037f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 74137f219c8SBruno Larsen (billionai) } 74237f219c8SBruno Larsen (billionai) 743a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 74437f219c8SBruno Larsen (billionai) { 74537f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 74637f219c8SBruno Larsen (billionai) } 74737f219c8SBruno Larsen (billionai) 748a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 74937f219c8SBruno Larsen (billionai) { 75037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 75137f219c8SBruno Larsen (billionai) } 75237f219c8SBruno Larsen (billionai) 753a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 75437f219c8SBruno Larsen (billionai) { 75537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 75637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 75737f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 75837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 75937f219c8SBruno Larsen (billionai) } 760a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 76137f219c8SBruno Larsen (billionai) { 76237f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 76337f219c8SBruno Larsen (billionai) } 76437f219c8SBruno Larsen (billionai) 765a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 76637f219c8SBruno Larsen (billionai) { 76737f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 76837f219c8SBruno Larsen (billionai) } 76937f219c8SBruno Larsen (billionai) 77037f219c8SBruno Larsen (billionai) /* DPDES */ 771a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 77237f219c8SBruno Larsen (billionai) { 77337f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 77437f219c8SBruno Larsen (billionai) } 77537f219c8SBruno Larsen (billionai) 776a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 77737f219c8SBruno Larsen (billionai) { 77837f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 77937f219c8SBruno Larsen (billionai) } 78037f219c8SBruno Larsen (billionai) #endif 78137f219c8SBruno Larsen (billionai) #endif 78237f219c8SBruno Larsen (billionai) 78337f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 78437f219c8SBruno Larsen (billionai) /* RTC */ 785a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 78637f219c8SBruno Larsen (billionai) { 78737f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) 79537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 796a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 79737f219c8SBruno Larsen (billionai) { 79837f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 79937f219c8SBruno Larsen (billionai) } 80037f219c8SBruno Larsen (billionai) 801a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 80237f219c8SBruno Larsen (billionai) { 80337f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 80437f219c8SBruno Larsen (billionai) } 80537f219c8SBruno Larsen (billionai) 806a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 80737f219c8SBruno Larsen (billionai) { 80837f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 80937f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 810d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81137f219c8SBruno Larsen (billionai) } 81237f219c8SBruno Larsen (billionai) #endif 81337f219c8SBruno Larsen (billionai) 81437f219c8SBruno Larsen (billionai) /* Unified bats */ 81537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 816a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 81737f219c8SBruno Larsen (billionai) { 81837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 81937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 82037f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 82137f219c8SBruno Larsen (billionai) } 82237f219c8SBruno Larsen (billionai) 823a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 82437f219c8SBruno Larsen (billionai) { 82537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 82637f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 82737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 82837f219c8SBruno Larsen (billionai) } 82937f219c8SBruno Larsen (billionai) 830a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 83137f219c8SBruno Larsen (billionai) { 83237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 83337f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 83437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) #endif 83737f219c8SBruno Larsen (billionai) 83837f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 83937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 840a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 84137f219c8SBruno Larsen (billionai) { 842f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84337f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84437f219c8SBruno Larsen (billionai) } 84537f219c8SBruno Larsen (billionai) 846a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84737f219c8SBruno Larsen (billionai) { 848f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84937f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 85037f219c8SBruno Larsen (billionai) } 85137f219c8SBruno Larsen (billionai) 852a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85337f219c8SBruno Larsen (billionai) { 854f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85637f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85737f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 858d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 85937f219c8SBruno Larsen (billionai) } 86037f219c8SBruno Larsen (billionai) 861a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86237f219c8SBruno Larsen (billionai) { 863f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86437f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86537f219c8SBruno Larsen (billionai) } 86637f219c8SBruno Larsen (billionai) 867a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 86837f219c8SBruno Larsen (billionai) { 869f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 87137f219c8SBruno Larsen (billionai) } 87237f219c8SBruno Larsen (billionai) 873a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 87437f219c8SBruno Larsen (billionai) { 875f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87637f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 87737f219c8SBruno Larsen (billionai) } 87837f219c8SBruno Larsen (billionai) #endif 87937f219c8SBruno Larsen (billionai) 88037f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 88137f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 88237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 883a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 88437f219c8SBruno Larsen (billionai) { 88537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 88637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 88737f219c8SBruno Larsen (billionai) } 88837f219c8SBruno Larsen (billionai) 889a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 89037f219c8SBruno Larsen (billionai) { 89137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 89237f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 89337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89437f219c8SBruno Larsen (billionai) } 89537f219c8SBruno Larsen (billionai) 896a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 89737f219c8SBruno Larsen (billionai) { 89837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 89937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90237f219c8SBruno Larsen (billionai) } 90337f219c8SBruno Larsen (billionai) #endif 90437f219c8SBruno Larsen (billionai) 90537f219c8SBruno Larsen (billionai) /* SPE specific registers */ 906a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 90737f219c8SBruno Larsen (billionai) { 90837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 90937f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91037f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91237f219c8SBruno Larsen (billionai) } 91337f219c8SBruno Larsen (billionai) 914a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91537f219c8SBruno Larsen (billionai) { 91637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91737f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 91837f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92037f219c8SBruno Larsen (billionai) } 92137f219c8SBruno Larsen (billionai) 92237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92337f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 924a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92537f219c8SBruno Larsen (billionai) { 92637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 92837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 92937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93237f219c8SBruno Larsen (billionai) } 93337f219c8SBruno Larsen (billionai) 934a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93537f219c8SBruno Larsen (billionai) { 93637f219c8SBruno Larsen (billionai) int sprn_offs; 93737f219c8SBruno Larsen (billionai) 93837f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 93937f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 94037f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94437f219c8SBruno Larsen (billionai) } else { 94537f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 94637f219c8SBruno Larsen (billionai) sprn, sprn); 94737f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 94837f219c8SBruno Larsen (billionai) return; 94937f219c8SBruno Larsen (billionai) } 95037f219c8SBruno Larsen (billionai) 95137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 95737f219c8SBruno Larsen (billionai) } 95837f219c8SBruno Larsen (billionai) #endif 95937f219c8SBruno Larsen (billionai) 96037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 96137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 962a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96337f219c8SBruno Larsen (billionai) { 96437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96737f219c8SBruno Larsen (billionai) 96837f219c8SBruno Larsen (billionai) /* 96937f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 97037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97137f219c8SBruno Larsen (billionai) */ 97237f219c8SBruno Larsen (billionai) 97337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97437f219c8SBruno Larsen (billionai) if (ctx->pr) { 97537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97637f219c8SBruno Larsen (billionai) } else { 97737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97837f219c8SBruno Larsen (billionai) } 97937f219c8SBruno Larsen (billionai) 98037f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98237f219c8SBruno Larsen (billionai) 98337f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98437f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98537f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98637f219c8SBruno Larsen (billionai) 98737f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 98937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 99037f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 99137f219c8SBruno Larsen (billionai) 99237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 99337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 99437f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 99537f219c8SBruno Larsen (billionai) } 99637f219c8SBruno Larsen (billionai) 997a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 99837f219c8SBruno Larsen (billionai) { 99937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100237f219c8SBruno Larsen (billionai) 100337f219c8SBruno Larsen (billionai) /* 100437f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100637f219c8SBruno Larsen (billionai) */ 100737f219c8SBruno Larsen (billionai) 100837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101037f219c8SBruno Larsen (billionai) 101137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101337f219c8SBruno Larsen (billionai) 101437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101737f219c8SBruno Larsen (billionai) 101837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 102137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 102237f219c8SBruno Larsen (billionai) 102337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 102537f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 102637f219c8SBruno Larsen (billionai) } 102737f219c8SBruno Larsen (billionai) 1028a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 102937f219c8SBruno Larsen (billionai) { 103037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103337f219c8SBruno Larsen (billionai) 103437f219c8SBruno Larsen (billionai) /* 103537f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 103637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 103737f219c8SBruno Larsen (billionai) */ 103837f219c8SBruno Larsen (billionai) 103937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104137f219c8SBruno Larsen (billionai) 104237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 104437f219c8SBruno Larsen (billionai) 104537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 104637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 104737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 104837f219c8SBruno Larsen (billionai) 104937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 105237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 105337f219c8SBruno Larsen (billionai) 105437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 105637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 105737f219c8SBruno Larsen (billionai) } 105837f219c8SBruno Larsen (billionai) #endif 105937f219c8SBruno Larsen (billionai) #endif 106037f219c8SBruno Larsen (billionai) 106137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1062a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 106337f219c8SBruno Larsen (billionai) { 106437f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 106537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 106637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 106737f219c8SBruno Larsen (billionai) } 106837f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 106937f219c8SBruno Larsen (billionai) 107037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1071a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 107237f219c8SBruno Larsen (billionai) { 107337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107437f219c8SBruno Larsen (billionai) 107537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 107637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107837f219c8SBruno Larsen (billionai) } 107937f219c8SBruno Larsen (billionai) 1080a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 108137f219c8SBruno Larsen (billionai) { 108237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108337f219c8SBruno Larsen (billionai) 108437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 108537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108737f219c8SBruno Larsen (billionai) } 108837f219c8SBruno Larsen (billionai) 1089a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 109037f219c8SBruno Larsen (billionai) { 109137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109237f219c8SBruno Larsen (billionai) 109337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 109437f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 109537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109737f219c8SBruno Larsen (billionai) } 109837f219c8SBruno Larsen (billionai) 1099a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 110037f219c8SBruno Larsen (billionai) { 110137f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 110237f219c8SBruno Larsen (billionai) } 110337f219c8SBruno Larsen (billionai) 1104a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 110537f219c8SBruno Larsen (billionai) { 110637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 110737f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 110837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 110937f219c8SBruno Larsen (billionai) } 1110a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 111137f219c8SBruno Larsen (billionai) { 111237f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 111337f219c8SBruno Larsen (billionai) } 1114a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 111537f219c8SBruno Larsen (billionai) { 111637f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 111737f219c8SBruno Larsen (billionai) } 111837f219c8SBruno Larsen (billionai) 111937f219c8SBruno Larsen (billionai) #endif 112037f219c8SBruno Larsen (billionai) 112137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1122a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 112337f219c8SBruno Larsen (billionai) { 112437f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 112537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 112637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 112737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 112837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 112937f219c8SBruno Larsen (billionai) tcg_temp_free(val); 113037f219c8SBruno Larsen (billionai) } 113137f219c8SBruno Larsen (billionai) 1132a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 113337f219c8SBruno Larsen (billionai) { 113437f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 113537f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 113637f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 113737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 113837f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 113937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 114037f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 114137f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 114237f219c8SBruno Larsen (billionai) } 114337f219c8SBruno Larsen (billionai) 114437f219c8SBruno Larsen (billionai) #endif 114537f219c8SBruno Larsen (billionai) 114637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 114737f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 114837f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114937f219c8SBruno Larsen (billionai) { 115037f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 115137f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 115237f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 115337f219c8SBruno Larsen (billionai) 115437f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 115537f219c8SBruno Larsen (billionai) 115637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 115737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 115837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 115937f219c8SBruno Larsen (billionai) } 116037f219c8SBruno Larsen (billionai) 116137f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 116237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116337f219c8SBruno Larsen (billionai) { 116437f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 116537f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 116637f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 116937f219c8SBruno Larsen (billionai) 117037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 117337f219c8SBruno Larsen (billionai) } 117437f219c8SBruno Larsen (billionai) 1175a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 117637f219c8SBruno Larsen (billionai) { 117737f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 117837f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 117937f219c8SBruno Larsen (billionai) 118037f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 118237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 118337f219c8SBruno Larsen (billionai) 118437f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 118537f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 118637f219c8SBruno Larsen (billionai) } 118737f219c8SBruno Larsen (billionai) 1188a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 118937f219c8SBruno Larsen (billionai) { 119037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119137f219c8SBruno Larsen (billionai) 119237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119337f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 119437f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 119537f219c8SBruno Larsen (billionai) 119637f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 119737f219c8SBruno Larsen (billionai) } 119837f219c8SBruno Larsen (billionai) 119937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1200a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 120137f219c8SBruno Larsen (billionai) { 120237f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 120337f219c8SBruno Larsen (billionai) 120437f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 120537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 120637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 120737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 120837f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 120937f219c8SBruno Larsen (billionai) } 121037f219c8SBruno Larsen (billionai) 1211a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 121237f219c8SBruno Larsen (billionai) { 121337f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 121437f219c8SBruno Larsen (billionai) } 121537f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 121637f219c8SBruno Larsen (billionai) 1217a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 121837f219c8SBruno Larsen (billionai) { 121937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122137f219c8SBruno Larsen (billionai) } 122237f219c8SBruno Larsen (billionai) 1223a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 122437f219c8SBruno Larsen (billionai) { 122537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 122737f219c8SBruno Larsen (billionai) } 122837f219c8SBruno Larsen (billionai) 1229a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 123037f219c8SBruno Larsen (billionai) { 123137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123237f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123337f219c8SBruno Larsen (billionai) } 123437f219c8SBruno Larsen (billionai) 1235a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 123637f219c8SBruno Larsen (billionai) { 123737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123937f219c8SBruno Larsen (billionai) } 124037f219c8SBruno Larsen (billionai) 1241a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 124237f219c8SBruno Larsen (billionai) { 124337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124437f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124537f219c8SBruno Larsen (billionai) } 124637f219c8SBruno Larsen (billionai) 1247a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 124837f219c8SBruno Larsen (billionai) { 124937f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125037f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125137f219c8SBruno Larsen (billionai) } 125237f219c8SBruno Larsen (billionai) 1253a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 125437f219c8SBruno Larsen (billionai) { 125537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125737f219c8SBruno Larsen (billionai) } 125837f219c8SBruno Larsen (billionai) 1259a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 126037f219c8SBruno Larsen (billionai) { 126137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126337f219c8SBruno Larsen (billionai) } 126437f219c8SBruno Larsen (billionai) 1265a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 126637f219c8SBruno Larsen (billionai) { 126737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 126937f219c8SBruno Larsen (billionai) } 127037f219c8SBruno Larsen (billionai) 1271a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 127237f219c8SBruno Larsen (billionai) { 127337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 127537f219c8SBruno Larsen (billionai) } 127637f219c8SBruno Larsen (billionai) #endif 127737f219c8SBruno Larsen (billionai) 1278fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1279fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1280fcf5ef2aSThomas Huth 1281fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1282fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1283fcf5ef2aSThomas Huth 1284fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1285fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1286fcf5ef2aSThomas Huth 1287fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1288fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1289fcf5ef2aSThomas Huth 1290fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1291fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1292fcf5ef2aSThomas Huth 1293fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1294fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1295fcf5ef2aSThomas Huth 1296fcf5ef2aSThomas Huth typedef struct opcode_t { 1297fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1298fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1299fcf5ef2aSThomas Huth unsigned char pad[4]; 1300fcf5ef2aSThomas Huth #endif 1301fcf5ef2aSThomas Huth opc_handler_t handler; 1302fcf5ef2aSThomas Huth const char *oname; 1303fcf5ef2aSThomas Huth } opcode_t; 1304fcf5ef2aSThomas Huth 1305fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1306fcf5ef2aSThomas Huth #define GEN_PRIV \ 1307fcf5ef2aSThomas Huth do { \ 1308fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1309fcf5ef2aSThomas Huth } while (0) 1310fcf5ef2aSThomas Huth 1311fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1312fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1313fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1314fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1315fcf5ef2aSThomas Huth #else 1316fcf5ef2aSThomas Huth #define CHK_HV \ 1317fcf5ef2aSThomas Huth do { \ 1318fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1319fcf5ef2aSThomas Huth GEN_PRIV; \ 1320fcf5ef2aSThomas Huth } \ 1321fcf5ef2aSThomas Huth } while (0) 1322fcf5ef2aSThomas Huth #define CHK_SV \ 1323fcf5ef2aSThomas Huth do { \ 1324fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1325fcf5ef2aSThomas Huth GEN_PRIV; \ 1326fcf5ef2aSThomas Huth } \ 1327fcf5ef2aSThomas Huth } while (0) 1328fcf5ef2aSThomas Huth #define CHK_HVRM \ 1329fcf5ef2aSThomas Huth do { \ 1330fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1331fcf5ef2aSThomas Huth GEN_PRIV; \ 1332fcf5ef2aSThomas Huth } \ 1333fcf5ef2aSThomas Huth } while (0) 1334fcf5ef2aSThomas Huth #endif 1335fcf5ef2aSThomas Huth 1336fcf5ef2aSThomas Huth #define CHK_NONE 1337fcf5ef2aSThomas Huth 1338fcf5ef2aSThomas Huth /*****************************************************************************/ 1339fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1340fcf5ef2aSThomas Huth 1341fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1342fcf5ef2aSThomas Huth { \ 1343fcf5ef2aSThomas Huth .opc1 = op1, \ 1344fcf5ef2aSThomas Huth .opc2 = op2, \ 1345fcf5ef2aSThomas Huth .opc3 = op3, \ 1346fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1347fcf5ef2aSThomas Huth .handler = { \ 1348fcf5ef2aSThomas Huth .inval1 = invl, \ 1349fcf5ef2aSThomas Huth .type = _typ, \ 1350fcf5ef2aSThomas Huth .type2 = _typ2, \ 1351fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1352fcf5ef2aSThomas Huth }, \ 1353fcf5ef2aSThomas Huth .oname = stringify(name), \ 1354fcf5ef2aSThomas Huth } 1355fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1356fcf5ef2aSThomas Huth { \ 1357fcf5ef2aSThomas Huth .opc1 = op1, \ 1358fcf5ef2aSThomas Huth .opc2 = op2, \ 1359fcf5ef2aSThomas Huth .opc3 = op3, \ 1360fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1361fcf5ef2aSThomas Huth .handler = { \ 1362fcf5ef2aSThomas Huth .inval1 = invl1, \ 1363fcf5ef2aSThomas Huth .inval2 = invl2, \ 1364fcf5ef2aSThomas Huth .type = _typ, \ 1365fcf5ef2aSThomas Huth .type2 = _typ2, \ 1366fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1367fcf5ef2aSThomas Huth }, \ 1368fcf5ef2aSThomas Huth .oname = stringify(name), \ 1369fcf5ef2aSThomas Huth } 1370fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1371fcf5ef2aSThomas Huth { \ 1372fcf5ef2aSThomas Huth .opc1 = op1, \ 1373fcf5ef2aSThomas Huth .opc2 = op2, \ 1374fcf5ef2aSThomas Huth .opc3 = op3, \ 1375fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1376fcf5ef2aSThomas Huth .handler = { \ 1377fcf5ef2aSThomas Huth .inval1 = invl, \ 1378fcf5ef2aSThomas Huth .type = _typ, \ 1379fcf5ef2aSThomas Huth .type2 = _typ2, \ 1380fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1381fcf5ef2aSThomas Huth }, \ 1382fcf5ef2aSThomas Huth .oname = onam, \ 1383fcf5ef2aSThomas Huth } 1384fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1385fcf5ef2aSThomas Huth { \ 1386fcf5ef2aSThomas Huth .opc1 = op1, \ 1387fcf5ef2aSThomas Huth .opc2 = op2, \ 1388fcf5ef2aSThomas Huth .opc3 = op3, \ 1389fcf5ef2aSThomas Huth .opc4 = op4, \ 1390fcf5ef2aSThomas Huth .handler = { \ 1391fcf5ef2aSThomas Huth .inval1 = invl, \ 1392fcf5ef2aSThomas Huth .type = _typ, \ 1393fcf5ef2aSThomas Huth .type2 = _typ2, \ 1394fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1395fcf5ef2aSThomas Huth }, \ 1396fcf5ef2aSThomas Huth .oname = stringify(name), \ 1397fcf5ef2aSThomas Huth } 1398fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1399fcf5ef2aSThomas Huth { \ 1400fcf5ef2aSThomas Huth .opc1 = op1, \ 1401fcf5ef2aSThomas Huth .opc2 = op2, \ 1402fcf5ef2aSThomas Huth .opc3 = op3, \ 1403fcf5ef2aSThomas Huth .opc4 = op4, \ 1404fcf5ef2aSThomas Huth .handler = { \ 1405fcf5ef2aSThomas Huth .inval1 = invl, \ 1406fcf5ef2aSThomas Huth .type = _typ, \ 1407fcf5ef2aSThomas Huth .type2 = _typ2, \ 1408fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1409fcf5ef2aSThomas Huth }, \ 1410fcf5ef2aSThomas Huth .oname = onam, \ 1411fcf5ef2aSThomas Huth } 1412fcf5ef2aSThomas Huth 1413fcf5ef2aSThomas Huth /* Invalid instruction */ 1414fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1415fcf5ef2aSThomas Huth { 1416fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth 1419fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1420fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1421fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1422fcf5ef2aSThomas Huth .type = PPC_NONE, 1423fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1424fcf5ef2aSThomas Huth .handler = gen_invalid, 1425fcf5ef2aSThomas Huth }; 1426fcf5ef2aSThomas Huth 1427fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1428fcf5ef2aSThomas Huth 1429fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1430fcf5ef2aSThomas Huth { 1431fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1432b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1433b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1434fcf5ef2aSThomas Huth 1435b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1436b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1437efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1438efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1439b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1440efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1441efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1442b62b3686Spbonzini@redhat.com 1443b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1444fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1445b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1446fcf5ef2aSThomas Huth 1447fcf5ef2aSThomas Huth tcg_temp_free(t0); 1448b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1449b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1450fcf5ef2aSThomas Huth } 1451fcf5ef2aSThomas Huth 1452fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1453fcf5ef2aSThomas Huth { 1454fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1455fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1456fcf5ef2aSThomas Huth tcg_temp_free(t0); 1457fcf5ef2aSThomas Huth } 1458fcf5ef2aSThomas Huth 1459fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1460fcf5ef2aSThomas Huth { 1461fcf5ef2aSThomas Huth TCGv t0, t1; 1462fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1463fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1464fcf5ef2aSThomas Huth if (s) { 1465fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1466fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1467fcf5ef2aSThomas Huth } else { 1468fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1469fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1470fcf5ef2aSThomas Huth } 1471fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1472fcf5ef2aSThomas Huth tcg_temp_free(t1); 1473fcf5ef2aSThomas Huth tcg_temp_free(t0); 1474fcf5ef2aSThomas Huth } 1475fcf5ef2aSThomas Huth 1476fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1477fcf5ef2aSThomas Huth { 1478fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1479fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1480fcf5ef2aSThomas Huth tcg_temp_free(t0); 1481fcf5ef2aSThomas Huth } 1482fcf5ef2aSThomas Huth 1483fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1484fcf5ef2aSThomas Huth { 1485fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1486fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1487fcf5ef2aSThomas Huth } else { 1488fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1489fcf5ef2aSThomas Huth } 1490fcf5ef2aSThomas Huth } 1491fcf5ef2aSThomas Huth 1492fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1493fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1494fcf5ef2aSThomas Huth { 1495fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1496fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1497fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1498fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1499fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1500fcf5ef2aSThomas Huth 1501fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1502fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1503fcf5ef2aSThomas Huth 1504fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1505fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1506fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1507fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1508fcf5ef2aSThomas Huth 1509fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1510fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1511fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1512fcf5ef2aSThomas Huth 1513fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1514fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1515fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1516fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1517fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1518fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1519fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1520fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1521fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1522fcf5ef2aSThomas Huth } 1523efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1524fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1525fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1526fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1527fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1528fcf5ef2aSThomas Huth } 1529fcf5ef2aSThomas Huth 1530fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1531fcf5ef2aSThomas Huth /* cmpeqb */ 1532fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1533fcf5ef2aSThomas Huth { 1534fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1535fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1536fcf5ef2aSThomas Huth } 1537fcf5ef2aSThomas Huth #endif 1538fcf5ef2aSThomas Huth 1539fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1540fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1541fcf5ef2aSThomas Huth { 1542fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1543fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1544fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1545fcf5ef2aSThomas Huth TCGv zr; 1546fcf5ef2aSThomas Huth 1547fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1548fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1549fcf5ef2aSThomas Huth 1550fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1551fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1552fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1553fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1554fcf5ef2aSThomas Huth tcg_temp_free(zr); 1555fcf5ef2aSThomas Huth tcg_temp_free(t0); 1556fcf5ef2aSThomas Huth } 1557fcf5ef2aSThomas Huth 1558fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1559fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1560fcf5ef2aSThomas Huth { 1561fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1562fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1563fcf5ef2aSThomas Huth } 1564fcf5ef2aSThomas Huth 1565fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1566fcf5ef2aSThomas Huth 1567fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1568fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1569fcf5ef2aSThomas Huth { 1570fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1571fcf5ef2aSThomas Huth 1572fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1573fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1574fcf5ef2aSThomas Huth if (sub) { 1575fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1576fcf5ef2aSThomas Huth } else { 1577fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1578fcf5ef2aSThomas Huth } 1579fcf5ef2aSThomas Huth tcg_temp_free(t0); 1580fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1581dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1582dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1583dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1584fcf5ef2aSThomas Huth } 1585dc0ad844SNikunj A Dadhania } else { 1586dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1587dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1588dc0ad844SNikunj A Dadhania } 158938a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1590dc0ad844SNikunj A Dadhania } 1591fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1592fcf5ef2aSThomas Huth } 1593fcf5ef2aSThomas Huth 15946b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15956b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15964c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15976b10d008SNikunj A Dadhania { 15986b10d008SNikunj A Dadhania TCGv t0; 15996b10d008SNikunj A Dadhania 16006b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16016b10d008SNikunj A Dadhania return; 16026b10d008SNikunj A Dadhania } 16036b10d008SNikunj A Dadhania 16046b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 160533903d0aSNikunj A Dadhania if (sub) { 160633903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 160733903d0aSNikunj A Dadhania } else { 16086b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 160933903d0aSNikunj A Dadhania } 16106b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16114c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16126b10d008SNikunj A Dadhania tcg_temp_free(t0); 16136b10d008SNikunj A Dadhania } 16146b10d008SNikunj A Dadhania 1615fcf5ef2aSThomas Huth /* Common add function */ 1616fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16174c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16184c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1619fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1620fcf5ef2aSThomas Huth { 1621fcf5ef2aSThomas Huth TCGv t0 = ret; 1622fcf5ef2aSThomas Huth 1623fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1624fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1625fcf5ef2aSThomas Huth } 1626fcf5ef2aSThomas Huth 1627fcf5ef2aSThomas Huth if (compute_ca) { 1628fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1629efe843d8SDavid Gibson /* 1630efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1631efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1632efe843d8SDavid Gibson * produce the carry into bit 32. 1633efe843d8SDavid Gibson */ 1634fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1635fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1636fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1637fcf5ef2aSThomas Huth if (add_ca) { 16384c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1639fcf5ef2aSThomas Huth } 16404c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1641fcf5ef2aSThomas Huth tcg_temp_free(t1); 16424c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16436b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16444c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16456b10d008SNikunj A Dadhania } 1646fcf5ef2aSThomas Huth } else { 1647fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1648fcf5ef2aSThomas Huth if (add_ca) { 16494c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16504c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1651fcf5ef2aSThomas Huth } else { 16524c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1653fcf5ef2aSThomas Huth } 16544c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1655fcf5ef2aSThomas Huth tcg_temp_free(zero); 1656fcf5ef2aSThomas Huth } 1657fcf5ef2aSThomas Huth } else { 1658fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1659fcf5ef2aSThomas Huth if (add_ca) { 16604c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1661fcf5ef2aSThomas Huth } 1662fcf5ef2aSThomas Huth } 1663fcf5ef2aSThomas Huth 1664fcf5ef2aSThomas Huth if (compute_ov) { 1665fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1668fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1669fcf5ef2aSThomas Huth } 1670fcf5ef2aSThomas Huth 167111f4e8f8SRichard Henderson if (t0 != ret) { 1672fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1673fcf5ef2aSThomas Huth tcg_temp_free(t0); 1674fcf5ef2aSThomas Huth } 1675fcf5ef2aSThomas Huth } 1676fcf5ef2aSThomas Huth /* Add functions with two operands */ 16774c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1678fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1679fcf5ef2aSThomas Huth { \ 1680fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1681fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16824c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1683fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1684fcf5ef2aSThomas Huth } 1685fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16864c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1687fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1688fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1689fcf5ef2aSThomas Huth { \ 1690fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1691fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1692fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16934c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1694fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1695fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1696fcf5ef2aSThomas Huth } 1697fcf5ef2aSThomas Huth 1698fcf5ef2aSThomas Huth /* add add. addo addo. */ 16994c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17004c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1701fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17024c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17034c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1704fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17054c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17064c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1707fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17084c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17094c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17104c5920afSSuraj Jitindar Singh /* addex */ 17114c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1712fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17134c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17144c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1715fcf5ef2aSThomas Huth /* addic addic.*/ 1716fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1717fcf5ef2aSThomas Huth { 1718fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1719fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17204c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1721fcf5ef2aSThomas Huth tcg_temp_free(c); 1722fcf5ef2aSThomas Huth } 1723fcf5ef2aSThomas Huth 1724fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1725fcf5ef2aSThomas Huth { 1726fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1727fcf5ef2aSThomas Huth } 1728fcf5ef2aSThomas Huth 1729fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1730fcf5ef2aSThomas Huth { 1731fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1732fcf5ef2aSThomas Huth } 1733fcf5ef2aSThomas Huth 1734fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1735fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1736fcf5ef2aSThomas Huth { 1737fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1738fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1739fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1740fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1741fcf5ef2aSThomas Huth 1742fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1743fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1744fcf5ef2aSThomas Huth if (sign) { 1745fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1746fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1747fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1748fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1749fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1750fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1751fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1752fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1753fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1754fcf5ef2aSThomas Huth } else { 1755fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1756fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1757fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1758fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1759fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1760fcf5ef2aSThomas Huth } 1761fcf5ef2aSThomas Huth if (compute_ov) { 1762fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1763c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1764c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1765c44027ffSNikunj A Dadhania } 1766fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1767fcf5ef2aSThomas Huth } 1768fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1769fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1770fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1771fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1772fcf5ef2aSThomas Huth 1773efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1774fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1775fcf5ef2aSThomas Huth } 1776efe843d8SDavid Gibson } 1777fcf5ef2aSThomas Huth /* Div functions */ 1778fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1779fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1780fcf5ef2aSThomas Huth { \ 1781fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1782fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1783fcf5ef2aSThomas Huth sign, compute_ov); \ 1784fcf5ef2aSThomas Huth } 1785fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1786fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1787fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1788fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1789fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1790fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1791fcf5ef2aSThomas Huth 1792fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1793fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1794fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1795fcf5ef2aSThomas Huth { \ 1796fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1797fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1798fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1799fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1800fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1801fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1802fcf5ef2aSThomas Huth } \ 1803fcf5ef2aSThomas Huth } 1804fcf5ef2aSThomas Huth 1805fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1806fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1807fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1808fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1809fcf5ef2aSThomas Huth 1810fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1811fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1812fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1813fcf5ef2aSThomas Huth { 1814fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1815fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1816fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1817fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1818fcf5ef2aSThomas Huth 1819fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1820fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1821fcf5ef2aSThomas Huth if (sign) { 1822fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1823fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1824fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1825fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1826fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1827fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1828fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1829fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1830fcf5ef2aSThomas Huth } else { 1831fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1832fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1833fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1834fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1835fcf5ef2aSThomas Huth } 1836fcf5ef2aSThomas Huth if (compute_ov) { 1837fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1838c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1839c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1840c44027ffSNikunj A Dadhania } 1841fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1842fcf5ef2aSThomas Huth } 1843fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1844fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1845fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1846fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1847fcf5ef2aSThomas Huth 1848efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1849fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1850fcf5ef2aSThomas Huth } 1851efe843d8SDavid Gibson } 1852fcf5ef2aSThomas Huth 1853fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1854fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1855fcf5ef2aSThomas Huth { \ 1856fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1857fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1858fcf5ef2aSThomas Huth sign, compute_ov); \ 1859fcf5ef2aSThomas Huth } 1860c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1861fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1862fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1863c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1864fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1865fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1866fcf5ef2aSThomas Huth 1867fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1868fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1869fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1870fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1871fcf5ef2aSThomas Huth #endif 1872fcf5ef2aSThomas Huth 1873fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1874fcf5ef2aSThomas Huth TCGv arg2, int sign) 1875fcf5ef2aSThomas Huth { 1876fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1877fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1878fcf5ef2aSThomas Huth 1879fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1880fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1881fcf5ef2aSThomas Huth if (sign) { 1882fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1883fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1884fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1885fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1886fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1887fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1888fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1889fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1890fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1891fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1892fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1893fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1894fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1895fcf5ef2aSThomas Huth } else { 1896fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1897fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1898fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1899fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1900fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1901fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1902fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1903fcf5ef2aSThomas Huth } 1904fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1905fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1906fcf5ef2aSThomas Huth } 1907fcf5ef2aSThomas Huth 1908fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1909fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1910fcf5ef2aSThomas Huth { \ 1911fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1912fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1913fcf5ef2aSThomas Huth sign); \ 1914fcf5ef2aSThomas Huth } 1915fcf5ef2aSThomas Huth 1916fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1917fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1918fcf5ef2aSThomas Huth 1919fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1920fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1921fcf5ef2aSThomas Huth TCGv arg2, int sign) 1922fcf5ef2aSThomas Huth { 1923fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1924fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1925fcf5ef2aSThomas Huth 1926fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1927fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1928fcf5ef2aSThomas Huth if (sign) { 1929fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1930fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1931fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1932fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1933fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1934fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1935fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1936fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1937fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1938fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1939fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1940fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1941fcf5ef2aSThomas Huth } else { 1942fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1943fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1944fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1945fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1946fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1947fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1948fcf5ef2aSThomas Huth } 1949fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1950fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1951fcf5ef2aSThomas Huth } 1952fcf5ef2aSThomas Huth 1953fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1954fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1955fcf5ef2aSThomas Huth { \ 1956fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1957fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1958fcf5ef2aSThomas Huth sign); \ 1959fcf5ef2aSThomas Huth } 1960fcf5ef2aSThomas Huth 1961fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1962fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1963fcf5ef2aSThomas Huth #endif 1964fcf5ef2aSThomas Huth 1965fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1966fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1967fcf5ef2aSThomas Huth { 1968fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1969fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1970fcf5ef2aSThomas Huth 1971fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1972fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1973fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1974fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1975fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1976fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1977efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1978fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1979fcf5ef2aSThomas Huth } 1980efe843d8SDavid Gibson } 1981fcf5ef2aSThomas Huth 1982fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1983fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1984fcf5ef2aSThomas Huth { 1985fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1986fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1987fcf5ef2aSThomas Huth 1988fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1989fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1990fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1991fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1992fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1993fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1994efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1995fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1996fcf5ef2aSThomas Huth } 1997efe843d8SDavid Gibson } 1998fcf5ef2aSThomas Huth 1999fcf5ef2aSThomas Huth /* mullw mullw. */ 2000fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2001fcf5ef2aSThomas Huth { 2002fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2003fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2004fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2005fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2006fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2007fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2008fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2009fcf5ef2aSThomas Huth tcg_temp_free(t0); 2010fcf5ef2aSThomas Huth tcg_temp_free(t1); 2011fcf5ef2aSThomas Huth #else 2012fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2013fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2014fcf5ef2aSThomas Huth #endif 2015efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2016fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2017fcf5ef2aSThomas Huth } 2018efe843d8SDavid Gibson } 2019fcf5ef2aSThomas Huth 2020fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2021fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2022fcf5ef2aSThomas Huth { 2023fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2024fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2025fcf5ef2aSThomas Huth 2026fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2027fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2028fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2029fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2030fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2031fcf5ef2aSThomas Huth #else 2032fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2033fcf5ef2aSThomas Huth #endif 2034fcf5ef2aSThomas Huth 2035fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2036fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2037fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 203861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 203961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 204061aa9a69SNikunj A Dadhania } 2041fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2042fcf5ef2aSThomas Huth 2043fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2044fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2045efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2046fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2047fcf5ef2aSThomas Huth } 2048efe843d8SDavid Gibson } 2049fcf5ef2aSThomas Huth 2050fcf5ef2aSThomas Huth /* mulli */ 2051fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2052fcf5ef2aSThomas Huth { 2053fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2054fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2055fcf5ef2aSThomas Huth } 2056fcf5ef2aSThomas Huth 2057fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2058fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2059fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2060fcf5ef2aSThomas Huth { 2061fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2062fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2063fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2064fcf5ef2aSThomas Huth tcg_temp_free(lo); 2065fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2066fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2067fcf5ef2aSThomas Huth } 2068fcf5ef2aSThomas Huth } 2069fcf5ef2aSThomas Huth 2070fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2071fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2072fcf5ef2aSThomas Huth { 2073fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2074fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2075fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2076fcf5ef2aSThomas Huth tcg_temp_free(lo); 2077fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2078fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2079fcf5ef2aSThomas Huth } 2080fcf5ef2aSThomas Huth } 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth /* mulld mulld. */ 2083fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2084fcf5ef2aSThomas Huth { 2085fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2086fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2087efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2088fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2089fcf5ef2aSThomas Huth } 2090efe843d8SDavid Gibson } 2091fcf5ef2aSThomas Huth 2092fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2093fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2094fcf5ef2aSThomas Huth { 2095fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2096fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2097fcf5ef2aSThomas Huth 2098fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2099fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2100fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2101fcf5ef2aSThomas Huth 2102fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2103fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 210461aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 210561aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 210661aa9a69SNikunj A Dadhania } 2107fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2108fcf5ef2aSThomas Huth 2109fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2110fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2111fcf5ef2aSThomas Huth 2112fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2113fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2114fcf5ef2aSThomas Huth } 2115fcf5ef2aSThomas Huth } 2116fcf5ef2aSThomas Huth #endif 2117fcf5ef2aSThomas Huth 2118fcf5ef2aSThomas Huth /* Common subf function */ 2119fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2120fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2121fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2122fcf5ef2aSThomas Huth { 2123fcf5ef2aSThomas Huth TCGv t0 = ret; 2124fcf5ef2aSThomas Huth 2125fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2126fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2127fcf5ef2aSThomas Huth } 2128fcf5ef2aSThomas Huth 2129fcf5ef2aSThomas Huth if (compute_ca) { 2130fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2131fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2132efe843d8SDavid Gibson /* 2133efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2134efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2135efe843d8SDavid Gibson * produce the carry into bit 32. 2136efe843d8SDavid Gibson */ 2137fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2138fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2139fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2140fcf5ef2aSThomas Huth if (add_ca) { 2141fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2142fcf5ef2aSThomas Huth } else { 2143fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2144fcf5ef2aSThomas Huth } 2145fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2146fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2147fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2148fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2149fcf5ef2aSThomas Huth tcg_temp_free(t1); 2150e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 215133903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 215233903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 215333903d0aSNikunj A Dadhania } 2154fcf5ef2aSThomas Huth } else if (add_ca) { 2155fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2156fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2157fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2158fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2159fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21604c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2161fcf5ef2aSThomas Huth tcg_temp_free(zero); 2162fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2163fcf5ef2aSThomas Huth } else { 2164fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2165fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21664c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2167fcf5ef2aSThomas Huth } 2168fcf5ef2aSThomas Huth } else if (add_ca) { 2169efe843d8SDavid Gibson /* 2170efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2171efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2172efe843d8SDavid Gibson */ 2173fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2174fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2175fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2176fcf5ef2aSThomas Huth } else { 2177fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2178fcf5ef2aSThomas Huth } 2179fcf5ef2aSThomas Huth 2180fcf5ef2aSThomas Huth if (compute_ov) { 2181fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2182fcf5ef2aSThomas Huth } 2183fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2184fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2185fcf5ef2aSThomas Huth } 2186fcf5ef2aSThomas Huth 218711f4e8f8SRichard Henderson if (t0 != ret) { 2188fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2189fcf5ef2aSThomas Huth tcg_temp_free(t0); 2190fcf5ef2aSThomas Huth } 2191fcf5ef2aSThomas Huth } 2192fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2193fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2194fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2195fcf5ef2aSThomas Huth { \ 2196fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2197fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2198fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2199fcf5ef2aSThomas Huth } 2200fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2201fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2202fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2203fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2204fcf5ef2aSThomas Huth { \ 2205fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2206fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2207fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2208fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2209fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2210fcf5ef2aSThomas Huth } 2211fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2212fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2213fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2214fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2215fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2216fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2217fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2218fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2219fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2220fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2221fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2222fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2223fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2224fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2225fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2226fcf5ef2aSThomas Huth 2227fcf5ef2aSThomas Huth /* subfic */ 2228fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2229fcf5ef2aSThomas Huth { 2230fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2231fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2232fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2233fcf5ef2aSThomas Huth tcg_temp_free(c); 2234fcf5ef2aSThomas Huth } 2235fcf5ef2aSThomas Huth 2236fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2237fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2238fcf5ef2aSThomas Huth { 2239fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2240fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2241fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2242fcf5ef2aSThomas Huth tcg_temp_free(zero); 2243fcf5ef2aSThomas Huth } 2244fcf5ef2aSThomas Huth 2245fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2246fcf5ef2aSThomas Huth { 22471480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22481480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22491480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22501480d71cSNikunj A Dadhania } 2251fcf5ef2aSThomas Huth } 2252fcf5ef2aSThomas Huth 2253fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2254fcf5ef2aSThomas Huth { 2255fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2256fcf5ef2aSThomas Huth } 2257fcf5ef2aSThomas Huth 2258fcf5ef2aSThomas Huth /*** Integer logical ***/ 2259fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2260fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2261fcf5ef2aSThomas Huth { \ 2262fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2263fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2264fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2265fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2266fcf5ef2aSThomas Huth } 2267fcf5ef2aSThomas Huth 2268fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2269fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2270fcf5ef2aSThomas Huth { \ 2271fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2272fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2273fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2274fcf5ef2aSThomas Huth } 2275fcf5ef2aSThomas Huth 2276fcf5ef2aSThomas Huth /* and & and. */ 2277fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2278fcf5ef2aSThomas Huth /* andc & andc. */ 2279fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2280fcf5ef2aSThomas Huth 2281fcf5ef2aSThomas Huth /* andi. */ 2282fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2283fcf5ef2aSThomas Huth { 2284efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2285efe843d8SDavid Gibson UIMM(ctx->opcode)); 2286fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2287fcf5ef2aSThomas Huth } 2288fcf5ef2aSThomas Huth 2289fcf5ef2aSThomas Huth /* andis. */ 2290fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2291fcf5ef2aSThomas Huth { 2292efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2293efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2294fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2295fcf5ef2aSThomas Huth } 2296fcf5ef2aSThomas Huth 2297fcf5ef2aSThomas Huth /* cntlzw */ 2298fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2299fcf5ef2aSThomas Huth { 23009b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23019b8514e5SRichard Henderson 23029b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23039b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23049b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23059b8514e5SRichard Henderson tcg_temp_free_i32(t); 23069b8514e5SRichard Henderson 2307efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2308fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2309fcf5ef2aSThomas Huth } 2310efe843d8SDavid Gibson } 2311fcf5ef2aSThomas Huth 2312fcf5ef2aSThomas Huth /* cnttzw */ 2313fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2314fcf5ef2aSThomas Huth { 23159b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23169b8514e5SRichard Henderson 23179b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23189b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23199b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23209b8514e5SRichard Henderson tcg_temp_free_i32(t); 23219b8514e5SRichard Henderson 2322fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2323fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2324fcf5ef2aSThomas Huth } 2325fcf5ef2aSThomas Huth } 2326fcf5ef2aSThomas Huth 2327fcf5ef2aSThomas Huth /* eqv & eqv. */ 2328fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2329fcf5ef2aSThomas Huth /* extsb & extsb. */ 2330fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2331fcf5ef2aSThomas Huth /* extsh & extsh. */ 2332fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2333fcf5ef2aSThomas Huth /* nand & nand. */ 2334fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2335fcf5ef2aSThomas Huth /* nor & nor. */ 2336fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2337fcf5ef2aSThomas Huth 2338fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2339fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2340fcf5ef2aSThomas Huth { 2341fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2342fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2343fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2344fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2345fcf5ef2aSThomas Huth 2346fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2347b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2348fcf5ef2aSThomas Huth } 2349fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2350fcf5ef2aSThomas Huth 2351fcf5ef2aSThomas Huth /* or & or. */ 2352fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2353fcf5ef2aSThomas Huth { 2354fcf5ef2aSThomas Huth int rs, ra, rb; 2355fcf5ef2aSThomas Huth 2356fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2357fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2358fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2359fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2360fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2361efe843d8SDavid Gibson if (rs != rb) { 2362fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2363efe843d8SDavid Gibson } else { 2364fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2365efe843d8SDavid Gibson } 2366efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2367fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2368efe843d8SDavid Gibson } 2369fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2370fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2371fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2372fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2373fcf5ef2aSThomas Huth int prio = 0; 2374fcf5ef2aSThomas Huth 2375fcf5ef2aSThomas Huth switch (rs) { 2376fcf5ef2aSThomas Huth case 1: 2377fcf5ef2aSThomas Huth /* Set process priority to low */ 2378fcf5ef2aSThomas Huth prio = 2; 2379fcf5ef2aSThomas Huth break; 2380fcf5ef2aSThomas Huth case 6: 2381fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2382fcf5ef2aSThomas Huth prio = 3; 2383fcf5ef2aSThomas Huth break; 2384fcf5ef2aSThomas Huth case 2: 2385fcf5ef2aSThomas Huth /* Set process priority to normal */ 2386fcf5ef2aSThomas Huth prio = 4; 2387fcf5ef2aSThomas Huth break; 2388fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2389fcf5ef2aSThomas Huth case 31: 2390fcf5ef2aSThomas Huth if (!ctx->pr) { 2391fcf5ef2aSThomas Huth /* Set process priority to very low */ 2392fcf5ef2aSThomas Huth prio = 1; 2393fcf5ef2aSThomas Huth } 2394fcf5ef2aSThomas Huth break; 2395fcf5ef2aSThomas Huth case 5: 2396fcf5ef2aSThomas Huth if (!ctx->pr) { 2397fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2398fcf5ef2aSThomas Huth prio = 5; 2399fcf5ef2aSThomas Huth } 2400fcf5ef2aSThomas Huth break; 2401fcf5ef2aSThomas Huth case 3: 2402fcf5ef2aSThomas Huth if (!ctx->pr) { 2403fcf5ef2aSThomas Huth /* Set process priority to high */ 2404fcf5ef2aSThomas Huth prio = 6; 2405fcf5ef2aSThomas Huth } 2406fcf5ef2aSThomas Huth break; 2407fcf5ef2aSThomas Huth case 7: 2408fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2409fcf5ef2aSThomas Huth /* Set process priority to very high */ 2410fcf5ef2aSThomas Huth prio = 7; 2411fcf5ef2aSThomas Huth } 2412fcf5ef2aSThomas Huth break; 2413fcf5ef2aSThomas Huth #endif 2414fcf5ef2aSThomas Huth default: 2415fcf5ef2aSThomas Huth break; 2416fcf5ef2aSThomas Huth } 2417fcf5ef2aSThomas Huth if (prio) { 2418fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2419fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2420fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2421fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2422fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2423fcf5ef2aSThomas Huth tcg_temp_free(t0); 2424fcf5ef2aSThomas Huth } 2425fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2426efe843d8SDavid Gibson /* 2427efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2428efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2429efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2430efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2431fcf5ef2aSThomas Huth */ 2432fcf5ef2aSThomas Huth gen_pause(ctx); 2433fcf5ef2aSThomas Huth #endif 2434fcf5ef2aSThomas Huth #endif 2435fcf5ef2aSThomas Huth } 2436fcf5ef2aSThomas Huth } 2437fcf5ef2aSThomas Huth /* orc & orc. */ 2438fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2439fcf5ef2aSThomas Huth 2440fcf5ef2aSThomas Huth /* xor & xor. */ 2441fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2442fcf5ef2aSThomas Huth { 2443fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2444efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2445efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2446efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2447efe843d8SDavid Gibson } else { 2448fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2449efe843d8SDavid Gibson } 2450efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2451fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2452fcf5ef2aSThomas Huth } 2453efe843d8SDavid Gibson } 2454fcf5ef2aSThomas Huth 2455fcf5ef2aSThomas Huth /* ori */ 2456fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2457fcf5ef2aSThomas Huth { 2458fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2459fcf5ef2aSThomas Huth 2460fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2461fcf5ef2aSThomas Huth return; 2462fcf5ef2aSThomas Huth } 2463fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2464fcf5ef2aSThomas Huth } 2465fcf5ef2aSThomas Huth 2466fcf5ef2aSThomas Huth /* oris */ 2467fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2468fcf5ef2aSThomas Huth { 2469fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2470fcf5ef2aSThomas Huth 2471fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2472fcf5ef2aSThomas Huth /* NOP */ 2473fcf5ef2aSThomas Huth return; 2474fcf5ef2aSThomas Huth } 2475efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2476efe843d8SDavid Gibson uimm << 16); 2477fcf5ef2aSThomas Huth } 2478fcf5ef2aSThomas Huth 2479fcf5ef2aSThomas Huth /* xori */ 2480fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2481fcf5ef2aSThomas Huth { 2482fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2483fcf5ef2aSThomas Huth 2484fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2485fcf5ef2aSThomas Huth /* NOP */ 2486fcf5ef2aSThomas Huth return; 2487fcf5ef2aSThomas Huth } 2488fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2489fcf5ef2aSThomas Huth } 2490fcf5ef2aSThomas Huth 2491fcf5ef2aSThomas Huth /* xoris */ 2492fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2493fcf5ef2aSThomas Huth { 2494fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2495fcf5ef2aSThomas Huth 2496fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2497fcf5ef2aSThomas Huth /* NOP */ 2498fcf5ef2aSThomas Huth return; 2499fcf5ef2aSThomas Huth } 2500efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2501efe843d8SDavid Gibson uimm << 16); 2502fcf5ef2aSThomas Huth } 2503fcf5ef2aSThomas Huth 2504fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2505fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2506fcf5ef2aSThomas Huth { 2507fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2508fcf5ef2aSThomas Huth } 2509fcf5ef2aSThomas Huth 2510fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2511fcf5ef2aSThomas Huth { 251279770002SRichard Henderson #if defined(TARGET_PPC64) 2513fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251479770002SRichard Henderson #else 251579770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251679770002SRichard Henderson #endif 2517fcf5ef2aSThomas Huth } 2518fcf5ef2aSThomas Huth 2519fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2520fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2521fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2522fcf5ef2aSThomas Huth { 252379770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2524fcf5ef2aSThomas Huth } 2525fcf5ef2aSThomas Huth #endif 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2528fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2529fcf5ef2aSThomas Huth { 2530fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2531fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2532fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2533fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2534fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2535fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2536fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2537fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2538fcf5ef2aSThomas Huth tcg_temp_free(t0); 2539fcf5ef2aSThomas Huth } 2540fcf5ef2aSThomas Huth 2541fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2542fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2543fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2544fcf5ef2aSThomas Huth { 2545fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2546fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2547fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2548fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2549fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2550fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2551fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2552fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2553fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2554fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2555fcf5ef2aSThomas Huth tcg_temp_free(t0); 2556fcf5ef2aSThomas Huth } 2557fcf5ef2aSThomas Huth #endif 2558fcf5ef2aSThomas Huth 2559fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2560fcf5ef2aSThomas Huth /* bpermd */ 2561fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2562fcf5ef2aSThomas Huth { 2563fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2564fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2565fcf5ef2aSThomas Huth } 2566fcf5ef2aSThomas Huth #endif 2567fcf5ef2aSThomas Huth 2568fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2569fcf5ef2aSThomas Huth /* extsw & extsw. */ 2570fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2571fcf5ef2aSThomas Huth 2572fcf5ef2aSThomas Huth /* cntlzd */ 2573fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2574fcf5ef2aSThomas Huth { 25759b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2576efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2577fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2578fcf5ef2aSThomas Huth } 2579efe843d8SDavid Gibson } 2580fcf5ef2aSThomas Huth 2581fcf5ef2aSThomas Huth /* cnttzd */ 2582fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2583fcf5ef2aSThomas Huth { 25849b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2585fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2586fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2587fcf5ef2aSThomas Huth } 2588fcf5ef2aSThomas Huth } 2589fcf5ef2aSThomas Huth 2590fcf5ef2aSThomas Huth /* darn */ 2591fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2592fcf5ef2aSThomas Huth { 2593fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2594fcf5ef2aSThomas Huth 25957e4357f6SRichard Henderson if (l > 2) { 25967e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25977e4357f6SRichard Henderson } else { 2598f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2599fcf5ef2aSThomas Huth if (l == 0) { 2600fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26017e4357f6SRichard Henderson } else { 2602fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2603fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26047e4357f6SRichard Henderson } 2605fcf5ef2aSThomas Huth } 2606fcf5ef2aSThomas Huth } 2607fcf5ef2aSThomas Huth #endif 2608fcf5ef2aSThomas Huth 2609fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2610fcf5ef2aSThomas Huth 2611fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2612fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2613fcf5ef2aSThomas Huth { 2614fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2615fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2616fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2617fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2618fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2619fcf5ef2aSThomas Huth 2620fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2621fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2622fcf5ef2aSThomas Huth } else { 2623fcf5ef2aSThomas Huth target_ulong mask; 2624c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2625fcf5ef2aSThomas Huth TCGv t1; 2626fcf5ef2aSThomas Huth 2627fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2628fcf5ef2aSThomas Huth mb += 32; 2629fcf5ef2aSThomas Huth me += 32; 2630fcf5ef2aSThomas Huth #endif 2631fcf5ef2aSThomas Huth mask = MASK(mb, me); 2632fcf5ef2aSThomas Huth 2633c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2634c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2635c4f6a4a3SDaniele Buono mask_in_32b = false; 2636c4f6a4a3SDaniele Buono } 2637c4f6a4a3SDaniele Buono #endif 2638fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2639c4f6a4a3SDaniele Buono if (mask_in_32b) { 2640fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2641fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2642fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2643fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2644fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2645fcf5ef2aSThomas Huth } else { 2646fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2647fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2648fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2649fcf5ef2aSThomas Huth #else 2650fcf5ef2aSThomas Huth g_assert_not_reached(); 2651fcf5ef2aSThomas Huth #endif 2652fcf5ef2aSThomas Huth } 2653fcf5ef2aSThomas Huth 2654fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2655fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2656fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2657fcf5ef2aSThomas Huth tcg_temp_free(t1); 2658fcf5ef2aSThomas Huth } 2659fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2660fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2661fcf5ef2aSThomas Huth } 2662fcf5ef2aSThomas Huth } 2663fcf5ef2aSThomas Huth 2664fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2665fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2666fcf5ef2aSThomas Huth { 2667fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2668fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26697b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26707b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26717b4d326fSRichard Henderson int me = ME(ctx->opcode); 26727b4d326fSRichard Henderson int len = me - mb + 1; 26737b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2674fcf5ef2aSThomas Huth 26757b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26767b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26777b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26787b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2679fcf5ef2aSThomas Huth } else { 2680fcf5ef2aSThomas Huth target_ulong mask; 2681c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2682fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2683fcf5ef2aSThomas Huth mb += 32; 2684fcf5ef2aSThomas Huth me += 32; 2685fcf5ef2aSThomas Huth #endif 2686fcf5ef2aSThomas Huth mask = MASK(mb, me); 2687c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2688c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2689c4f6a4a3SDaniele Buono mask_in_32b = false; 2690c4f6a4a3SDaniele Buono } 2691c4f6a4a3SDaniele Buono #endif 2692c4f6a4a3SDaniele Buono if (mask_in_32b) { 26937b4d326fSRichard Henderson if (sh == 0) { 26947b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 269594f040aaSVitaly Chikunov } else { 2696fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2697fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2698fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2699fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2700fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2701fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 270294f040aaSVitaly Chikunov } 2703fcf5ef2aSThomas Huth } else { 2704fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2705fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2706fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2707fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2708fcf5ef2aSThomas Huth #else 2709fcf5ef2aSThomas Huth g_assert_not_reached(); 2710fcf5ef2aSThomas Huth #endif 2711fcf5ef2aSThomas Huth } 2712fcf5ef2aSThomas Huth } 2713fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2714fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2715fcf5ef2aSThomas Huth } 2716fcf5ef2aSThomas Huth } 2717fcf5ef2aSThomas Huth 2718fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2719fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2720fcf5ef2aSThomas Huth { 2721fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2722fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2723fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2724fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2725fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2726fcf5ef2aSThomas Huth target_ulong mask; 2727c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2728fcf5ef2aSThomas Huth 2729fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2730fcf5ef2aSThomas Huth mb += 32; 2731fcf5ef2aSThomas Huth me += 32; 2732fcf5ef2aSThomas Huth #endif 2733fcf5ef2aSThomas Huth mask = MASK(mb, me); 2734fcf5ef2aSThomas Huth 2735c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2736c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2737c4f6a4a3SDaniele Buono mask_in_32b = false; 2738c4f6a4a3SDaniele Buono } 2739c4f6a4a3SDaniele Buono #endif 2740c4f6a4a3SDaniele Buono if (mask_in_32b) { 2741fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2742fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2743fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2744fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2745fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2746fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2747fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2748fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2749fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2750fcf5ef2aSThomas Huth } else { 2751fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2752fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2753fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2754fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2755fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2756fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2757fcf5ef2aSThomas Huth #else 2758fcf5ef2aSThomas Huth g_assert_not_reached(); 2759fcf5ef2aSThomas Huth #endif 2760fcf5ef2aSThomas Huth } 2761fcf5ef2aSThomas Huth 2762fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2763fcf5ef2aSThomas Huth 2764fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2765fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2766fcf5ef2aSThomas Huth } 2767fcf5ef2aSThomas Huth } 2768fcf5ef2aSThomas Huth 2769fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2770fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2771fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2772fcf5ef2aSThomas Huth { \ 2773fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2774fcf5ef2aSThomas Huth } \ 2775fcf5ef2aSThomas Huth \ 2776fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2777fcf5ef2aSThomas Huth { \ 2778fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2779fcf5ef2aSThomas Huth } 2780fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2781fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2782fcf5ef2aSThomas Huth { \ 2783fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2784fcf5ef2aSThomas Huth } \ 2785fcf5ef2aSThomas Huth \ 2786fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2787fcf5ef2aSThomas Huth { \ 2788fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2789fcf5ef2aSThomas Huth } \ 2790fcf5ef2aSThomas Huth \ 2791fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2792fcf5ef2aSThomas Huth { \ 2793fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2794fcf5ef2aSThomas Huth } \ 2795fcf5ef2aSThomas Huth \ 2796fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2797fcf5ef2aSThomas Huth { \ 2798fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2799fcf5ef2aSThomas Huth } 2800fcf5ef2aSThomas Huth 2801fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2802fcf5ef2aSThomas Huth { 2803fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2804fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28057b4d326fSRichard Henderson int len = me - mb + 1; 28067b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2807fcf5ef2aSThomas Huth 28087b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28097b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28107b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28117b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2812fcf5ef2aSThomas Huth } else { 2813fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2814fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2815fcf5ef2aSThomas Huth } 2816fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2817fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2818fcf5ef2aSThomas Huth } 2819fcf5ef2aSThomas Huth } 2820fcf5ef2aSThomas Huth 2821fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2822fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2823fcf5ef2aSThomas Huth { 2824fcf5ef2aSThomas Huth uint32_t sh, mb; 2825fcf5ef2aSThomas Huth 2826fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2827fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2828fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2829fcf5ef2aSThomas Huth } 2830fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2831fcf5ef2aSThomas Huth 2832fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2833fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2834fcf5ef2aSThomas Huth { 2835fcf5ef2aSThomas Huth uint32_t sh, me; 2836fcf5ef2aSThomas Huth 2837fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2838fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2839fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2840fcf5ef2aSThomas Huth } 2841fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2842fcf5ef2aSThomas Huth 2843fcf5ef2aSThomas Huth /* rldic - rldic. */ 2844fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2845fcf5ef2aSThomas Huth { 2846fcf5ef2aSThomas Huth uint32_t sh, mb; 2847fcf5ef2aSThomas Huth 2848fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2849fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2850fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2851fcf5ef2aSThomas Huth } 2852fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2853fcf5ef2aSThomas Huth 2854fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2855fcf5ef2aSThomas Huth { 2856fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2857fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2858fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2859fcf5ef2aSThomas Huth TCGv t0; 2860fcf5ef2aSThomas Huth 2861fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2862fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2863fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2864fcf5ef2aSThomas Huth tcg_temp_free(t0); 2865fcf5ef2aSThomas Huth 2866fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2867fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2868fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2869fcf5ef2aSThomas Huth } 2870fcf5ef2aSThomas Huth } 2871fcf5ef2aSThomas Huth 2872fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2873fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2874fcf5ef2aSThomas Huth { 2875fcf5ef2aSThomas Huth uint32_t mb; 2876fcf5ef2aSThomas Huth 2877fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2878fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2879fcf5ef2aSThomas Huth } 2880fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2881fcf5ef2aSThomas Huth 2882fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2883fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2884fcf5ef2aSThomas Huth { 2885fcf5ef2aSThomas Huth uint32_t me; 2886fcf5ef2aSThomas Huth 2887fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2888fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2889fcf5ef2aSThomas Huth } 2890fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2891fcf5ef2aSThomas Huth 2892fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2893fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2894fcf5ef2aSThomas Huth { 2895fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2896fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2897fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2898fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2899fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2900fcf5ef2aSThomas Huth 2901fcf5ef2aSThomas Huth if (mb <= me) { 2902fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2903fcf5ef2aSThomas Huth } else { 2904fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2905fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2906fcf5ef2aSThomas Huth 2907fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2908fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2909fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2910fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2911fcf5ef2aSThomas Huth tcg_temp_free(t1); 2912fcf5ef2aSThomas Huth } 2913fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2914fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2915fcf5ef2aSThomas Huth } 2916fcf5ef2aSThomas Huth } 2917fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2918fcf5ef2aSThomas Huth #endif 2919fcf5ef2aSThomas Huth 2920fcf5ef2aSThomas Huth /*** Integer shift ***/ 2921fcf5ef2aSThomas Huth 2922fcf5ef2aSThomas Huth /* slw & slw. */ 2923fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2924fcf5ef2aSThomas Huth { 2925fcf5ef2aSThomas Huth TCGv t0, t1; 2926fcf5ef2aSThomas Huth 2927fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2928fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2929fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2930fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2931fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2932fcf5ef2aSThomas Huth #else 2933fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2934fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2935fcf5ef2aSThomas Huth #endif 2936fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2937fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2938fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2939fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2940fcf5ef2aSThomas Huth tcg_temp_free(t1); 2941fcf5ef2aSThomas Huth tcg_temp_free(t0); 2942fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2943efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2944fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2945fcf5ef2aSThomas Huth } 2946efe843d8SDavid Gibson } 2947fcf5ef2aSThomas Huth 2948fcf5ef2aSThomas Huth /* sraw & sraw. */ 2949fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2950fcf5ef2aSThomas Huth { 2951fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2952fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2953efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2954fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2955fcf5ef2aSThomas Huth } 2956efe843d8SDavid Gibson } 2957fcf5ef2aSThomas Huth 2958fcf5ef2aSThomas Huth /* srawi & srawi. */ 2959fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2960fcf5ef2aSThomas Huth { 2961fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2962fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2963fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2964fcf5ef2aSThomas Huth if (sh == 0) { 2965fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2966fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2967af1c259fSSandipan Das if (is_isa300(ctx)) { 2968af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2969af1c259fSSandipan Das } 2970fcf5ef2aSThomas Huth } else { 2971fcf5ef2aSThomas Huth TCGv t0; 2972fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2973fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2974fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2975fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2976fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2977fcf5ef2aSThomas Huth tcg_temp_free(t0); 2978fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2979af1c259fSSandipan Das if (is_isa300(ctx)) { 2980af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2981af1c259fSSandipan Das } 2982fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2983fcf5ef2aSThomas Huth } 2984fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2985fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2986fcf5ef2aSThomas Huth } 2987fcf5ef2aSThomas Huth } 2988fcf5ef2aSThomas Huth 2989fcf5ef2aSThomas Huth /* srw & srw. */ 2990fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2991fcf5ef2aSThomas Huth { 2992fcf5ef2aSThomas Huth TCGv t0, t1; 2993fcf5ef2aSThomas Huth 2994fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2995fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2996fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2997fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2998fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2999fcf5ef2aSThomas Huth #else 3000fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3001fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3002fcf5ef2aSThomas Huth #endif 3003fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3004fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3005fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3006fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3007fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3008fcf5ef2aSThomas Huth tcg_temp_free(t1); 3009fcf5ef2aSThomas Huth tcg_temp_free(t0); 3010efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3011fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3012fcf5ef2aSThomas Huth } 3013efe843d8SDavid Gibson } 3014fcf5ef2aSThomas Huth 3015fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3016fcf5ef2aSThomas Huth /* sld & sld. */ 3017fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3018fcf5ef2aSThomas Huth { 3019fcf5ef2aSThomas Huth TCGv t0, t1; 3020fcf5ef2aSThomas Huth 3021fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3022fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3023fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3024fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3025fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3026fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3027fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3028fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3029fcf5ef2aSThomas Huth tcg_temp_free(t1); 3030fcf5ef2aSThomas Huth tcg_temp_free(t0); 3031efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3032fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3033fcf5ef2aSThomas Huth } 3034efe843d8SDavid Gibson } 3035fcf5ef2aSThomas Huth 3036fcf5ef2aSThomas Huth /* srad & srad. */ 3037fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3038fcf5ef2aSThomas Huth { 3039fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3040fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3041efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3042fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3043fcf5ef2aSThomas Huth } 3044efe843d8SDavid Gibson } 3045fcf5ef2aSThomas Huth /* sradi & sradi. */ 3046fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3047fcf5ef2aSThomas Huth { 3048fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3049fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3050fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3051fcf5ef2aSThomas Huth if (sh == 0) { 3052fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3053fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3054af1c259fSSandipan Das if (is_isa300(ctx)) { 3055af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3056af1c259fSSandipan Das } 3057fcf5ef2aSThomas Huth } else { 3058fcf5ef2aSThomas Huth TCGv t0; 3059fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3060fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3061fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3062fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3063fcf5ef2aSThomas Huth tcg_temp_free(t0); 3064fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3065af1c259fSSandipan Das if (is_isa300(ctx)) { 3066af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3067af1c259fSSandipan Das } 3068fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3069fcf5ef2aSThomas Huth } 3070fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3071fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3072fcf5ef2aSThomas Huth } 3073fcf5ef2aSThomas Huth } 3074fcf5ef2aSThomas Huth 3075fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3076fcf5ef2aSThomas Huth { 3077fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3078fcf5ef2aSThomas Huth } 3079fcf5ef2aSThomas Huth 3080fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3081fcf5ef2aSThomas Huth { 3082fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth 3085fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3086fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3087fcf5ef2aSThomas Huth { 3088fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3089fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3090fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3091fcf5ef2aSThomas Huth 3092fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3093fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3094fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3095fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3096fcf5ef2aSThomas Huth } 3097fcf5ef2aSThomas Huth } 3098fcf5ef2aSThomas Huth 3099fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3100fcf5ef2aSThomas Huth { 3101fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3102fcf5ef2aSThomas Huth } 3103fcf5ef2aSThomas Huth 3104fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3105fcf5ef2aSThomas Huth { 3106fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3107fcf5ef2aSThomas Huth } 3108fcf5ef2aSThomas Huth 3109fcf5ef2aSThomas Huth /* srd & srd. */ 3110fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3111fcf5ef2aSThomas Huth { 3112fcf5ef2aSThomas Huth TCGv t0, t1; 3113fcf5ef2aSThomas Huth 3114fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3115fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3116fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3117fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3118fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3119fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3120fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3121fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3122fcf5ef2aSThomas Huth tcg_temp_free(t1); 3123fcf5ef2aSThomas Huth tcg_temp_free(t0); 3124efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3125fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3126fcf5ef2aSThomas Huth } 3127efe843d8SDavid Gibson } 3128fcf5ef2aSThomas Huth #endif 3129fcf5ef2aSThomas Huth 3130fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3131fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3132fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3133fcf5ef2aSThomas Huth target_long maskl) 3134fcf5ef2aSThomas Huth { 3135fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3136fcf5ef2aSThomas Huth 3137fcf5ef2aSThomas Huth simm &= ~maskl; 3138fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3139fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3140fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3141fcf5ef2aSThomas Huth } 3142fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3143fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3144fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3145fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3146fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3147fcf5ef2aSThomas Huth } 3148fcf5ef2aSThomas Huth } else { 3149fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3150fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3151fcf5ef2aSThomas Huth } else { 3152fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3153fcf5ef2aSThomas Huth } 3154fcf5ef2aSThomas Huth } 3155fcf5ef2aSThomas Huth } 3156fcf5ef2aSThomas Huth 3157fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3158fcf5ef2aSThomas Huth { 3159fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3160fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3161fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3162fcf5ef2aSThomas Huth } else { 3163fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3164fcf5ef2aSThomas Huth } 3165fcf5ef2aSThomas Huth } else { 3166fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3167fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3168fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3169fcf5ef2aSThomas Huth } 3170fcf5ef2aSThomas Huth } 3171fcf5ef2aSThomas Huth } 3172fcf5ef2aSThomas Huth 3173fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3174fcf5ef2aSThomas Huth { 3175fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3176fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3177fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3178fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3179fcf5ef2aSThomas Huth } else { 3180fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3181fcf5ef2aSThomas Huth } 3182fcf5ef2aSThomas Huth } 3183fcf5ef2aSThomas Huth 3184fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3185fcf5ef2aSThomas Huth target_long val) 3186fcf5ef2aSThomas Huth { 3187fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3188fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3189fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3190fcf5ef2aSThomas Huth } 3191fcf5ef2aSThomas Huth } 3192fcf5ef2aSThomas Huth 3193fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3194fcf5ef2aSThomas Huth { 3195fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3196fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3197fcf5ef2aSThomas Huth } 3198fcf5ef2aSThomas Huth 3199fcf5ef2aSThomas Huth /*** Integer load ***/ 3200fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3201fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3202fcf5ef2aSThomas Huth 3203fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3204fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3205fcf5ef2aSThomas Huth TCGv val, \ 3206fcf5ef2aSThomas Huth TCGv addr) \ 3207fcf5ef2aSThomas Huth { \ 3208fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3209fcf5ef2aSThomas Huth } 3210fcf5ef2aSThomas Huth 3211fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3212fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3213fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3214fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3215fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3216fcf5ef2aSThomas Huth 3217fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3218fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3219fcf5ef2aSThomas Huth 3220fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3221fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3222fcf5ef2aSThomas Huth TCGv_i64 val, \ 3223fcf5ef2aSThomas Huth TCGv addr) \ 3224fcf5ef2aSThomas Huth { \ 3225fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3226fcf5ef2aSThomas Huth } 3227fcf5ef2aSThomas Huth 3228fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3229fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3230fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3231fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3232fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3233fcf5ef2aSThomas Huth 3234fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3235fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3236fcf5ef2aSThomas Huth #endif 3237fcf5ef2aSThomas Huth 3238fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3239fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3240fcf5ef2aSThomas Huth TCGv val, \ 3241fcf5ef2aSThomas Huth TCGv addr) \ 3242fcf5ef2aSThomas Huth { \ 3243fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3244fcf5ef2aSThomas Huth } 3245fcf5ef2aSThomas Huth 3246e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3247fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3248e8f4c8d6SRichard Henderson #endif 3249fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3250fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3251fcf5ef2aSThomas Huth 3252fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3253fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3254fcf5ef2aSThomas Huth 3255fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3256fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3257fcf5ef2aSThomas Huth TCGv_i64 val, \ 3258fcf5ef2aSThomas Huth TCGv addr) \ 3259fcf5ef2aSThomas Huth { \ 3260fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3261fcf5ef2aSThomas Huth } 3262fcf5ef2aSThomas Huth 3263fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3264fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3265fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3266fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3267fcf5ef2aSThomas Huth 3268fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3269fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3270fcf5ef2aSThomas Huth #endif 3271fcf5ef2aSThomas Huth 3272fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3273fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3274fcf5ef2aSThomas Huth { \ 3275fcf5ef2aSThomas Huth TCGv EA; \ 3276fcf5ef2aSThomas Huth chk; \ 3277fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3278fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3279fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3280fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3281fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3282fcf5ef2aSThomas Huth } 3283fcf5ef2aSThomas Huth 3284fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3285fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3286fcf5ef2aSThomas Huth 3287fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3288fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3289fcf5ef2aSThomas Huth 329050728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 329150728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 329250728199SRoman Kapl { \ 329350728199SRoman Kapl TCGv EA; \ 329450728199SRoman Kapl CHK_SV; \ 329550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 329650728199SRoman Kapl EA = tcg_temp_new(); \ 329750728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 329850728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 329950728199SRoman Kapl tcg_temp_free(EA); \ 330050728199SRoman Kapl } 330150728199SRoman Kapl 330250728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 330350728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 330450728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 330550728199SRoman Kapl #if defined(TARGET_PPC64) 330650728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 330750728199SRoman Kapl #endif 330850728199SRoman Kapl 3309fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3310fcf5ef2aSThomas Huth /* CI load/store variants */ 3311fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3312fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3313fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3314fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3315fcf5ef2aSThomas Huth 3316fcf5ef2aSThomas Huth /* lq */ 3317fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3318fcf5ef2aSThomas Huth { 3319fcf5ef2aSThomas Huth int ra, rd; 332094bf2658SRichard Henderson TCGv EA, hi, lo; 3321fcf5ef2aSThomas Huth 3322fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3323fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3324fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3325fcf5ef2aSThomas Huth 3326fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3327fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3328fcf5ef2aSThomas Huth return; 3329fcf5ef2aSThomas Huth } 3330fcf5ef2aSThomas Huth 3331fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3332fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3333fcf5ef2aSThomas Huth return; 3334fcf5ef2aSThomas Huth } 3335fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3336fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3337fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3338fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3339fcf5ef2aSThomas Huth return; 3340fcf5ef2aSThomas Huth } 3341fcf5ef2aSThomas Huth 3342fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3343fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3344fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3345fcf5ef2aSThomas Huth 334694bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 334794bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 334894bf2658SRichard Henderson hi = cpu_gpr[rd]; 334994bf2658SRichard Henderson 335094bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3351f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 335294bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 335394bf2658SRichard Henderson if (ctx->le_mode) { 335494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 335594bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3356fcf5ef2aSThomas Huth } else { 335794bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 335894bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 335994bf2658SRichard Henderson } 336094bf2658SRichard Henderson tcg_temp_free_i32(oi); 336194bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3362f34ec0f6SRichard Henderson } else { 336394bf2658SRichard Henderson /* Restart with exclusive lock. */ 336494bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 336594bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3366f34ec0f6SRichard Henderson } 336794bf2658SRichard Henderson } else if (ctx->le_mode) { 336894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3369fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 337094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 337194bf2658SRichard Henderson } else { 337294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 337394bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 337494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3375fcf5ef2aSThomas Huth } 3376fcf5ef2aSThomas Huth tcg_temp_free(EA); 3377fcf5ef2aSThomas Huth } 3378fcf5ef2aSThomas Huth #endif 3379fcf5ef2aSThomas Huth 3380fcf5ef2aSThomas Huth /*** Integer store ***/ 3381fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3382fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3383fcf5ef2aSThomas Huth { \ 3384fcf5ef2aSThomas Huth TCGv EA; \ 3385fcf5ef2aSThomas Huth chk; \ 3386fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3387fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3388fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3389fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3390fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3391fcf5ef2aSThomas Huth } 3392fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3393fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3394fcf5ef2aSThomas Huth 3395fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3396fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3397fcf5ef2aSThomas Huth 339850728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 339950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 340050728199SRoman Kapl { \ 340150728199SRoman Kapl TCGv EA; \ 340250728199SRoman Kapl CHK_SV; \ 340350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 340450728199SRoman Kapl EA = tcg_temp_new(); \ 340550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 340650728199SRoman Kapl tcg_gen_qemu_st_tl( \ 340750728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 340850728199SRoman Kapl tcg_temp_free(EA); \ 340950728199SRoman Kapl } 341050728199SRoman Kapl 341150728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 341250728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 341350728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 341450728199SRoman Kapl #if defined(TARGET_PPC64) 341550728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 341650728199SRoman Kapl #endif 341750728199SRoman Kapl 3418fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3419fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3420fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3421fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3422fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3423fcf5ef2aSThomas Huth 3424fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3425fcf5ef2aSThomas Huth { 3426fcf5ef2aSThomas Huth int rs; 3427fcf5ef2aSThomas Huth TCGv EA; 3428fcf5ef2aSThomas Huth 3429fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3430fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3431fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3432fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3433f89ced5fSRichard Henderson TCGv hi, lo; 3434fcf5ef2aSThomas Huth 3435fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3436fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3437fcf5ef2aSThomas Huth } 3438fcf5ef2aSThomas Huth 3439fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3440fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3441fcf5ef2aSThomas Huth return; 3442fcf5ef2aSThomas Huth } 3443fcf5ef2aSThomas Huth 3444fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3445fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3446fcf5ef2aSThomas Huth return; 3447fcf5ef2aSThomas Huth } 3448fcf5ef2aSThomas Huth 3449fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3450fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3451fcf5ef2aSThomas Huth return; 3452fcf5ef2aSThomas Huth } 3453fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3454fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3455fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3456fcf5ef2aSThomas Huth 3457f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3458f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3459f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3460f89ced5fSRichard Henderson 3461f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3462f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3463f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3464f89ced5fSRichard Henderson if (ctx->le_mode) { 3465f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3466f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3467fcf5ef2aSThomas Huth } else { 3468f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3469f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3470f89ced5fSRichard Henderson } 3471f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3472f34ec0f6SRichard Henderson } else { 3473f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3474f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3475f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3476f34ec0f6SRichard Henderson } 3477f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3478f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3479fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3480f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3481f89ced5fSRichard Henderson } else { 3482f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3483f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3484f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3485fcf5ef2aSThomas Huth } 3486fcf5ef2aSThomas Huth tcg_temp_free(EA); 3487fcf5ef2aSThomas Huth } else { 3488fcf5ef2aSThomas Huth /* std / stdu */ 3489fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3490fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3491fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3492fcf5ef2aSThomas Huth return; 3493fcf5ef2aSThomas Huth } 3494fcf5ef2aSThomas Huth } 3495fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3496fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3497fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3498fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3499efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3500fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3501efe843d8SDavid Gibson } 3502fcf5ef2aSThomas Huth tcg_temp_free(EA); 3503fcf5ef2aSThomas Huth } 3504fcf5ef2aSThomas Huth } 3505fcf5ef2aSThomas Huth #endif 3506fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3507fcf5ef2aSThomas Huth 3508fcf5ef2aSThomas Huth /* lhbrx */ 3509fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3510fcf5ef2aSThomas Huth 3511fcf5ef2aSThomas Huth /* lwbrx */ 3512fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3513fcf5ef2aSThomas Huth 3514fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3515fcf5ef2aSThomas Huth /* ldbrx */ 3516fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3517fcf5ef2aSThomas Huth /* stdbrx */ 3518fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3519fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3520fcf5ef2aSThomas Huth 3521fcf5ef2aSThomas Huth /* sthbrx */ 3522fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3523fcf5ef2aSThomas Huth /* stwbrx */ 3524fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3525fcf5ef2aSThomas Huth 3526fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3527fcf5ef2aSThomas Huth 3528fcf5ef2aSThomas Huth /* lmw */ 3529fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3530fcf5ef2aSThomas Huth { 3531fcf5ef2aSThomas Huth TCGv t0; 3532fcf5ef2aSThomas Huth TCGv_i32 t1; 3533fcf5ef2aSThomas Huth 3534fcf5ef2aSThomas Huth if (ctx->le_mode) { 3535fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3536fcf5ef2aSThomas Huth return; 3537fcf5ef2aSThomas Huth } 3538fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3539fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3540fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3541fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3542fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3543fcf5ef2aSThomas Huth tcg_temp_free(t0); 3544fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3545fcf5ef2aSThomas Huth } 3546fcf5ef2aSThomas Huth 3547fcf5ef2aSThomas Huth /* stmw */ 3548fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3549fcf5ef2aSThomas Huth { 3550fcf5ef2aSThomas Huth TCGv t0; 3551fcf5ef2aSThomas Huth TCGv_i32 t1; 3552fcf5ef2aSThomas Huth 3553fcf5ef2aSThomas Huth if (ctx->le_mode) { 3554fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3555fcf5ef2aSThomas Huth return; 3556fcf5ef2aSThomas Huth } 3557fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3558fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3559fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3560fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3561fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3562fcf5ef2aSThomas Huth tcg_temp_free(t0); 3563fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3564fcf5ef2aSThomas Huth } 3565fcf5ef2aSThomas Huth 3566fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3567fcf5ef2aSThomas Huth 3568fcf5ef2aSThomas Huth /* lswi */ 3569efe843d8SDavid Gibson /* 3570efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3571efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3572efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3573efe843d8SDavid Gibson * spec... 3574fcf5ef2aSThomas Huth */ 3575fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3576fcf5ef2aSThomas Huth { 3577fcf5ef2aSThomas Huth TCGv t0; 3578fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3579fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3580fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3581fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3582fcf5ef2aSThomas Huth int nr; 3583fcf5ef2aSThomas Huth 3584fcf5ef2aSThomas Huth if (ctx->le_mode) { 3585fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3586fcf5ef2aSThomas Huth return; 3587fcf5ef2aSThomas Huth } 3588efe843d8SDavid Gibson if (nb == 0) { 3589fcf5ef2aSThomas Huth nb = 32; 3590efe843d8SDavid Gibson } 3591f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3592fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3593fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3594fcf5ef2aSThomas Huth return; 3595fcf5ef2aSThomas Huth } 3596fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3597fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3598fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3599fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3600fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3601fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3602fcf5ef2aSThomas Huth tcg_temp_free(t0); 3603fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3604fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3605fcf5ef2aSThomas Huth } 3606fcf5ef2aSThomas Huth 3607fcf5ef2aSThomas Huth /* lswx */ 3608fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3609fcf5ef2aSThomas Huth { 3610fcf5ef2aSThomas Huth TCGv t0; 3611fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3612fcf5ef2aSThomas Huth 3613fcf5ef2aSThomas Huth if (ctx->le_mode) { 3614fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3615fcf5ef2aSThomas Huth return; 3616fcf5ef2aSThomas Huth } 3617fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3618fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3619fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3620fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3621fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3622fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3623fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3624fcf5ef2aSThomas Huth tcg_temp_free(t0); 3625fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3626fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3627fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3628fcf5ef2aSThomas Huth } 3629fcf5ef2aSThomas Huth 3630fcf5ef2aSThomas Huth /* stswi */ 3631fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3632fcf5ef2aSThomas Huth { 3633fcf5ef2aSThomas Huth TCGv t0; 3634fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3635fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3636fcf5ef2aSThomas Huth 3637fcf5ef2aSThomas Huth if (ctx->le_mode) { 3638fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3639fcf5ef2aSThomas Huth return; 3640fcf5ef2aSThomas Huth } 3641fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3642fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3643fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3644efe843d8SDavid Gibson if (nb == 0) { 3645fcf5ef2aSThomas Huth nb = 32; 3646efe843d8SDavid Gibson } 3647fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3648fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3649fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3650fcf5ef2aSThomas Huth tcg_temp_free(t0); 3651fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3652fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3653fcf5ef2aSThomas Huth } 3654fcf5ef2aSThomas Huth 3655fcf5ef2aSThomas Huth /* stswx */ 3656fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3657fcf5ef2aSThomas Huth { 3658fcf5ef2aSThomas Huth TCGv t0; 3659fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3660fcf5ef2aSThomas Huth 3661fcf5ef2aSThomas Huth if (ctx->le_mode) { 3662fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3663fcf5ef2aSThomas Huth return; 3664fcf5ef2aSThomas Huth } 3665fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3666fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3667fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3668fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3669fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3670fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3671fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3672fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3673fcf5ef2aSThomas Huth tcg_temp_free(t0); 3674fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3675fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3676fcf5ef2aSThomas Huth } 3677fcf5ef2aSThomas Huth 3678fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3679fcf5ef2aSThomas Huth /* eieio */ 3680fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3681fcf5ef2aSThomas Huth { 3682c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3683c8fd8373SCédric Le Goater 3684c8fd8373SCédric Le Goater /* 3685c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3686c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3687c8fd8373SCédric Le Goater */ 3688c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3689c8fd8373SCédric Le Goater /* 3690c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3691c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3692c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3693c8fd8373SCédric Le Goater * complain to the user. 3694c8fd8373SCédric Le Goater */ 3695c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3696c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 36972c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3698c8fd8373SCédric Le Goater } else { 3699c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3700c8fd8373SCédric Le Goater } 3701c8fd8373SCédric Le Goater } 3702c8fd8373SCédric Le Goater 3703c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3704fcf5ef2aSThomas Huth } 3705fcf5ef2aSThomas Huth 3706fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3707fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3708fcf5ef2aSThomas Huth { 3709fcf5ef2aSThomas Huth TCGv_i32 t; 3710fcf5ef2aSThomas Huth TCGLabel *l; 3711fcf5ef2aSThomas Huth 3712fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3713fcf5ef2aSThomas Huth return; 3714fcf5ef2aSThomas Huth } 3715fcf5ef2aSThomas Huth l = gen_new_label(); 3716fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3717fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3718fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3719fcf5ef2aSThomas Huth if (global) { 3720fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3721fcf5ef2aSThomas Huth } else { 3722fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3723fcf5ef2aSThomas Huth } 3724fcf5ef2aSThomas Huth gen_set_label(l); 3725fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3726fcf5ef2aSThomas Huth } 3727fcf5ef2aSThomas Huth #else 3728fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3729fcf5ef2aSThomas Huth #endif 3730fcf5ef2aSThomas Huth 3731fcf5ef2aSThomas Huth /* isync */ 3732fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3733fcf5ef2aSThomas Huth { 3734fcf5ef2aSThomas Huth /* 3735fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3736fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3737fcf5ef2aSThomas Huth */ 3738fcf5ef2aSThomas Huth if (!ctx->pr) { 3739fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3740fcf5ef2aSThomas Huth } 37414771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3742d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3743fcf5ef2aSThomas Huth } 3744fcf5ef2aSThomas Huth 3745fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3746fcf5ef2aSThomas Huth 374714776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 37482a4e6c1bSRichard Henderson { 37492a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 37502a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 37512a4e6c1bSRichard Henderson 37522a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 37532a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 37542a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 37552a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 37562a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 37572a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 37582a4e6c1bSRichard Henderson tcg_temp_free(t0); 37592a4e6c1bSRichard Henderson } 37602a4e6c1bSRichard Henderson 3761fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3762fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3763fcf5ef2aSThomas Huth { \ 37642a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3765fcf5ef2aSThomas Huth } 3766fcf5ef2aSThomas Huth 3767fcf5ef2aSThomas Huth /* lwarx */ 3768fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3769fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3770fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3771fcf5ef2aSThomas Huth 377214776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 377320923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 377420923c1dSRichard Henderson { 377520923c1dSRichard Henderson TCGv t = tcg_temp_new(); 377620923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 377720923c1dSRichard Henderson TCGv u = tcg_temp_new(); 377820923c1dSRichard Henderson 377920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 378020923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 378120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 378220923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 378320923c1dSRichard Henderson 378420923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 378520923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 378620923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 378720923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 378820923c1dSRichard Henderson 378920923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 379020923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 379120923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 379220923c1dSRichard Henderson 379320923c1dSRichard Henderson tcg_temp_free(t); 379420923c1dSRichard Henderson tcg_temp_free(t2); 379520923c1dSRichard Henderson tcg_temp_free(u); 379620923c1dSRichard Henderson } 379720923c1dSRichard Henderson 379814776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 379920ba8504SRichard Henderson { 380020ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 380120ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 380220923c1dSRichard Henderson int rt = rD(ctx->opcode); 380320923c1dSRichard Henderson bool need_serial; 380420ba8504SRichard Henderson TCGv src, dst; 380520ba8504SRichard Henderson 380620ba8504SRichard Henderson gen_addr_register(ctx, EA); 380720923c1dSRichard Henderson dst = cpu_gpr[rt]; 380820923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 380920ba8504SRichard Henderson 381020923c1dSRichard Henderson need_serial = false; 381120ba8504SRichard Henderson memop |= MO_ALIGN; 381220ba8504SRichard Henderson switch (gpr_FC) { 381320ba8504SRichard Henderson case 0: /* Fetch and add */ 381420ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 381520ba8504SRichard Henderson break; 381620ba8504SRichard Henderson case 1: /* Fetch and xor */ 381720ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 381820ba8504SRichard Henderson break; 381920ba8504SRichard Henderson case 2: /* Fetch and or */ 382020ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 382120ba8504SRichard Henderson break; 382220ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 382320ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 382420ba8504SRichard Henderson break; 3825b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3826b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3827b8ce0f86SRichard Henderson break; 3828b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3829b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3830b8ce0f86SRichard Henderson break; 3831b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3832b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3833b8ce0f86SRichard Henderson break; 3834b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3835b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3836b8ce0f86SRichard Henderson break; 383720ba8504SRichard Henderson case 8: /* Swap */ 383820ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 383920ba8504SRichard Henderson break; 384020923c1dSRichard Henderson 384120923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 384220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 384320923c1dSRichard Henderson need_serial = true; 384420923c1dSRichard Henderson } else { 384520923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 384620923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 384720923c1dSRichard Henderson 384820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 384920923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 385020923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 385120923c1dSRichard Henderson } else { 385220923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 385320923c1dSRichard Henderson } 385420923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 385520923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 385620923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 385720923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 385820923c1dSRichard Henderson 385920923c1dSRichard Henderson tcg_temp_free(t0); 386020923c1dSRichard Henderson tcg_temp_free(t1); 386120923c1dSRichard Henderson } 386220ba8504SRichard Henderson break; 386320923c1dSRichard Henderson 386420923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 386520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 386620923c1dSRichard Henderson need_serial = true; 386720923c1dSRichard Henderson } else { 386820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 386920923c1dSRichard Henderson } 387020923c1dSRichard Henderson break; 387120923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 387220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 387320923c1dSRichard Henderson need_serial = true; 387420923c1dSRichard Henderson } else { 387520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 387620923c1dSRichard Henderson } 387720923c1dSRichard Henderson break; 387820923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 387920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 388020923c1dSRichard Henderson need_serial = true; 388120923c1dSRichard Henderson } else { 388220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 388320923c1dSRichard Henderson } 388420923c1dSRichard Henderson break; 388520923c1dSRichard Henderson 388620ba8504SRichard Henderson default: 388720ba8504SRichard Henderson /* invoke data storage error handler */ 388820ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 388920ba8504SRichard Henderson } 389020ba8504SRichard Henderson tcg_temp_free(EA); 389120923c1dSRichard Henderson 389220923c1dSRichard Henderson if (need_serial) { 389320923c1dSRichard Henderson /* Restart with exclusive lock. */ 389420923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 389520923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 389620923c1dSRichard Henderson } 3897a68a6146SBalamuruhan S } 3898a68a6146SBalamuruhan S 389920ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 390020ba8504SRichard Henderson { 390120ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 390220ba8504SRichard Henderson } 390320ba8504SRichard Henderson 390420ba8504SRichard Henderson #ifdef TARGET_PPC64 390520ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 390620ba8504SRichard Henderson { 390720ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 390820ba8504SRichard Henderson } 3909a68a6146SBalamuruhan S #endif 3910a68a6146SBalamuruhan S 391114776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 39129deb041cSRichard Henderson { 39139deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 39149deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 39159deb041cSRichard Henderson TCGv src, discard; 39169deb041cSRichard Henderson 39179deb041cSRichard Henderson gen_addr_register(ctx, EA); 39189deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 39199deb041cSRichard Henderson discard = tcg_temp_new(); 39209deb041cSRichard Henderson 39219deb041cSRichard Henderson memop |= MO_ALIGN; 39229deb041cSRichard Henderson switch (gpr_FC) { 39239deb041cSRichard Henderson case 0: /* add and Store */ 39249deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39259deb041cSRichard Henderson break; 39269deb041cSRichard Henderson case 1: /* xor and Store */ 39279deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39289deb041cSRichard Henderson break; 39299deb041cSRichard Henderson case 2: /* Or and Store */ 39309deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39319deb041cSRichard Henderson break; 39329deb041cSRichard Henderson case 3: /* 'and' and Store */ 39339deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39349deb041cSRichard Henderson break; 39359deb041cSRichard Henderson case 4: /* Store max unsigned */ 3936b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3937b8ce0f86SRichard Henderson break; 39389deb041cSRichard Henderson case 5: /* Store max signed */ 3939b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3940b8ce0f86SRichard Henderson break; 39419deb041cSRichard Henderson case 6: /* Store min unsigned */ 3942b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3943b8ce0f86SRichard Henderson break; 39449deb041cSRichard Henderson case 7: /* Store min signed */ 3945b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3946b8ce0f86SRichard Henderson break; 39479deb041cSRichard Henderson case 24: /* Store twin */ 39487fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 39497fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 39507fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 39517fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 39527fbc2b20SRichard Henderson } else { 39537fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 39547fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 39557fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 39567fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 39577fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 39587fbc2b20SRichard Henderson 39597fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 39607fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 39617fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 39627fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 39637fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 39647fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 39657fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 39667fbc2b20SRichard Henderson 39677fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 39687fbc2b20SRichard Henderson tcg_temp_free(s2); 39697fbc2b20SRichard Henderson tcg_temp_free(s); 39707fbc2b20SRichard Henderson tcg_temp_free(t2); 39717fbc2b20SRichard Henderson tcg_temp_free(t); 39727fbc2b20SRichard Henderson } 39739deb041cSRichard Henderson break; 39749deb041cSRichard Henderson default: 39759deb041cSRichard Henderson /* invoke data storage error handler */ 39769deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 39779deb041cSRichard Henderson } 39789deb041cSRichard Henderson tcg_temp_free(discard); 39799deb041cSRichard Henderson tcg_temp_free(EA); 3980a3401188SBalamuruhan S } 3981a3401188SBalamuruhan S 39829deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 39839deb041cSRichard Henderson { 39849deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 39859deb041cSRichard Henderson } 39869deb041cSRichard Henderson 39879deb041cSRichard Henderson #ifdef TARGET_PPC64 39889deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 39899deb041cSRichard Henderson { 39909deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 39919deb041cSRichard Henderson } 3992a3401188SBalamuruhan S #endif 3993a3401188SBalamuruhan S 399414776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3995fcf5ef2aSThomas Huth { 3996253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3997253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3998d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3999d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4000fcf5ef2aSThomas Huth 4001d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4002d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4003d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4004d8b86898SRichard Henderson tcg_temp_free(t0); 4005253ce7b2SNikunj A Dadhania 4006253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4007253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4008253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4009253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4010253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4011253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4012253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4013253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4014253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4015253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4016253ce7b2SNikunj A Dadhania 4017fcf5ef2aSThomas Huth gen_set_label(l1); 40184771df23SNikunj A Dadhania 4019efe843d8SDavid Gibson /* 4020efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4021efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4022efe843d8SDavid Gibson */ 40234771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4024253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4025253ce7b2SNikunj A Dadhania 4026253ce7b2SNikunj A Dadhania gen_set_label(l2); 4027fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4028fcf5ef2aSThomas Huth } 4029fcf5ef2aSThomas Huth 4030fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4031fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4032fcf5ef2aSThomas Huth { \ 4033d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4034fcf5ef2aSThomas Huth } 4035fcf5ef2aSThomas Huth 4036fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4037fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4038fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4039fcf5ef2aSThomas Huth 4040fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4041fcf5ef2aSThomas Huth /* ldarx */ 4042fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4043fcf5ef2aSThomas Huth /* stdcx. */ 4044fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4045fcf5ef2aSThomas Huth 4046fcf5ef2aSThomas Huth /* lqarx */ 4047fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4048fcf5ef2aSThomas Huth { 4049fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 405094bf2658SRichard Henderson TCGv EA, hi, lo; 4051fcf5ef2aSThomas Huth 4052fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4053fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4054fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4055fcf5ef2aSThomas Huth return; 4056fcf5ef2aSThomas Huth } 4057fcf5ef2aSThomas Huth 4058fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 405994bf2658SRichard Henderson EA = tcg_temp_new(); 4060fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 406194bf2658SRichard Henderson 406294bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 406394bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 406494bf2658SRichard Henderson hi = cpu_gpr[rd]; 406594bf2658SRichard Henderson 406694bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4067f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 406894bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 406994bf2658SRichard Henderson if (ctx->le_mode) { 407094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 407194bf2658SRichard Henderson ctx->mem_idx)); 407294bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4073fcf5ef2aSThomas Huth } else { 407494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 407594bf2658SRichard Henderson ctx->mem_idx)); 407694bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4077fcf5ef2aSThomas Huth } 407894bf2658SRichard Henderson tcg_temp_free_i32(oi); 407994bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4080f34ec0f6SRichard Henderson } else { 408194bf2658SRichard Henderson /* Restart with exclusive lock. */ 408294bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 408394bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 408494bf2658SRichard Henderson tcg_temp_free(EA); 408594bf2658SRichard Henderson return; 4086f34ec0f6SRichard Henderson } 408794bf2658SRichard Henderson } else if (ctx->le_mode) { 408894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4089fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4090fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 409194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 409294bf2658SRichard Henderson } else { 409394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 409494bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 409594bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 409694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 409794bf2658SRichard Henderson } 4098fcf5ef2aSThomas Huth tcg_temp_free(EA); 409994bf2658SRichard Henderson 410094bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 410194bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4102fcf5ef2aSThomas Huth } 4103fcf5ef2aSThomas Huth 4104fcf5ef2aSThomas Huth /* stqcx. */ 4105fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4106fcf5ef2aSThomas Huth { 41074a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 41084a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4109fcf5ef2aSThomas Huth 41104a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4111fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4112fcf5ef2aSThomas Huth return; 4113fcf5ef2aSThomas Huth } 41144a9b3c5dSRichard Henderson 4115fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 41164a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4117fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4118fcf5ef2aSThomas Huth 41194a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 41204a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 41214a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4122fcf5ef2aSThomas Huth 41234a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4124f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 41254a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 41264a9b3c5dSRichard Henderson if (ctx->le_mode) { 4127f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4128f34ec0f6SRichard Henderson EA, lo, hi, oi); 4129fcf5ef2aSThomas Huth } else { 4130f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4131f34ec0f6SRichard Henderson EA, lo, hi, oi); 4132fcf5ef2aSThomas Huth } 4133f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4134f34ec0f6SRichard Henderson } else { 41354a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 41364a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 41374a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4138f34ec0f6SRichard Henderson } 4139fcf5ef2aSThomas Huth tcg_temp_free(EA); 41404a9b3c5dSRichard Henderson } else { 41414a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 41424a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 41434a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 41444a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4145fcf5ef2aSThomas Huth 41464a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 41474a9b3c5dSRichard Henderson tcg_temp_free(EA); 41484a9b3c5dSRichard Henderson 41494a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 41504a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 41514a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 41524a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 41534a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 41544a9b3c5dSRichard Henderson 41554a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 41564a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 41574a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 41584a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 41594a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 41604a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 41614a9b3c5dSRichard Henderson 41624a9b3c5dSRichard Henderson /* Success */ 41634a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 41644a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 41654a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 41664a9b3c5dSRichard Henderson 41674a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 41684a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 41694a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 41704a9b3c5dSRichard Henderson 41714a9b3c5dSRichard Henderson gen_set_label(lab_fail); 41724a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 41734a9b3c5dSRichard Henderson 41744a9b3c5dSRichard Henderson gen_set_label(lab_over); 41754a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 41764a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 41774a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 41784a9b3c5dSRichard Henderson } 41794a9b3c5dSRichard Henderson } 4180fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4181fcf5ef2aSThomas Huth 4182fcf5ef2aSThomas Huth /* sync */ 4183fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4184fcf5ef2aSThomas Huth { 4185fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4186fcf5ef2aSThomas Huth 4187fcf5ef2aSThomas Huth /* 4188fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4189fcf5ef2aSThomas Huth * 4190fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4191fcf5ef2aSThomas Huth * 4192fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4193fcf5ef2aSThomas Huth * check MSR_PR as well. 4194fcf5ef2aSThomas Huth */ 4195fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4196fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4197fcf5ef2aSThomas Huth } 41984771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4199fcf5ef2aSThomas Huth } 4200fcf5ef2aSThomas Huth 4201fcf5ef2aSThomas Huth /* wait */ 4202fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4203fcf5ef2aSThomas Huth { 4204fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4205fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4206fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4207fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4208fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4209b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4210fcf5ef2aSThomas Huth } 4211fcf5ef2aSThomas Huth 4212fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4213fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4214fcf5ef2aSThomas Huth { 4215fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4216fcf5ef2aSThomas Huth GEN_PRIV; 4217fcf5ef2aSThomas Huth #else 4218fcf5ef2aSThomas Huth TCGv_i32 t; 4219fcf5ef2aSThomas Huth 4220fcf5ef2aSThomas Huth CHK_HV; 4221fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4222fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4223fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4224154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4225154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4226fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4227fcf5ef2aSThomas Huth } 4228fcf5ef2aSThomas Huth 4229fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4230fcf5ef2aSThomas Huth { 4231fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4232fcf5ef2aSThomas Huth GEN_PRIV; 4233fcf5ef2aSThomas Huth #else 4234fcf5ef2aSThomas Huth TCGv_i32 t; 4235fcf5ef2aSThomas Huth 4236fcf5ef2aSThomas Huth CHK_HV; 4237fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4238fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4239fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4240154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4241154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4242fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4243fcf5ef2aSThomas Huth } 4244fcf5ef2aSThomas Huth 4245cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4246cdee0e72SNikunj A Dadhania { 424721c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 424821c0d66aSBenjamin Herrenschmidt GEN_PRIV; 424921c0d66aSBenjamin Herrenschmidt #else 425021c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 425121c0d66aSBenjamin Herrenschmidt 425221c0d66aSBenjamin Herrenschmidt CHK_HV; 425321c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 425421c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 425521c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 425621c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 425721c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 425821c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4259cdee0e72SNikunj A Dadhania } 4260cdee0e72SNikunj A Dadhania 4261fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4262fcf5ef2aSThomas Huth { 4263fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4264fcf5ef2aSThomas Huth GEN_PRIV; 4265fcf5ef2aSThomas Huth #else 4266fcf5ef2aSThomas Huth TCGv_i32 t; 4267fcf5ef2aSThomas Huth 4268fcf5ef2aSThomas Huth CHK_HV; 4269fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4270fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4271fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4272154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4273154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4274fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4275fcf5ef2aSThomas Huth } 4276fcf5ef2aSThomas Huth 4277fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4278fcf5ef2aSThomas Huth { 4279fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4280fcf5ef2aSThomas Huth GEN_PRIV; 4281fcf5ef2aSThomas Huth #else 4282fcf5ef2aSThomas Huth TCGv_i32 t; 4283fcf5ef2aSThomas Huth 4284fcf5ef2aSThomas Huth CHK_HV; 4285fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4286fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4287fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4288154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4289154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4290fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4291fcf5ef2aSThomas Huth } 4292fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4293fcf5ef2aSThomas Huth 4294fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4295fcf5ef2aSThomas Huth { 4296fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4297efe843d8SDavid Gibson if (ctx->has_cfar) { 4298fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4299efe843d8SDavid Gibson } 4300fcf5ef2aSThomas Huth #endif 4301fcf5ef2aSThomas Huth } 4302fcf5ef2aSThomas Huth 4303fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4304fcf5ef2aSThomas Huth { 4305fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4306fcf5ef2aSThomas Huth return false; 4307fcf5ef2aSThomas Huth } 4308fcf5ef2aSThomas Huth 4309fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4310b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4311fcf5ef2aSThomas Huth #else 4312fcf5ef2aSThomas Huth return true; 4313fcf5ef2aSThomas Huth #endif 4314fcf5ef2aSThomas Huth } 4315fcf5ef2aSThomas Huth 43160e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 43170e3bf489SRoman Kapl { 43180e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 43190e3bf489SRoman Kapl if (unlikely(sse)) { 43200e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 43210e3bf489SRoman Kapl gen_debug_exception(ctx); 43220e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4323eba3c766SLuis Pires gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 43240032dbdbSRichard Henderson } else { 43250e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 43260032dbdbSRichard Henderson } 43270e3bf489SRoman Kapl } else { 43280e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 43290e3bf489SRoman Kapl } 43300e3bf489SRoman Kapl } 43310e3bf489SRoman Kapl 4332fcf5ef2aSThomas Huth /*** Branch ***/ 4333c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4334fcf5ef2aSThomas Huth { 4335fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4336fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4337fcf5ef2aSThomas Huth } 4338fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4339fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4340fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 434107ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4342fcf5ef2aSThomas Huth } else { 4343fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 43440e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4345fcf5ef2aSThomas Huth } 4346fcf5ef2aSThomas Huth } 4347fcf5ef2aSThomas Huth 4348fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4349fcf5ef2aSThomas Huth { 4350fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4351fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4352fcf5ef2aSThomas Huth } 4353fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4354fcf5ef2aSThomas Huth } 4355fcf5ef2aSThomas Huth 4356fcf5ef2aSThomas Huth /* b ba bl bla */ 4357fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4358fcf5ef2aSThomas Huth { 4359fcf5ef2aSThomas Huth target_ulong li, target; 4360fcf5ef2aSThomas Huth 4361fcf5ef2aSThomas Huth /* sign extend LI */ 4362fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4363fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4364fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43652c2bcb1bSRichard Henderson target = ctx->cia + li; 4366fcf5ef2aSThomas Huth } else { 4367fcf5ef2aSThomas Huth target = li; 4368fcf5ef2aSThomas Huth } 4369fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4370b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4371fcf5ef2aSThomas Huth } 43722c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4373fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 43746086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4375fcf5ef2aSThomas Huth } 4376fcf5ef2aSThomas Huth 4377fcf5ef2aSThomas Huth #define BCOND_IM 0 4378fcf5ef2aSThomas Huth #define BCOND_LR 1 4379fcf5ef2aSThomas Huth #define BCOND_CTR 2 4380fcf5ef2aSThomas Huth #define BCOND_TAR 3 4381fcf5ef2aSThomas Huth 4382c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4383fcf5ef2aSThomas Huth { 4384fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4385fcf5ef2aSThomas Huth TCGLabel *l1; 4386fcf5ef2aSThomas Huth TCGv target; 43870e3bf489SRoman Kapl 4388fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4389fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4390efe843d8SDavid Gibson if (type == BCOND_CTR) { 4391fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4392efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4393fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4394efe843d8SDavid Gibson } else { 4395fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4396efe843d8SDavid Gibson } 4397fcf5ef2aSThomas Huth } else { 4398f764718dSRichard Henderson target = NULL; 4399fcf5ef2aSThomas Huth } 4400efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4401b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4402efe843d8SDavid Gibson } 4403fcf5ef2aSThomas Huth l1 = gen_new_label(); 4404fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4405fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4406fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4407fa200c95SGreg Kurz 4408fa200c95SGreg Kurz if (type == BCOND_CTR) { 4409fa200c95SGreg Kurz /* 4410fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4411fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4412fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 441315d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 441415d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 441515d68c5eSGreg Kurz * it basically useless and thus never used in real code. 441615d68c5eSGreg Kurz * 441715d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 441815d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 441915d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 442015d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 442115d68c5eSGreg Kurz * doing anything else harmful. 4422fa200c95SGreg Kurz */ 4423d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4424fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 44259acc95cdSGreg Kurz tcg_temp_free(temp); 44269acc95cdSGreg Kurz tcg_temp_free(target); 4427fcf5ef2aSThomas Huth return; 4428fcf5ef2aSThomas Huth } 4429fa200c95SGreg Kurz 4430fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4431fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4432fa200c95SGreg Kurz } else { 4433fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4434fa200c95SGreg Kurz } 4435fa200c95SGreg Kurz if (bo & 0x2) { 4436fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4437fa200c95SGreg Kurz } else { 4438fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4439fa200c95SGreg Kurz } 4440fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4441fa200c95SGreg Kurz } else { 4442fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4443fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4444fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4445fcf5ef2aSThomas Huth } else { 4446fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4447fcf5ef2aSThomas Huth } 4448fcf5ef2aSThomas Huth if (bo & 0x2) { 4449fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4450fcf5ef2aSThomas Huth } else { 4451fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4452fcf5ef2aSThomas Huth } 4453fa200c95SGreg Kurz } 4454fcf5ef2aSThomas Huth tcg_temp_free(temp); 4455fcf5ef2aSThomas Huth } 4456fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4457fcf5ef2aSThomas Huth /* Test CR */ 4458fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4459fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4460fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4461fcf5ef2aSThomas Huth 4462fcf5ef2aSThomas Huth if (bo & 0x8) { 4463fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4464fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4465fcf5ef2aSThomas Huth } else { 4466fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4467fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4468fcf5ef2aSThomas Huth } 4469fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4470fcf5ef2aSThomas Huth } 44712c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4472fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4473fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4474fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 44752c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4476fcf5ef2aSThomas Huth } else { 4477fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4478fcf5ef2aSThomas Huth } 4479fcf5ef2aSThomas Huth } else { 4480fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4481fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4482fcf5ef2aSThomas Huth } else { 4483fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4484fcf5ef2aSThomas Huth } 44850e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4486c4a2e3a9SRichard Henderson tcg_temp_free(target); 4487c4a2e3a9SRichard Henderson } 4488fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 44890e3bf489SRoman Kapl /* fallthrough case */ 4490fcf5ef2aSThomas Huth gen_set_label(l1); 4491b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4492fcf5ef2aSThomas Huth } 44936086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4494fcf5ef2aSThomas Huth } 4495fcf5ef2aSThomas Huth 4496fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4497fcf5ef2aSThomas Huth { 4498fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4499fcf5ef2aSThomas Huth } 4500fcf5ef2aSThomas Huth 4501fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4502fcf5ef2aSThomas Huth { 4503fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4504fcf5ef2aSThomas Huth } 4505fcf5ef2aSThomas Huth 4506fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4507fcf5ef2aSThomas Huth { 4508fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4509fcf5ef2aSThomas Huth } 4510fcf5ef2aSThomas Huth 4511fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4512fcf5ef2aSThomas Huth { 4513fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4514fcf5ef2aSThomas Huth } 4515fcf5ef2aSThomas Huth 4516fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4517fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4518fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4519fcf5ef2aSThomas Huth { \ 4520fcf5ef2aSThomas Huth uint8_t bitmask; \ 4521fcf5ef2aSThomas Huth int sh; \ 4522fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4523fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4524fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4525fcf5ef2aSThomas Huth if (sh > 0) \ 4526fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4527fcf5ef2aSThomas Huth else if (sh < 0) \ 4528fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4529fcf5ef2aSThomas Huth else \ 4530fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4531fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4532fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4533fcf5ef2aSThomas Huth if (sh > 0) \ 4534fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4535fcf5ef2aSThomas Huth else if (sh < 0) \ 4536fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4537fcf5ef2aSThomas Huth else \ 4538fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4539fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4540fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4541fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4542fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4543fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4544fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4545fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4546fcf5ef2aSThomas Huth } 4547fcf5ef2aSThomas Huth 4548fcf5ef2aSThomas Huth /* crand */ 4549fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4550fcf5ef2aSThomas Huth /* crandc */ 4551fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4552fcf5ef2aSThomas Huth /* creqv */ 4553fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4554fcf5ef2aSThomas Huth /* crnand */ 4555fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4556fcf5ef2aSThomas Huth /* crnor */ 4557fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4558fcf5ef2aSThomas Huth /* cror */ 4559fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4560fcf5ef2aSThomas Huth /* crorc */ 4561fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4562fcf5ef2aSThomas Huth /* crxor */ 4563fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4564fcf5ef2aSThomas Huth 4565fcf5ef2aSThomas Huth /* mcrf */ 4566fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4567fcf5ef2aSThomas Huth { 4568fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4569fcf5ef2aSThomas Huth } 4570fcf5ef2aSThomas Huth 4571fcf5ef2aSThomas Huth /*** System linkage ***/ 4572fcf5ef2aSThomas Huth 4573fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4574fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4575fcf5ef2aSThomas Huth { 4576fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4577fcf5ef2aSThomas Huth GEN_PRIV; 4578fcf5ef2aSThomas Huth #else 4579efe843d8SDavid Gibson /* 4580efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4581fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4582fcf5ef2aSThomas Huth */ 4583d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4584fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4585fcf5ef2aSThomas Huth return; 4586fcf5ef2aSThomas Huth } 4587fcf5ef2aSThomas Huth /* Restore CPU state */ 4588fcf5ef2aSThomas Huth CHK_SV; 4589f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45902c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4591fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 459259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4593fcf5ef2aSThomas Huth #endif 4594fcf5ef2aSThomas Huth } 4595fcf5ef2aSThomas Huth 4596fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4597fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4598fcf5ef2aSThomas Huth { 4599fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4600fcf5ef2aSThomas Huth GEN_PRIV; 4601fcf5ef2aSThomas Huth #else 4602fcf5ef2aSThomas Huth /* Restore CPU state */ 4603fcf5ef2aSThomas Huth CHK_SV; 4604f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46052c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4606fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 460759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4608fcf5ef2aSThomas Huth #endif 4609fcf5ef2aSThomas Huth } 4610fcf5ef2aSThomas Huth 46113c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46123c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 46133c89b8d6SNicholas Piggin { 46143c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 46153c89b8d6SNicholas Piggin GEN_PRIV; 46163c89b8d6SNicholas Piggin #else 46173c89b8d6SNicholas Piggin /* Restore CPU state */ 46183c89b8d6SNicholas Piggin CHK_SV; 4619f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46202c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 46213c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 462259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 46233c89b8d6SNicholas Piggin #endif 46243c89b8d6SNicholas Piggin } 46253c89b8d6SNicholas Piggin #endif 46263c89b8d6SNicholas Piggin 4627fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4628fcf5ef2aSThomas Huth { 4629fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4630fcf5ef2aSThomas Huth GEN_PRIV; 4631fcf5ef2aSThomas Huth #else 4632fcf5ef2aSThomas Huth /* Restore CPU state */ 4633fcf5ef2aSThomas Huth CHK_HV; 4634fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 463559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4636fcf5ef2aSThomas Huth #endif 4637fcf5ef2aSThomas Huth } 4638fcf5ef2aSThomas Huth #endif 4639fcf5ef2aSThomas Huth 4640fcf5ef2aSThomas Huth /* sc */ 4641fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4642fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4643fcf5ef2aSThomas Huth #else 4644fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 46453c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4646fcf5ef2aSThomas Huth #endif 4647fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4648fcf5ef2aSThomas Huth { 4649fcf5ef2aSThomas Huth uint32_t lev; 4650fcf5ef2aSThomas Huth 4651fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4652fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4653fcf5ef2aSThomas Huth } 4654fcf5ef2aSThomas Huth 46553c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 46563c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46573c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 46583c89b8d6SNicholas Piggin { 4659f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 46603c89b8d6SNicholas Piggin 4661f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 46622c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4663f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 46643c89b8d6SNicholas Piggin 46657a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 46663c89b8d6SNicholas Piggin } 46673c89b8d6SNicholas Piggin #endif 46683c89b8d6SNicholas Piggin #endif 46693c89b8d6SNicholas Piggin 4670fcf5ef2aSThomas Huth /*** Trap ***/ 4671fcf5ef2aSThomas Huth 4672fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4673fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4674fcf5ef2aSThomas Huth { 4675fcf5ef2aSThomas Huth /* Trap never */ 4676fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4677fcf5ef2aSThomas Huth return true; 4678fcf5ef2aSThomas Huth } 4679fcf5ef2aSThomas Huth /* Trap always */ 4680fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4681fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4682fcf5ef2aSThomas Huth return true; 4683fcf5ef2aSThomas Huth } 4684fcf5ef2aSThomas Huth return false; 4685fcf5ef2aSThomas Huth } 4686fcf5ef2aSThomas Huth 4687fcf5ef2aSThomas Huth /* tw */ 4688fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4689fcf5ef2aSThomas Huth { 4690fcf5ef2aSThomas Huth TCGv_i32 t0; 4691fcf5ef2aSThomas Huth 4692fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4693fcf5ef2aSThomas Huth return; 4694fcf5ef2aSThomas Huth } 4695fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4696fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4697fcf5ef2aSThomas Huth t0); 4698fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4699fcf5ef2aSThomas Huth } 4700fcf5ef2aSThomas Huth 4701fcf5ef2aSThomas Huth /* twi */ 4702fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4703fcf5ef2aSThomas Huth { 4704fcf5ef2aSThomas Huth TCGv t0; 4705fcf5ef2aSThomas Huth TCGv_i32 t1; 4706fcf5ef2aSThomas Huth 4707fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4708fcf5ef2aSThomas Huth return; 4709fcf5ef2aSThomas Huth } 4710fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4711fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4712fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4713fcf5ef2aSThomas Huth tcg_temp_free(t0); 4714fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4715fcf5ef2aSThomas Huth } 4716fcf5ef2aSThomas Huth 4717fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4718fcf5ef2aSThomas Huth /* td */ 4719fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4720fcf5ef2aSThomas Huth { 4721fcf5ef2aSThomas Huth TCGv_i32 t0; 4722fcf5ef2aSThomas Huth 4723fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4724fcf5ef2aSThomas Huth return; 4725fcf5ef2aSThomas Huth } 4726fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4727fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4728fcf5ef2aSThomas Huth t0); 4729fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4730fcf5ef2aSThomas Huth } 4731fcf5ef2aSThomas Huth 4732fcf5ef2aSThomas Huth /* tdi */ 4733fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4734fcf5ef2aSThomas Huth { 4735fcf5ef2aSThomas Huth TCGv t0; 4736fcf5ef2aSThomas Huth TCGv_i32 t1; 4737fcf5ef2aSThomas Huth 4738fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4739fcf5ef2aSThomas Huth return; 4740fcf5ef2aSThomas Huth } 4741fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4742fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4743fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4744fcf5ef2aSThomas Huth tcg_temp_free(t0); 4745fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4746fcf5ef2aSThomas Huth } 4747fcf5ef2aSThomas Huth #endif 4748fcf5ef2aSThomas Huth 4749fcf5ef2aSThomas Huth /*** Processor control ***/ 4750fcf5ef2aSThomas Huth 4751fcf5ef2aSThomas Huth /* mcrxr */ 4752fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4753fcf5ef2aSThomas Huth { 4754fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4755fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4756fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4757fcf5ef2aSThomas Huth 4758fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4759fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4760fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4761fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4762fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4763fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4764fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4765fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4766fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4767fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4768fcf5ef2aSThomas Huth 4769fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4770fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4771fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4772fcf5ef2aSThomas Huth } 4773fcf5ef2aSThomas Huth 4774b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4775b63d0434SNikunj A Dadhania /* mcrxrx */ 4776b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4777b63d0434SNikunj A Dadhania { 4778b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4779b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4780b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4781b63d0434SNikunj A Dadhania 4782b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4783b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4784b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4785b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4786b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4787b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4788b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4789b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4790b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4791b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4792b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4793b63d0434SNikunj A Dadhania } 4794b63d0434SNikunj A Dadhania #endif 4795b63d0434SNikunj A Dadhania 4796fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4797fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4798fcf5ef2aSThomas Huth { 4799fcf5ef2aSThomas Huth uint32_t crm, crn; 4800fcf5ef2aSThomas Huth 4801fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4802fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4803fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4804fcf5ef2aSThomas Huth crn = ctz32(crm); 4805fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4806fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4807fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4808fcf5ef2aSThomas Huth } 4809fcf5ef2aSThomas Huth } else { 4810fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4811fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4812fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4813fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4814fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4815fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4816fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4817fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4818fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4819fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4820fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4821fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4822fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4823fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4824fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4825fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4826fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4827fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4828fcf5ef2aSThomas Huth } 4829fcf5ef2aSThomas Huth } 4830fcf5ef2aSThomas Huth 4831fcf5ef2aSThomas Huth /* mfmsr */ 4832fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4833fcf5ef2aSThomas Huth { 4834fcf5ef2aSThomas Huth CHK_SV; 4835fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4836fcf5ef2aSThomas Huth } 4837fcf5ef2aSThomas Huth 4838fcf5ef2aSThomas Huth /* mfspr */ 4839fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4840fcf5ef2aSThomas Huth { 4841fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4842fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4843fcf5ef2aSThomas Huth 4844fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4845fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4846fcf5ef2aSThomas Huth #else 4847fcf5ef2aSThomas Huth if (ctx->pr) { 4848fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4849fcf5ef2aSThomas Huth } else if (ctx->hv) { 4850fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4851fcf5ef2aSThomas Huth } else { 4852fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4853fcf5ef2aSThomas Huth } 4854fcf5ef2aSThomas Huth #endif 4855fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4856fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4857fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4858fcf5ef2aSThomas Huth } else { 4859fcf5ef2aSThomas Huth /* Privilege exception */ 4860efe843d8SDavid Gibson /* 4861efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4862fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4863fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4864fcf5ef2aSThomas Huth */ 4865fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 486631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 486731085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48682c2bcb1bSRichard Henderson ctx->cia); 4869fcf5ef2aSThomas Huth } 4870fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4871fcf5ef2aSThomas Huth } 4872fcf5ef2aSThomas Huth } else { 4873fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4874fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4875fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4876fcf5ef2aSThomas Huth /* This is a nop */ 4877fcf5ef2aSThomas Huth return; 4878fcf5ef2aSThomas Huth } 4879fcf5ef2aSThomas Huth /* Not defined */ 488031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 488131085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 48822c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4883fcf5ef2aSThomas Huth 4884efe843d8SDavid Gibson /* 4885efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4886efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4887fcf5ef2aSThomas Huth */ 4888fcf5ef2aSThomas Huth if (sprn & 0x10) { 4889fcf5ef2aSThomas Huth if (ctx->pr) { 4890fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4891fcf5ef2aSThomas Huth } 4892fcf5ef2aSThomas Huth } else { 4893fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4894fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4895fcf5ef2aSThomas Huth } 4896fcf5ef2aSThomas Huth } 4897fcf5ef2aSThomas Huth } 4898fcf5ef2aSThomas Huth } 4899fcf5ef2aSThomas Huth 4900fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4901fcf5ef2aSThomas Huth { 4902fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4903fcf5ef2aSThomas Huth } 4904fcf5ef2aSThomas Huth 4905fcf5ef2aSThomas Huth /* mftb */ 4906fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4907fcf5ef2aSThomas Huth { 4908fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4909fcf5ef2aSThomas Huth } 4910fcf5ef2aSThomas Huth 4911fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4912fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4913fcf5ef2aSThomas Huth { 4914fcf5ef2aSThomas Huth uint32_t crm, crn; 4915fcf5ef2aSThomas Huth 4916fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4917fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4918fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4919fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4920fcf5ef2aSThomas Huth crn = ctz32(crm); 4921fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4922fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4923fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4924fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4925fcf5ef2aSThomas Huth } 4926fcf5ef2aSThomas Huth } else { 4927fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4928fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4929fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4930fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4931fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4932fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4933fcf5ef2aSThomas Huth } 4934fcf5ef2aSThomas Huth } 4935fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4936fcf5ef2aSThomas Huth } 4937fcf5ef2aSThomas Huth } 4938fcf5ef2aSThomas Huth 4939fcf5ef2aSThomas Huth /* mtmsr */ 4940fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4941fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4942fcf5ef2aSThomas Huth { 4943*caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4944*caf590ddSNicholas Piggin gen_invalid(ctx); 4945*caf590ddSNicholas Piggin return; 4946*caf590ddSNicholas Piggin } 4947*caf590ddSNicholas Piggin 4948fcf5ef2aSThomas Huth CHK_SV; 4949fcf5ef2aSThomas Huth 4950fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4951f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4952fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49535ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 4954fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 49555ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 4956efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4957efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 49585ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 4959efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 49605ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 49615ed19506SNicholas Piggin 49625ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 4963fcf5ef2aSThomas Huth tcg_temp_free(t0); 49645ed19506SNicholas Piggin tcg_temp_free(t1); 49655ed19506SNicholas Piggin 4966fcf5ef2aSThomas Huth } else { 4967efe843d8SDavid Gibson /* 4968efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4969efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4970efe843d8SDavid Gibson * ppc_store_msr 4971fcf5ef2aSThomas Huth */ 4972b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4973fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4974fcf5ef2aSThomas Huth } 49755ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4976d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4977fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4978fcf5ef2aSThomas Huth } 4979fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4980fcf5ef2aSThomas Huth 4981fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4982fcf5ef2aSThomas Huth { 4983fcf5ef2aSThomas Huth CHK_SV; 4984fcf5ef2aSThomas Huth 4985fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4986f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4987fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49885ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 4989fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 49905ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 4991efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4992efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 49935ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 4994efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 49955ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 49965ed19506SNicholas Piggin 49975ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 4998fcf5ef2aSThomas Huth tcg_temp_free(t0); 49995ed19506SNicholas Piggin tcg_temp_free(t1); 50005ed19506SNicholas Piggin 5001fcf5ef2aSThomas Huth } else { 5002fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5003fcf5ef2aSThomas Huth 5004efe843d8SDavid Gibson /* 5005efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5006efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5007efe843d8SDavid Gibson * ppc_store_msr 5008fcf5ef2aSThomas Huth */ 5009b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5010fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5011fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5012fcf5ef2aSThomas Huth #else 5013fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5014fcf5ef2aSThomas Huth #endif 5015fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5016fcf5ef2aSThomas Huth tcg_temp_free(msr); 5017fcf5ef2aSThomas Huth } 50185ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5019d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5020fcf5ef2aSThomas Huth #endif 5021fcf5ef2aSThomas Huth } 5022fcf5ef2aSThomas Huth 5023fcf5ef2aSThomas Huth /* mtspr */ 5024fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5025fcf5ef2aSThomas Huth { 5026fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5027fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5028fcf5ef2aSThomas Huth 5029fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5030fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5031fcf5ef2aSThomas Huth #else 5032fcf5ef2aSThomas Huth if (ctx->pr) { 5033fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5034fcf5ef2aSThomas Huth } else if (ctx->hv) { 5035fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5036fcf5ef2aSThomas Huth } else { 5037fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5038fcf5ef2aSThomas Huth } 5039fcf5ef2aSThomas Huth #endif 5040fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5041fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5042fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5043fcf5ef2aSThomas Huth } else { 5044fcf5ef2aSThomas Huth /* Privilege exception */ 504531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 504631085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 50472c2bcb1bSRichard Henderson ctx->cia); 5048fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5049fcf5ef2aSThomas Huth } 5050fcf5ef2aSThomas Huth } else { 5051fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5052fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5053fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5054fcf5ef2aSThomas Huth /* This is a nop */ 5055fcf5ef2aSThomas Huth return; 5056fcf5ef2aSThomas Huth } 5057fcf5ef2aSThomas Huth 5058fcf5ef2aSThomas Huth /* Not defined */ 505931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 506031085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 50612c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5062fcf5ef2aSThomas Huth 5063fcf5ef2aSThomas Huth 5064efe843d8SDavid Gibson /* 5065efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5066efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5067fcf5ef2aSThomas Huth */ 5068fcf5ef2aSThomas Huth if (sprn & 0x10) { 5069fcf5ef2aSThomas Huth if (ctx->pr) { 5070fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5071fcf5ef2aSThomas Huth } 5072fcf5ef2aSThomas Huth } else { 5073fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5074fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5075fcf5ef2aSThomas Huth } 5076fcf5ef2aSThomas Huth } 5077fcf5ef2aSThomas Huth } 5078fcf5ef2aSThomas Huth } 5079fcf5ef2aSThomas Huth 5080fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5081fcf5ef2aSThomas Huth /* setb */ 5082fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5083fcf5ef2aSThomas Huth { 5084fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5085fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5086fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5087fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5088fcf5ef2aSThomas Huth 5089fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5090fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5091fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5092fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5093fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5094fcf5ef2aSThomas Huth 5095fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5096fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5097fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5098fcf5ef2aSThomas Huth } 5099fcf5ef2aSThomas Huth #endif 5100fcf5ef2aSThomas Huth 5101fcf5ef2aSThomas Huth /*** Cache management ***/ 5102fcf5ef2aSThomas Huth 5103fcf5ef2aSThomas Huth /* dcbf */ 5104fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5105fcf5ef2aSThomas Huth { 5106fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5107fcf5ef2aSThomas Huth TCGv t0; 5108fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5109fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5110fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5111fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5112fcf5ef2aSThomas Huth tcg_temp_free(t0); 5113fcf5ef2aSThomas Huth } 5114fcf5ef2aSThomas Huth 511550728199SRoman Kapl /* dcbfep (external PID dcbf) */ 511650728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 511750728199SRoman Kapl { 511850728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 511950728199SRoman Kapl TCGv t0; 512050728199SRoman Kapl CHK_SV; 512150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 512250728199SRoman Kapl t0 = tcg_temp_new(); 512350728199SRoman Kapl gen_addr_reg_index(ctx, t0); 512450728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 512550728199SRoman Kapl tcg_temp_free(t0); 512650728199SRoman Kapl } 512750728199SRoman Kapl 5128fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5129fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5130fcf5ef2aSThomas Huth { 5131fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5132fcf5ef2aSThomas Huth GEN_PRIV; 5133fcf5ef2aSThomas Huth #else 5134fcf5ef2aSThomas Huth TCGv EA, val; 5135fcf5ef2aSThomas Huth 5136fcf5ef2aSThomas Huth CHK_SV; 5137fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5138fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5139fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5140fcf5ef2aSThomas Huth val = tcg_temp_new(); 5141fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5142fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5143fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5144fcf5ef2aSThomas Huth tcg_temp_free(val); 5145fcf5ef2aSThomas Huth tcg_temp_free(EA); 5146fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5147fcf5ef2aSThomas Huth } 5148fcf5ef2aSThomas Huth 5149fcf5ef2aSThomas Huth /* dcdst */ 5150fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5151fcf5ef2aSThomas Huth { 5152fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5153fcf5ef2aSThomas Huth TCGv t0; 5154fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5155fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5156fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5157fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5158fcf5ef2aSThomas Huth tcg_temp_free(t0); 5159fcf5ef2aSThomas Huth } 5160fcf5ef2aSThomas Huth 516150728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 516250728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 516350728199SRoman Kapl { 516450728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 516550728199SRoman Kapl TCGv t0; 516650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 516750728199SRoman Kapl t0 = tcg_temp_new(); 516850728199SRoman Kapl gen_addr_reg_index(ctx, t0); 516950728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 517050728199SRoman Kapl tcg_temp_free(t0); 517150728199SRoman Kapl } 517250728199SRoman Kapl 5173fcf5ef2aSThomas Huth /* dcbt */ 5174fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5175fcf5ef2aSThomas Huth { 5176efe843d8SDavid Gibson /* 5177efe843d8SDavid Gibson * interpreted as no-op 5178efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5179efe843d8SDavid Gibson * does not generate any exception 5180fcf5ef2aSThomas Huth */ 5181fcf5ef2aSThomas Huth } 5182fcf5ef2aSThomas Huth 518350728199SRoman Kapl /* dcbtep */ 518450728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 518550728199SRoman Kapl { 5186efe843d8SDavid Gibson /* 5187efe843d8SDavid Gibson * interpreted as no-op 5188efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5189efe843d8SDavid Gibson * does not generate any exception 519050728199SRoman Kapl */ 519150728199SRoman Kapl } 519250728199SRoman Kapl 5193fcf5ef2aSThomas Huth /* dcbtst */ 5194fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5195fcf5ef2aSThomas Huth { 5196efe843d8SDavid Gibson /* 5197efe843d8SDavid Gibson * interpreted as no-op 5198efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5199efe843d8SDavid Gibson * does not generate any exception 5200fcf5ef2aSThomas Huth */ 5201fcf5ef2aSThomas Huth } 5202fcf5ef2aSThomas Huth 520350728199SRoman Kapl /* dcbtstep */ 520450728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 520550728199SRoman Kapl { 5206efe843d8SDavid Gibson /* 5207efe843d8SDavid Gibson * interpreted as no-op 5208efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5209efe843d8SDavid Gibson * does not generate any exception 521050728199SRoman Kapl */ 521150728199SRoman Kapl } 521250728199SRoman Kapl 5213fcf5ef2aSThomas Huth /* dcbtls */ 5214fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5215fcf5ef2aSThomas Huth { 5216fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5217fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5218fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5219fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5220fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5221fcf5ef2aSThomas Huth tcg_temp_free(t0); 5222fcf5ef2aSThomas Huth } 5223fcf5ef2aSThomas Huth 5224fcf5ef2aSThomas Huth /* dcbz */ 5225fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5226fcf5ef2aSThomas Huth { 5227fcf5ef2aSThomas Huth TCGv tcgv_addr; 5228fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5229fcf5ef2aSThomas Huth 5230fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5231fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5232fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5233fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5234fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5235fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5236fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5237fcf5ef2aSThomas Huth } 5238fcf5ef2aSThomas Huth 523950728199SRoman Kapl /* dcbzep */ 524050728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 524150728199SRoman Kapl { 524250728199SRoman Kapl TCGv tcgv_addr; 524350728199SRoman Kapl TCGv_i32 tcgv_op; 524450728199SRoman Kapl 524550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 524650728199SRoman Kapl tcgv_addr = tcg_temp_new(); 524750728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 524850728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 524950728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 525050728199SRoman Kapl tcg_temp_free(tcgv_addr); 525150728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 525250728199SRoman Kapl } 525350728199SRoman Kapl 5254fcf5ef2aSThomas Huth /* dst / dstt */ 5255fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5256fcf5ef2aSThomas Huth { 5257fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5258fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5259fcf5ef2aSThomas Huth } else { 5260fcf5ef2aSThomas Huth /* interpreted as no-op */ 5261fcf5ef2aSThomas Huth } 5262fcf5ef2aSThomas Huth } 5263fcf5ef2aSThomas Huth 5264fcf5ef2aSThomas Huth /* dstst /dststt */ 5265fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5266fcf5ef2aSThomas Huth { 5267fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5268fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5269fcf5ef2aSThomas Huth } else { 5270fcf5ef2aSThomas Huth /* interpreted as no-op */ 5271fcf5ef2aSThomas Huth } 5272fcf5ef2aSThomas Huth 5273fcf5ef2aSThomas Huth } 5274fcf5ef2aSThomas Huth 5275fcf5ef2aSThomas Huth /* dss / dssall */ 5276fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5277fcf5ef2aSThomas Huth { 5278fcf5ef2aSThomas Huth /* interpreted as no-op */ 5279fcf5ef2aSThomas Huth } 5280fcf5ef2aSThomas Huth 5281fcf5ef2aSThomas Huth /* icbi */ 5282fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5283fcf5ef2aSThomas Huth { 5284fcf5ef2aSThomas Huth TCGv t0; 5285fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5286fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5287fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5288fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5289fcf5ef2aSThomas Huth tcg_temp_free(t0); 5290fcf5ef2aSThomas Huth } 5291fcf5ef2aSThomas Huth 529250728199SRoman Kapl /* icbiep */ 529350728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 529450728199SRoman Kapl { 529550728199SRoman Kapl TCGv t0; 529650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 529750728199SRoman Kapl t0 = tcg_temp_new(); 529850728199SRoman Kapl gen_addr_reg_index(ctx, t0); 529950728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 530050728199SRoman Kapl tcg_temp_free(t0); 530150728199SRoman Kapl } 530250728199SRoman Kapl 5303fcf5ef2aSThomas Huth /* Optional: */ 5304fcf5ef2aSThomas Huth /* dcba */ 5305fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5306fcf5ef2aSThomas Huth { 5307efe843d8SDavid Gibson /* 5308efe843d8SDavid Gibson * interpreted as no-op 5309efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5310fcf5ef2aSThomas Huth * but does not generate any exception 5311fcf5ef2aSThomas Huth */ 5312fcf5ef2aSThomas Huth } 5313fcf5ef2aSThomas Huth 5314fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5315fcf5ef2aSThomas Huth /* Supervisor only: */ 5316fcf5ef2aSThomas Huth 5317fcf5ef2aSThomas Huth /* mfsr */ 5318fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5319fcf5ef2aSThomas Huth { 5320fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5321fcf5ef2aSThomas Huth GEN_PRIV; 5322fcf5ef2aSThomas Huth #else 5323fcf5ef2aSThomas Huth TCGv t0; 5324fcf5ef2aSThomas Huth 5325fcf5ef2aSThomas Huth CHK_SV; 5326fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5327fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5328fcf5ef2aSThomas Huth tcg_temp_free(t0); 5329fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5330fcf5ef2aSThomas Huth } 5331fcf5ef2aSThomas Huth 5332fcf5ef2aSThomas Huth /* mfsrin */ 5333fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5334fcf5ef2aSThomas Huth { 5335fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5336fcf5ef2aSThomas Huth GEN_PRIV; 5337fcf5ef2aSThomas Huth #else 5338fcf5ef2aSThomas Huth TCGv t0; 5339fcf5ef2aSThomas Huth 5340fcf5ef2aSThomas Huth CHK_SV; 5341fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5342e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5343fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5344fcf5ef2aSThomas Huth tcg_temp_free(t0); 5345fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5346fcf5ef2aSThomas Huth } 5347fcf5ef2aSThomas Huth 5348fcf5ef2aSThomas Huth /* mtsr */ 5349fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5350fcf5ef2aSThomas Huth { 5351fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5352fcf5ef2aSThomas Huth GEN_PRIV; 5353fcf5ef2aSThomas Huth #else 5354fcf5ef2aSThomas Huth TCGv t0; 5355fcf5ef2aSThomas Huth 5356fcf5ef2aSThomas Huth CHK_SV; 5357fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5358fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5359fcf5ef2aSThomas Huth tcg_temp_free(t0); 5360fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5361fcf5ef2aSThomas Huth } 5362fcf5ef2aSThomas Huth 5363fcf5ef2aSThomas Huth /* mtsrin */ 5364fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5365fcf5ef2aSThomas Huth { 5366fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5367fcf5ef2aSThomas Huth GEN_PRIV; 5368fcf5ef2aSThomas Huth #else 5369fcf5ef2aSThomas Huth TCGv t0; 5370fcf5ef2aSThomas Huth CHK_SV; 5371fcf5ef2aSThomas Huth 5372fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5373e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5374fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5375fcf5ef2aSThomas Huth tcg_temp_free(t0); 5376fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5377fcf5ef2aSThomas Huth } 5378fcf5ef2aSThomas Huth 5379fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5380fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5381fcf5ef2aSThomas Huth 5382fcf5ef2aSThomas Huth /* mfsr */ 5383fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5384fcf5ef2aSThomas Huth { 5385fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5386fcf5ef2aSThomas Huth GEN_PRIV; 5387fcf5ef2aSThomas Huth #else 5388fcf5ef2aSThomas Huth TCGv t0; 5389fcf5ef2aSThomas Huth 5390fcf5ef2aSThomas Huth CHK_SV; 5391fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5392fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5393fcf5ef2aSThomas Huth tcg_temp_free(t0); 5394fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5395fcf5ef2aSThomas Huth } 5396fcf5ef2aSThomas Huth 5397fcf5ef2aSThomas Huth /* mfsrin */ 5398fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5399fcf5ef2aSThomas Huth { 5400fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5401fcf5ef2aSThomas Huth GEN_PRIV; 5402fcf5ef2aSThomas Huth #else 5403fcf5ef2aSThomas Huth TCGv t0; 5404fcf5ef2aSThomas Huth 5405fcf5ef2aSThomas Huth CHK_SV; 5406fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5407e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5408fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5409fcf5ef2aSThomas Huth tcg_temp_free(t0); 5410fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5411fcf5ef2aSThomas Huth } 5412fcf5ef2aSThomas Huth 5413fcf5ef2aSThomas Huth /* mtsr */ 5414fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5415fcf5ef2aSThomas Huth { 5416fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5417fcf5ef2aSThomas Huth GEN_PRIV; 5418fcf5ef2aSThomas Huth #else 5419fcf5ef2aSThomas Huth TCGv t0; 5420fcf5ef2aSThomas Huth 5421fcf5ef2aSThomas Huth CHK_SV; 5422fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5423fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5424fcf5ef2aSThomas Huth tcg_temp_free(t0); 5425fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5426fcf5ef2aSThomas Huth } 5427fcf5ef2aSThomas Huth 5428fcf5ef2aSThomas Huth /* mtsrin */ 5429fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5430fcf5ef2aSThomas Huth { 5431fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5432fcf5ef2aSThomas Huth GEN_PRIV; 5433fcf5ef2aSThomas Huth #else 5434fcf5ef2aSThomas Huth TCGv t0; 5435fcf5ef2aSThomas Huth 5436fcf5ef2aSThomas Huth CHK_SV; 5437fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5438e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5439fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5440fcf5ef2aSThomas Huth tcg_temp_free(t0); 5441fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5442fcf5ef2aSThomas Huth } 5443fcf5ef2aSThomas Huth 5444fcf5ef2aSThomas Huth /* slbmte */ 5445fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5446fcf5ef2aSThomas Huth { 5447fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5448fcf5ef2aSThomas Huth GEN_PRIV; 5449fcf5ef2aSThomas Huth #else 5450fcf5ef2aSThomas Huth CHK_SV; 5451fcf5ef2aSThomas Huth 5452fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5453fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5454fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5455fcf5ef2aSThomas Huth } 5456fcf5ef2aSThomas Huth 5457fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5458fcf5ef2aSThomas Huth { 5459fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5460fcf5ef2aSThomas Huth GEN_PRIV; 5461fcf5ef2aSThomas Huth #else 5462fcf5ef2aSThomas Huth CHK_SV; 5463fcf5ef2aSThomas Huth 5464fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5465fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5466fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5467fcf5ef2aSThomas Huth } 5468fcf5ef2aSThomas Huth 5469fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5470fcf5ef2aSThomas Huth { 5471fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5472fcf5ef2aSThomas Huth GEN_PRIV; 5473fcf5ef2aSThomas Huth #else 5474fcf5ef2aSThomas Huth CHK_SV; 5475fcf5ef2aSThomas Huth 5476fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5477fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5478fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5479fcf5ef2aSThomas Huth } 5480fcf5ef2aSThomas Huth 5481fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5482fcf5ef2aSThomas Huth { 5483fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5484fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5485fcf5ef2aSThomas Huth #else 5486fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5487fcf5ef2aSThomas Huth 5488fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5489fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5490fcf5ef2aSThomas Huth return; 5491fcf5ef2aSThomas Huth } 5492fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5493fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5494fcf5ef2aSThomas Huth l1 = gen_new_label(); 5495fcf5ef2aSThomas Huth l2 = gen_new_label(); 5496fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5497fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5498efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5499fcf5ef2aSThomas Huth tcg_gen_br(l2); 5500fcf5ef2aSThomas Huth gen_set_label(l1); 5501fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5502fcf5ef2aSThomas Huth gen_set_label(l2); 5503fcf5ef2aSThomas Huth #endif 5504fcf5ef2aSThomas Huth } 5505fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5506fcf5ef2aSThomas Huth 5507fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5508fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5509fcf5ef2aSThomas Huth 5510fcf5ef2aSThomas Huth /* tlbia */ 5511fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5512fcf5ef2aSThomas Huth { 5513fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5514fcf5ef2aSThomas Huth GEN_PRIV; 5515fcf5ef2aSThomas Huth #else 5516fcf5ef2aSThomas Huth CHK_HV; 5517fcf5ef2aSThomas Huth 5518fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5519fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5520fcf5ef2aSThomas Huth } 5521fcf5ef2aSThomas Huth 5522fcf5ef2aSThomas Huth /* tlbiel */ 5523fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5524fcf5ef2aSThomas Huth { 5525fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5526fcf5ef2aSThomas Huth GEN_PRIV; 5527fcf5ef2aSThomas Huth #else 5528fcf5ef2aSThomas Huth CHK_SV; 5529fcf5ef2aSThomas Huth 5530fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5531fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5532fcf5ef2aSThomas Huth } 5533fcf5ef2aSThomas Huth 5534fcf5ef2aSThomas Huth /* tlbie */ 5535fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5536fcf5ef2aSThomas Huth { 5537fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5538fcf5ef2aSThomas Huth GEN_PRIV; 5539fcf5ef2aSThomas Huth #else 5540fcf5ef2aSThomas Huth TCGv_i32 t1; 5541c6fd28fdSSuraj Jitindar Singh 5542c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 554391c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5544c6fd28fdSSuraj Jitindar Singh } else { 5545c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5546c6fd28fdSSuraj Jitindar Singh } 5547fcf5ef2aSThomas Huth 5548fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5549fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5550fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5551fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5552fcf5ef2aSThomas Huth tcg_temp_free(t0); 5553fcf5ef2aSThomas Huth } else { 5554fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5555fcf5ef2aSThomas Huth } 5556fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5557fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5558fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5559fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5560fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5561fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5562fcf5ef2aSThomas Huth } 5563fcf5ef2aSThomas Huth 5564fcf5ef2aSThomas Huth /* tlbsync */ 5565fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5566fcf5ef2aSThomas Huth { 5567fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5568fcf5ef2aSThomas Huth GEN_PRIV; 5569fcf5ef2aSThomas Huth #else 557091c60f12SCédric Le Goater 557191c60f12SCédric Le Goater if (ctx->gtse) { 557291c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 557391c60f12SCédric Le Goater } else { 557491c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 557591c60f12SCédric Le Goater } 5576fcf5ef2aSThomas Huth 5577fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5578fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5579fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5580fcf5ef2aSThomas Huth } 5581fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5582fcf5ef2aSThomas Huth } 5583fcf5ef2aSThomas Huth 5584fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5585fcf5ef2aSThomas Huth /* slbia */ 5586fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5587fcf5ef2aSThomas Huth { 5588fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5589fcf5ef2aSThomas Huth GEN_PRIV; 5590fcf5ef2aSThomas Huth #else 55910418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 55920418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 55930418bf78SNicholas Piggin 5594fcf5ef2aSThomas Huth CHK_SV; 5595fcf5ef2aSThomas Huth 55960418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 55973119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5598fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5599fcf5ef2aSThomas Huth } 5600fcf5ef2aSThomas Huth 5601fcf5ef2aSThomas Huth /* slbie */ 5602fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5603fcf5ef2aSThomas Huth { 5604fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5605fcf5ef2aSThomas Huth GEN_PRIV; 5606fcf5ef2aSThomas Huth #else 5607fcf5ef2aSThomas Huth CHK_SV; 5608fcf5ef2aSThomas Huth 5609fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5610fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5611fcf5ef2aSThomas Huth } 5612a63f1dfcSNikunj A Dadhania 5613a63f1dfcSNikunj A Dadhania /* slbieg */ 5614a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5615a63f1dfcSNikunj A Dadhania { 5616a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5617a63f1dfcSNikunj A Dadhania GEN_PRIV; 5618a63f1dfcSNikunj A Dadhania #else 5619a63f1dfcSNikunj A Dadhania CHK_SV; 5620a63f1dfcSNikunj A Dadhania 5621a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5622a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5623a63f1dfcSNikunj A Dadhania } 5624a63f1dfcSNikunj A Dadhania 562562d897caSNikunj A Dadhania /* slbsync */ 562662d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 562762d897caSNikunj A Dadhania { 562862d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 562962d897caSNikunj A Dadhania GEN_PRIV; 563062d897caSNikunj A Dadhania #else 563162d897caSNikunj A Dadhania CHK_SV; 563262d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 563362d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 563462d897caSNikunj A Dadhania } 563562d897caSNikunj A Dadhania 5636fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5637fcf5ef2aSThomas Huth 5638fcf5ef2aSThomas Huth /*** External control ***/ 5639fcf5ef2aSThomas Huth /* Optional: */ 5640fcf5ef2aSThomas Huth 5641fcf5ef2aSThomas Huth /* eciwx */ 5642fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5643fcf5ef2aSThomas Huth { 5644fcf5ef2aSThomas Huth TCGv t0; 5645fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5646fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5647fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5648fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5649c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5650c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5651fcf5ef2aSThomas Huth tcg_temp_free(t0); 5652fcf5ef2aSThomas Huth } 5653fcf5ef2aSThomas Huth 5654fcf5ef2aSThomas Huth /* ecowx */ 5655fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5656fcf5ef2aSThomas Huth { 5657fcf5ef2aSThomas Huth TCGv t0; 5658fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5659fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5660fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5661fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5662c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5663c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5664fcf5ef2aSThomas Huth tcg_temp_free(t0); 5665fcf5ef2aSThomas Huth } 5666fcf5ef2aSThomas Huth 5667fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5668fcf5ef2aSThomas Huth 5669fcf5ef2aSThomas Huth /* abs - abs. */ 5670fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5671fcf5ef2aSThomas Huth { 5672fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5673fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5674fe21b785SRichard Henderson 5675fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5676efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5677fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5678fcf5ef2aSThomas Huth } 5679efe843d8SDavid Gibson } 5680fcf5ef2aSThomas Huth 5681fcf5ef2aSThomas Huth /* abso - abso. */ 5682fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5683fcf5ef2aSThomas Huth { 5684fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5685fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5686fe21b785SRichard Henderson 5687fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5688fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5689fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5690efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5691fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5692fcf5ef2aSThomas Huth } 5693efe843d8SDavid Gibson } 5694fcf5ef2aSThomas Huth 5695fcf5ef2aSThomas Huth /* clcs */ 5696fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5697fcf5ef2aSThomas Huth { 5698fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5699fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5700fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5701fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5702fcf5ef2aSThomas Huth } 5703fcf5ef2aSThomas Huth 5704fcf5ef2aSThomas Huth /* div - div. */ 5705fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5706fcf5ef2aSThomas Huth { 5707fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5708fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5709efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5710fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5711fcf5ef2aSThomas Huth } 5712efe843d8SDavid Gibson } 5713fcf5ef2aSThomas Huth 5714fcf5ef2aSThomas Huth /* divo - divo. */ 5715fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5716fcf5ef2aSThomas Huth { 5717fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5718fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5719efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5720fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5721fcf5ef2aSThomas Huth } 5722efe843d8SDavid Gibson } 5723fcf5ef2aSThomas Huth 5724fcf5ef2aSThomas Huth /* divs - divs. */ 5725fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5726fcf5ef2aSThomas Huth { 5727fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5728fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5729efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5730fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5731fcf5ef2aSThomas Huth } 5732efe843d8SDavid Gibson } 5733fcf5ef2aSThomas Huth 5734fcf5ef2aSThomas Huth /* divso - divso. */ 5735fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5736fcf5ef2aSThomas Huth { 5737fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5738fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5739efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5740fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5741fcf5ef2aSThomas Huth } 5742efe843d8SDavid Gibson } 5743fcf5ef2aSThomas Huth 5744fcf5ef2aSThomas Huth /* doz - doz. */ 5745fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5746fcf5ef2aSThomas Huth { 5747fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5748fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5749efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5750efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5751efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5752efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5753fcf5ef2aSThomas Huth tcg_gen_br(l2); 5754fcf5ef2aSThomas Huth gen_set_label(l1); 5755fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5756fcf5ef2aSThomas Huth gen_set_label(l2); 5757efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5758fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5759fcf5ef2aSThomas Huth } 5760efe843d8SDavid Gibson } 5761fcf5ef2aSThomas Huth 5762fcf5ef2aSThomas Huth /* dozo - dozo. */ 5763fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5764fcf5ef2aSThomas Huth { 5765fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5766fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5767fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5768fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5769fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5770fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5771fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5772efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5773efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5774fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5775fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5776fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5777fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5778fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5779fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5780fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5781fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5782fcf5ef2aSThomas Huth tcg_gen_br(l2); 5783fcf5ef2aSThomas Huth gen_set_label(l1); 5784fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5785fcf5ef2aSThomas Huth gen_set_label(l2); 5786fcf5ef2aSThomas Huth tcg_temp_free(t0); 5787fcf5ef2aSThomas Huth tcg_temp_free(t1); 5788fcf5ef2aSThomas Huth tcg_temp_free(t2); 5789efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5790fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5791fcf5ef2aSThomas Huth } 5792efe843d8SDavid Gibson } 5793fcf5ef2aSThomas Huth 5794fcf5ef2aSThomas Huth /* dozi */ 5795fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5796fcf5ef2aSThomas Huth { 5797fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5798fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5799fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5800fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5801fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5802fcf5ef2aSThomas Huth tcg_gen_br(l2); 5803fcf5ef2aSThomas Huth gen_set_label(l1); 5804fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5805fcf5ef2aSThomas Huth gen_set_label(l2); 5806efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5807fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5808fcf5ef2aSThomas Huth } 5809efe843d8SDavid Gibson } 5810fcf5ef2aSThomas Huth 5811fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5812fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5813fcf5ef2aSThomas Huth { 5814fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5815fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5816fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5817fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5818fcf5ef2aSThomas Huth 5819fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5820fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5821fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5822fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5823fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5824fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5825fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5826efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5827fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5828efe843d8SDavid Gibson } 5829fcf5ef2aSThomas Huth tcg_temp_free(t0); 5830fcf5ef2aSThomas Huth } 5831fcf5ef2aSThomas Huth 5832fcf5ef2aSThomas Huth /* maskg - maskg. */ 5833fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5834fcf5ef2aSThomas Huth { 5835fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5836fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5837fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5838fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5839fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5840fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5841fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5842fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5843fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5844fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5845fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5846fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5847fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5848fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5849fcf5ef2aSThomas Huth gen_set_label(l1); 5850fcf5ef2aSThomas Huth tcg_temp_free(t0); 5851fcf5ef2aSThomas Huth tcg_temp_free(t1); 5852fcf5ef2aSThomas Huth tcg_temp_free(t2); 5853fcf5ef2aSThomas Huth tcg_temp_free(t3); 5854efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5855fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5856fcf5ef2aSThomas Huth } 5857efe843d8SDavid Gibson } 5858fcf5ef2aSThomas Huth 5859fcf5ef2aSThomas Huth /* maskir - maskir. */ 5860fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5861fcf5ef2aSThomas Huth { 5862fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5863fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5864fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5865fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5866fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5867fcf5ef2aSThomas Huth tcg_temp_free(t0); 5868fcf5ef2aSThomas Huth tcg_temp_free(t1); 5869efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5870fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5871fcf5ef2aSThomas Huth } 5872efe843d8SDavid Gibson } 5873fcf5ef2aSThomas Huth 5874fcf5ef2aSThomas Huth /* mul - mul. */ 5875fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5876fcf5ef2aSThomas Huth { 5877fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5878fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5879fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5880fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5881fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5882fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5883fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5884fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5885fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5886fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5887fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5888fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5889fcf5ef2aSThomas Huth tcg_temp_free(t2); 5890efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5891fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5892fcf5ef2aSThomas Huth } 5893efe843d8SDavid Gibson } 5894fcf5ef2aSThomas Huth 5895fcf5ef2aSThomas Huth /* mulo - mulo. */ 5896fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5897fcf5ef2aSThomas Huth { 5898fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5899fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5900fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5901fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5902fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5903fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5904fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5905fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5906fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5907fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5908fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5909fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5910fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5911fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5912fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5913fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5914fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5915fcf5ef2aSThomas Huth gen_set_label(l1); 5916fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5917fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5918fcf5ef2aSThomas Huth tcg_temp_free(t2); 5919efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5920fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5921fcf5ef2aSThomas Huth } 5922efe843d8SDavid Gibson } 5923fcf5ef2aSThomas Huth 5924fcf5ef2aSThomas Huth /* nabs - nabs. */ 5925fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5926fcf5ef2aSThomas Huth { 5927fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5928fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5929fe21b785SRichard Henderson 5930fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5931fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5932efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5933fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5934fcf5ef2aSThomas Huth } 5935efe843d8SDavid Gibson } 5936fcf5ef2aSThomas Huth 5937fcf5ef2aSThomas Huth /* nabso - nabso. */ 5938fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5939fcf5ef2aSThomas Huth { 5940fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5941fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5942fe21b785SRichard Henderson 5943fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5944fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5945fcf5ef2aSThomas Huth /* nabs never overflows */ 5946fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5947efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5948fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5949fcf5ef2aSThomas Huth } 5950efe843d8SDavid Gibson } 5951fcf5ef2aSThomas Huth 5952fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5953fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5954fcf5ef2aSThomas Huth { 5955fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5956fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5957fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5958fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5959fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5960fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5961efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5962efe843d8SDavid Gibson ~MASK(mb, me)); 5963fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5964fcf5ef2aSThomas Huth tcg_temp_free(t0); 5965efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5966fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5967fcf5ef2aSThomas Huth } 5968efe843d8SDavid Gibson } 5969fcf5ef2aSThomas Huth 5970fcf5ef2aSThomas Huth /* rrib - rrib. */ 5971fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5972fcf5ef2aSThomas Huth { 5973fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5974fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5975fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5976fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5977fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5978fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5979fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5980fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5981fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5982fcf5ef2aSThomas Huth tcg_temp_free(t0); 5983fcf5ef2aSThomas Huth tcg_temp_free(t1); 5984efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5985fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5986fcf5ef2aSThomas Huth } 5987efe843d8SDavid Gibson } 5988fcf5ef2aSThomas Huth 5989fcf5ef2aSThomas Huth /* sle - sle. */ 5990fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5991fcf5ef2aSThomas Huth { 5992fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5993fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5994fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5995fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5996fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5997fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5998fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5999fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6000fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6001fcf5ef2aSThomas Huth tcg_temp_free(t0); 6002fcf5ef2aSThomas Huth tcg_temp_free(t1); 6003efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6004fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6005fcf5ef2aSThomas Huth } 6006efe843d8SDavid Gibson } 6007fcf5ef2aSThomas Huth 6008fcf5ef2aSThomas Huth /* sleq - sleq. */ 6009fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6010fcf5ef2aSThomas Huth { 6011fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6012fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6013fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6014fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6015fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6016fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6017fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6018fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6019fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6020fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6021fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6022fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6023fcf5ef2aSThomas Huth tcg_temp_free(t0); 6024fcf5ef2aSThomas Huth tcg_temp_free(t1); 6025fcf5ef2aSThomas Huth tcg_temp_free(t2); 6026efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6027fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6028fcf5ef2aSThomas Huth } 6029efe843d8SDavid Gibson } 6030fcf5ef2aSThomas Huth 6031fcf5ef2aSThomas Huth /* sliq - sliq. */ 6032fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6033fcf5ef2aSThomas Huth { 6034fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6035fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6036fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6037fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6038fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6039fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6040fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6041fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6042fcf5ef2aSThomas Huth tcg_temp_free(t0); 6043fcf5ef2aSThomas Huth tcg_temp_free(t1); 6044efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6045fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6046fcf5ef2aSThomas Huth } 6047efe843d8SDavid Gibson } 6048fcf5ef2aSThomas Huth 6049fcf5ef2aSThomas Huth /* slliq - slliq. */ 6050fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6051fcf5ef2aSThomas Huth { 6052fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6053fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6054fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6055fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6056fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6057fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6058fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6059fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6060fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6061fcf5ef2aSThomas Huth tcg_temp_free(t0); 6062fcf5ef2aSThomas Huth tcg_temp_free(t1); 6063efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6064fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6065fcf5ef2aSThomas Huth } 6066efe843d8SDavid Gibson } 6067fcf5ef2aSThomas Huth 6068fcf5ef2aSThomas Huth /* sllq - sllq. */ 6069fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6070fcf5ef2aSThomas Huth { 6071fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6072fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6073fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6074fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6075fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6076fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6077fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6078fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6079fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6080fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6081fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6082fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6083fcf5ef2aSThomas Huth tcg_gen_br(l2); 6084fcf5ef2aSThomas Huth gen_set_label(l1); 6085fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6086fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6087fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6088fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6089fcf5ef2aSThomas Huth gen_set_label(l2); 6090fcf5ef2aSThomas Huth tcg_temp_free(t0); 6091fcf5ef2aSThomas Huth tcg_temp_free(t1); 6092fcf5ef2aSThomas Huth tcg_temp_free(t2); 6093efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6094fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6095fcf5ef2aSThomas Huth } 6096efe843d8SDavid Gibson } 6097fcf5ef2aSThomas Huth 6098fcf5ef2aSThomas Huth /* slq - slq. */ 6099fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6100fcf5ef2aSThomas Huth { 6101fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6102fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6103fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6104fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6105fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6106fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6107fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6108fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6109fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6110fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6111fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6112fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6113fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6114fcf5ef2aSThomas Huth gen_set_label(l1); 6115fcf5ef2aSThomas Huth tcg_temp_free(t0); 6116fcf5ef2aSThomas Huth tcg_temp_free(t1); 6117efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6118fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6119fcf5ef2aSThomas Huth } 6120efe843d8SDavid Gibson } 6121fcf5ef2aSThomas Huth 6122fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6123fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6124fcf5ef2aSThomas Huth { 6125fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6126fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6127fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6128fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6129fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6130fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6131fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6132fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6133fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6134fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6135fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6136fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6137fcf5ef2aSThomas Huth gen_set_label(l1); 6138fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6139fcf5ef2aSThomas Huth tcg_temp_free(t0); 6140fcf5ef2aSThomas Huth tcg_temp_free(t1); 6141efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6142fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6143fcf5ef2aSThomas Huth } 6144efe843d8SDavid Gibson } 6145fcf5ef2aSThomas Huth 6146fcf5ef2aSThomas Huth /* sraq - sraq. */ 6147fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6148fcf5ef2aSThomas Huth { 6149fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6150fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6151fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6152fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6153fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6154fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6155fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6156fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6157fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6158fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6159fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6160fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6161fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6162fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6163fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6164fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6165fcf5ef2aSThomas Huth gen_set_label(l1); 6166fcf5ef2aSThomas Huth tcg_temp_free(t0); 6167fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6168fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6169fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6170fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6171fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6172fcf5ef2aSThomas Huth gen_set_label(l2); 6173fcf5ef2aSThomas Huth tcg_temp_free(t1); 6174fcf5ef2aSThomas Huth tcg_temp_free(t2); 6175efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6176fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6177fcf5ef2aSThomas Huth } 6178efe843d8SDavid Gibson } 6179fcf5ef2aSThomas Huth 6180fcf5ef2aSThomas Huth /* sre - sre. */ 6181fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6182fcf5ef2aSThomas Huth { 6183fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6184fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6185fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6186fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6187fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6188fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6189fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6190fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6191fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6192fcf5ef2aSThomas Huth tcg_temp_free(t0); 6193fcf5ef2aSThomas Huth tcg_temp_free(t1); 6194efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6195fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6196fcf5ef2aSThomas Huth } 6197efe843d8SDavid Gibson } 6198fcf5ef2aSThomas Huth 6199fcf5ef2aSThomas Huth /* srea - srea. */ 6200fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6201fcf5ef2aSThomas Huth { 6202fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6203fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6204fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6205fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6206fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6207fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6208fcf5ef2aSThomas Huth tcg_temp_free(t0); 6209fcf5ef2aSThomas Huth tcg_temp_free(t1); 6210efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6211fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6212fcf5ef2aSThomas Huth } 6213efe843d8SDavid Gibson } 6214fcf5ef2aSThomas Huth 6215fcf5ef2aSThomas Huth /* sreq */ 6216fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6217fcf5ef2aSThomas Huth { 6218fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6219fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6220fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6221fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6222fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6223fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6224fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6225fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6226fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6227fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6228fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6229fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6230fcf5ef2aSThomas Huth tcg_temp_free(t0); 6231fcf5ef2aSThomas Huth tcg_temp_free(t1); 6232fcf5ef2aSThomas Huth tcg_temp_free(t2); 6233efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6234fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6235fcf5ef2aSThomas Huth } 6236efe843d8SDavid Gibson } 6237fcf5ef2aSThomas Huth 6238fcf5ef2aSThomas Huth /* sriq */ 6239fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6240fcf5ef2aSThomas Huth { 6241fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6242fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6243fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6244fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6245fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6246fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6247fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6248fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6249fcf5ef2aSThomas Huth tcg_temp_free(t0); 6250fcf5ef2aSThomas Huth tcg_temp_free(t1); 6251efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6252fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6253fcf5ef2aSThomas Huth } 6254efe843d8SDavid Gibson } 6255fcf5ef2aSThomas Huth 6256fcf5ef2aSThomas Huth /* srliq */ 6257fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6258fcf5ef2aSThomas Huth { 6259fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6260fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6261fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6262fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6263fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6264fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6265fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6266fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6267fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6268fcf5ef2aSThomas Huth tcg_temp_free(t0); 6269fcf5ef2aSThomas Huth tcg_temp_free(t1); 6270efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6271fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6272fcf5ef2aSThomas Huth } 6273efe843d8SDavid Gibson } 6274fcf5ef2aSThomas Huth 6275fcf5ef2aSThomas Huth /* srlq */ 6276fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6277fcf5ef2aSThomas Huth { 6278fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6279fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6280fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6281fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6282fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6283fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6284fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6285fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6286fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6287fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6288fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6289fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6290fcf5ef2aSThomas Huth tcg_gen_br(l2); 6291fcf5ef2aSThomas Huth gen_set_label(l1); 6292fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6293fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6294fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6295fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6296fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6297fcf5ef2aSThomas Huth gen_set_label(l2); 6298fcf5ef2aSThomas Huth tcg_temp_free(t0); 6299fcf5ef2aSThomas Huth tcg_temp_free(t1); 6300fcf5ef2aSThomas Huth tcg_temp_free(t2); 6301efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6302fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6303fcf5ef2aSThomas Huth } 6304efe843d8SDavid Gibson } 6305fcf5ef2aSThomas Huth 6306fcf5ef2aSThomas Huth /* srq */ 6307fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6308fcf5ef2aSThomas Huth { 6309fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6310fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6311fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6312fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6313fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6314fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6315fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6316fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6317fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6318fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6319fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6320fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6321fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6322fcf5ef2aSThomas Huth gen_set_label(l1); 6323fcf5ef2aSThomas Huth tcg_temp_free(t0); 6324fcf5ef2aSThomas Huth tcg_temp_free(t1); 6325efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6326fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6327fcf5ef2aSThomas Huth } 6328efe843d8SDavid Gibson } 6329fcf5ef2aSThomas Huth 6330fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6331fcf5ef2aSThomas Huth 6332fcf5ef2aSThomas Huth /* dsa */ 6333fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6334fcf5ef2aSThomas Huth { 6335fcf5ef2aSThomas Huth /* XXX: TODO */ 6336fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6337fcf5ef2aSThomas Huth } 6338fcf5ef2aSThomas Huth 6339fcf5ef2aSThomas Huth /* esa */ 6340fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6341fcf5ef2aSThomas Huth { 6342fcf5ef2aSThomas Huth /* XXX: TODO */ 6343fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6344fcf5ef2aSThomas Huth } 6345fcf5ef2aSThomas Huth 6346fcf5ef2aSThomas Huth /* mfrom */ 6347fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6348fcf5ef2aSThomas Huth { 6349fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6350fcf5ef2aSThomas Huth GEN_PRIV; 6351fcf5ef2aSThomas Huth #else 6352fcf5ef2aSThomas Huth CHK_SV; 6353fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6354fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6355fcf5ef2aSThomas Huth } 6356fcf5ef2aSThomas Huth 6357fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6358fcf5ef2aSThomas Huth 6359fcf5ef2aSThomas Huth /* tlbld */ 6360fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6361fcf5ef2aSThomas Huth { 6362fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6363fcf5ef2aSThomas Huth GEN_PRIV; 6364fcf5ef2aSThomas Huth #else 6365fcf5ef2aSThomas Huth CHK_SV; 6366fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6367fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6368fcf5ef2aSThomas Huth } 6369fcf5ef2aSThomas Huth 6370fcf5ef2aSThomas Huth /* tlbli */ 6371fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6372fcf5ef2aSThomas Huth { 6373fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6374fcf5ef2aSThomas Huth GEN_PRIV; 6375fcf5ef2aSThomas Huth #else 6376fcf5ef2aSThomas Huth CHK_SV; 6377fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6378fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6379fcf5ef2aSThomas Huth } 6380fcf5ef2aSThomas Huth 6381fcf5ef2aSThomas Huth /* 74xx TLB management */ 6382fcf5ef2aSThomas Huth 6383fcf5ef2aSThomas Huth /* tlbld */ 6384fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6385fcf5ef2aSThomas Huth { 6386fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6387fcf5ef2aSThomas Huth GEN_PRIV; 6388fcf5ef2aSThomas Huth #else 6389fcf5ef2aSThomas Huth CHK_SV; 6390fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6391fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6392fcf5ef2aSThomas Huth } 6393fcf5ef2aSThomas Huth 6394fcf5ef2aSThomas Huth /* tlbli */ 6395fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6396fcf5ef2aSThomas Huth { 6397fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6398fcf5ef2aSThomas Huth GEN_PRIV; 6399fcf5ef2aSThomas Huth #else 6400fcf5ef2aSThomas Huth CHK_SV; 6401fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6402fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6403fcf5ef2aSThomas Huth } 6404fcf5ef2aSThomas Huth 6405fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6406fcf5ef2aSThomas Huth 6407fcf5ef2aSThomas Huth /* clf */ 6408fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6409fcf5ef2aSThomas Huth { 6410fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6411fcf5ef2aSThomas Huth } 6412fcf5ef2aSThomas Huth 6413fcf5ef2aSThomas Huth /* cli */ 6414fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6415fcf5ef2aSThomas Huth { 6416fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6417fcf5ef2aSThomas Huth GEN_PRIV; 6418fcf5ef2aSThomas Huth #else 6419fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6420fcf5ef2aSThomas Huth CHK_SV; 6421fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6422fcf5ef2aSThomas Huth } 6423fcf5ef2aSThomas Huth 6424fcf5ef2aSThomas Huth /* dclst */ 6425fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6426fcf5ef2aSThomas Huth { 6427fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6428fcf5ef2aSThomas Huth } 6429fcf5ef2aSThomas Huth 6430fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6431fcf5ef2aSThomas Huth { 6432fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6433fcf5ef2aSThomas Huth GEN_PRIV; 6434fcf5ef2aSThomas Huth #else 6435fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6436fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6437fcf5ef2aSThomas Huth TCGv t0; 6438fcf5ef2aSThomas Huth 6439fcf5ef2aSThomas Huth CHK_SV; 6440fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6441fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6442e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6443fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6444fcf5ef2aSThomas Huth tcg_temp_free(t0); 6445efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6446fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6447efe843d8SDavid Gibson } 6448fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6449fcf5ef2aSThomas Huth } 6450fcf5ef2aSThomas Huth 6451fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6452fcf5ef2aSThomas Huth { 6453fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6454fcf5ef2aSThomas Huth GEN_PRIV; 6455fcf5ef2aSThomas Huth #else 6456fcf5ef2aSThomas Huth TCGv t0; 6457fcf5ef2aSThomas Huth 6458fcf5ef2aSThomas Huth CHK_SV; 6459fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6460fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6461fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6462fcf5ef2aSThomas Huth tcg_temp_free(t0); 6463fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6464fcf5ef2aSThomas Huth } 6465fcf5ef2aSThomas Huth 6466fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6467fcf5ef2aSThomas Huth { 6468fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6469fcf5ef2aSThomas Huth GEN_PRIV; 6470fcf5ef2aSThomas Huth #else 6471fcf5ef2aSThomas Huth CHK_SV; 6472fcf5ef2aSThomas Huth 6473fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 647459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6475fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6476fcf5ef2aSThomas Huth } 6477fcf5ef2aSThomas Huth 6478fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6479fcf5ef2aSThomas Huth 6480fcf5ef2aSThomas Huth /* BookE specific instructions */ 6481fcf5ef2aSThomas Huth 6482fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6483fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6484fcf5ef2aSThomas Huth { 6485fcf5ef2aSThomas Huth /* XXX: TODO */ 6486fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6487fcf5ef2aSThomas Huth } 6488fcf5ef2aSThomas Huth 6489fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6490fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6491fcf5ef2aSThomas Huth { 6492fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6493fcf5ef2aSThomas Huth GEN_PRIV; 6494fcf5ef2aSThomas Huth #else 6495fcf5ef2aSThomas Huth TCGv t0; 6496fcf5ef2aSThomas Huth 6497fcf5ef2aSThomas Huth CHK_SV; 6498fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6499fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6500fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6501fcf5ef2aSThomas Huth tcg_temp_free(t0); 6502fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6503fcf5ef2aSThomas Huth } 6504fcf5ef2aSThomas Huth 6505fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6506fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6507fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6508fcf5ef2aSThomas Huth { 6509fcf5ef2aSThomas Huth TCGv t0, t1; 6510fcf5ef2aSThomas Huth 6511fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6512fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6513fcf5ef2aSThomas Huth 6514fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6515fcf5ef2aSThomas Huth case 0x05: 6516fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6517fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6518fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6519fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6520fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6521fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6522fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6523fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6524fcf5ef2aSThomas Huth break; 6525fcf5ef2aSThomas Huth case 0x04: 6526fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6527fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6528fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6529fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6530fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6531fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6532fcf5ef2aSThomas Huth break; 6533fcf5ef2aSThomas Huth case 0x01: 6534fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6535fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6536fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6537fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6538fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6539fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6540fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6541fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6542fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6543fcf5ef2aSThomas Huth break; 6544fcf5ef2aSThomas Huth case 0x00: 6545fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6546fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6547fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6548fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6549fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6550fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6551fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6552fcf5ef2aSThomas Huth break; 6553fcf5ef2aSThomas Huth case 0x0D: 6554fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6555fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6556fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6557fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6558fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6559fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6560fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6561fcf5ef2aSThomas Huth break; 6562fcf5ef2aSThomas Huth case 0x0C: 6563fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6564fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6565fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6566fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6567fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6568fcf5ef2aSThomas Huth break; 6569fcf5ef2aSThomas Huth } 6570fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6571fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6572fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6573fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6574fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6575fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6576fcf5ef2aSThomas Huth } else { 6577fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6578fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6579fcf5ef2aSThomas Huth } 6580fcf5ef2aSThomas Huth 6581fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6582fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6583fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6584fcf5ef2aSThomas Huth 6585fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6586fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6587fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6588fcf5ef2aSThomas Huth } 6589fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6590fcf5ef2aSThomas Huth /* Signed */ 6591fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6592fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6593fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6594fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6595fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6596fcf5ef2aSThomas Huth /* Saturate */ 6597fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6598fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6599fcf5ef2aSThomas Huth } 6600fcf5ef2aSThomas Huth } else { 6601fcf5ef2aSThomas Huth /* Unsigned */ 6602fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6603fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6604fcf5ef2aSThomas Huth /* Saturate */ 6605fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6606fcf5ef2aSThomas Huth } 6607fcf5ef2aSThomas Huth } 6608fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6609fcf5ef2aSThomas Huth /* Check overflow */ 6610fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6611fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6612fcf5ef2aSThomas Huth } 6613fcf5ef2aSThomas Huth gen_set_label(l1); 6614fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6615fcf5ef2aSThomas Huth } 6616fcf5ef2aSThomas Huth } else { 6617fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6618fcf5ef2aSThomas Huth } 6619fcf5ef2aSThomas Huth tcg_temp_free(t0); 6620fcf5ef2aSThomas Huth tcg_temp_free(t1); 6621fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6622fcf5ef2aSThomas Huth /* Update Rc0 */ 6623fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6624fcf5ef2aSThomas Huth } 6625fcf5ef2aSThomas Huth } 6626fcf5ef2aSThomas Huth 6627fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6628fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6629fcf5ef2aSThomas Huth { \ 6630fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6631fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6632fcf5ef2aSThomas Huth } 6633fcf5ef2aSThomas Huth 6634fcf5ef2aSThomas Huth /* macchw - macchw. */ 6635fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6636fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6637fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6638fcf5ef2aSThomas Huth /* macchws - macchws. */ 6639fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6640fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6641fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6642fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6643fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6644fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6645fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6646fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6647fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6648fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6649fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6650fcf5ef2aSThomas Huth /* machhw - machhw. */ 6651fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6652fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6653fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6654fcf5ef2aSThomas Huth /* machhws - machhws. */ 6655fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6656fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6657fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6658fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6659fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6660fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6661fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6662fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6663fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6664fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6665fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6666fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6667fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6668fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6669fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6670fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6671fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6672fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6673fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6674fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6675fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6676fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6677fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6678fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6679fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6680fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6681fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6682fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6683fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6684fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6685fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6686fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6687fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6688fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6689fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6690fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6691fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6692fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6693fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6694fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6695fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6696fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6697fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6698fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6699fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6700fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6701fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6702fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6703fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6704fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6705fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6706fcf5ef2aSThomas Huth 6707fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6708fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6709fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6710fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6711fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6712fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6713fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6714fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6715fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6716fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6717fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6718fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6719fcf5ef2aSThomas Huth 6720fcf5ef2aSThomas Huth /* mfdcr */ 6721fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6722fcf5ef2aSThomas Huth { 6723fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6724fcf5ef2aSThomas Huth GEN_PRIV; 6725fcf5ef2aSThomas Huth #else 6726fcf5ef2aSThomas Huth TCGv dcrn; 6727fcf5ef2aSThomas Huth 6728fcf5ef2aSThomas Huth CHK_SV; 6729fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6730fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6731fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6732fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6733fcf5ef2aSThomas Huth } 6734fcf5ef2aSThomas Huth 6735fcf5ef2aSThomas Huth /* mtdcr */ 6736fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6737fcf5ef2aSThomas Huth { 6738fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6739fcf5ef2aSThomas Huth GEN_PRIV; 6740fcf5ef2aSThomas Huth #else 6741fcf5ef2aSThomas Huth TCGv dcrn; 6742fcf5ef2aSThomas Huth 6743fcf5ef2aSThomas Huth CHK_SV; 6744fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6745fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6746fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6747fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6748fcf5ef2aSThomas Huth } 6749fcf5ef2aSThomas Huth 6750fcf5ef2aSThomas Huth /* mfdcrx */ 6751fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6752fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6753fcf5ef2aSThomas Huth { 6754fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6755fcf5ef2aSThomas Huth GEN_PRIV; 6756fcf5ef2aSThomas Huth #else 6757fcf5ef2aSThomas Huth CHK_SV; 6758fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6759fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6760fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6761fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6762fcf5ef2aSThomas Huth } 6763fcf5ef2aSThomas Huth 6764fcf5ef2aSThomas Huth /* mtdcrx */ 6765fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6766fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6767fcf5ef2aSThomas Huth { 6768fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6769fcf5ef2aSThomas Huth GEN_PRIV; 6770fcf5ef2aSThomas Huth #else 6771fcf5ef2aSThomas Huth CHK_SV; 6772fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6773fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6774fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6775fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6776fcf5ef2aSThomas Huth } 6777fcf5ef2aSThomas Huth 6778fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6779fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6780fcf5ef2aSThomas Huth { 6781fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6782fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6783fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6784fcf5ef2aSThomas Huth } 6785fcf5ef2aSThomas Huth 6786fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6787fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6788fcf5ef2aSThomas Huth { 6789fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6790fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6791fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6792fcf5ef2aSThomas Huth } 6793fcf5ef2aSThomas Huth 6794fcf5ef2aSThomas Huth /* dccci */ 6795fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6796fcf5ef2aSThomas Huth { 6797fcf5ef2aSThomas Huth CHK_SV; 6798fcf5ef2aSThomas Huth /* interpreted as no-op */ 6799fcf5ef2aSThomas Huth } 6800fcf5ef2aSThomas Huth 6801fcf5ef2aSThomas Huth /* dcread */ 6802fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6803fcf5ef2aSThomas Huth { 6804fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6805fcf5ef2aSThomas Huth GEN_PRIV; 6806fcf5ef2aSThomas Huth #else 6807fcf5ef2aSThomas Huth TCGv EA, val; 6808fcf5ef2aSThomas Huth 6809fcf5ef2aSThomas Huth CHK_SV; 6810fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6811fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6812fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6813fcf5ef2aSThomas Huth val = tcg_temp_new(); 6814fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6815fcf5ef2aSThomas Huth tcg_temp_free(val); 6816fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6817fcf5ef2aSThomas Huth tcg_temp_free(EA); 6818fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6819fcf5ef2aSThomas Huth } 6820fcf5ef2aSThomas Huth 6821fcf5ef2aSThomas Huth /* icbt */ 6822fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6823fcf5ef2aSThomas Huth { 6824efe843d8SDavid Gibson /* 6825efe843d8SDavid Gibson * interpreted as no-op 6826efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6827efe843d8SDavid Gibson * does not generate any exception 6828fcf5ef2aSThomas Huth */ 6829fcf5ef2aSThomas Huth } 6830fcf5ef2aSThomas Huth 6831fcf5ef2aSThomas Huth /* iccci */ 6832fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6833fcf5ef2aSThomas Huth { 6834fcf5ef2aSThomas Huth CHK_SV; 6835fcf5ef2aSThomas Huth /* interpreted as no-op */ 6836fcf5ef2aSThomas Huth } 6837fcf5ef2aSThomas Huth 6838fcf5ef2aSThomas Huth /* icread */ 6839fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6840fcf5ef2aSThomas Huth { 6841fcf5ef2aSThomas Huth CHK_SV; 6842fcf5ef2aSThomas Huth /* interpreted as no-op */ 6843fcf5ef2aSThomas Huth } 6844fcf5ef2aSThomas Huth 6845fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6846fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6847fcf5ef2aSThomas Huth { 6848fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6849fcf5ef2aSThomas Huth GEN_PRIV; 6850fcf5ef2aSThomas Huth #else 6851fcf5ef2aSThomas Huth CHK_SV; 6852fcf5ef2aSThomas Huth /* Restore CPU state */ 6853fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 685459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6855fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6856fcf5ef2aSThomas Huth } 6857fcf5ef2aSThomas Huth 6858fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6859fcf5ef2aSThomas Huth { 6860fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6861fcf5ef2aSThomas Huth GEN_PRIV; 6862fcf5ef2aSThomas Huth #else 6863fcf5ef2aSThomas Huth CHK_SV; 6864fcf5ef2aSThomas Huth /* Restore CPU state */ 6865fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 686659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6867fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6868fcf5ef2aSThomas Huth } 6869fcf5ef2aSThomas Huth 6870fcf5ef2aSThomas Huth /* BookE specific */ 6871fcf5ef2aSThomas Huth 6872fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6873fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6874fcf5ef2aSThomas Huth { 6875fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6876fcf5ef2aSThomas Huth GEN_PRIV; 6877fcf5ef2aSThomas Huth #else 6878fcf5ef2aSThomas Huth CHK_SV; 6879fcf5ef2aSThomas Huth /* Restore CPU state */ 6880fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 688159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6882fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6883fcf5ef2aSThomas Huth } 6884fcf5ef2aSThomas Huth 6885fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6886fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6887fcf5ef2aSThomas Huth { 6888fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6889fcf5ef2aSThomas Huth GEN_PRIV; 6890fcf5ef2aSThomas Huth #else 6891fcf5ef2aSThomas Huth CHK_SV; 6892fcf5ef2aSThomas Huth /* Restore CPU state */ 6893fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 689459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6895fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6896fcf5ef2aSThomas Huth } 6897fcf5ef2aSThomas Huth 6898fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6899fcf5ef2aSThomas Huth 6900fcf5ef2aSThomas Huth /* tlbre */ 6901fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6902fcf5ef2aSThomas Huth { 6903fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6904fcf5ef2aSThomas Huth GEN_PRIV; 6905fcf5ef2aSThomas Huth #else 6906fcf5ef2aSThomas Huth CHK_SV; 6907fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6908fcf5ef2aSThomas Huth case 0: 6909fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6910fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6911fcf5ef2aSThomas Huth break; 6912fcf5ef2aSThomas Huth case 1: 6913fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6914fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6915fcf5ef2aSThomas Huth break; 6916fcf5ef2aSThomas Huth default: 6917fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6918fcf5ef2aSThomas Huth break; 6919fcf5ef2aSThomas Huth } 6920fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6921fcf5ef2aSThomas Huth } 6922fcf5ef2aSThomas Huth 6923fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6924fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6925fcf5ef2aSThomas Huth { 6926fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6927fcf5ef2aSThomas Huth GEN_PRIV; 6928fcf5ef2aSThomas Huth #else 6929fcf5ef2aSThomas Huth TCGv t0; 6930fcf5ef2aSThomas Huth 6931fcf5ef2aSThomas Huth CHK_SV; 6932fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6933fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6934fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6935fcf5ef2aSThomas Huth tcg_temp_free(t0); 6936fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6937fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6938fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6939fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6940fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6941fcf5ef2aSThomas Huth gen_set_label(l1); 6942fcf5ef2aSThomas Huth } 6943fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6944fcf5ef2aSThomas Huth } 6945fcf5ef2aSThomas Huth 6946fcf5ef2aSThomas Huth /* tlbwe */ 6947fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6948fcf5ef2aSThomas Huth { 6949fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6950fcf5ef2aSThomas Huth GEN_PRIV; 6951fcf5ef2aSThomas Huth #else 6952fcf5ef2aSThomas Huth CHK_SV; 6953fcf5ef2aSThomas Huth 6954fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6955fcf5ef2aSThomas Huth case 0: 6956fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6957fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6958fcf5ef2aSThomas Huth break; 6959fcf5ef2aSThomas Huth case 1: 6960fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6961fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6962fcf5ef2aSThomas Huth break; 6963fcf5ef2aSThomas Huth default: 6964fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6965fcf5ef2aSThomas Huth break; 6966fcf5ef2aSThomas Huth } 6967fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6968fcf5ef2aSThomas Huth } 6969fcf5ef2aSThomas Huth 6970fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6971fcf5ef2aSThomas Huth 6972fcf5ef2aSThomas Huth /* tlbre */ 6973fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6974fcf5ef2aSThomas Huth { 6975fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6976fcf5ef2aSThomas Huth GEN_PRIV; 6977fcf5ef2aSThomas Huth #else 6978fcf5ef2aSThomas Huth CHK_SV; 6979fcf5ef2aSThomas Huth 6980fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6981fcf5ef2aSThomas Huth case 0: 6982fcf5ef2aSThomas Huth case 1: 6983fcf5ef2aSThomas Huth case 2: 6984fcf5ef2aSThomas Huth { 6985fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6986fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6987fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6988fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6989fcf5ef2aSThomas Huth } 6990fcf5ef2aSThomas Huth break; 6991fcf5ef2aSThomas Huth default: 6992fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6993fcf5ef2aSThomas Huth break; 6994fcf5ef2aSThomas Huth } 6995fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6996fcf5ef2aSThomas Huth } 6997fcf5ef2aSThomas Huth 6998fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6999fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7000fcf5ef2aSThomas Huth { 7001fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7002fcf5ef2aSThomas Huth GEN_PRIV; 7003fcf5ef2aSThomas Huth #else 7004fcf5ef2aSThomas Huth TCGv t0; 7005fcf5ef2aSThomas Huth 7006fcf5ef2aSThomas Huth CHK_SV; 7007fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7008fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7009fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7010fcf5ef2aSThomas Huth tcg_temp_free(t0); 7011fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7012fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7013fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7014fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7015fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7016fcf5ef2aSThomas Huth gen_set_label(l1); 7017fcf5ef2aSThomas Huth } 7018fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7019fcf5ef2aSThomas Huth } 7020fcf5ef2aSThomas Huth 7021fcf5ef2aSThomas Huth /* tlbwe */ 7022fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7023fcf5ef2aSThomas Huth { 7024fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7025fcf5ef2aSThomas Huth GEN_PRIV; 7026fcf5ef2aSThomas Huth #else 7027fcf5ef2aSThomas Huth CHK_SV; 7028fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7029fcf5ef2aSThomas Huth case 0: 7030fcf5ef2aSThomas Huth case 1: 7031fcf5ef2aSThomas Huth case 2: 7032fcf5ef2aSThomas Huth { 7033fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7034fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7035fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7036fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7037fcf5ef2aSThomas Huth } 7038fcf5ef2aSThomas Huth break; 7039fcf5ef2aSThomas Huth default: 7040fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7041fcf5ef2aSThomas Huth break; 7042fcf5ef2aSThomas Huth } 7043fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7044fcf5ef2aSThomas Huth } 7045fcf5ef2aSThomas Huth 7046fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7047fcf5ef2aSThomas Huth 7048fcf5ef2aSThomas Huth /* tlbre */ 7049fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7050fcf5ef2aSThomas Huth { 7051fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7052fcf5ef2aSThomas Huth GEN_PRIV; 7053fcf5ef2aSThomas Huth #else 7054fcf5ef2aSThomas Huth CHK_SV; 7055fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7056fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7057fcf5ef2aSThomas Huth } 7058fcf5ef2aSThomas Huth 7059fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7060fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7061fcf5ef2aSThomas Huth { 7062fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7063fcf5ef2aSThomas Huth GEN_PRIV; 7064fcf5ef2aSThomas Huth #else 7065fcf5ef2aSThomas Huth TCGv t0; 7066fcf5ef2aSThomas Huth 7067fcf5ef2aSThomas Huth CHK_SV; 7068fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7069fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7070fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7071fcf5ef2aSThomas Huth } else { 7072fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7073fcf5ef2aSThomas Huth } 7074fcf5ef2aSThomas Huth 7075fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7076fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7077fcf5ef2aSThomas Huth tcg_temp_free(t0); 7078fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7079fcf5ef2aSThomas Huth } 7080fcf5ef2aSThomas Huth 7081fcf5ef2aSThomas Huth /* tlbwe */ 7082fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7083fcf5ef2aSThomas Huth { 7084fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7085fcf5ef2aSThomas Huth GEN_PRIV; 7086fcf5ef2aSThomas Huth #else 7087fcf5ef2aSThomas Huth CHK_SV; 7088fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7089fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7090fcf5ef2aSThomas Huth } 7091fcf5ef2aSThomas Huth 7092fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7093fcf5ef2aSThomas Huth { 7094fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7095fcf5ef2aSThomas Huth GEN_PRIV; 7096fcf5ef2aSThomas Huth #else 7097fcf5ef2aSThomas Huth TCGv t0; 7098fcf5ef2aSThomas Huth 7099fcf5ef2aSThomas Huth CHK_SV; 7100fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7101fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7102fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7103fcf5ef2aSThomas Huth tcg_temp_free(t0); 7104fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7105fcf5ef2aSThomas Huth } 7106fcf5ef2aSThomas Huth 7107fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7108fcf5ef2aSThomas Huth { 7109fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7110fcf5ef2aSThomas Huth GEN_PRIV; 7111fcf5ef2aSThomas Huth #else 7112fcf5ef2aSThomas Huth TCGv t0; 7113fcf5ef2aSThomas Huth 7114fcf5ef2aSThomas Huth CHK_SV; 7115fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7116fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7117fcf5ef2aSThomas Huth 7118fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7119fcf5ef2aSThomas Huth case 0: 7120fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7121fcf5ef2aSThomas Huth break; 7122fcf5ef2aSThomas Huth case 1: 7123fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7124fcf5ef2aSThomas Huth break; 7125fcf5ef2aSThomas Huth case 3: 7126fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7127fcf5ef2aSThomas Huth break; 7128fcf5ef2aSThomas Huth default: 7129fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7130fcf5ef2aSThomas Huth break; 7131fcf5ef2aSThomas Huth } 7132fcf5ef2aSThomas Huth 7133fcf5ef2aSThomas Huth tcg_temp_free(t0); 7134fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7135fcf5ef2aSThomas Huth } 7136fcf5ef2aSThomas Huth 7137fcf5ef2aSThomas Huth 7138fcf5ef2aSThomas Huth /* wrtee */ 7139fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7140fcf5ef2aSThomas Huth { 7141fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7142fcf5ef2aSThomas Huth GEN_PRIV; 7143fcf5ef2aSThomas Huth #else 7144fcf5ef2aSThomas Huth TCGv t0; 7145fcf5ef2aSThomas Huth 7146fcf5ef2aSThomas Huth CHK_SV; 7147fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7148fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7149fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7150fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7151fcf5ef2aSThomas Huth tcg_temp_free(t0); 7152efe843d8SDavid Gibson /* 7153efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7154efe843d8SDavid Gibson * just set msr_ee to 1 7155fcf5ef2aSThomas Huth */ 7156d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7157fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7158fcf5ef2aSThomas Huth } 7159fcf5ef2aSThomas Huth 7160fcf5ef2aSThomas Huth /* wrteei */ 7161fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7162fcf5ef2aSThomas Huth { 7163fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7164fcf5ef2aSThomas Huth GEN_PRIV; 7165fcf5ef2aSThomas Huth #else 7166fcf5ef2aSThomas Huth CHK_SV; 7167fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7168fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7169fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7170d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7171fcf5ef2aSThomas Huth } else { 7172fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7173fcf5ef2aSThomas Huth } 7174fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7175fcf5ef2aSThomas Huth } 7176fcf5ef2aSThomas Huth 7177fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7178fcf5ef2aSThomas Huth 7179fcf5ef2aSThomas Huth /* dlmzb */ 7180fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7181fcf5ef2aSThomas Huth { 7182fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7183fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7184fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7185fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7186fcf5ef2aSThomas Huth } 7187fcf5ef2aSThomas Huth 7188fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7189fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7190fcf5ef2aSThomas Huth { 7191fcf5ef2aSThomas Huth /* interpreted as no-op */ 7192fcf5ef2aSThomas Huth } 7193fcf5ef2aSThomas Huth 7194fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7195fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7196fcf5ef2aSThomas Huth { 719727a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 719827a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 719927a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 720027a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 720127a3ea7eSBALATON Zoltan } 720227a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7203fcf5ef2aSThomas Huth } 7204fcf5ef2aSThomas Huth 7205fcf5ef2aSThomas Huth /* icbt */ 7206fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7207fcf5ef2aSThomas Huth { 7208efe843d8SDavid Gibson /* 7209efe843d8SDavid Gibson * interpreted as no-op 7210efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7211efe843d8SDavid Gibson * does not generate any exception 7212fcf5ef2aSThomas Huth */ 7213fcf5ef2aSThomas Huth } 7214fcf5ef2aSThomas Huth 7215fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7216fcf5ef2aSThomas Huth 7217fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7218fcf5ef2aSThomas Huth { 7219fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7220fcf5ef2aSThomas Huth GEN_PRIV; 7221fcf5ef2aSThomas Huth #else 7222ebca5e6dSCédric Le Goater CHK_HV; 7223d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 72247af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72257af1e7b0SCédric Le Goater } else { 7226fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72277af1e7b0SCédric Le Goater } 7228fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7229fcf5ef2aSThomas Huth } 7230fcf5ef2aSThomas Huth 7231fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7232fcf5ef2aSThomas Huth { 7233fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7234fcf5ef2aSThomas Huth GEN_PRIV; 7235fcf5ef2aSThomas Huth #else 7236ebca5e6dSCédric Le Goater CHK_HV; 7237d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 72387af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 72397af1e7b0SCédric Le Goater } else { 7240fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 72417af1e7b0SCédric Le Goater } 7242fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7243fcf5ef2aSThomas Huth } 7244fcf5ef2aSThomas Huth 72455ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 72465ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 72475ba7ba1dSCédric Le Goater { 72485ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 72495ba7ba1dSCédric Le Goater GEN_PRIV; 72505ba7ba1dSCédric Le Goater #else 72515ba7ba1dSCédric Le Goater CHK_SV; 72525ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72535ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72545ba7ba1dSCédric Le Goater } 72555ba7ba1dSCédric Le Goater 72565ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 72575ba7ba1dSCédric Le Goater { 72585ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 72595ba7ba1dSCédric Le Goater GEN_PRIV; 72605ba7ba1dSCédric Le Goater #else 72615ba7ba1dSCédric Le Goater CHK_SV; 72625ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72635ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72645ba7ba1dSCédric Le Goater } 72655ba7ba1dSCédric Le Goater #endif 72665ba7ba1dSCédric Le Goater 72677af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 72687af1e7b0SCédric Le Goater { 72697af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 72707af1e7b0SCédric Le Goater GEN_PRIV; 72717af1e7b0SCédric Le Goater #else 72727af1e7b0SCédric Le Goater CHK_HV; 72737af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72747af1e7b0SCédric Le Goater /* interpreted as no-op */ 72757af1e7b0SCédric Le Goater } 7276fcf5ef2aSThomas Huth 7277fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7278fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7279fcf5ef2aSThomas Huth { 7280fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7281fcf5ef2aSThomas Huth 7282fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7283fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7284fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7285fcf5ef2aSThomas Huth } 7286fcf5ef2aSThomas Huth 7287fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7288fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7289fcf5ef2aSThomas Huth { 7290fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7291fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7292fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7293fcf5ef2aSThomas Huth 7294fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7295fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7296fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7297fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7298fcf5ef2aSThomas Huth } else { 7299fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7300fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7301fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7302fcf5ef2aSThomas Huth } 7303fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7304fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7305fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7306fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7307fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7308fcf5ef2aSThomas Huth } 7309fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7310fcf5ef2aSThomas Huth 7311fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7312fcf5ef2aSThomas Huth { 7313fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7314fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7315fcf5ef2aSThomas Huth return; 7316fcf5ef2aSThomas Huth } 7317fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7318fcf5ef2aSThomas Huth } 7319fcf5ef2aSThomas Huth 7320fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7321fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7322fcf5ef2aSThomas Huth { \ 7323fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7324fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7325fcf5ef2aSThomas Huth return; \ 7326fcf5ef2aSThomas Huth } \ 7327efe843d8SDavid Gibson /* \ 7328efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7329fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7330fcf5ef2aSThomas Huth * \ 7331fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7332fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7333fcf5ef2aSThomas Huth */ \ 7334fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7335fcf5ef2aSThomas Huth } 7336fcf5ef2aSThomas Huth 7337fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7338fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7339fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7340fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7341fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7342fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7343fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7344efe843d8SDavid Gibson 7345b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7346b8b4576eSSuraj Jitindar Singh { 7347efe843d8SDavid Gibson /* Do Nothing */ 7348b8b4576eSSuraj Jitindar Singh } 7349fcf5ef2aSThomas Huth 735080b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 735180b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 735280b8c1eeSNikunj A Dadhania { \ 7353efe843d8SDavid Gibson /* \ 7354efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7355efe843d8SDavid Gibson * implementation of the copy paste facility \ 735680b8c1eeSNikunj A Dadhania */ \ 735780b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 735880b8c1eeSNikunj A Dadhania } 735980b8c1eeSNikunj A Dadhania 736080b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 736180b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 736280b8c1eeSNikunj A Dadhania 7363fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7364fcf5ef2aSThomas Huth { 7365fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7366fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7367fcf5ef2aSThomas Huth return; 7368fcf5ef2aSThomas Huth } 7369efe843d8SDavid Gibson /* 7370efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7371efe843d8SDavid Gibson * simple: 7372fcf5ef2aSThomas Huth * 7373fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7374fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7375fcf5ef2aSThomas Huth */ 7376fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7377fcf5ef2aSThomas Huth } 7378fcf5ef2aSThomas Huth 7379fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7380fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7381fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7382fcf5ef2aSThomas Huth { \ 7383fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7384fcf5ef2aSThomas Huth } 7385fcf5ef2aSThomas Huth 7386fcf5ef2aSThomas Huth #else 7387fcf5ef2aSThomas Huth 7388fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7389fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7390fcf5ef2aSThomas Huth { \ 7391fcf5ef2aSThomas Huth CHK_SV; \ 7392fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7393fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7394fcf5ef2aSThomas Huth return; \ 7395fcf5ef2aSThomas Huth } \ 7396efe843d8SDavid Gibson /* \ 7397efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7398fcf5ef2aSThomas Huth * simple: \ 7399fcf5ef2aSThomas Huth * \ 7400fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7401fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7402fcf5ef2aSThomas Huth */ \ 7403fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7404fcf5ef2aSThomas Huth } 7405fcf5ef2aSThomas Huth 7406fcf5ef2aSThomas Huth #endif 7407fcf5ef2aSThomas Huth 7408fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7409fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7410fcf5ef2aSThomas Huth 74111a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 74121a404c91SMark Cave-Ayland { 7413e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 74141a404c91SMark Cave-Ayland } 74151a404c91SMark Cave-Ayland 74161a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 74171a404c91SMark Cave-Ayland { 7418e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 74191a404c91SMark Cave-Ayland } 74201a404c91SMark Cave-Ayland 7421c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7422c4a18dbfSMark Cave-Ayland { 742337da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7424c4a18dbfSMark Cave-Ayland } 7425c4a18dbfSMark Cave-Ayland 7426c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7427c4a18dbfSMark Cave-Ayland { 742837da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7429c4a18dbfSMark Cave-Ayland } 7430c4a18dbfSMark Cave-Ayland 7431c9826ae9SRichard Henderson /* 7432f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 7433f2aabda8SRichard Henderson */ 7434f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 7435f2aabda8SRichard Henderson { 7436f2aabda8SRichard Henderson return x * 4; 7437f2aabda8SRichard Henderson } 7438f2aabda8SRichard Henderson 7439f2aabda8SRichard Henderson /* 7440c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 7441c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 7442c9826ae9SRichard Henderson * proper variable. 7443c9826ae9SRichard Henderson */ 7444c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7445c9826ae9SRichard Henderson do { \ 7446c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7447c9826ae9SRichard Henderson return false; \ 7448c9826ae9SRichard Henderson } \ 7449c9826ae9SRichard Henderson } while (0) 7450c9826ae9SRichard Henderson 7451c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7452c9826ae9SRichard Henderson do { \ 7453c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7454c9826ae9SRichard Henderson return false; \ 7455c9826ae9SRichard Henderson } \ 7456c9826ae9SRichard Henderson } while (0) 7457c9826ae9SRichard Henderson 7458c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7459c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 7460c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 7461c9826ae9SRichard Henderson #else 7462c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7463c9826ae9SRichard Henderson #endif 7464c9826ae9SRichard Henderson 7465f2aabda8SRichard Henderson /* 7466f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 7467f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 7468f2aabda8SRichard Henderson */ 7469f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 7470f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7471f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 7472f2aabda8SRichard Henderson 7473f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 7474f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7475f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 7476f2aabda8SRichard Henderson 7477f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 7478f2aabda8SRichard Henderson 7479f2aabda8SRichard Henderson 748099082815SRichard Henderson #include "decode-insn32.c.inc" 748199082815SRichard Henderson #include "decode-insn64.c.inc" 748299082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 748399082815SRichard Henderson 7484139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7485fcf5ef2aSThomas Huth 7486139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7487fcf5ef2aSThomas Huth 7488139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7489a5f56954SMatheus Ferst #include "translate/vector-impl.c.inc" 7490fcf5ef2aSThomas Huth 7491139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7492fcf5ef2aSThomas Huth 7493139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7494fcf5ef2aSThomas Huth 74955cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 74965cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 74975cb091a4SNikunj A Dadhania { 74985cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 74995cb091a4SNikunj A Dadhania case 0: /* lfdp */ 75005cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 75015cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 75025cb091a4SNikunj A Dadhania } 75035cb091a4SNikunj A Dadhania break; 75045cb091a4SNikunj A Dadhania case 2: /* lxsd */ 75055cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 75065cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 75075cb091a4SNikunj A Dadhania } 75085cb091a4SNikunj A Dadhania break; 75095cb091a4SNikunj A Dadhania case 3: /* lxssp */ 75105cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 75115cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 75125cb091a4SNikunj A Dadhania } 75135cb091a4SNikunj A Dadhania break; 75145cb091a4SNikunj A Dadhania } 75155cb091a4SNikunj A Dadhania return gen_invalid(ctx); 75165cb091a4SNikunj A Dadhania } 75175cb091a4SNikunj A Dadhania 7518d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7519e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7520e3001664SNikunj A Dadhania { 7521e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7522e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7523e3001664SNikunj A Dadhania case 1: /* lxv */ 7524d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7525d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7526d59ba583SNikunj A Dadhania } 7527e3001664SNikunj A Dadhania break; 7528e3001664SNikunj A Dadhania case 5: /* stxv */ 7529d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7530d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7531d59ba583SNikunj A Dadhania } 7532e3001664SNikunj A Dadhania break; 7533e3001664SNikunj A Dadhania } 7534e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7535e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7536e3001664SNikunj A Dadhania case 0: /* stfdp */ 7537e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7538e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7539e3001664SNikunj A Dadhania } 7540e3001664SNikunj A Dadhania break; 7541e3001664SNikunj A Dadhania case 2: /* stxsd */ 7542e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7543e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7544e3001664SNikunj A Dadhania } 7545e3001664SNikunj A Dadhania break; 7546e3001664SNikunj A Dadhania case 3: /* stxssp */ 7547e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7548e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7549e3001664SNikunj A Dadhania } 7550e3001664SNikunj A Dadhania break; 7551e3001664SNikunj A Dadhania } 7552e3001664SNikunj A Dadhania } 7553e3001664SNikunj A Dadhania return gen_invalid(ctx); 7554e3001664SNikunj A Dadhania } 7555e3001664SNikunj A Dadhania 75569d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75579d69cfa2SLijun Pan /* brd */ 75589d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 75599d69cfa2SLijun Pan { 75609d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75619d69cfa2SLijun Pan } 75629d69cfa2SLijun Pan 75639d69cfa2SLijun Pan /* brw */ 75649d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 75659d69cfa2SLijun Pan { 75669d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75679d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 75689d69cfa2SLijun Pan 75699d69cfa2SLijun Pan } 75709d69cfa2SLijun Pan 75719d69cfa2SLijun Pan /* brh */ 75729d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 75739d69cfa2SLijun Pan { 75749d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 75759d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 75769d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 75779d69cfa2SLijun Pan 75789d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 75799d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 75809d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 75819d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 75829d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 75839d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 75849d69cfa2SLijun Pan 75859d69cfa2SLijun Pan tcg_temp_free_i64(t0); 75869d69cfa2SLijun Pan tcg_temp_free_i64(t1); 75879d69cfa2SLijun Pan tcg_temp_free_i64(t2); 75889d69cfa2SLijun Pan } 75899d69cfa2SLijun Pan #endif 75909d69cfa2SLijun Pan 7591fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 75929d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75939d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 75949d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 75959d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 75969d69cfa2SLijun Pan #endif 7597fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7598fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7599fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7600fcf5ef2aSThomas Huth #endif 7601fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7602fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7603fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7604fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7605fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7606fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7607fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7608fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7609fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7610fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7611fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7612fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7613fcf5ef2aSThomas Huth #endif 7614fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7615fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7616fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7617fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7618fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7619fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7620fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 762180b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7622b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 762380b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7624fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7625fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7626fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7627fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7628fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7629fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7630fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7631fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7632fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7633fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7634fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7635fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7636fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7637fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7638fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7639fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7640fcf5ef2aSThomas Huth #endif 7641fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7642fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7643fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7644fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7645fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7646fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7647fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7648fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7649fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7650fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7651fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7652fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7653fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7654fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7655fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7656fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7657fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7658fcf5ef2aSThomas Huth #endif 7659fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7660fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7661fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7662fcf5ef2aSThomas Huth #endif 76635cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 76645cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7665d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7666e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7667fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7668fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7669fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7670fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7671fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7672fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7673c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7674fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7675fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7676fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7677fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7678a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7679a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7680fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7681fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7682fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7683fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7684a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7685a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7686fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7687fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7688fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7689fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7690fcf5ef2aSThomas Huth #endif 7691fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7692fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7693c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7694fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7695fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7696fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7697fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7698fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7699fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7700fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7701fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7702fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 77033c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 77043c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 77053c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 77063c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 77073c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 77083c89b8d6SNicholas Piggin #endif 7709cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7710fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7711fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7712fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7713fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7714fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7715fcf5ef2aSThomas Huth #endif 77163c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 77173c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 77183c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7719fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7720fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7721fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7722fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7723fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7724fcf5ef2aSThomas Huth #endif 7725fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7726fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7727fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7728fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7729fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7730fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7731fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7732fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7733fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7734b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7735fcf5ef2aSThomas Huth #endif 7736fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7737fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7738fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 773950728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7740fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7741fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 774250728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7743fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 774450728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7745fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 774650728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7747fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7748fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 774950728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7750fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 775199d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7752fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7753fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 775450728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7755fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7756fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7757fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7758fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7759fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7760fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7761fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7762fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7763fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7764fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7765fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7766fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7767fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7768fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7769fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7770fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7771fcf5ef2aSThomas Huth #endif 7772fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7773efe843d8SDavid Gibson /* 7774efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7775efe843d8SDavid Gibson * different ISA versions 7776efe843d8SDavid Gibson */ 7777fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7778fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7779c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7780c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7781fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7782fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7783fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7784fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7785a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 778662d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7787fcf5ef2aSThomas Huth #endif 7788fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7789fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7790fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7791fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7792fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7793fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7794fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7795fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7796fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7797fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7798fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7799fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7800fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7801fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7802fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7803fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7804fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7805fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7806fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7807fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7808fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7809fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7810fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7811fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7812fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7813fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7814fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7815fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7816fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7817fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7818fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7819fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7820fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7821fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7822fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7823fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7824fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7825fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7826fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7827fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7828fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7829fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7830fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7831fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7832fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7833fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7834fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7835fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7836fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7837fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7838fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7839fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7840fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7841fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7842fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7843fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7844fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7845fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7846fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7847fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7848fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7849fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7850fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7851fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7852fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7853fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7854fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7855fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7856fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7857fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7858fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7859fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7860fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7861fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7862fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7863fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7864fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7865fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7866fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7867fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7868fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7869fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7870fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7871fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7872fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7873fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7874fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7875fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7876fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7877fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7878fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7879fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7880fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7881fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 78827af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 78837af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7884fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7885fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7886fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7887fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7888fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 788927a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7890fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7891fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 78920c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 78930c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7894fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7895fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7896fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7897fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7898fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7899fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7900fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7901fcf5ef2aSThomas Huth PPC2_ISA300), 7902fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 79035ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 79045ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 79055ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 79065ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 7907fcf5ef2aSThomas Huth #endif 7908fcf5ef2aSThomas Huth 7909fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7910fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7911fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7912fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7913fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7914fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7915fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7916fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7917fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7918fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7919fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7920fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7921fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7922fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7923fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 79244c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7925fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7926fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7927fcf5ef2aSThomas Huth 7928fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7929fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7930fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7931fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7932fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7933fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7934fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7935fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7936fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7937fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7938fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7939fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7940fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7941fcf5ef2aSThomas Huth 7942fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7943fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7944fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7945fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7946fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7947fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7948fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7949fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7950fcf5ef2aSThomas Huth 7951fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7952fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7953fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7954fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7955fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7956fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7957fcf5ef2aSThomas Huth 7958fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7959fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7960fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7961fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7962fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7963fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7964fcf5ef2aSThomas Huth #endif 7965fcf5ef2aSThomas Huth 7966fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7967fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7968fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7969fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7970fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7971fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7972fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7973fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7974fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7975fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7976fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7977fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7978fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7979fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7980fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7981fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7982fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7983fcf5ef2aSThomas Huth 7984fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7985fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7986fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7987fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7988fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7989fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7990fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7991fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7992fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7993fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7994fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7995fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7996fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7997fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7998fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7999fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8000fcf5ef2aSThomas Huth #endif 8001fcf5ef2aSThomas Huth 8002fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8003fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8004fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8005fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8006fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8007fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8008fcf5ef2aSThomas Huth PPC_64B) 8009fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8010fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8011fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8012fcf5ef2aSThomas Huth PPC_64B), \ 8013fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8014fcf5ef2aSThomas Huth PPC_64B), \ 8015fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8016fcf5ef2aSThomas Huth PPC_64B) 8017fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8018fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8019fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8020fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8021fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8022fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8023fcf5ef2aSThomas Huth #endif 8024fcf5ef2aSThomas Huth 8025fcf5ef2aSThomas Huth #undef GEN_LDX_E 8026fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8027fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8028fcf5ef2aSThomas Huth 8029fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8030fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8031fcf5ef2aSThomas Huth 8032fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8033fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8034fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8035fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8036fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8037fcf5ef2aSThomas Huth #endif 8038fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8039fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8040fcf5ef2aSThomas Huth 804150728199SRoman Kapl /* External PID based load */ 804250728199SRoman Kapl #undef GEN_LDEPX 804350728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 804450728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 804550728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 804650728199SRoman Kapl 804750728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 804850728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 804950728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 805050728199SRoman Kapl #if defined(TARGET_PPC64) 805150728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 805250728199SRoman Kapl #endif 805350728199SRoman Kapl 8054fcf5ef2aSThomas Huth #undef GEN_STX_E 8055fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 80560123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8057fcf5ef2aSThomas Huth 8058fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8059fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8060fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8061fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8062fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8063fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8064fcf5ef2aSThomas Huth #endif 8065fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8066fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8067fcf5ef2aSThomas Huth 806850728199SRoman Kapl #undef GEN_STEPX 806950728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 807050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 807150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 807250728199SRoman Kapl 807350728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 807450728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 807550728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 807650728199SRoman Kapl #if defined(TARGET_PPC64) 807750728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 807850728199SRoman Kapl #endif 807950728199SRoman Kapl 8080fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8081fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8082fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8083fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8084fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8085fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8086fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8087fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8088fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8089fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8090fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8091fcf5ef2aSThomas Huth 8092fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8093fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8094fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8096fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8104fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8106fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8108fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8110fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8112fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8114fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8116fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8118fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8120fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8122fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8124fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8126fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8128fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8130fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8132fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8134fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8136fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8137fcf5ef2aSThomas Huth 8138fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8139fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8140fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8141fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8142fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8143fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8144fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8145fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8146fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8147fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8148fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8149fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8150fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8151fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8152fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8153fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8154fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8155fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8156fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8157fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8158fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8159fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8160fcf5ef2aSThomas Huth 8161139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8162fcf5ef2aSThomas Huth 8163139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8164fcf5ef2aSThomas Huth 8165139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8166fcf5ef2aSThomas Huth 8167139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8168fcf5ef2aSThomas Huth 8169139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8170fcf5ef2aSThomas Huth }; 8171fcf5ef2aSThomas Huth 81727468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 81737468e2c8SBruno Larsen (billionai) /* Opcode types */ 81747468e2c8SBruno Larsen (billionai) enum { 81757468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 81767468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 81777468e2c8SBruno Larsen (billionai) }; 81787468e2c8SBruno Larsen (billionai) 81797468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 81807468e2c8SBruno Larsen (billionai) 81817468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 81827468e2c8SBruno Larsen (billionai) { 81837468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 81847468e2c8SBruno Larsen (billionai) } 81857468e2c8SBruno Larsen (billionai) 81867468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 81877468e2c8SBruno Larsen (billionai) { 81887468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 81897468e2c8SBruno Larsen (billionai) } 81907468e2c8SBruno Larsen (billionai) 81917468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 81927468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 81937468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 81947468e2c8SBruno Larsen (billionai) { 81957468e2c8SBruno Larsen (billionai) int i; 81967468e2c8SBruno Larsen (billionai) 81977468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 81987468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 81997468e2c8SBruno Larsen (billionai) } 82007468e2c8SBruno Larsen (billionai) } 82017468e2c8SBruno Larsen (billionai) 82027468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 82037468e2c8SBruno Larsen (billionai) { 82047468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 82057468e2c8SBruno Larsen (billionai) 82067468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 82077468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 82087468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 82097468e2c8SBruno Larsen (billionai) 82107468e2c8SBruno Larsen (billionai) return 0; 82117468e2c8SBruno Larsen (billionai) } 82127468e2c8SBruno Larsen (billionai) 82137468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 82147468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82157468e2c8SBruno Larsen (billionai) { 82167468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 82177468e2c8SBruno Larsen (billionai) return -1; 82187468e2c8SBruno Larsen (billionai) } 82197468e2c8SBruno Larsen (billionai) table[idx] = handler; 82207468e2c8SBruno Larsen (billionai) 82217468e2c8SBruno Larsen (billionai) return 0; 82227468e2c8SBruno Larsen (billionai) } 82237468e2c8SBruno Larsen (billionai) 82247468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 82257468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 82267468e2c8SBruno Larsen (billionai) { 82277468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 82287468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 82297468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 82307468e2c8SBruno Larsen (billionai) return -1; 82317468e2c8SBruno Larsen (billionai) } 82327468e2c8SBruno Larsen (billionai) 82337468e2c8SBruno Larsen (billionai) return 0; 82347468e2c8SBruno Larsen (billionai) } 82357468e2c8SBruno Larsen (billionai) 82367468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 82377468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82387468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82397468e2c8SBruno Larsen (billionai) { 82407468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 82417468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 82427468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 82437468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 82447468e2c8SBruno Larsen (billionai) return -1; 82457468e2c8SBruno Larsen (billionai) } 82467468e2c8SBruno Larsen (billionai) } else { 82477468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 82487468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 82497468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 82507468e2c8SBruno Larsen (billionai) return -1; 82517468e2c8SBruno Larsen (billionai) } 82527468e2c8SBruno Larsen (billionai) } 82537468e2c8SBruno Larsen (billionai) if (handler != NULL && 82547468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 82557468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 82567468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 82577468e2c8SBruno Larsen (billionai) return -1; 82587468e2c8SBruno Larsen (billionai) } 82597468e2c8SBruno Larsen (billionai) 82607468e2c8SBruno Larsen (billionai) return 0; 82617468e2c8SBruno Larsen (billionai) } 82627468e2c8SBruno Larsen (billionai) 82637468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 82647468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82657468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82667468e2c8SBruno Larsen (billionai) { 82677468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 82687468e2c8SBruno Larsen (billionai) } 82697468e2c8SBruno Larsen (billionai) 82707468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 82717468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82727468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 82737468e2c8SBruno Larsen (billionai) { 82747468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82757468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82767468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82777468e2c8SBruno Larsen (billionai) return -1; 82787468e2c8SBruno Larsen (billionai) } 82797468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 82807468e2c8SBruno Larsen (billionai) handler) < 0) { 82817468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 82827468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 82837468e2c8SBruno Larsen (billionai) return -1; 82847468e2c8SBruno Larsen (billionai) } 82857468e2c8SBruno Larsen (billionai) 82867468e2c8SBruno Larsen (billionai) return 0; 82877468e2c8SBruno Larsen (billionai) } 82887468e2c8SBruno Larsen (billionai) 82897468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 82907468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82917468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 82927468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82937468e2c8SBruno Larsen (billionai) { 82947468e2c8SBruno Larsen (billionai) opc_handler_t **table; 82957468e2c8SBruno Larsen (billionai) 82967468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82977468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82987468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82997468e2c8SBruno Larsen (billionai) return -1; 83007468e2c8SBruno Larsen (billionai) } 83017468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 83027468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 83037468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 83047468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 83057468e2c8SBruno Larsen (billionai) return -1; 83067468e2c8SBruno Larsen (billionai) } 83077468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 83087468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 83097468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 83107468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 83117468e2c8SBruno Larsen (billionai) return -1; 83127468e2c8SBruno Larsen (billionai) } 83137468e2c8SBruno Larsen (billionai) return 0; 83147468e2c8SBruno Larsen (billionai) } 83157468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 83167468e2c8SBruno Larsen (billionai) { 83177468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 83187468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 83197468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 83207468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 83217468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 83227468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 83237468e2c8SBruno Larsen (billionai) return -1; 83247468e2c8SBruno Larsen (billionai) } 83257468e2c8SBruno Larsen (billionai) } else { 83267468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 83277468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 83287468e2c8SBruno Larsen (billionai) return -1; 83297468e2c8SBruno Larsen (billionai) } 83307468e2c8SBruno Larsen (billionai) } 83317468e2c8SBruno Larsen (billionai) } else { 83327468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 83337468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 83347468e2c8SBruno Larsen (billionai) return -1; 83357468e2c8SBruno Larsen (billionai) } 83367468e2c8SBruno Larsen (billionai) } 83377468e2c8SBruno Larsen (billionai) } else { 83387468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 83397468e2c8SBruno Larsen (billionai) return -1; 83407468e2c8SBruno Larsen (billionai) } 83417468e2c8SBruno Larsen (billionai) } 83427468e2c8SBruno Larsen (billionai) 83437468e2c8SBruno Larsen (billionai) return 0; 83447468e2c8SBruno Larsen (billionai) } 83457468e2c8SBruno Larsen (billionai) 83467468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 83477468e2c8SBruno Larsen (billionai) { 83487468e2c8SBruno Larsen (billionai) int i, count, tmp; 83497468e2c8SBruno Larsen (billionai) 83507468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 83517468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 83527468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 83537468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83547468e2c8SBruno Larsen (billionai) } 83557468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 83567468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 83577468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 83587468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 83597468e2c8SBruno Larsen (billionai) if (tmp == 0) { 83607468e2c8SBruno Larsen (billionai) free(table[i]); 83617468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83627468e2c8SBruno Larsen (billionai) } else { 83637468e2c8SBruno Larsen (billionai) count++; 83647468e2c8SBruno Larsen (billionai) } 83657468e2c8SBruno Larsen (billionai) } else { 83667468e2c8SBruno Larsen (billionai) count++; 83677468e2c8SBruno Larsen (billionai) } 83687468e2c8SBruno Larsen (billionai) } 83697468e2c8SBruno Larsen (billionai) } 83707468e2c8SBruno Larsen (billionai) 83717468e2c8SBruno Larsen (billionai) return count; 83727468e2c8SBruno Larsen (billionai) } 83737468e2c8SBruno Larsen (billionai) 83747468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 83757468e2c8SBruno Larsen (billionai) { 83767468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 83777468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 83787468e2c8SBruno Larsen (billionai) } 83797468e2c8SBruno Larsen (billionai) } 83807468e2c8SBruno Larsen (billionai) 83817468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 83827468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 83837468e2c8SBruno Larsen (billionai) { 83847468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 83857468e2c8SBruno Larsen (billionai) opcode_t *opc; 83867468e2c8SBruno Larsen (billionai) 83877468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 83887468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 83897468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 83907468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 83917468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 83927468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 83937468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 83947468e2c8SBruno Larsen (billionai) opc->opc3); 83957468e2c8SBruno Larsen (billionai) return; 83967468e2c8SBruno Larsen (billionai) } 83977468e2c8SBruno Larsen (billionai) } 83987468e2c8SBruno Larsen (billionai) } 83997468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 84007468e2c8SBruno Larsen (billionai) fflush(stdout); 84017468e2c8SBruno Larsen (billionai) fflush(stderr); 84027468e2c8SBruno Larsen (billionai) } 84037468e2c8SBruno Larsen (billionai) 84047468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 84057468e2c8SBruno Larsen (billionai) { 84067468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 84077468e2c8SBruno Larsen (billionai) int i, j, k; 84087468e2c8SBruno Larsen (billionai) 84097468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 84107468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 84117468e2c8SBruno Larsen (billionai) continue; 84127468e2c8SBruno Larsen (billionai) } 84137468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 84147468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 84157468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 84167468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 84177468e2c8SBruno Larsen (billionai) continue; 84187468e2c8SBruno Larsen (billionai) } 84197468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 84207468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 84217468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 84227468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 84237468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 84247468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 84257468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84267468e2c8SBruno Larsen (billionai) } 84277468e2c8SBruno Larsen (billionai) } 84287468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 84297468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84307468e2c8SBruno Larsen (billionai) } 84317468e2c8SBruno Larsen (billionai) } 84327468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 84337468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84347468e2c8SBruno Larsen (billionai) } 84357468e2c8SBruno Larsen (billionai) } 84367468e2c8SBruno Larsen (billionai) } 84377468e2c8SBruno Larsen (billionai) 84387468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 84397468e2c8SBruno Larsen (billionai) { 84407468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 84417468e2c8SBruno Larsen (billionai) 84427468e2c8SBruno Larsen (billionai) /* 84437468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 84447468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 84457468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 84467468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 84477468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 84487468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 84497468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 84507468e2c8SBruno Larsen (billionai) */ 84517468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 84527468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 84537468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 84547468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 84557468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 84567468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 84577468e2c8SBruno Larsen (billionai) } 84587468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 84597468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 84607468e2c8SBruno Larsen (billionai) return 0; 84617468e2c8SBruno Larsen (billionai) } 84627468e2c8SBruno Larsen (billionai) 8463624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8464624cb07fSRichard Henderson { 8465624cb07fSRichard Henderson opc_handler_t **table, *handler; 8466624cb07fSRichard Henderson uint32_t inval; 8467624cb07fSRichard Henderson 8468624cb07fSRichard Henderson ctx->opcode = insn; 8469624cb07fSRichard Henderson 8470624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8471624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8472624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8473624cb07fSRichard Henderson 8474624cb07fSRichard Henderson table = cpu->opcodes; 8475624cb07fSRichard Henderson handler = table[opc1(insn)]; 8476624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8477624cb07fSRichard Henderson table = ind_table(handler); 8478624cb07fSRichard Henderson handler = table[opc2(insn)]; 8479624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8480624cb07fSRichard Henderson table = ind_table(handler); 8481624cb07fSRichard Henderson handler = table[opc3(insn)]; 8482624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8483624cb07fSRichard Henderson table = ind_table(handler); 8484624cb07fSRichard Henderson handler = table[opc4(insn)]; 8485624cb07fSRichard Henderson } 8486624cb07fSRichard Henderson } 8487624cb07fSRichard Henderson } 8488624cb07fSRichard Henderson 8489624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8490624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8491624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8492624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8493624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8494624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8495624cb07fSRichard Henderson insn, ctx->cia); 8496624cb07fSRichard Henderson return false; 8497624cb07fSRichard Henderson } 8498624cb07fSRichard Henderson 8499624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8500624cb07fSRichard Henderson && Rc(insn))) { 8501624cb07fSRichard Henderson inval = handler->inval2; 8502624cb07fSRichard Henderson } else { 8503624cb07fSRichard Henderson inval = handler->inval1; 8504624cb07fSRichard Henderson } 8505624cb07fSRichard Henderson 8506624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8507624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8508624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8509624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8510624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8511624cb07fSRichard Henderson insn, ctx->cia); 8512624cb07fSRichard Henderson return false; 8513624cb07fSRichard Henderson } 8514624cb07fSRichard Henderson 8515624cb07fSRichard Henderson handler->handler(ctx); 8516624cb07fSRichard Henderson return true; 8517624cb07fSRichard Henderson } 8518624cb07fSRichard Henderson 8519b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8520fcf5ef2aSThomas Huth { 8521b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 85229c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 85232df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8524fcf5ef2aSThomas Huth 8525b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 85262df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8527d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 85282df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 85292df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 8530b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 8531b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 8532b0c2d521SEmilio G. Cota ctx->access_type = -1; 8533d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 85342df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8535b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 85360e3bf489SRoman Kapl ctx->flags = env->flags; 8537fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 85382df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8539b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8540fcf5ef2aSThomas Huth #endif 8541e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8542e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 8543d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 8544fcf5ef2aSThomas Huth 85452df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 85462df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 85472df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 85482df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 85492df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8550f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 85512df4fe7aSRichard Henderson 8552b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 85532df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 85542df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 8555efe843d8SDavid Gibson } 85562df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 8557b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8558efe843d8SDavid Gibson } 8559b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 8560b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 8561fcf5ef2aSThomas Huth } 8562b0c2d521SEmilio G. Cota 856313b45575SRichard Henderson if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) { 856413b45575SRichard Henderson ctx->base.max_insns = 1; 8565fcf5ef2aSThomas Huth } 856613b45575SRichard Henderson } 8567fcf5ef2aSThomas Huth 8568b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8569b0c2d521SEmilio G. Cota { 8570b0c2d521SEmilio G. Cota } 8571fcf5ef2aSThomas Huth 8572b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8573b0c2d521SEmilio G. Cota { 8574b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 8575b0c2d521SEmilio G. Cota } 8576b0c2d521SEmilio G. Cota 8577b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 8578b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 8579b0c2d521SEmilio G. Cota { 8580b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8581b0c2d521SEmilio G. Cota 85822736fc61SRichard Henderson gen_update_nip(ctx, ctx->base.pc_next); 8583b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 8584efe843d8SDavid Gibson /* 8585efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 8586efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 8587efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 8588efe843d8SDavid Gibson * setting tb->size below does the right thing. 8589efe843d8SDavid Gibson */ 8590b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 8591b0c2d521SEmilio G. Cota return true; 8592fcf5ef2aSThomas Huth } 8593fcf5ef2aSThomas Huth 859499082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 859599082815SRichard Henderson { 859699082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 859799082815SRichard Henderson return opc1(insn) == 1; 859899082815SRichard Henderson } 859999082815SRichard Henderson 8600b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8601b0c2d521SEmilio G. Cota { 8602b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 860328876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 8604b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 860599082815SRichard Henderson target_ulong pc; 8606624cb07fSRichard Henderson uint32_t insn; 8607624cb07fSRichard Henderson bool ok; 8608b0c2d521SEmilio G. Cota 8609fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 8610fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8611b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8612b0c2d521SEmilio G. Cota 861399082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 861499082815SRichard Henderson insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); 861599082815SRichard Henderson ctx->base.pc_next = pc += 4; 8616fcf5ef2aSThomas Huth 861799082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 861899082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 861999082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 862099082815SRichard Henderson } else if ((pc & 63) == 0) { 862199082815SRichard Henderson /* 862299082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 862399082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 862499082815SRichard Henderson * 64-byte address boundary (system alignment error). 862599082815SRichard Henderson */ 862699082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 862799082815SRichard Henderson ok = true; 862899082815SRichard Henderson } else { 862999082815SRichard Henderson uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); 863099082815SRichard Henderson ctx->base.pc_next = pc += 4; 863199082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 863299082815SRichard Henderson } 8633624cb07fSRichard Henderson if (!ok) { 8634624cb07fSRichard Henderson gen_invalid(ctx); 8635fcf5ef2aSThomas Huth } 8636624cb07fSRichard Henderson 863764a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 863899082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 863964a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 864064a0f644SRichard Henderson } 864164a0f644SRichard Henderson 864251eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 8643fcf5ef2aSThomas Huth } 8644b0c2d521SEmilio G. Cota 8645b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8646b0c2d521SEmilio G. Cota { 8647b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8648a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 8649a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 865013b45575SRichard Henderson int sse; 8651b0c2d521SEmilio G. Cota 8652a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 8653a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 86543d8a5b69SRichard Henderson return; 86553d8a5b69SRichard Henderson } 86563d8a5b69SRichard Henderson 8657a9b5b3d0SRichard Henderson /* Honor single stepping. */ 865813b45575SRichard Henderson sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP); 865913b45575SRichard Henderson if (unlikely(sse)) { 8660a9b5b3d0SRichard Henderson switch (is_jmp) { 8661a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8662a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8663a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8664a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8665a9b5b3d0SRichard Henderson break; 8666a9b5b3d0SRichard Henderson case DISAS_EXIT: 8667a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8668a9b5b3d0SRichard Henderson break; 8669a9b5b3d0SRichard Henderson default: 8670a9b5b3d0SRichard Henderson g_assert_not_reached(); 8671fcf5ef2aSThomas Huth } 867213b45575SRichard Henderson 867313b45575SRichard Henderson if (sse & GDBSTUB_SINGLE_STEP) { 8674a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 8675a9b5b3d0SRichard Henderson return; 8676a9b5b3d0SRichard Henderson } 867713b45575SRichard Henderson /* else CPU_SINGLE_STEP... */ 867813b45575SRichard Henderson if (nip <= 0x100 || nip > 0xf00) { 8679eba3c766SLuis Pires gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 868013b45575SRichard Henderson return; 868113b45575SRichard Henderson } 868213b45575SRichard Henderson } 8683a9b5b3d0SRichard Henderson 8684a9b5b3d0SRichard Henderson switch (is_jmp) { 8685a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8686a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 8687a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 8688a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8689a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 8690a9b5b3d0SRichard Henderson break; 8691a9b5b3d0SRichard Henderson } 8692a9b5b3d0SRichard Henderson /* fall through */ 8693a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8694a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8695a9b5b3d0SRichard Henderson /* fall through */ 8696a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8697a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 8698a9b5b3d0SRichard Henderson break; 8699a9b5b3d0SRichard Henderson 8700a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8701a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8702a9b5b3d0SRichard Henderson /* fall through */ 8703a9b5b3d0SRichard Henderson case DISAS_EXIT: 870407ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8705a9b5b3d0SRichard Henderson break; 8706a9b5b3d0SRichard Henderson 8707a9b5b3d0SRichard Henderson default: 8708a9b5b3d0SRichard Henderson g_assert_not_reached(); 8709fcf5ef2aSThomas Huth } 8710fcf5ef2aSThomas Huth } 8711b0c2d521SEmilio G. Cota 8712b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8713b0c2d521SEmilio G. Cota { 8714b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8715b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8716b0c2d521SEmilio G. Cota } 8717b0c2d521SEmilio G. Cota 8718b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8719b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8720b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8721b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8722b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 8723b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8724b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8725b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8726b0c2d521SEmilio G. Cota }; 8727b0c2d521SEmilio G. Cota 87288b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8729b0c2d521SEmilio G. Cota { 8730b0c2d521SEmilio G. Cota DisasContext ctx; 8731b0c2d521SEmilio G. Cota 87328b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8733fcf5ef2aSThomas Huth } 8734fcf5ef2aSThomas Huth 8735fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8736fcf5ef2aSThomas Huth target_ulong *data) 8737fcf5ef2aSThomas Huth { 8738fcf5ef2aSThomas Huth env->nip = data[0]; 8739fcf5ef2aSThomas Huth } 8740