1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26fcf5ef2aSThomas Huth #include "tcg-op.h" 27fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #include "trace-tcg.h" 34b6bac4bcSEmilio G. Cota #include "exec/translator.h" 35fcf5ef2aSThomas Huth #include "exec/log.h" 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth 38fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 39fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 40fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 41fcf5ef2aSThomas Huth 42fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 43fcf5ef2aSThomas Huth //#define PPC_DEBUG_DISAS 44fcf5ef2aSThomas Huth //#define DO_PPC_STATISTICS 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 47fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 48fcf5ef2aSThomas Huth #else 49fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 50fcf5ef2aSThomas Huth #endif 51fcf5ef2aSThomas Huth /*****************************************************************************/ 52fcf5ef2aSThomas Huth /* Code translation helpers */ 53fcf5ef2aSThomas Huth 54fcf5ef2aSThomas Huth /* global register indexes */ 55fcf5ef2aSThomas Huth static char cpu_reg_names[10*3 + 22*4 /* GPR */ 56fcf5ef2aSThomas Huth + 10*4 + 22*5 /* SPE GPRh */ 57fcf5ef2aSThomas Huth + 10*4 + 22*5 /* FPR */ 58fcf5ef2aSThomas Huth + 2*(10*6 + 22*7) /* AVRh, AVRl */ 59fcf5ef2aSThomas Huth + 10*5 + 22*6 /* VSR */ 60fcf5ef2aSThomas Huth + 8*5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[32]; 64fcf5ef2aSThomas Huth static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 65fcf5ef2aSThomas Huth static TCGv_i64 cpu_vsr[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char* p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "fp%d", i); 112fcf5ef2aSThomas Huth cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpr[i]), p); 114fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 115fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dH", i); 118fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 119fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 120fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 121fcf5ef2aSThomas Huth #else 122fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 126fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dL", i); 129fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 130fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 132fcf5ef2aSThomas Huth #else 133fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 135fcf5ef2aSThomas Huth #endif 136fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 137fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 138fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "vsr%d", i); 139fcf5ef2aSThomas Huth cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, vsr[i]), p); 141fcf5ef2aSThomas Huth p += (i < 10) ? 5 : 6; 142fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 5 : 6; 143fcf5ef2aSThomas Huth } 144fcf5ef2aSThomas Huth 145fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 146fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 147fcf5ef2aSThomas Huth 148fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 149fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 152fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 155fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 158fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 159fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 160fcf5ef2aSThomas Huth #endif 161fcf5ef2aSThomas Huth 162fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 163fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 164fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 165fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 166fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 167fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 168fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 169fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 170dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 171dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 172dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 173dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 174fcf5ef2aSThomas Huth 175fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 176fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 177fcf5ef2aSThomas Huth "reserve_addr"); 178253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 179253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 180253ce7b2SNikunj A Dadhania "reserve_val"); 181fcf5ef2aSThomas Huth 182fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 183fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 184fcf5ef2aSThomas Huth 185fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 186fcf5ef2aSThomas Huth offsetof(CPUPPCState, access_type), "access_type"); 187fcf5ef2aSThomas Huth } 188fcf5ef2aSThomas Huth 189fcf5ef2aSThomas Huth /* internal defines */ 190fcf5ef2aSThomas Huth struct DisasContext { 191b6bac4bcSEmilio G. Cota DisasContextBase base; 192fcf5ef2aSThomas Huth uint32_t opcode; 193fcf5ef2aSThomas Huth uint32_t exception; 194fcf5ef2aSThomas Huth /* Routine used to access memory */ 195fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 196fcf5ef2aSThomas Huth bool lazy_tlb_flush; 197fcf5ef2aSThomas Huth bool need_access_type; 198fcf5ef2aSThomas Huth int mem_idx; 199fcf5ef2aSThomas Huth int access_type; 200fcf5ef2aSThomas Huth /* Translation flags */ 201fcf5ef2aSThomas Huth TCGMemOp default_tcg_memop_mask; 202fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 203fcf5ef2aSThomas Huth bool sf_mode; 204fcf5ef2aSThomas Huth bool has_cfar; 205fcf5ef2aSThomas Huth #endif 206fcf5ef2aSThomas Huth bool fpu_enabled; 207fcf5ef2aSThomas Huth bool altivec_enabled; 208fcf5ef2aSThomas Huth bool vsx_enabled; 209fcf5ef2aSThomas Huth bool spe_enabled; 210fcf5ef2aSThomas Huth bool tm_enabled; 211c6fd28fdSSuraj Jitindar Singh bool gtse; 212fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 213fcf5ef2aSThomas Huth int singlestep_enabled; 214fcf5ef2aSThomas Huth uint64_t insns_flags; 215fcf5ef2aSThomas Huth uint64_t insns_flags2; 216fcf5ef2aSThomas Huth }; 217fcf5ef2aSThomas Huth 218fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 219fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 220fcf5ef2aSThomas Huth { 221fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 222fcf5ef2aSThomas Huth return ctx->le_mode; 223fcf5ef2aSThomas Huth #else 224fcf5ef2aSThomas Huth return !ctx->le_mode; 225fcf5ef2aSThomas Huth #endif 226fcf5ef2aSThomas Huth } 227fcf5ef2aSThomas Huth 228fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 229fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 230fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 231fcf5ef2aSThomas Huth #else 232fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 233fcf5ef2aSThomas Huth #endif 234fcf5ef2aSThomas Huth 235fcf5ef2aSThomas Huth struct opc_handler_t { 236fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 237fcf5ef2aSThomas Huth uint32_t inval1; 238fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 239fcf5ef2aSThomas Huth uint32_t inval2; 240fcf5ef2aSThomas Huth /* instruction type */ 241fcf5ef2aSThomas Huth uint64_t type; 242fcf5ef2aSThomas Huth /* extended instruction type */ 243fcf5ef2aSThomas Huth uint64_t type2; 244fcf5ef2aSThomas Huth /* handler */ 245fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 246fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 247fcf5ef2aSThomas Huth const char *oname; 248fcf5ef2aSThomas Huth #endif 249fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 250fcf5ef2aSThomas Huth uint64_t count; 251fcf5ef2aSThomas Huth #endif 252fcf5ef2aSThomas Huth }; 253fcf5ef2aSThomas Huth 254fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 255fcf5ef2aSThomas Huth { 256fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 257fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 258fcf5ef2aSThomas Huth ctx->access_type = access_type; 259fcf5ef2aSThomas Huth } 260fcf5ef2aSThomas Huth } 261fcf5ef2aSThomas Huth 262fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 263fcf5ef2aSThomas Huth { 264fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 265fcf5ef2aSThomas Huth nip = (uint32_t)nip; 266fcf5ef2aSThomas Huth } 267fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 268fcf5ef2aSThomas Huth } 269fcf5ef2aSThomas Huth 270fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 271fcf5ef2aSThomas Huth { 272fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 273fcf5ef2aSThomas Huth 274fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 275fcf5ef2aSThomas Huth * the faulting instruction 276fcf5ef2aSThomas Huth */ 277fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 278b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 279fcf5ef2aSThomas Huth } 280fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 281fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 282fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 283fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 284fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 285fcf5ef2aSThomas Huth ctx->exception = (excp); 286fcf5ef2aSThomas Huth } 287fcf5ef2aSThomas Huth 288fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 289fcf5ef2aSThomas Huth { 290fcf5ef2aSThomas Huth TCGv_i32 t0; 291fcf5ef2aSThomas Huth 292fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 293fcf5ef2aSThomas Huth * the faulting instruction 294fcf5ef2aSThomas Huth */ 295fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 296b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 297fcf5ef2aSThomas Huth } 298fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 299fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 300fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 301fcf5ef2aSThomas Huth ctx->exception = (excp); 302fcf5ef2aSThomas Huth } 303fcf5ef2aSThomas Huth 304fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 305fcf5ef2aSThomas Huth target_ulong nip) 306fcf5ef2aSThomas Huth { 307fcf5ef2aSThomas Huth TCGv_i32 t0; 308fcf5ef2aSThomas Huth 309fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 310fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 311fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 312fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 313fcf5ef2aSThomas Huth ctx->exception = (excp); 314fcf5ef2aSThomas Huth } 315fcf5ef2aSThomas Huth 316fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 317fcf5ef2aSThomas Huth { 318fcf5ef2aSThomas Huth TCGv_i32 t0; 319fcf5ef2aSThomas Huth 320fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 321fcf5ef2aSThomas Huth * the faulting instruction 322fcf5ef2aSThomas Huth */ 323fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 324fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 325b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 326fcf5ef2aSThomas Huth } 327fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 328fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 329fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 330fcf5ef2aSThomas Huth } 331fcf5ef2aSThomas Huth 332fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 333fcf5ef2aSThomas Huth { 334fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 335fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 336fcf5ef2aSThomas Huth } 337fcf5ef2aSThomas Huth 338fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 339fcf5ef2aSThomas Huth { 340fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 341fcf5ef2aSThomas Huth } 342fcf5ef2aSThomas Huth 343fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 344fcf5ef2aSThomas Huth { 345fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 346fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 347fcf5ef2aSThomas Huth } 348fcf5ef2aSThomas Huth 349fcf5ef2aSThomas Huth /* Stop translation */ 350fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 351fcf5ef2aSThomas Huth { 352b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 353fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 354fcf5ef2aSThomas Huth } 355fcf5ef2aSThomas Huth 356fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 357fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 358fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 359fcf5ef2aSThomas Huth { 360fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 361fcf5ef2aSThomas Huth } 362fcf5ef2aSThomas Huth #endif 363fcf5ef2aSThomas Huth 364fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 365fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 366fcf5ef2aSThomas Huth 367fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 368fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 369fcf5ef2aSThomas Huth 370fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 371fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 372fcf5ef2aSThomas Huth 373fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 374fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 375fcf5ef2aSThomas Huth 376fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 377fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 378fcf5ef2aSThomas Huth 379fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 380fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 381fcf5ef2aSThomas Huth 382fcf5ef2aSThomas Huth typedef struct opcode_t { 383fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 384fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 385fcf5ef2aSThomas Huth unsigned char pad[4]; 386fcf5ef2aSThomas Huth #endif 387fcf5ef2aSThomas Huth opc_handler_t handler; 388fcf5ef2aSThomas Huth const char *oname; 389fcf5ef2aSThomas Huth } opcode_t; 390fcf5ef2aSThomas Huth 391fcf5ef2aSThomas Huth /* Helpers for priv. check */ 392fcf5ef2aSThomas Huth #define GEN_PRIV \ 393fcf5ef2aSThomas Huth do { \ 394fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 395fcf5ef2aSThomas Huth } while (0) 396fcf5ef2aSThomas Huth 397fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 398fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 399fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 400fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 401fcf5ef2aSThomas Huth #else 402fcf5ef2aSThomas Huth #define CHK_HV \ 403fcf5ef2aSThomas Huth do { \ 404fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 405fcf5ef2aSThomas Huth GEN_PRIV; \ 406fcf5ef2aSThomas Huth } \ 407fcf5ef2aSThomas Huth } while (0) 408fcf5ef2aSThomas Huth #define CHK_SV \ 409fcf5ef2aSThomas Huth do { \ 410fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 411fcf5ef2aSThomas Huth GEN_PRIV; \ 412fcf5ef2aSThomas Huth } \ 413fcf5ef2aSThomas Huth } while (0) 414fcf5ef2aSThomas Huth #define CHK_HVRM \ 415fcf5ef2aSThomas Huth do { \ 416fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 417fcf5ef2aSThomas Huth GEN_PRIV; \ 418fcf5ef2aSThomas Huth } \ 419fcf5ef2aSThomas Huth } while (0) 420fcf5ef2aSThomas Huth #endif 421fcf5ef2aSThomas Huth 422fcf5ef2aSThomas Huth #define CHK_NONE 423fcf5ef2aSThomas Huth 424fcf5ef2aSThomas Huth /*****************************************************************************/ 425fcf5ef2aSThomas Huth /* PowerPC instructions table */ 426fcf5ef2aSThomas Huth 427fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 428fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 429fcf5ef2aSThomas Huth { \ 430fcf5ef2aSThomas Huth .opc1 = op1, \ 431fcf5ef2aSThomas Huth .opc2 = op2, \ 432fcf5ef2aSThomas Huth .opc3 = op3, \ 433fcf5ef2aSThomas Huth .opc4 = 0xff, \ 434fcf5ef2aSThomas Huth .handler = { \ 435fcf5ef2aSThomas Huth .inval1 = invl, \ 436fcf5ef2aSThomas Huth .type = _typ, \ 437fcf5ef2aSThomas Huth .type2 = _typ2, \ 438fcf5ef2aSThomas Huth .handler = &gen_##name, \ 439fcf5ef2aSThomas Huth .oname = stringify(name), \ 440fcf5ef2aSThomas Huth }, \ 441fcf5ef2aSThomas Huth .oname = stringify(name), \ 442fcf5ef2aSThomas Huth } 443fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 444fcf5ef2aSThomas Huth { \ 445fcf5ef2aSThomas Huth .opc1 = op1, \ 446fcf5ef2aSThomas Huth .opc2 = op2, \ 447fcf5ef2aSThomas Huth .opc3 = op3, \ 448fcf5ef2aSThomas Huth .opc4 = 0xff, \ 449fcf5ef2aSThomas Huth .handler = { \ 450fcf5ef2aSThomas Huth .inval1 = invl1, \ 451fcf5ef2aSThomas Huth .inval2 = invl2, \ 452fcf5ef2aSThomas Huth .type = _typ, \ 453fcf5ef2aSThomas Huth .type2 = _typ2, \ 454fcf5ef2aSThomas Huth .handler = &gen_##name, \ 455fcf5ef2aSThomas Huth .oname = stringify(name), \ 456fcf5ef2aSThomas Huth }, \ 457fcf5ef2aSThomas Huth .oname = stringify(name), \ 458fcf5ef2aSThomas Huth } 459fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 460fcf5ef2aSThomas Huth { \ 461fcf5ef2aSThomas Huth .opc1 = op1, \ 462fcf5ef2aSThomas Huth .opc2 = op2, \ 463fcf5ef2aSThomas Huth .opc3 = op3, \ 464fcf5ef2aSThomas Huth .opc4 = 0xff, \ 465fcf5ef2aSThomas Huth .handler = { \ 466fcf5ef2aSThomas Huth .inval1 = invl, \ 467fcf5ef2aSThomas Huth .type = _typ, \ 468fcf5ef2aSThomas Huth .type2 = _typ2, \ 469fcf5ef2aSThomas Huth .handler = &gen_##name, \ 470fcf5ef2aSThomas Huth .oname = onam, \ 471fcf5ef2aSThomas Huth }, \ 472fcf5ef2aSThomas Huth .oname = onam, \ 473fcf5ef2aSThomas Huth } 474fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 475fcf5ef2aSThomas Huth { \ 476fcf5ef2aSThomas Huth .opc1 = op1, \ 477fcf5ef2aSThomas Huth .opc2 = op2, \ 478fcf5ef2aSThomas Huth .opc3 = op3, \ 479fcf5ef2aSThomas Huth .opc4 = op4, \ 480fcf5ef2aSThomas Huth .handler = { \ 481fcf5ef2aSThomas Huth .inval1 = invl, \ 482fcf5ef2aSThomas Huth .type = _typ, \ 483fcf5ef2aSThomas Huth .type2 = _typ2, \ 484fcf5ef2aSThomas Huth .handler = &gen_##name, \ 485fcf5ef2aSThomas Huth .oname = stringify(name), \ 486fcf5ef2aSThomas Huth }, \ 487fcf5ef2aSThomas Huth .oname = stringify(name), \ 488fcf5ef2aSThomas Huth } 489fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 490fcf5ef2aSThomas Huth { \ 491fcf5ef2aSThomas Huth .opc1 = op1, \ 492fcf5ef2aSThomas Huth .opc2 = op2, \ 493fcf5ef2aSThomas Huth .opc3 = op3, \ 494fcf5ef2aSThomas Huth .opc4 = op4, \ 495fcf5ef2aSThomas Huth .handler = { \ 496fcf5ef2aSThomas Huth .inval1 = invl, \ 497fcf5ef2aSThomas Huth .type = _typ, \ 498fcf5ef2aSThomas Huth .type2 = _typ2, \ 499fcf5ef2aSThomas Huth .handler = &gen_##name, \ 500fcf5ef2aSThomas Huth .oname = onam, \ 501fcf5ef2aSThomas Huth }, \ 502fcf5ef2aSThomas Huth .oname = onam, \ 503fcf5ef2aSThomas Huth } 504fcf5ef2aSThomas Huth #else 505fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 506fcf5ef2aSThomas Huth { \ 507fcf5ef2aSThomas Huth .opc1 = op1, \ 508fcf5ef2aSThomas Huth .opc2 = op2, \ 509fcf5ef2aSThomas Huth .opc3 = op3, \ 510fcf5ef2aSThomas Huth .opc4 = 0xff, \ 511fcf5ef2aSThomas Huth .handler = { \ 512fcf5ef2aSThomas Huth .inval1 = invl, \ 513fcf5ef2aSThomas Huth .type = _typ, \ 514fcf5ef2aSThomas Huth .type2 = _typ2, \ 515fcf5ef2aSThomas Huth .handler = &gen_##name, \ 516fcf5ef2aSThomas Huth }, \ 517fcf5ef2aSThomas Huth .oname = stringify(name), \ 518fcf5ef2aSThomas Huth } 519fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 520fcf5ef2aSThomas Huth { \ 521fcf5ef2aSThomas Huth .opc1 = op1, \ 522fcf5ef2aSThomas Huth .opc2 = op2, \ 523fcf5ef2aSThomas Huth .opc3 = op3, \ 524fcf5ef2aSThomas Huth .opc4 = 0xff, \ 525fcf5ef2aSThomas Huth .handler = { \ 526fcf5ef2aSThomas Huth .inval1 = invl1, \ 527fcf5ef2aSThomas Huth .inval2 = invl2, \ 528fcf5ef2aSThomas Huth .type = _typ, \ 529fcf5ef2aSThomas Huth .type2 = _typ2, \ 530fcf5ef2aSThomas Huth .handler = &gen_##name, \ 531fcf5ef2aSThomas Huth }, \ 532fcf5ef2aSThomas Huth .oname = stringify(name), \ 533fcf5ef2aSThomas Huth } 534fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 535fcf5ef2aSThomas Huth { \ 536fcf5ef2aSThomas Huth .opc1 = op1, \ 537fcf5ef2aSThomas Huth .opc2 = op2, \ 538fcf5ef2aSThomas Huth .opc3 = op3, \ 539fcf5ef2aSThomas Huth .opc4 = 0xff, \ 540fcf5ef2aSThomas Huth .handler = { \ 541fcf5ef2aSThomas Huth .inval1 = invl, \ 542fcf5ef2aSThomas Huth .type = _typ, \ 543fcf5ef2aSThomas Huth .type2 = _typ2, \ 544fcf5ef2aSThomas Huth .handler = &gen_##name, \ 545fcf5ef2aSThomas Huth }, \ 546fcf5ef2aSThomas Huth .oname = onam, \ 547fcf5ef2aSThomas Huth } 548fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 549fcf5ef2aSThomas Huth { \ 550fcf5ef2aSThomas Huth .opc1 = op1, \ 551fcf5ef2aSThomas Huth .opc2 = op2, \ 552fcf5ef2aSThomas Huth .opc3 = op3, \ 553fcf5ef2aSThomas Huth .opc4 = op4, \ 554fcf5ef2aSThomas Huth .handler = { \ 555fcf5ef2aSThomas Huth .inval1 = invl, \ 556fcf5ef2aSThomas Huth .type = _typ, \ 557fcf5ef2aSThomas Huth .type2 = _typ2, \ 558fcf5ef2aSThomas Huth .handler = &gen_##name, \ 559fcf5ef2aSThomas Huth }, \ 560fcf5ef2aSThomas Huth .oname = stringify(name), \ 561fcf5ef2aSThomas Huth } 562fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 563fcf5ef2aSThomas Huth { \ 564fcf5ef2aSThomas Huth .opc1 = op1, \ 565fcf5ef2aSThomas Huth .opc2 = op2, \ 566fcf5ef2aSThomas Huth .opc3 = op3, \ 567fcf5ef2aSThomas Huth .opc4 = op4, \ 568fcf5ef2aSThomas Huth .handler = { \ 569fcf5ef2aSThomas Huth .inval1 = invl, \ 570fcf5ef2aSThomas Huth .type = _typ, \ 571fcf5ef2aSThomas Huth .type2 = _typ2, \ 572fcf5ef2aSThomas Huth .handler = &gen_##name, \ 573fcf5ef2aSThomas Huth }, \ 574fcf5ef2aSThomas Huth .oname = onam, \ 575fcf5ef2aSThomas Huth } 576fcf5ef2aSThomas Huth #endif 577fcf5ef2aSThomas Huth 578fcf5ef2aSThomas Huth /* SPR load/store helpers */ 579fcf5ef2aSThomas Huth static inline void gen_load_spr(TCGv t, int reg) 580fcf5ef2aSThomas Huth { 581fcf5ef2aSThomas Huth tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 582fcf5ef2aSThomas Huth } 583fcf5ef2aSThomas Huth 584fcf5ef2aSThomas Huth static inline void gen_store_spr(int reg, TCGv t) 585fcf5ef2aSThomas Huth { 586fcf5ef2aSThomas Huth tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 587fcf5ef2aSThomas Huth } 588fcf5ef2aSThomas Huth 589fcf5ef2aSThomas Huth /* Invalid instruction */ 590fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 591fcf5ef2aSThomas Huth { 592fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 593fcf5ef2aSThomas Huth } 594fcf5ef2aSThomas Huth 595fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 596fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 597fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 598fcf5ef2aSThomas Huth .type = PPC_NONE, 599fcf5ef2aSThomas Huth .type2 = PPC_NONE, 600fcf5ef2aSThomas Huth .handler = gen_invalid, 601fcf5ef2aSThomas Huth }; 602fcf5ef2aSThomas Huth 603fcf5ef2aSThomas Huth /*** Integer comparison ***/ 604fcf5ef2aSThomas Huth 605fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 606fcf5ef2aSThomas Huth { 607fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 608b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 609b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 610fcf5ef2aSThomas Huth 611b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 612b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 613b62b3686Spbonzini@redhat.com tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0); 614b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 615b62b3686Spbonzini@redhat.com tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0); 616b62b3686Spbonzini@redhat.com 617b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 618fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 619b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 620fcf5ef2aSThomas Huth 621fcf5ef2aSThomas Huth tcg_temp_free(t0); 622b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 623b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 624fcf5ef2aSThomas Huth } 625fcf5ef2aSThomas Huth 626fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 627fcf5ef2aSThomas Huth { 628fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 629fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 630fcf5ef2aSThomas Huth tcg_temp_free(t0); 631fcf5ef2aSThomas Huth } 632fcf5ef2aSThomas Huth 633fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 634fcf5ef2aSThomas Huth { 635fcf5ef2aSThomas Huth TCGv t0, t1; 636fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 637fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 638fcf5ef2aSThomas Huth if (s) { 639fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 640fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 641fcf5ef2aSThomas Huth } else { 642fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 643fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 644fcf5ef2aSThomas Huth } 645fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 646fcf5ef2aSThomas Huth tcg_temp_free(t1); 647fcf5ef2aSThomas Huth tcg_temp_free(t0); 648fcf5ef2aSThomas Huth } 649fcf5ef2aSThomas Huth 650fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 651fcf5ef2aSThomas Huth { 652fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 653fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 654fcf5ef2aSThomas Huth tcg_temp_free(t0); 655fcf5ef2aSThomas Huth } 656fcf5ef2aSThomas Huth 657fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 658fcf5ef2aSThomas Huth { 659fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 660fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 661fcf5ef2aSThomas Huth } else { 662fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 663fcf5ef2aSThomas Huth } 664fcf5ef2aSThomas Huth } 665fcf5ef2aSThomas Huth 666fcf5ef2aSThomas Huth /* cmp */ 667fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 668fcf5ef2aSThomas Huth { 669fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 670fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 671fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 672fcf5ef2aSThomas Huth } else { 673fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 674fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 675fcf5ef2aSThomas Huth } 676fcf5ef2aSThomas Huth } 677fcf5ef2aSThomas Huth 678fcf5ef2aSThomas Huth /* cmpi */ 679fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 680fcf5ef2aSThomas Huth { 681fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 682fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 683fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 684fcf5ef2aSThomas Huth } else { 685fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 686fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 687fcf5ef2aSThomas Huth } 688fcf5ef2aSThomas Huth } 689fcf5ef2aSThomas Huth 690fcf5ef2aSThomas Huth /* cmpl */ 691fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 692fcf5ef2aSThomas Huth { 693fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 694fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 695fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 696fcf5ef2aSThomas Huth } else { 697fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 698fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 699fcf5ef2aSThomas Huth } 700fcf5ef2aSThomas Huth } 701fcf5ef2aSThomas Huth 702fcf5ef2aSThomas Huth /* cmpli */ 703fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 704fcf5ef2aSThomas Huth { 705fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 706fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 707fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 708fcf5ef2aSThomas Huth } else { 709fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 710fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 711fcf5ef2aSThomas Huth } 712fcf5ef2aSThomas Huth } 713fcf5ef2aSThomas Huth 714fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 715fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 716fcf5ef2aSThomas Huth { 717fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 718fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 719fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 720fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 721fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 722fcf5ef2aSThomas Huth 723fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 724fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 725fcf5ef2aSThomas Huth 726fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 727fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 728fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 729fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 730fcf5ef2aSThomas Huth 731fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 732fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 733fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 734fcf5ef2aSThomas Huth 735fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 736fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 737fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 738fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 739fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 740fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 741fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 742fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 743fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 744fcf5ef2aSThomas Huth } 745efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 746fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 747fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 748fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 749fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 750fcf5ef2aSThomas Huth } 751fcf5ef2aSThomas Huth 752fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 753fcf5ef2aSThomas Huth /* cmpeqb */ 754fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 755fcf5ef2aSThomas Huth { 756fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 757fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 758fcf5ef2aSThomas Huth } 759fcf5ef2aSThomas Huth #endif 760fcf5ef2aSThomas Huth 761fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 762fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 763fcf5ef2aSThomas Huth { 764fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 765fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 766fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 767fcf5ef2aSThomas Huth TCGv zr; 768fcf5ef2aSThomas Huth 769fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 770fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 771fcf5ef2aSThomas Huth 772fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 773fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 774fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 775fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 776fcf5ef2aSThomas Huth tcg_temp_free(zr); 777fcf5ef2aSThomas Huth tcg_temp_free(t0); 778fcf5ef2aSThomas Huth } 779fcf5ef2aSThomas Huth 780fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 781fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 782fcf5ef2aSThomas Huth { 783fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 784fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 785fcf5ef2aSThomas Huth } 786fcf5ef2aSThomas Huth 787fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 788fcf5ef2aSThomas Huth 789fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 790fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 791fcf5ef2aSThomas Huth { 792fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 793fcf5ef2aSThomas Huth 794fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 795fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 796fcf5ef2aSThomas Huth if (sub) { 797fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 798fcf5ef2aSThomas Huth } else { 799fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 800fcf5ef2aSThomas Huth } 801fcf5ef2aSThomas Huth tcg_temp_free(t0); 802fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 803dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 804dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 805dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 806fcf5ef2aSThomas Huth } 807dc0ad844SNikunj A Dadhania } else { 808dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 809dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 810dc0ad844SNikunj A Dadhania } 81138a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 812dc0ad844SNikunj A Dadhania } 813fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 814fcf5ef2aSThomas Huth } 815fcf5ef2aSThomas Huth 8166b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8176b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 8186b10d008SNikunj A Dadhania int sub) 8196b10d008SNikunj A Dadhania { 8206b10d008SNikunj A Dadhania TCGv t0; 8216b10d008SNikunj A Dadhania 8226b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8236b10d008SNikunj A Dadhania return; 8246b10d008SNikunj A Dadhania } 8256b10d008SNikunj A Dadhania 8266b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 82733903d0aSNikunj A Dadhania if (sub) { 82833903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 82933903d0aSNikunj A Dadhania } else { 8306b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 83133903d0aSNikunj A Dadhania } 8326b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 8336b10d008SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); 8346b10d008SNikunj A Dadhania tcg_temp_free(t0); 8356b10d008SNikunj A Dadhania } 8366b10d008SNikunj A Dadhania 837fcf5ef2aSThomas Huth /* Common add function */ 838fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 839fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 840fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 841fcf5ef2aSThomas Huth { 842fcf5ef2aSThomas Huth TCGv t0 = ret; 843fcf5ef2aSThomas Huth 844fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 845fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 846fcf5ef2aSThomas Huth } 847fcf5ef2aSThomas Huth 848fcf5ef2aSThomas Huth if (compute_ca) { 849fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 850fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 851fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 852fcf5ef2aSThomas Huth carry into bit 32. */ 853fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 854fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 855fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 856fcf5ef2aSThomas Huth if (add_ca) { 857fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 858fcf5ef2aSThomas Huth } 859fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 860fcf5ef2aSThomas Huth tcg_temp_free(t1); 861e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 8626b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 8636b10d008SNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 8646b10d008SNikunj A Dadhania } 865fcf5ef2aSThomas Huth } else { 866fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 867fcf5ef2aSThomas Huth if (add_ca) { 868fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 869fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 870fcf5ef2aSThomas Huth } else { 871fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 872fcf5ef2aSThomas Huth } 8736b10d008SNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); 874fcf5ef2aSThomas Huth tcg_temp_free(zero); 875fcf5ef2aSThomas Huth } 876fcf5ef2aSThomas Huth } else { 877fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 878fcf5ef2aSThomas Huth if (add_ca) { 879fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 880fcf5ef2aSThomas Huth } 881fcf5ef2aSThomas Huth } 882fcf5ef2aSThomas Huth 883fcf5ef2aSThomas Huth if (compute_ov) { 884fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 885fcf5ef2aSThomas Huth } 886fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 887fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 888fcf5ef2aSThomas Huth } 889fcf5ef2aSThomas Huth 89011f4e8f8SRichard Henderson if (t0 != ret) { 891fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 892fcf5ef2aSThomas Huth tcg_temp_free(t0); 893fcf5ef2aSThomas Huth } 894fcf5ef2aSThomas Huth } 895fcf5ef2aSThomas Huth /* Add functions with two operands */ 896fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 897fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 898fcf5ef2aSThomas Huth { \ 899fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 900fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 901fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 902fcf5ef2aSThomas Huth } 903fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 904fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 905fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 906fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 907fcf5ef2aSThomas Huth { \ 908fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 909fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 910fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 911fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 912fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 913fcf5ef2aSThomas Huth } 914fcf5ef2aSThomas Huth 915fcf5ef2aSThomas Huth /* add add. addo addo. */ 916fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 917fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 918fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 919fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 920fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 921fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 922fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 923fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 924fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 925fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 926fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 927fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 928fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 929fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 930fcf5ef2aSThomas Huth /* addi */ 931fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 932fcf5ef2aSThomas Huth { 933fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 934fcf5ef2aSThomas Huth 935fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 936fcf5ef2aSThomas Huth /* li case */ 937fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 938fcf5ef2aSThomas Huth } else { 939fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 940fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 941fcf5ef2aSThomas Huth } 942fcf5ef2aSThomas Huth } 943fcf5ef2aSThomas Huth /* addic addic.*/ 944fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 945fcf5ef2aSThomas Huth { 946fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 947fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 948fcf5ef2aSThomas Huth c, 0, 1, 0, compute_rc0); 949fcf5ef2aSThomas Huth tcg_temp_free(c); 950fcf5ef2aSThomas Huth } 951fcf5ef2aSThomas Huth 952fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 953fcf5ef2aSThomas Huth { 954fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 955fcf5ef2aSThomas Huth } 956fcf5ef2aSThomas Huth 957fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 958fcf5ef2aSThomas Huth { 959fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 960fcf5ef2aSThomas Huth } 961fcf5ef2aSThomas Huth 962fcf5ef2aSThomas Huth /* addis */ 963fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 964fcf5ef2aSThomas Huth { 965fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 966fcf5ef2aSThomas Huth 967fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 968fcf5ef2aSThomas Huth /* lis case */ 969fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 970fcf5ef2aSThomas Huth } else { 971fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 972fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 973fcf5ef2aSThomas Huth } 974fcf5ef2aSThomas Huth } 975fcf5ef2aSThomas Huth 976fcf5ef2aSThomas Huth /* addpcis */ 977fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 978fcf5ef2aSThomas Huth { 979fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 980fcf5ef2aSThomas Huth 981b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 982fcf5ef2aSThomas Huth } 983fcf5ef2aSThomas Huth 984fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 985fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 986fcf5ef2aSThomas Huth { 987fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 988fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 989fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 990fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 991fcf5ef2aSThomas Huth 992fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 993fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 994fcf5ef2aSThomas Huth if (sign) { 995fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 996fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 997fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 998fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 999fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1000fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1001fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1002fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1003fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1004fcf5ef2aSThomas Huth } else { 1005fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1006fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1007fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1008fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1009fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1010fcf5ef2aSThomas Huth } 1011fcf5ef2aSThomas Huth if (compute_ov) { 1012fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1013c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1014c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1015c44027ffSNikunj A Dadhania } 1016fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1017fcf5ef2aSThomas Huth } 1018fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1019fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1020fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1021fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1022fcf5ef2aSThomas Huth 1023fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1024fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1025fcf5ef2aSThomas Huth } 1026fcf5ef2aSThomas Huth /* Div functions */ 1027fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1028fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1029fcf5ef2aSThomas Huth { \ 1030fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1031fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1032fcf5ef2aSThomas Huth sign, compute_ov); \ 1033fcf5ef2aSThomas Huth } 1034fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1035fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1036fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1037fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1038fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1039fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1040fcf5ef2aSThomas Huth 1041fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1042fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1043fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1044fcf5ef2aSThomas Huth { \ 1045fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1046fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1047fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1048fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1049fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1050fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1051fcf5ef2aSThomas Huth } \ 1052fcf5ef2aSThomas Huth } 1053fcf5ef2aSThomas Huth 1054fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1055fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1056fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1057fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1058fcf5ef2aSThomas Huth 1059fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1060fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1061fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1062fcf5ef2aSThomas Huth { 1063fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1064fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1065fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1066fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1067fcf5ef2aSThomas Huth 1068fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1069fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1070fcf5ef2aSThomas Huth if (sign) { 1071fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1072fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1073fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1074fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1075fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1076fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1077fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1078fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1079fcf5ef2aSThomas Huth } else { 1080fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1081fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1082fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1083fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1084fcf5ef2aSThomas Huth } 1085fcf5ef2aSThomas Huth if (compute_ov) { 1086fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1087c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1088c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1089c44027ffSNikunj A Dadhania } 1090fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1091fcf5ef2aSThomas Huth } 1092fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1093fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1094fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1095fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1096fcf5ef2aSThomas Huth 1097fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1098fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1099fcf5ef2aSThomas Huth } 1100fcf5ef2aSThomas Huth 1101fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1102fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1103fcf5ef2aSThomas Huth { \ 1104fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1105fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1106fcf5ef2aSThomas Huth sign, compute_ov); \ 1107fcf5ef2aSThomas Huth } 1108c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1109fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1110fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1111c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1112fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1113fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1114fcf5ef2aSThomas Huth 1115fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1116fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1117fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1118fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1119fcf5ef2aSThomas Huth #endif 1120fcf5ef2aSThomas Huth 1121fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1122fcf5ef2aSThomas Huth TCGv arg2, int sign) 1123fcf5ef2aSThomas Huth { 1124fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1125fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1126fcf5ef2aSThomas Huth 1127fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1128fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1129fcf5ef2aSThomas Huth if (sign) { 1130fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1131fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1132fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1133fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1134fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1135fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1136fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1137fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1138fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1139fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1140fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1141fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1142fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1143fcf5ef2aSThomas Huth } else { 1144fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1145fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1146fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1147fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1148fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1149fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1150fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1151fcf5ef2aSThomas Huth } 1152fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1153fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1154fcf5ef2aSThomas Huth } 1155fcf5ef2aSThomas Huth 1156fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1157fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1158fcf5ef2aSThomas Huth { \ 1159fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1160fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1161fcf5ef2aSThomas Huth sign); \ 1162fcf5ef2aSThomas Huth } 1163fcf5ef2aSThomas Huth 1164fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1165fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1166fcf5ef2aSThomas Huth 1167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1168fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1169fcf5ef2aSThomas Huth TCGv arg2, int sign) 1170fcf5ef2aSThomas Huth { 1171fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1172fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1173fcf5ef2aSThomas Huth 1174fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1175fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1176fcf5ef2aSThomas Huth if (sign) { 1177fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1178fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1179fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1180fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1181fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1182fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1183fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1184fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1185fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1186fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1187fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1188fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1189fcf5ef2aSThomas Huth } else { 1190fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1191fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1192fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1193fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1194fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1195fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1196fcf5ef2aSThomas Huth } 1197fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1198fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1199fcf5ef2aSThomas Huth } 1200fcf5ef2aSThomas Huth 1201fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1202fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1203fcf5ef2aSThomas Huth { \ 1204fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1205fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1206fcf5ef2aSThomas Huth sign); \ 1207fcf5ef2aSThomas Huth } 1208fcf5ef2aSThomas Huth 1209fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1210fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1211fcf5ef2aSThomas Huth #endif 1212fcf5ef2aSThomas Huth 1213fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1214fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1215fcf5ef2aSThomas Huth { 1216fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1217fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1218fcf5ef2aSThomas Huth 1219fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1220fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1221fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1222fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1223fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1224fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1225fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1226fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1227fcf5ef2aSThomas Huth } 1228fcf5ef2aSThomas Huth 1229fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1230fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1231fcf5ef2aSThomas Huth { 1232fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1233fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1234fcf5ef2aSThomas Huth 1235fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1236fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1237fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1238fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1239fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1240fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1241fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1242fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1243fcf5ef2aSThomas Huth } 1244fcf5ef2aSThomas Huth 1245fcf5ef2aSThomas Huth /* mullw mullw. */ 1246fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1247fcf5ef2aSThomas Huth { 1248fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1249fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1250fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1251fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1252fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1253fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1254fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1255fcf5ef2aSThomas Huth tcg_temp_free(t0); 1256fcf5ef2aSThomas Huth tcg_temp_free(t1); 1257fcf5ef2aSThomas Huth #else 1258fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1259fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1260fcf5ef2aSThomas Huth #endif 1261fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1262fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1263fcf5ef2aSThomas Huth } 1264fcf5ef2aSThomas Huth 1265fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1266fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1267fcf5ef2aSThomas Huth { 1268fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1269fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1270fcf5ef2aSThomas Huth 1271fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1272fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1273fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1274fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1275fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1276fcf5ef2aSThomas Huth #else 1277fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1278fcf5ef2aSThomas Huth #endif 1279fcf5ef2aSThomas Huth 1280fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1281fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1282fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 128361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 128461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 128561aa9a69SNikunj A Dadhania } 1286fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1287fcf5ef2aSThomas Huth 1288fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1289fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1290fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1291fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1292fcf5ef2aSThomas Huth } 1293fcf5ef2aSThomas Huth 1294fcf5ef2aSThomas Huth /* mulli */ 1295fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1296fcf5ef2aSThomas Huth { 1297fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1298fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1299fcf5ef2aSThomas Huth } 1300fcf5ef2aSThomas Huth 1301fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1302fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1303fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1304fcf5ef2aSThomas Huth { 1305fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1306fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1307fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1308fcf5ef2aSThomas Huth tcg_temp_free(lo); 1309fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1310fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1311fcf5ef2aSThomas Huth } 1312fcf5ef2aSThomas Huth } 1313fcf5ef2aSThomas Huth 1314fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1315fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1316fcf5ef2aSThomas Huth { 1317fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1318fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1319fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1320fcf5ef2aSThomas Huth tcg_temp_free(lo); 1321fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1322fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1323fcf5ef2aSThomas Huth } 1324fcf5ef2aSThomas Huth } 1325fcf5ef2aSThomas Huth 1326fcf5ef2aSThomas Huth /* mulld mulld. */ 1327fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1328fcf5ef2aSThomas Huth { 1329fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1330fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1331fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1332fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1333fcf5ef2aSThomas Huth } 1334fcf5ef2aSThomas Huth 1335fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1336fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1337fcf5ef2aSThomas Huth { 1338fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1339fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1340fcf5ef2aSThomas Huth 1341fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1342fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1343fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1344fcf5ef2aSThomas Huth 1345fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1346fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 134761aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 134861aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 134961aa9a69SNikunj A Dadhania } 1350fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1351fcf5ef2aSThomas Huth 1352fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1353fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1354fcf5ef2aSThomas Huth 1355fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1356fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1357fcf5ef2aSThomas Huth } 1358fcf5ef2aSThomas Huth } 1359fcf5ef2aSThomas Huth #endif 1360fcf5ef2aSThomas Huth 1361fcf5ef2aSThomas Huth /* Common subf function */ 1362fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1363fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1364fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1365fcf5ef2aSThomas Huth { 1366fcf5ef2aSThomas Huth TCGv t0 = ret; 1367fcf5ef2aSThomas Huth 1368fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1369fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1370fcf5ef2aSThomas Huth } 1371fcf5ef2aSThomas Huth 1372fcf5ef2aSThomas Huth if (compute_ca) { 1373fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1374fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1375fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 1376fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 1377fcf5ef2aSThomas Huth carry into bit 32. */ 1378fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1379fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1380fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1381fcf5ef2aSThomas Huth if (add_ca) { 1382fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1383fcf5ef2aSThomas Huth } else { 1384fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1385fcf5ef2aSThomas Huth } 1386fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1387fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1388fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1389fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1390fcf5ef2aSThomas Huth tcg_temp_free(t1); 1391e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 139233903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 139333903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 139433903d0aSNikunj A Dadhania } 1395fcf5ef2aSThomas Huth } else if (add_ca) { 1396fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1397fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1398fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1399fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1400fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 140133903d0aSNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); 1402fcf5ef2aSThomas Huth tcg_temp_free(zero); 1403fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1404fcf5ef2aSThomas Huth } else { 1405fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1406fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 140733903d0aSNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); 1408fcf5ef2aSThomas Huth } 1409fcf5ef2aSThomas Huth } else if (add_ca) { 1410fcf5ef2aSThomas Huth /* Since we're ignoring carry-out, we can simplify the 1411fcf5ef2aSThomas Huth standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1412fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1413fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1414fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1415fcf5ef2aSThomas Huth } else { 1416fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth 1419fcf5ef2aSThomas Huth if (compute_ov) { 1420fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1421fcf5ef2aSThomas Huth } 1422fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1423fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1424fcf5ef2aSThomas Huth } 1425fcf5ef2aSThomas Huth 142611f4e8f8SRichard Henderson if (t0 != ret) { 1427fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1428fcf5ef2aSThomas Huth tcg_temp_free(t0); 1429fcf5ef2aSThomas Huth } 1430fcf5ef2aSThomas Huth } 1431fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1432fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1433fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1434fcf5ef2aSThomas Huth { \ 1435fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1436fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1437fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1438fcf5ef2aSThomas Huth } 1439fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1440fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1441fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1442fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1443fcf5ef2aSThomas Huth { \ 1444fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1445fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1446fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1447fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1448fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1449fcf5ef2aSThomas Huth } 1450fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1451fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1452fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1453fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1454fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1455fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1456fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1457fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1458fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1459fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1460fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1461fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1462fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1463fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1464fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1465fcf5ef2aSThomas Huth 1466fcf5ef2aSThomas Huth /* subfic */ 1467fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1468fcf5ef2aSThomas Huth { 1469fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1470fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1471fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1472fcf5ef2aSThomas Huth tcg_temp_free(c); 1473fcf5ef2aSThomas Huth } 1474fcf5ef2aSThomas Huth 1475fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1476fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1477fcf5ef2aSThomas Huth { 1478fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1479fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1480fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1481fcf5ef2aSThomas Huth tcg_temp_free(zero); 1482fcf5ef2aSThomas Huth } 1483fcf5ef2aSThomas Huth 1484fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1485fcf5ef2aSThomas Huth { 14861480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 14871480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 14881480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 14891480d71cSNikunj A Dadhania } 1490fcf5ef2aSThomas Huth } 1491fcf5ef2aSThomas Huth 1492fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1493fcf5ef2aSThomas Huth { 1494fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1495fcf5ef2aSThomas Huth } 1496fcf5ef2aSThomas Huth 1497fcf5ef2aSThomas Huth /*** Integer logical ***/ 1498fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1499fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1500fcf5ef2aSThomas Huth { \ 1501fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1502fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1503fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1504fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1505fcf5ef2aSThomas Huth } 1506fcf5ef2aSThomas Huth 1507fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1508fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1509fcf5ef2aSThomas Huth { \ 1510fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1511fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1512fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1513fcf5ef2aSThomas Huth } 1514fcf5ef2aSThomas Huth 1515fcf5ef2aSThomas Huth /* and & and. */ 1516fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1517fcf5ef2aSThomas Huth /* andc & andc. */ 1518fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1519fcf5ef2aSThomas Huth 1520fcf5ef2aSThomas Huth /* andi. */ 1521fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1522fcf5ef2aSThomas Huth { 1523fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1524fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1525fcf5ef2aSThomas Huth } 1526fcf5ef2aSThomas Huth 1527fcf5ef2aSThomas Huth /* andis. */ 1528fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1529fcf5ef2aSThomas Huth { 1530fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1531fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1532fcf5ef2aSThomas Huth } 1533fcf5ef2aSThomas Huth 1534fcf5ef2aSThomas Huth /* cntlzw */ 1535fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1536fcf5ef2aSThomas Huth { 15379b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15389b8514e5SRichard Henderson 15399b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15409b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15419b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15429b8514e5SRichard Henderson tcg_temp_free_i32(t); 15439b8514e5SRichard Henderson 1544fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1545fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1546fcf5ef2aSThomas Huth } 1547fcf5ef2aSThomas Huth 1548fcf5ef2aSThomas Huth /* cnttzw */ 1549fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1550fcf5ef2aSThomas Huth { 15519b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15529b8514e5SRichard Henderson 15539b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15549b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15559b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15569b8514e5SRichard Henderson tcg_temp_free_i32(t); 15579b8514e5SRichard Henderson 1558fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1559fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1560fcf5ef2aSThomas Huth } 1561fcf5ef2aSThomas Huth } 1562fcf5ef2aSThomas Huth 1563fcf5ef2aSThomas Huth /* eqv & eqv. */ 1564fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1565fcf5ef2aSThomas Huth /* extsb & extsb. */ 1566fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1567fcf5ef2aSThomas Huth /* extsh & extsh. */ 1568fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1569fcf5ef2aSThomas Huth /* nand & nand. */ 1570fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1571fcf5ef2aSThomas Huth /* nor & nor. */ 1572fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1573fcf5ef2aSThomas Huth 1574fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1575fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1576fcf5ef2aSThomas Huth { 1577fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1578fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1579fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1580fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1581fcf5ef2aSThomas Huth 1582fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1583b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1584fcf5ef2aSThomas Huth } 1585fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1586fcf5ef2aSThomas Huth 1587fcf5ef2aSThomas Huth /* or & or. */ 1588fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1589fcf5ef2aSThomas Huth { 1590fcf5ef2aSThomas Huth int rs, ra, rb; 1591fcf5ef2aSThomas Huth 1592fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1593fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1594fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1595fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1596fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1597fcf5ef2aSThomas Huth if (rs != rb) 1598fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1599fcf5ef2aSThomas Huth else 1600fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1601fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1602fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1603fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1604fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1605fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1606fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1607fcf5ef2aSThomas Huth int prio = 0; 1608fcf5ef2aSThomas Huth 1609fcf5ef2aSThomas Huth switch (rs) { 1610fcf5ef2aSThomas Huth case 1: 1611fcf5ef2aSThomas Huth /* Set process priority to low */ 1612fcf5ef2aSThomas Huth prio = 2; 1613fcf5ef2aSThomas Huth break; 1614fcf5ef2aSThomas Huth case 6: 1615fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1616fcf5ef2aSThomas Huth prio = 3; 1617fcf5ef2aSThomas Huth break; 1618fcf5ef2aSThomas Huth case 2: 1619fcf5ef2aSThomas Huth /* Set process priority to normal */ 1620fcf5ef2aSThomas Huth prio = 4; 1621fcf5ef2aSThomas Huth break; 1622fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1623fcf5ef2aSThomas Huth case 31: 1624fcf5ef2aSThomas Huth if (!ctx->pr) { 1625fcf5ef2aSThomas Huth /* Set process priority to very low */ 1626fcf5ef2aSThomas Huth prio = 1; 1627fcf5ef2aSThomas Huth } 1628fcf5ef2aSThomas Huth break; 1629fcf5ef2aSThomas Huth case 5: 1630fcf5ef2aSThomas Huth if (!ctx->pr) { 1631fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1632fcf5ef2aSThomas Huth prio = 5; 1633fcf5ef2aSThomas Huth } 1634fcf5ef2aSThomas Huth break; 1635fcf5ef2aSThomas Huth case 3: 1636fcf5ef2aSThomas Huth if (!ctx->pr) { 1637fcf5ef2aSThomas Huth /* Set process priority to high */ 1638fcf5ef2aSThomas Huth prio = 6; 1639fcf5ef2aSThomas Huth } 1640fcf5ef2aSThomas Huth break; 1641fcf5ef2aSThomas Huth case 7: 1642fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1643fcf5ef2aSThomas Huth /* Set process priority to very high */ 1644fcf5ef2aSThomas Huth prio = 7; 1645fcf5ef2aSThomas Huth } 1646fcf5ef2aSThomas Huth break; 1647fcf5ef2aSThomas Huth #endif 1648fcf5ef2aSThomas Huth default: 1649fcf5ef2aSThomas Huth break; 1650fcf5ef2aSThomas Huth } 1651fcf5ef2aSThomas Huth if (prio) { 1652fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1653fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1654fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1655fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1656fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1657fcf5ef2aSThomas Huth tcg_temp_free(t0); 1658fcf5ef2aSThomas Huth } 1659fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1660fcf5ef2aSThomas Huth /* Pause out of TCG otherwise spin loops with smt_low eat too much 1661fcf5ef2aSThomas Huth * CPU and the kernel hangs. This applies to all encodings other 1662fcf5ef2aSThomas Huth * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1663fcf5ef2aSThomas Huth * and all currently undefined. 1664fcf5ef2aSThomas Huth */ 1665fcf5ef2aSThomas Huth gen_pause(ctx); 1666fcf5ef2aSThomas Huth #endif 1667fcf5ef2aSThomas Huth #endif 1668fcf5ef2aSThomas Huth } 1669fcf5ef2aSThomas Huth } 1670fcf5ef2aSThomas Huth /* orc & orc. */ 1671fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1672fcf5ef2aSThomas Huth 1673fcf5ef2aSThomas Huth /* xor & xor. */ 1674fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1675fcf5ef2aSThomas Huth { 1676fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1677fcf5ef2aSThomas Huth if (rS(ctx->opcode) != rB(ctx->opcode)) 1678fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1679fcf5ef2aSThomas Huth else 1680fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1681fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1682fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1683fcf5ef2aSThomas Huth } 1684fcf5ef2aSThomas Huth 1685fcf5ef2aSThomas Huth /* ori */ 1686fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1687fcf5ef2aSThomas Huth { 1688fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1689fcf5ef2aSThomas Huth 1690fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1691fcf5ef2aSThomas Huth return; 1692fcf5ef2aSThomas Huth } 1693fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1694fcf5ef2aSThomas Huth } 1695fcf5ef2aSThomas Huth 1696fcf5ef2aSThomas Huth /* oris */ 1697fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1698fcf5ef2aSThomas Huth { 1699fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1700fcf5ef2aSThomas Huth 1701fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1702fcf5ef2aSThomas Huth /* NOP */ 1703fcf5ef2aSThomas Huth return; 1704fcf5ef2aSThomas Huth } 1705fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1706fcf5ef2aSThomas Huth } 1707fcf5ef2aSThomas Huth 1708fcf5ef2aSThomas Huth /* xori */ 1709fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1710fcf5ef2aSThomas Huth { 1711fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1712fcf5ef2aSThomas Huth 1713fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1714fcf5ef2aSThomas Huth /* NOP */ 1715fcf5ef2aSThomas Huth return; 1716fcf5ef2aSThomas Huth } 1717fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1718fcf5ef2aSThomas Huth } 1719fcf5ef2aSThomas Huth 1720fcf5ef2aSThomas Huth /* xoris */ 1721fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1722fcf5ef2aSThomas Huth { 1723fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1724fcf5ef2aSThomas Huth 1725fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1726fcf5ef2aSThomas Huth /* NOP */ 1727fcf5ef2aSThomas Huth return; 1728fcf5ef2aSThomas Huth } 1729fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1730fcf5ef2aSThomas Huth } 1731fcf5ef2aSThomas Huth 1732fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1733fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1734fcf5ef2aSThomas Huth { 1735fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1736fcf5ef2aSThomas Huth } 1737fcf5ef2aSThomas Huth 1738fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1739fcf5ef2aSThomas Huth { 174079770002SRichard Henderson #if defined(TARGET_PPC64) 1741fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 174279770002SRichard Henderson #else 174379770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 174479770002SRichard Henderson #endif 1745fcf5ef2aSThomas Huth } 1746fcf5ef2aSThomas Huth 1747fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1748fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1749fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1750fcf5ef2aSThomas Huth { 175179770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1752fcf5ef2aSThomas Huth } 1753fcf5ef2aSThomas Huth #endif 1754fcf5ef2aSThomas Huth 1755fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1756fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1757fcf5ef2aSThomas Huth { 1758fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1759fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1760fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1761fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1762fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1763fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1764fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1765fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1766fcf5ef2aSThomas Huth tcg_temp_free(t0); 1767fcf5ef2aSThomas Huth } 1768fcf5ef2aSThomas Huth 1769fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1770fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1771fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1772fcf5ef2aSThomas Huth { 1773fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1774fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1775fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1776fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1777fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1778fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1779fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1780fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1781fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1782fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1783fcf5ef2aSThomas Huth tcg_temp_free(t0); 1784fcf5ef2aSThomas Huth } 1785fcf5ef2aSThomas Huth #endif 1786fcf5ef2aSThomas Huth 1787fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1788fcf5ef2aSThomas Huth /* bpermd */ 1789fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1790fcf5ef2aSThomas Huth { 1791fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1792fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1793fcf5ef2aSThomas Huth } 1794fcf5ef2aSThomas Huth #endif 1795fcf5ef2aSThomas Huth 1796fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1797fcf5ef2aSThomas Huth /* extsw & extsw. */ 1798fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1799fcf5ef2aSThomas Huth 1800fcf5ef2aSThomas Huth /* cntlzd */ 1801fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1802fcf5ef2aSThomas Huth { 18039b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1804fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1805fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1806fcf5ef2aSThomas Huth } 1807fcf5ef2aSThomas Huth 1808fcf5ef2aSThomas Huth /* cnttzd */ 1809fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1810fcf5ef2aSThomas Huth { 18119b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1812fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1813fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1814fcf5ef2aSThomas Huth } 1815fcf5ef2aSThomas Huth } 1816fcf5ef2aSThomas Huth 1817fcf5ef2aSThomas Huth /* darn */ 1818fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1819fcf5ef2aSThomas Huth { 1820fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1821fcf5ef2aSThomas Huth 1822fcf5ef2aSThomas Huth if (l == 0) { 1823fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1824fcf5ef2aSThomas Huth } else if (l <= 2) { 1825fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1826fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1827fcf5ef2aSThomas Huth } else { 1828fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1829fcf5ef2aSThomas Huth } 1830fcf5ef2aSThomas Huth } 1831fcf5ef2aSThomas Huth #endif 1832fcf5ef2aSThomas Huth 1833fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1834fcf5ef2aSThomas Huth 1835fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1836fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1837fcf5ef2aSThomas Huth { 1838fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1839fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1840fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1841fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1842fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1843fcf5ef2aSThomas Huth 1844fcf5ef2aSThomas Huth if (sh == (31-me) && mb <= me) { 1845fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1846fcf5ef2aSThomas Huth } else { 1847fcf5ef2aSThomas Huth target_ulong mask; 1848fcf5ef2aSThomas Huth TCGv t1; 1849fcf5ef2aSThomas Huth 1850fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1851fcf5ef2aSThomas Huth mb += 32; 1852fcf5ef2aSThomas Huth me += 32; 1853fcf5ef2aSThomas Huth #endif 1854fcf5ef2aSThomas Huth mask = MASK(mb, me); 1855fcf5ef2aSThomas Huth 1856fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1857fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1858fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1859fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1860fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1861fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1862fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1863fcf5ef2aSThomas Huth } else { 1864fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1865fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1866fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1867fcf5ef2aSThomas Huth #else 1868fcf5ef2aSThomas Huth g_assert_not_reached(); 1869fcf5ef2aSThomas Huth #endif 1870fcf5ef2aSThomas Huth } 1871fcf5ef2aSThomas Huth 1872fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1873fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1874fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1875fcf5ef2aSThomas Huth tcg_temp_free(t1); 1876fcf5ef2aSThomas Huth } 1877fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1878fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1879fcf5ef2aSThomas Huth } 1880fcf5ef2aSThomas Huth } 1881fcf5ef2aSThomas Huth 1882fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1883fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1884fcf5ef2aSThomas Huth { 1885fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1886fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 18877b4d326fSRichard Henderson int sh = SH(ctx->opcode); 18887b4d326fSRichard Henderson int mb = MB(ctx->opcode); 18897b4d326fSRichard Henderson int me = ME(ctx->opcode); 18907b4d326fSRichard Henderson int len = me - mb + 1; 18917b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1892fcf5ef2aSThomas Huth 18937b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 18947b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 18957b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 18967b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1897fcf5ef2aSThomas Huth } else { 1898fcf5ef2aSThomas Huth target_ulong mask; 1899fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1900fcf5ef2aSThomas Huth mb += 32; 1901fcf5ef2aSThomas Huth me += 32; 1902fcf5ef2aSThomas Huth #endif 1903fcf5ef2aSThomas Huth mask = MASK(mb, me); 19047b4d326fSRichard Henderson if (sh == 0) { 19057b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 19067b4d326fSRichard Henderson } else if (mask <= 0xffffffffu) { 1907fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1908fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1909fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1910fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1911fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1912fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1913fcf5ef2aSThomas Huth } else { 1914fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1915fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1916fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1917fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1918fcf5ef2aSThomas Huth #else 1919fcf5ef2aSThomas Huth g_assert_not_reached(); 1920fcf5ef2aSThomas Huth #endif 1921fcf5ef2aSThomas Huth } 1922fcf5ef2aSThomas Huth } 1923fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1924fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1925fcf5ef2aSThomas Huth } 1926fcf5ef2aSThomas Huth } 1927fcf5ef2aSThomas Huth 1928fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1929fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1930fcf5ef2aSThomas Huth { 1931fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1932fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1933fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1934fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1935fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1936fcf5ef2aSThomas Huth target_ulong mask; 1937fcf5ef2aSThomas Huth 1938fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1939fcf5ef2aSThomas Huth mb += 32; 1940fcf5ef2aSThomas Huth me += 32; 1941fcf5ef2aSThomas Huth #endif 1942fcf5ef2aSThomas Huth mask = MASK(mb, me); 1943fcf5ef2aSThomas Huth 1944fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1945fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1946fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1947fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1948fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1949fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1950fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1951fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1952fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1953fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1954fcf5ef2aSThomas Huth } else { 1955fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1956fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1957fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1958fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1959fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1960fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1961fcf5ef2aSThomas Huth #else 1962fcf5ef2aSThomas Huth g_assert_not_reached(); 1963fcf5ef2aSThomas Huth #endif 1964fcf5ef2aSThomas Huth } 1965fcf5ef2aSThomas Huth 1966fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 1967fcf5ef2aSThomas Huth 1968fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1969fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1970fcf5ef2aSThomas Huth } 1971fcf5ef2aSThomas Huth } 1972fcf5ef2aSThomas Huth 1973fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1974fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 1975fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1976fcf5ef2aSThomas Huth { \ 1977fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 1978fcf5ef2aSThomas Huth } \ 1979fcf5ef2aSThomas Huth \ 1980fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1981fcf5ef2aSThomas Huth { \ 1982fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 1983fcf5ef2aSThomas Huth } 1984fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 1985fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1986fcf5ef2aSThomas Huth { \ 1987fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 1988fcf5ef2aSThomas Huth } \ 1989fcf5ef2aSThomas Huth \ 1990fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1991fcf5ef2aSThomas Huth { \ 1992fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 1993fcf5ef2aSThomas Huth } \ 1994fcf5ef2aSThomas Huth \ 1995fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 1996fcf5ef2aSThomas Huth { \ 1997fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 1998fcf5ef2aSThomas Huth } \ 1999fcf5ef2aSThomas Huth \ 2000fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2001fcf5ef2aSThomas Huth { \ 2002fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2003fcf5ef2aSThomas Huth } 2004fcf5ef2aSThomas Huth 2005fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2006fcf5ef2aSThomas Huth { 2007fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2008fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20097b4d326fSRichard Henderson int len = me - mb + 1; 20107b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2011fcf5ef2aSThomas Huth 20127b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20137b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20147b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20157b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2016fcf5ef2aSThomas Huth } else { 2017fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2018fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2019fcf5ef2aSThomas Huth } 2020fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2021fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2022fcf5ef2aSThomas Huth } 2023fcf5ef2aSThomas Huth } 2024fcf5ef2aSThomas Huth 2025fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2026fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2027fcf5ef2aSThomas Huth { 2028fcf5ef2aSThomas Huth uint32_t sh, mb; 2029fcf5ef2aSThomas Huth 2030fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2031fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2032fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2033fcf5ef2aSThomas Huth } 2034fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2035fcf5ef2aSThomas Huth 2036fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2037fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2038fcf5ef2aSThomas Huth { 2039fcf5ef2aSThomas Huth uint32_t sh, me; 2040fcf5ef2aSThomas Huth 2041fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2042fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2043fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2044fcf5ef2aSThomas Huth } 2045fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2046fcf5ef2aSThomas Huth 2047fcf5ef2aSThomas Huth /* rldic - rldic. */ 2048fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2049fcf5ef2aSThomas Huth { 2050fcf5ef2aSThomas Huth uint32_t sh, mb; 2051fcf5ef2aSThomas Huth 2052fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2053fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2054fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2055fcf5ef2aSThomas Huth } 2056fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2057fcf5ef2aSThomas Huth 2058fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2059fcf5ef2aSThomas Huth { 2060fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2061fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2062fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2063fcf5ef2aSThomas Huth TCGv t0; 2064fcf5ef2aSThomas Huth 2065fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2066fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2067fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2068fcf5ef2aSThomas Huth tcg_temp_free(t0); 2069fcf5ef2aSThomas Huth 2070fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2071fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2072fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2073fcf5ef2aSThomas Huth } 2074fcf5ef2aSThomas Huth } 2075fcf5ef2aSThomas Huth 2076fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2077fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2078fcf5ef2aSThomas Huth { 2079fcf5ef2aSThomas Huth uint32_t mb; 2080fcf5ef2aSThomas Huth 2081fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2082fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2083fcf5ef2aSThomas Huth } 2084fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2085fcf5ef2aSThomas Huth 2086fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2087fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2088fcf5ef2aSThomas Huth { 2089fcf5ef2aSThomas Huth uint32_t me; 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2092fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2093fcf5ef2aSThomas Huth } 2094fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2095fcf5ef2aSThomas Huth 2096fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2097fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2098fcf5ef2aSThomas Huth { 2099fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2100fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2101fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2102fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2103fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2104fcf5ef2aSThomas Huth 2105fcf5ef2aSThomas Huth if (mb <= me) { 2106fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2107fcf5ef2aSThomas Huth } else { 2108fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2109fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2110fcf5ef2aSThomas Huth 2111fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2112fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2113fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2114fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2115fcf5ef2aSThomas Huth tcg_temp_free(t1); 2116fcf5ef2aSThomas Huth } 2117fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2118fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2119fcf5ef2aSThomas Huth } 2120fcf5ef2aSThomas Huth } 2121fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2122fcf5ef2aSThomas Huth #endif 2123fcf5ef2aSThomas Huth 2124fcf5ef2aSThomas Huth /*** Integer shift ***/ 2125fcf5ef2aSThomas Huth 2126fcf5ef2aSThomas Huth /* slw & slw. */ 2127fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2128fcf5ef2aSThomas Huth { 2129fcf5ef2aSThomas Huth TCGv t0, t1; 2130fcf5ef2aSThomas Huth 2131fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2132fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2133fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2134fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2135fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2136fcf5ef2aSThomas Huth #else 2137fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2138fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2139fcf5ef2aSThomas Huth #endif 2140fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2141fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2142fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2143fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2144fcf5ef2aSThomas Huth tcg_temp_free(t1); 2145fcf5ef2aSThomas Huth tcg_temp_free(t0); 2146fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2147fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2148fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2149fcf5ef2aSThomas Huth } 2150fcf5ef2aSThomas Huth 2151fcf5ef2aSThomas Huth /* sraw & sraw. */ 2152fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2153fcf5ef2aSThomas Huth { 2154fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2155fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2156fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2157fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2158fcf5ef2aSThomas Huth } 2159fcf5ef2aSThomas Huth 2160fcf5ef2aSThomas Huth /* srawi & srawi. */ 2161fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2162fcf5ef2aSThomas Huth { 2163fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2164fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2165fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2166fcf5ef2aSThomas Huth if (sh == 0) { 2167fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2168fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2169af1c259fSSandipan Das if (is_isa300(ctx)) { 2170af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2171af1c259fSSandipan Das } 2172fcf5ef2aSThomas Huth } else { 2173fcf5ef2aSThomas Huth TCGv t0; 2174fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2175fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2176fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2177fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2178fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2179fcf5ef2aSThomas Huth tcg_temp_free(t0); 2180fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2181af1c259fSSandipan Das if (is_isa300(ctx)) { 2182af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2183af1c259fSSandipan Das } 2184fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2185fcf5ef2aSThomas Huth } 2186fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2187fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2188fcf5ef2aSThomas Huth } 2189fcf5ef2aSThomas Huth } 2190fcf5ef2aSThomas Huth 2191fcf5ef2aSThomas Huth /* srw & srw. */ 2192fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2193fcf5ef2aSThomas Huth { 2194fcf5ef2aSThomas Huth TCGv t0, t1; 2195fcf5ef2aSThomas Huth 2196fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2197fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2198fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2199fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2200fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2201fcf5ef2aSThomas Huth #else 2202fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2203fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2204fcf5ef2aSThomas Huth #endif 2205fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2206fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2207fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2208fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2209fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2210fcf5ef2aSThomas Huth tcg_temp_free(t1); 2211fcf5ef2aSThomas Huth tcg_temp_free(t0); 2212fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2213fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2214fcf5ef2aSThomas Huth } 2215fcf5ef2aSThomas Huth 2216fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2217fcf5ef2aSThomas Huth /* sld & sld. */ 2218fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2219fcf5ef2aSThomas Huth { 2220fcf5ef2aSThomas Huth TCGv t0, t1; 2221fcf5ef2aSThomas Huth 2222fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2223fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2224fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2225fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2226fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2227fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2228fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2229fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2230fcf5ef2aSThomas Huth tcg_temp_free(t1); 2231fcf5ef2aSThomas Huth tcg_temp_free(t0); 2232fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2233fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2234fcf5ef2aSThomas Huth } 2235fcf5ef2aSThomas Huth 2236fcf5ef2aSThomas Huth /* srad & srad. */ 2237fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2238fcf5ef2aSThomas Huth { 2239fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2240fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2241fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2242fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2243fcf5ef2aSThomas Huth } 2244fcf5ef2aSThomas Huth /* sradi & sradi. */ 2245fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2246fcf5ef2aSThomas Huth { 2247fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2248fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2249fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2250fcf5ef2aSThomas Huth if (sh == 0) { 2251fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2252fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2253af1c259fSSandipan Das if (is_isa300(ctx)) { 2254af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2255af1c259fSSandipan Das } 2256fcf5ef2aSThomas Huth } else { 2257fcf5ef2aSThomas Huth TCGv t0; 2258fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2259fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2260fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2261fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2262fcf5ef2aSThomas Huth tcg_temp_free(t0); 2263fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2264af1c259fSSandipan Das if (is_isa300(ctx)) { 2265af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2266af1c259fSSandipan Das } 2267fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2268fcf5ef2aSThomas Huth } 2269fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2270fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2271fcf5ef2aSThomas Huth } 2272fcf5ef2aSThomas Huth } 2273fcf5ef2aSThomas Huth 2274fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2275fcf5ef2aSThomas Huth { 2276fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2277fcf5ef2aSThomas Huth } 2278fcf5ef2aSThomas Huth 2279fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2280fcf5ef2aSThomas Huth { 2281fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2282fcf5ef2aSThomas Huth } 2283fcf5ef2aSThomas Huth 2284fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2285fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2286fcf5ef2aSThomas Huth { 2287fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2288fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2289fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2290fcf5ef2aSThomas Huth 2291fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2292fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2293fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2294fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2295fcf5ef2aSThomas Huth } 2296fcf5ef2aSThomas Huth } 2297fcf5ef2aSThomas Huth 2298fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2299fcf5ef2aSThomas Huth { 2300fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2301fcf5ef2aSThomas Huth } 2302fcf5ef2aSThomas Huth 2303fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2304fcf5ef2aSThomas Huth { 2305fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2306fcf5ef2aSThomas Huth } 2307fcf5ef2aSThomas Huth 2308fcf5ef2aSThomas Huth /* srd & srd. */ 2309fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2310fcf5ef2aSThomas Huth { 2311fcf5ef2aSThomas Huth TCGv t0, t1; 2312fcf5ef2aSThomas Huth 2313fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2314fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2315fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2316fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2317fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2318fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2319fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2320fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2321fcf5ef2aSThomas Huth tcg_temp_free(t1); 2322fcf5ef2aSThomas Huth tcg_temp_free(t0); 2323fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2324fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2325fcf5ef2aSThomas Huth } 2326fcf5ef2aSThomas Huth #endif 2327fcf5ef2aSThomas Huth 2328fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2329fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2330fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2331fcf5ef2aSThomas Huth target_long maskl) 2332fcf5ef2aSThomas Huth { 2333fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2334fcf5ef2aSThomas Huth 2335fcf5ef2aSThomas Huth simm &= ~maskl; 2336fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2337fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2338fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2339fcf5ef2aSThomas Huth } 2340fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2341fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2342fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2343fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2344fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2345fcf5ef2aSThomas Huth } 2346fcf5ef2aSThomas Huth } else { 2347fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2348fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2349fcf5ef2aSThomas Huth } else { 2350fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2351fcf5ef2aSThomas Huth } 2352fcf5ef2aSThomas Huth } 2353fcf5ef2aSThomas Huth } 2354fcf5ef2aSThomas Huth 2355fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2356fcf5ef2aSThomas Huth { 2357fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2358fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2359fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2360fcf5ef2aSThomas Huth } else { 2361fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2362fcf5ef2aSThomas Huth } 2363fcf5ef2aSThomas Huth } else { 2364fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2365fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2366fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2367fcf5ef2aSThomas Huth } 2368fcf5ef2aSThomas Huth } 2369fcf5ef2aSThomas Huth } 2370fcf5ef2aSThomas Huth 2371fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2372fcf5ef2aSThomas Huth { 2373fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2374fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2375fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2376fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2377fcf5ef2aSThomas Huth } else { 2378fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2379fcf5ef2aSThomas Huth } 2380fcf5ef2aSThomas Huth } 2381fcf5ef2aSThomas Huth 2382fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2383fcf5ef2aSThomas Huth target_long val) 2384fcf5ef2aSThomas Huth { 2385fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2386fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2387fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2388fcf5ef2aSThomas Huth } 2389fcf5ef2aSThomas Huth } 2390fcf5ef2aSThomas Huth 2391fcf5ef2aSThomas Huth static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) 2392fcf5ef2aSThomas Huth { 2393fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 2394fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2395fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2396fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, EA, mask); 2397fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 2398fcf5ef2aSThomas Huth t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); 2399fcf5ef2aSThomas Huth t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); 2400b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 2401fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t1, t2); 2402fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2403fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2404fcf5ef2aSThomas Huth gen_set_label(l1); 2405fcf5ef2aSThomas Huth tcg_temp_free(t0); 2406fcf5ef2aSThomas Huth } 2407fcf5ef2aSThomas Huth 2408fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2409fcf5ef2aSThomas Huth { 2410fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2411fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2412fcf5ef2aSThomas Huth } 2413fcf5ef2aSThomas Huth 2414fcf5ef2aSThomas Huth /*** Integer load ***/ 2415fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2416fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2417fcf5ef2aSThomas Huth 2418fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2419fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2420fcf5ef2aSThomas Huth TCGv val, \ 2421fcf5ef2aSThomas Huth TCGv addr) \ 2422fcf5ef2aSThomas Huth { \ 2423fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2424fcf5ef2aSThomas Huth } 2425fcf5ef2aSThomas Huth 2426fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2427fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2428fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2429fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2430fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2431fcf5ef2aSThomas Huth 2432fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2433fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2434fcf5ef2aSThomas Huth 2435fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2436fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2437fcf5ef2aSThomas Huth TCGv_i64 val, \ 2438fcf5ef2aSThomas Huth TCGv addr) \ 2439fcf5ef2aSThomas Huth { \ 2440fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2441fcf5ef2aSThomas Huth } 2442fcf5ef2aSThomas Huth 2443fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2444fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2445fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2446fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2447fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2448fcf5ef2aSThomas Huth 2449fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2450fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2451fcf5ef2aSThomas Huth #endif 2452fcf5ef2aSThomas Huth 2453fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2454fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2455fcf5ef2aSThomas Huth TCGv val, \ 2456fcf5ef2aSThomas Huth TCGv addr) \ 2457fcf5ef2aSThomas Huth { \ 2458fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2459fcf5ef2aSThomas Huth } 2460fcf5ef2aSThomas Huth 2461fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2462fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2463fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2464fcf5ef2aSThomas Huth 2465fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2466fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2467fcf5ef2aSThomas Huth 2468fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2469fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2470fcf5ef2aSThomas Huth TCGv_i64 val, \ 2471fcf5ef2aSThomas Huth TCGv addr) \ 2472fcf5ef2aSThomas Huth { \ 2473fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2474fcf5ef2aSThomas Huth } 2475fcf5ef2aSThomas Huth 2476fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2477fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2478fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2479fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2480fcf5ef2aSThomas Huth 2481fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2482fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2483fcf5ef2aSThomas Huth #endif 2484fcf5ef2aSThomas Huth 2485fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2486fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2487fcf5ef2aSThomas Huth { \ 2488fcf5ef2aSThomas Huth TCGv EA; \ 2489fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2490fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2491fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2492fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2493fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2494fcf5ef2aSThomas Huth } 2495fcf5ef2aSThomas Huth 2496fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2497fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2498fcf5ef2aSThomas Huth { \ 2499fcf5ef2aSThomas Huth TCGv EA; \ 2500fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2501fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2502fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2503fcf5ef2aSThomas Huth return; \ 2504fcf5ef2aSThomas Huth } \ 2505fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2506fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2507fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2508fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2509fcf5ef2aSThomas Huth else \ 2510fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2511fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2512fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2513fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2514fcf5ef2aSThomas Huth } 2515fcf5ef2aSThomas Huth 2516fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2517fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2518fcf5ef2aSThomas Huth { \ 2519fcf5ef2aSThomas Huth TCGv EA; \ 2520fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2521fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2522fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2523fcf5ef2aSThomas Huth return; \ 2524fcf5ef2aSThomas Huth } \ 2525fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2526fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2527fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2528fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2529fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2530fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2531fcf5ef2aSThomas Huth } 2532fcf5ef2aSThomas Huth 2533fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2534fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2535fcf5ef2aSThomas Huth { \ 2536fcf5ef2aSThomas Huth TCGv EA; \ 2537fcf5ef2aSThomas Huth chk; \ 2538fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2539fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2540fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2541fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2542fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2543fcf5ef2aSThomas Huth } 2544fcf5ef2aSThomas Huth 2545fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2546fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2547fcf5ef2aSThomas Huth 2548fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2549fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2550fcf5ef2aSThomas Huth 2551fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2552fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2553fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2554fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2555fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2556fcf5ef2aSThomas Huth 2557fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2558fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2559fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2560fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2561fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2562fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2563fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2564fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2565fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2566fcf5ef2aSThomas Huth /* lwaux */ 2567fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2568fcf5ef2aSThomas Huth /* lwax */ 2569fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2570fcf5ef2aSThomas Huth /* ldux */ 2571fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2572fcf5ef2aSThomas Huth /* ldx */ 2573fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2574fcf5ef2aSThomas Huth 2575fcf5ef2aSThomas Huth /* CI load/store variants */ 2576fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2577fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2578fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2579fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2580fcf5ef2aSThomas Huth 2581fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2582fcf5ef2aSThomas Huth { 2583fcf5ef2aSThomas Huth TCGv EA; 2584fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2585fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2586fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2587fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2588fcf5ef2aSThomas Huth return; 2589fcf5ef2aSThomas Huth } 2590fcf5ef2aSThomas Huth } 2591fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2592fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2593fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2594fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2595fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2596fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2597fcf5ef2aSThomas Huth } else { 2598fcf5ef2aSThomas Huth /* ld - ldu */ 2599fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2600fcf5ef2aSThomas Huth } 2601fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2602fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2603fcf5ef2aSThomas Huth tcg_temp_free(EA); 2604fcf5ef2aSThomas Huth } 2605fcf5ef2aSThomas Huth 2606fcf5ef2aSThomas Huth /* lq */ 2607fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2608fcf5ef2aSThomas Huth { 2609fcf5ef2aSThomas Huth int ra, rd; 2610fcf5ef2aSThomas Huth TCGv EA; 2611fcf5ef2aSThomas Huth 2612fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2613fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2614fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2615fcf5ef2aSThomas Huth 2616fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2617fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2618fcf5ef2aSThomas Huth return; 2619fcf5ef2aSThomas Huth } 2620fcf5ef2aSThomas Huth 2621fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2622fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2623fcf5ef2aSThomas Huth return; 2624fcf5ef2aSThomas Huth } 2625fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2626fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2627fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2628fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2629fcf5ef2aSThomas Huth return; 2630fcf5ef2aSThomas Huth } 2631fcf5ef2aSThomas Huth 2632fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2633fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2634fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2635fcf5ef2aSThomas Huth 2636fcf5ef2aSThomas Huth /* We only need to swap high and low halves. gen_qemu_ld64_i64 does 2637fcf5ef2aSThomas Huth necessary 64-bit byteswap already. */ 2638fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 2639fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2640fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2641fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2642fcf5ef2aSThomas Huth } else { 2643fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2644fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2645fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2646fcf5ef2aSThomas Huth } 2647fcf5ef2aSThomas Huth tcg_temp_free(EA); 2648fcf5ef2aSThomas Huth } 2649fcf5ef2aSThomas Huth #endif 2650fcf5ef2aSThomas Huth 2651fcf5ef2aSThomas Huth /*** Integer store ***/ 2652fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2653fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2654fcf5ef2aSThomas Huth { \ 2655fcf5ef2aSThomas Huth TCGv EA; \ 2656fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2657fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2658fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2659fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2660fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2661fcf5ef2aSThomas Huth } 2662fcf5ef2aSThomas Huth 2663fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2664fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2665fcf5ef2aSThomas Huth { \ 2666fcf5ef2aSThomas Huth TCGv EA; \ 2667fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2668fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2669fcf5ef2aSThomas Huth return; \ 2670fcf5ef2aSThomas Huth } \ 2671fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2672fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2673fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2674fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2675fcf5ef2aSThomas Huth else \ 2676fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2677fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2678fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2679fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2680fcf5ef2aSThomas Huth } 2681fcf5ef2aSThomas Huth 2682fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2683fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2684fcf5ef2aSThomas Huth { \ 2685fcf5ef2aSThomas Huth TCGv EA; \ 2686fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2687fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2688fcf5ef2aSThomas Huth return; \ 2689fcf5ef2aSThomas Huth } \ 2690fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2691fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2692fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2693fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2694fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2695fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2696fcf5ef2aSThomas Huth } 2697fcf5ef2aSThomas Huth 2698fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2699fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2700fcf5ef2aSThomas Huth { \ 2701fcf5ef2aSThomas Huth TCGv EA; \ 2702fcf5ef2aSThomas Huth chk; \ 2703fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2704fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2705fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2706fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2707fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2708fcf5ef2aSThomas Huth } 2709fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2710fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2711fcf5ef2aSThomas Huth 2712fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2713fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2714fcf5ef2aSThomas Huth 2715fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2716fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2717fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2718fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2719fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2720fcf5ef2aSThomas Huth 2721fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2722fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2723fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2724fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2725fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2726fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2727fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2728fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2729fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2730fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2731fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2732fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2733fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2734fcf5ef2aSThomas Huth 2735fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2736fcf5ef2aSThomas Huth { 2737fcf5ef2aSThomas Huth int rs; 2738fcf5ef2aSThomas Huth TCGv EA; 2739fcf5ef2aSThomas Huth 2740fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2741fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2742fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2743fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2744fcf5ef2aSThomas Huth 2745fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2746fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2747fcf5ef2aSThomas Huth } 2748fcf5ef2aSThomas Huth 2749fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2750fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2751fcf5ef2aSThomas Huth return; 2752fcf5ef2aSThomas Huth } 2753fcf5ef2aSThomas Huth 2754fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2755fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2756fcf5ef2aSThomas Huth return; 2757fcf5ef2aSThomas Huth } 2758fcf5ef2aSThomas Huth 2759fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2760fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2761fcf5ef2aSThomas Huth return; 2762fcf5ef2aSThomas Huth } 2763fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2764fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2765fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2766fcf5ef2aSThomas Huth 2767fcf5ef2aSThomas Huth /* We only need to swap high and low halves. gen_qemu_st64_i64 does 2768fcf5ef2aSThomas Huth necessary 64-bit byteswap already. */ 2769fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 2770fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2771fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2772fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2773fcf5ef2aSThomas Huth } else { 2774fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2775fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2776fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2777fcf5ef2aSThomas Huth } 2778fcf5ef2aSThomas Huth tcg_temp_free(EA); 2779fcf5ef2aSThomas Huth } else { 2780fcf5ef2aSThomas Huth /* std / stdu*/ 2781fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2782fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2783fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2784fcf5ef2aSThomas Huth return; 2785fcf5ef2aSThomas Huth } 2786fcf5ef2aSThomas Huth } 2787fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2788fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2789fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2790fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2791fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2792fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2793fcf5ef2aSThomas Huth tcg_temp_free(EA); 2794fcf5ef2aSThomas Huth } 2795fcf5ef2aSThomas Huth } 2796fcf5ef2aSThomas Huth #endif 2797fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2798fcf5ef2aSThomas Huth 2799fcf5ef2aSThomas Huth /* lhbrx */ 2800fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2801fcf5ef2aSThomas Huth 2802fcf5ef2aSThomas Huth /* lwbrx */ 2803fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2804fcf5ef2aSThomas Huth 2805fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2806fcf5ef2aSThomas Huth /* ldbrx */ 2807fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2808fcf5ef2aSThomas Huth /* stdbrx */ 2809fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2810fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2811fcf5ef2aSThomas Huth 2812fcf5ef2aSThomas Huth /* sthbrx */ 2813fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2814fcf5ef2aSThomas Huth /* stwbrx */ 2815fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2816fcf5ef2aSThomas Huth 2817fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2818fcf5ef2aSThomas Huth 2819fcf5ef2aSThomas Huth /* lmw */ 2820fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2821fcf5ef2aSThomas Huth { 2822fcf5ef2aSThomas Huth TCGv t0; 2823fcf5ef2aSThomas Huth TCGv_i32 t1; 2824fcf5ef2aSThomas Huth 2825fcf5ef2aSThomas Huth if (ctx->le_mode) { 2826fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2827fcf5ef2aSThomas Huth return; 2828fcf5ef2aSThomas Huth } 2829fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2830fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2831fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2832fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2833fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2834fcf5ef2aSThomas Huth tcg_temp_free(t0); 2835fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2836fcf5ef2aSThomas Huth } 2837fcf5ef2aSThomas Huth 2838fcf5ef2aSThomas Huth /* stmw */ 2839fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2840fcf5ef2aSThomas Huth { 2841fcf5ef2aSThomas Huth TCGv t0; 2842fcf5ef2aSThomas Huth TCGv_i32 t1; 2843fcf5ef2aSThomas Huth 2844fcf5ef2aSThomas Huth if (ctx->le_mode) { 2845fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2846fcf5ef2aSThomas Huth return; 2847fcf5ef2aSThomas Huth } 2848fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2849fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2850fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2851fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2852fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2853fcf5ef2aSThomas Huth tcg_temp_free(t0); 2854fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2855fcf5ef2aSThomas Huth } 2856fcf5ef2aSThomas Huth 2857fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2858fcf5ef2aSThomas Huth 2859fcf5ef2aSThomas Huth /* lswi */ 2860fcf5ef2aSThomas Huth /* PowerPC32 specification says we must generate an exception if 2861fcf5ef2aSThomas Huth * rA is in the range of registers to be loaded. 2862fcf5ef2aSThomas Huth * In an other hand, IBM says this is valid, but rA won't be loaded. 2863fcf5ef2aSThomas Huth * For now, I'll follow the spec... 2864fcf5ef2aSThomas Huth */ 2865fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2866fcf5ef2aSThomas Huth { 2867fcf5ef2aSThomas Huth TCGv t0; 2868fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2869fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2870fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2871fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2872fcf5ef2aSThomas Huth int nr; 2873fcf5ef2aSThomas Huth 2874fcf5ef2aSThomas Huth if (ctx->le_mode) { 2875fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2876fcf5ef2aSThomas Huth return; 2877fcf5ef2aSThomas Huth } 2878fcf5ef2aSThomas Huth if (nb == 0) 2879fcf5ef2aSThomas Huth nb = 32; 2880f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 2881fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2882fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2883fcf5ef2aSThomas Huth return; 2884fcf5ef2aSThomas Huth } 2885fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2886fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2887fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2888fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2889fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 2890fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 2891fcf5ef2aSThomas Huth tcg_temp_free(t0); 2892fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2893fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2894fcf5ef2aSThomas Huth } 2895fcf5ef2aSThomas Huth 2896fcf5ef2aSThomas Huth /* lswx */ 2897fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 2898fcf5ef2aSThomas Huth { 2899fcf5ef2aSThomas Huth TCGv t0; 2900fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 2901fcf5ef2aSThomas Huth 2902fcf5ef2aSThomas Huth if (ctx->le_mode) { 2903fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2904fcf5ef2aSThomas Huth return; 2905fcf5ef2aSThomas Huth } 2906fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2907fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2908fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2909fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2910fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 2911fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 2912fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2913fcf5ef2aSThomas Huth tcg_temp_free(t0); 2914fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2915fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2916fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2917fcf5ef2aSThomas Huth } 2918fcf5ef2aSThomas Huth 2919fcf5ef2aSThomas Huth /* stswi */ 2920fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 2921fcf5ef2aSThomas Huth { 2922fcf5ef2aSThomas Huth TCGv t0; 2923fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2924fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2925fcf5ef2aSThomas Huth 2926fcf5ef2aSThomas Huth if (ctx->le_mode) { 2927fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2928fcf5ef2aSThomas Huth return; 2929fcf5ef2aSThomas Huth } 2930fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2931fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2932fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2933fcf5ef2aSThomas Huth if (nb == 0) 2934fcf5ef2aSThomas Huth nb = 32; 2935fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2936fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2937fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2938fcf5ef2aSThomas Huth tcg_temp_free(t0); 2939fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2940fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2941fcf5ef2aSThomas Huth } 2942fcf5ef2aSThomas Huth 2943fcf5ef2aSThomas Huth /* stswx */ 2944fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 2945fcf5ef2aSThomas Huth { 2946fcf5ef2aSThomas Huth TCGv t0; 2947fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2948fcf5ef2aSThomas Huth 2949fcf5ef2aSThomas Huth if (ctx->le_mode) { 2950fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2951fcf5ef2aSThomas Huth return; 2952fcf5ef2aSThomas Huth } 2953fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2954fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2955fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2956fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 2957fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 2958fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 2959fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2960fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2961fcf5ef2aSThomas Huth tcg_temp_free(t0); 2962fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2963fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2964fcf5ef2aSThomas Huth } 2965fcf5ef2aSThomas Huth 2966fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 2967fcf5ef2aSThomas Huth /* eieio */ 2968fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 2969fcf5ef2aSThomas Huth { 2970*c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 2971*c8fd8373SCédric Le Goater 2972*c8fd8373SCédric Le Goater /* 2973*c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 2974*c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 2975*c8fd8373SCédric Le Goater */ 2976*c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 2977*c8fd8373SCédric Le Goater /* 2978*c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 2979*c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 2980*c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 2981*c8fd8373SCédric Le Goater * complain to the user. 2982*c8fd8373SCédric Le Goater */ 2983*c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 2984*c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 2985*c8fd8373SCédric Le Goater TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 2986*c8fd8373SCédric Le Goater } else { 2987*c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 2988*c8fd8373SCédric Le Goater } 2989*c8fd8373SCédric Le Goater } 2990*c8fd8373SCédric Le Goater 2991*c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 2992fcf5ef2aSThomas Huth } 2993fcf5ef2aSThomas Huth 2994fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2995fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2996fcf5ef2aSThomas Huth { 2997fcf5ef2aSThomas Huth TCGv_i32 t; 2998fcf5ef2aSThomas Huth TCGLabel *l; 2999fcf5ef2aSThomas Huth 3000fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3001fcf5ef2aSThomas Huth return; 3002fcf5ef2aSThomas Huth } 3003fcf5ef2aSThomas Huth l = gen_new_label(); 3004fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3005fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3006fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3007fcf5ef2aSThomas Huth if (global) { 3008fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3009fcf5ef2aSThomas Huth } else { 3010fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3011fcf5ef2aSThomas Huth } 3012fcf5ef2aSThomas Huth gen_set_label(l); 3013fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3014fcf5ef2aSThomas Huth } 3015fcf5ef2aSThomas Huth #else 3016fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3017fcf5ef2aSThomas Huth #endif 3018fcf5ef2aSThomas Huth 3019fcf5ef2aSThomas Huth /* isync */ 3020fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3021fcf5ef2aSThomas Huth { 3022fcf5ef2aSThomas Huth /* 3023fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3024fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3025fcf5ef2aSThomas Huth */ 3026fcf5ef2aSThomas Huth if (!ctx->pr) { 3027fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3028fcf5ef2aSThomas Huth } 30294771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3030fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3031fcf5ef2aSThomas Huth } 3032fcf5ef2aSThomas Huth 3033fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3034fcf5ef2aSThomas Huth 3035fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3036fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3037fcf5ef2aSThomas Huth { \ 3038fcf5ef2aSThomas Huth TCGv t0; \ 3039fcf5ef2aSThomas Huth TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ 3040fcf5ef2aSThomas Huth int len = MEMOP_GET_SIZE(memop); \ 3041fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); \ 3042fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); \ 3043fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); \ 3044fcf5ef2aSThomas Huth if ((len) > 1) { \ 3045fcf5ef2aSThomas Huth gen_check_align(ctx, t0, (len)-1); \ 3046fcf5ef2aSThomas Huth } \ 3047fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ 3048fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, t0); \ 3049253ce7b2SNikunj A Dadhania tcg_gen_mov_tl(cpu_reserve_val, gpr); \ 30504771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \ 3051fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 3052fcf5ef2aSThomas Huth } 3053fcf5ef2aSThomas Huth 3054fcf5ef2aSThomas Huth /* lwarx */ 3055fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3056fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3057fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3058fcf5ef2aSThomas Huth 3059a68a6146SBalamuruhan S #define LD_ATOMIC(name, memop, tp, op, eop) \ 3060a68a6146SBalamuruhan S static void gen_##name(DisasContext *ctx) \ 3061a68a6146SBalamuruhan S { \ 3062a68a6146SBalamuruhan S int len = MEMOP_GET_SIZE(memop); \ 3063a68a6146SBalamuruhan S uint32_t gpr_FC = FC(ctx->opcode); \ 3064a68a6146SBalamuruhan S TCGv EA = tcg_temp_local_new(); \ 3065a68a6146SBalamuruhan S TCGv_##tp t0, t1; \ 3066a68a6146SBalamuruhan S \ 3067a68a6146SBalamuruhan S gen_addr_register(ctx, EA); \ 3068a68a6146SBalamuruhan S if (len > 1) { \ 3069a68a6146SBalamuruhan S gen_check_align(ctx, EA, len - 1); \ 3070a68a6146SBalamuruhan S } \ 3071a68a6146SBalamuruhan S t0 = tcg_temp_new_##tp(); \ 3072a68a6146SBalamuruhan S t1 = tcg_temp_new_##tp(); \ 3073a68a6146SBalamuruhan S tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3074a68a6146SBalamuruhan S \ 3075a68a6146SBalamuruhan S switch (gpr_FC) { \ 3076a68a6146SBalamuruhan S case 0: /* Fetch and add */ \ 3077a68a6146SBalamuruhan S tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3078a68a6146SBalamuruhan S break; \ 3079a68a6146SBalamuruhan S case 1: /* Fetch and xor */ \ 3080a68a6146SBalamuruhan S tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3081a68a6146SBalamuruhan S break; \ 3082a68a6146SBalamuruhan S case 2: /* Fetch and or */ \ 3083a68a6146SBalamuruhan S tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3084a68a6146SBalamuruhan S break; \ 3085a68a6146SBalamuruhan S case 3: /* Fetch and 'and' */ \ 3086a68a6146SBalamuruhan S tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3087a68a6146SBalamuruhan S break; \ 3088a68a6146SBalamuruhan S case 8: /* Swap */ \ 3089a68a6146SBalamuruhan S tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3090a68a6146SBalamuruhan S break; \ 3091a68a6146SBalamuruhan S case 4: /* Fetch and max unsigned */ \ 3092a68a6146SBalamuruhan S case 5: /* Fetch and max signed */ \ 3093a68a6146SBalamuruhan S case 6: /* Fetch and min unsigned */ \ 3094a68a6146SBalamuruhan S case 7: /* Fetch and min signed */ \ 3095a68a6146SBalamuruhan S case 16: /* compare and swap not equal */ \ 3096a68a6146SBalamuruhan S case 24: /* Fetch and increment bounded */ \ 3097a68a6146SBalamuruhan S case 25: /* Fetch and increment equal */ \ 3098a68a6146SBalamuruhan S case 28: /* Fetch and decrement bounded */ \ 3099a68a6146SBalamuruhan S gen_invalid(ctx); \ 3100a68a6146SBalamuruhan S break; \ 3101a68a6146SBalamuruhan S default: \ 3102a68a6146SBalamuruhan S /* invoke data storage error handler */ \ 3103a68a6146SBalamuruhan S gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3104a68a6146SBalamuruhan S } \ 3105a68a6146SBalamuruhan S tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ 3106a68a6146SBalamuruhan S tcg_temp_free_##tp(t0); \ 3107a68a6146SBalamuruhan S tcg_temp_free_##tp(t1); \ 3108a68a6146SBalamuruhan S tcg_temp_free(EA); \ 3109a68a6146SBalamuruhan S } 3110a68a6146SBalamuruhan S 3111a68a6146SBalamuruhan S LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) 3112a68a6146SBalamuruhan S #if defined(TARGET_PPC64) 3113a68a6146SBalamuruhan S LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) 3114a68a6146SBalamuruhan S #endif 3115a68a6146SBalamuruhan S 3116a3401188SBalamuruhan S #define ST_ATOMIC(name, memop, tp, op) \ 3117a3401188SBalamuruhan S static void gen_##name(DisasContext *ctx) \ 3118a3401188SBalamuruhan S { \ 3119a3401188SBalamuruhan S int len = MEMOP_GET_SIZE(memop); \ 3120a3401188SBalamuruhan S uint32_t gpr_FC = FC(ctx->opcode); \ 3121a3401188SBalamuruhan S TCGv EA = tcg_temp_local_new(); \ 3122a3401188SBalamuruhan S TCGv_##tp t0, t1; \ 3123a3401188SBalamuruhan S \ 3124a3401188SBalamuruhan S gen_addr_register(ctx, EA); \ 3125a3401188SBalamuruhan S if (len > 1) { \ 3126a3401188SBalamuruhan S gen_check_align(ctx, EA, len - 1); \ 3127a3401188SBalamuruhan S } \ 3128a3401188SBalamuruhan S t0 = tcg_temp_new_##tp(); \ 3129a3401188SBalamuruhan S t1 = tcg_temp_new_##tp(); \ 3130a3401188SBalamuruhan S tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3131a3401188SBalamuruhan S \ 3132a3401188SBalamuruhan S switch (gpr_FC) { \ 3133a3401188SBalamuruhan S case 0: /* add and Store */ \ 3134a3401188SBalamuruhan S tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3135a3401188SBalamuruhan S break; \ 3136a3401188SBalamuruhan S case 1: /* xor and Store */ \ 3137a3401188SBalamuruhan S tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3138a3401188SBalamuruhan S break; \ 3139a3401188SBalamuruhan S case 2: /* Or and Store */ \ 3140a3401188SBalamuruhan S tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3141a3401188SBalamuruhan S break; \ 3142a3401188SBalamuruhan S case 3: /* 'and' and Store */ \ 3143a3401188SBalamuruhan S tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3144a3401188SBalamuruhan S break; \ 3145a3401188SBalamuruhan S case 4: /* Store max unsigned */ \ 3146a3401188SBalamuruhan S case 5: /* Store max signed */ \ 3147a3401188SBalamuruhan S case 6: /* Store min unsigned */ \ 3148a3401188SBalamuruhan S case 7: /* Store min signed */ \ 3149a3401188SBalamuruhan S case 24: /* Store twin */ \ 3150a3401188SBalamuruhan S gen_invalid(ctx); \ 3151a3401188SBalamuruhan S break; \ 3152a3401188SBalamuruhan S default: \ 3153a3401188SBalamuruhan S /* invoke data storage error handler */ \ 3154a3401188SBalamuruhan S gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3155a3401188SBalamuruhan S } \ 3156a3401188SBalamuruhan S tcg_temp_free_##tp(t0); \ 3157a3401188SBalamuruhan S tcg_temp_free_##tp(t1); \ 3158a3401188SBalamuruhan S tcg_temp_free(EA); \ 3159a3401188SBalamuruhan S } 3160a3401188SBalamuruhan S 3161a3401188SBalamuruhan S ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) 3162a3401188SBalamuruhan S #if defined(TARGET_PPC64) 3163a3401188SBalamuruhan S ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) 3164a3401188SBalamuruhan S #endif 3165a3401188SBalamuruhan S 3166fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3167fcf5ef2aSThomas Huth static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3168fcf5ef2aSThomas Huth int reg, int memop) 3169fcf5ef2aSThomas Huth { 3170fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3171fcf5ef2aSThomas Huth 3172fcf5ef2aSThomas Huth tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); 3173fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); 3174fcf5ef2aSThomas Huth tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); 3175fcf5ef2aSThomas Huth tcg_temp_free(t0); 3176fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); 3177fcf5ef2aSThomas Huth } 3178fcf5ef2aSThomas Huth #else 3179fcf5ef2aSThomas Huth static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3180fcf5ef2aSThomas Huth int reg, int memop) 3181fcf5ef2aSThomas Huth { 3182253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3183253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3184253ce7b2SNikunj A Dadhania TCGv t0; 3185fcf5ef2aSThomas Huth 3186fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3187253ce7b2SNikunj A Dadhania 3188253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3189253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3190253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3191253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3192253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3193253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3194253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3195253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3196253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3197253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3198253ce7b2SNikunj A Dadhania 3199fcf5ef2aSThomas Huth gen_set_label(l1); 32004771df23SNikunj A Dadhania 32014771df23SNikunj A Dadhania /* Address mismatch implies failure. But we still need to provide the 32024771df23SNikunj A Dadhania memory barrier semantics of the instruction. */ 32034771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3204253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3205253ce7b2SNikunj A Dadhania 3206253ce7b2SNikunj A Dadhania gen_set_label(l2); 3207fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3208fcf5ef2aSThomas Huth } 3209fcf5ef2aSThomas Huth #endif 3210fcf5ef2aSThomas Huth 3211fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3212fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3213fcf5ef2aSThomas Huth { \ 3214fcf5ef2aSThomas Huth TCGv t0; \ 3215fcf5ef2aSThomas Huth int len = MEMOP_GET_SIZE(memop); \ 3216fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); \ 3217fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); \ 3218fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); \ 3219fcf5ef2aSThomas Huth if (len > 1) { \ 3220fcf5ef2aSThomas Huth gen_check_align(ctx, t0, (len) - 1); \ 3221fcf5ef2aSThomas Huth } \ 3222fcf5ef2aSThomas Huth gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ 3223fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 3224fcf5ef2aSThomas Huth } 3225fcf5ef2aSThomas Huth 3226fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3227fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3228fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3229fcf5ef2aSThomas Huth 3230fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3231fcf5ef2aSThomas Huth /* ldarx */ 3232fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3233fcf5ef2aSThomas Huth /* stdcx. */ 3234fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3235fcf5ef2aSThomas Huth 3236fcf5ef2aSThomas Huth /* lqarx */ 3237fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3238fcf5ef2aSThomas Huth { 3239fcf5ef2aSThomas Huth TCGv EA; 3240fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 3241fcf5ef2aSThomas Huth TCGv gpr1, gpr2; 3242fcf5ef2aSThomas Huth 3243fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3244fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3245fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3246fcf5ef2aSThomas Huth return; 3247fcf5ef2aSThomas Huth } 3248fcf5ef2aSThomas Huth 3249fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 3250fcf5ef2aSThomas Huth EA = tcg_temp_local_new(); 3251fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3252fcf5ef2aSThomas Huth gen_check_align(ctx, EA, 15); 3253fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 3254fcf5ef2aSThomas Huth gpr1 = cpu_gpr[rd+1]; 3255fcf5ef2aSThomas Huth gpr2 = cpu_gpr[rd]; 3256fcf5ef2aSThomas Huth } else { 3257fcf5ef2aSThomas Huth gpr1 = cpu_gpr[rd]; 3258fcf5ef2aSThomas Huth gpr2 = cpu_gpr[rd+1]; 3259fcf5ef2aSThomas Huth } 3260fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3261fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3262fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3263fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3264fcf5ef2aSThomas Huth 3265fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); 3266fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3267fcf5ef2aSThomas Huth tcg_temp_free(EA); 3268fcf5ef2aSThomas Huth } 3269fcf5ef2aSThomas Huth 3270fcf5ef2aSThomas Huth /* stqcx. */ 3271fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3272fcf5ef2aSThomas Huth { 3273fcf5ef2aSThomas Huth TCGv EA; 3274fcf5ef2aSThomas Huth int reg = rS(ctx->opcode); 3275fcf5ef2aSThomas Huth int len = 16; 3276fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3277fcf5ef2aSThomas Huth TCGLabel *l1; 3278fcf5ef2aSThomas Huth TCGv gpr1, gpr2; 3279fcf5ef2aSThomas Huth #endif 3280fcf5ef2aSThomas Huth 3281fcf5ef2aSThomas Huth if (unlikely((rD(ctx->opcode) & 1))) { 3282fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3283fcf5ef2aSThomas Huth return; 3284fcf5ef2aSThomas Huth } 3285fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 3286fcf5ef2aSThomas Huth EA = tcg_temp_local_new(); 3287fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3288fcf5ef2aSThomas Huth if (len > 1) { 3289fcf5ef2aSThomas Huth gen_check_align(ctx, EA, (len) - 1); 3290fcf5ef2aSThomas Huth } 3291fcf5ef2aSThomas Huth 3292fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3293fcf5ef2aSThomas Huth gen_conditional_store(ctx, EA, reg, 16); 3294fcf5ef2aSThomas Huth #else 3295fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3296fcf5ef2aSThomas Huth l1 = gen_new_label(); 3297fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3298efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3299fcf5ef2aSThomas Huth 3300fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 3301fcf5ef2aSThomas Huth gpr1 = cpu_gpr[reg + 1]; 3302fcf5ef2aSThomas Huth gpr2 = cpu_gpr[reg]; 3303fcf5ef2aSThomas Huth } else { 3304fcf5ef2aSThomas Huth gpr1 = cpu_gpr[reg]; 3305fcf5ef2aSThomas Huth gpr2 = cpu_gpr[reg + 1]; 3306fcf5ef2aSThomas Huth } 3307fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3308fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3309fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3310fcf5ef2aSThomas Huth 3311fcf5ef2aSThomas Huth gen_set_label(l1); 3312fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3313fcf5ef2aSThomas Huth #endif 3314fcf5ef2aSThomas Huth tcg_temp_free(EA); 3315fcf5ef2aSThomas Huth } 3316fcf5ef2aSThomas Huth 3317fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3318fcf5ef2aSThomas Huth 3319fcf5ef2aSThomas Huth /* sync */ 3320fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3321fcf5ef2aSThomas Huth { 3322fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3323fcf5ef2aSThomas Huth 3324fcf5ef2aSThomas Huth /* 3325fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3326fcf5ef2aSThomas Huth * 3327fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3328fcf5ef2aSThomas Huth * 3329fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3330fcf5ef2aSThomas Huth * check MSR_PR as well. 3331fcf5ef2aSThomas Huth */ 3332fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3333fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3334fcf5ef2aSThomas Huth } 33354771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3336fcf5ef2aSThomas Huth } 3337fcf5ef2aSThomas Huth 3338fcf5ef2aSThomas Huth /* wait */ 3339fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3340fcf5ef2aSThomas Huth { 3341fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3342fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3343fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3344fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3345fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3346b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3347fcf5ef2aSThomas Huth } 3348fcf5ef2aSThomas Huth 3349fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3350fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3351fcf5ef2aSThomas Huth { 3352fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3353fcf5ef2aSThomas Huth GEN_PRIV; 3354fcf5ef2aSThomas Huth #else 3355fcf5ef2aSThomas Huth TCGv_i32 t; 3356fcf5ef2aSThomas Huth 3357fcf5ef2aSThomas Huth CHK_HV; 3358fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3359fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3360fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3361fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3362fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3363fcf5ef2aSThomas Huth } 3364fcf5ef2aSThomas Huth 3365fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3366fcf5ef2aSThomas Huth { 3367fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3368fcf5ef2aSThomas Huth GEN_PRIV; 3369fcf5ef2aSThomas Huth #else 3370fcf5ef2aSThomas Huth TCGv_i32 t; 3371fcf5ef2aSThomas Huth 3372fcf5ef2aSThomas Huth CHK_HV; 3373fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3374fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3375fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3376fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3377fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3378fcf5ef2aSThomas Huth } 3379fcf5ef2aSThomas Huth 3380cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3381cdee0e72SNikunj A Dadhania { 3382cdee0e72SNikunj A Dadhania gen_nap(ctx); 3383cdee0e72SNikunj A Dadhania } 3384cdee0e72SNikunj A Dadhania 3385fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3386fcf5ef2aSThomas Huth { 3387fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3388fcf5ef2aSThomas Huth GEN_PRIV; 3389fcf5ef2aSThomas Huth #else 3390fcf5ef2aSThomas Huth TCGv_i32 t; 3391fcf5ef2aSThomas Huth 3392fcf5ef2aSThomas Huth CHK_HV; 3393fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3394fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3395fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3396fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3397fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3398fcf5ef2aSThomas Huth } 3399fcf5ef2aSThomas Huth 3400fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3401fcf5ef2aSThomas Huth { 3402fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3403fcf5ef2aSThomas Huth GEN_PRIV; 3404fcf5ef2aSThomas Huth #else 3405fcf5ef2aSThomas Huth TCGv_i32 t; 3406fcf5ef2aSThomas Huth 3407fcf5ef2aSThomas Huth CHK_HV; 3408fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3409fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3410fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3411fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3412fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3413fcf5ef2aSThomas Huth } 3414fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3415fcf5ef2aSThomas Huth 3416fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3417fcf5ef2aSThomas Huth { 3418fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3419fcf5ef2aSThomas Huth if (ctx->has_cfar) 3420fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3421fcf5ef2aSThomas Huth #endif 3422fcf5ef2aSThomas Huth } 3423fcf5ef2aSThomas Huth 3424fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3425fcf5ef2aSThomas Huth { 3426fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3427fcf5ef2aSThomas Huth return false; 3428fcf5ef2aSThomas Huth } 3429fcf5ef2aSThomas Huth 3430fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3431b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3432fcf5ef2aSThomas Huth #else 3433fcf5ef2aSThomas Huth return true; 3434fcf5ef2aSThomas Huth #endif 3435fcf5ef2aSThomas Huth } 3436fcf5ef2aSThomas Huth 3437fcf5ef2aSThomas Huth /*** Branch ***/ 3438c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3439fcf5ef2aSThomas Huth { 3440fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3441fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3442fcf5ef2aSThomas Huth } 3443fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3444fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3445fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 344607ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 3447fcf5ef2aSThomas Huth } else { 3448fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 3449fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3450fcf5ef2aSThomas Huth if ((ctx->singlestep_enabled & 3451fcf5ef2aSThomas Huth (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && 3452fcf5ef2aSThomas Huth (ctx->exception == POWERPC_EXCP_BRANCH || 3453fcf5ef2aSThomas Huth ctx->exception == POWERPC_EXCP_TRACE)) { 3454fcf5ef2aSThomas Huth gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); 3455fcf5ef2aSThomas Huth } 3456fcf5ef2aSThomas Huth if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { 3457fcf5ef2aSThomas Huth gen_debug_exception(ctx); 3458fcf5ef2aSThomas Huth } 3459fcf5ef2aSThomas Huth } 3460c4a2e3a9SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 3461fcf5ef2aSThomas Huth } 3462fcf5ef2aSThomas Huth } 3463fcf5ef2aSThomas Huth 3464fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3465fcf5ef2aSThomas Huth { 3466fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3467fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3468fcf5ef2aSThomas Huth } 3469fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3470fcf5ef2aSThomas Huth } 3471fcf5ef2aSThomas Huth 3472fcf5ef2aSThomas Huth /* b ba bl bla */ 3473fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3474fcf5ef2aSThomas Huth { 3475fcf5ef2aSThomas Huth target_ulong li, target; 3476fcf5ef2aSThomas Huth 3477fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3478fcf5ef2aSThomas Huth /* sign extend LI */ 3479fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3480fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3481fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3482b6bac4bcSEmilio G. Cota target = ctx->base.pc_next + li - 4; 3483fcf5ef2aSThomas Huth } else { 3484fcf5ef2aSThomas Huth target = li; 3485fcf5ef2aSThomas Huth } 3486fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3487b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3488fcf5ef2aSThomas Huth } 3489b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3490fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3491fcf5ef2aSThomas Huth } 3492fcf5ef2aSThomas Huth 3493fcf5ef2aSThomas Huth #define BCOND_IM 0 3494fcf5ef2aSThomas Huth #define BCOND_LR 1 3495fcf5ef2aSThomas Huth #define BCOND_CTR 2 3496fcf5ef2aSThomas Huth #define BCOND_TAR 3 3497fcf5ef2aSThomas Huth 3498c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 3499fcf5ef2aSThomas Huth { 3500fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3501fcf5ef2aSThomas Huth TCGLabel *l1; 3502fcf5ef2aSThomas Huth TCGv target; 3503fcf5ef2aSThomas Huth 3504fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3505fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3506fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3507fcf5ef2aSThomas Huth if (type == BCOND_CTR) 3508fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3509fcf5ef2aSThomas Huth else if (type == BCOND_TAR) 3510fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3511fcf5ef2aSThomas Huth else 3512fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3513fcf5ef2aSThomas Huth } else { 3514f764718dSRichard Henderson target = NULL; 3515fcf5ef2aSThomas Huth } 3516fcf5ef2aSThomas Huth if (LK(ctx->opcode)) 3517b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3518fcf5ef2aSThomas Huth l1 = gen_new_label(); 3519fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3520fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3521fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3522fcf5ef2aSThomas Huth if (unlikely(type == BCOND_CTR)) { 3523fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3524fcf5ef2aSThomas Huth return; 3525fcf5ef2aSThomas Huth } 3526fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3527fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3528fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3529fcf5ef2aSThomas Huth } else { 3530fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3531fcf5ef2aSThomas Huth } 3532fcf5ef2aSThomas Huth if (bo & 0x2) { 3533fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3534fcf5ef2aSThomas Huth } else { 3535fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3536fcf5ef2aSThomas Huth } 3537fcf5ef2aSThomas Huth tcg_temp_free(temp); 3538fcf5ef2aSThomas Huth } 3539fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3540fcf5ef2aSThomas Huth /* Test CR */ 3541fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3542fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3543fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3544fcf5ef2aSThomas Huth 3545fcf5ef2aSThomas Huth if (bo & 0x8) { 3546fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3547fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3548fcf5ef2aSThomas Huth } else { 3549fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3550fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3551fcf5ef2aSThomas Huth } 3552fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3553fcf5ef2aSThomas Huth } 3554b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3555fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3556fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3557fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3558b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3559fcf5ef2aSThomas Huth } else { 3560fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3561fcf5ef2aSThomas Huth } 3562fcf5ef2aSThomas Huth } else { 3563fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3564fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3565fcf5ef2aSThomas Huth } else { 3566fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3567fcf5ef2aSThomas Huth } 3568c4a2e3a9SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 3569c4a2e3a9SRichard Henderson tcg_temp_free(target); 3570c4a2e3a9SRichard Henderson } 3571fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 3572fcf5ef2aSThomas Huth gen_set_label(l1); 3573b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 3574fcf5ef2aSThomas Huth } 3575fcf5ef2aSThomas Huth } 3576fcf5ef2aSThomas Huth 3577fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3578fcf5ef2aSThomas Huth { 3579fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3580fcf5ef2aSThomas Huth } 3581fcf5ef2aSThomas Huth 3582fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3583fcf5ef2aSThomas Huth { 3584fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3585fcf5ef2aSThomas Huth } 3586fcf5ef2aSThomas Huth 3587fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3588fcf5ef2aSThomas Huth { 3589fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3590fcf5ef2aSThomas Huth } 3591fcf5ef2aSThomas Huth 3592fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3593fcf5ef2aSThomas Huth { 3594fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3595fcf5ef2aSThomas Huth } 3596fcf5ef2aSThomas Huth 3597fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3598fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3599fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3600fcf5ef2aSThomas Huth { \ 3601fcf5ef2aSThomas Huth uint8_t bitmask; \ 3602fcf5ef2aSThomas Huth int sh; \ 3603fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3604fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3605fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3606fcf5ef2aSThomas Huth if (sh > 0) \ 3607fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3608fcf5ef2aSThomas Huth else if (sh < 0) \ 3609fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3610fcf5ef2aSThomas Huth else \ 3611fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3612fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3613fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3614fcf5ef2aSThomas Huth if (sh > 0) \ 3615fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3616fcf5ef2aSThomas Huth else if (sh < 0) \ 3617fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3618fcf5ef2aSThomas Huth else \ 3619fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3620fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3621fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3622fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3623fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3624fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3625fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3626fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3627fcf5ef2aSThomas Huth } 3628fcf5ef2aSThomas Huth 3629fcf5ef2aSThomas Huth /* crand */ 3630fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3631fcf5ef2aSThomas Huth /* crandc */ 3632fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3633fcf5ef2aSThomas Huth /* creqv */ 3634fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3635fcf5ef2aSThomas Huth /* crnand */ 3636fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3637fcf5ef2aSThomas Huth /* crnor */ 3638fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3639fcf5ef2aSThomas Huth /* cror */ 3640fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3641fcf5ef2aSThomas Huth /* crorc */ 3642fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3643fcf5ef2aSThomas Huth /* crxor */ 3644fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3645fcf5ef2aSThomas Huth 3646fcf5ef2aSThomas Huth /* mcrf */ 3647fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3648fcf5ef2aSThomas Huth { 3649fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3650fcf5ef2aSThomas Huth } 3651fcf5ef2aSThomas Huth 3652fcf5ef2aSThomas Huth /*** System linkage ***/ 3653fcf5ef2aSThomas Huth 3654fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3655fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3656fcf5ef2aSThomas Huth { 3657fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3658fcf5ef2aSThomas Huth GEN_PRIV; 3659fcf5ef2aSThomas Huth #else 3660fcf5ef2aSThomas Huth /* This instruction doesn't exist anymore on 64-bit server 3661fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3662fcf5ef2aSThomas Huth */ 3663fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_SEGMENT_64B) { 3664fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3665fcf5ef2aSThomas Huth return; 3666fcf5ef2aSThomas Huth } 3667fcf5ef2aSThomas Huth /* Restore CPU state */ 3668fcf5ef2aSThomas Huth CHK_SV; 3669b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3670fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3671fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3672fcf5ef2aSThomas Huth #endif 3673fcf5ef2aSThomas Huth } 3674fcf5ef2aSThomas Huth 3675fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3676fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 3677fcf5ef2aSThomas Huth { 3678fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3679fcf5ef2aSThomas Huth GEN_PRIV; 3680fcf5ef2aSThomas Huth #else 3681fcf5ef2aSThomas Huth /* Restore CPU state */ 3682fcf5ef2aSThomas Huth CHK_SV; 3683b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3684fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 3685fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3686fcf5ef2aSThomas Huth #endif 3687fcf5ef2aSThomas Huth } 3688fcf5ef2aSThomas Huth 3689fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 3690fcf5ef2aSThomas Huth { 3691fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3692fcf5ef2aSThomas Huth GEN_PRIV; 3693fcf5ef2aSThomas Huth #else 3694fcf5ef2aSThomas Huth /* Restore CPU state */ 3695fcf5ef2aSThomas Huth CHK_HV; 3696fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 3697fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3698fcf5ef2aSThomas Huth #endif 3699fcf5ef2aSThomas Huth } 3700fcf5ef2aSThomas Huth #endif 3701fcf5ef2aSThomas Huth 3702fcf5ef2aSThomas Huth /* sc */ 3703fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3704fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3705fcf5ef2aSThomas Huth #else 3706fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3707fcf5ef2aSThomas Huth #endif 3708fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 3709fcf5ef2aSThomas Huth { 3710fcf5ef2aSThomas Huth uint32_t lev; 3711fcf5ef2aSThomas Huth 3712fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 3713fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3714fcf5ef2aSThomas Huth } 3715fcf5ef2aSThomas Huth 3716fcf5ef2aSThomas Huth /*** Trap ***/ 3717fcf5ef2aSThomas Huth 3718fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 3719fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 3720fcf5ef2aSThomas Huth { 3721fcf5ef2aSThomas Huth /* Trap never */ 3722fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 3723fcf5ef2aSThomas Huth return true; 3724fcf5ef2aSThomas Huth } 3725fcf5ef2aSThomas Huth /* Trap always */ 3726fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 3727fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3728fcf5ef2aSThomas Huth return true; 3729fcf5ef2aSThomas Huth } 3730fcf5ef2aSThomas Huth return false; 3731fcf5ef2aSThomas Huth } 3732fcf5ef2aSThomas Huth 3733fcf5ef2aSThomas Huth /* tw */ 3734fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 3735fcf5ef2aSThomas Huth { 3736fcf5ef2aSThomas Huth TCGv_i32 t0; 3737fcf5ef2aSThomas Huth 3738fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3739fcf5ef2aSThomas Huth return; 3740fcf5ef2aSThomas Huth } 3741fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3742fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3743fcf5ef2aSThomas Huth t0); 3744fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3745fcf5ef2aSThomas Huth } 3746fcf5ef2aSThomas Huth 3747fcf5ef2aSThomas Huth /* twi */ 3748fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 3749fcf5ef2aSThomas Huth { 3750fcf5ef2aSThomas Huth TCGv t0; 3751fcf5ef2aSThomas Huth TCGv_i32 t1; 3752fcf5ef2aSThomas Huth 3753fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3754fcf5ef2aSThomas Huth return; 3755fcf5ef2aSThomas Huth } 3756fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3757fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3758fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3759fcf5ef2aSThomas Huth tcg_temp_free(t0); 3760fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3761fcf5ef2aSThomas Huth } 3762fcf5ef2aSThomas Huth 3763fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3764fcf5ef2aSThomas Huth /* td */ 3765fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 3766fcf5ef2aSThomas Huth { 3767fcf5ef2aSThomas Huth TCGv_i32 t0; 3768fcf5ef2aSThomas Huth 3769fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3770fcf5ef2aSThomas Huth return; 3771fcf5ef2aSThomas Huth } 3772fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3773fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3774fcf5ef2aSThomas Huth t0); 3775fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3776fcf5ef2aSThomas Huth } 3777fcf5ef2aSThomas Huth 3778fcf5ef2aSThomas Huth /* tdi */ 3779fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 3780fcf5ef2aSThomas Huth { 3781fcf5ef2aSThomas Huth TCGv t0; 3782fcf5ef2aSThomas Huth TCGv_i32 t1; 3783fcf5ef2aSThomas Huth 3784fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3785fcf5ef2aSThomas Huth return; 3786fcf5ef2aSThomas Huth } 3787fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3788fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3789fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3790fcf5ef2aSThomas Huth tcg_temp_free(t0); 3791fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3792fcf5ef2aSThomas Huth } 3793fcf5ef2aSThomas Huth #endif 3794fcf5ef2aSThomas Huth 3795fcf5ef2aSThomas Huth /*** Processor control ***/ 3796fcf5ef2aSThomas Huth 3797dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 3798fcf5ef2aSThomas Huth { 3799fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3800fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3801fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 3802fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 3803fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 3804fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 3805fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 3806fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 3807fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 3808fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 3809dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 3810dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 3811dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 3812dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 3813dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 3814dd09c361SNikunj A Dadhania } 3815fcf5ef2aSThomas Huth tcg_temp_free(t0); 3816fcf5ef2aSThomas Huth tcg_temp_free(t1); 3817fcf5ef2aSThomas Huth tcg_temp_free(t2); 3818fcf5ef2aSThomas Huth } 3819fcf5ef2aSThomas Huth 3820fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 3821fcf5ef2aSThomas Huth { 3822dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 3823fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 3824dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 3825dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 3826dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 3827dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 3828dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 38291bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 38301bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 38311bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 3832fcf5ef2aSThomas Huth } 3833fcf5ef2aSThomas Huth 3834fcf5ef2aSThomas Huth /* mcrxr */ 3835fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 3836fcf5ef2aSThomas Huth { 3837fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3838fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3839fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3840fcf5ef2aSThomas Huth 3841fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 3842fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 3843fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 3844fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 3845fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 3846fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 3847fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 3848fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 3849fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3850fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3851fcf5ef2aSThomas Huth 3852fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 3853fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 3854fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3855fcf5ef2aSThomas Huth } 3856fcf5ef2aSThomas Huth 3857b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 3858b63d0434SNikunj A Dadhania /* mcrxrx */ 3859b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 3860b63d0434SNikunj A Dadhania { 3861b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 3862b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 3863b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3864b63d0434SNikunj A Dadhania 3865b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 3866b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 3867b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 3868b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 3869b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 3870b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 3871b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 3872b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 3873b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 3874b63d0434SNikunj A Dadhania tcg_temp_free(t0); 3875b63d0434SNikunj A Dadhania tcg_temp_free(t1); 3876b63d0434SNikunj A Dadhania } 3877b63d0434SNikunj A Dadhania #endif 3878b63d0434SNikunj A Dadhania 3879fcf5ef2aSThomas Huth /* mfcr mfocrf */ 3880fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 3881fcf5ef2aSThomas Huth { 3882fcf5ef2aSThomas Huth uint32_t crm, crn; 3883fcf5ef2aSThomas Huth 3884fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 3885fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 3886fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 3887fcf5ef2aSThomas Huth crn = ctz32 (crm); 3888fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3889fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 3890fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 3891fcf5ef2aSThomas Huth } 3892fcf5ef2aSThomas Huth } else { 3893fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3894fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 3895fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3896fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 3897fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3898fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 3899fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3900fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 3901fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3902fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 3903fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3904fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 3905fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3906fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 3907fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3908fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 3909fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 3910fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3911fcf5ef2aSThomas Huth } 3912fcf5ef2aSThomas Huth } 3913fcf5ef2aSThomas Huth 3914fcf5ef2aSThomas Huth /* mfmsr */ 3915fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 3916fcf5ef2aSThomas Huth { 3917fcf5ef2aSThomas Huth CHK_SV; 3918fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 3919fcf5ef2aSThomas Huth } 3920fcf5ef2aSThomas Huth 3921fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 3922fcf5ef2aSThomas Huth { 3923fcf5ef2aSThomas Huth #if 0 3924fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 3925fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 3926fcf5ef2aSThomas Huth #endif 3927fcf5ef2aSThomas Huth } 3928fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 3929fcf5ef2aSThomas Huth 3930fcf5ef2aSThomas Huth /* mfspr */ 3931fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 3932fcf5ef2aSThomas Huth { 3933fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 3934fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 3935fcf5ef2aSThomas Huth 3936fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3937fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 3938fcf5ef2aSThomas Huth #else 3939fcf5ef2aSThomas Huth if (ctx->pr) { 3940fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 3941fcf5ef2aSThomas Huth } else if (ctx->hv) { 3942fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 3943fcf5ef2aSThomas Huth } else { 3944fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 3945fcf5ef2aSThomas Huth } 3946fcf5ef2aSThomas Huth #endif 3947fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 3948fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 3949fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 3950fcf5ef2aSThomas Huth } else { 3951fcf5ef2aSThomas Huth /* Privilege exception */ 3952fcf5ef2aSThomas Huth /* This is a hack to avoid warnings when running Linux: 3953fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 3954fcf5ef2aSThomas Huth * allowing userland application to read the PVR 3955fcf5ef2aSThomas Huth */ 3956fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 395731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 395831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 3959b6bac4bcSEmilio G. Cota ctx->base.pc_next - 4); 3960fcf5ef2aSThomas Huth } 3961fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 3962fcf5ef2aSThomas Huth } 3963fcf5ef2aSThomas Huth } else { 3964fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 3965fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 3966fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 3967fcf5ef2aSThomas Huth /* This is a nop */ 3968fcf5ef2aSThomas Huth return; 3969fcf5ef2aSThomas Huth } 3970fcf5ef2aSThomas Huth /* Not defined */ 397131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 397231085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 3973b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 3974fcf5ef2aSThomas Huth 3975fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 3976fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 3977fcf5ef2aSThomas Huth */ 3978fcf5ef2aSThomas Huth if (sprn & 0x10) { 3979fcf5ef2aSThomas Huth if (ctx->pr) { 3980fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3981fcf5ef2aSThomas Huth } 3982fcf5ef2aSThomas Huth } else { 3983fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 3984fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3985fcf5ef2aSThomas Huth } 3986fcf5ef2aSThomas Huth } 3987fcf5ef2aSThomas Huth } 3988fcf5ef2aSThomas Huth } 3989fcf5ef2aSThomas Huth 3990fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 3991fcf5ef2aSThomas Huth { 3992fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 3993fcf5ef2aSThomas Huth } 3994fcf5ef2aSThomas Huth 3995fcf5ef2aSThomas Huth /* mftb */ 3996fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 3997fcf5ef2aSThomas Huth { 3998fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 3999fcf5ef2aSThomas Huth } 4000fcf5ef2aSThomas Huth 4001fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4002fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4003fcf5ef2aSThomas Huth { 4004fcf5ef2aSThomas Huth uint32_t crm, crn; 4005fcf5ef2aSThomas Huth 4006fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4007fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4008fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4009fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4010fcf5ef2aSThomas Huth crn = ctz32 (crm); 4011fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4012fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4013fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4014fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4015fcf5ef2aSThomas Huth } 4016fcf5ef2aSThomas Huth } else { 4017fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4018fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4019fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4020fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4021fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4022fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4023fcf5ef2aSThomas Huth } 4024fcf5ef2aSThomas Huth } 4025fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4026fcf5ef2aSThomas Huth } 4027fcf5ef2aSThomas Huth } 4028fcf5ef2aSThomas Huth 4029fcf5ef2aSThomas Huth /* mtmsr */ 4030fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4031fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4032fcf5ef2aSThomas Huth { 4033fcf5ef2aSThomas Huth CHK_SV; 4034fcf5ef2aSThomas Huth 4035fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4036fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4037fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4038fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4039fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4040fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4041fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4042fcf5ef2aSThomas Huth tcg_temp_free(t0); 4043fcf5ef2aSThomas Huth } else { 4044fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4045fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4046fcf5ef2aSThomas Huth * directly from ppc_store_msr 4047fcf5ef2aSThomas Huth */ 4048b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4049fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4050fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4051fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4052fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4053fcf5ef2aSThomas Huth } 4054fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4055fcf5ef2aSThomas Huth } 4056fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4057fcf5ef2aSThomas Huth 4058fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4059fcf5ef2aSThomas Huth { 4060fcf5ef2aSThomas Huth CHK_SV; 4061fcf5ef2aSThomas Huth 4062fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4063fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4064fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4065fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4066fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4067fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4068fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4069fcf5ef2aSThomas Huth tcg_temp_free(t0); 4070fcf5ef2aSThomas Huth } else { 4071fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4072fcf5ef2aSThomas Huth 4073fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4074fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4075fcf5ef2aSThomas Huth * directly from ppc_store_msr 4076fcf5ef2aSThomas Huth */ 4077b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4078fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4079fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4080fcf5ef2aSThomas Huth #else 4081fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4082fcf5ef2aSThomas Huth #endif 4083fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4084fcf5ef2aSThomas Huth tcg_temp_free(msr); 4085fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4086fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4087fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4088fcf5ef2aSThomas Huth } 4089fcf5ef2aSThomas Huth #endif 4090fcf5ef2aSThomas Huth } 4091fcf5ef2aSThomas Huth 4092fcf5ef2aSThomas Huth /* mtspr */ 4093fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4094fcf5ef2aSThomas Huth { 4095fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4096fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4097fcf5ef2aSThomas Huth 4098fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4099fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4100fcf5ef2aSThomas Huth #else 4101fcf5ef2aSThomas Huth if (ctx->pr) { 4102fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4103fcf5ef2aSThomas Huth } else if (ctx->hv) { 4104fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4105fcf5ef2aSThomas Huth } else { 4106fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4107fcf5ef2aSThomas Huth } 4108fcf5ef2aSThomas Huth #endif 4109fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4110fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4111fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4112fcf5ef2aSThomas Huth } else { 4113fcf5ef2aSThomas Huth /* Privilege exception */ 411431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 411531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 411631085338SThomas Huth ctx->base.pc_next - 4); 4117fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4118fcf5ef2aSThomas Huth } 4119fcf5ef2aSThomas Huth } else { 4120fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4121fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4122fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4123fcf5ef2aSThomas Huth /* This is a nop */ 4124fcf5ef2aSThomas Huth return; 4125fcf5ef2aSThomas Huth } 4126fcf5ef2aSThomas Huth 4127fcf5ef2aSThomas Huth /* Not defined */ 412831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 412931085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 4130b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4131fcf5ef2aSThomas Huth 4132fcf5ef2aSThomas Huth 4133fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4134fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4135fcf5ef2aSThomas Huth */ 4136fcf5ef2aSThomas Huth if (sprn & 0x10) { 4137fcf5ef2aSThomas Huth if (ctx->pr) { 4138fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4139fcf5ef2aSThomas Huth } 4140fcf5ef2aSThomas Huth } else { 4141fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4142fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4143fcf5ef2aSThomas Huth } 4144fcf5ef2aSThomas Huth } 4145fcf5ef2aSThomas Huth } 4146fcf5ef2aSThomas Huth } 4147fcf5ef2aSThomas Huth 4148fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4149fcf5ef2aSThomas Huth /* setb */ 4150fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4151fcf5ef2aSThomas Huth { 4152fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4153fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4154fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4155fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4156fcf5ef2aSThomas Huth 4157fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4158fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4159fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4160fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4161fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4162fcf5ef2aSThomas Huth 4163fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4164fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4165fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4166fcf5ef2aSThomas Huth } 4167fcf5ef2aSThomas Huth #endif 4168fcf5ef2aSThomas Huth 4169fcf5ef2aSThomas Huth /*** Cache management ***/ 4170fcf5ef2aSThomas Huth 4171fcf5ef2aSThomas Huth /* dcbf */ 4172fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4173fcf5ef2aSThomas Huth { 4174fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4175fcf5ef2aSThomas Huth TCGv t0; 4176fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4177fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4178fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4179fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4180fcf5ef2aSThomas Huth tcg_temp_free(t0); 4181fcf5ef2aSThomas Huth } 4182fcf5ef2aSThomas Huth 4183fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4184fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4185fcf5ef2aSThomas Huth { 4186fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4187fcf5ef2aSThomas Huth GEN_PRIV; 4188fcf5ef2aSThomas Huth #else 4189fcf5ef2aSThomas Huth TCGv EA, val; 4190fcf5ef2aSThomas Huth 4191fcf5ef2aSThomas Huth CHK_SV; 4192fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4193fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4194fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4195fcf5ef2aSThomas Huth val = tcg_temp_new(); 4196fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4197fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4198fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4199fcf5ef2aSThomas Huth tcg_temp_free(val); 4200fcf5ef2aSThomas Huth tcg_temp_free(EA); 4201fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4202fcf5ef2aSThomas Huth } 4203fcf5ef2aSThomas Huth 4204fcf5ef2aSThomas Huth /* dcdst */ 4205fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4206fcf5ef2aSThomas Huth { 4207fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4208fcf5ef2aSThomas Huth TCGv t0; 4209fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4210fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4211fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4212fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4213fcf5ef2aSThomas Huth tcg_temp_free(t0); 4214fcf5ef2aSThomas Huth } 4215fcf5ef2aSThomas Huth 4216fcf5ef2aSThomas Huth /* dcbt */ 4217fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4218fcf5ef2aSThomas Huth { 4219fcf5ef2aSThomas Huth /* interpreted as no-op */ 4220fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4221fcf5ef2aSThomas Huth * but does not generate any exception 4222fcf5ef2aSThomas Huth */ 4223fcf5ef2aSThomas Huth } 4224fcf5ef2aSThomas Huth 4225fcf5ef2aSThomas Huth /* dcbtst */ 4226fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4227fcf5ef2aSThomas Huth { 4228fcf5ef2aSThomas Huth /* interpreted as no-op */ 4229fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4230fcf5ef2aSThomas Huth * but does not generate any exception 4231fcf5ef2aSThomas Huth */ 4232fcf5ef2aSThomas Huth } 4233fcf5ef2aSThomas Huth 4234fcf5ef2aSThomas Huth /* dcbtls */ 4235fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4236fcf5ef2aSThomas Huth { 4237fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4238fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4239fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4240fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4241fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4242fcf5ef2aSThomas Huth tcg_temp_free(t0); 4243fcf5ef2aSThomas Huth } 4244fcf5ef2aSThomas Huth 4245fcf5ef2aSThomas Huth /* dcbz */ 4246fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4247fcf5ef2aSThomas Huth { 4248fcf5ef2aSThomas Huth TCGv tcgv_addr; 4249fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4250fcf5ef2aSThomas Huth 4251fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4252fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4253fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4254fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4255fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4256fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4257fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4258fcf5ef2aSThomas Huth } 4259fcf5ef2aSThomas Huth 4260fcf5ef2aSThomas Huth /* dst / dstt */ 4261fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4262fcf5ef2aSThomas Huth { 4263fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4264fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4265fcf5ef2aSThomas Huth } else { 4266fcf5ef2aSThomas Huth /* interpreted as no-op */ 4267fcf5ef2aSThomas Huth } 4268fcf5ef2aSThomas Huth } 4269fcf5ef2aSThomas Huth 4270fcf5ef2aSThomas Huth /* dstst /dststt */ 4271fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4272fcf5ef2aSThomas Huth { 4273fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4274fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4275fcf5ef2aSThomas Huth } else { 4276fcf5ef2aSThomas Huth /* interpreted as no-op */ 4277fcf5ef2aSThomas Huth } 4278fcf5ef2aSThomas Huth 4279fcf5ef2aSThomas Huth } 4280fcf5ef2aSThomas Huth 4281fcf5ef2aSThomas Huth /* dss / dssall */ 4282fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4283fcf5ef2aSThomas Huth { 4284fcf5ef2aSThomas Huth /* interpreted as no-op */ 4285fcf5ef2aSThomas Huth } 4286fcf5ef2aSThomas Huth 4287fcf5ef2aSThomas Huth /* icbi */ 4288fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4289fcf5ef2aSThomas Huth { 4290fcf5ef2aSThomas Huth TCGv t0; 4291fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4292fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4293fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4294fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4295fcf5ef2aSThomas Huth tcg_temp_free(t0); 4296fcf5ef2aSThomas Huth } 4297fcf5ef2aSThomas Huth 4298fcf5ef2aSThomas Huth /* Optional: */ 4299fcf5ef2aSThomas Huth /* dcba */ 4300fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4301fcf5ef2aSThomas Huth { 4302fcf5ef2aSThomas Huth /* interpreted as no-op */ 4303fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a store by the MMU 4304fcf5ef2aSThomas Huth * but does not generate any exception 4305fcf5ef2aSThomas Huth */ 4306fcf5ef2aSThomas Huth } 4307fcf5ef2aSThomas Huth 4308fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4309fcf5ef2aSThomas Huth /* Supervisor only: */ 4310fcf5ef2aSThomas Huth 4311fcf5ef2aSThomas Huth /* mfsr */ 4312fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4313fcf5ef2aSThomas Huth { 4314fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4315fcf5ef2aSThomas Huth GEN_PRIV; 4316fcf5ef2aSThomas Huth #else 4317fcf5ef2aSThomas Huth TCGv t0; 4318fcf5ef2aSThomas Huth 4319fcf5ef2aSThomas Huth CHK_SV; 4320fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4321fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4322fcf5ef2aSThomas Huth tcg_temp_free(t0); 4323fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4324fcf5ef2aSThomas Huth } 4325fcf5ef2aSThomas Huth 4326fcf5ef2aSThomas Huth /* mfsrin */ 4327fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4328fcf5ef2aSThomas Huth { 4329fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4330fcf5ef2aSThomas Huth GEN_PRIV; 4331fcf5ef2aSThomas Huth #else 4332fcf5ef2aSThomas Huth TCGv t0; 4333fcf5ef2aSThomas Huth 4334fcf5ef2aSThomas Huth CHK_SV; 4335fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4336e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4337fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4338fcf5ef2aSThomas Huth tcg_temp_free(t0); 4339fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4340fcf5ef2aSThomas Huth } 4341fcf5ef2aSThomas Huth 4342fcf5ef2aSThomas Huth /* mtsr */ 4343fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4344fcf5ef2aSThomas Huth { 4345fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4346fcf5ef2aSThomas Huth GEN_PRIV; 4347fcf5ef2aSThomas Huth #else 4348fcf5ef2aSThomas Huth TCGv t0; 4349fcf5ef2aSThomas Huth 4350fcf5ef2aSThomas Huth CHK_SV; 4351fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4352fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4353fcf5ef2aSThomas Huth tcg_temp_free(t0); 4354fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4355fcf5ef2aSThomas Huth } 4356fcf5ef2aSThomas Huth 4357fcf5ef2aSThomas Huth /* mtsrin */ 4358fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4359fcf5ef2aSThomas Huth { 4360fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4361fcf5ef2aSThomas Huth GEN_PRIV; 4362fcf5ef2aSThomas Huth #else 4363fcf5ef2aSThomas Huth TCGv t0; 4364fcf5ef2aSThomas Huth CHK_SV; 4365fcf5ef2aSThomas Huth 4366fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4367e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4368fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4369fcf5ef2aSThomas Huth tcg_temp_free(t0); 4370fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4371fcf5ef2aSThomas Huth } 4372fcf5ef2aSThomas Huth 4373fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4374fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4375fcf5ef2aSThomas Huth 4376fcf5ef2aSThomas Huth /* mfsr */ 4377fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4378fcf5ef2aSThomas Huth { 4379fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4380fcf5ef2aSThomas Huth GEN_PRIV; 4381fcf5ef2aSThomas Huth #else 4382fcf5ef2aSThomas Huth TCGv t0; 4383fcf5ef2aSThomas Huth 4384fcf5ef2aSThomas Huth CHK_SV; 4385fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4386fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4387fcf5ef2aSThomas Huth tcg_temp_free(t0); 4388fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4389fcf5ef2aSThomas Huth } 4390fcf5ef2aSThomas Huth 4391fcf5ef2aSThomas Huth /* mfsrin */ 4392fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4393fcf5ef2aSThomas Huth { 4394fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4395fcf5ef2aSThomas Huth GEN_PRIV; 4396fcf5ef2aSThomas Huth #else 4397fcf5ef2aSThomas Huth TCGv t0; 4398fcf5ef2aSThomas Huth 4399fcf5ef2aSThomas Huth CHK_SV; 4400fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4401e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4402fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4403fcf5ef2aSThomas Huth tcg_temp_free(t0); 4404fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4405fcf5ef2aSThomas Huth } 4406fcf5ef2aSThomas Huth 4407fcf5ef2aSThomas Huth /* mtsr */ 4408fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4409fcf5ef2aSThomas Huth { 4410fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4411fcf5ef2aSThomas Huth GEN_PRIV; 4412fcf5ef2aSThomas Huth #else 4413fcf5ef2aSThomas Huth TCGv t0; 4414fcf5ef2aSThomas Huth 4415fcf5ef2aSThomas Huth CHK_SV; 4416fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4417fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4418fcf5ef2aSThomas Huth tcg_temp_free(t0); 4419fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4420fcf5ef2aSThomas Huth } 4421fcf5ef2aSThomas Huth 4422fcf5ef2aSThomas Huth /* mtsrin */ 4423fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4424fcf5ef2aSThomas Huth { 4425fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4426fcf5ef2aSThomas Huth GEN_PRIV; 4427fcf5ef2aSThomas Huth #else 4428fcf5ef2aSThomas Huth TCGv t0; 4429fcf5ef2aSThomas Huth 4430fcf5ef2aSThomas Huth CHK_SV; 4431fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4432e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4433fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4434fcf5ef2aSThomas Huth tcg_temp_free(t0); 4435fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4436fcf5ef2aSThomas Huth } 4437fcf5ef2aSThomas Huth 4438fcf5ef2aSThomas Huth /* slbmte */ 4439fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4440fcf5ef2aSThomas Huth { 4441fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4442fcf5ef2aSThomas Huth GEN_PRIV; 4443fcf5ef2aSThomas Huth #else 4444fcf5ef2aSThomas Huth CHK_SV; 4445fcf5ef2aSThomas Huth 4446fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4447fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4448fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4449fcf5ef2aSThomas Huth } 4450fcf5ef2aSThomas Huth 4451fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4452fcf5ef2aSThomas Huth { 4453fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4454fcf5ef2aSThomas Huth GEN_PRIV; 4455fcf5ef2aSThomas Huth #else 4456fcf5ef2aSThomas Huth CHK_SV; 4457fcf5ef2aSThomas Huth 4458fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4459fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4460fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4461fcf5ef2aSThomas Huth } 4462fcf5ef2aSThomas Huth 4463fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4464fcf5ef2aSThomas Huth { 4465fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4466fcf5ef2aSThomas Huth GEN_PRIV; 4467fcf5ef2aSThomas Huth #else 4468fcf5ef2aSThomas Huth CHK_SV; 4469fcf5ef2aSThomas Huth 4470fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4471fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4472fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4473fcf5ef2aSThomas Huth } 4474fcf5ef2aSThomas Huth 4475fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4476fcf5ef2aSThomas Huth { 4477fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4478fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4479fcf5ef2aSThomas Huth #else 4480fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4481fcf5ef2aSThomas Huth 4482fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4483fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4484fcf5ef2aSThomas Huth return; 4485fcf5ef2aSThomas Huth } 4486fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4487fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4488fcf5ef2aSThomas Huth l1 = gen_new_label(); 4489fcf5ef2aSThomas Huth l2 = gen_new_label(); 4490fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4491fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4492efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4493fcf5ef2aSThomas Huth tcg_gen_br(l2); 4494fcf5ef2aSThomas Huth gen_set_label(l1); 4495fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4496fcf5ef2aSThomas Huth gen_set_label(l2); 4497fcf5ef2aSThomas Huth #endif 4498fcf5ef2aSThomas Huth } 4499fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4500fcf5ef2aSThomas Huth 4501fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4502fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4503fcf5ef2aSThomas Huth 4504fcf5ef2aSThomas Huth /* tlbia */ 4505fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4506fcf5ef2aSThomas Huth { 4507fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4508fcf5ef2aSThomas Huth GEN_PRIV; 4509fcf5ef2aSThomas Huth #else 4510fcf5ef2aSThomas Huth CHK_HV; 4511fcf5ef2aSThomas Huth 4512fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4513fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4514fcf5ef2aSThomas Huth } 4515fcf5ef2aSThomas Huth 4516fcf5ef2aSThomas Huth /* tlbiel */ 4517fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4518fcf5ef2aSThomas Huth { 4519fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4520fcf5ef2aSThomas Huth GEN_PRIV; 4521fcf5ef2aSThomas Huth #else 4522fcf5ef2aSThomas Huth CHK_SV; 4523fcf5ef2aSThomas Huth 4524fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4525fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4526fcf5ef2aSThomas Huth } 4527fcf5ef2aSThomas Huth 4528fcf5ef2aSThomas Huth /* tlbie */ 4529fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4530fcf5ef2aSThomas Huth { 4531fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4532fcf5ef2aSThomas Huth GEN_PRIV; 4533fcf5ef2aSThomas Huth #else 4534fcf5ef2aSThomas Huth TCGv_i32 t1; 4535c6fd28fdSSuraj Jitindar Singh 4536c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 453791c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4538c6fd28fdSSuraj Jitindar Singh } else { 4539c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 4540c6fd28fdSSuraj Jitindar Singh } 4541fcf5ef2aSThomas Huth 4542fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4543fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4544fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4545fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4546fcf5ef2aSThomas Huth tcg_temp_free(t0); 4547fcf5ef2aSThomas Huth } else { 4548fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4549fcf5ef2aSThomas Huth } 4550fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4551fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4552fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4553fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4554fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4555fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4556fcf5ef2aSThomas Huth } 4557fcf5ef2aSThomas Huth 4558fcf5ef2aSThomas Huth /* tlbsync */ 4559fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4560fcf5ef2aSThomas Huth { 4561fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4562fcf5ef2aSThomas Huth GEN_PRIV; 4563fcf5ef2aSThomas Huth #else 456491c60f12SCédric Le Goater 456591c60f12SCédric Le Goater if (ctx->gtse) { 456691c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 456791c60f12SCédric Le Goater } else { 456891c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 456991c60f12SCédric Le Goater } 4570fcf5ef2aSThomas Huth 4571fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4572fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4573fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4574fcf5ef2aSThomas Huth } 4575fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4576fcf5ef2aSThomas Huth } 4577fcf5ef2aSThomas Huth 4578fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4579fcf5ef2aSThomas Huth /* slbia */ 4580fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 4581fcf5ef2aSThomas Huth { 4582fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4583fcf5ef2aSThomas Huth GEN_PRIV; 4584fcf5ef2aSThomas Huth #else 4585fcf5ef2aSThomas Huth CHK_SV; 4586fcf5ef2aSThomas Huth 4587fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 4588fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4589fcf5ef2aSThomas Huth } 4590fcf5ef2aSThomas Huth 4591fcf5ef2aSThomas Huth /* slbie */ 4592fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 4593fcf5ef2aSThomas Huth { 4594fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4595fcf5ef2aSThomas Huth GEN_PRIV; 4596fcf5ef2aSThomas Huth #else 4597fcf5ef2aSThomas Huth CHK_SV; 4598fcf5ef2aSThomas Huth 4599fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4600fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4601fcf5ef2aSThomas Huth } 4602a63f1dfcSNikunj A Dadhania 4603a63f1dfcSNikunj A Dadhania /* slbieg */ 4604a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 4605a63f1dfcSNikunj A Dadhania { 4606a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 4607a63f1dfcSNikunj A Dadhania GEN_PRIV; 4608a63f1dfcSNikunj A Dadhania #else 4609a63f1dfcSNikunj A Dadhania CHK_SV; 4610a63f1dfcSNikunj A Dadhania 4611a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4612a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 4613a63f1dfcSNikunj A Dadhania } 4614a63f1dfcSNikunj A Dadhania 461562d897caSNikunj A Dadhania /* slbsync */ 461662d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 461762d897caSNikunj A Dadhania { 461862d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 461962d897caSNikunj A Dadhania GEN_PRIV; 462062d897caSNikunj A Dadhania #else 462162d897caSNikunj A Dadhania CHK_SV; 462262d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 462362d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 462462d897caSNikunj A Dadhania } 462562d897caSNikunj A Dadhania 4626fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4627fcf5ef2aSThomas Huth 4628fcf5ef2aSThomas Huth /*** External control ***/ 4629fcf5ef2aSThomas Huth /* Optional: */ 4630fcf5ef2aSThomas Huth 4631fcf5ef2aSThomas Huth /* eciwx */ 4632fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 4633fcf5ef2aSThomas Huth { 4634fcf5ef2aSThomas Huth TCGv t0; 4635fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4636fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4637fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4638fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4639fcf5ef2aSThomas Huth gen_check_align(ctx, t0, 0x03); 4640fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4641fcf5ef2aSThomas Huth tcg_temp_free(t0); 4642fcf5ef2aSThomas Huth } 4643fcf5ef2aSThomas Huth 4644fcf5ef2aSThomas Huth /* ecowx */ 4645fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 4646fcf5ef2aSThomas Huth { 4647fcf5ef2aSThomas Huth TCGv t0; 4648fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4649fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4650fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4651fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4652fcf5ef2aSThomas Huth gen_check_align(ctx, t0, 0x03); 4653fcf5ef2aSThomas Huth gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4654fcf5ef2aSThomas Huth tcg_temp_free(t0); 4655fcf5ef2aSThomas Huth } 4656fcf5ef2aSThomas Huth 4657fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 4658fcf5ef2aSThomas Huth 4659fcf5ef2aSThomas Huth /* abs - abs. */ 4660fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 4661fcf5ef2aSThomas Huth { 4662fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4663fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4664fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4665fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4666fcf5ef2aSThomas Huth tcg_gen_br(l2); 4667fcf5ef2aSThomas Huth gen_set_label(l1); 4668fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4669fcf5ef2aSThomas Huth gen_set_label(l2); 4670fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4671fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4672fcf5ef2aSThomas Huth } 4673fcf5ef2aSThomas Huth 4674fcf5ef2aSThomas Huth /* abso - abso. */ 4675fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 4676fcf5ef2aSThomas Huth { 4677fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4678fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4679fcf5ef2aSThomas Huth TCGLabel *l3 = gen_new_label(); 4680fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4681fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4682fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4683fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4684fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4685fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4686fcf5ef2aSThomas Huth tcg_gen_br(l2); 4687fcf5ef2aSThomas Huth gen_set_label(l1); 4688fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4689fcf5ef2aSThomas Huth tcg_gen_br(l3); 4690fcf5ef2aSThomas Huth gen_set_label(l2); 4691fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4692fcf5ef2aSThomas Huth gen_set_label(l3); 4693fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4694fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4695fcf5ef2aSThomas Huth } 4696fcf5ef2aSThomas Huth 4697fcf5ef2aSThomas Huth /* clcs */ 4698fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 4699fcf5ef2aSThomas Huth { 4700fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4701fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4702fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4703fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 4704fcf5ef2aSThomas Huth } 4705fcf5ef2aSThomas Huth 4706fcf5ef2aSThomas Huth /* div - div. */ 4707fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 4708fcf5ef2aSThomas Huth { 4709fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4710fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4711fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4712fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4713fcf5ef2aSThomas Huth } 4714fcf5ef2aSThomas Huth 4715fcf5ef2aSThomas Huth /* divo - divo. */ 4716fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 4717fcf5ef2aSThomas Huth { 4718fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4719fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4720fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4721fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4722fcf5ef2aSThomas Huth } 4723fcf5ef2aSThomas Huth 4724fcf5ef2aSThomas Huth /* divs - divs. */ 4725fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 4726fcf5ef2aSThomas Huth { 4727fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4728fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4729fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4730fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4731fcf5ef2aSThomas Huth } 4732fcf5ef2aSThomas Huth 4733fcf5ef2aSThomas Huth /* divso - divso. */ 4734fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 4735fcf5ef2aSThomas Huth { 4736fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4737fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4738fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4739fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4740fcf5ef2aSThomas Huth } 4741fcf5ef2aSThomas Huth 4742fcf5ef2aSThomas Huth /* doz - doz. */ 4743fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 4744fcf5ef2aSThomas Huth { 4745fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4746fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4747fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4748fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4749fcf5ef2aSThomas Huth tcg_gen_br(l2); 4750fcf5ef2aSThomas Huth gen_set_label(l1); 4751fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4752fcf5ef2aSThomas Huth gen_set_label(l2); 4753fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4754fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4755fcf5ef2aSThomas Huth } 4756fcf5ef2aSThomas Huth 4757fcf5ef2aSThomas Huth /* dozo - dozo. */ 4758fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 4759fcf5ef2aSThomas Huth { 4760fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4761fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4762fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4763fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4764fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4765fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4766fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4767fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4768fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4769fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4770fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4771fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 4772fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4773fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4774fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4775fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4776fcf5ef2aSThomas Huth tcg_gen_br(l2); 4777fcf5ef2aSThomas Huth gen_set_label(l1); 4778fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4779fcf5ef2aSThomas Huth gen_set_label(l2); 4780fcf5ef2aSThomas Huth tcg_temp_free(t0); 4781fcf5ef2aSThomas Huth tcg_temp_free(t1); 4782fcf5ef2aSThomas Huth tcg_temp_free(t2); 4783fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4784fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4785fcf5ef2aSThomas Huth } 4786fcf5ef2aSThomas Huth 4787fcf5ef2aSThomas Huth /* dozi */ 4788fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 4789fcf5ef2aSThomas Huth { 4790fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 4791fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4792fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4793fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 4794fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 4795fcf5ef2aSThomas Huth tcg_gen_br(l2); 4796fcf5ef2aSThomas Huth gen_set_label(l1); 4797fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4798fcf5ef2aSThomas Huth gen_set_label(l2); 4799fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4800fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4801fcf5ef2aSThomas Huth } 4802fcf5ef2aSThomas Huth 4803fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 4804fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 4805fcf5ef2aSThomas Huth { 4806fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4807fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 4808fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 4809fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 4810fcf5ef2aSThomas Huth 4811fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4812fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 4813fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4814fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4815fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4816fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 4817fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 4818fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4819fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 4820fcf5ef2aSThomas Huth tcg_temp_free(t0); 4821fcf5ef2aSThomas Huth } 4822fcf5ef2aSThomas Huth 4823fcf5ef2aSThomas Huth /* maskg - maskg. */ 4824fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 4825fcf5ef2aSThomas Huth { 4826fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4827fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4828fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4829fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4830fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 4831fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 4832fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4833fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 4834fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 4835fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 4836fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 4837fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 4838fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4839fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4840fcf5ef2aSThomas Huth gen_set_label(l1); 4841fcf5ef2aSThomas Huth tcg_temp_free(t0); 4842fcf5ef2aSThomas Huth tcg_temp_free(t1); 4843fcf5ef2aSThomas Huth tcg_temp_free(t2); 4844fcf5ef2aSThomas Huth tcg_temp_free(t3); 4845fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4846fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4847fcf5ef2aSThomas Huth } 4848fcf5ef2aSThomas Huth 4849fcf5ef2aSThomas Huth /* maskir - maskir. */ 4850fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 4851fcf5ef2aSThomas Huth { 4852fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4853fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4854fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4855fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4856fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4857fcf5ef2aSThomas Huth tcg_temp_free(t0); 4858fcf5ef2aSThomas Huth tcg_temp_free(t1); 4859fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4860fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4861fcf5ef2aSThomas Huth } 4862fcf5ef2aSThomas Huth 4863fcf5ef2aSThomas Huth /* mul - mul. */ 4864fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 4865fcf5ef2aSThomas Huth { 4866fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 4867fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 4868fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4869fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4870fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4871fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 4872fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 4873fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 4874fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 4875fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4876fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 4877fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 4878fcf5ef2aSThomas Huth tcg_temp_free(t2); 4879fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4880fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4881fcf5ef2aSThomas Huth } 4882fcf5ef2aSThomas Huth 4883fcf5ef2aSThomas Huth /* mulo - mulo. */ 4884fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 4885fcf5ef2aSThomas Huth { 4886fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4887fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 4888fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 4889fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4890fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4891fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4892fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4893fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4894fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 4895fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 4896fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 4897fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 4898fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4899fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 4900fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 4901fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4902fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4903fcf5ef2aSThomas Huth gen_set_label(l1); 4904fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 4905fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 4906fcf5ef2aSThomas Huth tcg_temp_free(t2); 4907fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4908fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4909fcf5ef2aSThomas Huth } 4910fcf5ef2aSThomas Huth 4911fcf5ef2aSThomas Huth /* nabs - nabs. */ 4912fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 4913fcf5ef2aSThomas Huth { 4914fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4915fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4916fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4917fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4918fcf5ef2aSThomas Huth tcg_gen_br(l2); 4919fcf5ef2aSThomas Huth gen_set_label(l1); 4920fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4921fcf5ef2aSThomas Huth gen_set_label(l2); 4922fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4923fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4924fcf5ef2aSThomas Huth } 4925fcf5ef2aSThomas Huth 4926fcf5ef2aSThomas Huth /* nabso - nabso. */ 4927fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 4928fcf5ef2aSThomas Huth { 4929fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4930fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4931fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4932fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4933fcf5ef2aSThomas Huth tcg_gen_br(l2); 4934fcf5ef2aSThomas Huth gen_set_label(l1); 4935fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4936fcf5ef2aSThomas Huth gen_set_label(l2); 4937fcf5ef2aSThomas Huth /* nabs never overflows */ 4938fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4939fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4940fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4941fcf5ef2aSThomas Huth } 4942fcf5ef2aSThomas Huth 4943fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 4944fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 4945fcf5ef2aSThomas Huth { 4946fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 4947fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 4948fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4949fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4950fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4951fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 4952fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 4953fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 4954fcf5ef2aSThomas Huth tcg_temp_free(t0); 4955fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4956fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4957fcf5ef2aSThomas Huth } 4958fcf5ef2aSThomas Huth 4959fcf5ef2aSThomas Huth /* rrib - rrib. */ 4960fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 4961fcf5ef2aSThomas Huth { 4962fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4963fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4964fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4965fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 4966fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 4967fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4968fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 4969fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 4970fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4971fcf5ef2aSThomas Huth tcg_temp_free(t0); 4972fcf5ef2aSThomas Huth tcg_temp_free(t1); 4973fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4974fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4975fcf5ef2aSThomas Huth } 4976fcf5ef2aSThomas Huth 4977fcf5ef2aSThomas Huth /* sle - sle. */ 4978fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 4979fcf5ef2aSThomas Huth { 4980fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4981fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4982fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4983fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4984fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 4985fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4986fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 4987fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4988fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 4989fcf5ef2aSThomas Huth tcg_temp_free(t0); 4990fcf5ef2aSThomas Huth tcg_temp_free(t1); 4991fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4992fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4993fcf5ef2aSThomas Huth } 4994fcf5ef2aSThomas Huth 4995fcf5ef2aSThomas Huth /* sleq - sleq. */ 4996fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 4997fcf5ef2aSThomas Huth { 4998fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4999fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5000fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5001fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5002fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5003fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5004fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5005fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5006fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5007fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5008fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5009fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5010fcf5ef2aSThomas Huth tcg_temp_free(t0); 5011fcf5ef2aSThomas Huth tcg_temp_free(t1); 5012fcf5ef2aSThomas Huth tcg_temp_free(t2); 5013fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5014fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5015fcf5ef2aSThomas Huth } 5016fcf5ef2aSThomas Huth 5017fcf5ef2aSThomas Huth /* sliq - sliq. */ 5018fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5019fcf5ef2aSThomas Huth { 5020fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5021fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5022fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5023fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5024fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5025fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5026fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5027fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5028fcf5ef2aSThomas Huth tcg_temp_free(t0); 5029fcf5ef2aSThomas Huth tcg_temp_free(t1); 5030fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5031fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5032fcf5ef2aSThomas Huth } 5033fcf5ef2aSThomas Huth 5034fcf5ef2aSThomas Huth /* slliq - slliq. */ 5035fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5036fcf5ef2aSThomas Huth { 5037fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5038fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5039fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5040fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5041fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5042fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5043fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5044fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5045fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5046fcf5ef2aSThomas Huth tcg_temp_free(t0); 5047fcf5ef2aSThomas Huth tcg_temp_free(t1); 5048fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5049fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5050fcf5ef2aSThomas Huth } 5051fcf5ef2aSThomas Huth 5052fcf5ef2aSThomas Huth /* sllq - sllq. */ 5053fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5054fcf5ef2aSThomas Huth { 5055fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5056fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5057fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5058fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5059fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5060fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5061fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5062fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5063fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5064fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5065fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5066fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5067fcf5ef2aSThomas Huth tcg_gen_br(l2); 5068fcf5ef2aSThomas Huth gen_set_label(l1); 5069fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5070fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5071fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5072fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5073fcf5ef2aSThomas Huth gen_set_label(l2); 5074fcf5ef2aSThomas Huth tcg_temp_free(t0); 5075fcf5ef2aSThomas Huth tcg_temp_free(t1); 5076fcf5ef2aSThomas Huth tcg_temp_free(t2); 5077fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5078fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5079fcf5ef2aSThomas Huth } 5080fcf5ef2aSThomas Huth 5081fcf5ef2aSThomas Huth /* slq - slq. */ 5082fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5083fcf5ef2aSThomas Huth { 5084fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5085fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5086fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5087fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5088fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5089fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5090fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5091fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5092fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5093fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5094fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5095fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5096fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5097fcf5ef2aSThomas Huth gen_set_label(l1); 5098fcf5ef2aSThomas Huth tcg_temp_free(t0); 5099fcf5ef2aSThomas Huth tcg_temp_free(t1); 5100fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5101fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5102fcf5ef2aSThomas Huth } 5103fcf5ef2aSThomas Huth 5104fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5105fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5106fcf5ef2aSThomas Huth { 5107fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5108fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5109fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5110fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5111fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5112fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5113fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5114fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5115fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5116fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5117fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5118fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5119fcf5ef2aSThomas Huth gen_set_label(l1); 5120fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5121fcf5ef2aSThomas Huth tcg_temp_free(t0); 5122fcf5ef2aSThomas Huth tcg_temp_free(t1); 5123fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5124fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5125fcf5ef2aSThomas Huth } 5126fcf5ef2aSThomas Huth 5127fcf5ef2aSThomas Huth /* sraq - sraq. */ 5128fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5129fcf5ef2aSThomas Huth { 5130fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5131fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5132fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5133fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5134fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5135fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5136fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5137fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5138fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5139fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5140fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5141fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5142fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5143fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5144fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5145fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5146fcf5ef2aSThomas Huth gen_set_label(l1); 5147fcf5ef2aSThomas Huth tcg_temp_free(t0); 5148fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5149fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5150fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5151fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5152fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5153fcf5ef2aSThomas Huth gen_set_label(l2); 5154fcf5ef2aSThomas Huth tcg_temp_free(t1); 5155fcf5ef2aSThomas Huth tcg_temp_free(t2); 5156fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5157fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5158fcf5ef2aSThomas Huth } 5159fcf5ef2aSThomas Huth 5160fcf5ef2aSThomas Huth /* sre - sre. */ 5161fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5162fcf5ef2aSThomas Huth { 5163fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5164fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5165fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5166fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5167fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5168fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5169fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5170fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5171fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5172fcf5ef2aSThomas Huth tcg_temp_free(t0); 5173fcf5ef2aSThomas Huth tcg_temp_free(t1); 5174fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5175fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5176fcf5ef2aSThomas Huth } 5177fcf5ef2aSThomas Huth 5178fcf5ef2aSThomas Huth /* srea - srea. */ 5179fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5180fcf5ef2aSThomas Huth { 5181fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5182fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5183fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5184fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5185fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5186fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5187fcf5ef2aSThomas Huth tcg_temp_free(t0); 5188fcf5ef2aSThomas Huth tcg_temp_free(t1); 5189fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5190fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5191fcf5ef2aSThomas Huth } 5192fcf5ef2aSThomas Huth 5193fcf5ef2aSThomas Huth /* sreq */ 5194fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5195fcf5ef2aSThomas Huth { 5196fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5197fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5198fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5199fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5200fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5201fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5202fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5203fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5204fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5205fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5206fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5207fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5208fcf5ef2aSThomas Huth tcg_temp_free(t0); 5209fcf5ef2aSThomas Huth tcg_temp_free(t1); 5210fcf5ef2aSThomas Huth tcg_temp_free(t2); 5211fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5212fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5213fcf5ef2aSThomas Huth } 5214fcf5ef2aSThomas Huth 5215fcf5ef2aSThomas Huth /* sriq */ 5216fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5217fcf5ef2aSThomas Huth { 5218fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5219fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5220fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5221fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5222fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5223fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5224fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5225fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5226fcf5ef2aSThomas Huth tcg_temp_free(t0); 5227fcf5ef2aSThomas Huth tcg_temp_free(t1); 5228fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5229fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5230fcf5ef2aSThomas Huth } 5231fcf5ef2aSThomas Huth 5232fcf5ef2aSThomas Huth /* srliq */ 5233fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5234fcf5ef2aSThomas Huth { 5235fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5236fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5237fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5238fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5239fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5240fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5241fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5242fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5243fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5244fcf5ef2aSThomas Huth tcg_temp_free(t0); 5245fcf5ef2aSThomas Huth tcg_temp_free(t1); 5246fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5247fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5248fcf5ef2aSThomas Huth } 5249fcf5ef2aSThomas Huth 5250fcf5ef2aSThomas Huth /* srlq */ 5251fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5252fcf5ef2aSThomas Huth { 5253fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5254fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5255fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5256fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5257fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5258fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5259fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5260fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5261fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5262fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5263fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5264fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5265fcf5ef2aSThomas Huth tcg_gen_br(l2); 5266fcf5ef2aSThomas Huth gen_set_label(l1); 5267fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5268fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5269fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5270fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5271fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5272fcf5ef2aSThomas Huth gen_set_label(l2); 5273fcf5ef2aSThomas Huth tcg_temp_free(t0); 5274fcf5ef2aSThomas Huth tcg_temp_free(t1); 5275fcf5ef2aSThomas Huth tcg_temp_free(t2); 5276fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5277fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5278fcf5ef2aSThomas Huth } 5279fcf5ef2aSThomas Huth 5280fcf5ef2aSThomas Huth /* srq */ 5281fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5282fcf5ef2aSThomas Huth { 5283fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5284fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5285fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5286fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5287fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5288fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5289fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5290fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5291fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5292fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5293fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5294fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5295fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5296fcf5ef2aSThomas Huth gen_set_label(l1); 5297fcf5ef2aSThomas Huth tcg_temp_free(t0); 5298fcf5ef2aSThomas Huth tcg_temp_free(t1); 5299fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5300fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5301fcf5ef2aSThomas Huth } 5302fcf5ef2aSThomas Huth 5303fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5304fcf5ef2aSThomas Huth 5305fcf5ef2aSThomas Huth /* dsa */ 5306fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5307fcf5ef2aSThomas Huth { 5308fcf5ef2aSThomas Huth /* XXX: TODO */ 5309fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5310fcf5ef2aSThomas Huth } 5311fcf5ef2aSThomas Huth 5312fcf5ef2aSThomas Huth /* esa */ 5313fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5314fcf5ef2aSThomas Huth { 5315fcf5ef2aSThomas Huth /* XXX: TODO */ 5316fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5317fcf5ef2aSThomas Huth } 5318fcf5ef2aSThomas Huth 5319fcf5ef2aSThomas Huth /* mfrom */ 5320fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5321fcf5ef2aSThomas Huth { 5322fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5323fcf5ef2aSThomas Huth GEN_PRIV; 5324fcf5ef2aSThomas Huth #else 5325fcf5ef2aSThomas Huth CHK_SV; 5326fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5327fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5328fcf5ef2aSThomas Huth } 5329fcf5ef2aSThomas Huth 5330fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5331fcf5ef2aSThomas Huth 5332fcf5ef2aSThomas Huth /* tlbld */ 5333fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5334fcf5ef2aSThomas Huth { 5335fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5336fcf5ef2aSThomas Huth GEN_PRIV; 5337fcf5ef2aSThomas Huth #else 5338fcf5ef2aSThomas Huth CHK_SV; 5339fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5340fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5341fcf5ef2aSThomas Huth } 5342fcf5ef2aSThomas Huth 5343fcf5ef2aSThomas Huth /* tlbli */ 5344fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5345fcf5ef2aSThomas Huth { 5346fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5347fcf5ef2aSThomas Huth GEN_PRIV; 5348fcf5ef2aSThomas Huth #else 5349fcf5ef2aSThomas Huth CHK_SV; 5350fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5351fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5352fcf5ef2aSThomas Huth } 5353fcf5ef2aSThomas Huth 5354fcf5ef2aSThomas Huth /* 74xx TLB management */ 5355fcf5ef2aSThomas Huth 5356fcf5ef2aSThomas Huth /* tlbld */ 5357fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5358fcf5ef2aSThomas Huth { 5359fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5360fcf5ef2aSThomas Huth GEN_PRIV; 5361fcf5ef2aSThomas Huth #else 5362fcf5ef2aSThomas Huth CHK_SV; 5363fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5365fcf5ef2aSThomas Huth } 5366fcf5ef2aSThomas Huth 5367fcf5ef2aSThomas Huth /* tlbli */ 5368fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5369fcf5ef2aSThomas Huth { 5370fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5371fcf5ef2aSThomas Huth GEN_PRIV; 5372fcf5ef2aSThomas Huth #else 5373fcf5ef2aSThomas Huth CHK_SV; 5374fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5375fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5376fcf5ef2aSThomas Huth } 5377fcf5ef2aSThomas Huth 5378fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5379fcf5ef2aSThomas Huth 5380fcf5ef2aSThomas Huth /* clf */ 5381fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5382fcf5ef2aSThomas Huth { 5383fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5384fcf5ef2aSThomas Huth } 5385fcf5ef2aSThomas Huth 5386fcf5ef2aSThomas Huth /* cli */ 5387fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5388fcf5ef2aSThomas Huth { 5389fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5390fcf5ef2aSThomas Huth GEN_PRIV; 5391fcf5ef2aSThomas Huth #else 5392fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5393fcf5ef2aSThomas Huth CHK_SV; 5394fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5395fcf5ef2aSThomas Huth } 5396fcf5ef2aSThomas Huth 5397fcf5ef2aSThomas Huth /* dclst */ 5398fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5399fcf5ef2aSThomas Huth { 5400fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5401fcf5ef2aSThomas Huth } 5402fcf5ef2aSThomas Huth 5403fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5404fcf5ef2aSThomas Huth { 5405fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5406fcf5ef2aSThomas Huth GEN_PRIV; 5407fcf5ef2aSThomas Huth #else 5408fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5409fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5410fcf5ef2aSThomas Huth TCGv t0; 5411fcf5ef2aSThomas Huth 5412fcf5ef2aSThomas Huth CHK_SV; 5413fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5414fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5415e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 5416fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5417fcf5ef2aSThomas Huth tcg_temp_free(t0); 5418fcf5ef2aSThomas Huth if (ra != 0 && ra != rd) 5419fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5420fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5421fcf5ef2aSThomas Huth } 5422fcf5ef2aSThomas Huth 5423fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5424fcf5ef2aSThomas Huth { 5425fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5426fcf5ef2aSThomas Huth GEN_PRIV; 5427fcf5ef2aSThomas Huth #else 5428fcf5ef2aSThomas Huth TCGv t0; 5429fcf5ef2aSThomas Huth 5430fcf5ef2aSThomas Huth CHK_SV; 5431fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5432fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5433fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5434fcf5ef2aSThomas Huth tcg_temp_free(t0); 5435fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5436fcf5ef2aSThomas Huth } 5437fcf5ef2aSThomas Huth 5438fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5439fcf5ef2aSThomas Huth { 5440fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5441fcf5ef2aSThomas Huth GEN_PRIV; 5442fcf5ef2aSThomas Huth #else 5443fcf5ef2aSThomas Huth CHK_SV; 5444fcf5ef2aSThomas Huth 5445fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5446fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5447fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5448fcf5ef2aSThomas Huth } 5449fcf5ef2aSThomas Huth 5450fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5451fcf5ef2aSThomas Huth 5452fcf5ef2aSThomas Huth /* BookE specific instructions */ 5453fcf5ef2aSThomas Huth 5454fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5455fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5456fcf5ef2aSThomas Huth { 5457fcf5ef2aSThomas Huth /* XXX: TODO */ 5458fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5459fcf5ef2aSThomas Huth } 5460fcf5ef2aSThomas Huth 5461fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5462fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5463fcf5ef2aSThomas Huth { 5464fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5465fcf5ef2aSThomas Huth GEN_PRIV; 5466fcf5ef2aSThomas Huth #else 5467fcf5ef2aSThomas Huth TCGv t0; 5468fcf5ef2aSThomas Huth 5469fcf5ef2aSThomas Huth CHK_SV; 5470fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5471fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5472fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5473fcf5ef2aSThomas Huth tcg_temp_free(t0); 5474fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5475fcf5ef2aSThomas Huth } 5476fcf5ef2aSThomas Huth 5477fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5478fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5479fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5480fcf5ef2aSThomas Huth { 5481fcf5ef2aSThomas Huth TCGv t0, t1; 5482fcf5ef2aSThomas Huth 5483fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5484fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5485fcf5ef2aSThomas Huth 5486fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5487fcf5ef2aSThomas Huth case 0x05: 5488fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5489fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5490fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5491fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5492fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5493fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5494fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5495fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5496fcf5ef2aSThomas Huth break; 5497fcf5ef2aSThomas Huth case 0x04: 5498fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5499fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5500fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5501fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5502fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5503fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5504fcf5ef2aSThomas Huth break; 5505fcf5ef2aSThomas Huth case 0x01: 5506fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5507fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5508fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5509fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5510fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5511fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5512fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5513fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5514fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5515fcf5ef2aSThomas Huth break; 5516fcf5ef2aSThomas Huth case 0x00: 5517fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5518fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5519fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5520fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5521fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5522fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5523fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5524fcf5ef2aSThomas Huth break; 5525fcf5ef2aSThomas Huth case 0x0D: 5526fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5527fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5528fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5529fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5530fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5531fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5532fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5533fcf5ef2aSThomas Huth break; 5534fcf5ef2aSThomas Huth case 0x0C: 5535fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5536fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5537fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5538fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5539fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5540fcf5ef2aSThomas Huth break; 5541fcf5ef2aSThomas Huth } 5542fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5543fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5544fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5545fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5546fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5547fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5548fcf5ef2aSThomas Huth } else { 5549fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5550fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5551fcf5ef2aSThomas Huth } 5552fcf5ef2aSThomas Huth 5553fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5554fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5555fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5556fcf5ef2aSThomas Huth 5557fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5558fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5559fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5560fcf5ef2aSThomas Huth } 5561fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5562fcf5ef2aSThomas Huth /* Signed */ 5563fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5564fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5565fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5566fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5567fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5568fcf5ef2aSThomas Huth /* Saturate */ 5569fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5570fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5571fcf5ef2aSThomas Huth } 5572fcf5ef2aSThomas Huth } else { 5573fcf5ef2aSThomas Huth /* Unsigned */ 5574fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5575fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5576fcf5ef2aSThomas Huth /* Saturate */ 5577fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5578fcf5ef2aSThomas Huth } 5579fcf5ef2aSThomas Huth } 5580fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5581fcf5ef2aSThomas Huth /* Check overflow */ 5582fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5583fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5584fcf5ef2aSThomas Huth } 5585fcf5ef2aSThomas Huth gen_set_label(l1); 5586fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5587fcf5ef2aSThomas Huth } 5588fcf5ef2aSThomas Huth } else { 5589fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5590fcf5ef2aSThomas Huth } 5591fcf5ef2aSThomas Huth tcg_temp_free(t0); 5592fcf5ef2aSThomas Huth tcg_temp_free(t1); 5593fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5594fcf5ef2aSThomas Huth /* Update Rc0 */ 5595fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5596fcf5ef2aSThomas Huth } 5597fcf5ef2aSThomas Huth } 5598fcf5ef2aSThomas Huth 5599fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5600fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5601fcf5ef2aSThomas Huth { \ 5602fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5603fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5604fcf5ef2aSThomas Huth } 5605fcf5ef2aSThomas Huth 5606fcf5ef2aSThomas Huth /* macchw - macchw. */ 5607fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5608fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5609fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5610fcf5ef2aSThomas Huth /* macchws - macchws. */ 5611fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5612fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5613fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5614fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5615fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5616fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5617fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5618fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5619fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5620fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5621fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5622fcf5ef2aSThomas Huth /* machhw - machhw. */ 5623fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5624fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5625fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5626fcf5ef2aSThomas Huth /* machhws - machhws. */ 5627fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5628fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5629fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5630fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5631fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5632fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5633fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5634fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5635fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5636fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5637fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5638fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5639fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5640fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5641fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5642fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5643fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5644fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5645fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5646fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5647fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5648fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5649fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5650fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5651fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5652fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5653fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5654fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5655fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5656fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5657fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5658fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5659fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5660fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5661fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5662fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5663fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5664fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5665fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5666fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5667fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5668fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5669fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5670fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5671fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5672fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5673fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5674fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5675fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5676fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5677fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5678fcf5ef2aSThomas Huth 5679fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5680fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5681fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5682fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5683fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5684fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5685fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5686fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5687fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5688fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5689fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5690fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5691fcf5ef2aSThomas Huth 5692fcf5ef2aSThomas Huth /* mfdcr */ 5693fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5694fcf5ef2aSThomas Huth { 5695fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5696fcf5ef2aSThomas Huth GEN_PRIV; 5697fcf5ef2aSThomas Huth #else 5698fcf5ef2aSThomas Huth TCGv dcrn; 5699fcf5ef2aSThomas Huth 5700fcf5ef2aSThomas Huth CHK_SV; 5701fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5702fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5703fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5704fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5705fcf5ef2aSThomas Huth } 5706fcf5ef2aSThomas Huth 5707fcf5ef2aSThomas Huth /* mtdcr */ 5708fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5709fcf5ef2aSThomas Huth { 5710fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5711fcf5ef2aSThomas Huth GEN_PRIV; 5712fcf5ef2aSThomas Huth #else 5713fcf5ef2aSThomas Huth TCGv dcrn; 5714fcf5ef2aSThomas Huth 5715fcf5ef2aSThomas Huth CHK_SV; 5716fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5717fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5718fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5719fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5720fcf5ef2aSThomas Huth } 5721fcf5ef2aSThomas Huth 5722fcf5ef2aSThomas Huth /* mfdcrx */ 5723fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5724fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5725fcf5ef2aSThomas Huth { 5726fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5727fcf5ef2aSThomas Huth GEN_PRIV; 5728fcf5ef2aSThomas Huth #else 5729fcf5ef2aSThomas Huth CHK_SV; 5730fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5731fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5732fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5733fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5734fcf5ef2aSThomas Huth } 5735fcf5ef2aSThomas Huth 5736fcf5ef2aSThomas Huth /* mtdcrx */ 5737fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5738fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5739fcf5ef2aSThomas Huth { 5740fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5741fcf5ef2aSThomas Huth GEN_PRIV; 5742fcf5ef2aSThomas Huth #else 5743fcf5ef2aSThomas Huth CHK_SV; 5744fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5745fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5746fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5747fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5748fcf5ef2aSThomas Huth } 5749fcf5ef2aSThomas Huth 5750fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 5751fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 5752fcf5ef2aSThomas Huth { 5753fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5754fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5755fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5756fcf5ef2aSThomas Huth } 5757fcf5ef2aSThomas Huth 5758fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 5759fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 5760fcf5ef2aSThomas Huth { 5761fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5762fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5763fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5764fcf5ef2aSThomas Huth } 5765fcf5ef2aSThomas Huth 5766fcf5ef2aSThomas Huth /* dccci */ 5767fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5768fcf5ef2aSThomas Huth { 5769fcf5ef2aSThomas Huth CHK_SV; 5770fcf5ef2aSThomas Huth /* interpreted as no-op */ 5771fcf5ef2aSThomas Huth } 5772fcf5ef2aSThomas Huth 5773fcf5ef2aSThomas Huth /* dcread */ 5774fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5775fcf5ef2aSThomas Huth { 5776fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5777fcf5ef2aSThomas Huth GEN_PRIV; 5778fcf5ef2aSThomas Huth #else 5779fcf5ef2aSThomas Huth TCGv EA, val; 5780fcf5ef2aSThomas Huth 5781fcf5ef2aSThomas Huth CHK_SV; 5782fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5783fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5784fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5785fcf5ef2aSThomas Huth val = tcg_temp_new(); 5786fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5787fcf5ef2aSThomas Huth tcg_temp_free(val); 5788fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5789fcf5ef2aSThomas Huth tcg_temp_free(EA); 5790fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5791fcf5ef2aSThomas Huth } 5792fcf5ef2aSThomas Huth 5793fcf5ef2aSThomas Huth /* icbt */ 5794fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5795fcf5ef2aSThomas Huth { 5796fcf5ef2aSThomas Huth /* interpreted as no-op */ 5797fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 5798fcf5ef2aSThomas Huth * but does not generate any exception 5799fcf5ef2aSThomas Huth */ 5800fcf5ef2aSThomas Huth } 5801fcf5ef2aSThomas Huth 5802fcf5ef2aSThomas Huth /* iccci */ 5803fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5804fcf5ef2aSThomas Huth { 5805fcf5ef2aSThomas Huth CHK_SV; 5806fcf5ef2aSThomas Huth /* interpreted as no-op */ 5807fcf5ef2aSThomas Huth } 5808fcf5ef2aSThomas Huth 5809fcf5ef2aSThomas Huth /* icread */ 5810fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5811fcf5ef2aSThomas Huth { 5812fcf5ef2aSThomas Huth CHK_SV; 5813fcf5ef2aSThomas Huth /* interpreted as no-op */ 5814fcf5ef2aSThomas Huth } 5815fcf5ef2aSThomas Huth 5816fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5817fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5818fcf5ef2aSThomas Huth { 5819fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5820fcf5ef2aSThomas Huth GEN_PRIV; 5821fcf5ef2aSThomas Huth #else 5822fcf5ef2aSThomas Huth CHK_SV; 5823fcf5ef2aSThomas Huth /* Restore CPU state */ 5824fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 5825fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5826fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5827fcf5ef2aSThomas Huth } 5828fcf5ef2aSThomas Huth 5829fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5830fcf5ef2aSThomas Huth { 5831fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5832fcf5ef2aSThomas Huth GEN_PRIV; 5833fcf5ef2aSThomas Huth #else 5834fcf5ef2aSThomas Huth CHK_SV; 5835fcf5ef2aSThomas Huth /* Restore CPU state */ 5836fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 5837fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5838fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5839fcf5ef2aSThomas Huth } 5840fcf5ef2aSThomas Huth 5841fcf5ef2aSThomas Huth /* BookE specific */ 5842fcf5ef2aSThomas Huth 5843fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5844fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5845fcf5ef2aSThomas Huth { 5846fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5847fcf5ef2aSThomas Huth GEN_PRIV; 5848fcf5ef2aSThomas Huth #else 5849fcf5ef2aSThomas Huth CHK_SV; 5850fcf5ef2aSThomas Huth /* Restore CPU state */ 5851fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 5852fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5853fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5854fcf5ef2aSThomas Huth } 5855fcf5ef2aSThomas Huth 5856fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5857fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5858fcf5ef2aSThomas Huth { 5859fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5860fcf5ef2aSThomas Huth GEN_PRIV; 5861fcf5ef2aSThomas Huth #else 5862fcf5ef2aSThomas Huth CHK_SV; 5863fcf5ef2aSThomas Huth /* Restore CPU state */ 5864fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 5865fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5866fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5867fcf5ef2aSThomas Huth } 5868fcf5ef2aSThomas Huth 5869fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5870fcf5ef2aSThomas Huth 5871fcf5ef2aSThomas Huth /* tlbre */ 5872fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5873fcf5ef2aSThomas Huth { 5874fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5875fcf5ef2aSThomas Huth GEN_PRIV; 5876fcf5ef2aSThomas Huth #else 5877fcf5ef2aSThomas Huth CHK_SV; 5878fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5879fcf5ef2aSThomas Huth case 0: 5880fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5881fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5882fcf5ef2aSThomas Huth break; 5883fcf5ef2aSThomas Huth case 1: 5884fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5885fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5886fcf5ef2aSThomas Huth break; 5887fcf5ef2aSThomas Huth default: 5888fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5889fcf5ef2aSThomas Huth break; 5890fcf5ef2aSThomas Huth } 5891fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5892fcf5ef2aSThomas Huth } 5893fcf5ef2aSThomas Huth 5894fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5895fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5896fcf5ef2aSThomas Huth { 5897fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5898fcf5ef2aSThomas Huth GEN_PRIV; 5899fcf5ef2aSThomas Huth #else 5900fcf5ef2aSThomas Huth TCGv t0; 5901fcf5ef2aSThomas Huth 5902fcf5ef2aSThomas Huth CHK_SV; 5903fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5904fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5905fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5906fcf5ef2aSThomas Huth tcg_temp_free(t0); 5907fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5908fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5909fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5910fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5911fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5912fcf5ef2aSThomas Huth gen_set_label(l1); 5913fcf5ef2aSThomas Huth } 5914fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5915fcf5ef2aSThomas Huth } 5916fcf5ef2aSThomas Huth 5917fcf5ef2aSThomas Huth /* tlbwe */ 5918fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5919fcf5ef2aSThomas Huth { 5920fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5921fcf5ef2aSThomas Huth GEN_PRIV; 5922fcf5ef2aSThomas Huth #else 5923fcf5ef2aSThomas Huth CHK_SV; 5924fcf5ef2aSThomas Huth 5925fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5926fcf5ef2aSThomas Huth case 0: 5927fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5928fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5929fcf5ef2aSThomas Huth break; 5930fcf5ef2aSThomas Huth case 1: 5931fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5932fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5933fcf5ef2aSThomas Huth break; 5934fcf5ef2aSThomas Huth default: 5935fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5936fcf5ef2aSThomas Huth break; 5937fcf5ef2aSThomas Huth } 5938fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5939fcf5ef2aSThomas Huth } 5940fcf5ef2aSThomas Huth 5941fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5942fcf5ef2aSThomas Huth 5943fcf5ef2aSThomas Huth /* tlbre */ 5944fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5945fcf5ef2aSThomas Huth { 5946fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5947fcf5ef2aSThomas Huth GEN_PRIV; 5948fcf5ef2aSThomas Huth #else 5949fcf5ef2aSThomas Huth CHK_SV; 5950fcf5ef2aSThomas Huth 5951fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5952fcf5ef2aSThomas Huth case 0: 5953fcf5ef2aSThomas Huth case 1: 5954fcf5ef2aSThomas Huth case 2: 5955fcf5ef2aSThomas Huth { 5956fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5957fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5958fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5959fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5960fcf5ef2aSThomas Huth } 5961fcf5ef2aSThomas Huth break; 5962fcf5ef2aSThomas Huth default: 5963fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5964fcf5ef2aSThomas Huth break; 5965fcf5ef2aSThomas Huth } 5966fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5967fcf5ef2aSThomas Huth } 5968fcf5ef2aSThomas Huth 5969fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5970fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5971fcf5ef2aSThomas Huth { 5972fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5973fcf5ef2aSThomas Huth GEN_PRIV; 5974fcf5ef2aSThomas Huth #else 5975fcf5ef2aSThomas Huth TCGv t0; 5976fcf5ef2aSThomas Huth 5977fcf5ef2aSThomas Huth CHK_SV; 5978fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5979fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5980fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5981fcf5ef2aSThomas Huth tcg_temp_free(t0); 5982fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5983fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5984fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5985fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5986fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5987fcf5ef2aSThomas Huth gen_set_label(l1); 5988fcf5ef2aSThomas Huth } 5989fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5990fcf5ef2aSThomas Huth } 5991fcf5ef2aSThomas Huth 5992fcf5ef2aSThomas Huth /* tlbwe */ 5993fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5994fcf5ef2aSThomas Huth { 5995fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5996fcf5ef2aSThomas Huth GEN_PRIV; 5997fcf5ef2aSThomas Huth #else 5998fcf5ef2aSThomas Huth CHK_SV; 5999fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6000fcf5ef2aSThomas Huth case 0: 6001fcf5ef2aSThomas Huth case 1: 6002fcf5ef2aSThomas Huth case 2: 6003fcf5ef2aSThomas Huth { 6004fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6005fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6006fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6007fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6008fcf5ef2aSThomas Huth } 6009fcf5ef2aSThomas Huth break; 6010fcf5ef2aSThomas Huth default: 6011fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6012fcf5ef2aSThomas Huth break; 6013fcf5ef2aSThomas Huth } 6014fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6015fcf5ef2aSThomas Huth } 6016fcf5ef2aSThomas Huth 6017fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6018fcf5ef2aSThomas Huth 6019fcf5ef2aSThomas Huth /* tlbre */ 6020fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6021fcf5ef2aSThomas Huth { 6022fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6023fcf5ef2aSThomas Huth GEN_PRIV; 6024fcf5ef2aSThomas Huth #else 6025fcf5ef2aSThomas Huth CHK_SV; 6026fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6027fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6028fcf5ef2aSThomas Huth } 6029fcf5ef2aSThomas Huth 6030fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6031fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6032fcf5ef2aSThomas Huth { 6033fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6034fcf5ef2aSThomas Huth GEN_PRIV; 6035fcf5ef2aSThomas Huth #else 6036fcf5ef2aSThomas Huth TCGv t0; 6037fcf5ef2aSThomas Huth 6038fcf5ef2aSThomas Huth CHK_SV; 6039fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6040fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6041fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6042fcf5ef2aSThomas Huth } else { 6043fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6044fcf5ef2aSThomas Huth } 6045fcf5ef2aSThomas Huth 6046fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6047fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6048fcf5ef2aSThomas Huth tcg_temp_free(t0); 6049fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6050fcf5ef2aSThomas Huth } 6051fcf5ef2aSThomas Huth 6052fcf5ef2aSThomas Huth /* tlbwe */ 6053fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6054fcf5ef2aSThomas Huth { 6055fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6056fcf5ef2aSThomas Huth GEN_PRIV; 6057fcf5ef2aSThomas Huth #else 6058fcf5ef2aSThomas Huth CHK_SV; 6059fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6060fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6061fcf5ef2aSThomas Huth } 6062fcf5ef2aSThomas Huth 6063fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6064fcf5ef2aSThomas Huth { 6065fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6066fcf5ef2aSThomas Huth GEN_PRIV; 6067fcf5ef2aSThomas Huth #else 6068fcf5ef2aSThomas Huth TCGv t0; 6069fcf5ef2aSThomas Huth 6070fcf5ef2aSThomas Huth CHK_SV; 6071fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6072fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6073fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6074fcf5ef2aSThomas Huth tcg_temp_free(t0); 6075fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6076fcf5ef2aSThomas Huth } 6077fcf5ef2aSThomas Huth 6078fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6079fcf5ef2aSThomas Huth { 6080fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6081fcf5ef2aSThomas Huth GEN_PRIV; 6082fcf5ef2aSThomas Huth #else 6083fcf5ef2aSThomas Huth TCGv t0; 6084fcf5ef2aSThomas Huth 6085fcf5ef2aSThomas Huth CHK_SV; 6086fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6087fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6088fcf5ef2aSThomas Huth 6089fcf5ef2aSThomas Huth switch((ctx->opcode >> 21) & 0x3) { 6090fcf5ef2aSThomas Huth case 0: 6091fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6092fcf5ef2aSThomas Huth break; 6093fcf5ef2aSThomas Huth case 1: 6094fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6095fcf5ef2aSThomas Huth break; 6096fcf5ef2aSThomas Huth case 3: 6097fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6098fcf5ef2aSThomas Huth break; 6099fcf5ef2aSThomas Huth default: 6100fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6101fcf5ef2aSThomas Huth break; 6102fcf5ef2aSThomas Huth } 6103fcf5ef2aSThomas Huth 6104fcf5ef2aSThomas Huth tcg_temp_free(t0); 6105fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6106fcf5ef2aSThomas Huth } 6107fcf5ef2aSThomas Huth 6108fcf5ef2aSThomas Huth 6109fcf5ef2aSThomas Huth /* wrtee */ 6110fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6111fcf5ef2aSThomas Huth { 6112fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6113fcf5ef2aSThomas Huth GEN_PRIV; 6114fcf5ef2aSThomas Huth #else 6115fcf5ef2aSThomas Huth TCGv t0; 6116fcf5ef2aSThomas Huth 6117fcf5ef2aSThomas Huth CHK_SV; 6118fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6119fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6120fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6121fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6122fcf5ef2aSThomas Huth tcg_temp_free(t0); 6123fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception 6124fcf5ef2aSThomas Huth * if we just set msr_ee to 1 6125fcf5ef2aSThomas Huth */ 6126fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6127fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6128fcf5ef2aSThomas Huth } 6129fcf5ef2aSThomas Huth 6130fcf5ef2aSThomas Huth /* wrteei */ 6131fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6132fcf5ef2aSThomas Huth { 6133fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6134fcf5ef2aSThomas Huth GEN_PRIV; 6135fcf5ef2aSThomas Huth #else 6136fcf5ef2aSThomas Huth CHK_SV; 6137fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6138fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6139fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6140fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6141fcf5ef2aSThomas Huth } else { 6142fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6143fcf5ef2aSThomas Huth } 6144fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6145fcf5ef2aSThomas Huth } 6146fcf5ef2aSThomas Huth 6147fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6148fcf5ef2aSThomas Huth 6149fcf5ef2aSThomas Huth /* dlmzb */ 6150fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6151fcf5ef2aSThomas Huth { 6152fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6153fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6154fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6155fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6156fcf5ef2aSThomas Huth } 6157fcf5ef2aSThomas Huth 6158fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6159fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6160fcf5ef2aSThomas Huth { 6161fcf5ef2aSThomas Huth /* interpreted as no-op */ 6162fcf5ef2aSThomas Huth } 6163fcf5ef2aSThomas Huth 6164fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6165fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6166fcf5ef2aSThomas Huth { 6167fcf5ef2aSThomas Huth /* interpreted as no-op */ 6168fcf5ef2aSThomas Huth } 6169fcf5ef2aSThomas Huth 6170fcf5ef2aSThomas Huth /* icbt */ 6171fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6172fcf5ef2aSThomas Huth { 6173fcf5ef2aSThomas Huth /* interpreted as no-op */ 6174fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6175fcf5ef2aSThomas Huth * but does not generate any exception 6176fcf5ef2aSThomas Huth */ 6177fcf5ef2aSThomas Huth } 6178fcf5ef2aSThomas Huth 6179fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6180fcf5ef2aSThomas Huth 6181fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6182fcf5ef2aSThomas Huth { 6183fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6184fcf5ef2aSThomas Huth GEN_PRIV; 6185fcf5ef2aSThomas Huth #else 6186ebca5e6dSCédric Le Goater CHK_HV; 61877af1e7b0SCédric Le Goater /* 64-bit server processors compliant with arch 2.x */ 61887af1e7b0SCédric Le Goater if (ctx->insns_flags & PPC_SEGMENT_64B) { 61897af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 61907af1e7b0SCédric Le Goater } else { 6191fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 61927af1e7b0SCédric Le Goater } 6193fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6194fcf5ef2aSThomas Huth } 6195fcf5ef2aSThomas Huth 6196fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6197fcf5ef2aSThomas Huth { 6198fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6199fcf5ef2aSThomas Huth GEN_PRIV; 6200fcf5ef2aSThomas Huth #else 6201ebca5e6dSCédric Le Goater CHK_HV; 62027af1e7b0SCédric Le Goater /* 64-bit server processors compliant with arch 2.x */ 62037af1e7b0SCédric Le Goater if (ctx->insns_flags & PPC_SEGMENT_64B) { 62047af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 62057af1e7b0SCédric Le Goater } else { 6206fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 62077af1e7b0SCédric Le Goater } 6208fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6209fcf5ef2aSThomas Huth } 6210fcf5ef2aSThomas Huth 62117af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 62127af1e7b0SCédric Le Goater { 62137af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 62147af1e7b0SCédric Le Goater GEN_PRIV; 62157af1e7b0SCédric Le Goater #else 62167af1e7b0SCédric Le Goater CHK_HV; 62177af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 62187af1e7b0SCédric Le Goater /* interpreted as no-op */ 62197af1e7b0SCédric Le Goater } 6220fcf5ef2aSThomas Huth 6221fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6222fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6223fcf5ef2aSThomas Huth { 6224fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6225fcf5ef2aSThomas Huth 6226fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6227fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6228fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6229fcf5ef2aSThomas Huth } 6230fcf5ef2aSThomas Huth 6231fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6232fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6233fcf5ef2aSThomas Huth { 6234fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6235fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6236fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6237fcf5ef2aSThomas Huth 6238fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6239fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6240fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6241fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6242fcf5ef2aSThomas Huth } else { 6243fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6244fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6245fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6246fcf5ef2aSThomas Huth } 6247fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6248fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6249fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6250fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6251fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6252fcf5ef2aSThomas Huth } 6253fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6254fcf5ef2aSThomas Huth 6255fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6256fcf5ef2aSThomas Huth { 6257fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6258fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6259fcf5ef2aSThomas Huth return; 6260fcf5ef2aSThomas Huth } 6261fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6262fcf5ef2aSThomas Huth } 6263fcf5ef2aSThomas Huth 6264fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6265fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6266fcf5ef2aSThomas Huth { \ 6267fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6268fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6269fcf5ef2aSThomas Huth return; \ 6270fcf5ef2aSThomas Huth } \ 6271fcf5ef2aSThomas Huth /* Because tbegin always fails in QEMU, these user \ 6272fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6273fcf5ef2aSThomas Huth * \ 6274fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6275fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6276fcf5ef2aSThomas Huth */ \ 6277fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6278fcf5ef2aSThomas Huth } 6279fcf5ef2aSThomas Huth 6280fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6281fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6282fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6283fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6284fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6285fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6286fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6287b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6288b8b4576eSSuraj Jitindar Singh { 6289b8b4576eSSuraj Jitindar Singh // Do Nothing 6290b8b4576eSSuraj Jitindar Singh } 6291fcf5ef2aSThomas Huth 629280b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 629380b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 629480b8c1eeSNikunj A Dadhania { \ 629580b8c1eeSNikunj A Dadhania /* Generate invalid exception until \ 629680b8c1eeSNikunj A Dadhania * we have an implementation of the copy \ 629780b8c1eeSNikunj A Dadhania * paste facility \ 629880b8c1eeSNikunj A Dadhania */ \ 629980b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 630080b8c1eeSNikunj A Dadhania } 630180b8c1eeSNikunj A Dadhania 630280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 630380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 630480b8c1eeSNikunj A Dadhania 6305fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6306fcf5ef2aSThomas Huth { 6307fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6308fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6309fcf5ef2aSThomas Huth return; 6310fcf5ef2aSThomas Huth } 6311fcf5ef2aSThomas Huth /* Because tbegin always fails, the tcheck implementation 6312fcf5ef2aSThomas Huth * is simple: 6313fcf5ef2aSThomas Huth * 6314fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6315fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6316fcf5ef2aSThomas Huth */ 6317fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6318fcf5ef2aSThomas Huth } 6319fcf5ef2aSThomas Huth 6320fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6321fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6322fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6323fcf5ef2aSThomas Huth { \ 6324fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6325fcf5ef2aSThomas Huth } 6326fcf5ef2aSThomas Huth 6327fcf5ef2aSThomas Huth #else 6328fcf5ef2aSThomas Huth 6329fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6330fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6331fcf5ef2aSThomas Huth { \ 6332fcf5ef2aSThomas Huth CHK_SV; \ 6333fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6334fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6335fcf5ef2aSThomas Huth return; \ 6336fcf5ef2aSThomas Huth } \ 6337fcf5ef2aSThomas Huth /* Because tbegin always fails, the implementation is \ 6338fcf5ef2aSThomas Huth * simple: \ 6339fcf5ef2aSThomas Huth * \ 6340fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6341fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6342fcf5ef2aSThomas Huth */ \ 6343fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6344fcf5ef2aSThomas Huth } 6345fcf5ef2aSThomas Huth 6346fcf5ef2aSThomas Huth #endif 6347fcf5ef2aSThomas Huth 6348fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6349fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6350fcf5ef2aSThomas Huth 6351fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6352fcf5ef2aSThomas Huth 6353fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6354fcf5ef2aSThomas Huth 6355fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6356fcf5ef2aSThomas Huth 6357fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6358fcf5ef2aSThomas Huth 6359fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6360fcf5ef2aSThomas Huth 63615cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 63625cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 63635cb091a4SNikunj A Dadhania { 63645cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 63655cb091a4SNikunj A Dadhania case 0: /* lfdp */ 63665cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 63675cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 63685cb091a4SNikunj A Dadhania } 63695cb091a4SNikunj A Dadhania break; 63705cb091a4SNikunj A Dadhania case 2: /* lxsd */ 63715cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 63725cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 63735cb091a4SNikunj A Dadhania } 63745cb091a4SNikunj A Dadhania break; 63755cb091a4SNikunj A Dadhania case 3: /* lxssp */ 63765cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 63775cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 63785cb091a4SNikunj A Dadhania } 63795cb091a4SNikunj A Dadhania break; 63805cb091a4SNikunj A Dadhania } 63815cb091a4SNikunj A Dadhania return gen_invalid(ctx); 63825cb091a4SNikunj A Dadhania } 63835cb091a4SNikunj A Dadhania 6384d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6385e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6386e3001664SNikunj A Dadhania { 6387e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6388e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6389e3001664SNikunj A Dadhania case 1: /* lxv */ 6390d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6391d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6392d59ba583SNikunj A Dadhania } 6393e3001664SNikunj A Dadhania break; 6394e3001664SNikunj A Dadhania case 5: /* stxv */ 6395d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6396d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6397d59ba583SNikunj A Dadhania } 6398e3001664SNikunj A Dadhania break; 6399e3001664SNikunj A Dadhania } 6400e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6401e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6402e3001664SNikunj A Dadhania case 0: /* stfdp */ 6403e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6404e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6405e3001664SNikunj A Dadhania } 6406e3001664SNikunj A Dadhania break; 6407e3001664SNikunj A Dadhania case 2: /* stxsd */ 6408e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6409e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6410e3001664SNikunj A Dadhania } 6411e3001664SNikunj A Dadhania break; 6412e3001664SNikunj A Dadhania case 3: /* stxssp */ 6413e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6414e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6415e3001664SNikunj A Dadhania } 6416e3001664SNikunj A Dadhania break; 6417e3001664SNikunj A Dadhania } 6418e3001664SNikunj A Dadhania } 6419e3001664SNikunj A Dadhania return gen_invalid(ctx); 6420e3001664SNikunj A Dadhania } 6421e3001664SNikunj A Dadhania 6422fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6423fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6424fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6425fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6426fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6427fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6428fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6429fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6430fcf5ef2aSThomas Huth #endif 6431fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6432fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6433fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6434fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6435fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6436fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6437fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6438fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6439fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6440fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6441fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6442fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6443fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6444fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6445fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6446fcf5ef2aSThomas Huth #endif 6447fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6448fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6449fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6450fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6451fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6452fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6453fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 645480b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6455b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 645680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6457fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6458fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6459fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6460fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6461fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6462fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6463fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6464fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6465fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6466fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6467fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6468fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6469fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6470fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6471fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6472fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6473fcf5ef2aSThomas Huth #endif 6474fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6475fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6476fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6477fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6478fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6479fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6480fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6481fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6482fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6483fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6484fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6485fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6486fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6487fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6488fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6489fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6490fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6491fcf5ef2aSThomas Huth #endif 6492fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6493fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6494fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6495fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6496fcf5ef2aSThomas Huth #endif 64975cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 64985cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6499d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6500e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6501fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6502fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6503fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6504fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6505fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6506fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6507*c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6508fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6509fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6510fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6511fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6512a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6513a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6514fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6515fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6516fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6517fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6518a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6519a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6520fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6521fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6522fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6523fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6524fcf5ef2aSThomas Huth #endif 6525fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6526fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6527c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6528fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6529fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6530fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6531fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6532fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6533fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6534fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6535fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6536fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6537cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6538fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6539fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6540fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6541fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6542fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6543fcf5ef2aSThomas Huth #endif 6544fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6545fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6546fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6547fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6548fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6549fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6550fcf5ef2aSThomas Huth #endif 6551fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6552fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6553fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6554fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6555fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6556fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6557fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6558fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6559fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6560b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6561fcf5ef2aSThomas Huth #endif 6562fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6563fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6564fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6565fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6566fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6567fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6568fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6569fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6570fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6571fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 657299d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6573fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6574fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6575fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6576fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6577fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6578fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6579fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6580fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6581fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6582fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6583fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6584fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6585fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6586fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6587fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6588fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6589fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6590fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6591fcf5ef2aSThomas Huth #endif 6592fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6593fcf5ef2aSThomas Huth /* XXX Those instructions will need to be handled differently for 6594fcf5ef2aSThomas Huth * different ISA versions */ 6595fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6596fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6597c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 6598c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 6599fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6600fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6601fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6602fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6603a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 660462d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6605fcf5ef2aSThomas Huth #endif 6606fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6607fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6608fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6609fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6610fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6611fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6612fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6613fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6614fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6615fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6616fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6617fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6618fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6619fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6620fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6621fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6622fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6623fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6624fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6625fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6626fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6627fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6628fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6629fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6630fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6631fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6632fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6633fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6634fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6635fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6636fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6637fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6638fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6639fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6640fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6641fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6642fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6643fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6644fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6645fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6646fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6647fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6648fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6649fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6650fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6651fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6652fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6653fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6654fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6655fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6656fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6657fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6658fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6659fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6660fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6661fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6662fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6663fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6664fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6665fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6666fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6667fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6668fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6669fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6670fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6671fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6672fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6673fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6674fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6675fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6676fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6677fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6678fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6679fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6680fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6681fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6682fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6683fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6684fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6685fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6686fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6687fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6688fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6689fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6690fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6691fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6692fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6693fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6694fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6695fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6696fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6697fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6698fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6699fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 67007af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 67017af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 6702fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6703fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6704fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6705fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6706fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6707fcf5ef2aSThomas Huth GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6708fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6709fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6710fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6711fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6712fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6713fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6714fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6715fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6716fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6717fcf5ef2aSThomas Huth PPC2_ISA300), 6718fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6719fcf5ef2aSThomas Huth #endif 6720fcf5ef2aSThomas Huth 6721fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6722fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6723fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6724fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6725fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6726fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6727fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6728fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6729fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6730fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6731fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6732fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6733fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6734fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6735fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6736fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6737fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6738fcf5ef2aSThomas Huth 6739fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6740fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6741fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6742fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6743fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6744fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6745fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6746fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6747fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6748fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6749fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6750fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6751fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6752fcf5ef2aSThomas Huth 6753fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6754fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6755fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6756fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6757fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6758fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6759fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6760fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6761fcf5ef2aSThomas Huth 6762fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6763fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6764fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6765fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6766fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6767fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6768fcf5ef2aSThomas Huth 6769fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6770fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6771fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6772fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6773fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6774fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6775fcf5ef2aSThomas Huth #endif 6776fcf5ef2aSThomas Huth 6777fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6778fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6779fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6780fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6781fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6782fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6783fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6784fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6785fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6786fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6787fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6788fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6789fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6790fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6791fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6792fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6793fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6794fcf5ef2aSThomas Huth 6795fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6796fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6797fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6798fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6799fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6800fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6801fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6802fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6803fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6804fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6805fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6806fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6807fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6808fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6809fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6810fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6811fcf5ef2aSThomas Huth #endif 6812fcf5ef2aSThomas Huth 6813fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6814fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6815fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6816fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6817fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6818fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6819fcf5ef2aSThomas Huth PPC_64B) 6820fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6821fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6822fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6823fcf5ef2aSThomas Huth PPC_64B), \ 6824fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6825fcf5ef2aSThomas Huth PPC_64B), \ 6826fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6827fcf5ef2aSThomas Huth PPC_64B) 6828fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6829fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6830fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6831fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6832fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6833fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6834fcf5ef2aSThomas Huth #endif 6835fcf5ef2aSThomas Huth 6836fcf5ef2aSThomas Huth #undef GEN_LD 6837fcf5ef2aSThomas Huth #undef GEN_LDU 6838fcf5ef2aSThomas Huth #undef GEN_LDUX 6839fcf5ef2aSThomas Huth #undef GEN_LDX_E 6840fcf5ef2aSThomas Huth #undef GEN_LDS 6841fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 6842fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6843fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 6844fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 6845fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 6846fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6847fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6848fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6849fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 6850fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 6851fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 6852fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 6853fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 6854fcf5ef2aSThomas Huth 6855fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 6856fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 6857fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 6858fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 6859fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6860fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 6861fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 6862fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 6863fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 6864fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6865fcf5ef2aSThomas Huth 6866fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6867fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6868fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6869fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6870fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6871fcf5ef2aSThomas Huth #endif 6872fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6873fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6874fcf5ef2aSThomas Huth 6875fcf5ef2aSThomas Huth #undef GEN_ST 6876fcf5ef2aSThomas Huth #undef GEN_STU 6877fcf5ef2aSThomas Huth #undef GEN_STUX 6878fcf5ef2aSThomas Huth #undef GEN_STX_E 6879fcf5ef2aSThomas Huth #undef GEN_STS 6880fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 6881fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6882fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 6883fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 6884fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 6885fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6886fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6887fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6888fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 6889fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 6890fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 6891fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 6892fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 6893fcf5ef2aSThomas Huth 6894fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 6895fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 6896fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 6897fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6898fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 6899fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 6900fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6901fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6902fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6903fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6904fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6905fcf5ef2aSThomas Huth #endif 6906fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6907fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6908fcf5ef2aSThomas Huth 6909fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6910fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6911fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6912fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6913fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6914fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6915fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6916fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6917fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6918fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6919fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6920fcf5ef2aSThomas Huth 6921fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6922fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6923fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6924fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6925fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6926fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6927fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6928fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6929fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6930fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6931fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6932fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6933fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6934fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6935fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6936fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6937fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6938fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6939fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6940fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6941fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6942fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6943fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6944fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6945fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6946fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6947fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6948fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6949fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6950fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6951fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6952fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6953fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6954fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6955fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6956fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6957fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6958fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6959fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6960fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6961fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6962fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6963fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6964fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6965fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6966fcf5ef2aSThomas Huth 6967fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6968fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6969fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6970fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6971fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6972fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6973fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6974fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6975fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6976fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6977fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6978fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6979fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6980fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6981fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6982fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6983fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6984fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6985fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6986fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6987fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6988fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6989fcf5ef2aSThomas Huth 6990fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 6991fcf5ef2aSThomas Huth 6992fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 6993fcf5ef2aSThomas Huth 6994fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 6995fcf5ef2aSThomas Huth 6996fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 6997fcf5ef2aSThomas Huth 6998fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 6999fcf5ef2aSThomas Huth }; 7000fcf5ef2aSThomas Huth 7001fcf5ef2aSThomas Huth #include "helper_regs.h" 70025b27a92dSPaolo Bonzini #include "translate_init.inc.c" 7003fcf5ef2aSThomas Huth 7004fcf5ef2aSThomas Huth /*****************************************************************************/ 7005fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 7006fcf5ef2aSThomas Huth void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 7007fcf5ef2aSThomas Huth int flags) 7008fcf5ef2aSThomas Huth { 7009fcf5ef2aSThomas Huth #define RGPL 4 7010fcf5ef2aSThomas Huth #define RFPL 4 7011fcf5ef2aSThomas Huth 7012fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7013fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 7014fcf5ef2aSThomas Huth int i; 7015fcf5ef2aSThomas Huth 7016fcf5ef2aSThomas Huth cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7017fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7018fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 7019fcf5ef2aSThomas Huth cs->cpu_index); 7020fcf5ef2aSThomas Huth cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7021fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 7022fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 7023fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 7024fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 7025fcf5ef2aSThomas Huth cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7026fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7027fcf5ef2aSThomas Huth " DECR %08" PRIu32 7028fcf5ef2aSThomas Huth #endif 7029fcf5ef2aSThomas Huth "\n", 7030fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7031fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7032fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 7033fcf5ef2aSThomas Huth #endif 7034fcf5ef2aSThomas Huth ); 7035fcf5ef2aSThomas Huth #endif 7036fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7037fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == 0) 7038fcf5ef2aSThomas Huth cpu_fprintf(f, "GPR%02d", i); 7039fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7040fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == (RGPL - 1)) 7041fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7042fcf5ef2aSThomas Huth } 7043fcf5ef2aSThomas Huth cpu_fprintf(f, "CR "); 7044fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 7045fcf5ef2aSThomas Huth cpu_fprintf(f, "%01x", env->crf[i]); 7046fcf5ef2aSThomas Huth cpu_fprintf(f, " ["); 7047fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 7048fcf5ef2aSThomas Huth char a = '-'; 7049fcf5ef2aSThomas Huth if (env->crf[i] & 0x08) 7050fcf5ef2aSThomas Huth a = 'L'; 7051fcf5ef2aSThomas Huth else if (env->crf[i] & 0x04) 7052fcf5ef2aSThomas Huth a = 'G'; 7053fcf5ef2aSThomas Huth else if (env->crf[i] & 0x02) 7054fcf5ef2aSThomas Huth a = 'E'; 7055fcf5ef2aSThomas Huth cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7056fcf5ef2aSThomas Huth } 7057fcf5ef2aSThomas Huth cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7058fcf5ef2aSThomas Huth env->reserve_addr); 7059685f1ce2SRichard Henderson 7060685f1ce2SRichard Henderson if (flags & CPU_DUMP_FPU) { 7061fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7062685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == 0) { 7063fcf5ef2aSThomas Huth cpu_fprintf(f, "FPR%02d", i); 7064685f1ce2SRichard Henderson } 7065fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 7066685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == (RFPL - 1)) { 7067fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7068fcf5ef2aSThomas Huth } 7069685f1ce2SRichard Henderson } 7070fcf5ef2aSThomas Huth cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7071685f1ce2SRichard Henderson } 7072685f1ce2SRichard Henderson 7073fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7074fcf5ef2aSThomas Huth cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7075fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7076fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7077fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7078fcf5ef2aSThomas Huth 7079fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7080fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7081fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7082fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7083fcf5ef2aSThomas Huth 7084fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7085fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7086fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7087fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7088fcf5ef2aSThomas Huth 7089fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7090fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7091fcf5ef2aSThomas Huth env->excp_model == POWERPC_EXCP_POWER8) { 7092fcf5ef2aSThomas Huth cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7093fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7094fcf5ef2aSThomas Huth } 7095fcf5ef2aSThomas Huth #endif 7096fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 7097fcf5ef2aSThomas Huth cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7098fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7099fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7100fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7101fcf5ef2aSThomas Huth 7102fcf5ef2aSThomas Huth cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7103fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7104fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7105fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7106fcf5ef2aSThomas Huth 7107fcf5ef2aSThomas Huth cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7108fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7109fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7110fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7111fcf5ef2aSThomas Huth 7112fcf5ef2aSThomas Huth cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7113fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7114fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7115fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7116fcf5ef2aSThomas Huth 7117fcf5ef2aSThomas Huth /* FSL-specific */ 7118fcf5ef2aSThomas Huth cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7119fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7120fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7121fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7122fcf5ef2aSThomas Huth 7123fcf5ef2aSThomas Huth /* 7124fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7125fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7126fcf5ef2aSThomas Huth */ 7127fcf5ef2aSThomas Huth } 7128fcf5ef2aSThomas Huth 7129fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7130fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 7131fcf5ef2aSThomas Huth cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7132fcf5ef2aSThomas Huth } 7133fcf5ef2aSThomas Huth #endif 7134fcf5ef2aSThomas Huth 7135d801a61eSSuraj Jitindar Singh if (env->spr_cb[SPR_LPCR].name) 7136d801a61eSSuraj Jitindar Singh cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7137d801a61eSSuraj Jitindar Singh 71380941d728SDavid Gibson switch (env->mmu_model) { 7139fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7140fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7141fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7142fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7143fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 71440941d728SDavid Gibson case POWERPC_MMU_64B: 71450941d728SDavid Gibson case POWERPC_MMU_2_03: 71460941d728SDavid Gibson case POWERPC_MMU_2_06: 71470941d728SDavid Gibson case POWERPC_MMU_2_07: 71480941d728SDavid Gibson case POWERPC_MMU_3_00: 7149fcf5ef2aSThomas Huth #endif 71504f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 71514f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 71524f4f28ffSSuraj Jitindar Singh } 71534a7518e0SCédric Le Goater if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 71544a7518e0SCédric Le Goater cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 71554a7518e0SCédric Le Goater } 71564f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7157fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7158fcf5ef2aSThomas Huth break; 7159fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 7160fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7161fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7162fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7163fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7164fcf5ef2aSThomas Huth 7165fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7166fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7167fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7168fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7169fcf5ef2aSThomas Huth 7170fcf5ef2aSThomas Huth cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7171fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7172fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7173fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7174fcf5ef2aSThomas Huth break; 7175fcf5ef2aSThomas Huth default: 7176fcf5ef2aSThomas Huth break; 7177fcf5ef2aSThomas Huth } 7178fcf5ef2aSThomas Huth #endif 7179fcf5ef2aSThomas Huth 7180fcf5ef2aSThomas Huth #undef RGPL 7181fcf5ef2aSThomas Huth #undef RFPL 7182fcf5ef2aSThomas Huth } 7183fcf5ef2aSThomas Huth 7184fcf5ef2aSThomas Huth void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7185fcf5ef2aSThomas Huth fprintf_function cpu_fprintf, int flags) 7186fcf5ef2aSThomas Huth { 7187fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7188fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7189fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7190fcf5ef2aSThomas Huth int op1, op2, op3; 7191fcf5ef2aSThomas Huth 7192fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7193fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7194fcf5ef2aSThomas Huth handler = t1[op1]; 7195fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7196fcf5ef2aSThomas Huth t2 = ind_table(handler); 7197fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7198fcf5ef2aSThomas Huth handler = t2[op2]; 7199fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7200fcf5ef2aSThomas Huth t3 = ind_table(handler); 7201fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7202fcf5ef2aSThomas Huth handler = t3[op3]; 7203fcf5ef2aSThomas Huth if (handler->count == 0) 7204fcf5ef2aSThomas Huth continue; 7205fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7206fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7207fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7208fcf5ef2aSThomas Huth handler->oname, 7209fcf5ef2aSThomas Huth handler->count, handler->count); 7210fcf5ef2aSThomas Huth } 7211fcf5ef2aSThomas Huth } else { 7212fcf5ef2aSThomas Huth if (handler->count == 0) 7213fcf5ef2aSThomas Huth continue; 7214fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7215fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7216fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7217fcf5ef2aSThomas Huth handler->count, handler->count); 7218fcf5ef2aSThomas Huth } 7219fcf5ef2aSThomas Huth } 7220fcf5ef2aSThomas Huth } else { 7221fcf5ef2aSThomas Huth if (handler->count == 0) 7222fcf5ef2aSThomas Huth continue; 7223fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7224fcf5ef2aSThomas Huth " %" PRId64 "\n", 7225fcf5ef2aSThomas Huth op1, op1, handler->oname, 7226fcf5ef2aSThomas Huth handler->count, handler->count); 7227fcf5ef2aSThomas Huth } 7228fcf5ef2aSThomas Huth } 7229fcf5ef2aSThomas Huth #endif 7230fcf5ef2aSThomas Huth } 7231fcf5ef2aSThomas Huth 7232b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7233fcf5ef2aSThomas Huth { 7234b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 72359c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 7236b0c2d521SEmilio G. Cota int bound; 7237fcf5ef2aSThomas Huth 7238b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 7239b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 7240b0c2d521SEmilio G. Cota ctx->pr = msr_pr; 7241b0c2d521SEmilio G. Cota ctx->mem_idx = env->dmmu_idx; 7242b0c2d521SEmilio G. Cota ctx->dr = msr_dr; 7243fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7244b0c2d521SEmilio G. Cota ctx->hv = msr_hv || !env->has_hv_mode; 7245fcf5ef2aSThomas Huth #endif 7246b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7247b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7248b0c2d521SEmilio G. Cota ctx->access_type = -1; 7249b0c2d521SEmilio G. Cota ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7250b0c2d521SEmilio G. Cota ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7251b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7252fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7253b0c2d521SEmilio G. Cota ctx->sf_mode = msr_is_64bit(env, env->msr); 7254b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7255fcf5ef2aSThomas Huth #endif 7256e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7257e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 7258e69ba2b4SDavid Gibson || (env->mmu_model & POWERPC_MMU_64B); 7259fcf5ef2aSThomas Huth 7260b0c2d521SEmilio G. Cota ctx->fpu_enabled = !!msr_fp; 7261fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7262b0c2d521SEmilio G. Cota ctx->spe_enabled = !!msr_spe; 7263fcf5ef2aSThomas Huth else 7264b0c2d521SEmilio G. Cota ctx->spe_enabled = false; 7265fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7266b0c2d521SEmilio G. Cota ctx->altivec_enabled = !!msr_vr; 7267fcf5ef2aSThomas Huth else 7268b0c2d521SEmilio G. Cota ctx->altivec_enabled = false; 7269fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7270b0c2d521SEmilio G. Cota ctx->vsx_enabled = !!msr_vsx; 7271fcf5ef2aSThomas Huth } else { 7272b0c2d521SEmilio G. Cota ctx->vsx_enabled = false; 7273fcf5ef2aSThomas Huth } 7274fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7275fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7276b0c2d521SEmilio G. Cota ctx->tm_enabled = !!msr_tm; 7277fcf5ef2aSThomas Huth } else { 7278b0c2d521SEmilio G. Cota ctx->tm_enabled = false; 7279fcf5ef2aSThomas Huth } 7280fcf5ef2aSThomas Huth #endif 7281b0c2d521SEmilio G. Cota ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7282fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7283b0c2d521SEmilio G. Cota ctx->singlestep_enabled = CPU_SINGLE_STEP; 7284fcf5ef2aSThomas Huth else 7285b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 7286fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7287b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7288b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7289b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7290fcf5ef2aSThomas Huth } 7291fcf5ef2aSThomas Huth #if defined (DO_SINGLE_STEP) && 0 7292fcf5ef2aSThomas Huth /* Single step trace mode */ 7293fcf5ef2aSThomas Huth msr_se = 1; 7294fcf5ef2aSThomas Huth #endif 7295b0c2d521SEmilio G. Cota 7296b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7297b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7298fcf5ef2aSThomas Huth } 7299fcf5ef2aSThomas Huth 7300b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7301b0c2d521SEmilio G. Cota { 7302b0c2d521SEmilio G. Cota } 7303fcf5ef2aSThomas Huth 7304b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7305b0c2d521SEmilio G. Cota { 7306b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7307b0c2d521SEmilio G. Cota } 7308b0c2d521SEmilio G. Cota 7309b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7310b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 7311b0c2d521SEmilio G. Cota { 7312b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7313b0c2d521SEmilio G. Cota 7314b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 7315fcf5ef2aSThomas Huth /* The address covered by the breakpoint must be included in 7316fcf5ef2aSThomas Huth [tb->pc, tb->pc + tb->size) in order to for it to be 7317fcf5ef2aSThomas Huth properly cleared -- thus we increment the PC here so that 7318fcf5ef2aSThomas Huth the logic setting tb->size below does the right thing. */ 7319b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7320b0c2d521SEmilio G. Cota return true; 7321fcf5ef2aSThomas Huth } 7322fcf5ef2aSThomas Huth 7323b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7324b0c2d521SEmilio G. Cota { 7325b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7326b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 7327b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 7328b0c2d521SEmilio G. Cota 7329fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7330fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7331b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7332b0c2d521SEmilio G. Cota 7333b0c2d521SEmilio G. Cota if (unlikely(need_byteswap(ctx))) { 7334b0c2d521SEmilio G. Cota ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); 7335fcf5ef2aSThomas Huth } else { 7336b0c2d521SEmilio G. Cota ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); 7337fcf5ef2aSThomas Huth } 7338fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7339b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7340b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7341b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 7342b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7343fcf5ef2aSThomas Huth table = env->opcodes; 7344b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 7345fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7346fcf5ef2aSThomas Huth table = ind_table(handler); 7347b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 7348fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7349fcf5ef2aSThomas Huth table = ind_table(handler); 7350b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 7351fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7352fcf5ef2aSThomas Huth table = ind_table(handler); 7353b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 7354fcf5ef2aSThomas Huth } 7355fcf5ef2aSThomas Huth } 7356fcf5ef2aSThomas Huth } 7357fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7358fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7359fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7360fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7361fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7362b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7363b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7364b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7365fcf5ef2aSThomas Huth } else { 7366fcf5ef2aSThomas Huth uint32_t inval; 7367fcf5ef2aSThomas Huth 7368b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7369b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 7370fcf5ef2aSThomas Huth inval = handler->inval2; 7371fcf5ef2aSThomas Huth } else { 7372fcf5ef2aSThomas Huth inval = handler->inval1; 7373fcf5ef2aSThomas Huth } 7374fcf5ef2aSThomas Huth 7375b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 7376fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7377fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7378b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 7379b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7380b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7381b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4); 7382b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7383b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 7384b0c2d521SEmilio G. Cota return; 7385fcf5ef2aSThomas Huth } 7386fcf5ef2aSThomas Huth } 7387b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 7388fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7389fcf5ef2aSThomas Huth handler->count++; 7390fcf5ef2aSThomas Huth #endif 7391fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7392b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7393b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7394b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 7395b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 7396b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 7397b0c2d521SEmilio G. Cota gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next); 7398fcf5ef2aSThomas Huth } 7399b0c2d521SEmilio G. Cota 7400fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7401b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7402b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7403b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7404fcf5ef2aSThomas Huth } 7405b0c2d521SEmilio G. Cota 7406b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7407b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 7408fcf5ef2aSThomas Huth } 7409b0c2d521SEmilio G. Cota 7410b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7411b0c2d521SEmilio G. Cota { 7412b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7413b0c2d521SEmilio G. Cota 7414b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 7415b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 7416b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7417b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7418b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 7419fcf5ef2aSThomas Huth } 7420fcf5ef2aSThomas Huth /* Generate the return instruction */ 742107ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7422fcf5ef2aSThomas Huth } 7423fcf5ef2aSThomas Huth } 7424b0c2d521SEmilio G. Cota 7425b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7426b0c2d521SEmilio G. Cota { 7427b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7428b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7429b0c2d521SEmilio G. Cota } 7430b0c2d521SEmilio G. Cota 7431b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7432b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7433b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7434b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7435b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 7436b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7437b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7438b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7439b0c2d521SEmilio G. Cota }; 7440b0c2d521SEmilio G. Cota 7441b0c2d521SEmilio G. Cota void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 7442b0c2d521SEmilio G. Cota { 7443b0c2d521SEmilio G. Cota DisasContext ctx; 7444b0c2d521SEmilio G. Cota 7445b0c2d521SEmilio G. Cota translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); 7446fcf5ef2aSThomas Huth } 7447fcf5ef2aSThomas Huth 7448fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7449fcf5ef2aSThomas Huth target_ulong *data) 7450fcf5ef2aSThomas Huth { 7451fcf5ef2aSThomas Huth env->nip = data[0]; 7452fcf5ef2aSThomas Huth } 7453