1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39eeaaefe9SLeandro Lupori #include "power8-pmu.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44d53106c9SRichard Henderson #define HELPER_H "helper.h" 45d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 46d53106c9SRichard Henderson #undef HELPER_H 47d53106c9SRichard Henderson 48fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 49fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 50fcf5ef2aSThomas Huth 51fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 52efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 53fcf5ef2aSThomas Huth 54fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56fcf5ef2aSThomas Huth #else 57fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 58fcf5ef2aSThomas Huth #endif 59fcf5ef2aSThomas Huth /*****************************************************************************/ 60fcf5ef2aSThomas Huth /* Code translation helpers */ 61fcf5ef2aSThomas Huth 62fcf5ef2aSThomas Huth /* global register indexes */ 63fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 65fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 66fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 67fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 68fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 69fcf5ef2aSThomas Huth static TCGv cpu_nip; 70fcf5ef2aSThomas Huth static TCGv cpu_msr; 71fcf5ef2aSThomas Huth static TCGv cpu_ctr; 72fcf5ef2aSThomas Huth static TCGv cpu_lr; 73fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 74fcf5ef2aSThomas Huth static TCGv cpu_cfar; 75fcf5ef2aSThomas Huth #endif 76dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77fcf5ef2aSThomas Huth static TCGv cpu_reserve; 78392d328aSNicholas Piggin static TCGv cpu_reserve_length; 79253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 80894448aeSRichard Henderson static TCGv cpu_reserve_val2; 81fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 82fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 83fcf5ef2aSThomas Huth 84fcf5ef2aSThomas Huth void ppc_translate_init(void) 85fcf5ef2aSThomas Huth { 86fcf5ef2aSThomas Huth int i; 87fcf5ef2aSThomas Huth char *p; 88fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth p = cpu_reg_names; 91fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 92fcf5ef2aSThomas Huth 93fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 94fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 95fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 97fcf5ef2aSThomas Huth p += 5; 98fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 99fcf5ef2aSThomas Huth } 100fcf5ef2aSThomas Huth 101fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 103fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 107fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 108fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 110fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 111fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 112fcf5ef2aSThomas Huth } 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 124fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 127fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 128fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 129fcf5ef2aSThomas Huth #endif 130fcf5ef2aSThomas Huth 131fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 133fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 135fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 137fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 138fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 139dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 141dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 142dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 145fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 146fcf5ef2aSThomas Huth "reserve_addr"); 147392d328aSNicholas Piggin cpu_reserve_length = tcg_global_mem_new(cpu_env, 148392d328aSNicholas Piggin offsetof(CPUPPCState, 149392d328aSNicholas Piggin reserve_length), 150392d328aSNicholas Piggin "reserve_length"); 151253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 152253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 153253ce7b2SNikunj A Dadhania "reserve_val"); 154894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 156894448aeSRichard Henderson "reserve_val2"); 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 159fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 160fcf5ef2aSThomas Huth 161fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 163efe843d8SDavid Gibson "access_type"); 164fcf5ef2aSThomas Huth } 165fcf5ef2aSThomas Huth 166fcf5ef2aSThomas Huth /* internal defines */ 167fcf5ef2aSThomas Huth struct DisasContext { 168b6bac4bcSEmilio G. Cota DisasContextBase base; 1692c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 170fcf5ef2aSThomas Huth uint32_t opcode; 171fcf5ef2aSThomas Huth /* Routine used to access memory */ 172fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 173fcf5ef2aSThomas Huth bool lazy_tlb_flush; 174fcf5ef2aSThomas Huth bool need_access_type; 175fcf5ef2aSThomas Huth int mem_idx; 176fcf5ef2aSThomas Huth int access_type; 177fcf5ef2aSThomas Huth /* Translation flags */ 17814776ab5STony Nguyen MemOp default_tcg_memop_mask; 179fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 180fcf5ef2aSThomas Huth bool sf_mode; 181fcf5ef2aSThomas Huth bool has_cfar; 182fcf5ef2aSThomas Huth #endif 183fcf5ef2aSThomas Huth bool fpu_enabled; 184fcf5ef2aSThomas Huth bool altivec_enabled; 185fcf5ef2aSThomas Huth bool vsx_enabled; 186fcf5ef2aSThomas Huth bool spe_enabled; 187fcf5ef2aSThomas Huth bool tm_enabled; 188c6fd28fdSSuraj Jitindar Singh bool gtse; 1891db3632aSMatheus Ferst bool hr; 190f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 191f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1928b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1938b3d1c49SLeandro Lupori bool pmc_other; 19446d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 195fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196fcf5ef2aSThomas Huth int singlestep_enabled; 1970e3bf489SRoman Kapl uint32_t flags; 198fcf5ef2aSThomas Huth uint64_t insns_flags; 199fcf5ef2aSThomas Huth uint64_t insns_flags2; 200fcf5ef2aSThomas Huth }; 201fcf5ef2aSThomas Huth 202a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206a9b5b3d0SRichard Henderson 207fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 208fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 209fcf5ef2aSThomas Huth { 210ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 211fcf5ef2aSThomas Huth return ctx->le_mode; 212fcf5ef2aSThomas Huth #else 213fcf5ef2aSThomas Huth return !ctx->le_mode; 214fcf5ef2aSThomas Huth #endif 215fcf5ef2aSThomas Huth } 216fcf5ef2aSThomas Huth 217fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 218fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 219fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 220fcf5ef2aSThomas Huth #else 221fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 222fcf5ef2aSThomas Huth #endif 223fcf5ef2aSThomas Huth 224fcf5ef2aSThomas Huth struct opc_handler_t { 225fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226fcf5ef2aSThomas Huth uint32_t inval1; 227fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228fcf5ef2aSThomas Huth uint32_t inval2; 229fcf5ef2aSThomas Huth /* instruction type */ 230fcf5ef2aSThomas Huth uint64_t type; 231fcf5ef2aSThomas Huth /* extended instruction type */ 232fcf5ef2aSThomas Huth uint64_t type2; 233fcf5ef2aSThomas Huth /* handler */ 234fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 235fcf5ef2aSThomas Huth }; 236fcf5ef2aSThomas Huth 237*b769d4c8SNicholas Piggin static inline bool gen_serialize(DisasContext *ctx) 238*b769d4c8SNicholas Piggin { 239*b769d4c8SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 240*b769d4c8SNicholas Piggin /* Restart with exclusive lock. */ 241*b769d4c8SNicholas Piggin gen_helper_exit_atomic(cpu_env); 242*b769d4c8SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 243*b769d4c8SNicholas Piggin return false; 244*b769d4c8SNicholas Piggin } 245*b769d4c8SNicholas Piggin return true; 246*b769d4c8SNicholas Piggin } 247*b769d4c8SNicholas Piggin 248*b769d4c8SNicholas Piggin #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 249*b769d4c8SNicholas Piggin static inline bool gen_serialize_core(DisasContext *ctx) 250*b769d4c8SNicholas Piggin { 251*b769d4c8SNicholas Piggin if (ctx->flags & POWERPC_FLAG_SMT) { 252*b769d4c8SNicholas Piggin return gen_serialize(ctx); 253*b769d4c8SNicholas Piggin } 254*b769d4c8SNicholas Piggin 255*b769d4c8SNicholas Piggin return true; 256*b769d4c8SNicholas Piggin } 257*b769d4c8SNicholas Piggin #endif 258*b769d4c8SNicholas Piggin 2590e3bf489SRoman Kapl /* SPR load/store helpers */ 2600e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2610e3bf489SRoman Kapl { 2620e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2630e3bf489SRoman Kapl } 2640e3bf489SRoman Kapl 2650e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2660e3bf489SRoman Kapl { 2670e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2680e3bf489SRoman Kapl } 2690e3bf489SRoman Kapl 270fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 271fcf5ef2aSThomas Huth { 272fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 273fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 274fcf5ef2aSThomas Huth ctx->access_type = access_type; 275fcf5ef2aSThomas Huth } 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth 278fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 279fcf5ef2aSThomas Huth { 280fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 281fcf5ef2aSThomas Huth nip = (uint32_t)nip; 282fcf5ef2aSThomas Huth } 283fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 284fcf5ef2aSThomas Huth } 285fcf5ef2aSThomas Huth 286fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 287fcf5ef2aSThomas Huth { 288fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 289fcf5ef2aSThomas Huth 290efe843d8SDavid Gibson /* 291efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 292efe843d8SDavid Gibson * faulting instruction 293fcf5ef2aSThomas Huth */ 2942c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2957058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 2967058ff52SRichard Henderson t1 = tcg_constant_i32(error); 297fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 2983d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 299fcf5ef2aSThomas Huth } 300fcf5ef2aSThomas Huth 301fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 302fcf5ef2aSThomas Huth { 303fcf5ef2aSThomas Huth TCGv_i32 t0; 304fcf5ef2aSThomas Huth 305efe843d8SDavid Gibson /* 306efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 307efe843d8SDavid Gibson * faulting instruction 308fcf5ef2aSThomas Huth */ 3092c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 3107058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 311fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3123d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 313fcf5ef2aSThomas Huth } 314fcf5ef2aSThomas Huth 315fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 316fcf5ef2aSThomas Huth target_ulong nip) 317fcf5ef2aSThomas Huth { 318fcf5ef2aSThomas Huth TCGv_i32 t0; 319fcf5ef2aSThomas Huth 320fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 3217058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 322fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3233d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 324fcf5ef2aSThomas Huth } 325fcf5ef2aSThomas Huth 3262fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3272fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3282fdedcbcSMatheus Ferst { 329283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 3302fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3312fdedcbcSMatheus Ferst } 3322fdedcbcSMatheus Ferst #endif 3332fdedcbcSMatheus Ferst 334e150ac89SRoman Kapl /* 335e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 336e150ac89SRoman Kapl * SPR registers for this exception. 337e150ac89SRoman Kapl * 338e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 339e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3400e3bf489SRoman Kapl */ 341e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3420e3bf489SRoman Kapl { 3430e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3440e3bf489SRoman Kapl target_ulong dbsr = 0; 345e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3460e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 347e150ac89SRoman Kapl } else { 348e150ac89SRoman Kapl /* Must have been branch */ 3490e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3500e3bf489SRoman Kapl } 3510e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3520e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3530e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3540e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3550e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3560e3bf489SRoman Kapl } else { 357e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3580e3bf489SRoman Kapl } 3590e3bf489SRoman Kapl } 3600e3bf489SRoman Kapl 361fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 362fcf5ef2aSThomas Huth { 3639498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3643d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 365fcf5ef2aSThomas Huth } 366fcf5ef2aSThomas Huth 367fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 368fcf5ef2aSThomas Huth { 369fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 370fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 371fcf5ef2aSThomas Huth } 372fcf5ef2aSThomas Huth 373fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 374fcf5ef2aSThomas Huth { 375fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 376fcf5ef2aSThomas Huth } 377fcf5ef2aSThomas Huth 378fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 379fcf5ef2aSThomas Huth { 380fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 381fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 382fcf5ef2aSThomas Huth } 383fcf5ef2aSThomas Huth 38437f219c8SBruno Larsen (billionai) /*****************************************************************************/ 38537f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 38637f219c8SBruno Larsen (billionai) 387a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 38837f219c8SBruno Larsen (billionai) { 38937f219c8SBruno Larsen (billionai) #if 0 39037f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 39137f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 39237f219c8SBruno Larsen (billionai) #endif 39337f219c8SBruno Larsen (billionai) } 39437f219c8SBruno Larsen (billionai) 39537f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 39637f219c8SBruno Larsen (billionai) 39737f219c8SBruno Larsen (billionai) /* 39837f219c8SBruno Larsen (billionai) * Generic callbacks: 39937f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 40037f219c8SBruno Larsen (billionai) */ 40137f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 40237f219c8SBruno Larsen (billionai) { 40337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4047058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 40537f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 40637f219c8SBruno Larsen (billionai) #endif 40737f219c8SBruno Larsen (billionai) } 40837f219c8SBruno Larsen (billionai) 409a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 41037f219c8SBruno Larsen (billionai) { 41137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 41237f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 41337f219c8SBruno Larsen (billionai) } 41437f219c8SBruno Larsen (billionai) 41537f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 41637f219c8SBruno Larsen (billionai) { 41737f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4187058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 41937f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 42037f219c8SBruno Larsen (billionai) #endif 42137f219c8SBruno Larsen (billionai) } 42237f219c8SBruno Larsen (billionai) 423a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 42437f219c8SBruno Larsen (billionai) { 42537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 42637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42737f219c8SBruno Larsen (billionai) } 42837f219c8SBruno Larsen (billionai) 429a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43037f219c8SBruno Larsen (billionai) { 43137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43537f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43637f219c8SBruno Larsen (billionai) #else 43737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43837f219c8SBruno Larsen (billionai) #endif 43937f219c8SBruno Larsen (billionai) } 44037f219c8SBruno Larsen (billionai) 441fbda88f7SNicholas Piggin void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 442fbda88f7SNicholas Piggin { 443488aad11SNicholas Piggin /* This does not implement >1 thread */ 444488aad11SNicholas Piggin TCGv t0 = tcg_temp_new(); 445488aad11SNicholas Piggin TCGv t1 = tcg_temp_new(); 446488aad11SNicholas Piggin tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 447488aad11SNicholas Piggin tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 448488aad11SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 449488aad11SNicholas Piggin gen_store_spr(sprn, t1); 450488aad11SNicholas Piggin spr_store_dump_spr(sprn); 451fbda88f7SNicholas Piggin 452fbda88f7SNicholas Piggin /* 453fbda88f7SNicholas Piggin * SPR_CTRL writes must force a new translation block, 454fbda88f7SNicholas Piggin * allowing the PMU to calculate the run latch events with 455fbda88f7SNicholas Piggin * more accuracy. 456fbda88f7SNicholas Piggin */ 457fbda88f7SNicholas Piggin ctx->base.is_jmp = DISAS_EXIT_UPDATE; 458fbda88f7SNicholas Piggin } 459fbda88f7SNicholas Piggin 460fbda88f7SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 461a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 46237f219c8SBruno Larsen (billionai) { 46337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 46437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 46537f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 46637f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 46737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 46837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 46937f219c8SBruno Larsen (billionai) } 47037f219c8SBruno Larsen (billionai) 471a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 47237f219c8SBruno Larsen (billionai) { 47337f219c8SBruno Larsen (billionai) } 47437f219c8SBruno Larsen (billionai) 47537f219c8SBruno Larsen (billionai) #endif 47637f219c8SBruno Larsen (billionai) 47737f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 47837f219c8SBruno Larsen (billionai) /* XER */ 479a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 48037f219c8SBruno Larsen (billionai) { 48137f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 48237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 48337f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 48437f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 48537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 48637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 48737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 48837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 48937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 49037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 49137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 49237f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 49337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 49437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 49537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 49637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 49737f219c8SBruno Larsen (billionai) } 49837f219c8SBruno Larsen (billionai) } 49937f219c8SBruno Larsen (billionai) 500a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 50137f219c8SBruno Larsen (billionai) { 50237f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 50337f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 50437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 50537f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 50637f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 50737f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 50837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 50937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 51037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 51137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 51237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 51337f219c8SBruno Larsen (billionai) } 51437f219c8SBruno Larsen (billionai) 51537f219c8SBruno Larsen (billionai) /* LR */ 516a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 51737f219c8SBruno Larsen (billionai) { 51837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 51937f219c8SBruno Larsen (billionai) } 52037f219c8SBruno Larsen (billionai) 521a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 52237f219c8SBruno Larsen (billionai) { 52337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 52437f219c8SBruno Larsen (billionai) } 52537f219c8SBruno Larsen (billionai) 52637f219c8SBruno Larsen (billionai) /* CFAR */ 52737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 528a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 52937f219c8SBruno Larsen (billionai) { 53037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 53137f219c8SBruno Larsen (billionai) } 53237f219c8SBruno Larsen (billionai) 533a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 53437f219c8SBruno Larsen (billionai) { 53537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 53637f219c8SBruno Larsen (billionai) } 53737f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 53837f219c8SBruno Larsen (billionai) 53937f219c8SBruno Larsen (billionai) /* CTR */ 540a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 54137f219c8SBruno Larsen (billionai) { 54237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 54337f219c8SBruno Larsen (billionai) } 54437f219c8SBruno Larsen (billionai) 545a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 54637f219c8SBruno Larsen (billionai) { 54737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 54837f219c8SBruno Larsen (billionai) } 54937f219c8SBruno Larsen (billionai) 55037f219c8SBruno Larsen (billionai) /* User read access to SPR */ 55137f219c8SBruno Larsen (billionai) /* USPRx */ 55237f219c8SBruno Larsen (billionai) /* UMMCRx */ 55337f219c8SBruno Larsen (billionai) /* UPMCx */ 55437f219c8SBruno Larsen (billionai) /* USIA */ 55537f219c8SBruno Larsen (billionai) /* UDECR */ 556a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 55737f219c8SBruno Larsen (billionai) { 55837f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 55937f219c8SBruno Larsen (billionai) } 56037f219c8SBruno Larsen (billionai) 56137f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 562a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 56337f219c8SBruno Larsen (billionai) { 56437f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 56537f219c8SBruno Larsen (billionai) } 56637f219c8SBruno Larsen (billionai) #endif 56737f219c8SBruno Larsen (billionai) 56837f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 56937f219c8SBruno Larsen (billionai) /* DECR */ 57037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 571a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 57237f219c8SBruno Larsen (billionai) { 573283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 57437f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 57537f219c8SBruno Larsen (billionai) } 57637f219c8SBruno Larsen (billionai) 577a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 57837f219c8SBruno Larsen (billionai) { 579283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 58037f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 58137f219c8SBruno Larsen (billionai) } 58237f219c8SBruno Larsen (billionai) #endif 58337f219c8SBruno Larsen (billionai) 58437f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 58537f219c8SBruno Larsen (billionai) /* Time base */ 586a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 58737f219c8SBruno Larsen (billionai) { 588283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 58937f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 59037f219c8SBruno Larsen (billionai) } 59137f219c8SBruno Larsen (billionai) 592a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 59337f219c8SBruno Larsen (billionai) { 594283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 59537f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 59637f219c8SBruno Larsen (billionai) } 59737f219c8SBruno Larsen (billionai) 598a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 59937f219c8SBruno Larsen (billionai) { 60037f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 60137f219c8SBruno Larsen (billionai) } 60237f219c8SBruno Larsen (billionai) 603a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 60437f219c8SBruno Larsen (billionai) { 60537f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 60637f219c8SBruno Larsen (billionai) } 60737f219c8SBruno Larsen (billionai) 60837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 609a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 61037f219c8SBruno Larsen (billionai) { 611283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 61237f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 61337f219c8SBruno Larsen (billionai) } 61437f219c8SBruno Larsen (billionai) 615a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 61637f219c8SBruno Larsen (billionai) { 617283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 61837f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 61937f219c8SBruno Larsen (billionai) } 62037f219c8SBruno Larsen (billionai) 621a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 62237f219c8SBruno Larsen (billionai) { 62337f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 62437f219c8SBruno Larsen (billionai) } 62537f219c8SBruno Larsen (billionai) 626a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 62737f219c8SBruno Larsen (billionai) { 62837f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 62937f219c8SBruno Larsen (billionai) } 63037f219c8SBruno Larsen (billionai) 63137f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 632a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 63337f219c8SBruno Larsen (billionai) { 634283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 63537f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 63637f219c8SBruno Larsen (billionai) } 63737f219c8SBruno Larsen (billionai) 638a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 63937f219c8SBruno Larsen (billionai) { 640283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 64137f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 64237f219c8SBruno Larsen (billionai) } 64337f219c8SBruno Larsen (billionai) 64437f219c8SBruno Larsen (billionai) /* HDECR */ 645a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 64637f219c8SBruno Larsen (billionai) { 647283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 64837f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 64937f219c8SBruno Larsen (billionai) } 65037f219c8SBruno Larsen (billionai) 651a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 65237f219c8SBruno Larsen (billionai) { 653283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65437f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) 657a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 65837f219c8SBruno Larsen (billionai) { 659283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 66037f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 66137f219c8SBruno Larsen (billionai) } 66237f219c8SBruno Larsen (billionai) 663a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 66437f219c8SBruno Larsen (billionai) { 665283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 66637f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 66737f219c8SBruno Larsen (billionai) } 66837f219c8SBruno Larsen (billionai) 669a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 67037f219c8SBruno Larsen (billionai) { 671283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67237f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 67337f219c8SBruno Larsen (billionai) } 67437f219c8SBruno Larsen (billionai) 67537f219c8SBruno Larsen (billionai) #endif 67637f219c8SBruno Larsen (billionai) #endif 67737f219c8SBruno Larsen (billionai) 67837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 67937f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 68037f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 681a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 68237f219c8SBruno Larsen (billionai) { 68337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 68437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 68537f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 68637f219c8SBruno Larsen (billionai) } 68737f219c8SBruno Larsen (billionai) 688a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 68937f219c8SBruno Larsen (billionai) { 69037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69237f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 69337f219c8SBruno Larsen (billionai) } 69437f219c8SBruno Larsen (billionai) 695a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 69637f219c8SBruno Larsen (billionai) { 6977058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 69837f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 69937f219c8SBruno Larsen (billionai) } 70037f219c8SBruno Larsen (billionai) 701a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 70237f219c8SBruno Larsen (billionai) { 7037058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 70437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 70537f219c8SBruno Larsen (billionai) } 70637f219c8SBruno Larsen (billionai) 707a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 70837f219c8SBruno Larsen (billionai) { 7097058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 71037f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 71137f219c8SBruno Larsen (billionai) } 71237f219c8SBruno Larsen (billionai) 713a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 71437f219c8SBruno Larsen (billionai) { 7157058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 71637f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 71737f219c8SBruno Larsen (billionai) } 71837f219c8SBruno Larsen (billionai) 71937f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 72037f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 721a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 72237f219c8SBruno Larsen (billionai) { 72337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 72437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 72537f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 72637f219c8SBruno Larsen (billionai) } 72737f219c8SBruno Larsen (billionai) 728a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 72937f219c8SBruno Larsen (billionai) { 73037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 73137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 73237f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 73337f219c8SBruno Larsen (billionai) } 73437f219c8SBruno Larsen (billionai) 735a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 73637f219c8SBruno Larsen (billionai) { 7377058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 73837f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 73937f219c8SBruno Larsen (billionai) } 74037f219c8SBruno Larsen (billionai) 741a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 74237f219c8SBruno Larsen (billionai) { 7437058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 74437f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 74537f219c8SBruno Larsen (billionai) } 74637f219c8SBruno Larsen (billionai) 747a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 74837f219c8SBruno Larsen (billionai) { 7497058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 75037f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 75137f219c8SBruno Larsen (billionai) } 75237f219c8SBruno Larsen (billionai) 753a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 75437f219c8SBruno Larsen (billionai) { 7557058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 75637f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 75737f219c8SBruno Larsen (billionai) } 75837f219c8SBruno Larsen (billionai) 75937f219c8SBruno Larsen (billionai) /* SDR1 */ 760a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 76137f219c8SBruno Larsen (billionai) { 76237f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 76337f219c8SBruno Larsen (billionai) } 76437f219c8SBruno Larsen (billionai) 76537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 76637f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 76737f219c8SBruno Larsen (billionai) /* PIDR */ 768a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 76937f219c8SBruno Larsen (billionai) { 77037f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 77137f219c8SBruno Larsen (billionai) } 77237f219c8SBruno Larsen (billionai) 773a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 77437f219c8SBruno Larsen (billionai) { 77537f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 77637f219c8SBruno Larsen (billionai) } 77737f219c8SBruno Larsen (billionai) 778a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 77937f219c8SBruno Larsen (billionai) { 78037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 78137f219c8SBruno Larsen (billionai) } 78237f219c8SBruno Larsen (billionai) 783a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 78437f219c8SBruno Larsen (billionai) { 78537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 78637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 78737f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 78837f219c8SBruno Larsen (billionai) } 789a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 79037f219c8SBruno Larsen (billionai) { 79137f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 79237f219c8SBruno Larsen (billionai) } 79337f219c8SBruno Larsen (billionai) 794a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 79537f219c8SBruno Larsen (billionai) { 79637f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 79737f219c8SBruno Larsen (billionai) } 79837f219c8SBruno Larsen (billionai) 79937f219c8SBruno Larsen (billionai) /* DPDES */ 800a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 80137f219c8SBruno Larsen (billionai) { 80237f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 80337f219c8SBruno Larsen (billionai) } 80437f219c8SBruno Larsen (billionai) 805a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 80637f219c8SBruno Larsen (billionai) { 80737f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 80837f219c8SBruno Larsen (billionai) } 80937f219c8SBruno Larsen (billionai) #endif 81037f219c8SBruno Larsen (billionai) #endif 81137f219c8SBruno Larsen (billionai) 81237f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 81337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 814a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 81537f219c8SBruno Larsen (billionai) { 816283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 81737f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 81837f219c8SBruno Larsen (billionai) } 81937f219c8SBruno Larsen (billionai) 820a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 82137f219c8SBruno Larsen (billionai) { 822283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 82337f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 82437f219c8SBruno Larsen (billionai) } 82537f219c8SBruno Larsen (billionai) 826a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 82737f219c8SBruno Larsen (billionai) { 828283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 82937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 83037f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 83137f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 832d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 83337f219c8SBruno Larsen (billionai) } 83437f219c8SBruno Larsen (billionai) 835a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 83637f219c8SBruno Larsen (billionai) { 837283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 83837f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 83937f219c8SBruno Larsen (billionai) } 84037f219c8SBruno Larsen (billionai) 841cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 842cbd8f17dSCédric Le Goater { 843283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 844cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 845cbd8f17dSCédric Le Goater } 846cbd8f17dSCédric Le Goater 847cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 848cbd8f17dSCédric Le Goater { 849283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 850cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 851cbd8f17dSCédric Le Goater } 852cbd8f17dSCédric Le Goater 853dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 854dd69d140SCédric Le Goater { 855dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 856dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 85747822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 858dd69d140SCédric Le Goater } 859dd69d140SCédric Le Goater 860a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 86137f219c8SBruno Larsen (billionai) { 862283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 86337f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 86437f219c8SBruno Larsen (billionai) } 86537f219c8SBruno Larsen (billionai) 866a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 86737f219c8SBruno Larsen (billionai) { 868283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 86937f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 87037f219c8SBruno Larsen (billionai) } 87137f219c8SBruno Larsen (billionai) #endif 87237f219c8SBruno Larsen (billionai) 873328c95fcSCédric Le Goater /* PIR */ 87437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 875a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 87637f219c8SBruno Larsen (billionai) { 87737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 87837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 87937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 88037f219c8SBruno Larsen (billionai) } 88137f219c8SBruno Larsen (billionai) #endif 88237f219c8SBruno Larsen (billionai) 88337f219c8SBruno Larsen (billionai) /* SPE specific registers */ 884a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 88537f219c8SBruno Larsen (billionai) { 88637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 88737f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 88837f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 88937f219c8SBruno Larsen (billionai) } 89037f219c8SBruno Larsen (billionai) 891a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 89237f219c8SBruno Larsen (billionai) { 89337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 89437f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 89537f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 89637f219c8SBruno Larsen (billionai) } 89737f219c8SBruno Larsen (billionai) 89837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 89937f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 900a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 90137f219c8SBruno Larsen (billionai) { 90237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 90437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 90537f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 90637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 90737f219c8SBruno Larsen (billionai) } 90837f219c8SBruno Larsen (billionai) 909a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 91037f219c8SBruno Larsen (billionai) { 91137f219c8SBruno Larsen (billionai) int sprn_offs; 91237f219c8SBruno Larsen (billionai) 91337f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 91437f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 91537f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 91637f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 91737f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 91837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 91937f219c8SBruno Larsen (billionai) } else { 9208e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9218e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9228e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 92337f219c8SBruno Larsen (billionai) return; 92437f219c8SBruno Larsen (billionai) } 92537f219c8SBruno Larsen (billionai) 92637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 92837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 92937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 93037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93137f219c8SBruno Larsen (billionai) } 93237f219c8SBruno Larsen (billionai) #endif 93337f219c8SBruno Larsen (billionai) 93437f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 93537f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 936a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 93737f219c8SBruno Larsen (billionai) { 93837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 93937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 94037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 94137f219c8SBruno Larsen (billionai) 94237f219c8SBruno Larsen (billionai) /* 94337f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 94437f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 94537f219c8SBruno Larsen (billionai) */ 94637f219c8SBruno Larsen (billionai) 94737f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 94837f219c8SBruno Larsen (billionai) if (ctx->pr) { 94937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 95037f219c8SBruno Larsen (billionai) } else { 95137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 95237f219c8SBruno Larsen (billionai) } 95337f219c8SBruno Larsen (billionai) 95437f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 95537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 95637f219c8SBruno Larsen (billionai) 95737f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 95837f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 95937f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 96037f219c8SBruno Larsen (billionai) 96137f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 96237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 96337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 96437f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 96537f219c8SBruno Larsen (billionai) } 96637f219c8SBruno Larsen (billionai) 967a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 96837f219c8SBruno Larsen (billionai) { 96937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 97137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 97237f219c8SBruno Larsen (billionai) 97337f219c8SBruno Larsen (billionai) /* 97437f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 97537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97637f219c8SBruno Larsen (billionai) */ 97737f219c8SBruno Larsen (billionai) 97837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 98037f219c8SBruno Larsen (billionai) 98137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98337f219c8SBruno Larsen (billionai) 98437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 98637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98737f219c8SBruno Larsen (billionai) 98837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 99037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 99137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 99237f219c8SBruno Larsen (billionai) } 99337f219c8SBruno Larsen (billionai) 994a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 99537f219c8SBruno Larsen (billionai) { 99637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 99737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 99837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 99937f219c8SBruno Larsen (billionai) 100037f219c8SBruno Larsen (billionai) /* 100137f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100337f219c8SBruno Larsen (billionai) */ 100437f219c8SBruno Larsen (billionai) 100537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 100737f219c8SBruno Larsen (billionai) 100837f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 100937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101037f219c8SBruno Larsen (billionai) 101137f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101237f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 101337f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101437f219c8SBruno Larsen (billionai) 101537f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 101737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 101837f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 101937f219c8SBruno Larsen (billionai) } 102037f219c8SBruno Larsen (billionai) #endif 102137f219c8SBruno Larsen (billionai) #endif 102237f219c8SBruno Larsen (billionai) 102337f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1024a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 102537f219c8SBruno Larsen (billionai) { 102637f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 102737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 102837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 102937f219c8SBruno Larsen (billionai) } 103037f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 103137f219c8SBruno Larsen (billionai) 103237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1033a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 103437f219c8SBruno Larsen (billionai) { 103537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103637f219c8SBruno Larsen (billionai) 103737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 103837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 103937f219c8SBruno Larsen (billionai) } 104037f219c8SBruno Larsen (billionai) 1041a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 104237f219c8SBruno Larsen (billionai) { 104337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 104437f219c8SBruno Larsen (billionai) 104537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 104637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 104737f219c8SBruno Larsen (billionai) } 104837f219c8SBruno Larsen (billionai) 1049a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 105037f219c8SBruno Larsen (billionai) { 105137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 105237f219c8SBruno Larsen (billionai) 105337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 105437f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 105537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 105637f219c8SBruno Larsen (billionai) } 105737f219c8SBruno Larsen (billionai) 1058a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 105937f219c8SBruno Larsen (billionai) { 106037f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 106137f219c8SBruno Larsen (billionai) } 106237f219c8SBruno Larsen (billionai) 1063a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 106437f219c8SBruno Larsen (billionai) { 10657058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 106637f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 106737f219c8SBruno Larsen (billionai) } 10687058ff52SRichard Henderson 1069a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 107037f219c8SBruno Larsen (billionai) { 107137f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 107237f219c8SBruno Larsen (billionai) } 10737058ff52SRichard Henderson 1074a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 107537f219c8SBruno Larsen (billionai) { 107637f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 107737f219c8SBruno Larsen (billionai) } 107837f219c8SBruno Larsen (billionai) 107937f219c8SBruno Larsen (billionai) #endif 108037f219c8SBruno Larsen (billionai) 108137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1082a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 108337f219c8SBruno Larsen (billionai) { 108437f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 108537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 108637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 108737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 108837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 108937f219c8SBruno Larsen (billionai) } 109037f219c8SBruno Larsen (billionai) 1091a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 109237f219c8SBruno Larsen (billionai) { 109337f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 109437f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 109537f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 109637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 109737f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 109837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 109937f219c8SBruno Larsen (billionai) } 110037f219c8SBruno Larsen (billionai) 110137f219c8SBruno Larsen (billionai) #endif 110237f219c8SBruno Larsen (billionai) 110337f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 110437f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 110537f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 110637f219c8SBruno Larsen (billionai) { 11077058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11087058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11097058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 111037f219c8SBruno Larsen (billionai) 111137f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 111237f219c8SBruno Larsen (billionai) } 111337f219c8SBruno Larsen (billionai) 111437f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 111537f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 111637f219c8SBruno Larsen (billionai) { 11177058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11187058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11197058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 112037f219c8SBruno Larsen (billionai) 112137f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 112237f219c8SBruno Larsen (billionai) } 112337f219c8SBruno Larsen (billionai) 1124a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 112537f219c8SBruno Larsen (billionai) { 112637f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 112737f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 112837f219c8SBruno Larsen (billionai) 112937f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 113037f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 113137f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 113237f219c8SBruno Larsen (billionai) } 113337f219c8SBruno Larsen (billionai) 1134a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 113537f219c8SBruno Larsen (billionai) { 113637f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 113737f219c8SBruno Larsen (billionai) 113837f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 113937f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 114037f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 114137f219c8SBruno Larsen (billionai) } 114237f219c8SBruno Larsen (billionai) 114337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1144a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 114537f219c8SBruno Larsen (billionai) { 114637f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 114737f219c8SBruno Larsen (billionai) 114837f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 114937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 115037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 115137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 115237f219c8SBruno Larsen (billionai) } 115337f219c8SBruno Larsen (billionai) 1154a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 115537f219c8SBruno Larsen (billionai) { 115637f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 115737f219c8SBruno Larsen (billionai) } 115837f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 115937f219c8SBruno Larsen (billionai) 1160a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 116137f219c8SBruno Larsen (billionai) { 116237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 116337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 116437f219c8SBruno Larsen (billionai) } 116537f219c8SBruno Larsen (billionai) 1166a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 116737f219c8SBruno Larsen (billionai) { 116837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 116937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 117037f219c8SBruno Larsen (billionai) } 117137f219c8SBruno Larsen (billionai) 1172a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 117337f219c8SBruno Larsen (billionai) { 117437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 117537f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 117637f219c8SBruno Larsen (billionai) } 117737f219c8SBruno Larsen (billionai) 1178a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 117937f219c8SBruno Larsen (billionai) { 118037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 118137f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 118237f219c8SBruno Larsen (billionai) } 118337f219c8SBruno Larsen (billionai) 1184a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 118537f219c8SBruno Larsen (billionai) { 118637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 118737f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 118837f219c8SBruno Larsen (billionai) } 118937f219c8SBruno Larsen (billionai) 1190a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 119137f219c8SBruno Larsen (billionai) { 119237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 119337f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 119437f219c8SBruno Larsen (billionai) } 119537f219c8SBruno Larsen (billionai) 1196a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 119737f219c8SBruno Larsen (billionai) { 119837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 119937f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 120037f219c8SBruno Larsen (billionai) } 120137f219c8SBruno Larsen (billionai) 1202a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 120337f219c8SBruno Larsen (billionai) { 120437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 120537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 120637f219c8SBruno Larsen (billionai) } 120737f219c8SBruno Larsen (billionai) 1208a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 120937f219c8SBruno Larsen (billionai) { 121037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 121137f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 121237f219c8SBruno Larsen (billionai) } 121337f219c8SBruno Larsen (billionai) 1214a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 121537f219c8SBruno Larsen (billionai) { 121637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 121737f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 121837f219c8SBruno Larsen (billionai) } 1219395b5d5bSNicholas Miehlbradt 1220395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1221395b5d5bSNicholas Miehlbradt { 1222395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1223395b5d5bSNicholas Miehlbradt 1224395b5d5bSNicholas Miehlbradt /* 1225395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1226395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1227395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1228395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1229395b5d5bSNicholas Miehlbradt * 1230395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1231395b5d5bSNicholas Miehlbradt */ 1232395b5d5bSNicholas Miehlbradt 1233395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1234395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1235395b5d5bSNicholas Miehlbradt } 123637f219c8SBruno Larsen (billionai) #endif 123737f219c8SBruno Larsen (billionai) 1238fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1239fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1240fcf5ef2aSThomas Huth 1241fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1242fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1243fcf5ef2aSThomas Huth 1244fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1245fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1246fcf5ef2aSThomas Huth 1247fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1248fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1249fcf5ef2aSThomas Huth 1250fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1251fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1252fcf5ef2aSThomas Huth 1253fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1254fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1255fcf5ef2aSThomas Huth 1256fcf5ef2aSThomas Huth typedef struct opcode_t { 1257fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1258fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1259fcf5ef2aSThomas Huth unsigned char pad[4]; 1260fcf5ef2aSThomas Huth #endif 1261fcf5ef2aSThomas Huth opc_handler_t handler; 1262fcf5ef2aSThomas Huth const char *oname; 1263fcf5ef2aSThomas Huth } opcode_t; 1264fcf5ef2aSThomas Huth 12659f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 12669f0cf041SMatheus Ferst { 12679f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 12689f0cf041SMatheus Ferst } 12699f0cf041SMatheus Ferst 1270fcf5ef2aSThomas Huth /* Helpers for priv. check */ 12719f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1272fcf5ef2aSThomas Huth do { \ 12739f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1274fcf5ef2aSThomas Huth } while (0) 1275fcf5ef2aSThomas Huth 1276fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 12779f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 12789f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 12799f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1280fcf5ef2aSThomas Huth #else 12819f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1282fcf5ef2aSThomas Huth do { \ 1283fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 12849f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1285fcf5ef2aSThomas Huth } \ 1286fcf5ef2aSThomas Huth } while (0) 12879f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1288fcf5ef2aSThomas Huth do { \ 1289fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 12909f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1291fcf5ef2aSThomas Huth } \ 1292fcf5ef2aSThomas Huth } while (0) 12939f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1294fcf5ef2aSThomas Huth do { \ 1295fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 12969f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1297fcf5ef2aSThomas Huth } \ 1298fcf5ef2aSThomas Huth } while (0) 1299fcf5ef2aSThomas Huth #endif 1300fcf5ef2aSThomas Huth 13019f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1302fcf5ef2aSThomas Huth 1303fcf5ef2aSThomas Huth /*****************************************************************************/ 1304fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1305fcf5ef2aSThomas Huth 1306fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1307fcf5ef2aSThomas Huth { \ 1308fcf5ef2aSThomas Huth .opc1 = op1, \ 1309fcf5ef2aSThomas Huth .opc2 = op2, \ 1310fcf5ef2aSThomas Huth .opc3 = op3, \ 1311fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1312fcf5ef2aSThomas Huth .handler = { \ 1313fcf5ef2aSThomas Huth .inval1 = invl, \ 1314fcf5ef2aSThomas Huth .type = _typ, \ 1315fcf5ef2aSThomas Huth .type2 = _typ2, \ 1316fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1317fcf5ef2aSThomas Huth }, \ 1318fcf5ef2aSThomas Huth .oname = stringify(name), \ 1319fcf5ef2aSThomas Huth } 1320fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1321fcf5ef2aSThomas Huth { \ 1322fcf5ef2aSThomas Huth .opc1 = op1, \ 1323fcf5ef2aSThomas Huth .opc2 = op2, \ 1324fcf5ef2aSThomas Huth .opc3 = op3, \ 1325fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1326fcf5ef2aSThomas Huth .handler = { \ 1327fcf5ef2aSThomas Huth .inval1 = invl1, \ 1328fcf5ef2aSThomas Huth .inval2 = invl2, \ 1329fcf5ef2aSThomas Huth .type = _typ, \ 1330fcf5ef2aSThomas Huth .type2 = _typ2, \ 1331fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1332fcf5ef2aSThomas Huth }, \ 1333fcf5ef2aSThomas Huth .oname = stringify(name), \ 1334fcf5ef2aSThomas Huth } 1335fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1336fcf5ef2aSThomas Huth { \ 1337fcf5ef2aSThomas Huth .opc1 = op1, \ 1338fcf5ef2aSThomas Huth .opc2 = op2, \ 1339fcf5ef2aSThomas Huth .opc3 = op3, \ 1340fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1341fcf5ef2aSThomas Huth .handler = { \ 1342fcf5ef2aSThomas Huth .inval1 = invl, \ 1343fcf5ef2aSThomas Huth .type = _typ, \ 1344fcf5ef2aSThomas Huth .type2 = _typ2, \ 1345fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1346fcf5ef2aSThomas Huth }, \ 1347fcf5ef2aSThomas Huth .oname = onam, \ 1348fcf5ef2aSThomas Huth } 1349fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1350fcf5ef2aSThomas Huth { \ 1351fcf5ef2aSThomas Huth .opc1 = op1, \ 1352fcf5ef2aSThomas Huth .opc2 = op2, \ 1353fcf5ef2aSThomas Huth .opc3 = op3, \ 1354fcf5ef2aSThomas Huth .opc4 = op4, \ 1355fcf5ef2aSThomas Huth .handler = { \ 1356fcf5ef2aSThomas Huth .inval1 = invl, \ 1357fcf5ef2aSThomas Huth .type = _typ, \ 1358fcf5ef2aSThomas Huth .type2 = _typ2, \ 1359fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1360fcf5ef2aSThomas Huth }, \ 1361fcf5ef2aSThomas Huth .oname = stringify(name), \ 1362fcf5ef2aSThomas Huth } 1363fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1364fcf5ef2aSThomas Huth { \ 1365fcf5ef2aSThomas Huth .opc1 = op1, \ 1366fcf5ef2aSThomas Huth .opc2 = op2, \ 1367fcf5ef2aSThomas Huth .opc3 = op3, \ 1368fcf5ef2aSThomas Huth .opc4 = op4, \ 1369fcf5ef2aSThomas Huth .handler = { \ 1370fcf5ef2aSThomas Huth .inval1 = invl, \ 1371fcf5ef2aSThomas Huth .type = _typ, \ 1372fcf5ef2aSThomas Huth .type2 = _typ2, \ 1373fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1374fcf5ef2aSThomas Huth }, \ 1375fcf5ef2aSThomas Huth .oname = onam, \ 1376fcf5ef2aSThomas Huth } 1377fcf5ef2aSThomas Huth 1378fcf5ef2aSThomas Huth /* Invalid instruction */ 1379fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1380fcf5ef2aSThomas Huth { 1381fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1382fcf5ef2aSThomas Huth } 1383fcf5ef2aSThomas Huth 1384fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1385fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1386fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1387fcf5ef2aSThomas Huth .type = PPC_NONE, 1388fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1389fcf5ef2aSThomas Huth .handler = gen_invalid, 1390fcf5ef2aSThomas Huth }; 1391fcf5ef2aSThomas Huth 1392fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1393fcf5ef2aSThomas Huth 1394fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1395fcf5ef2aSThomas Huth { 1396fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1397b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1398b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1399fcf5ef2aSThomas Huth 1400b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1401b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1402efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1403efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1404b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1405efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1406efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1407b62b3686Spbonzini@redhat.com 1408b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1409fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1410b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1411fcf5ef2aSThomas Huth } 1412fcf5ef2aSThomas Huth 1413fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1414fcf5ef2aSThomas Huth { 14157058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1416fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth 1419fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1420fcf5ef2aSThomas Huth { 1421fcf5ef2aSThomas Huth TCGv t0, t1; 1422fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1423fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1424fcf5ef2aSThomas Huth if (s) { 1425fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1426fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1427fcf5ef2aSThomas Huth } else { 1428fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1429fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1430fcf5ef2aSThomas Huth } 1431fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1432fcf5ef2aSThomas Huth } 1433fcf5ef2aSThomas Huth 1434fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1435fcf5ef2aSThomas Huth { 14367058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1437fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1438fcf5ef2aSThomas Huth } 1439fcf5ef2aSThomas Huth 1440fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1441fcf5ef2aSThomas Huth { 1442fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1443fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1444fcf5ef2aSThomas Huth } else { 1445fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1446fcf5ef2aSThomas Huth } 1447fcf5ef2aSThomas Huth } 1448fcf5ef2aSThomas Huth 1449fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1450fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1451fcf5ef2aSThomas Huth { 1452fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1453fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1454fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1455fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1456fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1457fcf5ef2aSThomas Huth 1458fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1459fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1460fcf5ef2aSThomas Huth 1461fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1462fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1463fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1464fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1465fcf5ef2aSThomas Huth 1466fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1467fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1468fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1469fcf5ef2aSThomas Huth 1470fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1471fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1472fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1473fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1474fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1475fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1476fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1477fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1478fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1479fcf5ef2aSThomas Huth } 1480efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1481fcf5ef2aSThomas Huth } 1482fcf5ef2aSThomas Huth 1483fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1484fcf5ef2aSThomas Huth /* cmpeqb */ 1485fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1486fcf5ef2aSThomas Huth { 1487fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1488fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1489fcf5ef2aSThomas Huth } 1490fcf5ef2aSThomas Huth #endif 1491fcf5ef2aSThomas Huth 1492fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1493fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1494fcf5ef2aSThomas Huth { 1495fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1496fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1497fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1498fcf5ef2aSThomas Huth TCGv zr; 1499fcf5ef2aSThomas Huth 1500fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1501fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1502fcf5ef2aSThomas Huth 15037058ff52SRichard Henderson zr = tcg_constant_tl(0); 1504fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1505fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1506fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1507fcf5ef2aSThomas Huth } 1508fcf5ef2aSThomas Huth 1509fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1510fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1511fcf5ef2aSThomas Huth { 1512fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1513fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1514fcf5ef2aSThomas Huth } 1515fcf5ef2aSThomas Huth 1516fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1517fcf5ef2aSThomas Huth 1518fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1519fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1520fcf5ef2aSThomas Huth { 1521fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1522fcf5ef2aSThomas Huth 1523fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1524fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1525fcf5ef2aSThomas Huth if (sub) { 1526fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1527fcf5ef2aSThomas Huth } else { 1528fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1529fcf5ef2aSThomas Huth } 1530fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1531dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1532dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1533dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1534fcf5ef2aSThomas Huth } 1535dc0ad844SNikunj A Dadhania } else { 1536dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1537dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1538dc0ad844SNikunj A Dadhania } 153938a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1540dc0ad844SNikunj A Dadhania } 1541fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1542fcf5ef2aSThomas Huth } 1543fcf5ef2aSThomas Huth 15446b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15456b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15464c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15476b10d008SNikunj A Dadhania { 15486b10d008SNikunj A Dadhania TCGv t0; 15496b10d008SNikunj A Dadhania 15506b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 15516b10d008SNikunj A Dadhania return; 15526b10d008SNikunj A Dadhania } 15536b10d008SNikunj A Dadhania 15546b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 155533903d0aSNikunj A Dadhania if (sub) { 155633903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 155733903d0aSNikunj A Dadhania } else { 15586b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 155933903d0aSNikunj A Dadhania } 15606b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 15614c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 15626b10d008SNikunj A Dadhania } 15636b10d008SNikunj A Dadhania 1564fcf5ef2aSThomas Huth /* Common add function */ 1565fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 15664c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 15674c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1568fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1569fcf5ef2aSThomas Huth { 1570fcf5ef2aSThomas Huth TCGv t0 = ret; 1571fcf5ef2aSThomas Huth 1572fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1573fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1574fcf5ef2aSThomas Huth } 1575fcf5ef2aSThomas Huth 1576fcf5ef2aSThomas Huth if (compute_ca) { 1577fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1578efe843d8SDavid Gibson /* 1579efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1580efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1581efe843d8SDavid Gibson * produce the carry into bit 32. 1582efe843d8SDavid Gibson */ 1583fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1584fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1585fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1586fcf5ef2aSThomas Huth if (add_ca) { 15874c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1588fcf5ef2aSThomas Huth } 15894c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 15904c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 15916b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 15924c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 15936b10d008SNikunj A Dadhania } 1594fcf5ef2aSThomas Huth } else { 15957058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 1596fcf5ef2aSThomas Huth if (add_ca) { 15974c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 15984c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1599fcf5ef2aSThomas Huth } else { 16004c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1601fcf5ef2aSThomas Huth } 16024c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1603fcf5ef2aSThomas Huth } 1604fcf5ef2aSThomas Huth } else { 1605fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1606fcf5ef2aSThomas Huth if (add_ca) { 16074c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1608fcf5ef2aSThomas Huth } 1609fcf5ef2aSThomas Huth } 1610fcf5ef2aSThomas Huth 1611fcf5ef2aSThomas Huth if (compute_ov) { 1612fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1613fcf5ef2aSThomas Huth } 1614fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1615fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1616fcf5ef2aSThomas Huth } 1617fcf5ef2aSThomas Huth 161811f4e8f8SRichard Henderson if (t0 != ret) { 1619fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1620fcf5ef2aSThomas Huth } 1621fcf5ef2aSThomas Huth } 1622fcf5ef2aSThomas Huth /* Add functions with two operands */ 16234c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1624fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1625fcf5ef2aSThomas Huth { \ 1626fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1627fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16284c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1629fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1630fcf5ef2aSThomas Huth } 1631fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16324c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1633fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1634fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1635fcf5ef2aSThomas Huth { \ 16367058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 1637fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1638fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16394c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1640fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1641fcf5ef2aSThomas Huth } 1642fcf5ef2aSThomas Huth 1643fcf5ef2aSThomas Huth /* add add. addo addo. */ 16444c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16454c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1646fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16484c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1649fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 16504c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 16514c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1652fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 16534c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 16544c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 16554c5920afSSuraj Jitindar Singh /* addex */ 16564c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1657fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 16584c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 16594c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1660fcf5ef2aSThomas Huth /* addic addic.*/ 1661fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1662fcf5ef2aSThomas Huth { 16637058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1664fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 16654c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth 1668fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1669fcf5ef2aSThomas Huth { 1670fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1671fcf5ef2aSThomas Huth } 1672fcf5ef2aSThomas Huth 1673fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1674fcf5ef2aSThomas Huth { 1675fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1676fcf5ef2aSThomas Huth } 1677fcf5ef2aSThomas Huth 1678fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1679fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1680fcf5ef2aSThomas Huth { 1681fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1682fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1683fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1684fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1685fcf5ef2aSThomas Huth 1686fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1687fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1688fcf5ef2aSThomas Huth if (sign) { 1689fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1690fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1691fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1692fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1693fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1694fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1695fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1696fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1697fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1698fcf5ef2aSThomas Huth } else { 1699fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1700fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1701fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1702fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1703fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1704fcf5ef2aSThomas Huth } 1705fcf5ef2aSThomas Huth if (compute_ov) { 1706fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1707c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1708c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1709c44027ffSNikunj A Dadhania } 1710fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1711fcf5ef2aSThomas Huth } 1712fcf5ef2aSThomas Huth 1713efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1714fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1715fcf5ef2aSThomas Huth } 1716efe843d8SDavid Gibson } 1717fcf5ef2aSThomas Huth /* Div functions */ 1718fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1719fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1720fcf5ef2aSThomas Huth { \ 1721fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1722fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1723fcf5ef2aSThomas Huth sign, compute_ov); \ 1724fcf5ef2aSThomas Huth } 1725fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1726fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1727fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1728fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1729fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1730fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1731fcf5ef2aSThomas Huth 1732fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1733fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1734fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1735fcf5ef2aSThomas Huth { \ 17367058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1737fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1738fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1739fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1740fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1741fcf5ef2aSThomas Huth } \ 1742fcf5ef2aSThomas Huth } 1743fcf5ef2aSThomas Huth 1744fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1745fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1746fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1747fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1748fcf5ef2aSThomas Huth 1749fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1750fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1751fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1752fcf5ef2aSThomas Huth { 1753fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1754fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1755fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1756fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1757fcf5ef2aSThomas Huth 1758fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1759fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1760fcf5ef2aSThomas Huth if (sign) { 1761fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1762fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1763fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1764fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1765fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1766fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1767fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1768fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1769fcf5ef2aSThomas Huth } else { 1770fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1771fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1772fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1773fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1774fcf5ef2aSThomas Huth } 1775fcf5ef2aSThomas Huth if (compute_ov) { 1776fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1777c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1778c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1779c44027ffSNikunj A Dadhania } 1780fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1781fcf5ef2aSThomas Huth } 1782fcf5ef2aSThomas Huth 1783efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1784fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1785fcf5ef2aSThomas Huth } 1786efe843d8SDavid Gibson } 1787fcf5ef2aSThomas Huth 1788fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1789fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1790fcf5ef2aSThomas Huth { \ 1791fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1792fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1793fcf5ef2aSThomas Huth sign, compute_ov); \ 1794fcf5ef2aSThomas Huth } 1795c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1796fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1797fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1798c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1799fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1800fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1801fcf5ef2aSThomas Huth 1802fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1803fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1804fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1805fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1806fcf5ef2aSThomas Huth #endif 1807fcf5ef2aSThomas Huth 1808fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1809fcf5ef2aSThomas Huth TCGv arg2, int sign) 1810fcf5ef2aSThomas Huth { 1811fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1812fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1813fcf5ef2aSThomas Huth 1814fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1815fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1816fcf5ef2aSThomas Huth if (sign) { 1817fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1818fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1819fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1820fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1821fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1822fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1823fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1824fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1825fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1826fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1827fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1828fcf5ef2aSThomas Huth } else { 18297058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(1); 18307058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(0); 1831fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1832a253231fSRichard Henderson tcg_gen_remu_i32(t0, t0, t1); 1833a253231fSRichard Henderson tcg_gen_extu_i32_tl(ret, t0); 1834fcf5ef2aSThomas Huth } 1835fcf5ef2aSThomas Huth } 1836fcf5ef2aSThomas Huth 1837fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1838fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1839fcf5ef2aSThomas Huth { \ 1840fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1841fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1842fcf5ef2aSThomas Huth sign); \ 1843fcf5ef2aSThomas Huth } 1844fcf5ef2aSThomas Huth 1845fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1846fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1847fcf5ef2aSThomas Huth 1848fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1849fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1850fcf5ef2aSThomas Huth TCGv arg2, int sign) 1851fcf5ef2aSThomas Huth { 1852fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1853fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1854fcf5ef2aSThomas Huth 1855fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1856fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1857fcf5ef2aSThomas Huth if (sign) { 1858fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1859fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1860fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1861fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1862fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1863fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1864fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1865fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1866fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1867fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1868fcf5ef2aSThomas Huth } else { 18697058ff52SRichard Henderson TCGv_i64 t2 = tcg_constant_i64(1); 18707058ff52SRichard Henderson TCGv_i64 t3 = tcg_constant_i64(0); 1871fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1872fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1873fcf5ef2aSThomas Huth } 1874fcf5ef2aSThomas Huth } 1875fcf5ef2aSThomas Huth 1876fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1877fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1878fcf5ef2aSThomas Huth { \ 1879fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1880fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1881fcf5ef2aSThomas Huth sign); \ 1882fcf5ef2aSThomas Huth } 1883fcf5ef2aSThomas Huth 1884fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1885fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1886fcf5ef2aSThomas Huth #endif 1887fcf5ef2aSThomas Huth 1888fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1889fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1890fcf5ef2aSThomas Huth { 1891fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1892fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1893fcf5ef2aSThomas Huth 1894fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1895fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1896fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1897fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1898efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1899fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1900fcf5ef2aSThomas Huth } 1901efe843d8SDavid Gibson } 1902fcf5ef2aSThomas Huth 1903fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1904fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1905fcf5ef2aSThomas Huth { 1906fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1907fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1908fcf5ef2aSThomas Huth 1909fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1910fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1911fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1912fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1913efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1914fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1915fcf5ef2aSThomas Huth } 1916efe843d8SDavid Gibson } 1917fcf5ef2aSThomas Huth 1918fcf5ef2aSThomas Huth /* mullw mullw. */ 1919fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1920fcf5ef2aSThomas Huth { 1921fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1922fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1923fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1924fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1925fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1926fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1927fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1928fcf5ef2aSThomas Huth #else 1929fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1930fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1931fcf5ef2aSThomas Huth #endif 1932efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1933fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1934fcf5ef2aSThomas Huth } 1935efe843d8SDavid Gibson } 1936fcf5ef2aSThomas Huth 1937fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1938fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1939fcf5ef2aSThomas Huth { 1940fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1941fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1942fcf5ef2aSThomas Huth 1943fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1944fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1945fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1946fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1947fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1948fcf5ef2aSThomas Huth #else 1949fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1950fcf5ef2aSThomas Huth #endif 1951fcf5ef2aSThomas Huth 1952fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1953fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1954fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 195561aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 195661aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 195761aa9a69SNikunj A Dadhania } 1958fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1959fcf5ef2aSThomas Huth 1960efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1961fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1962fcf5ef2aSThomas Huth } 1963efe843d8SDavid Gibson } 1964fcf5ef2aSThomas Huth 1965fcf5ef2aSThomas Huth /* mulli */ 1966fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1967fcf5ef2aSThomas Huth { 1968fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1969fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1970fcf5ef2aSThomas Huth } 1971fcf5ef2aSThomas Huth 1972fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1973fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1974fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1975fcf5ef2aSThomas Huth { 1976fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1977fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1978fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1979fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1980fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1981fcf5ef2aSThomas Huth } 1982fcf5ef2aSThomas Huth } 1983fcf5ef2aSThomas Huth 1984fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1985fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1986fcf5ef2aSThomas Huth { 1987fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1988fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1989fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1990fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1991fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1992fcf5ef2aSThomas Huth } 1993fcf5ef2aSThomas Huth } 1994fcf5ef2aSThomas Huth 1995fcf5ef2aSThomas Huth /* mulld mulld. */ 1996fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1997fcf5ef2aSThomas Huth { 1998fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1999fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2000efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2001fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2002fcf5ef2aSThomas Huth } 2003efe843d8SDavid Gibson } 2004fcf5ef2aSThomas Huth 2005fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2006fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2007fcf5ef2aSThomas Huth { 2008fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2009fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2010fcf5ef2aSThomas Huth 2011fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2012fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2013fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2014fcf5ef2aSThomas Huth 2015fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2016fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 201761aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 201861aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 201961aa9a69SNikunj A Dadhania } 2020fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2021fcf5ef2aSThomas Huth 2022fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2023fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2024fcf5ef2aSThomas Huth } 2025fcf5ef2aSThomas Huth } 2026fcf5ef2aSThomas Huth #endif 2027fcf5ef2aSThomas Huth 2028fcf5ef2aSThomas Huth /* Common subf function */ 2029fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2030fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2031fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2032fcf5ef2aSThomas Huth { 2033fcf5ef2aSThomas Huth TCGv t0 = ret; 2034fcf5ef2aSThomas Huth 2035fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2036fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2037fcf5ef2aSThomas Huth } 2038fcf5ef2aSThomas Huth 2039fcf5ef2aSThomas Huth if (compute_ca) { 2040fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2041fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2042efe843d8SDavid Gibson /* 2043efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2044efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2045efe843d8SDavid Gibson * produce the carry into bit 32. 2046efe843d8SDavid Gibson */ 2047fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2048fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2049fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2050fcf5ef2aSThomas Huth if (add_ca) { 2051fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2052fcf5ef2aSThomas Huth } else { 2053fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2054fcf5ef2aSThomas Huth } 2055fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2056fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2057fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2058e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 205933903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 206033903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 206133903d0aSNikunj A Dadhania } 2062fcf5ef2aSThomas Huth } else if (add_ca) { 2063fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2064fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 20657058ff52SRichard Henderson zero = tcg_constant_tl(0); 2066fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2067fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 20684c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2069fcf5ef2aSThomas Huth } else { 2070fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2071fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 20724c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2073fcf5ef2aSThomas Huth } 2074fcf5ef2aSThomas Huth } else if (add_ca) { 2075efe843d8SDavid Gibson /* 2076efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2077efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2078efe843d8SDavid Gibson */ 2079fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2080fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2081fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2082fcf5ef2aSThomas Huth } else { 2083fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2084fcf5ef2aSThomas Huth } 2085fcf5ef2aSThomas Huth 2086fcf5ef2aSThomas Huth if (compute_ov) { 2087fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2088fcf5ef2aSThomas Huth } 2089fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2090fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2091fcf5ef2aSThomas Huth } 2092fcf5ef2aSThomas Huth 209311f4e8f8SRichard Henderson if (t0 != ret) { 2094fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2095fcf5ef2aSThomas Huth } 2096fcf5ef2aSThomas Huth } 2097fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2098fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2099fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2100fcf5ef2aSThomas Huth { \ 2101fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2102fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2103fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2104fcf5ef2aSThomas Huth } 2105fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2106fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2107fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2108fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2109fcf5ef2aSThomas Huth { \ 21107058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 2111fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2112fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2113fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2114fcf5ef2aSThomas Huth } 2115fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2116fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2117fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2118fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2119fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2120fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2121fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2122fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2123fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2124fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2125fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2126fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2127fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2128fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2129fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2130fcf5ef2aSThomas Huth 2131fcf5ef2aSThomas Huth /* subfic */ 2132fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2133fcf5ef2aSThomas Huth { 21347058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2135fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2136fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2137fcf5ef2aSThomas Huth } 2138fcf5ef2aSThomas Huth 2139fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2140fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2141fcf5ef2aSThomas Huth { 21427058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 2143fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2144fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2145fcf5ef2aSThomas Huth } 2146fcf5ef2aSThomas Huth 2147fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2148fcf5ef2aSThomas Huth { 21491480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 21501480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 21511480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 21521480d71cSNikunj A Dadhania } 2153fcf5ef2aSThomas Huth } 2154fcf5ef2aSThomas Huth 2155fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2156fcf5ef2aSThomas Huth { 2157fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2158fcf5ef2aSThomas Huth } 2159fcf5ef2aSThomas Huth 2160fcf5ef2aSThomas Huth /*** Integer logical ***/ 2161fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2162fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2163fcf5ef2aSThomas Huth { \ 2164fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2165fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2166fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2167fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2168fcf5ef2aSThomas Huth } 2169fcf5ef2aSThomas Huth 2170fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2171fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2172fcf5ef2aSThomas Huth { \ 2173fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2174fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2175fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2176fcf5ef2aSThomas Huth } 2177fcf5ef2aSThomas Huth 2178fcf5ef2aSThomas Huth /* and & and. */ 2179fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2180fcf5ef2aSThomas Huth /* andc & andc. */ 2181fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2182fcf5ef2aSThomas Huth 2183fcf5ef2aSThomas Huth /* andi. */ 2184fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2185fcf5ef2aSThomas Huth { 2186efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2187efe843d8SDavid Gibson UIMM(ctx->opcode)); 2188fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2189fcf5ef2aSThomas Huth } 2190fcf5ef2aSThomas Huth 2191fcf5ef2aSThomas Huth /* andis. */ 2192fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2193fcf5ef2aSThomas Huth { 2194efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2195efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2196fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2197fcf5ef2aSThomas Huth } 2198fcf5ef2aSThomas Huth 2199fcf5ef2aSThomas Huth /* cntlzw */ 2200fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2201fcf5ef2aSThomas Huth { 22029b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22039b8514e5SRichard Henderson 22049b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22059b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22069b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22079b8514e5SRichard Henderson 2208efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2209fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2210fcf5ef2aSThomas Huth } 2211efe843d8SDavid Gibson } 2212fcf5ef2aSThomas Huth 2213fcf5ef2aSThomas Huth /* cnttzw */ 2214fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2215fcf5ef2aSThomas Huth { 22169b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22179b8514e5SRichard Henderson 22189b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22199b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22209b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22219b8514e5SRichard Henderson 2222fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2223fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2224fcf5ef2aSThomas Huth } 2225fcf5ef2aSThomas Huth } 2226fcf5ef2aSThomas Huth 2227fcf5ef2aSThomas Huth /* eqv & eqv. */ 2228fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2229fcf5ef2aSThomas Huth /* extsb & extsb. */ 2230fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2231fcf5ef2aSThomas Huth /* extsh & extsh. */ 2232fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2233fcf5ef2aSThomas Huth /* nand & nand. */ 2234fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2235fcf5ef2aSThomas Huth /* nor & nor. */ 2236fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2237fcf5ef2aSThomas Huth 2238fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2239fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2240fcf5ef2aSThomas Huth { 22417058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(0); 2242fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2243fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2244fcf5ef2aSThomas Huth 2245fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2246b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2247fcf5ef2aSThomas Huth } 2248fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2249fcf5ef2aSThomas Huth 2250fcf5ef2aSThomas Huth /* or & or. */ 2251fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2252fcf5ef2aSThomas Huth { 2253fcf5ef2aSThomas Huth int rs, ra, rb; 2254fcf5ef2aSThomas Huth 2255fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2256fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2257fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2258fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2259fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2260efe843d8SDavid Gibson if (rs != rb) { 2261fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2262efe843d8SDavid Gibson } else { 2263fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2264efe843d8SDavid Gibson } 2265efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2266fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2267efe843d8SDavid Gibson } 2268fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2269fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2270fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2271fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2272fcf5ef2aSThomas Huth int prio = 0; 2273fcf5ef2aSThomas Huth 2274fcf5ef2aSThomas Huth switch (rs) { 2275fcf5ef2aSThomas Huth case 1: 2276fcf5ef2aSThomas Huth /* Set process priority to low */ 2277fcf5ef2aSThomas Huth prio = 2; 2278fcf5ef2aSThomas Huth break; 2279fcf5ef2aSThomas Huth case 6: 2280fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2281fcf5ef2aSThomas Huth prio = 3; 2282fcf5ef2aSThomas Huth break; 2283fcf5ef2aSThomas Huth case 2: 2284fcf5ef2aSThomas Huth /* Set process priority to normal */ 2285fcf5ef2aSThomas Huth prio = 4; 2286fcf5ef2aSThomas Huth break; 2287fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2288fcf5ef2aSThomas Huth case 31: 2289fcf5ef2aSThomas Huth if (!ctx->pr) { 2290fcf5ef2aSThomas Huth /* Set process priority to very low */ 2291fcf5ef2aSThomas Huth prio = 1; 2292fcf5ef2aSThomas Huth } 2293fcf5ef2aSThomas Huth break; 2294fcf5ef2aSThomas Huth case 5: 2295fcf5ef2aSThomas Huth if (!ctx->pr) { 2296fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2297fcf5ef2aSThomas Huth prio = 5; 2298fcf5ef2aSThomas Huth } 2299fcf5ef2aSThomas Huth break; 2300fcf5ef2aSThomas Huth case 3: 2301fcf5ef2aSThomas Huth if (!ctx->pr) { 2302fcf5ef2aSThomas Huth /* Set process priority to high */ 2303fcf5ef2aSThomas Huth prio = 6; 2304fcf5ef2aSThomas Huth } 2305fcf5ef2aSThomas Huth break; 2306fcf5ef2aSThomas Huth case 7: 2307fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2308fcf5ef2aSThomas Huth /* Set process priority to very high */ 2309fcf5ef2aSThomas Huth prio = 7; 2310fcf5ef2aSThomas Huth } 2311fcf5ef2aSThomas Huth break; 2312fcf5ef2aSThomas Huth #endif 2313fcf5ef2aSThomas Huth default: 2314fcf5ef2aSThomas Huth break; 2315fcf5ef2aSThomas Huth } 2316fcf5ef2aSThomas Huth if (prio) { 2317fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2318fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2319fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2320fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2321fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2322fcf5ef2aSThomas Huth } 2323fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2324efe843d8SDavid Gibson /* 2325efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2326efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2327efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2328efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2329fcf5ef2aSThomas Huth */ 2330fcf5ef2aSThomas Huth gen_pause(ctx); 2331fcf5ef2aSThomas Huth #endif 2332fcf5ef2aSThomas Huth #endif 2333fcf5ef2aSThomas Huth } 2334fcf5ef2aSThomas Huth } 2335fcf5ef2aSThomas Huth /* orc & orc. */ 2336fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2337fcf5ef2aSThomas Huth 2338fcf5ef2aSThomas Huth /* xor & xor. */ 2339fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2340fcf5ef2aSThomas Huth { 2341fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2342efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2343efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2344efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2345efe843d8SDavid Gibson } else { 2346fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2347efe843d8SDavid Gibson } 2348efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2349fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2350fcf5ef2aSThomas Huth } 2351efe843d8SDavid Gibson } 2352fcf5ef2aSThomas Huth 2353fcf5ef2aSThomas Huth /* ori */ 2354fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2355fcf5ef2aSThomas Huth { 2356fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2357fcf5ef2aSThomas Huth 2358fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2359fcf5ef2aSThomas Huth return; 2360fcf5ef2aSThomas Huth } 2361fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2362fcf5ef2aSThomas Huth } 2363fcf5ef2aSThomas Huth 2364fcf5ef2aSThomas Huth /* oris */ 2365fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2366fcf5ef2aSThomas Huth { 2367fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2368fcf5ef2aSThomas Huth 2369fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2370fcf5ef2aSThomas Huth /* NOP */ 2371fcf5ef2aSThomas Huth return; 2372fcf5ef2aSThomas Huth } 2373efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2374efe843d8SDavid Gibson uimm << 16); 2375fcf5ef2aSThomas Huth } 2376fcf5ef2aSThomas Huth 2377fcf5ef2aSThomas Huth /* xori */ 2378fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2379fcf5ef2aSThomas Huth { 2380fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2381fcf5ef2aSThomas Huth 2382fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2383fcf5ef2aSThomas Huth /* NOP */ 2384fcf5ef2aSThomas Huth return; 2385fcf5ef2aSThomas Huth } 2386fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2387fcf5ef2aSThomas Huth } 2388fcf5ef2aSThomas Huth 2389fcf5ef2aSThomas Huth /* xoris */ 2390fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2391fcf5ef2aSThomas Huth { 2392fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2393fcf5ef2aSThomas Huth 2394fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2395fcf5ef2aSThomas Huth /* NOP */ 2396fcf5ef2aSThomas Huth return; 2397fcf5ef2aSThomas Huth } 2398efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2399efe843d8SDavid Gibson uimm << 16); 2400fcf5ef2aSThomas Huth } 2401fcf5ef2aSThomas Huth 2402fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2403fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2404fcf5ef2aSThomas Huth { 2405fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2406fcf5ef2aSThomas Huth } 2407fcf5ef2aSThomas Huth 2408fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2409fcf5ef2aSThomas Huth { 241079770002SRichard Henderson #if defined(TARGET_PPC64) 2411fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 241279770002SRichard Henderson #else 241379770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 241479770002SRichard Henderson #endif 2415fcf5ef2aSThomas Huth } 2416fcf5ef2aSThomas Huth 2417fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2418fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2419fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2420fcf5ef2aSThomas Huth { 242179770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2422fcf5ef2aSThomas Huth } 2423fcf5ef2aSThomas Huth #endif 2424fcf5ef2aSThomas Huth 2425fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2426fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2427fcf5ef2aSThomas Huth { 2428fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2429fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2430fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2431fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2432fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2433fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2434fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2435fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2436fcf5ef2aSThomas Huth } 2437fcf5ef2aSThomas Huth 2438fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2439fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2440fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2441fcf5ef2aSThomas Huth { 2442fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2443fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2444fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2445fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2446fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2447fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2448fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2449fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2450fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2451fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2452fcf5ef2aSThomas Huth } 2453fcf5ef2aSThomas Huth #endif 2454fcf5ef2aSThomas Huth 2455fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2456fcf5ef2aSThomas Huth /* bpermd */ 2457fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2458fcf5ef2aSThomas Huth { 2459fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2460fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2461fcf5ef2aSThomas Huth } 2462fcf5ef2aSThomas Huth #endif 2463fcf5ef2aSThomas Huth 2464fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2465fcf5ef2aSThomas Huth /* extsw & extsw. */ 2466fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2467fcf5ef2aSThomas Huth 2468fcf5ef2aSThomas Huth /* cntlzd */ 2469fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2470fcf5ef2aSThomas Huth { 24719b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2472efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2473fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2474fcf5ef2aSThomas Huth } 2475efe843d8SDavid Gibson } 2476fcf5ef2aSThomas Huth 2477fcf5ef2aSThomas Huth /* cnttzd */ 2478fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2479fcf5ef2aSThomas Huth { 24809b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2481fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2482fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2483fcf5ef2aSThomas Huth } 2484fcf5ef2aSThomas Huth } 2485fcf5ef2aSThomas Huth 2486fcf5ef2aSThomas Huth /* darn */ 2487fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2488fcf5ef2aSThomas Huth { 2489fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2490fcf5ef2aSThomas Huth 24917e4357f6SRichard Henderson if (l > 2) { 24927e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 24937e4357f6SRichard Henderson } else { 2494283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 2495fcf5ef2aSThomas Huth if (l == 0) { 2496fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 24977e4357f6SRichard Henderson } else { 2498fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2499fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25007e4357f6SRichard Henderson } 2501fcf5ef2aSThomas Huth } 2502fcf5ef2aSThomas Huth } 2503fcf5ef2aSThomas Huth #endif 2504fcf5ef2aSThomas Huth 2505fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2506fcf5ef2aSThomas Huth 2507fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2508fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2509fcf5ef2aSThomas Huth { 2510fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2511fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2512fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2513fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2514fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2515fcf5ef2aSThomas Huth 2516fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2517fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2518fcf5ef2aSThomas Huth } else { 2519fcf5ef2aSThomas Huth target_ulong mask; 2520c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2521fcf5ef2aSThomas Huth TCGv t1; 2522fcf5ef2aSThomas Huth 2523fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2524fcf5ef2aSThomas Huth mb += 32; 2525fcf5ef2aSThomas Huth me += 32; 2526fcf5ef2aSThomas Huth #endif 2527fcf5ef2aSThomas Huth mask = MASK(mb, me); 2528fcf5ef2aSThomas Huth 2529c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2530c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2531c4f6a4a3SDaniele Buono mask_in_32b = false; 2532c4f6a4a3SDaniele Buono } 2533c4f6a4a3SDaniele Buono #endif 2534fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2535c4f6a4a3SDaniele Buono if (mask_in_32b) { 2536fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2537fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2538fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2539fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2540fcf5ef2aSThomas Huth } else { 2541fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2542fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2543fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2544fcf5ef2aSThomas Huth #else 2545fcf5ef2aSThomas Huth g_assert_not_reached(); 2546fcf5ef2aSThomas Huth #endif 2547fcf5ef2aSThomas Huth } 2548fcf5ef2aSThomas Huth 2549fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2550fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2551fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2552fcf5ef2aSThomas Huth } 2553fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2554fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2555fcf5ef2aSThomas Huth } 2556fcf5ef2aSThomas Huth } 2557fcf5ef2aSThomas Huth 2558fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2559fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2560fcf5ef2aSThomas Huth { 2561fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2562fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 25637b4d326fSRichard Henderson int sh = SH(ctx->opcode); 25647b4d326fSRichard Henderson int mb = MB(ctx->opcode); 25657b4d326fSRichard Henderson int me = ME(ctx->opcode); 25667b4d326fSRichard Henderson int len = me - mb + 1; 25677b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2568fcf5ef2aSThomas Huth 25697b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 25707b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 25717b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 25727b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2573fcf5ef2aSThomas Huth } else { 2574fcf5ef2aSThomas Huth target_ulong mask; 2575c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2576fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2577fcf5ef2aSThomas Huth mb += 32; 2578fcf5ef2aSThomas Huth me += 32; 2579fcf5ef2aSThomas Huth #endif 2580fcf5ef2aSThomas Huth mask = MASK(mb, me); 2581c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2582c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2583c4f6a4a3SDaniele Buono mask_in_32b = false; 2584c4f6a4a3SDaniele Buono } 2585c4f6a4a3SDaniele Buono #endif 2586c4f6a4a3SDaniele Buono if (mask_in_32b) { 25877b4d326fSRichard Henderson if (sh == 0) { 25887b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 258994f040aaSVitaly Chikunov } else { 2590fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2591fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2592fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2593fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2594fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 259594f040aaSVitaly Chikunov } 2596fcf5ef2aSThomas Huth } else { 2597fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2598fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2599fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2600fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2601fcf5ef2aSThomas Huth #else 2602fcf5ef2aSThomas Huth g_assert_not_reached(); 2603fcf5ef2aSThomas Huth #endif 2604fcf5ef2aSThomas Huth } 2605fcf5ef2aSThomas Huth } 2606fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2607fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2608fcf5ef2aSThomas Huth } 2609fcf5ef2aSThomas Huth } 2610fcf5ef2aSThomas Huth 2611fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2612fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2613fcf5ef2aSThomas Huth { 2614fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2615fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2616fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2617fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2618fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2619fcf5ef2aSThomas Huth target_ulong mask; 2620c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2621fcf5ef2aSThomas Huth 2622fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2623fcf5ef2aSThomas Huth mb += 32; 2624fcf5ef2aSThomas Huth me += 32; 2625fcf5ef2aSThomas Huth #endif 2626fcf5ef2aSThomas Huth mask = MASK(mb, me); 2627fcf5ef2aSThomas Huth 2628c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2629c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2630c4f6a4a3SDaniele Buono mask_in_32b = false; 2631c4f6a4a3SDaniele Buono } 2632c4f6a4a3SDaniele Buono #endif 2633c4f6a4a3SDaniele Buono if (mask_in_32b) { 2634fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2635fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2636fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2637fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2638fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2639fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2640fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2641fcf5ef2aSThomas Huth } else { 2642fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2643fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2644fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2645fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2646fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2647fcf5ef2aSThomas Huth #else 2648fcf5ef2aSThomas Huth g_assert_not_reached(); 2649fcf5ef2aSThomas Huth #endif 2650fcf5ef2aSThomas Huth } 2651fcf5ef2aSThomas Huth 2652fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2653fcf5ef2aSThomas Huth 2654fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2655fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2656fcf5ef2aSThomas Huth } 2657fcf5ef2aSThomas Huth } 2658fcf5ef2aSThomas Huth 2659fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2660fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2661fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2662fcf5ef2aSThomas Huth { \ 2663fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2664fcf5ef2aSThomas Huth } \ 2665fcf5ef2aSThomas Huth \ 2666fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2667fcf5ef2aSThomas Huth { \ 2668fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2669fcf5ef2aSThomas Huth } 2670fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2671fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2672fcf5ef2aSThomas Huth { \ 2673fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2674fcf5ef2aSThomas Huth } \ 2675fcf5ef2aSThomas Huth \ 2676fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2677fcf5ef2aSThomas Huth { \ 2678fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2679fcf5ef2aSThomas Huth } \ 2680fcf5ef2aSThomas Huth \ 2681fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2682fcf5ef2aSThomas Huth { \ 2683fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2684fcf5ef2aSThomas Huth } \ 2685fcf5ef2aSThomas Huth \ 2686fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2687fcf5ef2aSThomas Huth { \ 2688fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2689fcf5ef2aSThomas Huth } 2690fcf5ef2aSThomas Huth 2691fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2692fcf5ef2aSThomas Huth { 2693fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2694fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26957b4d326fSRichard Henderson int len = me - mb + 1; 26967b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2697fcf5ef2aSThomas Huth 26987b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 26997b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27007b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27017b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2702fcf5ef2aSThomas Huth } else { 2703fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2704fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2705fcf5ef2aSThomas Huth } 2706fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2707fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2708fcf5ef2aSThomas Huth } 2709fcf5ef2aSThomas Huth } 2710fcf5ef2aSThomas Huth 2711fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2712fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2713fcf5ef2aSThomas Huth { 2714fcf5ef2aSThomas Huth uint32_t sh, mb; 2715fcf5ef2aSThomas Huth 2716fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2717fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2718fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2719fcf5ef2aSThomas Huth } 2720fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2721fcf5ef2aSThomas Huth 2722fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2723fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2724fcf5ef2aSThomas Huth { 2725fcf5ef2aSThomas Huth uint32_t sh, me; 2726fcf5ef2aSThomas Huth 2727fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2728fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2729fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2730fcf5ef2aSThomas Huth } 2731fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2732fcf5ef2aSThomas Huth 2733fcf5ef2aSThomas Huth /* rldic - rldic. */ 2734fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2735fcf5ef2aSThomas Huth { 2736fcf5ef2aSThomas Huth uint32_t sh, mb; 2737fcf5ef2aSThomas Huth 2738fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2739fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2740fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2741fcf5ef2aSThomas Huth } 2742fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2743fcf5ef2aSThomas Huth 2744fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2745fcf5ef2aSThomas Huth { 2746fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2747fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2748fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2749fcf5ef2aSThomas Huth TCGv t0; 2750fcf5ef2aSThomas Huth 2751fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2752fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2753fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2754fcf5ef2aSThomas Huth 2755fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2756fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2757fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2758fcf5ef2aSThomas Huth } 2759fcf5ef2aSThomas Huth } 2760fcf5ef2aSThomas Huth 2761fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2762fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2763fcf5ef2aSThomas Huth { 2764fcf5ef2aSThomas Huth uint32_t mb; 2765fcf5ef2aSThomas Huth 2766fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2767fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2768fcf5ef2aSThomas Huth } 2769fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2770fcf5ef2aSThomas Huth 2771fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2772fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2773fcf5ef2aSThomas Huth { 2774fcf5ef2aSThomas Huth uint32_t me; 2775fcf5ef2aSThomas Huth 2776fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2777fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2778fcf5ef2aSThomas Huth } 2779fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2780fcf5ef2aSThomas Huth 2781fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2782fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2783fcf5ef2aSThomas Huth { 2784fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2785fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2786fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2787fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2788fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2789fcf5ef2aSThomas Huth 2790fcf5ef2aSThomas Huth if (mb <= me) { 2791fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2792fcf5ef2aSThomas Huth } else { 2793fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2794fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2795fcf5ef2aSThomas Huth 2796fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2797fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2798fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2799fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2800fcf5ef2aSThomas Huth } 2801fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2802fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2803fcf5ef2aSThomas Huth } 2804fcf5ef2aSThomas Huth } 2805fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2806fcf5ef2aSThomas Huth #endif 2807fcf5ef2aSThomas Huth 2808fcf5ef2aSThomas Huth /*** Integer shift ***/ 2809fcf5ef2aSThomas Huth 2810fcf5ef2aSThomas Huth /* slw & slw. */ 2811fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2812fcf5ef2aSThomas Huth { 2813fcf5ef2aSThomas Huth TCGv t0, t1; 2814fcf5ef2aSThomas Huth 2815fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2816fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2817fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2818fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2819fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2820fcf5ef2aSThomas Huth #else 2821fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2822fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2823fcf5ef2aSThomas Huth #endif 2824fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2825fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2826fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2827fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2828fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2829efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2830fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2831fcf5ef2aSThomas Huth } 2832efe843d8SDavid Gibson } 2833fcf5ef2aSThomas Huth 2834fcf5ef2aSThomas Huth /* sraw & sraw. */ 2835fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2836fcf5ef2aSThomas Huth { 2837fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2838fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2839efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2840fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2841fcf5ef2aSThomas Huth } 2842efe843d8SDavid Gibson } 2843fcf5ef2aSThomas Huth 2844fcf5ef2aSThomas Huth /* srawi & srawi. */ 2845fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2846fcf5ef2aSThomas Huth { 2847fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2848fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2849fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2850fcf5ef2aSThomas Huth if (sh == 0) { 2851fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2852fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2853af1c259fSSandipan Das if (is_isa300(ctx)) { 2854af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2855af1c259fSSandipan Das } 2856fcf5ef2aSThomas Huth } else { 2857fcf5ef2aSThomas Huth TCGv t0; 2858fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2859fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2860fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2861fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2862fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2863fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2864af1c259fSSandipan Das if (is_isa300(ctx)) { 2865af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2866af1c259fSSandipan Das } 2867fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2868fcf5ef2aSThomas Huth } 2869fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2870fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2871fcf5ef2aSThomas Huth } 2872fcf5ef2aSThomas Huth } 2873fcf5ef2aSThomas Huth 2874fcf5ef2aSThomas Huth /* srw & srw. */ 2875fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2876fcf5ef2aSThomas Huth { 2877fcf5ef2aSThomas Huth TCGv t0, t1; 2878fcf5ef2aSThomas Huth 2879fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2880fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2881fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2882fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2883fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2884fcf5ef2aSThomas Huth #else 2885fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2886fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2887fcf5ef2aSThomas Huth #endif 2888fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2889fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2890fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2891fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2892fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2893efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2894fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2895fcf5ef2aSThomas Huth } 2896efe843d8SDavid Gibson } 2897fcf5ef2aSThomas Huth 2898fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2899fcf5ef2aSThomas Huth /* sld & sld. */ 2900fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2901fcf5ef2aSThomas Huth { 2902fcf5ef2aSThomas Huth TCGv t0, t1; 2903fcf5ef2aSThomas Huth 2904fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2905fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2906fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2907fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2908fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2909fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2910fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2911fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2912efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2913fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2914fcf5ef2aSThomas Huth } 2915efe843d8SDavid Gibson } 2916fcf5ef2aSThomas Huth 2917fcf5ef2aSThomas Huth /* srad & srad. */ 2918fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2919fcf5ef2aSThomas Huth { 2920fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2921fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2922efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2923fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2924fcf5ef2aSThomas Huth } 2925efe843d8SDavid Gibson } 2926fcf5ef2aSThomas Huth /* sradi & sradi. */ 2927fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2928fcf5ef2aSThomas Huth { 2929fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2930fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2931fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2932fcf5ef2aSThomas Huth if (sh == 0) { 2933fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2934fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2935af1c259fSSandipan Das if (is_isa300(ctx)) { 2936af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2937af1c259fSSandipan Das } 2938fcf5ef2aSThomas Huth } else { 2939fcf5ef2aSThomas Huth TCGv t0; 2940fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2941fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2942fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2943fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2944fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2945af1c259fSSandipan Das if (is_isa300(ctx)) { 2946af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2947af1c259fSSandipan Das } 2948fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2949fcf5ef2aSThomas Huth } 2950fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2951fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2952fcf5ef2aSThomas Huth } 2953fcf5ef2aSThomas Huth } 2954fcf5ef2aSThomas Huth 2955fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2956fcf5ef2aSThomas Huth { 2957fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2958fcf5ef2aSThomas Huth } 2959fcf5ef2aSThomas Huth 2960fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2961fcf5ef2aSThomas Huth { 2962fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2963fcf5ef2aSThomas Huth } 2964fcf5ef2aSThomas Huth 2965fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2966fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2967fcf5ef2aSThomas Huth { 2968fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2969fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2970fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2971fcf5ef2aSThomas Huth 2972fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2973fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2974fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2975fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2976fcf5ef2aSThomas Huth } 2977fcf5ef2aSThomas Huth } 2978fcf5ef2aSThomas Huth 2979fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2980fcf5ef2aSThomas Huth { 2981fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2982fcf5ef2aSThomas Huth } 2983fcf5ef2aSThomas Huth 2984fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2985fcf5ef2aSThomas Huth { 2986fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2987fcf5ef2aSThomas Huth } 2988fcf5ef2aSThomas Huth 2989fcf5ef2aSThomas Huth /* srd & srd. */ 2990fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2991fcf5ef2aSThomas Huth { 2992fcf5ef2aSThomas Huth TCGv t0, t1; 2993fcf5ef2aSThomas Huth 2994fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2995fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2996fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2997fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2998fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2999fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3000fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3001fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3002efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3003fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3004fcf5ef2aSThomas Huth } 3005efe843d8SDavid Gibson } 3006fcf5ef2aSThomas Huth #endif 3007fcf5ef2aSThomas Huth 3008fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3009fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3010fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3011fcf5ef2aSThomas Huth target_long maskl) 3012fcf5ef2aSThomas Huth { 3013fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3014fcf5ef2aSThomas Huth 3015fcf5ef2aSThomas Huth simm &= ~maskl; 3016fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3017fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3018fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3019fcf5ef2aSThomas Huth } 3020fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3021fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3022fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3023fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3024fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3025fcf5ef2aSThomas Huth } 3026fcf5ef2aSThomas Huth } else { 3027fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3028fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3029fcf5ef2aSThomas Huth } else { 3030fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3031fcf5ef2aSThomas Huth } 3032fcf5ef2aSThomas Huth } 3033fcf5ef2aSThomas Huth } 3034fcf5ef2aSThomas Huth 3035fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3036fcf5ef2aSThomas Huth { 3037fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3038fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3039fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3040fcf5ef2aSThomas Huth } else { 3041fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3042fcf5ef2aSThomas Huth } 3043fcf5ef2aSThomas Huth } else { 3044fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3045fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3046fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3047fcf5ef2aSThomas Huth } 3048fcf5ef2aSThomas Huth } 3049fcf5ef2aSThomas Huth } 3050fcf5ef2aSThomas Huth 3051fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3052fcf5ef2aSThomas Huth { 3053fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3054fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3055fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3056fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3057fcf5ef2aSThomas Huth } else { 3058fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3059fcf5ef2aSThomas Huth } 3060fcf5ef2aSThomas Huth } 3061fcf5ef2aSThomas Huth 3062fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3063fcf5ef2aSThomas Huth target_long val) 3064fcf5ef2aSThomas Huth { 3065fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3066fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3067fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3068fcf5ef2aSThomas Huth } 3069fcf5ef2aSThomas Huth } 3070fcf5ef2aSThomas Huth 3071fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3072fcf5ef2aSThomas Huth { 3073fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3074fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3075fcf5ef2aSThomas Huth } 3076fcf5ef2aSThomas Huth 3077eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3078eb63efd9SFernando Eckhardt Valle { 3079eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3080eb63efd9SFernando Eckhardt Valle if (ra) { 3081eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3082eb63efd9SFernando Eckhardt Valle } else { 3083eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3084eb63efd9SFernando Eckhardt Valle } 3085eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3086eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3087eb63efd9SFernando Eckhardt Valle } 3088eb63efd9SFernando Eckhardt Valle return ea; 3089eb63efd9SFernando Eckhardt Valle } 3090eb63efd9SFernando Eckhardt Valle 3091fcf5ef2aSThomas Huth /*** Integer load ***/ 3092fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3093fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3094fcf5ef2aSThomas Huth 3095fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3096fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3097fcf5ef2aSThomas Huth TCGv val, \ 3098fcf5ef2aSThomas Huth TCGv addr) \ 3099fcf5ef2aSThomas Huth { \ 3100fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3101fcf5ef2aSThomas Huth } 3102fcf5ef2aSThomas Huth 3103fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3104fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3105fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3106fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3107fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3108fcf5ef2aSThomas Huth 3109fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3110fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3111fcf5ef2aSThomas Huth 3112fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3113fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3114fcf5ef2aSThomas Huth TCGv_i64 val, \ 3115fcf5ef2aSThomas Huth TCGv addr) \ 3116fcf5ef2aSThomas Huth { \ 3117fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3118fcf5ef2aSThomas Huth } 3119fcf5ef2aSThomas Huth 3120fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3121fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3122fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3123fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3124fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3125fcf5ef2aSThomas Huth 3126fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3127fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3128fcf5ef2aSThomas Huth #endif 3129fcf5ef2aSThomas Huth 3130fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3131fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3132fcf5ef2aSThomas Huth TCGv val, \ 3133fcf5ef2aSThomas Huth TCGv addr) \ 3134fcf5ef2aSThomas Huth { \ 3135fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3136fcf5ef2aSThomas Huth } 3137fcf5ef2aSThomas Huth 3138e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3139fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3140e8f4c8d6SRichard Henderson #endif 3141fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3142fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3143fcf5ef2aSThomas Huth 3144fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3145fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3146fcf5ef2aSThomas Huth 3147fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3148fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3149fcf5ef2aSThomas Huth TCGv_i64 val, \ 3150fcf5ef2aSThomas Huth TCGv addr) \ 3151fcf5ef2aSThomas Huth { \ 3152fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3153fcf5ef2aSThomas Huth } 3154fcf5ef2aSThomas Huth 3155fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3156fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3157fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3158fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3159fcf5ef2aSThomas Huth 3160fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3161fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3162fcf5ef2aSThomas Huth #endif 3163fcf5ef2aSThomas Huth 3164fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3165fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3166fcf5ef2aSThomas Huth { \ 3167fcf5ef2aSThomas Huth TCGv EA; \ 31689f0cf041SMatheus Ferst chk(ctx); \ 3169fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3170fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3171fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3172fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3173fcf5ef2aSThomas Huth } 3174fcf5ef2aSThomas Huth 3175fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3176fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3177fcf5ef2aSThomas Huth 3178fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3179fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3180fcf5ef2aSThomas Huth 318150728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 318250728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 318350728199SRoman Kapl { \ 318450728199SRoman Kapl TCGv EA; \ 31859f0cf041SMatheus Ferst CHK_SV(ctx); \ 318650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 318750728199SRoman Kapl EA = tcg_temp_new(); \ 318850728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 318950728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 319050728199SRoman Kapl } 319150728199SRoman Kapl 319250728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 319350728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 319450728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 319550728199SRoman Kapl #if defined(TARGET_PPC64) 3196fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 319750728199SRoman Kapl #endif 319850728199SRoman Kapl 3199fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3200fcf5ef2aSThomas Huth /* CI load/store variants */ 3201fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3202fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3203fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3204fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3205fcf5ef2aSThomas Huth #endif 3206fcf5ef2aSThomas Huth 3207fcf5ef2aSThomas Huth /*** Integer store ***/ 3208fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3209fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3210fcf5ef2aSThomas Huth { \ 3211fcf5ef2aSThomas Huth TCGv EA; \ 32129f0cf041SMatheus Ferst chk(ctx); \ 3213fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3214fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3215fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3216fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3217fcf5ef2aSThomas Huth } 3218fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3219fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3220fcf5ef2aSThomas Huth 3221fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3222fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3223fcf5ef2aSThomas Huth 322450728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 322550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 322650728199SRoman Kapl { \ 322750728199SRoman Kapl TCGv EA; \ 32289f0cf041SMatheus Ferst CHK_SV(ctx); \ 322950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 323050728199SRoman Kapl EA = tcg_temp_new(); \ 323150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 323250728199SRoman Kapl tcg_gen_qemu_st_tl( \ 323350728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 323450728199SRoman Kapl } 323550728199SRoman Kapl 323650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 323750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 323850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 323950728199SRoman Kapl #if defined(TARGET_PPC64) 3240fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 324150728199SRoman Kapl #endif 324250728199SRoman Kapl 3243fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3244fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3245fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3246fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3247fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3248fcf5ef2aSThomas Huth #endif 3249fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3250fcf5ef2aSThomas Huth 3251fcf5ef2aSThomas Huth /* lhbrx */ 3252fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3253fcf5ef2aSThomas Huth 3254fcf5ef2aSThomas Huth /* lwbrx */ 3255fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3256fcf5ef2aSThomas Huth 3257fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3258fcf5ef2aSThomas Huth /* ldbrx */ 3259fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3260fcf5ef2aSThomas Huth /* stdbrx */ 3261fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3262fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3263fcf5ef2aSThomas Huth 3264fcf5ef2aSThomas Huth /* sthbrx */ 3265fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3266fcf5ef2aSThomas Huth /* stwbrx */ 3267fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3268fcf5ef2aSThomas Huth 3269fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3270fcf5ef2aSThomas Huth 3271fcf5ef2aSThomas Huth /* lmw */ 3272fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3273fcf5ef2aSThomas Huth { 3274fcf5ef2aSThomas Huth TCGv t0; 3275fcf5ef2aSThomas Huth TCGv_i32 t1; 3276fcf5ef2aSThomas Huth 3277fcf5ef2aSThomas Huth if (ctx->le_mode) { 3278fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3279fcf5ef2aSThomas Huth return; 3280fcf5ef2aSThomas Huth } 3281fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3282fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 32837058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 3284fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3285fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3286fcf5ef2aSThomas Huth } 3287fcf5ef2aSThomas Huth 3288fcf5ef2aSThomas Huth /* stmw */ 3289fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3290fcf5ef2aSThomas Huth { 3291fcf5ef2aSThomas Huth TCGv t0; 3292fcf5ef2aSThomas Huth TCGv_i32 t1; 3293fcf5ef2aSThomas Huth 3294fcf5ef2aSThomas Huth if (ctx->le_mode) { 3295fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3296fcf5ef2aSThomas Huth return; 3297fcf5ef2aSThomas Huth } 3298fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3299fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33007058ff52SRichard Henderson t1 = tcg_constant_i32(rS(ctx->opcode)); 3301fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3302fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3303fcf5ef2aSThomas Huth } 3304fcf5ef2aSThomas Huth 3305fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3306fcf5ef2aSThomas Huth 3307fcf5ef2aSThomas Huth /* lswi */ 3308efe843d8SDavid Gibson /* 3309efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3310efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3311efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3312efe843d8SDavid Gibson * spec... 3313fcf5ef2aSThomas Huth */ 3314fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3315fcf5ef2aSThomas Huth { 3316fcf5ef2aSThomas Huth TCGv t0; 3317fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3318fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3319fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3320fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3321fcf5ef2aSThomas Huth int nr; 3322fcf5ef2aSThomas Huth 3323fcf5ef2aSThomas Huth if (ctx->le_mode) { 3324fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3325fcf5ef2aSThomas Huth return; 3326fcf5ef2aSThomas Huth } 3327efe843d8SDavid Gibson if (nb == 0) { 3328fcf5ef2aSThomas Huth nb = 32; 3329efe843d8SDavid Gibson } 3330f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3331fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3332fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3333fcf5ef2aSThomas Huth return; 3334fcf5ef2aSThomas Huth } 3335fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3336fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3337fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 33387058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 33397058ff52SRichard Henderson t2 = tcg_constant_i32(start); 3340fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3341fcf5ef2aSThomas Huth } 3342fcf5ef2aSThomas Huth 3343fcf5ef2aSThomas Huth /* lswx */ 3344fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3345fcf5ef2aSThomas Huth { 3346fcf5ef2aSThomas Huth TCGv t0; 3347fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3348fcf5ef2aSThomas Huth 3349fcf5ef2aSThomas Huth if (ctx->le_mode) { 3350fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3351fcf5ef2aSThomas Huth return; 3352fcf5ef2aSThomas Huth } 3353fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3354fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3355fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 33567058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 33577058ff52SRichard Henderson t2 = tcg_constant_i32(rA(ctx->opcode)); 33587058ff52SRichard Henderson t3 = tcg_constant_i32(rB(ctx->opcode)); 3359fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3360fcf5ef2aSThomas Huth } 3361fcf5ef2aSThomas Huth 3362fcf5ef2aSThomas Huth /* stswi */ 3363fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3364fcf5ef2aSThomas Huth { 3365fcf5ef2aSThomas Huth TCGv t0; 3366fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3367fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3368fcf5ef2aSThomas Huth 3369fcf5ef2aSThomas Huth if (ctx->le_mode) { 3370fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3371fcf5ef2aSThomas Huth return; 3372fcf5ef2aSThomas Huth } 3373fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3374fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3375fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3376efe843d8SDavid Gibson if (nb == 0) { 3377fcf5ef2aSThomas Huth nb = 32; 3378efe843d8SDavid Gibson } 33797058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 33807058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3381fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3382fcf5ef2aSThomas Huth } 3383fcf5ef2aSThomas Huth 3384fcf5ef2aSThomas Huth /* stswx */ 3385fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3386fcf5ef2aSThomas Huth { 3387fcf5ef2aSThomas Huth TCGv t0; 3388fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3389fcf5ef2aSThomas Huth 3390fcf5ef2aSThomas Huth if (ctx->le_mode) { 3391fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3392fcf5ef2aSThomas Huth return; 3393fcf5ef2aSThomas Huth } 3394fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3395fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3396fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3397fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3398fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3399fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 34007058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3401fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3402fcf5ef2aSThomas Huth } 3403fcf5ef2aSThomas Huth 3404fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3405fcf5ef2aSThomas Huth /* eieio */ 3406fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3407fcf5ef2aSThomas Huth { 3408fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3409fcb830afSNicholas Piggin 3410fcb830afSNicholas Piggin /* 3411fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3412fcb830afSNicholas Piggin * operations in the set: 3413fcb830afSNicholas Piggin * - loads from CI memory. 3414fcb830afSNicholas Piggin * - stores to CI memory. 3415fcb830afSNicholas Piggin * - stores to WT memory. 3416fcb830afSNicholas Piggin * 3417fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3418fcb830afSNicholas Piggin * - stores to cacheble memory. 3419fcb830afSNicholas Piggin * 3420fcb830afSNicholas Piggin * It also serializes instructions: 3421fcb830afSNicholas Piggin * - dcbt and dcbst. 3422fcb830afSNicholas Piggin * 3423fcb830afSNicholas Piggin * It separately serializes: 3424fcb830afSNicholas Piggin * - tlbie and tlbsync. 3425fcb830afSNicholas Piggin * 3426fcb830afSNicholas Piggin * And separately serializes: 3427fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3428fcb830afSNicholas Piggin * 3429fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3430fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3431fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3432fcb830afSNicholas Piggin * serialization. 3433fcb830afSNicholas Piggin */ 3434c8fd8373SCédric Le Goater 3435c8fd8373SCédric Le Goater /* 3436c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3437c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3438c8fd8373SCédric Le Goater */ 3439c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3440c8fd8373SCédric Le Goater /* 3441c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3442c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3443c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3444c8fd8373SCédric Le Goater * complain to the user. 3445c8fd8373SCédric Le Goater */ 3446c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3447c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 34482c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3449c8fd8373SCédric Le Goater } else { 3450c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3451c8fd8373SCédric Le Goater } 3452c8fd8373SCédric Le Goater } 3453c8fd8373SCédric Le Goater 3454c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3455fcf5ef2aSThomas Huth } 3456fcf5ef2aSThomas Huth 3457fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3458fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3459fcf5ef2aSThomas Huth { 3460fcf5ef2aSThomas Huth TCGv_i32 t; 3461fcf5ef2aSThomas Huth TCGLabel *l; 3462fcf5ef2aSThomas Huth 3463fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3464fcf5ef2aSThomas Huth return; 3465fcf5ef2aSThomas Huth } 3466fcf5ef2aSThomas Huth l = gen_new_label(); 3467fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3468fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3469fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3470fcf5ef2aSThomas Huth if (global) { 3471fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3472fcf5ef2aSThomas Huth } else { 3473fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3474fcf5ef2aSThomas Huth } 3475fcf5ef2aSThomas Huth gen_set_label(l); 3476fcf5ef2aSThomas Huth } 3477fcf5ef2aSThomas Huth #else 3478fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3479fcf5ef2aSThomas Huth #endif 3480fcf5ef2aSThomas Huth 3481fcf5ef2aSThomas Huth /* isync */ 3482fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3483fcf5ef2aSThomas Huth { 3484fcf5ef2aSThomas Huth /* 3485fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3486fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3487fcf5ef2aSThomas Huth */ 3488fcf5ef2aSThomas Huth if (!ctx->pr) { 3489fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3490fcf5ef2aSThomas Huth } 34914771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3492d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3493fcf5ef2aSThomas Huth } 3494fcf5ef2aSThomas Huth 3495fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3496fcf5ef2aSThomas Huth 349714776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 34982a4e6c1bSRichard Henderson { 34992a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 35002a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 35012a4e6c1bSRichard Henderson 35022a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 35032a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 35042a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 35052a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 3506392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 35072a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 35082a4e6c1bSRichard Henderson } 35092a4e6c1bSRichard Henderson 3510fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3511fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3512fcf5ef2aSThomas Huth { \ 35132a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3514fcf5ef2aSThomas Huth } 3515fcf5ef2aSThomas Huth 3516fcf5ef2aSThomas Huth /* lwarx */ 3517fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3518fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3519fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3520fcf5ef2aSThomas Huth 352114776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 352220923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 352320923c1dSRichard Henderson { 352420923c1dSRichard Henderson TCGv t = tcg_temp_new(); 352520923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 352620923c1dSRichard Henderson TCGv u = tcg_temp_new(); 352720923c1dSRichard Henderson 352820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 352920923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 353020923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 353120923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 353220923c1dSRichard Henderson 353320923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 353420923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 353520923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 353620923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 353720923c1dSRichard Henderson 353820923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 353920923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 354020923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 354120923c1dSRichard Henderson } 354220923c1dSRichard Henderson 354314776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 354420ba8504SRichard Henderson { 354520ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 354620ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 354720923c1dSRichard Henderson int rt = rD(ctx->opcode); 354820923c1dSRichard Henderson bool need_serial; 354920ba8504SRichard Henderson TCGv src, dst; 355020ba8504SRichard Henderson 355120ba8504SRichard Henderson gen_addr_register(ctx, EA); 355220923c1dSRichard Henderson dst = cpu_gpr[rt]; 355320923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 355420ba8504SRichard Henderson 355520923c1dSRichard Henderson need_serial = false; 355620ba8504SRichard Henderson memop |= MO_ALIGN; 355720ba8504SRichard Henderson switch (gpr_FC) { 355820ba8504SRichard Henderson case 0: /* Fetch and add */ 355920ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 356020ba8504SRichard Henderson break; 356120ba8504SRichard Henderson case 1: /* Fetch and xor */ 356220ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 356320ba8504SRichard Henderson break; 356420ba8504SRichard Henderson case 2: /* Fetch and or */ 356520ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 356620ba8504SRichard Henderson break; 356720ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 356820ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 356920ba8504SRichard Henderson break; 3570b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3571b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3572b8ce0f86SRichard Henderson break; 3573b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3574b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3575b8ce0f86SRichard Henderson break; 3576b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3577b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3578b8ce0f86SRichard Henderson break; 3579b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3580b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3581b8ce0f86SRichard Henderson break; 358220ba8504SRichard Henderson case 8: /* Swap */ 358320ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 358420ba8504SRichard Henderson break; 358520923c1dSRichard Henderson 358620923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 358720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 358820923c1dSRichard Henderson need_serial = true; 358920923c1dSRichard Henderson } else { 359020923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 359120923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 359220923c1dSRichard Henderson 359320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 359420923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 359520923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 359620923c1dSRichard Henderson } else { 359720923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 359820923c1dSRichard Henderson } 359920923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 360020923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 360120923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 360220923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 360320923c1dSRichard Henderson } 360420ba8504SRichard Henderson break; 360520923c1dSRichard Henderson 360620923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 360720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 360820923c1dSRichard Henderson need_serial = true; 360920923c1dSRichard Henderson } else { 361020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 361120923c1dSRichard Henderson } 361220923c1dSRichard Henderson break; 361320923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 361420923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 361520923c1dSRichard Henderson need_serial = true; 361620923c1dSRichard Henderson } else { 361720923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 361820923c1dSRichard Henderson } 361920923c1dSRichard Henderson break; 362020923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 362120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 362220923c1dSRichard Henderson need_serial = true; 362320923c1dSRichard Henderson } else { 362420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 362520923c1dSRichard Henderson } 362620923c1dSRichard Henderson break; 362720923c1dSRichard Henderson 362820ba8504SRichard Henderson default: 362920ba8504SRichard Henderson /* invoke data storage error handler */ 363020ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 363120ba8504SRichard Henderson } 363220923c1dSRichard Henderson 363320923c1dSRichard Henderson if (need_serial) { 363420923c1dSRichard Henderson /* Restart with exclusive lock. */ 363520923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 363620923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 363720923c1dSRichard Henderson } 3638a68a6146SBalamuruhan S } 3639a68a6146SBalamuruhan S 364020ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 364120ba8504SRichard Henderson { 364220ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 364320ba8504SRichard Henderson } 364420ba8504SRichard Henderson 364520ba8504SRichard Henderson #ifdef TARGET_PPC64 364620ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 364720ba8504SRichard Henderson { 3648fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 364920ba8504SRichard Henderson } 3650a68a6146SBalamuruhan S #endif 3651a68a6146SBalamuruhan S 365214776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 36539deb041cSRichard Henderson { 36549deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 36559deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 36569deb041cSRichard Henderson TCGv src, discard; 36579deb041cSRichard Henderson 36589deb041cSRichard Henderson gen_addr_register(ctx, EA); 36599deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 36609deb041cSRichard Henderson discard = tcg_temp_new(); 36619deb041cSRichard Henderson 36629deb041cSRichard Henderson memop |= MO_ALIGN; 36639deb041cSRichard Henderson switch (gpr_FC) { 36649deb041cSRichard Henderson case 0: /* add and Store */ 36659deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36669deb041cSRichard Henderson break; 36679deb041cSRichard Henderson case 1: /* xor and Store */ 36689deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36699deb041cSRichard Henderson break; 36709deb041cSRichard Henderson case 2: /* Or and Store */ 36719deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36729deb041cSRichard Henderson break; 36739deb041cSRichard Henderson case 3: /* 'and' and Store */ 36749deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36759deb041cSRichard Henderson break; 36769deb041cSRichard Henderson case 4: /* Store max unsigned */ 3677b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3678b8ce0f86SRichard Henderson break; 36799deb041cSRichard Henderson case 5: /* Store max signed */ 3680b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3681b8ce0f86SRichard Henderson break; 36829deb041cSRichard Henderson case 6: /* Store min unsigned */ 3683b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3684b8ce0f86SRichard Henderson break; 36859deb041cSRichard Henderson case 7: /* Store min signed */ 3686b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3687b8ce0f86SRichard Henderson break; 36889deb041cSRichard Henderson case 24: /* Store twin */ 36897fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 36907fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 36917fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 36927fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 36937fbc2b20SRichard Henderson } else { 36947fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 36957fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 36967fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 36977fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 36987fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 36997fbc2b20SRichard Henderson 37007fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 37017fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 37027fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 37037fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 37047fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 37057fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 37067fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 37077fbc2b20SRichard Henderson } 37089deb041cSRichard Henderson break; 37099deb041cSRichard Henderson default: 37109deb041cSRichard Henderson /* invoke data storage error handler */ 37119deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 37129deb041cSRichard Henderson } 3713a3401188SBalamuruhan S } 3714a3401188SBalamuruhan S 37159deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 37169deb041cSRichard Henderson { 37179deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 37189deb041cSRichard Henderson } 37199deb041cSRichard Henderson 37209deb041cSRichard Henderson #ifdef TARGET_PPC64 37219deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 37229deb041cSRichard Henderson { 3723fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 37249deb041cSRichard Henderson } 3725a3401188SBalamuruhan S #endif 3726a3401188SBalamuruhan S 372714776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3728fcf5ef2aSThomas Huth { 372921ee07e7SNicholas Piggin TCGLabel *lfail; 373021ee07e7SNicholas Piggin TCGv EA; 373121ee07e7SNicholas Piggin TCGv cr0; 373221ee07e7SNicholas Piggin TCGv t0; 373321ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3734fcf5ef2aSThomas Huth 373521ee07e7SNicholas Piggin lfail = gen_new_label(); 373621ee07e7SNicholas Piggin EA = tcg_temp_new(); 373721ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3738253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 373921ee07e7SNicholas Piggin 374021ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 374121ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 374221ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 374321ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 374421ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 374521ee07e7SNicholas Piggin 3746253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 374721ee07e7SNicholas Piggin cpu_gpr[rs], ctx->mem_idx, 3748253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3749253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3750253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 375121ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3752253ce7b2SNikunj A Dadhania 375321ee07e7SNicholas Piggin gen_set_label(lfail); 375421ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3755fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3756fcf5ef2aSThomas Huth } 3757fcf5ef2aSThomas Huth 3758fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3759fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3760fcf5ef2aSThomas Huth { \ 3761d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3762fcf5ef2aSThomas Huth } 3763fcf5ef2aSThomas Huth 3764fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3765fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3766fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3767fcf5ef2aSThomas Huth 3768fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3769fcf5ef2aSThomas Huth /* ldarx */ 3770fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3771fcf5ef2aSThomas Huth /* stdcx. */ 3772fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3773fcf5ef2aSThomas Huth 3774fcf5ef2aSThomas Huth /* lqarx */ 3775fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3776fcf5ef2aSThomas Huth { 3777fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 377894bf2658SRichard Henderson TCGv EA, hi, lo; 377957b38ffdSRichard Henderson TCGv_i128 t16; 3780fcf5ef2aSThomas Huth 3781fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3782fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3783fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3784fcf5ef2aSThomas Huth return; 3785fcf5ef2aSThomas Huth } 3786fcf5ef2aSThomas Huth 3787fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 378894bf2658SRichard Henderson EA = tcg_temp_new(); 3789fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 379094bf2658SRichard Henderson 379194bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 379294bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 379394bf2658SRichard Henderson hi = cpu_gpr[rd]; 379494bf2658SRichard Henderson 379557b38ffdSRichard Henderson t16 = tcg_temp_new_i128(); 379657b38ffdSRichard Henderson tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 379757b38ffdSRichard Henderson tcg_gen_extr_i128_i64(lo, hi, t16); 379894bf2658SRichard Henderson 3799e025e8f5SNicholas Piggin tcg_gen_mov_tl(cpu_reserve, EA); 3800392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, 16); 380194bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 380294bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3803fcf5ef2aSThomas Huth } 3804fcf5ef2aSThomas Huth 3805fcf5ef2aSThomas Huth /* stqcx. */ 3806fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3807fcf5ef2aSThomas Huth { 380821ee07e7SNicholas Piggin TCGLabel *lfail; 3809894448aeSRichard Henderson TCGv EA, t0, t1; 381021ee07e7SNicholas Piggin TCGv cr0; 3811894448aeSRichard Henderson TCGv_i128 cmp, val; 381221ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3813fcf5ef2aSThomas Huth 38144a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3815fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3816fcf5ef2aSThomas Huth return; 3817fcf5ef2aSThomas Huth } 38184a9b3c5dSRichard Henderson 381921ee07e7SNicholas Piggin lfail = gen_new_label(); 38204a9b3c5dSRichard Henderson EA = tcg_temp_new(); 382121ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3822fcf5ef2aSThomas Huth 382321ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 382421ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 382521ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 382621ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 382721ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 38284a9b3c5dSRichard Henderson 3829894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 3830894448aeSRichard Henderson val = tcg_temp_new_i128(); 38314a9b3c5dSRichard Henderson 3832894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 38334a9b3c5dSRichard Henderson 3834894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3835894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 38364a9b3c5dSRichard Henderson 3837894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3838894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 3839894448aeSRichard Henderson 3840894448aeSRichard Henderson t0 = tcg_temp_new(); 3841894448aeSRichard Henderson t1 = tcg_temp_new(); 3842894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 3843894448aeSRichard Henderson 3844894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3845894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3846894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 3847894448aeSRichard Henderson 3848894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3849894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 385021ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3851894448aeSRichard Henderson 385221ee07e7SNicholas Piggin gen_set_label(lfail); 385321ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 38544a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 38554a9b3c5dSRichard Henderson } 3856fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3857fcf5ef2aSThomas Huth 3858fcf5ef2aSThomas Huth /* sync */ 3859fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3860fcf5ef2aSThomas Huth { 386103abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 3862fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3863fcf5ef2aSThomas Huth 386403abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 386503abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 386603abfd90SNicholas Piggin } 386703abfd90SNicholas Piggin 3868fcf5ef2aSThomas Huth /* 3869fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3870fcf5ef2aSThomas Huth * 3871fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3872fcf5ef2aSThomas Huth * 3873fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3874fcf5ef2aSThomas Huth * check MSR_PR as well. 3875fcf5ef2aSThomas Huth */ 3876fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3877fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3878fcf5ef2aSThomas Huth } 387903abfd90SNicholas Piggin 388003abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 3881fcf5ef2aSThomas Huth } 3882fcf5ef2aSThomas Huth 3883fcf5ef2aSThomas Huth /* wait */ 3884fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3885fcf5ef2aSThomas Huth { 38860c9717ffSNicholas Piggin uint32_t wc; 38870c9717ffSNicholas Piggin 38880c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 38890c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 38900c9717ffSNicholas Piggin 38910c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 38920c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 38930c9717ffSNicholas Piggin wc = WC(ctx->opcode); 38940c9717ffSNicholas Piggin } else { 38950c9717ffSNicholas Piggin wc = 0; 38960c9717ffSNicholas Piggin } 38970c9717ffSNicholas Piggin 38980c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 38990c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 39000c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39010c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 39020c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 39030c9717ffSNicholas Piggin 39040c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 39050c9717ffSNicholas Piggin if (wc == 3) { 39060c9717ffSNicholas Piggin gen_invalid(ctx); 39070c9717ffSNicholas Piggin return; 39080c9717ffSNicholas Piggin } 39090c9717ffSNicholas Piggin 39100c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 39110c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 39120c9717ffSNicholas Piggin gen_invalid(ctx); 39130c9717ffSNicholas Piggin return; 39140c9717ffSNicholas Piggin } 39150c9717ffSNicholas Piggin 39160c9717ffSNicholas Piggin } else { /* ISA300 */ 39170c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 39180c9717ffSNicholas Piggin if (wc > 0) { 39190c9717ffSNicholas Piggin gen_invalid(ctx); 39200c9717ffSNicholas Piggin return; 39210c9717ffSNicholas Piggin } 39220c9717ffSNicholas Piggin } 39230c9717ffSNicholas Piggin 39240c9717ffSNicholas Piggin } else { 39250c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 39260c9717ffSNicholas Piggin gen_invalid(ctx); 39270c9717ffSNicholas Piggin return; 39280c9717ffSNicholas Piggin } 39290c9717ffSNicholas Piggin 39300c9717ffSNicholas Piggin /* 39310c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 39320c9717ffSNicholas Piggin * to occur. 39330c9717ffSNicholas Piggin */ 39340c9717ffSNicholas Piggin if (wc == 0) { 39357058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(1); 3936fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3937fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3938fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3939b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3940fcf5ef2aSThomas Huth } 3941fcf5ef2aSThomas Huth 39420c9717ffSNicholas Piggin /* 39430c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 39440c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 39450c9717ffSNicholas Piggin * 39460c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 39470c9717ffSNicholas Piggin * no-ops. 39480c9717ffSNicholas Piggin * 39490c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 39500c9717ffSNicholas Piggin * 39510c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 39520c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 39530c9717ffSNicholas Piggin * 39540c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 39550c9717ffSNicholas Piggin * 39560c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 39570c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 39580c9717ffSNicholas Piggin * can be implemented as a no-op. 39590c9717ffSNicholas Piggin * 39600c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 39610c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 39620c9717ffSNicholas Piggin * no-op. 39630c9717ffSNicholas Piggin * 39640c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 39650c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 39660c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 39670c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 39680c9717ffSNicholas Piggin * (if suboptimal). 39690c9717ffSNicholas Piggin */ 39700c9717ffSNicholas Piggin } 39710c9717ffSNicholas Piggin 3972fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3973fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3974fcf5ef2aSThomas Huth { 3975fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 39769f0cf041SMatheus Ferst GEN_PRIV(ctx); 3977fcf5ef2aSThomas Huth #else 3978fcf5ef2aSThomas Huth TCGv_i32 t; 3979fcf5ef2aSThomas Huth 39809f0cf041SMatheus Ferst CHK_HV(ctx); 39817058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_DOZE); 3982fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3983154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3984154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3985fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3986fcf5ef2aSThomas Huth } 3987fcf5ef2aSThomas Huth 3988fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3989fcf5ef2aSThomas Huth { 3990fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 39919f0cf041SMatheus Ferst GEN_PRIV(ctx); 3992fcf5ef2aSThomas Huth #else 3993fcf5ef2aSThomas Huth TCGv_i32 t; 3994fcf5ef2aSThomas Huth 39959f0cf041SMatheus Ferst CHK_HV(ctx); 39967058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_NAP); 3997fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3998154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3999154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4000fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4001fcf5ef2aSThomas Huth } 4002fcf5ef2aSThomas Huth 4003cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4004cdee0e72SNikunj A Dadhania { 400521c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 40069f0cf041SMatheus Ferst GEN_PRIV(ctx); 400721c0d66aSBenjamin Herrenschmidt #else 400821c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 400921c0d66aSBenjamin Herrenschmidt 40109f0cf041SMatheus Ferst CHK_HV(ctx); 40117058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_STOP); 401221c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 401321c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 401421c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 401521c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4016cdee0e72SNikunj A Dadhania } 4017cdee0e72SNikunj A Dadhania 4018fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4019fcf5ef2aSThomas Huth { 4020fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40219f0cf041SMatheus Ferst GEN_PRIV(ctx); 4022fcf5ef2aSThomas Huth #else 4023fcf5ef2aSThomas Huth TCGv_i32 t; 4024fcf5ef2aSThomas Huth 40259f0cf041SMatheus Ferst CHK_HV(ctx); 40267058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_SLEEP); 4027fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4028154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4029154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4030fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4031fcf5ef2aSThomas Huth } 4032fcf5ef2aSThomas Huth 4033fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4034fcf5ef2aSThomas Huth { 4035fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40369f0cf041SMatheus Ferst GEN_PRIV(ctx); 4037fcf5ef2aSThomas Huth #else 4038fcf5ef2aSThomas Huth TCGv_i32 t; 4039fcf5ef2aSThomas Huth 40409f0cf041SMatheus Ferst CHK_HV(ctx); 40417058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_RVWINKLE); 4042fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4043154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4044154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4045fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4046fcf5ef2aSThomas Huth } 4047fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4048fcf5ef2aSThomas Huth 4049fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4050fcf5ef2aSThomas Huth { 4051fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4052efe843d8SDavid Gibson if (ctx->has_cfar) { 4053fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4054efe843d8SDavid Gibson } 4055fcf5ef2aSThomas Huth #endif 4056fcf5ef2aSThomas Huth } 4057fcf5ef2aSThomas Huth 405846d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 405946d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 406046d396bdSDaniel Henrique Barboza { 406146d396bdSDaniel Henrique Barboza /* 406246d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 406346d396bdSDaniel Henrique Barboza * instructions. 406446d396bdSDaniel Henrique Barboza */ 406546d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 406646d396bdSDaniel Henrique Barboza return; 406746d396bdSDaniel Henrique Barboza } 406846d396bdSDaniel Henrique Barboza 406946d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4070eeaaefe9SLeandro Lupori TCGLabel *l; 4071eeaaefe9SLeandro Lupori TCGv t0; 4072eeaaefe9SLeandro Lupori 407346d396bdSDaniel Henrique Barboza /* 407446d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 407546d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 407646d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 407746d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 407846d396bdSDaniel Henrique Barboza */ 4079283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 408046d396bdSDaniel Henrique Barboza 4081eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4082eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4083eeaaefe9SLeandro Lupori l = gen_new_label(); 4084eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4085eeaaefe9SLeandro Lupori 4086eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4087eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4088eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4089eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4090eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4091eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4092eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4093eeaaefe9SLeandro Lupori } 4094eeaaefe9SLeandro Lupori 4095eeaaefe9SLeandro Lupori gen_set_label(l); 4096eeaaefe9SLeandro Lupori } else { 409746d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4098eeaaefe9SLeandro Lupori } 409946d396bdSDaniel Henrique Barboza #else 410046d396bdSDaniel Henrique Barboza /* 410146d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 410246d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 410346d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 410446d396bdSDaniel Henrique Barboza */ 410546d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 410646d396bdSDaniel Henrique Barboza 410746d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 410846d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 410946d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 411046d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 411146d396bdSDaniel Henrique Barboza } 411246d396bdSDaniel Henrique Barboza #else 411346d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 411446d396bdSDaniel Henrique Barboza { 411546d396bdSDaniel Henrique Barboza return; 411646d396bdSDaniel Henrique Barboza } 411746d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 411846d396bdSDaniel Henrique Barboza 4119fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4120fcf5ef2aSThomas Huth { 41216e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4122fcf5ef2aSThomas Huth } 4123fcf5ef2aSThomas Huth 41240e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 41250e3bf489SRoman Kapl { 41269498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 41270e3bf489SRoman Kapl gen_debug_exception(ctx); 41280e3bf489SRoman Kapl } else { 412946d396bdSDaniel Henrique Barboza /* 413046d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 413146d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 413246d396bdSDaniel Henrique Barboza */ 413346d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 413446d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 413546d396bdSDaniel Henrique Barboza } 413646d396bdSDaniel Henrique Barboza 41370e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 41380e3bf489SRoman Kapl } 41390e3bf489SRoman Kapl } 41400e3bf489SRoman Kapl 4141fcf5ef2aSThomas Huth /*** Branch ***/ 4142c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4143fcf5ef2aSThomas Huth { 4144fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4145fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4146fcf5ef2aSThomas Huth } 4147fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 414846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4149fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4150fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 415107ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4152fcf5ef2aSThomas Huth } else { 4153fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 41540e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4155fcf5ef2aSThomas Huth } 4156fcf5ef2aSThomas Huth } 4157fcf5ef2aSThomas Huth 4158fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4159fcf5ef2aSThomas Huth { 4160fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4161fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4162fcf5ef2aSThomas Huth } 4163fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4164fcf5ef2aSThomas Huth } 4165fcf5ef2aSThomas Huth 4166fcf5ef2aSThomas Huth /* b ba bl bla */ 4167fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4168fcf5ef2aSThomas Huth { 4169fcf5ef2aSThomas Huth target_ulong li, target; 4170fcf5ef2aSThomas Huth 4171fcf5ef2aSThomas Huth /* sign extend LI */ 4172fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4173fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4174fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 41752c2bcb1bSRichard Henderson target = ctx->cia + li; 4176fcf5ef2aSThomas Huth } else { 4177fcf5ef2aSThomas Huth target = li; 4178fcf5ef2aSThomas Huth } 4179fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4180b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4181fcf5ef2aSThomas Huth } 41822c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4183fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 41846086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4185fcf5ef2aSThomas Huth } 4186fcf5ef2aSThomas Huth 4187fcf5ef2aSThomas Huth #define BCOND_IM 0 4188fcf5ef2aSThomas Huth #define BCOND_LR 1 4189fcf5ef2aSThomas Huth #define BCOND_CTR 2 4190fcf5ef2aSThomas Huth #define BCOND_TAR 3 4191fcf5ef2aSThomas Huth 4192c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4193fcf5ef2aSThomas Huth { 4194fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4195fcf5ef2aSThomas Huth TCGLabel *l1; 4196fcf5ef2aSThomas Huth TCGv target; 41970e3bf489SRoman Kapl 4198fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 41999723281fSRichard Henderson target = tcg_temp_new(); 4200efe843d8SDavid Gibson if (type == BCOND_CTR) { 4201fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4202efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4203fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4204efe843d8SDavid Gibson } else { 4205fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4206efe843d8SDavid Gibson } 4207fcf5ef2aSThomas Huth } else { 4208f764718dSRichard Henderson target = NULL; 4209fcf5ef2aSThomas Huth } 4210efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4211b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4212efe843d8SDavid Gibson } 4213fcf5ef2aSThomas Huth l1 = gen_new_label(); 4214fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4215fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4216fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4217fa200c95SGreg Kurz 4218fa200c95SGreg Kurz if (type == BCOND_CTR) { 4219fa200c95SGreg Kurz /* 4220fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4221fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4222fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 422315d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 422415d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 422515d68c5eSGreg Kurz * it basically useless and thus never used in real code. 422615d68c5eSGreg Kurz * 422715d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 422815d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 422915d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 423015d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 423115d68c5eSGreg Kurz * doing anything else harmful. 4232fa200c95SGreg Kurz */ 4233d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4234fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4235fcf5ef2aSThomas Huth return; 4236fcf5ef2aSThomas Huth } 4237fa200c95SGreg Kurz 4238fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4239fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4240fa200c95SGreg Kurz } else { 4241fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4242fa200c95SGreg Kurz } 4243fa200c95SGreg Kurz if (bo & 0x2) { 4244fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4245fa200c95SGreg Kurz } else { 4246fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4247fa200c95SGreg Kurz } 4248fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4249fa200c95SGreg Kurz } else { 4250fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4251fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4252fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4253fcf5ef2aSThomas Huth } else { 4254fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4255fcf5ef2aSThomas Huth } 4256fcf5ef2aSThomas Huth if (bo & 0x2) { 4257fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4258fcf5ef2aSThomas Huth } else { 4259fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4260fcf5ef2aSThomas Huth } 4261fa200c95SGreg Kurz } 4262fcf5ef2aSThomas Huth } 4263fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4264fcf5ef2aSThomas Huth /* Test CR */ 4265fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4266fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4267fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4268fcf5ef2aSThomas Huth 4269fcf5ef2aSThomas Huth if (bo & 0x8) { 4270fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4271fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4272fcf5ef2aSThomas Huth } else { 4273fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4274fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4275fcf5ef2aSThomas Huth } 4276fcf5ef2aSThomas Huth } 42772c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4278fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4279fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4280fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42812c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4282fcf5ef2aSThomas Huth } else { 4283fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4284fcf5ef2aSThomas Huth } 4285fcf5ef2aSThomas Huth } else { 4286fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4287fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4288fcf5ef2aSThomas Huth } else { 4289fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4290fcf5ef2aSThomas Huth } 42910e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4292c4a2e3a9SRichard Henderson } 4293fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 42940e3bf489SRoman Kapl /* fallthrough case */ 4295fcf5ef2aSThomas Huth gen_set_label(l1); 4296b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4297fcf5ef2aSThomas Huth } 42986086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4299fcf5ef2aSThomas Huth } 4300fcf5ef2aSThomas Huth 4301fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4302fcf5ef2aSThomas Huth { 4303fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4304fcf5ef2aSThomas Huth } 4305fcf5ef2aSThomas Huth 4306fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4307fcf5ef2aSThomas Huth { 4308fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4309fcf5ef2aSThomas Huth } 4310fcf5ef2aSThomas Huth 4311fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4312fcf5ef2aSThomas Huth { 4313fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4314fcf5ef2aSThomas Huth } 4315fcf5ef2aSThomas Huth 4316fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4317fcf5ef2aSThomas Huth { 4318fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4319fcf5ef2aSThomas Huth } 4320fcf5ef2aSThomas Huth 4321fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4322fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4323fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4324fcf5ef2aSThomas Huth { \ 4325fcf5ef2aSThomas Huth uint8_t bitmask; \ 4326fcf5ef2aSThomas Huth int sh; \ 4327fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4328fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4329fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4330fcf5ef2aSThomas Huth if (sh > 0) \ 4331fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4332fcf5ef2aSThomas Huth else if (sh < 0) \ 4333fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4334fcf5ef2aSThomas Huth else \ 4335fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4336fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4337fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4338fcf5ef2aSThomas Huth if (sh > 0) \ 4339fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4340fcf5ef2aSThomas Huth else if (sh < 0) \ 4341fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4342fcf5ef2aSThomas Huth else \ 4343fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4344fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4345fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4346fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4347fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4348fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4349fcf5ef2aSThomas Huth } 4350fcf5ef2aSThomas Huth 4351fcf5ef2aSThomas Huth /* crand */ 4352fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4353fcf5ef2aSThomas Huth /* crandc */ 4354fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4355fcf5ef2aSThomas Huth /* creqv */ 4356fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4357fcf5ef2aSThomas Huth /* crnand */ 4358fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4359fcf5ef2aSThomas Huth /* crnor */ 4360fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4361fcf5ef2aSThomas Huth /* cror */ 4362fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4363fcf5ef2aSThomas Huth /* crorc */ 4364fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4365fcf5ef2aSThomas Huth /* crxor */ 4366fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4367fcf5ef2aSThomas Huth 4368fcf5ef2aSThomas Huth /* mcrf */ 4369fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4370fcf5ef2aSThomas Huth { 4371fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4372fcf5ef2aSThomas Huth } 4373fcf5ef2aSThomas Huth 4374fcf5ef2aSThomas Huth /*** System linkage ***/ 4375fcf5ef2aSThomas Huth 4376fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4377fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4378fcf5ef2aSThomas Huth { 4379fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 43809f0cf041SMatheus Ferst GEN_PRIV(ctx); 4381fcf5ef2aSThomas Huth #else 4382efe843d8SDavid Gibson /* 4383efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4384fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4385fcf5ef2aSThomas Huth */ 4386d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4387fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4388fcf5ef2aSThomas Huth return; 4389fcf5ef2aSThomas Huth } 4390fcf5ef2aSThomas Huth /* Restore CPU state */ 43919f0cf041SMatheus Ferst CHK_SV(ctx); 4392283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 43932c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4394fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 439559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4396fcf5ef2aSThomas Huth #endif 4397fcf5ef2aSThomas Huth } 4398fcf5ef2aSThomas Huth 4399fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4400fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4401fcf5ef2aSThomas Huth { 4402fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44039f0cf041SMatheus Ferst GEN_PRIV(ctx); 4404fcf5ef2aSThomas Huth #else 4405fcf5ef2aSThomas Huth /* Restore CPU state */ 44069f0cf041SMatheus Ferst CHK_SV(ctx); 4407283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44082c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4409fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 441059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4411fcf5ef2aSThomas Huth #endif 4412fcf5ef2aSThomas Huth } 4413fcf5ef2aSThomas Huth 44143c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44153c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 44163c89b8d6SNicholas Piggin { 44173c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 44189f0cf041SMatheus Ferst GEN_PRIV(ctx); 44193c89b8d6SNicholas Piggin #else 44203c89b8d6SNicholas Piggin /* Restore CPU state */ 44219f0cf041SMatheus Ferst CHK_SV(ctx); 4422283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44232c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 44243c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 442559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 44263c89b8d6SNicholas Piggin #endif 44273c89b8d6SNicholas Piggin } 44283c89b8d6SNicholas Piggin #endif 44293c89b8d6SNicholas Piggin 4430fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4431fcf5ef2aSThomas Huth { 4432fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44339f0cf041SMatheus Ferst GEN_PRIV(ctx); 4434fcf5ef2aSThomas Huth #else 4435fcf5ef2aSThomas Huth /* Restore CPU state */ 44369f0cf041SMatheus Ferst CHK_HV(ctx); 4437fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 443859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4439fcf5ef2aSThomas Huth #endif 4440fcf5ef2aSThomas Huth } 4441fcf5ef2aSThomas Huth #endif 4442fcf5ef2aSThomas Huth 4443fcf5ef2aSThomas Huth /* sc */ 4444fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4445fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4446fcf5ef2aSThomas Huth #else 4447fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 44483c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4449fcf5ef2aSThomas Huth #endif 4450fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4451fcf5ef2aSThomas Huth { 4452fcf5ef2aSThomas Huth uint32_t lev; 4453fcf5ef2aSThomas Huth 4454984eda58SNicholas Piggin /* 4455984eda58SNicholas Piggin * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4456984eda58SNicholas Piggin * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4457984eda58SNicholas Piggin * for Ultravisor which TCG does not support, so just ignore the top 6. 4458984eda58SNicholas Piggin */ 4459984eda58SNicholas Piggin lev = (ctx->opcode >> 5) & 0x1; 4460fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4461fcf5ef2aSThomas Huth } 4462fcf5ef2aSThomas Huth 44633c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 44643c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44653c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 44663c89b8d6SNicholas Piggin { 4467f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 44683c89b8d6SNicholas Piggin 4469f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 44702c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4471f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 44723c89b8d6SNicholas Piggin 44737a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 44743c89b8d6SNicholas Piggin } 44753c89b8d6SNicholas Piggin #endif 44763c89b8d6SNicholas Piggin #endif 44773c89b8d6SNicholas Piggin 4478fcf5ef2aSThomas Huth /*** Trap ***/ 4479fcf5ef2aSThomas Huth 4480fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4481fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4482fcf5ef2aSThomas Huth { 4483fcf5ef2aSThomas Huth /* Trap never */ 4484fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4485fcf5ef2aSThomas Huth return true; 4486fcf5ef2aSThomas Huth } 4487fcf5ef2aSThomas Huth /* Trap always */ 4488fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4489fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4490fcf5ef2aSThomas Huth return true; 4491fcf5ef2aSThomas Huth } 4492fcf5ef2aSThomas Huth return false; 4493fcf5ef2aSThomas Huth } 4494fcf5ef2aSThomas Huth 4495fcf5ef2aSThomas Huth /* tw */ 4496fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4497fcf5ef2aSThomas Huth { 4498fcf5ef2aSThomas Huth TCGv_i32 t0; 4499fcf5ef2aSThomas Huth 4500fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4501fcf5ef2aSThomas Huth return; 4502fcf5ef2aSThomas Huth } 45037058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4504fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4505fcf5ef2aSThomas Huth t0); 4506fcf5ef2aSThomas Huth } 4507fcf5ef2aSThomas Huth 4508fcf5ef2aSThomas Huth /* twi */ 4509fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4510fcf5ef2aSThomas Huth { 4511fcf5ef2aSThomas Huth TCGv t0; 4512fcf5ef2aSThomas Huth TCGv_i32 t1; 4513fcf5ef2aSThomas Huth 4514fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4515fcf5ef2aSThomas Huth return; 4516fcf5ef2aSThomas Huth } 45177058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45187058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4519fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4520fcf5ef2aSThomas Huth } 4521fcf5ef2aSThomas Huth 4522fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4523fcf5ef2aSThomas Huth /* td */ 4524fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4525fcf5ef2aSThomas Huth { 4526fcf5ef2aSThomas Huth TCGv_i32 t0; 4527fcf5ef2aSThomas Huth 4528fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4529fcf5ef2aSThomas Huth return; 4530fcf5ef2aSThomas Huth } 45317058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4532fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4533fcf5ef2aSThomas Huth t0); 4534fcf5ef2aSThomas Huth } 4535fcf5ef2aSThomas Huth 4536fcf5ef2aSThomas Huth /* tdi */ 4537fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4538fcf5ef2aSThomas Huth { 4539fcf5ef2aSThomas Huth TCGv t0; 4540fcf5ef2aSThomas Huth TCGv_i32 t1; 4541fcf5ef2aSThomas Huth 4542fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4543fcf5ef2aSThomas Huth return; 4544fcf5ef2aSThomas Huth } 45457058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45467058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4547fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4548fcf5ef2aSThomas Huth } 4549fcf5ef2aSThomas Huth #endif 4550fcf5ef2aSThomas Huth 4551fcf5ef2aSThomas Huth /*** Processor control ***/ 4552fcf5ef2aSThomas Huth 4553fcf5ef2aSThomas Huth /* mcrxr */ 4554fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4555fcf5ef2aSThomas Huth { 4556fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4557fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4558fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4559fcf5ef2aSThomas Huth 4560fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4561fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4562fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4563fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4564fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4565fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4566fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4567fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4568fcf5ef2aSThomas Huth 4569fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4570fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4571fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4572fcf5ef2aSThomas Huth } 4573fcf5ef2aSThomas Huth 4574b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4575b63d0434SNikunj A Dadhania /* mcrxrx */ 4576b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4577b63d0434SNikunj A Dadhania { 4578b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4579b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4580b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4581b63d0434SNikunj A Dadhania 4582b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4583b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4584b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4585b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4586b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4587b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4588b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4589b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4590b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4591b63d0434SNikunj A Dadhania } 4592b63d0434SNikunj A Dadhania #endif 4593b63d0434SNikunj A Dadhania 4594fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4595fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4596fcf5ef2aSThomas Huth { 4597fcf5ef2aSThomas Huth uint32_t crm, crn; 4598fcf5ef2aSThomas Huth 4599fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4600fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4601fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4602fcf5ef2aSThomas Huth crn = ctz32(crm); 4603fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4604fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4605fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4606fcf5ef2aSThomas Huth } 4607fcf5ef2aSThomas Huth } else { 4608fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4609fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4610fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4611fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4612fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4613fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4614fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4615fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4616fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4617fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4618fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4619fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4620fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4621fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4622fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4623fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4624fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4625fcf5ef2aSThomas Huth } 4626fcf5ef2aSThomas Huth } 4627fcf5ef2aSThomas Huth 4628fcf5ef2aSThomas Huth /* mfmsr */ 4629fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4630fcf5ef2aSThomas Huth { 46319f0cf041SMatheus Ferst CHK_SV(ctx); 4632fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4633fcf5ef2aSThomas Huth } 4634fcf5ef2aSThomas Huth 4635fcf5ef2aSThomas Huth /* mfspr */ 4636fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4637fcf5ef2aSThomas Huth { 4638fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4639fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4640fcf5ef2aSThomas Huth 4641fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4642fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4643fcf5ef2aSThomas Huth #else 4644fcf5ef2aSThomas Huth if (ctx->pr) { 4645fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4646fcf5ef2aSThomas Huth } else if (ctx->hv) { 4647fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4648fcf5ef2aSThomas Huth } else { 4649fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4650fcf5ef2aSThomas Huth } 4651fcf5ef2aSThomas Huth #endif 4652fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4653fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4654fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4655fcf5ef2aSThomas Huth } else { 4656fcf5ef2aSThomas Huth /* Privilege exception */ 4657efe843d8SDavid Gibson /* 4658efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4659fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4660fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4661fcf5ef2aSThomas Huth */ 4662fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 466331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 466431085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 46652c2bcb1bSRichard Henderson ctx->cia); 4666fcf5ef2aSThomas Huth } 4667fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4668fcf5ef2aSThomas Huth } 4669fcf5ef2aSThomas Huth } else { 4670fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4671fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4672fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4673fcf5ef2aSThomas Huth /* This is a nop */ 4674fcf5ef2aSThomas Huth return; 4675fcf5ef2aSThomas Huth } 4676fcf5ef2aSThomas Huth /* Not defined */ 467731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 467831085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 46792c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4680fcf5ef2aSThomas Huth 4681efe843d8SDavid Gibson /* 4682efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4683efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4684fcf5ef2aSThomas Huth */ 4685fcf5ef2aSThomas Huth if (sprn & 0x10) { 4686fcf5ef2aSThomas Huth if (ctx->pr) { 46871315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4688fcf5ef2aSThomas Huth } 4689fcf5ef2aSThomas Huth } else { 4690fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 46911315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4692fcf5ef2aSThomas Huth } 4693fcf5ef2aSThomas Huth } 4694fcf5ef2aSThomas Huth } 4695fcf5ef2aSThomas Huth } 4696fcf5ef2aSThomas Huth 4697fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4698fcf5ef2aSThomas Huth { 4699fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4700fcf5ef2aSThomas Huth } 4701fcf5ef2aSThomas Huth 4702fcf5ef2aSThomas Huth /* mftb */ 4703fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4704fcf5ef2aSThomas Huth { 4705fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4706fcf5ef2aSThomas Huth } 4707fcf5ef2aSThomas Huth 4708fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4709fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4710fcf5ef2aSThomas Huth { 4711fcf5ef2aSThomas Huth uint32_t crm, crn; 4712fcf5ef2aSThomas Huth 4713fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4714fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4715fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4716fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4717fcf5ef2aSThomas Huth crn = ctz32(crm); 4718fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4719fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4720fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4721fcf5ef2aSThomas Huth } 4722fcf5ef2aSThomas Huth } else { 4723fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4724fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4725fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4726fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4727fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4728fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4729fcf5ef2aSThomas Huth } 4730fcf5ef2aSThomas Huth } 4731fcf5ef2aSThomas Huth } 4732fcf5ef2aSThomas Huth } 4733fcf5ef2aSThomas Huth 4734fcf5ef2aSThomas Huth /* mtmsr */ 4735fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4736fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4737fcf5ef2aSThomas Huth { 4738caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4739caf590ddSNicholas Piggin gen_invalid(ctx); 4740caf590ddSNicholas Piggin return; 4741caf590ddSNicholas Piggin } 4742caf590ddSNicholas Piggin 47439f0cf041SMatheus Ferst CHK_SV(ctx); 4744fcf5ef2aSThomas Huth 4745fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 47466fa5726bSMatheus Ferst TCGv t0, t1; 47476fa5726bSMatheus Ferst target_ulong mask; 47486fa5726bSMatheus Ferst 47496fa5726bSMatheus Ferst t0 = tcg_temp_new(); 47506fa5726bSMatheus Ferst t1 = tcg_temp_new(); 47516fa5726bSMatheus Ferst 4752283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 47536fa5726bSMatheus Ferst 4754fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 47555ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 47566fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4757fcf5ef2aSThomas Huth } else { 47586fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 47596fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 47606fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4761efe843d8SDavid Gibson /* 4762efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4763efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4764efe843d8SDavid Gibson * ppc_store_msr 4765fcf5ef2aSThomas Huth */ 4766b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4767fcf5ef2aSThomas Huth } 47686fa5726bSMatheus Ferst 47696fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 47706fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 47716fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 47726fa5726bSMatheus Ferst 47736fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 47746fa5726bSMatheus Ferst 47755ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4776d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4777fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4778fcf5ef2aSThomas Huth } 4779fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4780fcf5ef2aSThomas Huth 4781fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4782fcf5ef2aSThomas Huth { 47839f0cf041SMatheus Ferst CHK_SV(ctx); 4784fcf5ef2aSThomas Huth 4785fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 47866fa5726bSMatheus Ferst TCGv t0, t1; 47876fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 47886fa5726bSMatheus Ferst 47896fa5726bSMatheus Ferst t0 = tcg_temp_new(); 47906fa5726bSMatheus Ferst t1 = tcg_temp_new(); 47916fa5726bSMatheus Ferst 4792283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 4793fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 47945ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 47956fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4796fcf5ef2aSThomas Huth } else { 47976fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 47986fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4799fcf5ef2aSThomas Huth 4800efe843d8SDavid Gibson /* 4801efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4802efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4803efe843d8SDavid Gibson * ppc_store_msr 4804fcf5ef2aSThomas Huth */ 4805b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4806fcf5ef2aSThomas Huth } 48076fa5726bSMatheus Ferst 48086fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48096fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48106fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48116fa5726bSMatheus Ferst 48126fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48136fa5726bSMatheus Ferst 48145ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4815d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4816fcf5ef2aSThomas Huth #endif 4817fcf5ef2aSThomas Huth } 4818fcf5ef2aSThomas Huth 4819fcf5ef2aSThomas Huth /* mtspr */ 4820fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4821fcf5ef2aSThomas Huth { 4822fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4823fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4824fcf5ef2aSThomas Huth 4825fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4826fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4827fcf5ef2aSThomas Huth #else 4828fcf5ef2aSThomas Huth if (ctx->pr) { 4829fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4830fcf5ef2aSThomas Huth } else if (ctx->hv) { 4831fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4832fcf5ef2aSThomas Huth } else { 4833fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4834fcf5ef2aSThomas Huth } 4835fcf5ef2aSThomas Huth #endif 4836fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4837fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4838fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4839fcf5ef2aSThomas Huth } else { 4840fcf5ef2aSThomas Huth /* Privilege exception */ 484131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 484231085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48432c2bcb1bSRichard Henderson ctx->cia); 4844fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4845fcf5ef2aSThomas Huth } 4846fcf5ef2aSThomas Huth } else { 4847fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4848fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4849fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4850fcf5ef2aSThomas Huth /* This is a nop */ 4851fcf5ef2aSThomas Huth return; 4852fcf5ef2aSThomas Huth } 4853fcf5ef2aSThomas Huth 4854fcf5ef2aSThomas Huth /* Not defined */ 485531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 485631085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 48572c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4858fcf5ef2aSThomas Huth 4859fcf5ef2aSThomas Huth 4860efe843d8SDavid Gibson /* 4861efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4862efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4863fcf5ef2aSThomas Huth */ 4864fcf5ef2aSThomas Huth if (sprn & 0x10) { 4865fcf5ef2aSThomas Huth if (ctx->pr) { 48661315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4867fcf5ef2aSThomas Huth } 4868fcf5ef2aSThomas Huth } else { 4869fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 48701315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4871fcf5ef2aSThomas Huth } 4872fcf5ef2aSThomas Huth } 4873fcf5ef2aSThomas Huth } 4874fcf5ef2aSThomas Huth } 4875fcf5ef2aSThomas Huth 4876fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4877fcf5ef2aSThomas Huth /* setb */ 4878fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4879fcf5ef2aSThomas Huth { 4880fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 48816f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 48826f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 4883fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4884fcf5ef2aSThomas Huth 4885fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4886fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4887fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4888fcf5ef2aSThomas Huth } 4889fcf5ef2aSThomas Huth #endif 4890fcf5ef2aSThomas Huth 4891fcf5ef2aSThomas Huth /*** Cache management ***/ 4892fcf5ef2aSThomas Huth 4893fcf5ef2aSThomas Huth /* dcbf */ 4894fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4895fcf5ef2aSThomas Huth { 4896fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4897fcf5ef2aSThomas Huth TCGv t0; 4898fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4899fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4900fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4901fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4902fcf5ef2aSThomas Huth } 4903fcf5ef2aSThomas Huth 490450728199SRoman Kapl /* dcbfep (external PID dcbf) */ 490550728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 490650728199SRoman Kapl { 490750728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 490850728199SRoman Kapl TCGv t0; 49099f0cf041SMatheus Ferst CHK_SV(ctx); 491050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 491150728199SRoman Kapl t0 = tcg_temp_new(); 491250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 491350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 491450728199SRoman Kapl } 491550728199SRoman Kapl 4916fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4917fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4918fcf5ef2aSThomas Huth { 4919fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 49209f0cf041SMatheus Ferst GEN_PRIV(ctx); 4921fcf5ef2aSThomas Huth #else 4922fcf5ef2aSThomas Huth TCGv EA, val; 4923fcf5ef2aSThomas Huth 49249f0cf041SMatheus Ferst CHK_SV(ctx); 4925fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4926fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4927fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4928fcf5ef2aSThomas Huth val = tcg_temp_new(); 4929fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4930fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4931fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4932fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4933fcf5ef2aSThomas Huth } 4934fcf5ef2aSThomas Huth 4935fcf5ef2aSThomas Huth /* dcdst */ 4936fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4937fcf5ef2aSThomas Huth { 4938fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4939fcf5ef2aSThomas Huth TCGv t0; 4940fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4941fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4942fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4943fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4944fcf5ef2aSThomas Huth } 4945fcf5ef2aSThomas Huth 494650728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 494750728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 494850728199SRoman Kapl { 494950728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 495050728199SRoman Kapl TCGv t0; 495150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 495250728199SRoman Kapl t0 = tcg_temp_new(); 495350728199SRoman Kapl gen_addr_reg_index(ctx, t0); 495450728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 495550728199SRoman Kapl } 495650728199SRoman Kapl 4957fcf5ef2aSThomas Huth /* dcbt */ 4958fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4959fcf5ef2aSThomas Huth { 4960efe843d8SDavid Gibson /* 4961efe843d8SDavid Gibson * interpreted as no-op 4962efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4963efe843d8SDavid Gibson * does not generate any exception 4964fcf5ef2aSThomas Huth */ 4965fcf5ef2aSThomas Huth } 4966fcf5ef2aSThomas Huth 496750728199SRoman Kapl /* dcbtep */ 496850728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 496950728199SRoman Kapl { 4970efe843d8SDavid Gibson /* 4971efe843d8SDavid Gibson * interpreted as no-op 4972efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4973efe843d8SDavid Gibson * does not generate any exception 497450728199SRoman Kapl */ 497550728199SRoman Kapl } 497650728199SRoman Kapl 4977fcf5ef2aSThomas Huth /* dcbtst */ 4978fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4979fcf5ef2aSThomas Huth { 4980efe843d8SDavid Gibson /* 4981efe843d8SDavid Gibson * interpreted as no-op 4982efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4983efe843d8SDavid Gibson * does not generate any exception 4984fcf5ef2aSThomas Huth */ 4985fcf5ef2aSThomas Huth } 4986fcf5ef2aSThomas Huth 498750728199SRoman Kapl /* dcbtstep */ 498850728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 498950728199SRoman Kapl { 4990efe843d8SDavid Gibson /* 4991efe843d8SDavid Gibson * interpreted as no-op 4992efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4993efe843d8SDavid Gibson * does not generate any exception 499450728199SRoman Kapl */ 499550728199SRoman Kapl } 499650728199SRoman Kapl 4997fcf5ef2aSThomas Huth /* dcbtls */ 4998fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4999fcf5ef2aSThomas Huth { 5000fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5001fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5002fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5003fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5004fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5005fcf5ef2aSThomas Huth } 5006fcf5ef2aSThomas Huth 5007e64645baSBernhard Beschow /* dcblc */ 5008e64645baSBernhard Beschow static void gen_dcblc(DisasContext *ctx) 5009e64645baSBernhard Beschow { 5010e64645baSBernhard Beschow /* 5011e64645baSBernhard Beschow * interpreted as no-op 5012e64645baSBernhard Beschow */ 5013e64645baSBernhard Beschow } 5014e64645baSBernhard Beschow 5015fcf5ef2aSThomas Huth /* dcbz */ 5016fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5017fcf5ef2aSThomas Huth { 5018fcf5ef2aSThomas Huth TCGv tcgv_addr; 5019fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5020fcf5ef2aSThomas Huth 5021fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5022fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 50237058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5024fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5025fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5026fcf5ef2aSThomas Huth } 5027fcf5ef2aSThomas Huth 502850728199SRoman Kapl /* dcbzep */ 502950728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 503050728199SRoman Kapl { 503150728199SRoman Kapl TCGv tcgv_addr; 503250728199SRoman Kapl TCGv_i32 tcgv_op; 503350728199SRoman Kapl 503450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 503550728199SRoman Kapl tcgv_addr = tcg_temp_new(); 50367058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 503750728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 503850728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 503950728199SRoman Kapl } 504050728199SRoman Kapl 5041fcf5ef2aSThomas Huth /* dst / dstt */ 5042fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5043fcf5ef2aSThomas Huth { 5044fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5045fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5046fcf5ef2aSThomas Huth } else { 5047fcf5ef2aSThomas Huth /* interpreted as no-op */ 5048fcf5ef2aSThomas Huth } 5049fcf5ef2aSThomas Huth } 5050fcf5ef2aSThomas Huth 5051fcf5ef2aSThomas Huth /* dstst /dststt */ 5052fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5053fcf5ef2aSThomas Huth { 5054fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5055fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5056fcf5ef2aSThomas Huth } else { 5057fcf5ef2aSThomas Huth /* interpreted as no-op */ 5058fcf5ef2aSThomas Huth } 5059fcf5ef2aSThomas Huth 5060fcf5ef2aSThomas Huth } 5061fcf5ef2aSThomas Huth 5062fcf5ef2aSThomas Huth /* dss / dssall */ 5063fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5064fcf5ef2aSThomas Huth { 5065fcf5ef2aSThomas Huth /* interpreted as no-op */ 5066fcf5ef2aSThomas Huth } 5067fcf5ef2aSThomas Huth 5068fcf5ef2aSThomas Huth /* icbi */ 5069fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5070fcf5ef2aSThomas Huth { 5071fcf5ef2aSThomas Huth TCGv t0; 5072fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5073fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5074fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5075fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5076fcf5ef2aSThomas Huth } 5077fcf5ef2aSThomas Huth 507850728199SRoman Kapl /* icbiep */ 507950728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 508050728199SRoman Kapl { 508150728199SRoman Kapl TCGv t0; 508250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 508350728199SRoman Kapl t0 = tcg_temp_new(); 508450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 508550728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 508650728199SRoman Kapl } 508750728199SRoman Kapl 5088fcf5ef2aSThomas Huth /* Optional: */ 5089fcf5ef2aSThomas Huth /* dcba */ 5090fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5091fcf5ef2aSThomas Huth { 5092efe843d8SDavid Gibson /* 5093efe843d8SDavid Gibson * interpreted as no-op 5094efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5095fcf5ef2aSThomas Huth * but does not generate any exception 5096fcf5ef2aSThomas Huth */ 5097fcf5ef2aSThomas Huth } 5098fcf5ef2aSThomas Huth 5099fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5100fcf5ef2aSThomas Huth /* Supervisor only: */ 5101fcf5ef2aSThomas Huth 5102fcf5ef2aSThomas Huth /* mfsr */ 5103fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5104fcf5ef2aSThomas Huth { 5105fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51069f0cf041SMatheus Ferst GEN_PRIV(ctx); 5107fcf5ef2aSThomas Huth #else 5108fcf5ef2aSThomas Huth TCGv t0; 5109fcf5ef2aSThomas Huth 51109f0cf041SMatheus Ferst CHK_SV(ctx); 51117058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5112fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5113fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5114fcf5ef2aSThomas Huth } 5115fcf5ef2aSThomas Huth 5116fcf5ef2aSThomas Huth /* mfsrin */ 5117fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5118fcf5ef2aSThomas Huth { 5119fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51209f0cf041SMatheus Ferst GEN_PRIV(ctx); 5121fcf5ef2aSThomas Huth #else 5122fcf5ef2aSThomas Huth TCGv t0; 5123fcf5ef2aSThomas Huth 51249f0cf041SMatheus Ferst CHK_SV(ctx); 5125fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5126e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5127fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5128fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5129fcf5ef2aSThomas Huth } 5130fcf5ef2aSThomas Huth 5131fcf5ef2aSThomas Huth /* mtsr */ 5132fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5133fcf5ef2aSThomas Huth { 5134fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51359f0cf041SMatheus Ferst GEN_PRIV(ctx); 5136fcf5ef2aSThomas Huth #else 5137fcf5ef2aSThomas Huth TCGv t0; 5138fcf5ef2aSThomas Huth 51399f0cf041SMatheus Ferst CHK_SV(ctx); 51407058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5141fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5142fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5143fcf5ef2aSThomas Huth } 5144fcf5ef2aSThomas Huth 5145fcf5ef2aSThomas Huth /* mtsrin */ 5146fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5147fcf5ef2aSThomas Huth { 5148fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51499f0cf041SMatheus Ferst GEN_PRIV(ctx); 5150fcf5ef2aSThomas Huth #else 5151fcf5ef2aSThomas Huth TCGv t0; 51529f0cf041SMatheus Ferst CHK_SV(ctx); 5153fcf5ef2aSThomas Huth 5154fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5155e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5156fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5157fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5158fcf5ef2aSThomas Huth } 5159fcf5ef2aSThomas Huth 5160fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5161fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5162fcf5ef2aSThomas Huth 5163fcf5ef2aSThomas Huth /* mfsr */ 5164fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5165fcf5ef2aSThomas Huth { 5166fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51679f0cf041SMatheus Ferst GEN_PRIV(ctx); 5168fcf5ef2aSThomas Huth #else 5169fcf5ef2aSThomas Huth TCGv t0; 5170fcf5ef2aSThomas Huth 51719f0cf041SMatheus Ferst CHK_SV(ctx); 51727058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5173fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5174fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5175fcf5ef2aSThomas Huth } 5176fcf5ef2aSThomas Huth 5177fcf5ef2aSThomas Huth /* mfsrin */ 5178fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5179fcf5ef2aSThomas Huth { 5180fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51819f0cf041SMatheus Ferst GEN_PRIV(ctx); 5182fcf5ef2aSThomas Huth #else 5183fcf5ef2aSThomas Huth TCGv t0; 5184fcf5ef2aSThomas Huth 51859f0cf041SMatheus Ferst CHK_SV(ctx); 5186fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5187e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5188fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5189fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5190fcf5ef2aSThomas Huth } 5191fcf5ef2aSThomas Huth 5192fcf5ef2aSThomas Huth /* mtsr */ 5193fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5194fcf5ef2aSThomas Huth { 5195fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51969f0cf041SMatheus Ferst GEN_PRIV(ctx); 5197fcf5ef2aSThomas Huth #else 5198fcf5ef2aSThomas Huth TCGv t0; 5199fcf5ef2aSThomas Huth 52009f0cf041SMatheus Ferst CHK_SV(ctx); 52017058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5202fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5203fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5204fcf5ef2aSThomas Huth } 5205fcf5ef2aSThomas Huth 5206fcf5ef2aSThomas Huth /* mtsrin */ 5207fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5208fcf5ef2aSThomas Huth { 5209fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52109f0cf041SMatheus Ferst GEN_PRIV(ctx); 5211fcf5ef2aSThomas Huth #else 5212fcf5ef2aSThomas Huth TCGv t0; 5213fcf5ef2aSThomas Huth 52149f0cf041SMatheus Ferst CHK_SV(ctx); 5215fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5216e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5217fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5218fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5219fcf5ef2aSThomas Huth } 5220fcf5ef2aSThomas Huth 5221fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5222fcf5ef2aSThomas Huth 5223fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5224fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5225fcf5ef2aSThomas Huth 5226fcf5ef2aSThomas Huth /* tlbia */ 5227fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5228fcf5ef2aSThomas Huth { 5229fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52309f0cf041SMatheus Ferst GEN_PRIV(ctx); 5231fcf5ef2aSThomas Huth #else 52329f0cf041SMatheus Ferst CHK_HV(ctx); 5233fcf5ef2aSThomas Huth 5234fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5235fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5236fcf5ef2aSThomas Huth } 5237fcf5ef2aSThomas Huth 5238fcf5ef2aSThomas Huth /* tlbsync */ 5239fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5240fcf5ef2aSThomas Huth { 5241fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52429f0cf041SMatheus Ferst GEN_PRIV(ctx); 5243fcf5ef2aSThomas Huth #else 524491c60f12SCédric Le Goater 524591c60f12SCédric Le Goater if (ctx->gtse) { 52469f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 524791c60f12SCédric Le Goater } else { 52489f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 524991c60f12SCédric Le Goater } 5250fcf5ef2aSThomas Huth 5251fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5252fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5253fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5254fcf5ef2aSThomas Huth } 5255fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5256fcf5ef2aSThomas Huth } 5257fcf5ef2aSThomas Huth 5258fcf5ef2aSThomas Huth /*** External control ***/ 5259fcf5ef2aSThomas Huth /* Optional: */ 5260fcf5ef2aSThomas Huth 5261fcf5ef2aSThomas Huth /* eciwx */ 5262fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5263fcf5ef2aSThomas Huth { 5264fcf5ef2aSThomas Huth TCGv t0; 5265fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5266fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5267fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5268fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5269c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5270c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5271fcf5ef2aSThomas Huth } 5272fcf5ef2aSThomas Huth 5273fcf5ef2aSThomas Huth /* ecowx */ 5274fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5275fcf5ef2aSThomas Huth { 5276fcf5ef2aSThomas Huth TCGv t0; 5277fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5278fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5279fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5280fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5281c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5282c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5283fcf5ef2aSThomas Huth } 5284fcf5ef2aSThomas Huth 5285fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5286fcf5ef2aSThomas Huth 5287fcf5ef2aSThomas Huth /* tlbld */ 5288fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5289fcf5ef2aSThomas Huth { 5290fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52919f0cf041SMatheus Ferst GEN_PRIV(ctx); 5292fcf5ef2aSThomas Huth #else 52939f0cf041SMatheus Ferst CHK_SV(ctx); 5294fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5295fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5296fcf5ef2aSThomas Huth } 5297fcf5ef2aSThomas Huth 5298fcf5ef2aSThomas Huth /* tlbli */ 5299fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5300fcf5ef2aSThomas Huth { 5301fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53029f0cf041SMatheus Ferst GEN_PRIV(ctx); 5303fcf5ef2aSThomas Huth #else 53049f0cf041SMatheus Ferst CHK_SV(ctx); 5305fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5306fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5307fcf5ef2aSThomas Huth } 5308fcf5ef2aSThomas Huth 5309fcf5ef2aSThomas Huth /* BookE specific instructions */ 5310fcf5ef2aSThomas Huth 5311fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5312fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5313fcf5ef2aSThomas Huth { 5314fcf5ef2aSThomas Huth /* XXX: TODO */ 5315fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5316fcf5ef2aSThomas Huth } 5317fcf5ef2aSThomas Huth 5318fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5319fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5320fcf5ef2aSThomas Huth { 5321fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53229f0cf041SMatheus Ferst GEN_PRIV(ctx); 5323fcf5ef2aSThomas Huth #else 5324fcf5ef2aSThomas Huth TCGv t0; 5325fcf5ef2aSThomas Huth 53269f0cf041SMatheus Ferst CHK_SV(ctx); 5327fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5328fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5329fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5330fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5331fcf5ef2aSThomas Huth } 5332fcf5ef2aSThomas Huth 5333fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5334fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5335fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5336fcf5ef2aSThomas Huth { 5337fcf5ef2aSThomas Huth TCGv t0, t1; 5338fcf5ef2aSThomas Huth 53399723281fSRichard Henderson t0 = tcg_temp_new(); 53409723281fSRichard Henderson t1 = tcg_temp_new(); 5341fcf5ef2aSThomas Huth 5342fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5343fcf5ef2aSThomas Huth case 0x05: 5344fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5345fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5346fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5347fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5348fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5349fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5350fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5351fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5352fcf5ef2aSThomas Huth break; 5353fcf5ef2aSThomas Huth case 0x04: 5354fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5355fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5356fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5357fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5358fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5359fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5360fcf5ef2aSThomas Huth break; 5361fcf5ef2aSThomas Huth case 0x01: 5362fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5363fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5364fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5365fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5366fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5367fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5368fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5369fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5370fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5371fcf5ef2aSThomas Huth break; 5372fcf5ef2aSThomas Huth case 0x00: 5373fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5374fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5375fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5376fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5377fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5378fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5379fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5380fcf5ef2aSThomas Huth break; 5381fcf5ef2aSThomas Huth case 0x0D: 5382fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5383fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5384fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5385fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5386fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5387fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5388fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5389fcf5ef2aSThomas Huth break; 5390fcf5ef2aSThomas Huth case 0x0C: 5391fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5392fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5393fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5394fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5395fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5396fcf5ef2aSThomas Huth break; 5397fcf5ef2aSThomas Huth } 5398fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5399fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5400fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5401fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5402fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5403fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5404fcf5ef2aSThomas Huth } else { 5405fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5406fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5407fcf5ef2aSThomas Huth } 5408fcf5ef2aSThomas Huth 5409fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5410fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5411fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5412fcf5ef2aSThomas Huth 5413fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5414fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5415fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5416fcf5ef2aSThomas Huth } 5417fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5418fcf5ef2aSThomas Huth /* Signed */ 5419fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5420fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5421fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5422fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5423fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5424fcf5ef2aSThomas Huth /* Saturate */ 5425fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5426fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5427fcf5ef2aSThomas Huth } 5428fcf5ef2aSThomas Huth } else { 5429fcf5ef2aSThomas Huth /* Unsigned */ 5430fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5431fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5432fcf5ef2aSThomas Huth /* Saturate */ 5433fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5434fcf5ef2aSThomas Huth } 5435fcf5ef2aSThomas Huth } 5436fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5437fcf5ef2aSThomas Huth /* Check overflow */ 5438fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5439fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5440fcf5ef2aSThomas Huth } 5441fcf5ef2aSThomas Huth gen_set_label(l1); 5442fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5443fcf5ef2aSThomas Huth } 5444fcf5ef2aSThomas Huth } else { 5445fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5446fcf5ef2aSThomas Huth } 5447fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5448fcf5ef2aSThomas Huth /* Update Rc0 */ 5449fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5450fcf5ef2aSThomas Huth } 5451fcf5ef2aSThomas Huth } 5452fcf5ef2aSThomas Huth 5453fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5454fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5455fcf5ef2aSThomas Huth { \ 5456fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5457fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5458fcf5ef2aSThomas Huth } 5459fcf5ef2aSThomas Huth 5460fcf5ef2aSThomas Huth /* macchw - macchw. */ 5461fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5462fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5463fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5464fcf5ef2aSThomas Huth /* macchws - macchws. */ 5465fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5466fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5467fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5468fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5469fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5470fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5471fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5472fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5473fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5474fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5475fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5476fcf5ef2aSThomas Huth /* machhw - machhw. */ 5477fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5478fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5479fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5480fcf5ef2aSThomas Huth /* machhws - machhws. */ 5481fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5482fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5483fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5484fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5485fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5486fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5487fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5488fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5489fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5490fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5491fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5492fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5493fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5494fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5495fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5496fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5497fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5498fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5499fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5500fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5501fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5502fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5503fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5504fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5505fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5506fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5507fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5508fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5509fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5510fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5511fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5512fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5513fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5514fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5515fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5516fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5517fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5518fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5519fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5520fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5521fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5522fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5523fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5524fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5525fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5526fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5527fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5528fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5529fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5530fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5531fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5532fcf5ef2aSThomas Huth 5533fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5534fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5535fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5536fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5537fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5538fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5539fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5540fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5541fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5542fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5543fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5544fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5545fcf5ef2aSThomas Huth 5546fcf5ef2aSThomas Huth /* mfdcr */ 5547fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5548fcf5ef2aSThomas Huth { 5549fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55509f0cf041SMatheus Ferst GEN_PRIV(ctx); 5551fcf5ef2aSThomas Huth #else 5552fcf5ef2aSThomas Huth TCGv dcrn; 5553fcf5ef2aSThomas Huth 55549f0cf041SMatheus Ferst CHK_SV(ctx); 55557058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5556fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5557fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5558fcf5ef2aSThomas Huth } 5559fcf5ef2aSThomas Huth 5560fcf5ef2aSThomas Huth /* mtdcr */ 5561fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5562fcf5ef2aSThomas Huth { 5563fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5565fcf5ef2aSThomas Huth #else 5566fcf5ef2aSThomas Huth TCGv dcrn; 5567fcf5ef2aSThomas Huth 55689f0cf041SMatheus Ferst CHK_SV(ctx); 55697058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5570fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5571fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5572fcf5ef2aSThomas Huth } 5573fcf5ef2aSThomas Huth 5574fcf5ef2aSThomas Huth /* mfdcrx */ 5575fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5576fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5577fcf5ef2aSThomas Huth { 5578fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55799f0cf041SMatheus Ferst GEN_PRIV(ctx); 5580fcf5ef2aSThomas Huth #else 55819f0cf041SMatheus Ferst CHK_SV(ctx); 5582fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5583fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5584fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5585fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5586fcf5ef2aSThomas Huth } 5587fcf5ef2aSThomas Huth 5588fcf5ef2aSThomas Huth /* mtdcrx */ 5589fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5590fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5591fcf5ef2aSThomas Huth { 5592fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55939f0cf041SMatheus Ferst GEN_PRIV(ctx); 5594fcf5ef2aSThomas Huth #else 55959f0cf041SMatheus Ferst CHK_SV(ctx); 5596fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5597fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5598fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5599fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5600fcf5ef2aSThomas Huth } 5601fcf5ef2aSThomas Huth 5602fcf5ef2aSThomas Huth /* dccci */ 5603fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5604fcf5ef2aSThomas Huth { 56059f0cf041SMatheus Ferst CHK_SV(ctx); 5606fcf5ef2aSThomas Huth /* interpreted as no-op */ 5607fcf5ef2aSThomas Huth } 5608fcf5ef2aSThomas Huth 5609fcf5ef2aSThomas Huth /* dcread */ 5610fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5611fcf5ef2aSThomas Huth { 5612fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56139f0cf041SMatheus Ferst GEN_PRIV(ctx); 5614fcf5ef2aSThomas Huth #else 5615fcf5ef2aSThomas Huth TCGv EA, val; 5616fcf5ef2aSThomas Huth 56179f0cf041SMatheus Ferst CHK_SV(ctx); 5618fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5619fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5620fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5621fcf5ef2aSThomas Huth val = tcg_temp_new(); 5622fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5623fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5624fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5625fcf5ef2aSThomas Huth } 5626fcf5ef2aSThomas Huth 5627fcf5ef2aSThomas Huth /* icbt */ 5628fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5629fcf5ef2aSThomas Huth { 5630efe843d8SDavid Gibson /* 5631efe843d8SDavid Gibson * interpreted as no-op 5632efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5633efe843d8SDavid Gibson * does not generate any exception 5634fcf5ef2aSThomas Huth */ 5635fcf5ef2aSThomas Huth } 5636fcf5ef2aSThomas Huth 5637fcf5ef2aSThomas Huth /* iccci */ 5638fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5639fcf5ef2aSThomas Huth { 56409f0cf041SMatheus Ferst CHK_SV(ctx); 5641fcf5ef2aSThomas Huth /* interpreted as no-op */ 5642fcf5ef2aSThomas Huth } 5643fcf5ef2aSThomas Huth 5644fcf5ef2aSThomas Huth /* icread */ 5645fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5646fcf5ef2aSThomas Huth { 56479f0cf041SMatheus Ferst CHK_SV(ctx); 5648fcf5ef2aSThomas Huth /* interpreted as no-op */ 5649fcf5ef2aSThomas Huth } 5650fcf5ef2aSThomas Huth 5651fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5652fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5653fcf5ef2aSThomas Huth { 5654fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56559f0cf041SMatheus Ferst GEN_PRIV(ctx); 5656fcf5ef2aSThomas Huth #else 56579f0cf041SMatheus Ferst CHK_SV(ctx); 5658fcf5ef2aSThomas Huth /* Restore CPU state */ 5659fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 566059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5661fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5662fcf5ef2aSThomas Huth } 5663fcf5ef2aSThomas Huth 5664fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5665fcf5ef2aSThomas Huth { 5666fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56679f0cf041SMatheus Ferst GEN_PRIV(ctx); 5668fcf5ef2aSThomas Huth #else 56699f0cf041SMatheus Ferst CHK_SV(ctx); 5670fcf5ef2aSThomas Huth /* Restore CPU state */ 5671fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 567259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5673fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5674fcf5ef2aSThomas Huth } 5675fcf5ef2aSThomas Huth 5676fcf5ef2aSThomas Huth /* BookE specific */ 5677fcf5ef2aSThomas Huth 5678fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5679fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5680fcf5ef2aSThomas Huth { 5681fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56829f0cf041SMatheus Ferst GEN_PRIV(ctx); 5683fcf5ef2aSThomas Huth #else 56849f0cf041SMatheus Ferst CHK_SV(ctx); 5685fcf5ef2aSThomas Huth /* Restore CPU state */ 5686fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 568759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5688fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5689fcf5ef2aSThomas Huth } 5690fcf5ef2aSThomas Huth 5691fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5692fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5693fcf5ef2aSThomas Huth { 5694fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56959f0cf041SMatheus Ferst GEN_PRIV(ctx); 5696fcf5ef2aSThomas Huth #else 56979f0cf041SMatheus Ferst CHK_SV(ctx); 5698fcf5ef2aSThomas Huth /* Restore CPU state */ 5699fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 570059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5701fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5702fcf5ef2aSThomas Huth } 5703fcf5ef2aSThomas Huth 5704fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5705fcf5ef2aSThomas Huth 5706fcf5ef2aSThomas Huth /* tlbre */ 5707fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5708fcf5ef2aSThomas Huth { 5709fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57109f0cf041SMatheus Ferst GEN_PRIV(ctx); 5711fcf5ef2aSThomas Huth #else 57129f0cf041SMatheus Ferst CHK_SV(ctx); 5713fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5714fcf5ef2aSThomas Huth case 0: 5715fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5716fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5717fcf5ef2aSThomas Huth break; 5718fcf5ef2aSThomas Huth case 1: 5719fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5720fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5721fcf5ef2aSThomas Huth break; 5722fcf5ef2aSThomas Huth default: 5723fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5724fcf5ef2aSThomas Huth break; 5725fcf5ef2aSThomas Huth } 5726fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5727fcf5ef2aSThomas Huth } 5728fcf5ef2aSThomas Huth 5729fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5730fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5731fcf5ef2aSThomas Huth { 5732fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57339f0cf041SMatheus Ferst GEN_PRIV(ctx); 5734fcf5ef2aSThomas Huth #else 5735fcf5ef2aSThomas Huth TCGv t0; 5736fcf5ef2aSThomas Huth 57379f0cf041SMatheus Ferst CHK_SV(ctx); 5738fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5739fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5740fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5741fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5742fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5743fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5744fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5745fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5746fcf5ef2aSThomas Huth gen_set_label(l1); 5747fcf5ef2aSThomas Huth } 5748fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5749fcf5ef2aSThomas Huth } 5750fcf5ef2aSThomas Huth 5751fcf5ef2aSThomas Huth /* tlbwe */ 5752fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5753fcf5ef2aSThomas Huth { 5754fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57559f0cf041SMatheus Ferst GEN_PRIV(ctx); 5756fcf5ef2aSThomas Huth #else 57579f0cf041SMatheus Ferst CHK_SV(ctx); 5758fcf5ef2aSThomas Huth 5759fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5760fcf5ef2aSThomas Huth case 0: 5761fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5762fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5763fcf5ef2aSThomas Huth break; 5764fcf5ef2aSThomas Huth case 1: 5765fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5766fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5767fcf5ef2aSThomas Huth break; 5768fcf5ef2aSThomas Huth default: 5769fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5770fcf5ef2aSThomas Huth break; 5771fcf5ef2aSThomas Huth } 5772fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5773fcf5ef2aSThomas Huth } 5774fcf5ef2aSThomas Huth 5775fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5776fcf5ef2aSThomas Huth 5777fcf5ef2aSThomas Huth /* tlbre */ 5778fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5779fcf5ef2aSThomas Huth { 5780fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57819f0cf041SMatheus Ferst GEN_PRIV(ctx); 5782fcf5ef2aSThomas Huth #else 57839f0cf041SMatheus Ferst CHK_SV(ctx); 5784fcf5ef2aSThomas Huth 5785fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5786fcf5ef2aSThomas Huth case 0: 5787fcf5ef2aSThomas Huth case 1: 5788fcf5ef2aSThomas Huth case 2: 5789fcf5ef2aSThomas Huth { 57907058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5791fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5792fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5793fcf5ef2aSThomas Huth } 5794fcf5ef2aSThomas Huth break; 5795fcf5ef2aSThomas Huth default: 5796fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5797fcf5ef2aSThomas Huth break; 5798fcf5ef2aSThomas Huth } 5799fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5800fcf5ef2aSThomas Huth } 5801fcf5ef2aSThomas Huth 5802fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5803fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5804fcf5ef2aSThomas Huth { 5805fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58069f0cf041SMatheus Ferst GEN_PRIV(ctx); 5807fcf5ef2aSThomas Huth #else 5808fcf5ef2aSThomas Huth TCGv t0; 5809fcf5ef2aSThomas Huth 58109f0cf041SMatheus Ferst CHK_SV(ctx); 5811fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5812fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5813fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5814fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5815fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5816fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5817fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5818fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5819fcf5ef2aSThomas Huth gen_set_label(l1); 5820fcf5ef2aSThomas Huth } 5821fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5822fcf5ef2aSThomas Huth } 5823fcf5ef2aSThomas Huth 5824fcf5ef2aSThomas Huth /* tlbwe */ 5825fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5826fcf5ef2aSThomas Huth { 5827fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58289f0cf041SMatheus Ferst GEN_PRIV(ctx); 5829fcf5ef2aSThomas Huth #else 58309f0cf041SMatheus Ferst CHK_SV(ctx); 5831fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5832fcf5ef2aSThomas Huth case 0: 5833fcf5ef2aSThomas Huth case 1: 5834fcf5ef2aSThomas Huth case 2: 5835fcf5ef2aSThomas Huth { 58367058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5837fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5838fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5839fcf5ef2aSThomas Huth } 5840fcf5ef2aSThomas Huth break; 5841fcf5ef2aSThomas Huth default: 5842fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5843fcf5ef2aSThomas Huth break; 5844fcf5ef2aSThomas Huth } 5845fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5846fcf5ef2aSThomas Huth } 5847fcf5ef2aSThomas Huth 5848fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5849fcf5ef2aSThomas Huth 5850fcf5ef2aSThomas Huth /* tlbre */ 5851fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5852fcf5ef2aSThomas Huth { 5853fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58549f0cf041SMatheus Ferst GEN_PRIV(ctx); 5855fcf5ef2aSThomas Huth #else 58569f0cf041SMatheus Ferst CHK_SV(ctx); 5857fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5858fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5859fcf5ef2aSThomas Huth } 5860fcf5ef2aSThomas Huth 5861fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5862fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5863fcf5ef2aSThomas Huth { 5864fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58659f0cf041SMatheus Ferst GEN_PRIV(ctx); 5866fcf5ef2aSThomas Huth #else 5867fcf5ef2aSThomas Huth TCGv t0; 5868fcf5ef2aSThomas Huth 58699f0cf041SMatheus Ferst CHK_SV(ctx); 5870fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5871fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 58729d15d8e1SRichard Henderson tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5873fcf5ef2aSThomas Huth } else { 58749d15d8e1SRichard Henderson t0 = cpu_gpr[rB(ctx->opcode)]; 5875fcf5ef2aSThomas Huth } 5876fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5877fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5878fcf5ef2aSThomas Huth } 5879fcf5ef2aSThomas Huth 5880fcf5ef2aSThomas Huth /* tlbwe */ 5881fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5882fcf5ef2aSThomas Huth { 5883fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58849f0cf041SMatheus Ferst GEN_PRIV(ctx); 5885fcf5ef2aSThomas Huth #else 58869f0cf041SMatheus Ferst CHK_SV(ctx); 5887fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5888fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5889fcf5ef2aSThomas Huth } 5890fcf5ef2aSThomas Huth 5891fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5892fcf5ef2aSThomas Huth { 5893fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58949f0cf041SMatheus Ferst GEN_PRIV(ctx); 5895fcf5ef2aSThomas Huth #else 5896fcf5ef2aSThomas Huth TCGv t0; 5897fcf5ef2aSThomas Huth 58989f0cf041SMatheus Ferst CHK_SV(ctx); 5899fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5900fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5901fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5902fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5903fcf5ef2aSThomas Huth } 5904fcf5ef2aSThomas Huth 5905fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5906fcf5ef2aSThomas Huth { 5907fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59089f0cf041SMatheus Ferst GEN_PRIV(ctx); 5909fcf5ef2aSThomas Huth #else 5910fcf5ef2aSThomas Huth TCGv t0; 5911fcf5ef2aSThomas Huth 59129f0cf041SMatheus Ferst CHK_SV(ctx); 5913fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5914fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5915fcf5ef2aSThomas Huth 5916fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 5917fcf5ef2aSThomas Huth case 0: 5918fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 5919fcf5ef2aSThomas Huth break; 5920fcf5ef2aSThomas Huth case 1: 5921fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 5922fcf5ef2aSThomas Huth break; 5923fcf5ef2aSThomas Huth case 3: 5924fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 5925fcf5ef2aSThomas Huth break; 5926fcf5ef2aSThomas Huth default: 5927fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5928fcf5ef2aSThomas Huth break; 5929fcf5ef2aSThomas Huth } 5930fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5931fcf5ef2aSThomas Huth } 5932fcf5ef2aSThomas Huth 5933fcf5ef2aSThomas Huth /* wrtee */ 5934fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 5935fcf5ef2aSThomas Huth { 5936fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59379f0cf041SMatheus Ferst GEN_PRIV(ctx); 5938fcf5ef2aSThomas Huth #else 5939fcf5ef2aSThomas Huth TCGv t0; 5940fcf5ef2aSThomas Huth 59419f0cf041SMatheus Ferst CHK_SV(ctx); 5942fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5943fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5944fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5945fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 59462fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5947efe843d8SDavid Gibson /* 5948efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 5949efe843d8SDavid Gibson * just set msr_ee to 1 5950fcf5ef2aSThomas Huth */ 5951d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5952fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5953fcf5ef2aSThomas Huth } 5954fcf5ef2aSThomas Huth 5955fcf5ef2aSThomas Huth /* wrteei */ 5956fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 5957fcf5ef2aSThomas Huth { 5958fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59599f0cf041SMatheus Ferst GEN_PRIV(ctx); 5960fcf5ef2aSThomas Huth #else 59619f0cf041SMatheus Ferst CHK_SV(ctx); 5962fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 5963fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 59642fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5965fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 5966d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5967fcf5ef2aSThomas Huth } else { 5968fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5969fcf5ef2aSThomas Huth } 5970fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5971fcf5ef2aSThomas Huth } 5972fcf5ef2aSThomas Huth 5973fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 5974fcf5ef2aSThomas Huth 5975fcf5ef2aSThomas Huth /* dlmzb */ 5976fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 5977fcf5ef2aSThomas Huth { 59787058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 5979fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 5980fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 5981fcf5ef2aSThomas Huth } 5982fcf5ef2aSThomas Huth 5983fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 5984fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 5985fcf5ef2aSThomas Huth { 5986fcf5ef2aSThomas Huth /* interpreted as no-op */ 5987fcf5ef2aSThomas Huth } 5988fcf5ef2aSThomas Huth 5989fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 5990fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 5991fcf5ef2aSThomas Huth { 599227a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 599327a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 599427a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 599527a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 599627a3ea7eSBALATON Zoltan } 599727a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 5998fcf5ef2aSThomas Huth } 5999fcf5ef2aSThomas Huth 6000fcf5ef2aSThomas Huth /* icbt */ 6001fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6002fcf5ef2aSThomas Huth { 6003efe843d8SDavid Gibson /* 6004efe843d8SDavid Gibson * interpreted as no-op 6005efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6006efe843d8SDavid Gibson * does not generate any exception 6007fcf5ef2aSThomas Huth */ 6008fcf5ef2aSThomas Huth } 6009fcf5ef2aSThomas Huth 6010fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6011fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6012fcf5ef2aSThomas Huth { 6013fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6014fcf5ef2aSThomas Huth 6015fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6016fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6017fcf5ef2aSThomas Huth } 6018fcf5ef2aSThomas Huth 6019fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6020fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6021fcf5ef2aSThomas Huth { 6022fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6023fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6024fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6025fcf5ef2aSThomas Huth 6026fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6027fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6028fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6029fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6030fcf5ef2aSThomas Huth } else { 6031fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6032fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6033fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6034fcf5ef2aSThomas Huth } 6035fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6036fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6037fcf5ef2aSThomas Huth } 6038fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6039fcf5ef2aSThomas Huth 6040fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6041fcf5ef2aSThomas Huth { 6042fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6043fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6044fcf5ef2aSThomas Huth return; 6045fcf5ef2aSThomas Huth } 6046fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6047fcf5ef2aSThomas Huth } 6048fcf5ef2aSThomas Huth 6049fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6050fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6051fcf5ef2aSThomas Huth { \ 6052fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6053fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6054fcf5ef2aSThomas Huth return; \ 6055fcf5ef2aSThomas Huth } \ 6056efe843d8SDavid Gibson /* \ 6057efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6058fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6059fcf5ef2aSThomas Huth * \ 6060fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6061fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6062fcf5ef2aSThomas Huth */ \ 6063fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6064fcf5ef2aSThomas Huth } 6065fcf5ef2aSThomas Huth 6066fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6067fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6068fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6069fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6070fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6071fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6072fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6073efe843d8SDavid Gibson 6074b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6075b8b4576eSSuraj Jitindar Singh { 6076efe843d8SDavid Gibson /* Do Nothing */ 6077b8b4576eSSuraj Jitindar Singh } 6078fcf5ef2aSThomas Huth 607980b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 608080b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 608180b8c1eeSNikunj A Dadhania { \ 6082efe843d8SDavid Gibson /* \ 6083efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6084efe843d8SDavid Gibson * implementation of the copy paste facility \ 608580b8c1eeSNikunj A Dadhania */ \ 608680b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 608780b8c1eeSNikunj A Dadhania } 608880b8c1eeSNikunj A Dadhania 608980b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 609080b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 609180b8c1eeSNikunj A Dadhania 6092fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6093fcf5ef2aSThomas Huth { 6094fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6095fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6096fcf5ef2aSThomas Huth return; 6097fcf5ef2aSThomas Huth } 6098efe843d8SDavid Gibson /* 6099efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6100efe843d8SDavid Gibson * simple: 6101fcf5ef2aSThomas Huth * 6102fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6103fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6104fcf5ef2aSThomas Huth */ 6105fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6106fcf5ef2aSThomas Huth } 6107fcf5ef2aSThomas Huth 6108fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6109fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6110fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6111fcf5ef2aSThomas Huth { \ 61129f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6113fcf5ef2aSThomas Huth } 6114fcf5ef2aSThomas Huth 6115fcf5ef2aSThomas Huth #else 6116fcf5ef2aSThomas Huth 6117fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6118fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6119fcf5ef2aSThomas Huth { \ 61209f0cf041SMatheus Ferst CHK_SV(ctx); \ 6121fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6122fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6123fcf5ef2aSThomas Huth return; \ 6124fcf5ef2aSThomas Huth } \ 6125efe843d8SDavid Gibson /* \ 6126efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6127fcf5ef2aSThomas Huth * simple: \ 6128fcf5ef2aSThomas Huth * \ 6129fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6130fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6131fcf5ef2aSThomas Huth */ \ 6132fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6133fcf5ef2aSThomas Huth } 6134fcf5ef2aSThomas Huth 6135fcf5ef2aSThomas Huth #endif 6136fcf5ef2aSThomas Huth 6137fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6138fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6139fcf5ef2aSThomas Huth 61401a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 61411a404c91SMark Cave-Ayland { 6142e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 61431a404c91SMark Cave-Ayland } 61441a404c91SMark Cave-Ayland 61451a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 61461a404c91SMark Cave-Ayland { 6147e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 61484b65b6e7SVíctor Colombo /* 61494b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 61504b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 61514b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 61524b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 61534b65b6e7SVíctor Colombo * to be 0. 61544b65b6e7SVíctor Colombo */ 61554b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 61561a404c91SMark Cave-Ayland } 61571a404c91SMark Cave-Ayland 6158c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6159c4a18dbfSMark Cave-Ayland { 616037da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6161c4a18dbfSMark Cave-Ayland } 6162c4a18dbfSMark Cave-Ayland 6163c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6164c4a18dbfSMark Cave-Ayland { 616537da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6166c4a18dbfSMark Cave-Ayland } 6167c4a18dbfSMark Cave-Ayland 6168c9826ae9SRichard Henderson /* 6169f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6170f2aabda8SRichard Henderson */ 6171d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6172d39b2cc7SLuis Pires { 6173d39b2cc7SLuis Pires return x * 2; 6174d39b2cc7SLuis Pires } 6175d39b2cc7SLuis Pires 6176f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6177f2aabda8SRichard Henderson { 6178f2aabda8SRichard Henderson return x * 4; 6179f2aabda8SRichard Henderson } 6180f2aabda8SRichard Henderson 6181e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6182e10271e1SMatheus Ferst { 6183e10271e1SMatheus Ferst return x * 16; 6184e10271e1SMatheus Ferst } 6185e10271e1SMatheus Ferst 6186670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6187670f1da3SVíctor Colombo { 6188670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6189670f1da3SVíctor Colombo } 6190670f1da3SVíctor Colombo 6191f2aabda8SRichard Henderson /* 6192c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6193c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6194c9826ae9SRichard Henderson * proper variable. 6195c9826ae9SRichard Henderson */ 6196c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6197c9826ae9SRichard Henderson do { \ 6198c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6199c9826ae9SRichard Henderson return false; \ 6200c9826ae9SRichard Henderson } \ 6201c9826ae9SRichard Henderson } while (0) 6202c9826ae9SRichard Henderson 6203c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6204c9826ae9SRichard Henderson do { \ 6205c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6206c9826ae9SRichard Henderson return false; \ 6207c9826ae9SRichard Henderson } \ 6208c9826ae9SRichard Henderson } while (0) 6209c9826ae9SRichard Henderson 6210c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6211c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6212c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6213c9826ae9SRichard Henderson #else 6214c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6215c9826ae9SRichard Henderson #endif 6216c9826ae9SRichard Henderson 6217e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6218e2205a46SBruno Larsen do { \ 6219e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6220e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6221e2205a46SBruno Larsen return true; \ 6222e2205a46SBruno Larsen } \ 6223e2205a46SBruno Larsen } while (0) 6224e2205a46SBruno Larsen 62258226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 62268226cb2dSBruno Larsen (billionai) do { \ 62278226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 62288226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 62298226cb2dSBruno Larsen (billionai) return true; \ 62308226cb2dSBruno Larsen (billionai) } \ 62318226cb2dSBruno Larsen (billionai) } while (0) 62328226cb2dSBruno Larsen (billionai) 623386057426SFernando Valle #define REQUIRE_FPU(ctx) \ 623486057426SFernando Valle do { \ 623586057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 623686057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 623786057426SFernando Valle return true; \ 623886057426SFernando Valle } \ 623986057426SFernando Valle } while (0) 624086057426SFernando Valle 6241fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6242fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6243fc34e81aSMatheus Ferst do { \ 6244fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6245fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6246fc34e81aSMatheus Ferst return true; \ 6247fc34e81aSMatheus Ferst } \ 6248fc34e81aSMatheus Ferst } while (0) 6249fc34e81aSMatheus Ferst 6250fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6251fc34e81aSMatheus Ferst do { \ 6252e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6253fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6254fc34e81aSMatheus Ferst return true; \ 6255fc34e81aSMatheus Ferst } \ 6256fc34e81aSMatheus Ferst } while (0) 6257fc34e81aSMatheus Ferst #else 6258fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6259fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6260fc34e81aSMatheus Ferst #endif 6261fc34e81aSMatheus Ferst 6262f2aabda8SRichard Henderson /* 6263f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6264f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6265f2aabda8SRichard Henderson */ 6266f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6267f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6268f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 626919f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 627019f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 627119f0862dSLuis Pires { \ 627219f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 627319f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 627419f0862dSLuis Pires } 627519f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 627619f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 627719f0862dSLuis Pires { \ 627819f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 627919f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 628019f0862dSLuis Pires } 6281f2aabda8SRichard Henderson 6282f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6283f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6284f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 628519f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 628619f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 628719f0862dSLuis Pires { \ 628819f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 628919f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 629019f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 629119f0862dSLuis Pires } 6292f2aabda8SRichard Henderson 6293f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6294f2aabda8SRichard Henderson 6295f2aabda8SRichard Henderson 629699082815SRichard Henderson #include "decode-insn32.c.inc" 629799082815SRichard Henderson #include "decode-insn64.c.inc" 6298565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6299565cb109SGustavo Romero 6300725b2d4dSFernando Eckhardt Valle /* 6301725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6302725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6303725b2d4dSFernando Eckhardt Valle */ 6304725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6305725b2d4dSFernando Eckhardt Valle { 6306725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6307725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6308725b2d4dSFernando Eckhardt Valle d->si = a->si; 6309725b2d4dSFernando Eckhardt Valle if (a->r) { 6310725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6311725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6312725b2d4dSFernando Eckhardt Valle return false; 6313725b2d4dSFernando Eckhardt Valle } 6314725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6315725b2d4dSFernando Eckhardt Valle } 6316725b2d4dSFernando Eckhardt Valle return true; 6317725b2d4dSFernando Eckhardt Valle } 6318725b2d4dSFernando Eckhardt Valle 631999082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 632099082815SRichard Henderson 6321139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6322fcf5ef2aSThomas Huth 6323139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6324fcf5ef2aSThomas Huth 6325139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6326fcf5ef2aSThomas Huth 6327139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6328fcf5ef2aSThomas Huth 6329139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6330fcf5ef2aSThomas Huth 63311f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 63321f26c751SDaniel Henrique Barboza 633398f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 633498f43417SMatheus Ferst 6335016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6336016b6e1dSLeandro Lupori 633720e2d04eSLeandro Lupori /* Handles lfdp */ 63385cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 63395cb091a4SNikunj A Dadhania { 634020e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 63415cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 63425cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 63435cb091a4SNikunj A Dadhania } 63445cb091a4SNikunj A Dadhania } 63455cb091a4SNikunj A Dadhania return gen_invalid(ctx); 63465cb091a4SNikunj A Dadhania } 63475cb091a4SNikunj A Dadhania 634820e2d04eSLeandro Lupori /* Handles stfdp */ 6349e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6350e3001664SNikunj A Dadhania { 635120e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 635220e2d04eSLeandro Lupori /* stfdp */ 6353e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6354e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6355e3001664SNikunj A Dadhania } 6356e3001664SNikunj A Dadhania } 6357e3001664SNikunj A Dadhania return gen_invalid(ctx); 6358e3001664SNikunj A Dadhania } 6359e3001664SNikunj A Dadhania 63609d69cfa2SLijun Pan #if defined(TARGET_PPC64) 63619d69cfa2SLijun Pan /* brd */ 63629d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 63639d69cfa2SLijun Pan { 63649d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 63659d69cfa2SLijun Pan } 63669d69cfa2SLijun Pan 63679d69cfa2SLijun Pan /* brw */ 63689d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 63699d69cfa2SLijun Pan { 63709d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 63719d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 63729d69cfa2SLijun Pan 63739d69cfa2SLijun Pan } 63749d69cfa2SLijun Pan 63759d69cfa2SLijun Pan /* brh */ 63769d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 63779d69cfa2SLijun Pan { 6378491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 63799d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 63809d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 63819d69cfa2SLijun Pan 63829d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6383491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6384491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 63859d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 63869d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 63879d69cfa2SLijun Pan } 63889d69cfa2SLijun Pan #endif 63899d69cfa2SLijun Pan 6390fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 63919d69cfa2SLijun Pan #if defined(TARGET_PPC64) 63929d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 63939d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 63949d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 63959d69cfa2SLijun Pan #endif 6396fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6397fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6398fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6399fcf5ef2aSThomas Huth #endif 6400fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6401fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6402fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6403fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6404fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6405fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6406fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6407fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6408fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6409fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6410fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6411fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6412fcf5ef2aSThomas Huth #endif 6413fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6414fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6415fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6416fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6417fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6418fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6419fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 642080b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6421b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 642280b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6423fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6424fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6425fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6426fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6427fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6428fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6429fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6430fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6431fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6432fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6433fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6434fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6435fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6436fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6437fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6438fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6439fcf5ef2aSThomas Huth #endif 6440fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6441fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6442fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6443fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6444fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6445fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6446fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6447fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6448fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6449fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6450fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6451fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6452fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6453fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6454fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6455fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6456fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6457fcf5ef2aSThomas Huth #endif 64585cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 64595cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 646072b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6461e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6462fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6463fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6464fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6465fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6466fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6467fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6468c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6469fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6470fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6471fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6472fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6473a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6474a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6475fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6476fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6477fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6478fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6479a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6480a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6481fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6482fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6483fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6484fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6485fcf5ef2aSThomas Huth #endif 6486fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 64870c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 64880c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 64890c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6490fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6491fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6492fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6493fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6494fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6495fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6496fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6497fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6498fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 64993c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 65003c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65013c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65023c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65033c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 65043c89b8d6SNicholas Piggin #endif 6505cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6506fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6507fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6508fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6509fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6510fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6511fcf5ef2aSThomas Huth #endif 65123c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65133c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 65143c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6515fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6516fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6517fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6518fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6519fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6520fcf5ef2aSThomas Huth #endif 6521fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6522fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6523fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6524fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6525fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6526fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6527fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6528fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6529fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6530b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6531fcf5ef2aSThomas Huth #endif 6532fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6533fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6534fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 653550728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6536fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6537fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 653850728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6539fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 654050728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6541fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 654250728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6543fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6544e64645baSBernhard Beschow GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6545fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 654650728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6547fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 654899d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6549fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6550fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 655150728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6552fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6553fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6554fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6555fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6556fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6557fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6558fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6559fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6560fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6561fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6562fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6563fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6564fcf5ef2aSThomas Huth #endif 6565fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6566efe843d8SDavid Gibson /* 6567efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6568efe843d8SDavid Gibson * different ISA versions 6569efe843d8SDavid Gibson */ 6570fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6571fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6572fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6573fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6574fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6575fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6576fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6577fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6578fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6579fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6580fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6581fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6582fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6583fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6584fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6585fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6586fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6587fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6588fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6589fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6590fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6591fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6592fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6593fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6594fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6595fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6596fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6597fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6598fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6599fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6600fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6601fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6602fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6603fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6604fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6605fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6606fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6607fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6608fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6609fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6610fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 661127a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6612fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6613fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 66140c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 66150c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6616fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6617fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6618fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6619fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6620fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6621fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6622fcf5ef2aSThomas Huth PPC2_ISA300), 6623fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6624fcf5ef2aSThomas Huth #endif 6625fcf5ef2aSThomas Huth 6626fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6627fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6628fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6629fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6630fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6631fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6632fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6633fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6634fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6635fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6636fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6637fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6638fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6639fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6640fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 66414c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6642fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6643fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6644fcf5ef2aSThomas Huth 6645fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6646fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6647fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6648fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6649fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6650fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6651fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6652fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6653fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6654fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6655fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6656fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6657fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6658fcf5ef2aSThomas Huth 6659fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6660fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6661fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6662fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6663fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6664fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6665fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6666fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6667fcf5ef2aSThomas Huth 6668fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6669fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6670fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6671fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6672fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6673fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6674fcf5ef2aSThomas Huth 6675fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6676fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6677fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6678fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6679fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6680fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6681fcf5ef2aSThomas Huth #endif 6682fcf5ef2aSThomas Huth 6683fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6684fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6685fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6686fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6687fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6688fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6689fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6690fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6691fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6692fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6693fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6694fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6695fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6696fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6697fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6698fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6699fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6700fcf5ef2aSThomas Huth 6701fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6702fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6703fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6704fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6705fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6706fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6707fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6708fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6709fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6710fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6711fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6712fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6713fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6714fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6715fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6716fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6717fcf5ef2aSThomas Huth #endif 6718fcf5ef2aSThomas Huth 6719fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6720fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6721fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6722fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6723fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6724fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6725fcf5ef2aSThomas Huth PPC_64B) 6726fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6727fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6728fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6729fcf5ef2aSThomas Huth PPC_64B), \ 6730fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6731fcf5ef2aSThomas Huth PPC_64B), \ 6732fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6733fcf5ef2aSThomas Huth PPC_64B) 6734fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6735fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6736fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6737fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6738fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6739fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6740fcf5ef2aSThomas Huth #endif 6741fcf5ef2aSThomas Huth 6742fcf5ef2aSThomas Huth #undef GEN_LDX_E 6743fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6744fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6745fcf5ef2aSThomas Huth 6746fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6747fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6748fcf5ef2aSThomas Huth 6749fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6750fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6751fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6752fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6753fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6754fcf5ef2aSThomas Huth #endif 6755fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6756fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6757fcf5ef2aSThomas Huth 675850728199SRoman Kapl /* External PID based load */ 675950728199SRoman Kapl #undef GEN_LDEPX 676050728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 676150728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 676250728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 676350728199SRoman Kapl 676450728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 676550728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 676650728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 676750728199SRoman Kapl #if defined(TARGET_PPC64) 6768fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 676950728199SRoman Kapl #endif 677050728199SRoman Kapl 6771fcf5ef2aSThomas Huth #undef GEN_STX_E 6772fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 67730123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6774fcf5ef2aSThomas Huth 6775fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6776fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6777fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6778fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6779fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6780fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6781fcf5ef2aSThomas Huth #endif 6782fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6783fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6784fcf5ef2aSThomas Huth 678550728199SRoman Kapl #undef GEN_STEPX 678650728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 678750728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 678850728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 678950728199SRoman Kapl 679050728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 679150728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 679250728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 679350728199SRoman Kapl #if defined(TARGET_PPC64) 6794fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 679550728199SRoman Kapl #endif 679650728199SRoman Kapl 6797fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6798fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6799fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6800fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6801fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6802fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6803fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6804fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6805fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6806fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6807fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6808fcf5ef2aSThomas Huth 6809fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6810fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6811fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6812fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6813fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6814fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6815fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6816fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6817fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6818fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6819fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6820fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6821fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6822fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6823fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6824fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6825fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6826fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6827fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6828fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6829fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6830fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6831fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6832fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6833fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6834fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6835fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6836fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6837fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6838fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6839fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6840fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6841fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6842fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6843fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6844fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6845fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6846fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6847fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6848fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6849fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6850fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6851fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6852fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6853fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6854fcf5ef2aSThomas Huth 6855fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6856fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6857fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6858fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6859fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6860fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6861fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6862fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6863fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6864fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6865fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6866fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6867fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6868fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6869fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6870fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6871fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6872fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6873fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6874fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6875fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6876fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6877fcf5ef2aSThomas Huth 6878139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 6879fcf5ef2aSThomas Huth 6880139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 6881fcf5ef2aSThomas Huth 6882139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 6883fcf5ef2aSThomas Huth 6884139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 6885fcf5ef2aSThomas Huth }; 6886fcf5ef2aSThomas Huth 68877468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 68887468e2c8SBruno Larsen (billionai) /* Opcode types */ 68897468e2c8SBruno Larsen (billionai) enum { 68907468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 68917468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 68927468e2c8SBruno Larsen (billionai) }; 68937468e2c8SBruno Larsen (billionai) 68947468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 68957468e2c8SBruno Larsen (billionai) 68967468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 68977468e2c8SBruno Larsen (billionai) { 68987468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 68997468e2c8SBruno Larsen (billionai) } 69007468e2c8SBruno Larsen (billionai) 69017468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 69027468e2c8SBruno Larsen (billionai) { 69037468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 69047468e2c8SBruno Larsen (billionai) } 69057468e2c8SBruno Larsen (billionai) 69067468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 69077468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 69087468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 69097468e2c8SBruno Larsen (billionai) { 69107468e2c8SBruno Larsen (billionai) int i; 69117468e2c8SBruno Larsen (billionai) 69127468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 69137468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 69147468e2c8SBruno Larsen (billionai) } 69157468e2c8SBruno Larsen (billionai) } 69167468e2c8SBruno Larsen (billionai) 69177468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 69187468e2c8SBruno Larsen (billionai) { 69197468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 69207468e2c8SBruno Larsen (billionai) 69217468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 69227468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 69237468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 69247468e2c8SBruno Larsen (billionai) 69257468e2c8SBruno Larsen (billionai) return 0; 69267468e2c8SBruno Larsen (billionai) } 69277468e2c8SBruno Larsen (billionai) 69287468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 69297468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69307468e2c8SBruno Larsen (billionai) { 69317468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 69327468e2c8SBruno Larsen (billionai) return -1; 69337468e2c8SBruno Larsen (billionai) } 69347468e2c8SBruno Larsen (billionai) table[idx] = handler; 69357468e2c8SBruno Larsen (billionai) 69367468e2c8SBruno Larsen (billionai) return 0; 69377468e2c8SBruno Larsen (billionai) } 69387468e2c8SBruno Larsen (billionai) 69397468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 69407468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 69417468e2c8SBruno Larsen (billionai) { 69427468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 69437468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 69447468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 69457468e2c8SBruno Larsen (billionai) return -1; 69467468e2c8SBruno Larsen (billionai) } 69477468e2c8SBruno Larsen (billionai) 69487468e2c8SBruno Larsen (billionai) return 0; 69497468e2c8SBruno Larsen (billionai) } 69507468e2c8SBruno Larsen (billionai) 69517468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 69527468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69537468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69547468e2c8SBruno Larsen (billionai) { 69557468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 69567468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 69577468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 69587468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 69597468e2c8SBruno Larsen (billionai) return -1; 69607468e2c8SBruno Larsen (billionai) } 69617468e2c8SBruno Larsen (billionai) } else { 69627468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 69637468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 69647468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 69657468e2c8SBruno Larsen (billionai) return -1; 69667468e2c8SBruno Larsen (billionai) } 69677468e2c8SBruno Larsen (billionai) } 69687468e2c8SBruno Larsen (billionai) if (handler != NULL && 69697468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 69707468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 69717468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 69727468e2c8SBruno Larsen (billionai) return -1; 69737468e2c8SBruno Larsen (billionai) } 69747468e2c8SBruno Larsen (billionai) 69757468e2c8SBruno Larsen (billionai) return 0; 69767468e2c8SBruno Larsen (billionai) } 69777468e2c8SBruno Larsen (billionai) 69787468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 69797468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69807468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69817468e2c8SBruno Larsen (billionai) { 69827468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 69837468e2c8SBruno Larsen (billionai) } 69847468e2c8SBruno Larsen (billionai) 69857468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 69867468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69877468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 69887468e2c8SBruno Larsen (billionai) { 69897468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 69907468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 69917468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 69927468e2c8SBruno Larsen (billionai) return -1; 69937468e2c8SBruno Larsen (billionai) } 69947468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 69957468e2c8SBruno Larsen (billionai) handler) < 0) { 69967468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 69977468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 69987468e2c8SBruno Larsen (billionai) return -1; 69997468e2c8SBruno Larsen (billionai) } 70007468e2c8SBruno Larsen (billionai) 70017468e2c8SBruno Larsen (billionai) return 0; 70027468e2c8SBruno Larsen (billionai) } 70037468e2c8SBruno Larsen (billionai) 70047468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 70057468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70067468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 70077468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70087468e2c8SBruno Larsen (billionai) { 70097468e2c8SBruno Larsen (billionai) opc_handler_t **table; 70107468e2c8SBruno Larsen (billionai) 70117468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70127468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70137468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70147468e2c8SBruno Larsen (billionai) return -1; 70157468e2c8SBruno Larsen (billionai) } 70167468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 70177468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 70187468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 70197468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70207468e2c8SBruno Larsen (billionai) return -1; 70217468e2c8SBruno Larsen (billionai) } 70227468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 70237468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 70247468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70257468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 70267468e2c8SBruno Larsen (billionai) return -1; 70277468e2c8SBruno Larsen (billionai) } 70287468e2c8SBruno Larsen (billionai) return 0; 70297468e2c8SBruno Larsen (billionai) } 70307468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 70317468e2c8SBruno Larsen (billionai) { 70327468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 70337468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 70347468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 70357468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70367468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 70377468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 70387468e2c8SBruno Larsen (billionai) return -1; 70397468e2c8SBruno Larsen (billionai) } 70407468e2c8SBruno Larsen (billionai) } else { 70417468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70427468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 70437468e2c8SBruno Larsen (billionai) return -1; 70447468e2c8SBruno Larsen (billionai) } 70457468e2c8SBruno Larsen (billionai) } 70467468e2c8SBruno Larsen (billionai) } else { 70477468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 70487468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 70497468e2c8SBruno Larsen (billionai) return -1; 70507468e2c8SBruno Larsen (billionai) } 70517468e2c8SBruno Larsen (billionai) } 70527468e2c8SBruno Larsen (billionai) } else { 70537468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 70547468e2c8SBruno Larsen (billionai) return -1; 70557468e2c8SBruno Larsen (billionai) } 70567468e2c8SBruno Larsen (billionai) } 70577468e2c8SBruno Larsen (billionai) 70587468e2c8SBruno Larsen (billionai) return 0; 70597468e2c8SBruno Larsen (billionai) } 70607468e2c8SBruno Larsen (billionai) 70617468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 70627468e2c8SBruno Larsen (billionai) { 70637468e2c8SBruno Larsen (billionai) int i, count, tmp; 70647468e2c8SBruno Larsen (billionai) 70657468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 70667468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 70677468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 70687468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 70697468e2c8SBruno Larsen (billionai) } 70707468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 70717468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 70727468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 70737468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 70747468e2c8SBruno Larsen (billionai) if (tmp == 0) { 70757468e2c8SBruno Larsen (billionai) free(table[i]); 70767468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 70777468e2c8SBruno Larsen (billionai) } else { 70787468e2c8SBruno Larsen (billionai) count++; 70797468e2c8SBruno Larsen (billionai) } 70807468e2c8SBruno Larsen (billionai) } else { 70817468e2c8SBruno Larsen (billionai) count++; 70827468e2c8SBruno Larsen (billionai) } 70837468e2c8SBruno Larsen (billionai) } 70847468e2c8SBruno Larsen (billionai) } 70857468e2c8SBruno Larsen (billionai) 70867468e2c8SBruno Larsen (billionai) return count; 70877468e2c8SBruno Larsen (billionai) } 70887468e2c8SBruno Larsen (billionai) 70897468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 70907468e2c8SBruno Larsen (billionai) { 70917468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 70927468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 70937468e2c8SBruno Larsen (billionai) } 70947468e2c8SBruno Larsen (billionai) } 70957468e2c8SBruno Larsen (billionai) 70967468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 70977468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 70987468e2c8SBruno Larsen (billionai) { 70997468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 71007468e2c8SBruno Larsen (billionai) opcode_t *opc; 71017468e2c8SBruno Larsen (billionai) 71027468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 71037468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 71047468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 71057468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 71067468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 71077468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 71087468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 71097468e2c8SBruno Larsen (billionai) opc->opc3); 71107468e2c8SBruno Larsen (billionai) return; 71117468e2c8SBruno Larsen (billionai) } 71127468e2c8SBruno Larsen (billionai) } 71137468e2c8SBruno Larsen (billionai) } 71147468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 71157468e2c8SBruno Larsen (billionai) fflush(stdout); 71167468e2c8SBruno Larsen (billionai) fflush(stderr); 71177468e2c8SBruno Larsen (billionai) } 71187468e2c8SBruno Larsen (billionai) 71197468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 71207468e2c8SBruno Larsen (billionai) { 71217468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 71227468e2c8SBruno Larsen (billionai) int i, j, k; 71237468e2c8SBruno Larsen (billionai) 71247468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 71257468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 71267468e2c8SBruno Larsen (billionai) continue; 71277468e2c8SBruno Larsen (billionai) } 71287468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 71297468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 71307468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 71317468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 71327468e2c8SBruno Larsen (billionai) continue; 71337468e2c8SBruno Larsen (billionai) } 71347468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 71357468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 71367468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 71377468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 71387468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 71397468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 71407468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71417468e2c8SBruno Larsen (billionai) } 71427468e2c8SBruno Larsen (billionai) } 71437468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 71447468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71457468e2c8SBruno Larsen (billionai) } 71467468e2c8SBruno Larsen (billionai) } 71477468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 71487468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71497468e2c8SBruno Larsen (billionai) } 71507468e2c8SBruno Larsen (billionai) } 71517468e2c8SBruno Larsen (billionai) } 71527468e2c8SBruno Larsen (billionai) 71537468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 71547468e2c8SBruno Larsen (billionai) { 71557468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 71567468e2c8SBruno Larsen (billionai) 71577468e2c8SBruno Larsen (billionai) /* 71587468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 71597468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 71607468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 71617468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 71627468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 71637468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 71647468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 71657468e2c8SBruno Larsen (billionai) */ 71667468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 71677468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 71687468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 71697468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 71707468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 71717468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 71727468e2c8SBruno Larsen (billionai) } 71737468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 71747468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 71757468e2c8SBruno Larsen (billionai) return 0; 71767468e2c8SBruno Larsen (billionai) } 71777468e2c8SBruno Larsen (billionai) 7178624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7179624cb07fSRichard Henderson { 7180624cb07fSRichard Henderson opc_handler_t **table, *handler; 7181624cb07fSRichard Henderson uint32_t inval; 7182624cb07fSRichard Henderson 7183624cb07fSRichard Henderson ctx->opcode = insn; 7184624cb07fSRichard Henderson 7185624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7186624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7187624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7188624cb07fSRichard Henderson 7189624cb07fSRichard Henderson table = cpu->opcodes; 7190624cb07fSRichard Henderson handler = table[opc1(insn)]; 7191624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7192624cb07fSRichard Henderson table = ind_table(handler); 7193624cb07fSRichard Henderson handler = table[opc2(insn)]; 7194624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7195624cb07fSRichard Henderson table = ind_table(handler); 7196624cb07fSRichard Henderson handler = table[opc3(insn)]; 7197624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7198624cb07fSRichard Henderson table = ind_table(handler); 7199624cb07fSRichard Henderson handler = table[opc4(insn)]; 7200624cb07fSRichard Henderson } 7201624cb07fSRichard Henderson } 7202624cb07fSRichard Henderson } 7203624cb07fSRichard Henderson 7204624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7205624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7206624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7207624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7208624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7209624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7210624cb07fSRichard Henderson insn, ctx->cia); 7211624cb07fSRichard Henderson return false; 7212624cb07fSRichard Henderson } 7213624cb07fSRichard Henderson 7214624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7215624cb07fSRichard Henderson && Rc(insn))) { 7216624cb07fSRichard Henderson inval = handler->inval2; 7217624cb07fSRichard Henderson } else { 7218624cb07fSRichard Henderson inval = handler->inval1; 7219624cb07fSRichard Henderson } 7220624cb07fSRichard Henderson 7221624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7222624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7223624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7224624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7225624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7226624cb07fSRichard Henderson insn, ctx->cia); 7227624cb07fSRichard Henderson return false; 7228624cb07fSRichard Henderson } 7229624cb07fSRichard Henderson 7230624cb07fSRichard Henderson handler->handler(ctx); 7231624cb07fSRichard Henderson return true; 7232624cb07fSRichard Henderson } 7233624cb07fSRichard Henderson 7234b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7235fcf5ef2aSThomas Huth { 7236b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 72379c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 72382df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7239fcf5ef2aSThomas Huth 7240b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 72412df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7242d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 72432df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 72442df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7245b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7246b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7247b0c2d521SEmilio G. Cota ctx->access_type = -1; 7248d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 72492df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7250b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 72510e3bf489SRoman Kapl ctx->flags = env->flags; 7252fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72532df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7254b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7255fcf5ef2aSThomas Huth #endif 7256e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7257d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7258fcf5ef2aSThomas Huth 72592df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 72602df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 72612df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 72622df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 72632df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7264f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 72651db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7266f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7267f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 72688b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 72698b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 727046d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 72712df4fe7aSRichard Henderson 7272b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 72732df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 72742df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 72759498d103SRichard Henderson ctx->base.max_insns = 1; 7276efe843d8SDavid Gibson } 72772df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7278b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7279efe843d8SDavid Gibson } 728013b45575SRichard Henderson } 7281fcf5ef2aSThomas Huth 7282b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7283b0c2d521SEmilio G. Cota { 7284b0c2d521SEmilio G. Cota } 7285fcf5ef2aSThomas Huth 7286b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7287b0c2d521SEmilio G. Cota { 7288b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7289b0c2d521SEmilio G. Cota } 7290b0c2d521SEmilio G. Cota 729199082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 729299082815SRichard Henderson { 729399082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 729499082815SRichard Henderson return opc1(insn) == 1; 729599082815SRichard Henderson } 729699082815SRichard Henderson 7297b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7298b0c2d521SEmilio G. Cota { 7299b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 730028876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7301b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 730299082815SRichard Henderson target_ulong pc; 7303624cb07fSRichard Henderson uint32_t insn; 7304624cb07fSRichard Henderson bool ok; 7305b0c2d521SEmilio G. Cota 7306fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7307fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7308b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7309b0c2d521SEmilio G. Cota 731099082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 73114e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 731299082815SRichard Henderson ctx->base.pc_next = pc += 4; 7313fcf5ef2aSThomas Huth 731499082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 731599082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 731699082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 731799082815SRichard Henderson } else if ((pc & 63) == 0) { 731899082815SRichard Henderson /* 731999082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 732099082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 732199082815SRichard Henderson * 64-byte address boundary (system alignment error). 732299082815SRichard Henderson */ 732399082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 732499082815SRichard Henderson ok = true; 732599082815SRichard Henderson } else { 73264e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 73274e116893SIlya Leoshkevich need_byteswap(ctx)); 732899082815SRichard Henderson ctx->base.pc_next = pc += 4; 732999082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 733099082815SRichard Henderson } 7331624cb07fSRichard Henderson if (!ok) { 7332624cb07fSRichard Henderson gen_invalid(ctx); 7333fcf5ef2aSThomas Huth } 7334624cb07fSRichard Henderson 733564a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 733699082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 733764a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 733864a0f644SRichard Henderson } 7339fcf5ef2aSThomas Huth } 7340b0c2d521SEmilio G. Cota 7341b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7342b0c2d521SEmilio G. Cota { 7343b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7344a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7345a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7346b0c2d521SEmilio G. Cota 7347a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7348a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 73493d8a5b69SRichard Henderson return; 73503d8a5b69SRichard Henderson } 73513d8a5b69SRichard Henderson 7352a9b5b3d0SRichard Henderson /* Honor single stepping. */ 73539498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 73549498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7355a9b5b3d0SRichard Henderson switch (is_jmp) { 7356a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7357a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7358a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7359a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7360a9b5b3d0SRichard Henderson break; 7361a9b5b3d0SRichard Henderson case DISAS_EXIT: 7362a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7363a9b5b3d0SRichard Henderson break; 7364a9b5b3d0SRichard Henderson default: 7365a9b5b3d0SRichard Henderson g_assert_not_reached(); 7366fcf5ef2aSThomas Huth } 736713b45575SRichard Henderson 7368a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7369a9b5b3d0SRichard Henderson return; 7370a9b5b3d0SRichard Henderson } 7371a9b5b3d0SRichard Henderson 7372a9b5b3d0SRichard Henderson switch (is_jmp) { 7373a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7374a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 737546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7376a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7377a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7378a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7379a9b5b3d0SRichard Henderson break; 7380a9b5b3d0SRichard Henderson } 7381a9b5b3d0SRichard Henderson /* fall through */ 7382a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7383a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7384a9b5b3d0SRichard Henderson /* fall through */ 7385a9b5b3d0SRichard Henderson case DISAS_CHAIN: 738646d396bdSDaniel Henrique Barboza /* 738746d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 738846d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 738946d396bdSDaniel Henrique Barboza */ 739046d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 739146d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 739246d396bdSDaniel Henrique Barboza } 739346d396bdSDaniel Henrique Barboza 7394a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7395a9b5b3d0SRichard Henderson break; 7396a9b5b3d0SRichard Henderson 7397a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7398a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7399a9b5b3d0SRichard Henderson /* fall through */ 7400a9b5b3d0SRichard Henderson case DISAS_EXIT: 740146d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 740207ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7403a9b5b3d0SRichard Henderson break; 7404a9b5b3d0SRichard Henderson 7405a9b5b3d0SRichard Henderson default: 7406a9b5b3d0SRichard Henderson g_assert_not_reached(); 7407fcf5ef2aSThomas Huth } 7408fcf5ef2aSThomas Huth } 7409b0c2d521SEmilio G. Cota 74108eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 74118eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7412b0c2d521SEmilio G. Cota { 74138eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 74148eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7415b0c2d521SEmilio G. Cota } 7416b0c2d521SEmilio G. Cota 7417b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7418b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7419b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7420b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7421b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7422b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7423b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7424b0c2d521SEmilio G. Cota }; 7425b0c2d521SEmilio G. Cota 7426597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7427306c8721SRichard Henderson target_ulong pc, void *host_pc) 7428b0c2d521SEmilio G. Cota { 7429b0c2d521SEmilio G. Cota DisasContext ctx; 7430b0c2d521SEmilio G. Cota 7431306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7432fcf5ef2aSThomas Huth } 7433