1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39eeaaefe9SLeandro Lupori #include "power8-pmu.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44d53106c9SRichard Henderson #define HELPER_H "helper.h" 45d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 46d53106c9SRichard Henderson #undef HELPER_H 47d53106c9SRichard Henderson 48fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 49fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 50fcf5ef2aSThomas Huth 51fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 52efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 53fcf5ef2aSThomas Huth 54fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56fcf5ef2aSThomas Huth #else 57fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 58fcf5ef2aSThomas Huth #endif 59fcf5ef2aSThomas Huth /*****************************************************************************/ 60fcf5ef2aSThomas Huth /* Code translation helpers */ 61fcf5ef2aSThomas Huth 62fcf5ef2aSThomas Huth /* global register indexes */ 63fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 65fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 66fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 67fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 68fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 69fcf5ef2aSThomas Huth static TCGv cpu_nip; 70fcf5ef2aSThomas Huth static TCGv cpu_msr; 71fcf5ef2aSThomas Huth static TCGv cpu_ctr; 72fcf5ef2aSThomas Huth static TCGv cpu_lr; 73fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 74fcf5ef2aSThomas Huth static TCGv cpu_cfar; 75fcf5ef2aSThomas Huth #endif 76dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77fcf5ef2aSThomas Huth static TCGv cpu_reserve; 78392d328aSNicholas Piggin static TCGv cpu_reserve_length; 79253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 80894448aeSRichard Henderson static TCGv cpu_reserve_val2; 81fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 82fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 83fcf5ef2aSThomas Huth 84fcf5ef2aSThomas Huth void ppc_translate_init(void) 85fcf5ef2aSThomas Huth { 86fcf5ef2aSThomas Huth int i; 87fcf5ef2aSThomas Huth char *p; 88fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth p = cpu_reg_names; 91fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 92fcf5ef2aSThomas Huth 93fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 94fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 95fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 97fcf5ef2aSThomas Huth p += 5; 98fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 99fcf5ef2aSThomas Huth } 100fcf5ef2aSThomas Huth 101fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 103fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 107fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 108fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 110fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 111fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 112fcf5ef2aSThomas Huth } 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 124fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 127fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 128fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 129fcf5ef2aSThomas Huth #endif 130fcf5ef2aSThomas Huth 131fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 133fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 135fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 137fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 138fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 139dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 141dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 142dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 145fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 146fcf5ef2aSThomas Huth "reserve_addr"); 147392d328aSNicholas Piggin cpu_reserve_length = tcg_global_mem_new(cpu_env, 148392d328aSNicholas Piggin offsetof(CPUPPCState, 149392d328aSNicholas Piggin reserve_length), 150392d328aSNicholas Piggin "reserve_length"); 151253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 152253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 153253ce7b2SNikunj A Dadhania "reserve_val"); 154894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 156894448aeSRichard Henderson "reserve_val2"); 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 159fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 160fcf5ef2aSThomas Huth 161fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 163efe843d8SDavid Gibson "access_type"); 164fcf5ef2aSThomas Huth } 165fcf5ef2aSThomas Huth 166fcf5ef2aSThomas Huth /* internal defines */ 167fcf5ef2aSThomas Huth struct DisasContext { 168b6bac4bcSEmilio G. Cota DisasContextBase base; 1692c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 170fcf5ef2aSThomas Huth uint32_t opcode; 171fcf5ef2aSThomas Huth /* Routine used to access memory */ 172fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 173fcf5ef2aSThomas Huth bool lazy_tlb_flush; 174fcf5ef2aSThomas Huth bool need_access_type; 175fcf5ef2aSThomas Huth int mem_idx; 176fcf5ef2aSThomas Huth int access_type; 177fcf5ef2aSThomas Huth /* Translation flags */ 17814776ab5STony Nguyen MemOp default_tcg_memop_mask; 179fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 180fcf5ef2aSThomas Huth bool sf_mode; 181fcf5ef2aSThomas Huth bool has_cfar; 182fcf5ef2aSThomas Huth #endif 183fcf5ef2aSThomas Huth bool fpu_enabled; 184fcf5ef2aSThomas Huth bool altivec_enabled; 185fcf5ef2aSThomas Huth bool vsx_enabled; 186fcf5ef2aSThomas Huth bool spe_enabled; 187fcf5ef2aSThomas Huth bool tm_enabled; 188c6fd28fdSSuraj Jitindar Singh bool gtse; 1891db3632aSMatheus Ferst bool hr; 190f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 191f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1928b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1938b3d1c49SLeandro Lupori bool pmc_other; 19446d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 195fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196fcf5ef2aSThomas Huth int singlestep_enabled; 1970e3bf489SRoman Kapl uint32_t flags; 198fcf5ef2aSThomas Huth uint64_t insns_flags; 199fcf5ef2aSThomas Huth uint64_t insns_flags2; 200fcf5ef2aSThomas Huth }; 201fcf5ef2aSThomas Huth 202a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206a9b5b3d0SRichard Henderson 207fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 208fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 209fcf5ef2aSThomas Huth { 210ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 211fcf5ef2aSThomas Huth return ctx->le_mode; 212fcf5ef2aSThomas Huth #else 213fcf5ef2aSThomas Huth return !ctx->le_mode; 214fcf5ef2aSThomas Huth #endif 215fcf5ef2aSThomas Huth } 216fcf5ef2aSThomas Huth 217fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 218fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 219fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 220fcf5ef2aSThomas Huth #else 221fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 222fcf5ef2aSThomas Huth #endif 223fcf5ef2aSThomas Huth 224fcf5ef2aSThomas Huth struct opc_handler_t { 225fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226fcf5ef2aSThomas Huth uint32_t inval1; 227fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228fcf5ef2aSThomas Huth uint32_t inval2; 229fcf5ef2aSThomas Huth /* instruction type */ 230fcf5ef2aSThomas Huth uint64_t type; 231fcf5ef2aSThomas Huth /* extended instruction type */ 232fcf5ef2aSThomas Huth uint64_t type2; 233fcf5ef2aSThomas Huth /* handler */ 234fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 235fcf5ef2aSThomas Huth }; 236fcf5ef2aSThomas Huth 237b769d4c8SNicholas Piggin static inline bool gen_serialize(DisasContext *ctx) 238b769d4c8SNicholas Piggin { 239b769d4c8SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 240b769d4c8SNicholas Piggin /* Restart with exclusive lock. */ 241b769d4c8SNicholas Piggin gen_helper_exit_atomic(cpu_env); 242b769d4c8SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 243b769d4c8SNicholas Piggin return false; 244b769d4c8SNicholas Piggin } 245b769d4c8SNicholas Piggin return true; 246b769d4c8SNicholas Piggin } 247b769d4c8SNicholas Piggin 248b769d4c8SNicholas Piggin #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 249b769d4c8SNicholas Piggin static inline bool gen_serialize_core(DisasContext *ctx) 250b769d4c8SNicholas Piggin { 251b769d4c8SNicholas Piggin if (ctx->flags & POWERPC_FLAG_SMT) { 252b769d4c8SNicholas Piggin return gen_serialize(ctx); 253b769d4c8SNicholas Piggin } 254b769d4c8SNicholas Piggin 255b769d4c8SNicholas Piggin return true; 256b769d4c8SNicholas Piggin } 257b769d4c8SNicholas Piggin #endif 258b769d4c8SNicholas Piggin 2590e3bf489SRoman Kapl /* SPR load/store helpers */ 2600e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2610e3bf489SRoman Kapl { 2620e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2630e3bf489SRoman Kapl } 2640e3bf489SRoman Kapl 2650e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2660e3bf489SRoman Kapl { 2670e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2680e3bf489SRoman Kapl } 2690e3bf489SRoman Kapl 270fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 271fcf5ef2aSThomas Huth { 272fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 273fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 274fcf5ef2aSThomas Huth ctx->access_type = access_type; 275fcf5ef2aSThomas Huth } 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth 278fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 279fcf5ef2aSThomas Huth { 280fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 281fcf5ef2aSThomas Huth nip = (uint32_t)nip; 282fcf5ef2aSThomas Huth } 283fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 284fcf5ef2aSThomas Huth } 285fcf5ef2aSThomas Huth 286fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 287fcf5ef2aSThomas Huth { 288fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 289fcf5ef2aSThomas Huth 290efe843d8SDavid Gibson /* 291efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 292efe843d8SDavid Gibson * faulting instruction 293fcf5ef2aSThomas Huth */ 2942c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2957058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 2967058ff52SRichard Henderson t1 = tcg_constant_i32(error); 297fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 2983d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 299fcf5ef2aSThomas Huth } 300fcf5ef2aSThomas Huth 301fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 302fcf5ef2aSThomas Huth { 303fcf5ef2aSThomas Huth TCGv_i32 t0; 304fcf5ef2aSThomas Huth 305efe843d8SDavid Gibson /* 306efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 307efe843d8SDavid Gibson * faulting instruction 308fcf5ef2aSThomas Huth */ 3092c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 3107058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 311fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3123d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 313fcf5ef2aSThomas Huth } 314fcf5ef2aSThomas Huth 315fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 316fcf5ef2aSThomas Huth target_ulong nip) 317fcf5ef2aSThomas Huth { 318fcf5ef2aSThomas Huth TCGv_i32 t0; 319fcf5ef2aSThomas Huth 320fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 3217058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 322fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3233d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 324fcf5ef2aSThomas Huth } 325fcf5ef2aSThomas Huth 3262fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3272fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3282fdedcbcSMatheus Ferst { 329283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 3302fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3312fdedcbcSMatheus Ferst } 3322fdedcbcSMatheus Ferst #endif 3332fdedcbcSMatheus Ferst 334e150ac89SRoman Kapl /* 335e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 336e150ac89SRoman Kapl * SPR registers for this exception. 337e150ac89SRoman Kapl * 338e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 339e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3400e3bf489SRoman Kapl */ 341e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3420e3bf489SRoman Kapl { 3430e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3440e3bf489SRoman Kapl target_ulong dbsr = 0; 345e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3460e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 347e150ac89SRoman Kapl } else { 348e150ac89SRoman Kapl /* Must have been branch */ 3490e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3500e3bf489SRoman Kapl } 3510e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3520e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3530e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3540e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3550e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3560e3bf489SRoman Kapl } else { 357e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3580e3bf489SRoman Kapl } 3590e3bf489SRoman Kapl } 3600e3bf489SRoman Kapl 361fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 362fcf5ef2aSThomas Huth { 3639498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3643d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 365fcf5ef2aSThomas Huth } 366fcf5ef2aSThomas Huth 367fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 368fcf5ef2aSThomas Huth { 369fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 370fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 371fcf5ef2aSThomas Huth } 372fcf5ef2aSThomas Huth 373fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 374fcf5ef2aSThomas Huth { 375fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 376fcf5ef2aSThomas Huth } 377fcf5ef2aSThomas Huth 378fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 379fcf5ef2aSThomas Huth { 380fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 381fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 382fcf5ef2aSThomas Huth } 383fcf5ef2aSThomas Huth 38437f219c8SBruno Larsen (billionai) /*****************************************************************************/ 38537f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 38637f219c8SBruno Larsen (billionai) 387a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 38837f219c8SBruno Larsen (billionai) { 38937f219c8SBruno Larsen (billionai) #if 0 39037f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 39137f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 39237f219c8SBruno Larsen (billionai) #endif 39337f219c8SBruno Larsen (billionai) } 39437f219c8SBruno Larsen (billionai) 39537f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 39637f219c8SBruno Larsen (billionai) 39737f219c8SBruno Larsen (billionai) /* 39837f219c8SBruno Larsen (billionai) * Generic callbacks: 39937f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 40037f219c8SBruno Larsen (billionai) */ 40137f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 40237f219c8SBruno Larsen (billionai) { 40337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4047058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 40537f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 40637f219c8SBruno Larsen (billionai) #endif 40737f219c8SBruno Larsen (billionai) } 40837f219c8SBruno Larsen (billionai) 409a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 41037f219c8SBruno Larsen (billionai) { 41137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 41237f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 41337f219c8SBruno Larsen (billionai) } 41437f219c8SBruno Larsen (billionai) 41537f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 41637f219c8SBruno Larsen (billionai) { 41737f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4187058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 41937f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 42037f219c8SBruno Larsen (billionai) #endif 42137f219c8SBruno Larsen (billionai) } 42237f219c8SBruno Larsen (billionai) 423a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 42437f219c8SBruno Larsen (billionai) { 42537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 42637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42737f219c8SBruno Larsen (billionai) } 42837f219c8SBruno Larsen (billionai) 429a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43037f219c8SBruno Larsen (billionai) { 43137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43537f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43637f219c8SBruno Larsen (billionai) #else 43737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43837f219c8SBruno Larsen (billionai) #endif 43937f219c8SBruno Larsen (billionai) } 44037f219c8SBruno Larsen (billionai) 441c5d98a7bSNicholas Piggin static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 442fbda88f7SNicholas Piggin { 443488aad11SNicholas Piggin /* This does not implement >1 thread */ 444488aad11SNicholas Piggin TCGv t0 = tcg_temp_new(); 445488aad11SNicholas Piggin TCGv t1 = tcg_temp_new(); 446488aad11SNicholas Piggin tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 447488aad11SNicholas Piggin tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 448488aad11SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 449488aad11SNicholas Piggin gen_store_spr(sprn, t1); 450c5d98a7bSNicholas Piggin } 451c5d98a7bSNicholas Piggin 452c5d98a7bSNicholas Piggin void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 453c5d98a7bSNicholas Piggin { 454c5d98a7bSNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT)) { 455c5d98a7bSNicholas Piggin spr_write_CTRL_ST(ctx, sprn, gprn); 456c5d98a7bSNicholas Piggin goto out; 457c5d98a7bSNicholas Piggin } 458c5d98a7bSNicholas Piggin 459c5d98a7bSNicholas Piggin if (!gen_serialize(ctx)) { 460c5d98a7bSNicholas Piggin return; 461c5d98a7bSNicholas Piggin } 462c5d98a7bSNicholas Piggin 463c5d98a7bSNicholas Piggin gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 464c5d98a7bSNicholas Piggin cpu_gpr[gprn]); 465c5d98a7bSNicholas Piggin out: 466488aad11SNicholas Piggin spr_store_dump_spr(sprn); 467fbda88f7SNicholas Piggin 468fbda88f7SNicholas Piggin /* 469fbda88f7SNicholas Piggin * SPR_CTRL writes must force a new translation block, 470fbda88f7SNicholas Piggin * allowing the PMU to calculate the run latch events with 471fbda88f7SNicholas Piggin * more accuracy. 472fbda88f7SNicholas Piggin */ 473fbda88f7SNicholas Piggin ctx->base.is_jmp = DISAS_EXIT_UPDATE; 474fbda88f7SNicholas Piggin } 475fbda88f7SNicholas Piggin 476fbda88f7SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 477a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 47837f219c8SBruno Larsen (billionai) { 47937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 48037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 48137f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 48237f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 48337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 48437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 48537f219c8SBruno Larsen (billionai) } 48637f219c8SBruno Larsen (billionai) 487a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 48837f219c8SBruno Larsen (billionai) { 48937f219c8SBruno Larsen (billionai) } 49037f219c8SBruno Larsen (billionai) 49137f219c8SBruno Larsen (billionai) #endif 49237f219c8SBruno Larsen (billionai) 49337f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 49437f219c8SBruno Larsen (billionai) /* XER */ 495a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 49637f219c8SBruno Larsen (billionai) { 49737f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 49837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 49937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 50037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 50137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 50237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 50337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 50437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 50537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 50637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 50737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 50837f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 50937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 51037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 51137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 51237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 51337f219c8SBruno Larsen (billionai) } 51437f219c8SBruno Larsen (billionai) } 51537f219c8SBruno Larsen (billionai) 516a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 51737f219c8SBruno Larsen (billionai) { 51837f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 51937f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 52037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 52137f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 52237f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 52337f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 52437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 52537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 52637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 52737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 52837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 52937f219c8SBruno Larsen (billionai) } 53037f219c8SBruno Larsen (billionai) 53137f219c8SBruno Larsen (billionai) /* LR */ 532a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 53337f219c8SBruno Larsen (billionai) { 53437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 53537f219c8SBruno Larsen (billionai) } 53637f219c8SBruno Larsen (billionai) 537a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 53837f219c8SBruno Larsen (billionai) { 53937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 54037f219c8SBruno Larsen (billionai) } 54137f219c8SBruno Larsen (billionai) 54237f219c8SBruno Larsen (billionai) /* CFAR */ 54337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 544a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 54537f219c8SBruno Larsen (billionai) { 54637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 54737f219c8SBruno Larsen (billionai) } 54837f219c8SBruno Larsen (billionai) 549a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 55037f219c8SBruno Larsen (billionai) { 55137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 55237f219c8SBruno Larsen (billionai) } 55337f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 55437f219c8SBruno Larsen (billionai) 55537f219c8SBruno Larsen (billionai) /* CTR */ 556a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 55737f219c8SBruno Larsen (billionai) { 55837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 55937f219c8SBruno Larsen (billionai) } 56037f219c8SBruno Larsen (billionai) 561a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 56237f219c8SBruno Larsen (billionai) { 56337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 56437f219c8SBruno Larsen (billionai) } 56537f219c8SBruno Larsen (billionai) 56637f219c8SBruno Larsen (billionai) /* User read access to SPR */ 56737f219c8SBruno Larsen (billionai) /* USPRx */ 56837f219c8SBruno Larsen (billionai) /* UMMCRx */ 56937f219c8SBruno Larsen (billionai) /* UPMCx */ 57037f219c8SBruno Larsen (billionai) /* USIA */ 57137f219c8SBruno Larsen (billionai) /* UDECR */ 572a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 57337f219c8SBruno Larsen (billionai) { 57437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 57537f219c8SBruno Larsen (billionai) } 57637f219c8SBruno Larsen (billionai) 57737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 578a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 57937f219c8SBruno Larsen (billionai) { 58037f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 58137f219c8SBruno Larsen (billionai) } 58237f219c8SBruno Larsen (billionai) #endif 58337f219c8SBruno Larsen (billionai) 58437f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 58537f219c8SBruno Larsen (billionai) /* DECR */ 58637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 587a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 58837f219c8SBruno Larsen (billionai) { 589283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 59037f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 59137f219c8SBruno Larsen (billionai) } 59237f219c8SBruno Larsen (billionai) 593a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 59437f219c8SBruno Larsen (billionai) { 595283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 59637f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 59737f219c8SBruno Larsen (billionai) } 59837f219c8SBruno Larsen (billionai) #endif 59937f219c8SBruno Larsen (billionai) 60037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 60137f219c8SBruno Larsen (billionai) /* Time base */ 602a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 60337f219c8SBruno Larsen (billionai) { 604283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 60537f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 60637f219c8SBruno Larsen (billionai) } 60737f219c8SBruno Larsen (billionai) 608a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 60937f219c8SBruno Larsen (billionai) { 610283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 61137f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 61237f219c8SBruno Larsen (billionai) } 61337f219c8SBruno Larsen (billionai) 614a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 61537f219c8SBruno Larsen (billionai) { 61637f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 61737f219c8SBruno Larsen (billionai) } 61837f219c8SBruno Larsen (billionai) 619a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 62037f219c8SBruno Larsen (billionai) { 62137f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 62237f219c8SBruno Larsen (billionai) } 62337f219c8SBruno Larsen (billionai) 62437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 625a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 62637f219c8SBruno Larsen (billionai) { 627283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 62837f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 62937f219c8SBruno Larsen (billionai) } 63037f219c8SBruno Larsen (billionai) 631a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 63237f219c8SBruno Larsen (billionai) { 633283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 63437f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 63537f219c8SBruno Larsen (billionai) } 63637f219c8SBruno Larsen (billionai) 637a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 63837f219c8SBruno Larsen (billionai) { 63937f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 64037f219c8SBruno Larsen (billionai) } 64137f219c8SBruno Larsen (billionai) 642a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 64337f219c8SBruno Larsen (billionai) { 64437f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 64537f219c8SBruno Larsen (billionai) } 64637f219c8SBruno Larsen (billionai) 64737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 648a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 64937f219c8SBruno Larsen (billionai) { 650283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65137f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 65237f219c8SBruno Larsen (billionai) } 65337f219c8SBruno Larsen (billionai) 654a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 65537f219c8SBruno Larsen (billionai) { 656283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65737f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 65837f219c8SBruno Larsen (billionai) } 65937f219c8SBruno Larsen (billionai) 66037f219c8SBruno Larsen (billionai) /* HDECR */ 661a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 66237f219c8SBruno Larsen (billionai) { 663283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 66437f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 66537f219c8SBruno Larsen (billionai) } 66637f219c8SBruno Larsen (billionai) 667a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 66837f219c8SBruno Larsen (billionai) { 669283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67037f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 67137f219c8SBruno Larsen (billionai) } 67237f219c8SBruno Larsen (billionai) 673a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 67437f219c8SBruno Larsen (billionai) { 675283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67637f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 67737f219c8SBruno Larsen (billionai) } 67837f219c8SBruno Larsen (billionai) 679a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 68037f219c8SBruno Larsen (billionai) { 681283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 68237f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 685a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 68637f219c8SBruno Larsen (billionai) { 687283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 68837f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 68937f219c8SBruno Larsen (billionai) } 69037f219c8SBruno Larsen (billionai) 69137f219c8SBruno Larsen (billionai) #endif 69237f219c8SBruno Larsen (billionai) #endif 69337f219c8SBruno Larsen (billionai) 69437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 69537f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 69637f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 697a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 69837f219c8SBruno Larsen (billionai) { 69937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 70237f219c8SBruno Larsen (billionai) } 70337f219c8SBruno Larsen (billionai) 704a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 70537f219c8SBruno Larsen (billionai) { 70637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70837f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 70937f219c8SBruno Larsen (billionai) } 71037f219c8SBruno Larsen (billionai) 711a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 71237f219c8SBruno Larsen (billionai) { 7137058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 71437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 71537f219c8SBruno Larsen (billionai) } 71637f219c8SBruno Larsen (billionai) 717a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 71837f219c8SBruno Larsen (billionai) { 7197058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 72037f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 72137f219c8SBruno Larsen (billionai) } 72237f219c8SBruno Larsen (billionai) 723a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 72437f219c8SBruno Larsen (billionai) { 7257058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 72637f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 729a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 73037f219c8SBruno Larsen (billionai) { 7317058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 73237f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) } 73437f219c8SBruno Larsen (billionai) 73537f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 73637f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 737a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 73837f219c8SBruno Larsen (billionai) { 73937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74137f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 74237f219c8SBruno Larsen (billionai) } 74337f219c8SBruno Larsen (billionai) 744a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74837f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 74937f219c8SBruno Larsen (billionai) } 75037f219c8SBruno Larsen (billionai) 751a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 75237f219c8SBruno Larsen (billionai) { 7537058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 75437f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 75537f219c8SBruno Larsen (billionai) } 75637f219c8SBruno Larsen (billionai) 757a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 75837f219c8SBruno Larsen (billionai) { 7597058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 76037f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 76137f219c8SBruno Larsen (billionai) } 76237f219c8SBruno Larsen (billionai) 763a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 76437f219c8SBruno Larsen (billionai) { 7657058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 76637f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 76737f219c8SBruno Larsen (billionai) } 76837f219c8SBruno Larsen (billionai) 769a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 77037f219c8SBruno Larsen (billionai) { 7717058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 77237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 77337f219c8SBruno Larsen (billionai) } 77437f219c8SBruno Larsen (billionai) 77537f219c8SBruno Larsen (billionai) /* SDR1 */ 776a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 77737f219c8SBruno Larsen (billionai) { 77837f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 77937f219c8SBruno Larsen (billionai) } 78037f219c8SBruno Larsen (billionai) 78137f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 78237f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 78337f219c8SBruno Larsen (billionai) /* PIDR */ 784a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 78537f219c8SBruno Larsen (billionai) { 78637f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 78737f219c8SBruno Larsen (billionai) } 78837f219c8SBruno Larsen (billionai) 789a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 79037f219c8SBruno Larsen (billionai) { 79137f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 79237f219c8SBruno Larsen (billionai) } 79337f219c8SBruno Larsen (billionai) 794a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 79537f219c8SBruno Larsen (billionai) { 79637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 79737f219c8SBruno Larsen (billionai) } 79837f219c8SBruno Larsen (billionai) 799a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 80037f219c8SBruno Larsen (billionai) { 80137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 80237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 80337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 80437f219c8SBruno Larsen (billionai) } 805a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 80637f219c8SBruno Larsen (billionai) { 80737f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 80837f219c8SBruno Larsen (billionai) } 80937f219c8SBruno Larsen (billionai) 810a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 81137f219c8SBruno Larsen (billionai) { 81237f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 81337f219c8SBruno Larsen (billionai) } 81437f219c8SBruno Larsen (billionai) 81537f219c8SBruno Larsen (billionai) /* DPDES */ 816a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 81737f219c8SBruno Larsen (billionai) { 818d24e80b2SNicholas Piggin if (!gen_serialize_core(ctx)) { 819d24e80b2SNicholas Piggin return; 820d24e80b2SNicholas Piggin } 821d24e80b2SNicholas Piggin 82237f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 82337f219c8SBruno Larsen (billionai) } 82437f219c8SBruno Larsen (billionai) 825a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 82637f219c8SBruno Larsen (billionai) { 827d24e80b2SNicholas Piggin if (!gen_serialize_core(ctx)) { 828d24e80b2SNicholas Piggin return; 829d24e80b2SNicholas Piggin } 830d24e80b2SNicholas Piggin 83137f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 83237f219c8SBruno Larsen (billionai) } 83337f219c8SBruno Larsen (billionai) #endif 83437f219c8SBruno Larsen (billionai) #endif 83537f219c8SBruno Larsen (billionai) 83637f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 83737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 838a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 83937f219c8SBruno Larsen (billionai) { 840283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 84137f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84237f219c8SBruno Larsen (billionai) } 84337f219c8SBruno Larsen (billionai) 844a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84537f219c8SBruno Larsen (billionai) { 846283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 84737f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 84837f219c8SBruno Larsen (billionai) } 84937f219c8SBruno Larsen (billionai) 850a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85137f219c8SBruno Larsen (billionai) { 852283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 85337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85437f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85537f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 856d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 85737f219c8SBruno Larsen (billionai) } 85837f219c8SBruno Larsen (billionai) 859a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86037f219c8SBruno Larsen (billionai) { 861283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 86237f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86337f219c8SBruno Larsen (billionai) } 86437f219c8SBruno Larsen (billionai) 865cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 866cbd8f17dSCédric Le Goater { 867283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 868cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 869cbd8f17dSCédric Le Goater } 870cbd8f17dSCédric Le Goater 871cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 872cbd8f17dSCédric Le Goater { 873283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 874cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 875cbd8f17dSCédric Le Goater } 876cbd8f17dSCédric Le Goater 877dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 878dd69d140SCédric Le Goater { 879dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 880dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 88147822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 882dd69d140SCédric Le Goater } 883dd69d140SCédric Le Goater 884a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 88537f219c8SBruno Larsen (billionai) { 886283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 88737f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 88837f219c8SBruno Larsen (billionai) } 88937f219c8SBruno Larsen (billionai) 890a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 89137f219c8SBruno Larsen (billionai) { 892283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 89337f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 89437f219c8SBruno Larsen (billionai) } 89537f219c8SBruno Larsen (billionai) #endif 89637f219c8SBruno Larsen (billionai) 897328c95fcSCédric Le Goater /* PIR */ 89837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 899a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 90037f219c8SBruno Larsen (billionai) { 90137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90437f219c8SBruno Larsen (billionai) } 90537f219c8SBruno Larsen (billionai) #endif 90637f219c8SBruno Larsen (billionai) 90737f219c8SBruno Larsen (billionai) /* SPE specific registers */ 908a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 90937f219c8SBruno Larsen (billionai) { 91037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91137f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91237f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91337f219c8SBruno Larsen (billionai) } 91437f219c8SBruno Larsen (billionai) 915a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91637f219c8SBruno Larsen (billionai) { 91737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91837f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 91937f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92037f219c8SBruno Larsen (billionai) } 92137f219c8SBruno Larsen (billionai) 92237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92337f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 924a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92537f219c8SBruno Larsen (billionai) { 92637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 92837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 92937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93137f219c8SBruno Larsen (billionai) } 93237f219c8SBruno Larsen (billionai) 933a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93437f219c8SBruno Larsen (billionai) { 93537f219c8SBruno Larsen (billionai) int sprn_offs; 93637f219c8SBruno Larsen (billionai) 93737f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 93837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 93937f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94037f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94137f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94237f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94337f219c8SBruno Larsen (billionai) } else { 9448e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9458e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9468e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 94737f219c8SBruno Larsen (billionai) return; 94837f219c8SBruno Larsen (billionai) } 94937f219c8SBruno Larsen (billionai) 95037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95537f219c8SBruno Larsen (billionai) } 95637f219c8SBruno Larsen (billionai) #endif 95737f219c8SBruno Larsen (billionai) 95837f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 95937f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 960a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96137f219c8SBruno Larsen (billionai) { 96237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96337f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96437f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96537f219c8SBruno Larsen (billionai) 96637f219c8SBruno Larsen (billionai) /* 96737f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 96837f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 96937f219c8SBruno Larsen (billionai) */ 97037f219c8SBruno Larsen (billionai) 97137f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97237f219c8SBruno Larsen (billionai) if (ctx->pr) { 97337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97437f219c8SBruno Larsen (billionai) } else { 97537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97637f219c8SBruno Larsen (billionai) } 97737f219c8SBruno Larsen (billionai) 97837f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 97937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98037f219c8SBruno Larsen (billionai) 98137f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98237f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98337f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98437f219c8SBruno Larsen (billionai) 98537f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 98737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 98837f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 98937f219c8SBruno Larsen (billionai) } 99037f219c8SBruno Larsen (billionai) 991a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 99237f219c8SBruno Larsen (billionai) { 99337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 99437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 99537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 99637f219c8SBruno Larsen (billionai) 99737f219c8SBruno Larsen (billionai) /* 99837f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 99937f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100037f219c8SBruno Larsen (billionai) */ 100137f219c8SBruno Larsen (billionai) 100237f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 100437f219c8SBruno Larsen (billionai) 100537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 100637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 100737f219c8SBruno Larsen (billionai) 100837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 100937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101137f219c8SBruno Larsen (billionai) 101237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 101437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 101537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 101637f219c8SBruno Larsen (billionai) } 101737f219c8SBruno Larsen (billionai) 1018a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 101937f219c8SBruno Larsen (billionai) { 102037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 102137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 102237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 102337f219c8SBruno Larsen (billionai) 102437f219c8SBruno Larsen (billionai) /* 102537f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 102637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 102737f219c8SBruno Larsen (billionai) */ 102837f219c8SBruno Larsen (billionai) 102937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 103037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 103137f219c8SBruno Larsen (billionai) 103237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 103337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 103437f219c8SBruno Larsen (billionai) 103537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 103637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 103737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 103837f219c8SBruno Larsen (billionai) 103937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 104037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 104137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 104237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 104337f219c8SBruno Larsen (billionai) } 104437f219c8SBruno Larsen (billionai) #endif 104537f219c8SBruno Larsen (billionai) #endif 104637f219c8SBruno Larsen (billionai) 104737f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1048a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 104937f219c8SBruno Larsen (billionai) { 105037f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 105137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 105237f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 105337f219c8SBruno Larsen (billionai) } 105437f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 105537f219c8SBruno Larsen (billionai) 105637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1057a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 105837f219c8SBruno Larsen (billionai) { 105937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106037f219c8SBruno Larsen (billionai) 106137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 106237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 106337f219c8SBruno Larsen (billionai) } 106437f219c8SBruno Larsen (billionai) 1065a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 106637f219c8SBruno Larsen (billionai) { 106737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106837f219c8SBruno Larsen (billionai) 106937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 107037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107137f219c8SBruno Larsen (billionai) } 107237f219c8SBruno Larsen (billionai) 1073a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 107437f219c8SBruno Larsen (billionai) { 107537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107637f219c8SBruno Larsen (billionai) 107737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 107837f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 107937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108037f219c8SBruno Larsen (billionai) } 108137f219c8SBruno Larsen (billionai) 1082a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 108337f219c8SBruno Larsen (billionai) { 108437f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 108537f219c8SBruno Larsen (billionai) } 108637f219c8SBruno Larsen (billionai) 1087a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 108837f219c8SBruno Larsen (billionai) { 10897058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 109037f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 109137f219c8SBruno Larsen (billionai) } 10927058ff52SRichard Henderson 1093a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 109437f219c8SBruno Larsen (billionai) { 109537f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 109637f219c8SBruno Larsen (billionai) } 10977058ff52SRichard Henderson 1098a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 109937f219c8SBruno Larsen (billionai) { 110037f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 110137f219c8SBruno Larsen (billionai) } 110237f219c8SBruno Larsen (billionai) 110337f219c8SBruno Larsen (billionai) #endif 110437f219c8SBruno Larsen (billionai) 110537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1106a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 110737f219c8SBruno Larsen (billionai) { 110837f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 110937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 111037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 111137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 111237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 111337f219c8SBruno Larsen (billionai) } 111437f219c8SBruno Larsen (billionai) 1115a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 111637f219c8SBruno Larsen (billionai) { 111737f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 111837f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 111937f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 112037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 112137f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 112237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 112337f219c8SBruno Larsen (billionai) } 112437f219c8SBruno Larsen (billionai) 112537f219c8SBruno Larsen (billionai) #endif 112637f219c8SBruno Larsen (billionai) 112737f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 112837f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 112937f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 113037f219c8SBruno Larsen (billionai) { 11317058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11327058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11337058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 113437f219c8SBruno Larsen (billionai) 113537f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 113637f219c8SBruno Larsen (billionai) } 113737f219c8SBruno Larsen (billionai) 113837f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 113937f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114037f219c8SBruno Larsen (billionai) { 11417058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11427058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11437058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 114437f219c8SBruno Larsen (billionai) 114537f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 114637f219c8SBruno Larsen (billionai) } 114737f219c8SBruno Larsen (billionai) 1148a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 114937f219c8SBruno Larsen (billionai) { 115037f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 115137f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 115237f219c8SBruno Larsen (billionai) 115337f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 115437f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 115537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 115637f219c8SBruno Larsen (billionai) } 115737f219c8SBruno Larsen (billionai) 1158a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 115937f219c8SBruno Larsen (billionai) { 116037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 116137f219c8SBruno Larsen (billionai) 116237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 116337f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 116437f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 116537f219c8SBruno Larsen (billionai) } 116637f219c8SBruno Larsen (billionai) 116737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1168a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 116937f219c8SBruno Larsen (billionai) { 117037f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 117137f219c8SBruno Larsen (billionai) 117237f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 117337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 117437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 117537f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 117637f219c8SBruno Larsen (billionai) } 117737f219c8SBruno Larsen (billionai) 1178*b25f2ffaSNicholas Piggin void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1179*b25f2ffaSNicholas Piggin { 1180*b25f2ffaSNicholas Piggin gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1181*b25f2ffaSNicholas Piggin } 1182*b25f2ffaSNicholas Piggin 1183*b25f2ffaSNicholas Piggin void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1184*b25f2ffaSNicholas Piggin { 1185*b25f2ffaSNicholas Piggin gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1186*b25f2ffaSNicholas Piggin } 1187*b25f2ffaSNicholas Piggin 1188a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 118937f219c8SBruno Larsen (billionai) { 119037f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 119137f219c8SBruno Larsen (billionai) } 119237f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 119337f219c8SBruno Larsen (billionai) 1194a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 119537f219c8SBruno Larsen (billionai) { 119637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 119737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 119837f219c8SBruno Larsen (billionai) } 119937f219c8SBruno Larsen (billionai) 1200a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 120137f219c8SBruno Larsen (billionai) { 120237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 120337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 120437f219c8SBruno Larsen (billionai) } 120537f219c8SBruno Larsen (billionai) 1206a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 120737f219c8SBruno Larsen (billionai) { 120837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 120937f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 121037f219c8SBruno Larsen (billionai) } 121137f219c8SBruno Larsen (billionai) 1212a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 121337f219c8SBruno Larsen (billionai) { 121437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 121637f219c8SBruno Larsen (billionai) } 121737f219c8SBruno Larsen (billionai) 1218a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 121937f219c8SBruno Larsen (billionai) { 122037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122137f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 122237f219c8SBruno Larsen (billionai) } 122337f219c8SBruno Larsen (billionai) 1224a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 122537f219c8SBruno Larsen (billionai) { 122637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122737f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 122837f219c8SBruno Larsen (billionai) } 122937f219c8SBruno Larsen (billionai) 1230a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 123137f219c8SBruno Larsen (billionai) { 123237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123437f219c8SBruno Larsen (billionai) } 123537f219c8SBruno Larsen (billionai) 1236a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 123737f219c8SBruno Larsen (billionai) { 123837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124037f219c8SBruno Larsen (billionai) } 124137f219c8SBruno Larsen (billionai) 1242a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 124337f219c8SBruno Larsen (billionai) { 124437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124537f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124637f219c8SBruno Larsen (billionai) } 124737f219c8SBruno Larsen (billionai) 1248a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 124937f219c8SBruno Larsen (billionai) { 125037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125137f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125237f219c8SBruno Larsen (billionai) } 1253395b5d5bSNicholas Miehlbradt 1254395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1255395b5d5bSNicholas Miehlbradt { 1256395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1257395b5d5bSNicholas Miehlbradt 1258395b5d5bSNicholas Miehlbradt /* 1259395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1260395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1261395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1262395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1263395b5d5bSNicholas Miehlbradt * 1264395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1265395b5d5bSNicholas Miehlbradt */ 1266395b5d5bSNicholas Miehlbradt 1267395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1268395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1269395b5d5bSNicholas Miehlbradt } 127037f219c8SBruno Larsen (billionai) #endif 127137f219c8SBruno Larsen (billionai) 1272fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1273fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1274fcf5ef2aSThomas Huth 1275fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1276fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1277fcf5ef2aSThomas Huth 1278fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1279fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1280fcf5ef2aSThomas Huth 1281fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1282fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1283fcf5ef2aSThomas Huth 1284fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1285fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1286fcf5ef2aSThomas Huth 1287fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1288fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1289fcf5ef2aSThomas Huth 1290fcf5ef2aSThomas Huth typedef struct opcode_t { 1291fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1292fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1293fcf5ef2aSThomas Huth unsigned char pad[4]; 1294fcf5ef2aSThomas Huth #endif 1295fcf5ef2aSThomas Huth opc_handler_t handler; 1296fcf5ef2aSThomas Huth const char *oname; 1297fcf5ef2aSThomas Huth } opcode_t; 1298fcf5ef2aSThomas Huth 12999f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 13009f0cf041SMatheus Ferst { 13019f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 13029f0cf041SMatheus Ferst } 13039f0cf041SMatheus Ferst 1304fcf5ef2aSThomas Huth /* Helpers for priv. check */ 13059f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1306fcf5ef2aSThomas Huth do { \ 13079f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1308fcf5ef2aSThomas Huth } while (0) 1309fcf5ef2aSThomas Huth 1310fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 13119f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 13129f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 13139f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1314fcf5ef2aSThomas Huth #else 13159f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1316fcf5ef2aSThomas Huth do { \ 1317fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 13189f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1319fcf5ef2aSThomas Huth } \ 1320fcf5ef2aSThomas Huth } while (0) 13219f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1322fcf5ef2aSThomas Huth do { \ 1323fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13249f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1325fcf5ef2aSThomas Huth } \ 1326fcf5ef2aSThomas Huth } while (0) 13279f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1328fcf5ef2aSThomas Huth do { \ 1329fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13309f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1331fcf5ef2aSThomas Huth } \ 1332fcf5ef2aSThomas Huth } while (0) 1333fcf5ef2aSThomas Huth #endif 1334fcf5ef2aSThomas Huth 13359f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1336fcf5ef2aSThomas Huth 1337fcf5ef2aSThomas Huth /*****************************************************************************/ 1338fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1339fcf5ef2aSThomas Huth 1340fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1341fcf5ef2aSThomas Huth { \ 1342fcf5ef2aSThomas Huth .opc1 = op1, \ 1343fcf5ef2aSThomas Huth .opc2 = op2, \ 1344fcf5ef2aSThomas Huth .opc3 = op3, \ 1345fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1346fcf5ef2aSThomas Huth .handler = { \ 1347fcf5ef2aSThomas Huth .inval1 = invl, \ 1348fcf5ef2aSThomas Huth .type = _typ, \ 1349fcf5ef2aSThomas Huth .type2 = _typ2, \ 1350fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1351fcf5ef2aSThomas Huth }, \ 1352fcf5ef2aSThomas Huth .oname = stringify(name), \ 1353fcf5ef2aSThomas Huth } 1354fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1355fcf5ef2aSThomas Huth { \ 1356fcf5ef2aSThomas Huth .opc1 = op1, \ 1357fcf5ef2aSThomas Huth .opc2 = op2, \ 1358fcf5ef2aSThomas Huth .opc3 = op3, \ 1359fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1360fcf5ef2aSThomas Huth .handler = { \ 1361fcf5ef2aSThomas Huth .inval1 = invl1, \ 1362fcf5ef2aSThomas Huth .inval2 = invl2, \ 1363fcf5ef2aSThomas Huth .type = _typ, \ 1364fcf5ef2aSThomas Huth .type2 = _typ2, \ 1365fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1366fcf5ef2aSThomas Huth }, \ 1367fcf5ef2aSThomas Huth .oname = stringify(name), \ 1368fcf5ef2aSThomas Huth } 1369fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1370fcf5ef2aSThomas Huth { \ 1371fcf5ef2aSThomas Huth .opc1 = op1, \ 1372fcf5ef2aSThomas Huth .opc2 = op2, \ 1373fcf5ef2aSThomas Huth .opc3 = op3, \ 1374fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1375fcf5ef2aSThomas Huth .handler = { \ 1376fcf5ef2aSThomas Huth .inval1 = invl, \ 1377fcf5ef2aSThomas Huth .type = _typ, \ 1378fcf5ef2aSThomas Huth .type2 = _typ2, \ 1379fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1380fcf5ef2aSThomas Huth }, \ 1381fcf5ef2aSThomas Huth .oname = onam, \ 1382fcf5ef2aSThomas Huth } 1383fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1384fcf5ef2aSThomas Huth { \ 1385fcf5ef2aSThomas Huth .opc1 = op1, \ 1386fcf5ef2aSThomas Huth .opc2 = op2, \ 1387fcf5ef2aSThomas Huth .opc3 = op3, \ 1388fcf5ef2aSThomas Huth .opc4 = op4, \ 1389fcf5ef2aSThomas Huth .handler = { \ 1390fcf5ef2aSThomas Huth .inval1 = invl, \ 1391fcf5ef2aSThomas Huth .type = _typ, \ 1392fcf5ef2aSThomas Huth .type2 = _typ2, \ 1393fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1394fcf5ef2aSThomas Huth }, \ 1395fcf5ef2aSThomas Huth .oname = stringify(name), \ 1396fcf5ef2aSThomas Huth } 1397fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1398fcf5ef2aSThomas Huth { \ 1399fcf5ef2aSThomas Huth .opc1 = op1, \ 1400fcf5ef2aSThomas Huth .opc2 = op2, \ 1401fcf5ef2aSThomas Huth .opc3 = op3, \ 1402fcf5ef2aSThomas Huth .opc4 = op4, \ 1403fcf5ef2aSThomas Huth .handler = { \ 1404fcf5ef2aSThomas Huth .inval1 = invl, \ 1405fcf5ef2aSThomas Huth .type = _typ, \ 1406fcf5ef2aSThomas Huth .type2 = _typ2, \ 1407fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1408fcf5ef2aSThomas Huth }, \ 1409fcf5ef2aSThomas Huth .oname = onam, \ 1410fcf5ef2aSThomas Huth } 1411fcf5ef2aSThomas Huth 1412fcf5ef2aSThomas Huth /* Invalid instruction */ 1413fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1414fcf5ef2aSThomas Huth { 1415fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1416fcf5ef2aSThomas Huth } 1417fcf5ef2aSThomas Huth 1418fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1419fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1420fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1421fcf5ef2aSThomas Huth .type = PPC_NONE, 1422fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1423fcf5ef2aSThomas Huth .handler = gen_invalid, 1424fcf5ef2aSThomas Huth }; 1425fcf5ef2aSThomas Huth 1426fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1427fcf5ef2aSThomas Huth 1428fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1429fcf5ef2aSThomas Huth { 1430fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1431b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1432b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1433fcf5ef2aSThomas Huth 1434b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1435b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1436efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1437efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1438b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1439efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1440efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1441b62b3686Spbonzini@redhat.com 1442b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1443fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1444b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1445fcf5ef2aSThomas Huth } 1446fcf5ef2aSThomas Huth 1447fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1448fcf5ef2aSThomas Huth { 14497058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1450fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1451fcf5ef2aSThomas Huth } 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1454fcf5ef2aSThomas Huth { 1455fcf5ef2aSThomas Huth TCGv t0, t1; 1456fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1457fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1458fcf5ef2aSThomas Huth if (s) { 1459fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1460fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1461fcf5ef2aSThomas Huth } else { 1462fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1463fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1464fcf5ef2aSThomas Huth } 1465fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1466fcf5ef2aSThomas Huth } 1467fcf5ef2aSThomas Huth 1468fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1469fcf5ef2aSThomas Huth { 14707058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1471fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1472fcf5ef2aSThomas Huth } 1473fcf5ef2aSThomas Huth 1474fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1475fcf5ef2aSThomas Huth { 1476fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1477fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1478fcf5ef2aSThomas Huth } else { 1479fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1480fcf5ef2aSThomas Huth } 1481fcf5ef2aSThomas Huth } 1482fcf5ef2aSThomas Huth 1483fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1484fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1485fcf5ef2aSThomas Huth { 1486fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1487fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1488fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1489fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1490fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1491fcf5ef2aSThomas Huth 1492fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1493fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1494fcf5ef2aSThomas Huth 1495fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1496fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1497fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1498fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1499fcf5ef2aSThomas Huth 1500fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1501fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1502fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1503fcf5ef2aSThomas Huth 1504fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1505fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1506fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1507fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1508fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1509fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1510fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1511fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1512fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1513fcf5ef2aSThomas Huth } 1514efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1515fcf5ef2aSThomas Huth } 1516fcf5ef2aSThomas Huth 1517fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1518fcf5ef2aSThomas Huth /* cmpeqb */ 1519fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1520fcf5ef2aSThomas Huth { 1521fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1522fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1523fcf5ef2aSThomas Huth } 1524fcf5ef2aSThomas Huth #endif 1525fcf5ef2aSThomas Huth 1526fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1527fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1528fcf5ef2aSThomas Huth { 1529fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1530fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1531fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1532fcf5ef2aSThomas Huth TCGv zr; 1533fcf5ef2aSThomas Huth 1534fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1535fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1536fcf5ef2aSThomas Huth 15377058ff52SRichard Henderson zr = tcg_constant_tl(0); 1538fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1539fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1540fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1541fcf5ef2aSThomas Huth } 1542fcf5ef2aSThomas Huth 1543fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1544fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1545fcf5ef2aSThomas Huth { 1546fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1547fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1548fcf5ef2aSThomas Huth } 1549fcf5ef2aSThomas Huth 1550fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1551fcf5ef2aSThomas Huth 1552fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1553fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1554fcf5ef2aSThomas Huth { 1555fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1556fcf5ef2aSThomas Huth 1557fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1558fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1559fcf5ef2aSThomas Huth if (sub) { 1560fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1561fcf5ef2aSThomas Huth } else { 1562fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1563fcf5ef2aSThomas Huth } 1564fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1565dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1566dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1567dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1568fcf5ef2aSThomas Huth } 1569dc0ad844SNikunj A Dadhania } else { 1570dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1571dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1572dc0ad844SNikunj A Dadhania } 157338a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1574dc0ad844SNikunj A Dadhania } 1575fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1576fcf5ef2aSThomas Huth } 1577fcf5ef2aSThomas Huth 15786b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15796b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15804c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15816b10d008SNikunj A Dadhania { 15826b10d008SNikunj A Dadhania TCGv t0; 15836b10d008SNikunj A Dadhania 15846b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 15856b10d008SNikunj A Dadhania return; 15866b10d008SNikunj A Dadhania } 15876b10d008SNikunj A Dadhania 15886b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 158933903d0aSNikunj A Dadhania if (sub) { 159033903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 159133903d0aSNikunj A Dadhania } else { 15926b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 159333903d0aSNikunj A Dadhania } 15946b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 15954c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 15966b10d008SNikunj A Dadhania } 15976b10d008SNikunj A Dadhania 1598fcf5ef2aSThomas Huth /* Common add function */ 1599fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16004c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16014c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1602fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1603fcf5ef2aSThomas Huth { 1604fcf5ef2aSThomas Huth TCGv t0 = ret; 1605fcf5ef2aSThomas Huth 1606fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1607fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1608fcf5ef2aSThomas Huth } 1609fcf5ef2aSThomas Huth 1610fcf5ef2aSThomas Huth if (compute_ca) { 1611fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1612efe843d8SDavid Gibson /* 1613efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1614efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1615efe843d8SDavid Gibson * produce the carry into bit 32. 1616efe843d8SDavid Gibson */ 1617fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1618fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1619fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1620fcf5ef2aSThomas Huth if (add_ca) { 16214c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1622fcf5ef2aSThomas Huth } 16234c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 16244c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16256b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16264c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16276b10d008SNikunj A Dadhania } 1628fcf5ef2aSThomas Huth } else { 16297058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 1630fcf5ef2aSThomas Huth if (add_ca) { 16314c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16324c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1633fcf5ef2aSThomas Huth } else { 16344c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1635fcf5ef2aSThomas Huth } 16364c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1637fcf5ef2aSThomas Huth } 1638fcf5ef2aSThomas Huth } else { 1639fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1640fcf5ef2aSThomas Huth if (add_ca) { 16414c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1642fcf5ef2aSThomas Huth } 1643fcf5ef2aSThomas Huth } 1644fcf5ef2aSThomas Huth 1645fcf5ef2aSThomas Huth if (compute_ov) { 1646fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1647fcf5ef2aSThomas Huth } 1648fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1649fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1650fcf5ef2aSThomas Huth } 1651fcf5ef2aSThomas Huth 165211f4e8f8SRichard Henderson if (t0 != ret) { 1653fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1654fcf5ef2aSThomas Huth } 1655fcf5ef2aSThomas Huth } 1656fcf5ef2aSThomas Huth /* Add functions with two operands */ 16574c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1658fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1659fcf5ef2aSThomas Huth { \ 1660fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1661fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16624c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1663fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1664fcf5ef2aSThomas Huth } 1665fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16664c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1667fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1668fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1669fcf5ef2aSThomas Huth { \ 16707058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 1671fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1672fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16734c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1674fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1675fcf5ef2aSThomas Huth } 1676fcf5ef2aSThomas Huth 1677fcf5ef2aSThomas Huth /* add add. addo addo. */ 16784c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16794c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1680fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16814c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16824c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1683fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 16844c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 16854c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1686fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 16874c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 16884c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 16894c5920afSSuraj Jitindar Singh /* addex */ 16904c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1691fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 16924c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 16934c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1694fcf5ef2aSThomas Huth /* addic addic.*/ 1695fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1696fcf5ef2aSThomas Huth { 16977058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1698fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 16994c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1700fcf5ef2aSThomas Huth } 1701fcf5ef2aSThomas Huth 1702fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1703fcf5ef2aSThomas Huth { 1704fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1705fcf5ef2aSThomas Huth } 1706fcf5ef2aSThomas Huth 1707fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1708fcf5ef2aSThomas Huth { 1709fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1710fcf5ef2aSThomas Huth } 1711fcf5ef2aSThomas Huth 1712fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1713fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1714fcf5ef2aSThomas Huth { 1715fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1716fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1717fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1718fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1719fcf5ef2aSThomas Huth 1720fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1721fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1722fcf5ef2aSThomas Huth if (sign) { 1723fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1724fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1725fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1726fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1727fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1728fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1729fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1730fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1731fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1732fcf5ef2aSThomas Huth } else { 1733fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1734fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1735fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1736fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1737fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1738fcf5ef2aSThomas Huth } 1739fcf5ef2aSThomas Huth if (compute_ov) { 1740fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1741c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1742c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1743c44027ffSNikunj A Dadhania } 1744fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1745fcf5ef2aSThomas Huth } 1746fcf5ef2aSThomas Huth 1747efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1748fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1749fcf5ef2aSThomas Huth } 1750efe843d8SDavid Gibson } 1751fcf5ef2aSThomas Huth /* Div functions */ 1752fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1753fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1754fcf5ef2aSThomas Huth { \ 1755fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1756fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1757fcf5ef2aSThomas Huth sign, compute_ov); \ 1758fcf5ef2aSThomas Huth } 1759fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1760fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1761fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1762fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1763fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1764fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1765fcf5ef2aSThomas Huth 1766fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1767fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1768fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1769fcf5ef2aSThomas Huth { \ 17707058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1771fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1772fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1773fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1774fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1775fcf5ef2aSThomas Huth } \ 1776fcf5ef2aSThomas Huth } 1777fcf5ef2aSThomas Huth 1778fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1779fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1780fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1781fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1782fcf5ef2aSThomas Huth 1783fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1784fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1785fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1786fcf5ef2aSThomas Huth { 1787fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1788fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1789fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1790fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1791fcf5ef2aSThomas Huth 1792fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1793fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1794fcf5ef2aSThomas Huth if (sign) { 1795fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1796fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1797fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1798fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1799fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1800fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1801fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1802fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1803fcf5ef2aSThomas Huth } else { 1804fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1805fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1806fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1807fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1808fcf5ef2aSThomas Huth } 1809fcf5ef2aSThomas Huth if (compute_ov) { 1810fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1811c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1812c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1813c44027ffSNikunj A Dadhania } 1814fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1815fcf5ef2aSThomas Huth } 1816fcf5ef2aSThomas Huth 1817efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1818fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1819fcf5ef2aSThomas Huth } 1820efe843d8SDavid Gibson } 1821fcf5ef2aSThomas Huth 1822fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1823fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1824fcf5ef2aSThomas Huth { \ 1825fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1826fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1827fcf5ef2aSThomas Huth sign, compute_ov); \ 1828fcf5ef2aSThomas Huth } 1829c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1830fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1831fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1832c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1833fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1834fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1835fcf5ef2aSThomas Huth 1836fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1837fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1838fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1839fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1840fcf5ef2aSThomas Huth #endif 1841fcf5ef2aSThomas Huth 1842fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1843fcf5ef2aSThomas Huth TCGv arg2, int sign) 1844fcf5ef2aSThomas Huth { 1845fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1846fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1847fcf5ef2aSThomas Huth 1848fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1849fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1850fcf5ef2aSThomas Huth if (sign) { 1851fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1852fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1853fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1854fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1855fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1856fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1857fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1858fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1859fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1860fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1861fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1862fcf5ef2aSThomas Huth } else { 18637058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(1); 18647058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(0); 1865fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1866a253231fSRichard Henderson tcg_gen_remu_i32(t0, t0, t1); 1867a253231fSRichard Henderson tcg_gen_extu_i32_tl(ret, t0); 1868fcf5ef2aSThomas Huth } 1869fcf5ef2aSThomas Huth } 1870fcf5ef2aSThomas Huth 1871fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1872fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1873fcf5ef2aSThomas Huth { \ 1874fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1875fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1876fcf5ef2aSThomas Huth sign); \ 1877fcf5ef2aSThomas Huth } 1878fcf5ef2aSThomas Huth 1879fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1880fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1881fcf5ef2aSThomas Huth 1882fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1883fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1884fcf5ef2aSThomas Huth TCGv arg2, int sign) 1885fcf5ef2aSThomas Huth { 1886fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1887fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1888fcf5ef2aSThomas Huth 1889fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1890fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1891fcf5ef2aSThomas Huth if (sign) { 1892fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1893fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1894fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1895fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1896fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1897fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1898fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1899fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1900fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1901fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1902fcf5ef2aSThomas Huth } else { 19037058ff52SRichard Henderson TCGv_i64 t2 = tcg_constant_i64(1); 19047058ff52SRichard Henderson TCGv_i64 t3 = tcg_constant_i64(0); 1905fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1906fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1907fcf5ef2aSThomas Huth } 1908fcf5ef2aSThomas Huth } 1909fcf5ef2aSThomas Huth 1910fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1911fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1912fcf5ef2aSThomas Huth { \ 1913fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1914fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1915fcf5ef2aSThomas Huth sign); \ 1916fcf5ef2aSThomas Huth } 1917fcf5ef2aSThomas Huth 1918fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1919fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1920fcf5ef2aSThomas Huth #endif 1921fcf5ef2aSThomas Huth 1922fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1923fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1924fcf5ef2aSThomas Huth { 1925fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1926fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1927fcf5ef2aSThomas Huth 1928fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1929fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1930fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1931fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1932efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1933fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1934fcf5ef2aSThomas Huth } 1935efe843d8SDavid Gibson } 1936fcf5ef2aSThomas Huth 1937fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1938fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1939fcf5ef2aSThomas Huth { 1940fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1941fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1942fcf5ef2aSThomas Huth 1943fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1944fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1945fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1946fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1947efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1948fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1949fcf5ef2aSThomas Huth } 1950efe843d8SDavid Gibson } 1951fcf5ef2aSThomas Huth 1952fcf5ef2aSThomas Huth /* mullw mullw. */ 1953fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1954fcf5ef2aSThomas Huth { 1955fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1956fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1957fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1958fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1959fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1960fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1961fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1962fcf5ef2aSThomas Huth #else 1963fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1964fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1965fcf5ef2aSThomas Huth #endif 1966efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1967fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1968fcf5ef2aSThomas Huth } 1969efe843d8SDavid Gibson } 1970fcf5ef2aSThomas Huth 1971fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1972fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1973fcf5ef2aSThomas Huth { 1974fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1975fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1976fcf5ef2aSThomas Huth 1977fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1978fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1979fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1980fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1981fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1982fcf5ef2aSThomas Huth #else 1983fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1984fcf5ef2aSThomas Huth #endif 1985fcf5ef2aSThomas Huth 1986fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1987fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1988fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 198961aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 199061aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 199161aa9a69SNikunj A Dadhania } 1992fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1993fcf5ef2aSThomas Huth 1994efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1995fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1996fcf5ef2aSThomas Huth } 1997efe843d8SDavid Gibson } 1998fcf5ef2aSThomas Huth 1999fcf5ef2aSThomas Huth /* mulli */ 2000fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2001fcf5ef2aSThomas Huth { 2002fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2003fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2004fcf5ef2aSThomas Huth } 2005fcf5ef2aSThomas Huth 2006fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2007fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2008fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2009fcf5ef2aSThomas Huth { 2010fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2011fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2012fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2013fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2014fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2015fcf5ef2aSThomas Huth } 2016fcf5ef2aSThomas Huth } 2017fcf5ef2aSThomas Huth 2018fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2019fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2020fcf5ef2aSThomas Huth { 2021fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2022fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2023fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2024fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2025fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2026fcf5ef2aSThomas Huth } 2027fcf5ef2aSThomas Huth } 2028fcf5ef2aSThomas Huth 2029fcf5ef2aSThomas Huth /* mulld mulld. */ 2030fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2031fcf5ef2aSThomas Huth { 2032fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2033fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2034efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2035fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2036fcf5ef2aSThomas Huth } 2037efe843d8SDavid Gibson } 2038fcf5ef2aSThomas Huth 2039fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2040fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2041fcf5ef2aSThomas Huth { 2042fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2043fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2044fcf5ef2aSThomas Huth 2045fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2046fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2047fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2048fcf5ef2aSThomas Huth 2049fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2050fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 205161aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 205261aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 205361aa9a69SNikunj A Dadhania } 2054fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2055fcf5ef2aSThomas Huth 2056fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2057fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2058fcf5ef2aSThomas Huth } 2059fcf5ef2aSThomas Huth } 2060fcf5ef2aSThomas Huth #endif 2061fcf5ef2aSThomas Huth 2062fcf5ef2aSThomas Huth /* Common subf function */ 2063fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2064fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2065fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2066fcf5ef2aSThomas Huth { 2067fcf5ef2aSThomas Huth TCGv t0 = ret; 2068fcf5ef2aSThomas Huth 2069fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2070fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2071fcf5ef2aSThomas Huth } 2072fcf5ef2aSThomas Huth 2073fcf5ef2aSThomas Huth if (compute_ca) { 2074fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2075fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2076efe843d8SDavid Gibson /* 2077efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2078efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2079efe843d8SDavid Gibson * produce the carry into bit 32. 2080efe843d8SDavid Gibson */ 2081fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2082fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2083fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2084fcf5ef2aSThomas Huth if (add_ca) { 2085fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2086fcf5ef2aSThomas Huth } else { 2087fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2088fcf5ef2aSThomas Huth } 2089fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2090fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2091fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2092e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 209333903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 209433903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 209533903d0aSNikunj A Dadhania } 2096fcf5ef2aSThomas Huth } else if (add_ca) { 2097fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2098fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 20997058ff52SRichard Henderson zero = tcg_constant_tl(0); 2100fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2101fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21024c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2103fcf5ef2aSThomas Huth } else { 2104fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2105fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21064c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2107fcf5ef2aSThomas Huth } 2108fcf5ef2aSThomas Huth } else if (add_ca) { 2109efe843d8SDavid Gibson /* 2110efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2111efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2112efe843d8SDavid Gibson */ 2113fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2114fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2115fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2116fcf5ef2aSThomas Huth } else { 2117fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2118fcf5ef2aSThomas Huth } 2119fcf5ef2aSThomas Huth 2120fcf5ef2aSThomas Huth if (compute_ov) { 2121fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2122fcf5ef2aSThomas Huth } 2123fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2124fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2125fcf5ef2aSThomas Huth } 2126fcf5ef2aSThomas Huth 212711f4e8f8SRichard Henderson if (t0 != ret) { 2128fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2129fcf5ef2aSThomas Huth } 2130fcf5ef2aSThomas Huth } 2131fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2132fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2133fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2134fcf5ef2aSThomas Huth { \ 2135fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2136fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2137fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2138fcf5ef2aSThomas Huth } 2139fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2140fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2141fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2142fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2143fcf5ef2aSThomas Huth { \ 21447058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 2145fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2146fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2147fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2148fcf5ef2aSThomas Huth } 2149fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2150fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2151fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2152fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2153fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2154fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2155fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2156fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2157fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2158fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2159fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2160fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2161fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2162fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2163fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2164fcf5ef2aSThomas Huth 2165fcf5ef2aSThomas Huth /* subfic */ 2166fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2167fcf5ef2aSThomas Huth { 21687058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2169fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2170fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2171fcf5ef2aSThomas Huth } 2172fcf5ef2aSThomas Huth 2173fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2174fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2175fcf5ef2aSThomas Huth { 21767058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 2177fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2178fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2179fcf5ef2aSThomas Huth } 2180fcf5ef2aSThomas Huth 2181fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2182fcf5ef2aSThomas Huth { 21831480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 21841480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 21851480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 21861480d71cSNikunj A Dadhania } 2187fcf5ef2aSThomas Huth } 2188fcf5ef2aSThomas Huth 2189fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2190fcf5ef2aSThomas Huth { 2191fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2192fcf5ef2aSThomas Huth } 2193fcf5ef2aSThomas Huth 2194fcf5ef2aSThomas Huth /*** Integer logical ***/ 2195fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2196fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2197fcf5ef2aSThomas Huth { \ 2198fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2199fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2200fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2201fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2202fcf5ef2aSThomas Huth } 2203fcf5ef2aSThomas Huth 2204fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2205fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2206fcf5ef2aSThomas Huth { \ 2207fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2208fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2209fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2210fcf5ef2aSThomas Huth } 2211fcf5ef2aSThomas Huth 2212fcf5ef2aSThomas Huth /* and & and. */ 2213fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2214fcf5ef2aSThomas Huth /* andc & andc. */ 2215fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2216fcf5ef2aSThomas Huth 2217fcf5ef2aSThomas Huth /* andi. */ 2218fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2219fcf5ef2aSThomas Huth { 2220efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2221efe843d8SDavid Gibson UIMM(ctx->opcode)); 2222fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2223fcf5ef2aSThomas Huth } 2224fcf5ef2aSThomas Huth 2225fcf5ef2aSThomas Huth /* andis. */ 2226fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2227fcf5ef2aSThomas Huth { 2228efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2229efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2230fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2231fcf5ef2aSThomas Huth } 2232fcf5ef2aSThomas Huth 2233fcf5ef2aSThomas Huth /* cntlzw */ 2234fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2235fcf5ef2aSThomas Huth { 22369b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22379b8514e5SRichard Henderson 22389b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22399b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22409b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22419b8514e5SRichard Henderson 2242efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2243fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2244fcf5ef2aSThomas Huth } 2245efe843d8SDavid Gibson } 2246fcf5ef2aSThomas Huth 2247fcf5ef2aSThomas Huth /* cnttzw */ 2248fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2249fcf5ef2aSThomas Huth { 22509b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22519b8514e5SRichard Henderson 22529b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22539b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22549b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22559b8514e5SRichard Henderson 2256fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2257fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2258fcf5ef2aSThomas Huth } 2259fcf5ef2aSThomas Huth } 2260fcf5ef2aSThomas Huth 2261fcf5ef2aSThomas Huth /* eqv & eqv. */ 2262fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2263fcf5ef2aSThomas Huth /* extsb & extsb. */ 2264fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2265fcf5ef2aSThomas Huth /* extsh & extsh. */ 2266fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2267fcf5ef2aSThomas Huth /* nand & nand. */ 2268fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2269fcf5ef2aSThomas Huth /* nor & nor. */ 2270fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2271fcf5ef2aSThomas Huth 2272fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2273fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2274fcf5ef2aSThomas Huth { 22757058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(0); 2276fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2277fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2278fcf5ef2aSThomas Huth 2279fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2280b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2281fcf5ef2aSThomas Huth } 2282fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2283fcf5ef2aSThomas Huth 2284fcf5ef2aSThomas Huth /* or & or. */ 2285fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2286fcf5ef2aSThomas Huth { 2287fcf5ef2aSThomas Huth int rs, ra, rb; 2288fcf5ef2aSThomas Huth 2289fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2290fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2291fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2292fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2293fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2294efe843d8SDavid Gibson if (rs != rb) { 2295fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2296efe843d8SDavid Gibson } else { 2297fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2298efe843d8SDavid Gibson } 2299efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2300fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2301efe843d8SDavid Gibson } 2302fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2303fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2304fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2305fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2306fcf5ef2aSThomas Huth int prio = 0; 2307fcf5ef2aSThomas Huth 2308fcf5ef2aSThomas Huth switch (rs) { 2309fcf5ef2aSThomas Huth case 1: 2310fcf5ef2aSThomas Huth /* Set process priority to low */ 2311fcf5ef2aSThomas Huth prio = 2; 2312fcf5ef2aSThomas Huth break; 2313fcf5ef2aSThomas Huth case 6: 2314fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2315fcf5ef2aSThomas Huth prio = 3; 2316fcf5ef2aSThomas Huth break; 2317fcf5ef2aSThomas Huth case 2: 2318fcf5ef2aSThomas Huth /* Set process priority to normal */ 2319fcf5ef2aSThomas Huth prio = 4; 2320fcf5ef2aSThomas Huth break; 2321fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2322fcf5ef2aSThomas Huth case 31: 2323fcf5ef2aSThomas Huth if (!ctx->pr) { 2324fcf5ef2aSThomas Huth /* Set process priority to very low */ 2325fcf5ef2aSThomas Huth prio = 1; 2326fcf5ef2aSThomas Huth } 2327fcf5ef2aSThomas Huth break; 2328fcf5ef2aSThomas Huth case 5: 2329fcf5ef2aSThomas Huth if (!ctx->pr) { 2330fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2331fcf5ef2aSThomas Huth prio = 5; 2332fcf5ef2aSThomas Huth } 2333fcf5ef2aSThomas Huth break; 2334fcf5ef2aSThomas Huth case 3: 2335fcf5ef2aSThomas Huth if (!ctx->pr) { 2336fcf5ef2aSThomas Huth /* Set process priority to high */ 2337fcf5ef2aSThomas Huth prio = 6; 2338fcf5ef2aSThomas Huth } 2339fcf5ef2aSThomas Huth break; 2340fcf5ef2aSThomas Huth case 7: 2341fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2342fcf5ef2aSThomas Huth /* Set process priority to very high */ 2343fcf5ef2aSThomas Huth prio = 7; 2344fcf5ef2aSThomas Huth } 2345fcf5ef2aSThomas Huth break; 2346fcf5ef2aSThomas Huth #endif 2347fcf5ef2aSThomas Huth default: 2348fcf5ef2aSThomas Huth break; 2349fcf5ef2aSThomas Huth } 2350fcf5ef2aSThomas Huth if (prio) { 2351fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2352fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2353fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2354fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2355fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2356fcf5ef2aSThomas Huth } 2357fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2358efe843d8SDavid Gibson /* 2359efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2360efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2361efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2362efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2363fcf5ef2aSThomas Huth */ 2364fcf5ef2aSThomas Huth gen_pause(ctx); 2365fcf5ef2aSThomas Huth #endif 2366fcf5ef2aSThomas Huth #endif 2367fcf5ef2aSThomas Huth } 2368fcf5ef2aSThomas Huth } 2369fcf5ef2aSThomas Huth /* orc & orc. */ 2370fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2371fcf5ef2aSThomas Huth 2372fcf5ef2aSThomas Huth /* xor & xor. */ 2373fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2374fcf5ef2aSThomas Huth { 2375fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2376efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2377efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2378efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2379efe843d8SDavid Gibson } else { 2380fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2381efe843d8SDavid Gibson } 2382efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2383fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2384fcf5ef2aSThomas Huth } 2385efe843d8SDavid Gibson } 2386fcf5ef2aSThomas Huth 2387fcf5ef2aSThomas Huth /* ori */ 2388fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2389fcf5ef2aSThomas Huth { 2390fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2391fcf5ef2aSThomas Huth 2392fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2393fcf5ef2aSThomas Huth return; 2394fcf5ef2aSThomas Huth } 2395fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2396fcf5ef2aSThomas Huth } 2397fcf5ef2aSThomas Huth 2398fcf5ef2aSThomas Huth /* oris */ 2399fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2400fcf5ef2aSThomas Huth { 2401fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2402fcf5ef2aSThomas Huth 2403fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2404fcf5ef2aSThomas Huth /* NOP */ 2405fcf5ef2aSThomas Huth return; 2406fcf5ef2aSThomas Huth } 2407efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2408efe843d8SDavid Gibson uimm << 16); 2409fcf5ef2aSThomas Huth } 2410fcf5ef2aSThomas Huth 2411fcf5ef2aSThomas Huth /* xori */ 2412fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2413fcf5ef2aSThomas Huth { 2414fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2415fcf5ef2aSThomas Huth 2416fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2417fcf5ef2aSThomas Huth /* NOP */ 2418fcf5ef2aSThomas Huth return; 2419fcf5ef2aSThomas Huth } 2420fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2421fcf5ef2aSThomas Huth } 2422fcf5ef2aSThomas Huth 2423fcf5ef2aSThomas Huth /* xoris */ 2424fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2425fcf5ef2aSThomas Huth { 2426fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2427fcf5ef2aSThomas Huth 2428fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2429fcf5ef2aSThomas Huth /* NOP */ 2430fcf5ef2aSThomas Huth return; 2431fcf5ef2aSThomas Huth } 2432efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2433efe843d8SDavid Gibson uimm << 16); 2434fcf5ef2aSThomas Huth } 2435fcf5ef2aSThomas Huth 2436fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2437fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2438fcf5ef2aSThomas Huth { 2439fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2440fcf5ef2aSThomas Huth } 2441fcf5ef2aSThomas Huth 2442fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2443fcf5ef2aSThomas Huth { 244479770002SRichard Henderson #if defined(TARGET_PPC64) 2445fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 244679770002SRichard Henderson #else 244779770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 244879770002SRichard Henderson #endif 2449fcf5ef2aSThomas Huth } 2450fcf5ef2aSThomas Huth 2451fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2452fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2453fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2454fcf5ef2aSThomas Huth { 245579770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2456fcf5ef2aSThomas Huth } 2457fcf5ef2aSThomas Huth #endif 2458fcf5ef2aSThomas Huth 2459fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2460fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2461fcf5ef2aSThomas Huth { 2462fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2463fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2464fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2465fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2466fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2467fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2468fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2469fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2470fcf5ef2aSThomas Huth } 2471fcf5ef2aSThomas Huth 2472fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2473fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2474fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2475fcf5ef2aSThomas Huth { 2476fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2477fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2478fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2479fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2480fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2481fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2482fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2483fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2484fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2485fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2486fcf5ef2aSThomas Huth } 2487fcf5ef2aSThomas Huth #endif 2488fcf5ef2aSThomas Huth 2489fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2490fcf5ef2aSThomas Huth /* bpermd */ 2491fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2492fcf5ef2aSThomas Huth { 2493fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2494fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2495fcf5ef2aSThomas Huth } 2496fcf5ef2aSThomas Huth #endif 2497fcf5ef2aSThomas Huth 2498fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2499fcf5ef2aSThomas Huth /* extsw & extsw. */ 2500fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2501fcf5ef2aSThomas Huth 2502fcf5ef2aSThomas Huth /* cntlzd */ 2503fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2504fcf5ef2aSThomas Huth { 25059b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2506efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2507fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2508fcf5ef2aSThomas Huth } 2509efe843d8SDavid Gibson } 2510fcf5ef2aSThomas Huth 2511fcf5ef2aSThomas Huth /* cnttzd */ 2512fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2513fcf5ef2aSThomas Huth { 25149b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2515fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2516fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2517fcf5ef2aSThomas Huth } 2518fcf5ef2aSThomas Huth } 2519fcf5ef2aSThomas Huth 2520fcf5ef2aSThomas Huth /* darn */ 2521fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2522fcf5ef2aSThomas Huth { 2523fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2524fcf5ef2aSThomas Huth 25257e4357f6SRichard Henderson if (l > 2) { 25267e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25277e4357f6SRichard Henderson } else { 2528283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 2529fcf5ef2aSThomas Huth if (l == 0) { 2530fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25317e4357f6SRichard Henderson } else { 2532fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2533fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25347e4357f6SRichard Henderson } 2535fcf5ef2aSThomas Huth } 2536fcf5ef2aSThomas Huth } 2537fcf5ef2aSThomas Huth #endif 2538fcf5ef2aSThomas Huth 2539fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2540fcf5ef2aSThomas Huth 2541fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2542fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2543fcf5ef2aSThomas Huth { 2544fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2545fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2546fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2547fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2548fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2549fcf5ef2aSThomas Huth 2550fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2551fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2552fcf5ef2aSThomas Huth } else { 2553fcf5ef2aSThomas Huth target_ulong mask; 2554c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2555fcf5ef2aSThomas Huth TCGv t1; 2556fcf5ef2aSThomas Huth 2557fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2558fcf5ef2aSThomas Huth mb += 32; 2559fcf5ef2aSThomas Huth me += 32; 2560fcf5ef2aSThomas Huth #endif 2561fcf5ef2aSThomas Huth mask = MASK(mb, me); 2562fcf5ef2aSThomas Huth 2563c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2564c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2565c4f6a4a3SDaniele Buono mask_in_32b = false; 2566c4f6a4a3SDaniele Buono } 2567c4f6a4a3SDaniele Buono #endif 2568fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2569c4f6a4a3SDaniele Buono if (mask_in_32b) { 2570fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2571fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2572fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2573fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2574fcf5ef2aSThomas Huth } else { 2575fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2576fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2577fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2578fcf5ef2aSThomas Huth #else 2579fcf5ef2aSThomas Huth g_assert_not_reached(); 2580fcf5ef2aSThomas Huth #endif 2581fcf5ef2aSThomas Huth } 2582fcf5ef2aSThomas Huth 2583fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2584fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2585fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2586fcf5ef2aSThomas Huth } 2587fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2588fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2589fcf5ef2aSThomas Huth } 2590fcf5ef2aSThomas Huth } 2591fcf5ef2aSThomas Huth 2592fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2593fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2594fcf5ef2aSThomas Huth { 2595fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2596fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 25977b4d326fSRichard Henderson int sh = SH(ctx->opcode); 25987b4d326fSRichard Henderson int mb = MB(ctx->opcode); 25997b4d326fSRichard Henderson int me = ME(ctx->opcode); 26007b4d326fSRichard Henderson int len = me - mb + 1; 26017b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2602fcf5ef2aSThomas Huth 26037b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26047b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26057b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26067b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2607fcf5ef2aSThomas Huth } else { 2608fcf5ef2aSThomas Huth target_ulong mask; 2609c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2610fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2611fcf5ef2aSThomas Huth mb += 32; 2612fcf5ef2aSThomas Huth me += 32; 2613fcf5ef2aSThomas Huth #endif 2614fcf5ef2aSThomas Huth mask = MASK(mb, me); 2615c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2616c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2617c4f6a4a3SDaniele Buono mask_in_32b = false; 2618c4f6a4a3SDaniele Buono } 2619c4f6a4a3SDaniele Buono #endif 2620c4f6a4a3SDaniele Buono if (mask_in_32b) { 26217b4d326fSRichard Henderson if (sh == 0) { 26227b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 262394f040aaSVitaly Chikunov } else { 2624fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2625fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2626fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2627fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2628fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 262994f040aaSVitaly Chikunov } 2630fcf5ef2aSThomas Huth } else { 2631fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2632fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2633fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2634fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2635fcf5ef2aSThomas Huth #else 2636fcf5ef2aSThomas Huth g_assert_not_reached(); 2637fcf5ef2aSThomas Huth #endif 2638fcf5ef2aSThomas Huth } 2639fcf5ef2aSThomas Huth } 2640fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2641fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2642fcf5ef2aSThomas Huth } 2643fcf5ef2aSThomas Huth } 2644fcf5ef2aSThomas Huth 2645fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2646fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2647fcf5ef2aSThomas Huth { 2648fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2649fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2650fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2651fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2652fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2653fcf5ef2aSThomas Huth target_ulong mask; 2654c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2655fcf5ef2aSThomas Huth 2656fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2657fcf5ef2aSThomas Huth mb += 32; 2658fcf5ef2aSThomas Huth me += 32; 2659fcf5ef2aSThomas Huth #endif 2660fcf5ef2aSThomas Huth mask = MASK(mb, me); 2661fcf5ef2aSThomas Huth 2662c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2663c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2664c4f6a4a3SDaniele Buono mask_in_32b = false; 2665c4f6a4a3SDaniele Buono } 2666c4f6a4a3SDaniele Buono #endif 2667c4f6a4a3SDaniele Buono if (mask_in_32b) { 2668fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2669fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2670fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2671fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2672fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2673fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2674fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2675fcf5ef2aSThomas Huth } else { 2676fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2677fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2678fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2679fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2680fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2681fcf5ef2aSThomas Huth #else 2682fcf5ef2aSThomas Huth g_assert_not_reached(); 2683fcf5ef2aSThomas Huth #endif 2684fcf5ef2aSThomas Huth } 2685fcf5ef2aSThomas Huth 2686fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2687fcf5ef2aSThomas Huth 2688fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2689fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2690fcf5ef2aSThomas Huth } 2691fcf5ef2aSThomas Huth } 2692fcf5ef2aSThomas Huth 2693fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2694fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2695fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2696fcf5ef2aSThomas Huth { \ 2697fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2698fcf5ef2aSThomas Huth } \ 2699fcf5ef2aSThomas Huth \ 2700fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2701fcf5ef2aSThomas Huth { \ 2702fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2703fcf5ef2aSThomas Huth } 2704fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2705fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2706fcf5ef2aSThomas Huth { \ 2707fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2708fcf5ef2aSThomas Huth } \ 2709fcf5ef2aSThomas Huth \ 2710fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2711fcf5ef2aSThomas Huth { \ 2712fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2713fcf5ef2aSThomas Huth } \ 2714fcf5ef2aSThomas Huth \ 2715fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2716fcf5ef2aSThomas Huth { \ 2717fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2718fcf5ef2aSThomas Huth } \ 2719fcf5ef2aSThomas Huth \ 2720fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2721fcf5ef2aSThomas Huth { \ 2722fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2723fcf5ef2aSThomas Huth } 2724fcf5ef2aSThomas Huth 2725fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2726fcf5ef2aSThomas Huth { 2727fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2728fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27297b4d326fSRichard Henderson int len = me - mb + 1; 27307b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2731fcf5ef2aSThomas Huth 27327b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27337b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27347b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27357b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2736fcf5ef2aSThomas Huth } else { 2737fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2738fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2739fcf5ef2aSThomas Huth } 2740fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2741fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2742fcf5ef2aSThomas Huth } 2743fcf5ef2aSThomas Huth } 2744fcf5ef2aSThomas Huth 2745fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2746fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2747fcf5ef2aSThomas Huth { 2748fcf5ef2aSThomas Huth uint32_t sh, mb; 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2751fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2752fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2753fcf5ef2aSThomas Huth } 2754fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2755fcf5ef2aSThomas Huth 2756fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2757fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2758fcf5ef2aSThomas Huth { 2759fcf5ef2aSThomas Huth uint32_t sh, me; 2760fcf5ef2aSThomas Huth 2761fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2762fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2763fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2764fcf5ef2aSThomas Huth } 2765fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2766fcf5ef2aSThomas Huth 2767fcf5ef2aSThomas Huth /* rldic - rldic. */ 2768fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2769fcf5ef2aSThomas Huth { 2770fcf5ef2aSThomas Huth uint32_t sh, mb; 2771fcf5ef2aSThomas Huth 2772fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2773fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2774fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2775fcf5ef2aSThomas Huth } 2776fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2777fcf5ef2aSThomas Huth 2778fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2779fcf5ef2aSThomas Huth { 2780fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2781fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2782fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2783fcf5ef2aSThomas Huth TCGv t0; 2784fcf5ef2aSThomas Huth 2785fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2786fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2787fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2788fcf5ef2aSThomas Huth 2789fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2790fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2791fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2792fcf5ef2aSThomas Huth } 2793fcf5ef2aSThomas Huth } 2794fcf5ef2aSThomas Huth 2795fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2796fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2797fcf5ef2aSThomas Huth { 2798fcf5ef2aSThomas Huth uint32_t mb; 2799fcf5ef2aSThomas Huth 2800fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2801fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2802fcf5ef2aSThomas Huth } 2803fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2804fcf5ef2aSThomas Huth 2805fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2806fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2807fcf5ef2aSThomas Huth { 2808fcf5ef2aSThomas Huth uint32_t me; 2809fcf5ef2aSThomas Huth 2810fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2811fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2812fcf5ef2aSThomas Huth } 2813fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2814fcf5ef2aSThomas Huth 2815fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2816fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2817fcf5ef2aSThomas Huth { 2818fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2819fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2820fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2821fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2822fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2823fcf5ef2aSThomas Huth 2824fcf5ef2aSThomas Huth if (mb <= me) { 2825fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2826fcf5ef2aSThomas Huth } else { 2827fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2828fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2829fcf5ef2aSThomas Huth 2830fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2831fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2832fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2833fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2834fcf5ef2aSThomas Huth } 2835fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2836fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2837fcf5ef2aSThomas Huth } 2838fcf5ef2aSThomas Huth } 2839fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2840fcf5ef2aSThomas Huth #endif 2841fcf5ef2aSThomas Huth 2842fcf5ef2aSThomas Huth /*** Integer shift ***/ 2843fcf5ef2aSThomas Huth 2844fcf5ef2aSThomas Huth /* slw & slw. */ 2845fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2846fcf5ef2aSThomas Huth { 2847fcf5ef2aSThomas Huth TCGv t0, t1; 2848fcf5ef2aSThomas Huth 2849fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2850fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2851fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2852fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2853fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2854fcf5ef2aSThomas Huth #else 2855fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2856fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2857fcf5ef2aSThomas Huth #endif 2858fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2859fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2860fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2861fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2862fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2863efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2864fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2865fcf5ef2aSThomas Huth } 2866efe843d8SDavid Gibson } 2867fcf5ef2aSThomas Huth 2868fcf5ef2aSThomas Huth /* sraw & sraw. */ 2869fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2870fcf5ef2aSThomas Huth { 2871fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2872fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2873efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2874fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2875fcf5ef2aSThomas Huth } 2876efe843d8SDavid Gibson } 2877fcf5ef2aSThomas Huth 2878fcf5ef2aSThomas Huth /* srawi & srawi. */ 2879fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2880fcf5ef2aSThomas Huth { 2881fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2882fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2883fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2884fcf5ef2aSThomas Huth if (sh == 0) { 2885fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2886fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2887af1c259fSSandipan Das if (is_isa300(ctx)) { 2888af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2889af1c259fSSandipan Das } 2890fcf5ef2aSThomas Huth } else { 2891fcf5ef2aSThomas Huth TCGv t0; 2892fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2893fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2894fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2895fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2896fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2897fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2898af1c259fSSandipan Das if (is_isa300(ctx)) { 2899af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2900af1c259fSSandipan Das } 2901fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2902fcf5ef2aSThomas Huth } 2903fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2904fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2905fcf5ef2aSThomas Huth } 2906fcf5ef2aSThomas Huth } 2907fcf5ef2aSThomas Huth 2908fcf5ef2aSThomas Huth /* srw & srw. */ 2909fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2910fcf5ef2aSThomas Huth { 2911fcf5ef2aSThomas Huth TCGv t0, t1; 2912fcf5ef2aSThomas Huth 2913fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2914fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2915fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2916fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2917fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2918fcf5ef2aSThomas Huth #else 2919fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2920fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2921fcf5ef2aSThomas Huth #endif 2922fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2923fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2924fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2925fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2926fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2927efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2928fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2929fcf5ef2aSThomas Huth } 2930efe843d8SDavid Gibson } 2931fcf5ef2aSThomas Huth 2932fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2933fcf5ef2aSThomas Huth /* sld & sld. */ 2934fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2935fcf5ef2aSThomas Huth { 2936fcf5ef2aSThomas Huth TCGv t0, t1; 2937fcf5ef2aSThomas Huth 2938fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2939fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2940fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2941fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2942fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2943fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2944fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2945fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2946efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2947fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2948fcf5ef2aSThomas Huth } 2949efe843d8SDavid Gibson } 2950fcf5ef2aSThomas Huth 2951fcf5ef2aSThomas Huth /* srad & srad. */ 2952fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2953fcf5ef2aSThomas Huth { 2954fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2955fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2956efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2957fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2958fcf5ef2aSThomas Huth } 2959efe843d8SDavid Gibson } 2960fcf5ef2aSThomas Huth /* sradi & sradi. */ 2961fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2962fcf5ef2aSThomas Huth { 2963fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2964fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2965fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2966fcf5ef2aSThomas Huth if (sh == 0) { 2967fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2968fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2969af1c259fSSandipan Das if (is_isa300(ctx)) { 2970af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2971af1c259fSSandipan Das } 2972fcf5ef2aSThomas Huth } else { 2973fcf5ef2aSThomas Huth TCGv t0; 2974fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2975fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2976fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2977fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2978fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2979af1c259fSSandipan Das if (is_isa300(ctx)) { 2980af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2981af1c259fSSandipan Das } 2982fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2983fcf5ef2aSThomas Huth } 2984fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2985fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2986fcf5ef2aSThomas Huth } 2987fcf5ef2aSThomas Huth } 2988fcf5ef2aSThomas Huth 2989fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2990fcf5ef2aSThomas Huth { 2991fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2992fcf5ef2aSThomas Huth } 2993fcf5ef2aSThomas Huth 2994fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2995fcf5ef2aSThomas Huth { 2996fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2997fcf5ef2aSThomas Huth } 2998fcf5ef2aSThomas Huth 2999fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3000fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3001fcf5ef2aSThomas Huth { 3002fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3003fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3004fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3005fcf5ef2aSThomas Huth 3006fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3007fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3008fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3009fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3010fcf5ef2aSThomas Huth } 3011fcf5ef2aSThomas Huth } 3012fcf5ef2aSThomas Huth 3013fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3014fcf5ef2aSThomas Huth { 3015fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3016fcf5ef2aSThomas Huth } 3017fcf5ef2aSThomas Huth 3018fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3019fcf5ef2aSThomas Huth { 3020fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3021fcf5ef2aSThomas Huth } 3022fcf5ef2aSThomas Huth 3023fcf5ef2aSThomas Huth /* srd & srd. */ 3024fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3025fcf5ef2aSThomas Huth { 3026fcf5ef2aSThomas Huth TCGv t0, t1; 3027fcf5ef2aSThomas Huth 3028fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3029fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3030fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3031fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3032fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3033fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3034fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3035fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3036efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3037fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3038fcf5ef2aSThomas Huth } 3039efe843d8SDavid Gibson } 3040fcf5ef2aSThomas Huth #endif 3041fcf5ef2aSThomas Huth 3042fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3043fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3044fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3045fcf5ef2aSThomas Huth target_long maskl) 3046fcf5ef2aSThomas Huth { 3047fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3048fcf5ef2aSThomas Huth 3049fcf5ef2aSThomas Huth simm &= ~maskl; 3050fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3051fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3052fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3053fcf5ef2aSThomas Huth } 3054fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3055fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3056fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3057fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3058fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3059fcf5ef2aSThomas Huth } 3060fcf5ef2aSThomas Huth } else { 3061fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3062fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3063fcf5ef2aSThomas Huth } else { 3064fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3065fcf5ef2aSThomas Huth } 3066fcf5ef2aSThomas Huth } 3067fcf5ef2aSThomas Huth } 3068fcf5ef2aSThomas Huth 3069fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3070fcf5ef2aSThomas Huth { 3071fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3072fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3073fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3074fcf5ef2aSThomas Huth } else { 3075fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3076fcf5ef2aSThomas Huth } 3077fcf5ef2aSThomas Huth } else { 3078fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3079fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3080fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3081fcf5ef2aSThomas Huth } 3082fcf5ef2aSThomas Huth } 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth 3085fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3086fcf5ef2aSThomas Huth { 3087fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3088fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3089fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3090fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3091fcf5ef2aSThomas Huth } else { 3092fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3093fcf5ef2aSThomas Huth } 3094fcf5ef2aSThomas Huth } 3095fcf5ef2aSThomas Huth 3096fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3097fcf5ef2aSThomas Huth target_long val) 3098fcf5ef2aSThomas Huth { 3099fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3100fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3101fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3102fcf5ef2aSThomas Huth } 3103fcf5ef2aSThomas Huth } 3104fcf5ef2aSThomas Huth 3105fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3106fcf5ef2aSThomas Huth { 3107fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3108fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3109fcf5ef2aSThomas Huth } 3110fcf5ef2aSThomas Huth 3111eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3112eb63efd9SFernando Eckhardt Valle { 3113eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3114eb63efd9SFernando Eckhardt Valle if (ra) { 3115eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3116eb63efd9SFernando Eckhardt Valle } else { 3117eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3118eb63efd9SFernando Eckhardt Valle } 3119eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3120eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3121eb63efd9SFernando Eckhardt Valle } 3122eb63efd9SFernando Eckhardt Valle return ea; 3123eb63efd9SFernando Eckhardt Valle } 3124eb63efd9SFernando Eckhardt Valle 3125fcf5ef2aSThomas Huth /*** Integer load ***/ 3126fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3127fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3128fcf5ef2aSThomas Huth 3129fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3130fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3131fcf5ef2aSThomas Huth TCGv val, \ 3132fcf5ef2aSThomas Huth TCGv addr) \ 3133fcf5ef2aSThomas Huth { \ 3134fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3135fcf5ef2aSThomas Huth } 3136fcf5ef2aSThomas Huth 3137fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3138fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3139fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3140fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3141fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3142fcf5ef2aSThomas Huth 3143fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3144fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3145fcf5ef2aSThomas Huth 3146fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3147fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3148fcf5ef2aSThomas Huth TCGv_i64 val, \ 3149fcf5ef2aSThomas Huth TCGv addr) \ 3150fcf5ef2aSThomas Huth { \ 3151fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3152fcf5ef2aSThomas Huth } 3153fcf5ef2aSThomas Huth 3154fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3155fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3156fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3157fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3158fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3159fcf5ef2aSThomas Huth 3160fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3161fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3162fcf5ef2aSThomas Huth #endif 3163fcf5ef2aSThomas Huth 3164fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3165fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3166fcf5ef2aSThomas Huth TCGv val, \ 3167fcf5ef2aSThomas Huth TCGv addr) \ 3168fcf5ef2aSThomas Huth { \ 3169fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3170fcf5ef2aSThomas Huth } 3171fcf5ef2aSThomas Huth 3172e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3173fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3174e8f4c8d6SRichard Henderson #endif 3175fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3176fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3177fcf5ef2aSThomas Huth 3178fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3179fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3180fcf5ef2aSThomas Huth 3181fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3182fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3183fcf5ef2aSThomas Huth TCGv_i64 val, \ 3184fcf5ef2aSThomas Huth TCGv addr) \ 3185fcf5ef2aSThomas Huth { \ 3186fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3187fcf5ef2aSThomas Huth } 3188fcf5ef2aSThomas Huth 3189fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3190fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3191fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3192fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3193fcf5ef2aSThomas Huth 3194fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3195fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3196fcf5ef2aSThomas Huth #endif 3197fcf5ef2aSThomas Huth 3198fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3199fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3200fcf5ef2aSThomas Huth { \ 3201fcf5ef2aSThomas Huth TCGv EA; \ 32029f0cf041SMatheus Ferst chk(ctx); \ 3203fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3204fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3205fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3206fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3207fcf5ef2aSThomas Huth } 3208fcf5ef2aSThomas Huth 3209fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3210fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3211fcf5ef2aSThomas Huth 3212fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3213fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3214fcf5ef2aSThomas Huth 321550728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 321650728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 321750728199SRoman Kapl { \ 321850728199SRoman Kapl TCGv EA; \ 32199f0cf041SMatheus Ferst CHK_SV(ctx); \ 322050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 322150728199SRoman Kapl EA = tcg_temp_new(); \ 322250728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 322350728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 322450728199SRoman Kapl } 322550728199SRoman Kapl 322650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 322750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 322850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 322950728199SRoman Kapl #if defined(TARGET_PPC64) 3230fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 323150728199SRoman Kapl #endif 323250728199SRoman Kapl 3233fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3234fcf5ef2aSThomas Huth /* CI load/store variants */ 3235fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3236fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3237fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3238fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3239fcf5ef2aSThomas Huth #endif 3240fcf5ef2aSThomas Huth 3241fcf5ef2aSThomas Huth /*** Integer store ***/ 3242fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3243fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3244fcf5ef2aSThomas Huth { \ 3245fcf5ef2aSThomas Huth TCGv EA; \ 32469f0cf041SMatheus Ferst chk(ctx); \ 3247fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3248fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3249fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3250fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3251fcf5ef2aSThomas Huth } 3252fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3253fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3254fcf5ef2aSThomas Huth 3255fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3256fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3257fcf5ef2aSThomas Huth 325850728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 325950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 326050728199SRoman Kapl { \ 326150728199SRoman Kapl TCGv EA; \ 32629f0cf041SMatheus Ferst CHK_SV(ctx); \ 326350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 326450728199SRoman Kapl EA = tcg_temp_new(); \ 326550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 326650728199SRoman Kapl tcg_gen_qemu_st_tl( \ 326750728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 326850728199SRoman Kapl } 326950728199SRoman Kapl 327050728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 327150728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 327250728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 327350728199SRoman Kapl #if defined(TARGET_PPC64) 3274fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 327550728199SRoman Kapl #endif 327650728199SRoman Kapl 3277fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3278fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3279fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3280fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3281fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3282fcf5ef2aSThomas Huth #endif 3283fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3284fcf5ef2aSThomas Huth 3285fcf5ef2aSThomas Huth /* lhbrx */ 3286fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3287fcf5ef2aSThomas Huth 3288fcf5ef2aSThomas Huth /* lwbrx */ 3289fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3290fcf5ef2aSThomas Huth 3291fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3292fcf5ef2aSThomas Huth /* ldbrx */ 3293fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3294fcf5ef2aSThomas Huth /* stdbrx */ 3295fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3296fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3297fcf5ef2aSThomas Huth 3298fcf5ef2aSThomas Huth /* sthbrx */ 3299fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3300fcf5ef2aSThomas Huth /* stwbrx */ 3301fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3302fcf5ef2aSThomas Huth 3303fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3304fcf5ef2aSThomas Huth 3305fcf5ef2aSThomas Huth /* lmw */ 3306fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3307fcf5ef2aSThomas Huth { 3308fcf5ef2aSThomas Huth TCGv t0; 3309fcf5ef2aSThomas Huth TCGv_i32 t1; 3310fcf5ef2aSThomas Huth 3311fcf5ef2aSThomas Huth if (ctx->le_mode) { 3312fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3313fcf5ef2aSThomas Huth return; 3314fcf5ef2aSThomas Huth } 3315fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3316fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33177058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 3318fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3319fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3320fcf5ef2aSThomas Huth } 3321fcf5ef2aSThomas Huth 3322fcf5ef2aSThomas Huth /* stmw */ 3323fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3324fcf5ef2aSThomas Huth { 3325fcf5ef2aSThomas Huth TCGv t0; 3326fcf5ef2aSThomas Huth TCGv_i32 t1; 3327fcf5ef2aSThomas Huth 3328fcf5ef2aSThomas Huth if (ctx->le_mode) { 3329fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3330fcf5ef2aSThomas Huth return; 3331fcf5ef2aSThomas Huth } 3332fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3333fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33347058ff52SRichard Henderson t1 = tcg_constant_i32(rS(ctx->opcode)); 3335fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3336fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3337fcf5ef2aSThomas Huth } 3338fcf5ef2aSThomas Huth 3339fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3340fcf5ef2aSThomas Huth 3341fcf5ef2aSThomas Huth /* lswi */ 3342efe843d8SDavid Gibson /* 3343efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3344efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3345efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3346efe843d8SDavid Gibson * spec... 3347fcf5ef2aSThomas Huth */ 3348fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3349fcf5ef2aSThomas Huth { 3350fcf5ef2aSThomas Huth TCGv t0; 3351fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3352fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3353fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3354fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3355fcf5ef2aSThomas Huth int nr; 3356fcf5ef2aSThomas Huth 3357fcf5ef2aSThomas Huth if (ctx->le_mode) { 3358fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3359fcf5ef2aSThomas Huth return; 3360fcf5ef2aSThomas Huth } 3361efe843d8SDavid Gibson if (nb == 0) { 3362fcf5ef2aSThomas Huth nb = 32; 3363efe843d8SDavid Gibson } 3364f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3365fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3366fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3367fcf5ef2aSThomas Huth return; 3368fcf5ef2aSThomas Huth } 3369fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3370fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3371fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 33727058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 33737058ff52SRichard Henderson t2 = tcg_constant_i32(start); 3374fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3375fcf5ef2aSThomas Huth } 3376fcf5ef2aSThomas Huth 3377fcf5ef2aSThomas Huth /* lswx */ 3378fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3379fcf5ef2aSThomas Huth { 3380fcf5ef2aSThomas Huth TCGv t0; 3381fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3382fcf5ef2aSThomas Huth 3383fcf5ef2aSThomas Huth if (ctx->le_mode) { 3384fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3385fcf5ef2aSThomas Huth return; 3386fcf5ef2aSThomas Huth } 3387fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3388fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3389fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 33907058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 33917058ff52SRichard Henderson t2 = tcg_constant_i32(rA(ctx->opcode)); 33927058ff52SRichard Henderson t3 = tcg_constant_i32(rB(ctx->opcode)); 3393fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3394fcf5ef2aSThomas Huth } 3395fcf5ef2aSThomas Huth 3396fcf5ef2aSThomas Huth /* stswi */ 3397fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3398fcf5ef2aSThomas Huth { 3399fcf5ef2aSThomas Huth TCGv t0; 3400fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3401fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3402fcf5ef2aSThomas Huth 3403fcf5ef2aSThomas Huth if (ctx->le_mode) { 3404fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3405fcf5ef2aSThomas Huth return; 3406fcf5ef2aSThomas Huth } 3407fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3408fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3409fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3410efe843d8SDavid Gibson if (nb == 0) { 3411fcf5ef2aSThomas Huth nb = 32; 3412efe843d8SDavid Gibson } 34137058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 34147058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3415fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3416fcf5ef2aSThomas Huth } 3417fcf5ef2aSThomas Huth 3418fcf5ef2aSThomas Huth /* stswx */ 3419fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3420fcf5ef2aSThomas Huth { 3421fcf5ef2aSThomas Huth TCGv t0; 3422fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3423fcf5ef2aSThomas Huth 3424fcf5ef2aSThomas Huth if (ctx->le_mode) { 3425fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3426fcf5ef2aSThomas Huth return; 3427fcf5ef2aSThomas Huth } 3428fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3429fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3430fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3431fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3432fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3433fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 34347058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3435fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3436fcf5ef2aSThomas Huth } 3437fcf5ef2aSThomas Huth 3438fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3439fcf5ef2aSThomas Huth /* eieio */ 3440fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3441fcf5ef2aSThomas Huth { 3442fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3443fcb830afSNicholas Piggin 3444fcb830afSNicholas Piggin /* 3445fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3446fcb830afSNicholas Piggin * operations in the set: 3447fcb830afSNicholas Piggin * - loads from CI memory. 3448fcb830afSNicholas Piggin * - stores to CI memory. 3449fcb830afSNicholas Piggin * - stores to WT memory. 3450fcb830afSNicholas Piggin * 3451fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3452fcb830afSNicholas Piggin * - stores to cacheble memory. 3453fcb830afSNicholas Piggin * 3454fcb830afSNicholas Piggin * It also serializes instructions: 3455fcb830afSNicholas Piggin * - dcbt and dcbst. 3456fcb830afSNicholas Piggin * 3457fcb830afSNicholas Piggin * It separately serializes: 3458fcb830afSNicholas Piggin * - tlbie and tlbsync. 3459fcb830afSNicholas Piggin * 3460fcb830afSNicholas Piggin * And separately serializes: 3461fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3462fcb830afSNicholas Piggin * 3463fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3464fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3465fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3466fcb830afSNicholas Piggin * serialization. 3467fcb830afSNicholas Piggin */ 3468c8fd8373SCédric Le Goater 3469c8fd8373SCédric Le Goater /* 3470c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3471c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3472c8fd8373SCédric Le Goater */ 3473c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3474c8fd8373SCédric Le Goater /* 3475c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3476c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3477c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3478c8fd8373SCédric Le Goater * complain to the user. 3479c8fd8373SCédric Le Goater */ 3480c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3481c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 34822c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3483c8fd8373SCédric Le Goater } else { 3484c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3485c8fd8373SCédric Le Goater } 3486c8fd8373SCédric Le Goater } 3487c8fd8373SCédric Le Goater 3488c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3489fcf5ef2aSThomas Huth } 3490fcf5ef2aSThomas Huth 3491fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3492fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3493fcf5ef2aSThomas Huth { 3494fcf5ef2aSThomas Huth TCGv_i32 t; 3495fcf5ef2aSThomas Huth TCGLabel *l; 3496fcf5ef2aSThomas Huth 3497fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3498fcf5ef2aSThomas Huth return; 3499fcf5ef2aSThomas Huth } 3500fcf5ef2aSThomas Huth l = gen_new_label(); 3501fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3502fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3503fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3504fcf5ef2aSThomas Huth if (global) { 3505fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3506fcf5ef2aSThomas Huth } else { 3507fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3508fcf5ef2aSThomas Huth } 3509fcf5ef2aSThomas Huth gen_set_label(l); 3510fcf5ef2aSThomas Huth } 3511fcf5ef2aSThomas Huth #else 3512fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3513fcf5ef2aSThomas Huth #endif 3514fcf5ef2aSThomas Huth 3515fcf5ef2aSThomas Huth /* isync */ 3516fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3517fcf5ef2aSThomas Huth { 3518fcf5ef2aSThomas Huth /* 3519fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3520fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3521fcf5ef2aSThomas Huth */ 3522fcf5ef2aSThomas Huth if (!ctx->pr) { 3523fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3524fcf5ef2aSThomas Huth } 35254771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3526d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3527fcf5ef2aSThomas Huth } 3528fcf5ef2aSThomas Huth 3529fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3530fcf5ef2aSThomas Huth 353114776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 35322a4e6c1bSRichard Henderson { 35332a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 35342a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 35352a4e6c1bSRichard Henderson 35362a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 35372a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 35382a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 35392a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 3540392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 35412a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 35422a4e6c1bSRichard Henderson } 35432a4e6c1bSRichard Henderson 3544fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3545fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3546fcf5ef2aSThomas Huth { \ 35472a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3548fcf5ef2aSThomas Huth } 3549fcf5ef2aSThomas Huth 3550fcf5ef2aSThomas Huth /* lwarx */ 3551fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3552fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3553fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3554fcf5ef2aSThomas Huth 355514776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 355620923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 355720923c1dSRichard Henderson { 355820923c1dSRichard Henderson TCGv t = tcg_temp_new(); 355920923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 356020923c1dSRichard Henderson TCGv u = tcg_temp_new(); 356120923c1dSRichard Henderson 356220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 356320923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 356420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 356520923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 356620923c1dSRichard Henderson 356720923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 356820923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 356920923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 357020923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 357120923c1dSRichard Henderson 357220923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 357320923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 357420923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 357520923c1dSRichard Henderson } 357620923c1dSRichard Henderson 357714776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 357820ba8504SRichard Henderson { 357920ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 358020ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 358120923c1dSRichard Henderson int rt = rD(ctx->opcode); 358220923c1dSRichard Henderson bool need_serial; 358320ba8504SRichard Henderson TCGv src, dst; 358420ba8504SRichard Henderson 358520ba8504SRichard Henderson gen_addr_register(ctx, EA); 358620923c1dSRichard Henderson dst = cpu_gpr[rt]; 358720923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 358820ba8504SRichard Henderson 358920923c1dSRichard Henderson need_serial = false; 359020ba8504SRichard Henderson memop |= MO_ALIGN; 359120ba8504SRichard Henderson switch (gpr_FC) { 359220ba8504SRichard Henderson case 0: /* Fetch and add */ 359320ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 359420ba8504SRichard Henderson break; 359520ba8504SRichard Henderson case 1: /* Fetch and xor */ 359620ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 359720ba8504SRichard Henderson break; 359820ba8504SRichard Henderson case 2: /* Fetch and or */ 359920ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 360020ba8504SRichard Henderson break; 360120ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 360220ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 360320ba8504SRichard Henderson break; 3604b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3605b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3606b8ce0f86SRichard Henderson break; 3607b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3608b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3609b8ce0f86SRichard Henderson break; 3610b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3611b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3612b8ce0f86SRichard Henderson break; 3613b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3614b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3615b8ce0f86SRichard Henderson break; 361620ba8504SRichard Henderson case 8: /* Swap */ 361720ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 361820ba8504SRichard Henderson break; 361920923c1dSRichard Henderson 362020923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 362120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 362220923c1dSRichard Henderson need_serial = true; 362320923c1dSRichard Henderson } else { 362420923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 362520923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 362620923c1dSRichard Henderson 362720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 362820923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 362920923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 363020923c1dSRichard Henderson } else { 363120923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 363220923c1dSRichard Henderson } 363320923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 363420923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 363520923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 363620923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 363720923c1dSRichard Henderson } 363820ba8504SRichard Henderson break; 363920923c1dSRichard Henderson 364020923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 364120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 364220923c1dSRichard Henderson need_serial = true; 364320923c1dSRichard Henderson } else { 364420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 364520923c1dSRichard Henderson } 364620923c1dSRichard Henderson break; 364720923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 364820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 364920923c1dSRichard Henderson need_serial = true; 365020923c1dSRichard Henderson } else { 365120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 365220923c1dSRichard Henderson } 365320923c1dSRichard Henderson break; 365420923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 365520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 365620923c1dSRichard Henderson need_serial = true; 365720923c1dSRichard Henderson } else { 365820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 365920923c1dSRichard Henderson } 366020923c1dSRichard Henderson break; 366120923c1dSRichard Henderson 366220ba8504SRichard Henderson default: 366320ba8504SRichard Henderson /* invoke data storage error handler */ 366420ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 366520ba8504SRichard Henderson } 366620923c1dSRichard Henderson 366720923c1dSRichard Henderson if (need_serial) { 366820923c1dSRichard Henderson /* Restart with exclusive lock. */ 366920923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 367020923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 367120923c1dSRichard Henderson } 3672a68a6146SBalamuruhan S } 3673a68a6146SBalamuruhan S 367420ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 367520ba8504SRichard Henderson { 367620ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 367720ba8504SRichard Henderson } 367820ba8504SRichard Henderson 367920ba8504SRichard Henderson #ifdef TARGET_PPC64 368020ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 368120ba8504SRichard Henderson { 3682fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 368320ba8504SRichard Henderson } 3684a68a6146SBalamuruhan S #endif 3685a68a6146SBalamuruhan S 368614776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 36879deb041cSRichard Henderson { 36889deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 36899deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 36909deb041cSRichard Henderson TCGv src, discard; 36919deb041cSRichard Henderson 36929deb041cSRichard Henderson gen_addr_register(ctx, EA); 36939deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 36949deb041cSRichard Henderson discard = tcg_temp_new(); 36959deb041cSRichard Henderson 36969deb041cSRichard Henderson memop |= MO_ALIGN; 36979deb041cSRichard Henderson switch (gpr_FC) { 36989deb041cSRichard Henderson case 0: /* add and Store */ 36999deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37009deb041cSRichard Henderson break; 37019deb041cSRichard Henderson case 1: /* xor and Store */ 37029deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37039deb041cSRichard Henderson break; 37049deb041cSRichard Henderson case 2: /* Or and Store */ 37059deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37069deb041cSRichard Henderson break; 37079deb041cSRichard Henderson case 3: /* 'and' and Store */ 37089deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37099deb041cSRichard Henderson break; 37109deb041cSRichard Henderson case 4: /* Store max unsigned */ 3711b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3712b8ce0f86SRichard Henderson break; 37139deb041cSRichard Henderson case 5: /* Store max signed */ 3714b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3715b8ce0f86SRichard Henderson break; 37169deb041cSRichard Henderson case 6: /* Store min unsigned */ 3717b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3718b8ce0f86SRichard Henderson break; 37199deb041cSRichard Henderson case 7: /* Store min signed */ 3720b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3721b8ce0f86SRichard Henderson break; 37229deb041cSRichard Henderson case 24: /* Store twin */ 37237fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 37247fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 37257fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 37267fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 37277fbc2b20SRichard Henderson } else { 37287fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 37297fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 37307fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 37317fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 37327fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 37337fbc2b20SRichard Henderson 37347fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 37357fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 37367fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 37377fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 37387fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 37397fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 37407fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 37417fbc2b20SRichard Henderson } 37429deb041cSRichard Henderson break; 37439deb041cSRichard Henderson default: 37449deb041cSRichard Henderson /* invoke data storage error handler */ 37459deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 37469deb041cSRichard Henderson } 3747a3401188SBalamuruhan S } 3748a3401188SBalamuruhan S 37499deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 37509deb041cSRichard Henderson { 37519deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 37529deb041cSRichard Henderson } 37539deb041cSRichard Henderson 37549deb041cSRichard Henderson #ifdef TARGET_PPC64 37559deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 37569deb041cSRichard Henderson { 3757fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 37589deb041cSRichard Henderson } 3759a3401188SBalamuruhan S #endif 3760a3401188SBalamuruhan S 376114776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3762fcf5ef2aSThomas Huth { 376321ee07e7SNicholas Piggin TCGLabel *lfail; 376421ee07e7SNicholas Piggin TCGv EA; 376521ee07e7SNicholas Piggin TCGv cr0; 376621ee07e7SNicholas Piggin TCGv t0; 376721ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3768fcf5ef2aSThomas Huth 376921ee07e7SNicholas Piggin lfail = gen_new_label(); 377021ee07e7SNicholas Piggin EA = tcg_temp_new(); 377121ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3772253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 377321ee07e7SNicholas Piggin 377421ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 377521ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 377621ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 377721ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 377821ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 377921ee07e7SNicholas Piggin 3780253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 378121ee07e7SNicholas Piggin cpu_gpr[rs], ctx->mem_idx, 3782253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3783253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3784253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 378521ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3786253ce7b2SNikunj A Dadhania 378721ee07e7SNicholas Piggin gen_set_label(lfail); 378821ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3789fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3790fcf5ef2aSThomas Huth } 3791fcf5ef2aSThomas Huth 3792fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3793fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3794fcf5ef2aSThomas Huth { \ 3795d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3796fcf5ef2aSThomas Huth } 3797fcf5ef2aSThomas Huth 3798fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3799fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3800fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3801fcf5ef2aSThomas Huth 3802fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3803fcf5ef2aSThomas Huth /* ldarx */ 3804fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3805fcf5ef2aSThomas Huth /* stdcx. */ 3806fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3807fcf5ef2aSThomas Huth 3808fcf5ef2aSThomas Huth /* lqarx */ 3809fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3810fcf5ef2aSThomas Huth { 3811fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 381294bf2658SRichard Henderson TCGv EA, hi, lo; 381357b38ffdSRichard Henderson TCGv_i128 t16; 3814fcf5ef2aSThomas Huth 3815fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3816fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3817fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3818fcf5ef2aSThomas Huth return; 3819fcf5ef2aSThomas Huth } 3820fcf5ef2aSThomas Huth 3821fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 382294bf2658SRichard Henderson EA = tcg_temp_new(); 3823fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 382494bf2658SRichard Henderson 382594bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 382694bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 382794bf2658SRichard Henderson hi = cpu_gpr[rd]; 382894bf2658SRichard Henderson 382957b38ffdSRichard Henderson t16 = tcg_temp_new_i128(); 383057b38ffdSRichard Henderson tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 383157b38ffdSRichard Henderson tcg_gen_extr_i128_i64(lo, hi, t16); 383294bf2658SRichard Henderson 3833e025e8f5SNicholas Piggin tcg_gen_mov_tl(cpu_reserve, EA); 3834392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, 16); 383594bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 383694bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3837fcf5ef2aSThomas Huth } 3838fcf5ef2aSThomas Huth 3839fcf5ef2aSThomas Huth /* stqcx. */ 3840fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3841fcf5ef2aSThomas Huth { 384221ee07e7SNicholas Piggin TCGLabel *lfail; 3843894448aeSRichard Henderson TCGv EA, t0, t1; 384421ee07e7SNicholas Piggin TCGv cr0; 3845894448aeSRichard Henderson TCGv_i128 cmp, val; 384621ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3847fcf5ef2aSThomas Huth 38484a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3849fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3850fcf5ef2aSThomas Huth return; 3851fcf5ef2aSThomas Huth } 38524a9b3c5dSRichard Henderson 385321ee07e7SNicholas Piggin lfail = gen_new_label(); 38544a9b3c5dSRichard Henderson EA = tcg_temp_new(); 385521ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3856fcf5ef2aSThomas Huth 385721ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 385821ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 385921ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 386021ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 386121ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 38624a9b3c5dSRichard Henderson 3863894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 3864894448aeSRichard Henderson val = tcg_temp_new_i128(); 38654a9b3c5dSRichard Henderson 3866894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 38674a9b3c5dSRichard Henderson 3868894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3869894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 38704a9b3c5dSRichard Henderson 3871894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3872894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 3873894448aeSRichard Henderson 3874894448aeSRichard Henderson t0 = tcg_temp_new(); 3875894448aeSRichard Henderson t1 = tcg_temp_new(); 3876894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 3877894448aeSRichard Henderson 3878894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3879894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3880894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 3881894448aeSRichard Henderson 3882894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3883894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 388421ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3885894448aeSRichard Henderson 388621ee07e7SNicholas Piggin gen_set_label(lfail); 388721ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 38884a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 38894a9b3c5dSRichard Henderson } 3890fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3891fcf5ef2aSThomas Huth 3892fcf5ef2aSThomas Huth /* sync */ 3893fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3894fcf5ef2aSThomas Huth { 389503abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 3896fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3897fcf5ef2aSThomas Huth 389803abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 389903abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 390003abfd90SNicholas Piggin } 390103abfd90SNicholas Piggin 3902fcf5ef2aSThomas Huth /* 3903fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3904fcf5ef2aSThomas Huth * 3905fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3906fcf5ef2aSThomas Huth * 3907fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3908fcf5ef2aSThomas Huth * check MSR_PR as well. 3909fcf5ef2aSThomas Huth */ 3910fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3911fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3912fcf5ef2aSThomas Huth } 391303abfd90SNicholas Piggin 391403abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 3915fcf5ef2aSThomas Huth } 3916fcf5ef2aSThomas Huth 3917fcf5ef2aSThomas Huth /* wait */ 3918fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3919fcf5ef2aSThomas Huth { 39200c9717ffSNicholas Piggin uint32_t wc; 39210c9717ffSNicholas Piggin 39220c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 39230c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 39240c9717ffSNicholas Piggin 39250c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 39260c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 39270c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39280c9717ffSNicholas Piggin } else { 39290c9717ffSNicholas Piggin wc = 0; 39300c9717ffSNicholas Piggin } 39310c9717ffSNicholas Piggin 39320c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 39330c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 39340c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39350c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 39360c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 39370c9717ffSNicholas Piggin 39380c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 39390c9717ffSNicholas Piggin if (wc == 3) { 39400c9717ffSNicholas Piggin gen_invalid(ctx); 39410c9717ffSNicholas Piggin return; 39420c9717ffSNicholas Piggin } 39430c9717ffSNicholas Piggin 39440c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 39450c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 39460c9717ffSNicholas Piggin gen_invalid(ctx); 39470c9717ffSNicholas Piggin return; 39480c9717ffSNicholas Piggin } 39490c9717ffSNicholas Piggin 39500c9717ffSNicholas Piggin } else { /* ISA300 */ 39510c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 39520c9717ffSNicholas Piggin if (wc > 0) { 39530c9717ffSNicholas Piggin gen_invalid(ctx); 39540c9717ffSNicholas Piggin return; 39550c9717ffSNicholas Piggin } 39560c9717ffSNicholas Piggin } 39570c9717ffSNicholas Piggin 39580c9717ffSNicholas Piggin } else { 39590c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 39600c9717ffSNicholas Piggin gen_invalid(ctx); 39610c9717ffSNicholas Piggin return; 39620c9717ffSNicholas Piggin } 39630c9717ffSNicholas Piggin 39640c9717ffSNicholas Piggin /* 39650c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 39660c9717ffSNicholas Piggin * to occur. 39670c9717ffSNicholas Piggin */ 39680c9717ffSNicholas Piggin if (wc == 0) { 39697058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(1); 3970fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3971fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3972fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3973b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3974fcf5ef2aSThomas Huth } 3975fcf5ef2aSThomas Huth 39760c9717ffSNicholas Piggin /* 39770c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 39780c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 39790c9717ffSNicholas Piggin * 39800c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 39810c9717ffSNicholas Piggin * no-ops. 39820c9717ffSNicholas Piggin * 39830c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 39840c9717ffSNicholas Piggin * 39850c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 39860c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 39870c9717ffSNicholas Piggin * 39880c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 39890c9717ffSNicholas Piggin * 39900c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 39910c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 39920c9717ffSNicholas Piggin * can be implemented as a no-op. 39930c9717ffSNicholas Piggin * 39940c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 39950c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 39960c9717ffSNicholas Piggin * no-op. 39970c9717ffSNicholas Piggin * 39980c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 39990c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 40000c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 40010c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 40020c9717ffSNicholas Piggin * (if suboptimal). 40030c9717ffSNicholas Piggin */ 40040c9717ffSNicholas Piggin } 40050c9717ffSNicholas Piggin 4006fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4007fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4008fcf5ef2aSThomas Huth { 4009fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40109f0cf041SMatheus Ferst GEN_PRIV(ctx); 4011fcf5ef2aSThomas Huth #else 4012fcf5ef2aSThomas Huth TCGv_i32 t; 4013fcf5ef2aSThomas Huth 40149f0cf041SMatheus Ferst CHK_HV(ctx); 40157058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_DOZE); 4016fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4017154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4018154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4019fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4020fcf5ef2aSThomas Huth } 4021fcf5ef2aSThomas Huth 4022fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4023fcf5ef2aSThomas Huth { 4024fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40259f0cf041SMatheus Ferst GEN_PRIV(ctx); 4026fcf5ef2aSThomas Huth #else 4027fcf5ef2aSThomas Huth TCGv_i32 t; 4028fcf5ef2aSThomas Huth 40299f0cf041SMatheus Ferst CHK_HV(ctx); 40307058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_NAP); 4031fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4032154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4033154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4034fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4035fcf5ef2aSThomas Huth } 4036fcf5ef2aSThomas Huth 4037cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4038cdee0e72SNikunj A Dadhania { 403921c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 40409f0cf041SMatheus Ferst GEN_PRIV(ctx); 404121c0d66aSBenjamin Herrenschmidt #else 404221c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 404321c0d66aSBenjamin Herrenschmidt 40449f0cf041SMatheus Ferst CHK_HV(ctx); 40457058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_STOP); 404621c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 404721c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 404821c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 404921c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4050cdee0e72SNikunj A Dadhania } 4051cdee0e72SNikunj A Dadhania 4052fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4053fcf5ef2aSThomas Huth { 4054fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40559f0cf041SMatheus Ferst GEN_PRIV(ctx); 4056fcf5ef2aSThomas Huth #else 4057fcf5ef2aSThomas Huth TCGv_i32 t; 4058fcf5ef2aSThomas Huth 40599f0cf041SMatheus Ferst CHK_HV(ctx); 40607058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_SLEEP); 4061fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4062154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4063154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4064fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4065fcf5ef2aSThomas Huth } 4066fcf5ef2aSThomas Huth 4067fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4068fcf5ef2aSThomas Huth { 4069fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40709f0cf041SMatheus Ferst GEN_PRIV(ctx); 4071fcf5ef2aSThomas Huth #else 4072fcf5ef2aSThomas Huth TCGv_i32 t; 4073fcf5ef2aSThomas Huth 40749f0cf041SMatheus Ferst CHK_HV(ctx); 40757058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_RVWINKLE); 4076fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4077154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4078154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4079fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4080fcf5ef2aSThomas Huth } 4081fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4082fcf5ef2aSThomas Huth 4083fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4084fcf5ef2aSThomas Huth { 4085fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4086efe843d8SDavid Gibson if (ctx->has_cfar) { 4087fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4088efe843d8SDavid Gibson } 4089fcf5ef2aSThomas Huth #endif 4090fcf5ef2aSThomas Huth } 4091fcf5ef2aSThomas Huth 409246d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 409346d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 409446d396bdSDaniel Henrique Barboza { 409546d396bdSDaniel Henrique Barboza /* 409646d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 409746d396bdSDaniel Henrique Barboza * instructions. 409846d396bdSDaniel Henrique Barboza */ 409946d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 410046d396bdSDaniel Henrique Barboza return; 410146d396bdSDaniel Henrique Barboza } 410246d396bdSDaniel Henrique Barboza 410346d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4104eeaaefe9SLeandro Lupori TCGLabel *l; 4105eeaaefe9SLeandro Lupori TCGv t0; 4106eeaaefe9SLeandro Lupori 410746d396bdSDaniel Henrique Barboza /* 410846d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 410946d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 411046d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 411146d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 411246d396bdSDaniel Henrique Barboza */ 4113283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 411446d396bdSDaniel Henrique Barboza 4115eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4116eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4117eeaaefe9SLeandro Lupori l = gen_new_label(); 4118eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4119eeaaefe9SLeandro Lupori 4120eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4121eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4122eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4123eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4124eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4125eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4126eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4127eeaaefe9SLeandro Lupori } 4128eeaaefe9SLeandro Lupori 4129eeaaefe9SLeandro Lupori gen_set_label(l); 4130eeaaefe9SLeandro Lupori } else { 413146d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4132eeaaefe9SLeandro Lupori } 413346d396bdSDaniel Henrique Barboza #else 413446d396bdSDaniel Henrique Barboza /* 413546d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 413646d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 413746d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 413846d396bdSDaniel Henrique Barboza */ 413946d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 414046d396bdSDaniel Henrique Barboza 414146d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 414246d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 414346d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 414446d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 414546d396bdSDaniel Henrique Barboza } 414646d396bdSDaniel Henrique Barboza #else 414746d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 414846d396bdSDaniel Henrique Barboza { 414946d396bdSDaniel Henrique Barboza return; 415046d396bdSDaniel Henrique Barboza } 415146d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 415246d396bdSDaniel Henrique Barboza 4153fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4154fcf5ef2aSThomas Huth { 41556e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4156fcf5ef2aSThomas Huth } 4157fcf5ef2aSThomas Huth 41580e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 41590e3bf489SRoman Kapl { 41609498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 41610e3bf489SRoman Kapl gen_debug_exception(ctx); 41620e3bf489SRoman Kapl } else { 416346d396bdSDaniel Henrique Barboza /* 416446d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 416546d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 416646d396bdSDaniel Henrique Barboza */ 416746d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 416846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 416946d396bdSDaniel Henrique Barboza } 417046d396bdSDaniel Henrique Barboza 41710e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 41720e3bf489SRoman Kapl } 41730e3bf489SRoman Kapl } 41740e3bf489SRoman Kapl 4175fcf5ef2aSThomas Huth /*** Branch ***/ 4176c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4177fcf5ef2aSThomas Huth { 4178fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4179fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4180fcf5ef2aSThomas Huth } 4181fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 418246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4183fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4184fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 418507ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4186fcf5ef2aSThomas Huth } else { 4187fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 41880e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4189fcf5ef2aSThomas Huth } 4190fcf5ef2aSThomas Huth } 4191fcf5ef2aSThomas Huth 4192fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4193fcf5ef2aSThomas Huth { 4194fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4195fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4196fcf5ef2aSThomas Huth } 4197fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4198fcf5ef2aSThomas Huth } 4199fcf5ef2aSThomas Huth 4200fcf5ef2aSThomas Huth /* b ba bl bla */ 4201fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4202fcf5ef2aSThomas Huth { 4203fcf5ef2aSThomas Huth target_ulong li, target; 4204fcf5ef2aSThomas Huth 4205fcf5ef2aSThomas Huth /* sign extend LI */ 4206fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4207fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4208fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42092c2bcb1bSRichard Henderson target = ctx->cia + li; 4210fcf5ef2aSThomas Huth } else { 4211fcf5ef2aSThomas Huth target = li; 4212fcf5ef2aSThomas Huth } 4213fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4214b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4215fcf5ef2aSThomas Huth } 42162c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4217fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 42186086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4219fcf5ef2aSThomas Huth } 4220fcf5ef2aSThomas Huth 4221fcf5ef2aSThomas Huth #define BCOND_IM 0 4222fcf5ef2aSThomas Huth #define BCOND_LR 1 4223fcf5ef2aSThomas Huth #define BCOND_CTR 2 4224fcf5ef2aSThomas Huth #define BCOND_TAR 3 4225fcf5ef2aSThomas Huth 4226c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4227fcf5ef2aSThomas Huth { 4228fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4229fcf5ef2aSThomas Huth TCGLabel *l1; 4230fcf5ef2aSThomas Huth TCGv target; 42310e3bf489SRoman Kapl 4232fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 42339723281fSRichard Henderson target = tcg_temp_new(); 4234efe843d8SDavid Gibson if (type == BCOND_CTR) { 4235fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4236efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4237fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4238efe843d8SDavid Gibson } else { 4239fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4240efe843d8SDavid Gibson } 4241fcf5ef2aSThomas Huth } else { 4242f764718dSRichard Henderson target = NULL; 4243fcf5ef2aSThomas Huth } 4244efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4245b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4246efe843d8SDavid Gibson } 4247fcf5ef2aSThomas Huth l1 = gen_new_label(); 4248fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4249fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4250fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4251fa200c95SGreg Kurz 4252fa200c95SGreg Kurz if (type == BCOND_CTR) { 4253fa200c95SGreg Kurz /* 4254fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4255fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4256fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 425715d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 425815d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 425915d68c5eSGreg Kurz * it basically useless and thus never used in real code. 426015d68c5eSGreg Kurz * 426115d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 426215d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 426315d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 426415d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 426515d68c5eSGreg Kurz * doing anything else harmful. 4266fa200c95SGreg Kurz */ 4267d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4268fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4269fcf5ef2aSThomas Huth return; 4270fcf5ef2aSThomas Huth } 4271fa200c95SGreg Kurz 4272fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4273fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4274fa200c95SGreg Kurz } else { 4275fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4276fa200c95SGreg Kurz } 4277fa200c95SGreg Kurz if (bo & 0x2) { 4278fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4279fa200c95SGreg Kurz } else { 4280fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4281fa200c95SGreg Kurz } 4282fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4283fa200c95SGreg Kurz } else { 4284fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4285fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4286fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4287fcf5ef2aSThomas Huth } else { 4288fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4289fcf5ef2aSThomas Huth } 4290fcf5ef2aSThomas Huth if (bo & 0x2) { 4291fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4292fcf5ef2aSThomas Huth } else { 4293fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4294fcf5ef2aSThomas Huth } 4295fa200c95SGreg Kurz } 4296fcf5ef2aSThomas Huth } 4297fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4298fcf5ef2aSThomas Huth /* Test CR */ 4299fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4300fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4301fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4302fcf5ef2aSThomas Huth 4303fcf5ef2aSThomas Huth if (bo & 0x8) { 4304fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4305fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4306fcf5ef2aSThomas Huth } else { 4307fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4308fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4309fcf5ef2aSThomas Huth } 4310fcf5ef2aSThomas Huth } 43112c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4312fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4313fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4314fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43152c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4316fcf5ef2aSThomas Huth } else { 4317fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4318fcf5ef2aSThomas Huth } 4319fcf5ef2aSThomas Huth } else { 4320fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4321fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4322fcf5ef2aSThomas Huth } else { 4323fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4324fcf5ef2aSThomas Huth } 43250e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4326c4a2e3a9SRichard Henderson } 4327fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 43280e3bf489SRoman Kapl /* fallthrough case */ 4329fcf5ef2aSThomas Huth gen_set_label(l1); 4330b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4331fcf5ef2aSThomas Huth } 43326086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4333fcf5ef2aSThomas Huth } 4334fcf5ef2aSThomas Huth 4335fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4336fcf5ef2aSThomas Huth { 4337fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4338fcf5ef2aSThomas Huth } 4339fcf5ef2aSThomas Huth 4340fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4341fcf5ef2aSThomas Huth { 4342fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4343fcf5ef2aSThomas Huth } 4344fcf5ef2aSThomas Huth 4345fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4346fcf5ef2aSThomas Huth { 4347fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4348fcf5ef2aSThomas Huth } 4349fcf5ef2aSThomas Huth 4350fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4351fcf5ef2aSThomas Huth { 4352fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4353fcf5ef2aSThomas Huth } 4354fcf5ef2aSThomas Huth 4355fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4356fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4357fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4358fcf5ef2aSThomas Huth { \ 4359fcf5ef2aSThomas Huth uint8_t bitmask; \ 4360fcf5ef2aSThomas Huth int sh; \ 4361fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4362fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4363fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4364fcf5ef2aSThomas Huth if (sh > 0) \ 4365fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4366fcf5ef2aSThomas Huth else if (sh < 0) \ 4367fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4368fcf5ef2aSThomas Huth else \ 4369fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4370fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4371fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4372fcf5ef2aSThomas Huth if (sh > 0) \ 4373fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4374fcf5ef2aSThomas Huth else if (sh < 0) \ 4375fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4376fcf5ef2aSThomas Huth else \ 4377fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4378fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4379fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4380fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4381fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4382fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4383fcf5ef2aSThomas Huth } 4384fcf5ef2aSThomas Huth 4385fcf5ef2aSThomas Huth /* crand */ 4386fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4387fcf5ef2aSThomas Huth /* crandc */ 4388fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4389fcf5ef2aSThomas Huth /* creqv */ 4390fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4391fcf5ef2aSThomas Huth /* crnand */ 4392fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4393fcf5ef2aSThomas Huth /* crnor */ 4394fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4395fcf5ef2aSThomas Huth /* cror */ 4396fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4397fcf5ef2aSThomas Huth /* crorc */ 4398fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4399fcf5ef2aSThomas Huth /* crxor */ 4400fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4401fcf5ef2aSThomas Huth 4402fcf5ef2aSThomas Huth /* mcrf */ 4403fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4404fcf5ef2aSThomas Huth { 4405fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4406fcf5ef2aSThomas Huth } 4407fcf5ef2aSThomas Huth 4408fcf5ef2aSThomas Huth /*** System linkage ***/ 4409fcf5ef2aSThomas Huth 4410fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4411fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4412fcf5ef2aSThomas Huth { 4413fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44149f0cf041SMatheus Ferst GEN_PRIV(ctx); 4415fcf5ef2aSThomas Huth #else 4416efe843d8SDavid Gibson /* 4417efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4418fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4419fcf5ef2aSThomas Huth */ 4420d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4421fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4422fcf5ef2aSThomas Huth return; 4423fcf5ef2aSThomas Huth } 4424fcf5ef2aSThomas Huth /* Restore CPU state */ 44259f0cf041SMatheus Ferst CHK_SV(ctx); 4426283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44272c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4428fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 442959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4430fcf5ef2aSThomas Huth #endif 4431fcf5ef2aSThomas Huth } 4432fcf5ef2aSThomas Huth 4433fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4434fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4435fcf5ef2aSThomas Huth { 4436fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44379f0cf041SMatheus Ferst GEN_PRIV(ctx); 4438fcf5ef2aSThomas Huth #else 4439fcf5ef2aSThomas Huth /* Restore CPU state */ 44409f0cf041SMatheus Ferst CHK_SV(ctx); 4441283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44422c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4443fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 444459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4445fcf5ef2aSThomas Huth #endif 4446fcf5ef2aSThomas Huth } 4447fcf5ef2aSThomas Huth 44483c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44493c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 44503c89b8d6SNicholas Piggin { 44513c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 44529f0cf041SMatheus Ferst GEN_PRIV(ctx); 44533c89b8d6SNicholas Piggin #else 44543c89b8d6SNicholas Piggin /* Restore CPU state */ 44559f0cf041SMatheus Ferst CHK_SV(ctx); 4456283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44572c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 44583c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 445959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 44603c89b8d6SNicholas Piggin #endif 44613c89b8d6SNicholas Piggin } 44623c89b8d6SNicholas Piggin #endif 44633c89b8d6SNicholas Piggin 4464fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4465fcf5ef2aSThomas Huth { 4466fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44679f0cf041SMatheus Ferst GEN_PRIV(ctx); 4468fcf5ef2aSThomas Huth #else 4469fcf5ef2aSThomas Huth /* Restore CPU state */ 44709f0cf041SMatheus Ferst CHK_HV(ctx); 4471fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 447259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4473fcf5ef2aSThomas Huth #endif 4474fcf5ef2aSThomas Huth } 4475fcf5ef2aSThomas Huth #endif 4476fcf5ef2aSThomas Huth 4477fcf5ef2aSThomas Huth /* sc */ 4478fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4479fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4480fcf5ef2aSThomas Huth #else 4481fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 44823c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4483fcf5ef2aSThomas Huth #endif 4484fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4485fcf5ef2aSThomas Huth { 4486fcf5ef2aSThomas Huth uint32_t lev; 4487fcf5ef2aSThomas Huth 4488984eda58SNicholas Piggin /* 4489984eda58SNicholas Piggin * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4490984eda58SNicholas Piggin * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4491984eda58SNicholas Piggin * for Ultravisor which TCG does not support, so just ignore the top 6. 4492984eda58SNicholas Piggin */ 4493984eda58SNicholas Piggin lev = (ctx->opcode >> 5) & 0x1; 4494fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4495fcf5ef2aSThomas Huth } 4496fcf5ef2aSThomas Huth 44973c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 44983c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44993c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 45003c89b8d6SNicholas Piggin { 4501f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 45023c89b8d6SNicholas Piggin 4503f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 45042c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4505f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 45063c89b8d6SNicholas Piggin 45077a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 45083c89b8d6SNicholas Piggin } 45093c89b8d6SNicholas Piggin #endif 45103c89b8d6SNicholas Piggin #endif 45113c89b8d6SNicholas Piggin 4512fcf5ef2aSThomas Huth /*** Trap ***/ 4513fcf5ef2aSThomas Huth 4514fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4515fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4516fcf5ef2aSThomas Huth { 4517fcf5ef2aSThomas Huth /* Trap never */ 4518fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4519fcf5ef2aSThomas Huth return true; 4520fcf5ef2aSThomas Huth } 4521fcf5ef2aSThomas Huth /* Trap always */ 4522fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4523fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4524fcf5ef2aSThomas Huth return true; 4525fcf5ef2aSThomas Huth } 4526fcf5ef2aSThomas Huth return false; 4527fcf5ef2aSThomas Huth } 4528fcf5ef2aSThomas Huth 4529fcf5ef2aSThomas Huth /* tw */ 4530fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4531fcf5ef2aSThomas Huth { 4532fcf5ef2aSThomas Huth TCGv_i32 t0; 4533fcf5ef2aSThomas Huth 4534fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4535fcf5ef2aSThomas Huth return; 4536fcf5ef2aSThomas Huth } 45377058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4538fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4539fcf5ef2aSThomas Huth t0); 4540fcf5ef2aSThomas Huth } 4541fcf5ef2aSThomas Huth 4542fcf5ef2aSThomas Huth /* twi */ 4543fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4544fcf5ef2aSThomas Huth { 4545fcf5ef2aSThomas Huth TCGv t0; 4546fcf5ef2aSThomas Huth TCGv_i32 t1; 4547fcf5ef2aSThomas Huth 4548fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4549fcf5ef2aSThomas Huth return; 4550fcf5ef2aSThomas Huth } 45517058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45527058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4553fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4554fcf5ef2aSThomas Huth } 4555fcf5ef2aSThomas Huth 4556fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4557fcf5ef2aSThomas Huth /* td */ 4558fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4559fcf5ef2aSThomas Huth { 4560fcf5ef2aSThomas Huth TCGv_i32 t0; 4561fcf5ef2aSThomas Huth 4562fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4563fcf5ef2aSThomas Huth return; 4564fcf5ef2aSThomas Huth } 45657058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4566fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4567fcf5ef2aSThomas Huth t0); 4568fcf5ef2aSThomas Huth } 4569fcf5ef2aSThomas Huth 4570fcf5ef2aSThomas Huth /* tdi */ 4571fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4572fcf5ef2aSThomas Huth { 4573fcf5ef2aSThomas Huth TCGv t0; 4574fcf5ef2aSThomas Huth TCGv_i32 t1; 4575fcf5ef2aSThomas Huth 4576fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4577fcf5ef2aSThomas Huth return; 4578fcf5ef2aSThomas Huth } 45797058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45807058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4581fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4582fcf5ef2aSThomas Huth } 4583fcf5ef2aSThomas Huth #endif 4584fcf5ef2aSThomas Huth 4585fcf5ef2aSThomas Huth /*** Processor control ***/ 4586fcf5ef2aSThomas Huth 4587fcf5ef2aSThomas Huth /* mcrxr */ 4588fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4589fcf5ef2aSThomas Huth { 4590fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4591fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4592fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4593fcf5ef2aSThomas Huth 4594fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4595fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4596fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4597fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4598fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4599fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4600fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4601fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4602fcf5ef2aSThomas Huth 4603fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4604fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4605fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4606fcf5ef2aSThomas Huth } 4607fcf5ef2aSThomas Huth 4608b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4609b63d0434SNikunj A Dadhania /* mcrxrx */ 4610b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4611b63d0434SNikunj A Dadhania { 4612b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4613b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4614b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4615b63d0434SNikunj A Dadhania 4616b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4617b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4618b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4619b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4620b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4621b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4622b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4623b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4624b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4625b63d0434SNikunj A Dadhania } 4626b63d0434SNikunj A Dadhania #endif 4627b63d0434SNikunj A Dadhania 4628fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4629fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4630fcf5ef2aSThomas Huth { 4631fcf5ef2aSThomas Huth uint32_t crm, crn; 4632fcf5ef2aSThomas Huth 4633fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4634fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4635fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4636fcf5ef2aSThomas Huth crn = ctz32(crm); 4637fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4638fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4639fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4640fcf5ef2aSThomas Huth } 4641fcf5ef2aSThomas Huth } else { 4642fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4643fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4644fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4645fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4646fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4647fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4648fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4649fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4650fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4651fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4652fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4653fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4654fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4655fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4656fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4657fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4658fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4659fcf5ef2aSThomas Huth } 4660fcf5ef2aSThomas Huth } 4661fcf5ef2aSThomas Huth 4662fcf5ef2aSThomas Huth /* mfmsr */ 4663fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4664fcf5ef2aSThomas Huth { 46659f0cf041SMatheus Ferst CHK_SV(ctx); 4666fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4667fcf5ef2aSThomas Huth } 4668fcf5ef2aSThomas Huth 4669fcf5ef2aSThomas Huth /* mfspr */ 4670fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4671fcf5ef2aSThomas Huth { 4672fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4673fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4674fcf5ef2aSThomas Huth 4675fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4676fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4677fcf5ef2aSThomas Huth #else 4678fcf5ef2aSThomas Huth if (ctx->pr) { 4679fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4680fcf5ef2aSThomas Huth } else if (ctx->hv) { 4681fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4682fcf5ef2aSThomas Huth } else { 4683fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4684fcf5ef2aSThomas Huth } 4685fcf5ef2aSThomas Huth #endif 4686fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4687fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4688fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4689fcf5ef2aSThomas Huth } else { 4690fcf5ef2aSThomas Huth /* Privilege exception */ 4691efe843d8SDavid Gibson /* 4692efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4693fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4694fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4695fcf5ef2aSThomas Huth */ 4696fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 469731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 469831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 46992c2bcb1bSRichard Henderson ctx->cia); 4700fcf5ef2aSThomas Huth } 4701fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4702fcf5ef2aSThomas Huth } 4703fcf5ef2aSThomas Huth } else { 4704fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4705fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4706fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4707fcf5ef2aSThomas Huth /* This is a nop */ 4708fcf5ef2aSThomas Huth return; 4709fcf5ef2aSThomas Huth } 4710fcf5ef2aSThomas Huth /* Not defined */ 471131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 471231085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 47132c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4714fcf5ef2aSThomas Huth 4715efe843d8SDavid Gibson /* 4716efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4717efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4718fcf5ef2aSThomas Huth */ 4719fcf5ef2aSThomas Huth if (sprn & 0x10) { 4720fcf5ef2aSThomas Huth if (ctx->pr) { 47211315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4722fcf5ef2aSThomas Huth } 4723fcf5ef2aSThomas Huth } else { 4724fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 47251315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4726fcf5ef2aSThomas Huth } 4727fcf5ef2aSThomas Huth } 4728fcf5ef2aSThomas Huth } 4729fcf5ef2aSThomas Huth } 4730fcf5ef2aSThomas Huth 4731fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4732fcf5ef2aSThomas Huth { 4733fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4734fcf5ef2aSThomas Huth } 4735fcf5ef2aSThomas Huth 4736fcf5ef2aSThomas Huth /* mftb */ 4737fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4738fcf5ef2aSThomas Huth { 4739fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4740fcf5ef2aSThomas Huth } 4741fcf5ef2aSThomas Huth 4742fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4743fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4744fcf5ef2aSThomas Huth { 4745fcf5ef2aSThomas Huth uint32_t crm, crn; 4746fcf5ef2aSThomas Huth 4747fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4748fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4749fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4750fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4751fcf5ef2aSThomas Huth crn = ctz32(crm); 4752fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4753fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4754fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4755fcf5ef2aSThomas Huth } 4756fcf5ef2aSThomas Huth } else { 4757fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4758fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4759fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4760fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4761fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4762fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4763fcf5ef2aSThomas Huth } 4764fcf5ef2aSThomas Huth } 4765fcf5ef2aSThomas Huth } 4766fcf5ef2aSThomas Huth } 4767fcf5ef2aSThomas Huth 4768fcf5ef2aSThomas Huth /* mtmsr */ 4769fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4770fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4771fcf5ef2aSThomas Huth { 4772caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4773caf590ddSNicholas Piggin gen_invalid(ctx); 4774caf590ddSNicholas Piggin return; 4775caf590ddSNicholas Piggin } 4776caf590ddSNicholas Piggin 47779f0cf041SMatheus Ferst CHK_SV(ctx); 4778fcf5ef2aSThomas Huth 4779fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 47806fa5726bSMatheus Ferst TCGv t0, t1; 47816fa5726bSMatheus Ferst target_ulong mask; 47826fa5726bSMatheus Ferst 47836fa5726bSMatheus Ferst t0 = tcg_temp_new(); 47846fa5726bSMatheus Ferst t1 = tcg_temp_new(); 47856fa5726bSMatheus Ferst 4786283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 47876fa5726bSMatheus Ferst 4788fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 47895ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 47906fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4791fcf5ef2aSThomas Huth } else { 47926fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 47936fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 47946fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4795efe843d8SDavid Gibson /* 4796efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4797efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4798efe843d8SDavid Gibson * ppc_store_msr 4799fcf5ef2aSThomas Huth */ 4800b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4801fcf5ef2aSThomas Huth } 48026fa5726bSMatheus Ferst 48036fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48046fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48056fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48066fa5726bSMatheus Ferst 48076fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48086fa5726bSMatheus Ferst 48095ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4810d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4811fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4812fcf5ef2aSThomas Huth } 4813fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4814fcf5ef2aSThomas Huth 4815fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4816fcf5ef2aSThomas Huth { 48179f0cf041SMatheus Ferst CHK_SV(ctx); 4818fcf5ef2aSThomas Huth 4819fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48206fa5726bSMatheus Ferst TCGv t0, t1; 48216fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 48226fa5726bSMatheus Ferst 48236fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48246fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48256fa5726bSMatheus Ferst 4826283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 4827fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48285ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48296fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4830fcf5ef2aSThomas Huth } else { 48316fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 48326fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4833fcf5ef2aSThomas Huth 4834efe843d8SDavid Gibson /* 4835efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4836efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4837efe843d8SDavid Gibson * ppc_store_msr 4838fcf5ef2aSThomas Huth */ 4839b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4840fcf5ef2aSThomas Huth } 48416fa5726bSMatheus Ferst 48426fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48436fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48446fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48456fa5726bSMatheus Ferst 48466fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48476fa5726bSMatheus Ferst 48485ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4849d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4850fcf5ef2aSThomas Huth #endif 4851fcf5ef2aSThomas Huth } 4852fcf5ef2aSThomas Huth 4853fcf5ef2aSThomas Huth /* mtspr */ 4854fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4855fcf5ef2aSThomas Huth { 4856fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4857fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4858fcf5ef2aSThomas Huth 4859fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4860fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4861fcf5ef2aSThomas Huth #else 4862fcf5ef2aSThomas Huth if (ctx->pr) { 4863fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4864fcf5ef2aSThomas Huth } else if (ctx->hv) { 4865fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4866fcf5ef2aSThomas Huth } else { 4867fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4868fcf5ef2aSThomas Huth } 4869fcf5ef2aSThomas Huth #endif 4870fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4871fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4872fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4873fcf5ef2aSThomas Huth } else { 4874fcf5ef2aSThomas Huth /* Privilege exception */ 487531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 487631085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48772c2bcb1bSRichard Henderson ctx->cia); 4878fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4879fcf5ef2aSThomas Huth } 4880fcf5ef2aSThomas Huth } else { 4881fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4882fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4883fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4884fcf5ef2aSThomas Huth /* This is a nop */ 4885fcf5ef2aSThomas Huth return; 4886fcf5ef2aSThomas Huth } 4887fcf5ef2aSThomas Huth 4888fcf5ef2aSThomas Huth /* Not defined */ 488931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 489031085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 48912c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4892fcf5ef2aSThomas Huth 4893fcf5ef2aSThomas Huth 4894efe843d8SDavid Gibson /* 4895efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4896efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4897fcf5ef2aSThomas Huth */ 4898fcf5ef2aSThomas Huth if (sprn & 0x10) { 4899fcf5ef2aSThomas Huth if (ctx->pr) { 49001315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4901fcf5ef2aSThomas Huth } 4902fcf5ef2aSThomas Huth } else { 4903fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 49041315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4905fcf5ef2aSThomas Huth } 4906fcf5ef2aSThomas Huth } 4907fcf5ef2aSThomas Huth } 4908fcf5ef2aSThomas Huth } 4909fcf5ef2aSThomas Huth 4910fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4911fcf5ef2aSThomas Huth /* setb */ 4912fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4913fcf5ef2aSThomas Huth { 4914fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 49156f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 49166f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 4917fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4918fcf5ef2aSThomas Huth 4919fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4920fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4921fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4922fcf5ef2aSThomas Huth } 4923fcf5ef2aSThomas Huth #endif 4924fcf5ef2aSThomas Huth 4925fcf5ef2aSThomas Huth /*** Cache management ***/ 4926fcf5ef2aSThomas Huth 4927fcf5ef2aSThomas Huth /* dcbf */ 4928fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4929fcf5ef2aSThomas Huth { 4930fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4931fcf5ef2aSThomas Huth TCGv t0; 4932fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4933fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4934fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4935fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4936fcf5ef2aSThomas Huth } 4937fcf5ef2aSThomas Huth 493850728199SRoman Kapl /* dcbfep (external PID dcbf) */ 493950728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 494050728199SRoman Kapl { 494150728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 494250728199SRoman Kapl TCGv t0; 49439f0cf041SMatheus Ferst CHK_SV(ctx); 494450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 494550728199SRoman Kapl t0 = tcg_temp_new(); 494650728199SRoman Kapl gen_addr_reg_index(ctx, t0); 494750728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 494850728199SRoman Kapl } 494950728199SRoman Kapl 4950fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4951fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4952fcf5ef2aSThomas Huth { 4953fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 49549f0cf041SMatheus Ferst GEN_PRIV(ctx); 4955fcf5ef2aSThomas Huth #else 4956fcf5ef2aSThomas Huth TCGv EA, val; 4957fcf5ef2aSThomas Huth 49589f0cf041SMatheus Ferst CHK_SV(ctx); 4959fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4960fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4961fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4962fcf5ef2aSThomas Huth val = tcg_temp_new(); 4963fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4964fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4965fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4966fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4967fcf5ef2aSThomas Huth } 4968fcf5ef2aSThomas Huth 4969fcf5ef2aSThomas Huth /* dcdst */ 4970fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4971fcf5ef2aSThomas Huth { 4972fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4973fcf5ef2aSThomas Huth TCGv t0; 4974fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4975fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4976fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4977fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4978fcf5ef2aSThomas Huth } 4979fcf5ef2aSThomas Huth 498050728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 498150728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 498250728199SRoman Kapl { 498350728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 498450728199SRoman Kapl TCGv t0; 498550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 498650728199SRoman Kapl t0 = tcg_temp_new(); 498750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 498850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 498950728199SRoman Kapl } 499050728199SRoman Kapl 4991fcf5ef2aSThomas Huth /* dcbt */ 4992fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4993fcf5ef2aSThomas Huth { 4994efe843d8SDavid Gibson /* 4995efe843d8SDavid Gibson * interpreted as no-op 4996efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4997efe843d8SDavid Gibson * does not generate any exception 4998fcf5ef2aSThomas Huth */ 4999fcf5ef2aSThomas Huth } 5000fcf5ef2aSThomas Huth 500150728199SRoman Kapl /* dcbtep */ 500250728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 500350728199SRoman Kapl { 5004efe843d8SDavid Gibson /* 5005efe843d8SDavid Gibson * interpreted as no-op 5006efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5007efe843d8SDavid Gibson * does not generate any exception 500850728199SRoman Kapl */ 500950728199SRoman Kapl } 501050728199SRoman Kapl 5011fcf5ef2aSThomas Huth /* dcbtst */ 5012fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5013fcf5ef2aSThomas Huth { 5014efe843d8SDavid Gibson /* 5015efe843d8SDavid Gibson * interpreted as no-op 5016efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5017efe843d8SDavid Gibson * does not generate any exception 5018fcf5ef2aSThomas Huth */ 5019fcf5ef2aSThomas Huth } 5020fcf5ef2aSThomas Huth 502150728199SRoman Kapl /* dcbtstep */ 502250728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 502350728199SRoman Kapl { 5024efe843d8SDavid Gibson /* 5025efe843d8SDavid Gibson * interpreted as no-op 5026efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5027efe843d8SDavid Gibson * does not generate any exception 502850728199SRoman Kapl */ 502950728199SRoman Kapl } 503050728199SRoman Kapl 5031fcf5ef2aSThomas Huth /* dcbtls */ 5032fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5033fcf5ef2aSThomas Huth { 5034fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5035fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5036fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5037fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5038fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5039fcf5ef2aSThomas Huth } 5040fcf5ef2aSThomas Huth 5041e64645baSBernhard Beschow /* dcblc */ 5042e64645baSBernhard Beschow static void gen_dcblc(DisasContext *ctx) 5043e64645baSBernhard Beschow { 5044e64645baSBernhard Beschow /* 5045e64645baSBernhard Beschow * interpreted as no-op 5046e64645baSBernhard Beschow */ 5047e64645baSBernhard Beschow } 5048e64645baSBernhard Beschow 5049fcf5ef2aSThomas Huth /* dcbz */ 5050fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5051fcf5ef2aSThomas Huth { 5052fcf5ef2aSThomas Huth TCGv tcgv_addr; 5053fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5054fcf5ef2aSThomas Huth 5055fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5056fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 50577058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5058fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5059fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5060fcf5ef2aSThomas Huth } 5061fcf5ef2aSThomas Huth 506250728199SRoman Kapl /* dcbzep */ 506350728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 506450728199SRoman Kapl { 506550728199SRoman Kapl TCGv tcgv_addr; 506650728199SRoman Kapl TCGv_i32 tcgv_op; 506750728199SRoman Kapl 506850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 506950728199SRoman Kapl tcgv_addr = tcg_temp_new(); 50707058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 507150728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 507250728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 507350728199SRoman Kapl } 507450728199SRoman Kapl 5075fcf5ef2aSThomas Huth /* dst / dstt */ 5076fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5077fcf5ef2aSThomas Huth { 5078fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5079fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5080fcf5ef2aSThomas Huth } else { 5081fcf5ef2aSThomas Huth /* interpreted as no-op */ 5082fcf5ef2aSThomas Huth } 5083fcf5ef2aSThomas Huth } 5084fcf5ef2aSThomas Huth 5085fcf5ef2aSThomas Huth /* dstst /dststt */ 5086fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5087fcf5ef2aSThomas Huth { 5088fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5089fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5090fcf5ef2aSThomas Huth } else { 5091fcf5ef2aSThomas Huth /* interpreted as no-op */ 5092fcf5ef2aSThomas Huth } 5093fcf5ef2aSThomas Huth 5094fcf5ef2aSThomas Huth } 5095fcf5ef2aSThomas Huth 5096fcf5ef2aSThomas Huth /* dss / dssall */ 5097fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5098fcf5ef2aSThomas Huth { 5099fcf5ef2aSThomas Huth /* interpreted as no-op */ 5100fcf5ef2aSThomas Huth } 5101fcf5ef2aSThomas Huth 5102fcf5ef2aSThomas Huth /* icbi */ 5103fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5104fcf5ef2aSThomas Huth { 5105fcf5ef2aSThomas Huth TCGv t0; 5106fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5107fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5108fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5109fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5110fcf5ef2aSThomas Huth } 5111fcf5ef2aSThomas Huth 511250728199SRoman Kapl /* icbiep */ 511350728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 511450728199SRoman Kapl { 511550728199SRoman Kapl TCGv t0; 511650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 511750728199SRoman Kapl t0 = tcg_temp_new(); 511850728199SRoman Kapl gen_addr_reg_index(ctx, t0); 511950728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 512050728199SRoman Kapl } 512150728199SRoman Kapl 5122fcf5ef2aSThomas Huth /* Optional: */ 5123fcf5ef2aSThomas Huth /* dcba */ 5124fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5125fcf5ef2aSThomas Huth { 5126efe843d8SDavid Gibson /* 5127efe843d8SDavid Gibson * interpreted as no-op 5128efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5129fcf5ef2aSThomas Huth * but does not generate any exception 5130fcf5ef2aSThomas Huth */ 5131fcf5ef2aSThomas Huth } 5132fcf5ef2aSThomas Huth 5133fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5134fcf5ef2aSThomas Huth /* Supervisor only: */ 5135fcf5ef2aSThomas Huth 5136fcf5ef2aSThomas Huth /* mfsr */ 5137fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5138fcf5ef2aSThomas Huth { 5139fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51409f0cf041SMatheus Ferst GEN_PRIV(ctx); 5141fcf5ef2aSThomas Huth #else 5142fcf5ef2aSThomas Huth TCGv t0; 5143fcf5ef2aSThomas Huth 51449f0cf041SMatheus Ferst CHK_SV(ctx); 51457058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5146fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5147fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5148fcf5ef2aSThomas Huth } 5149fcf5ef2aSThomas Huth 5150fcf5ef2aSThomas Huth /* mfsrin */ 5151fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5152fcf5ef2aSThomas Huth { 5153fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51549f0cf041SMatheus Ferst GEN_PRIV(ctx); 5155fcf5ef2aSThomas Huth #else 5156fcf5ef2aSThomas Huth TCGv t0; 5157fcf5ef2aSThomas Huth 51589f0cf041SMatheus Ferst CHK_SV(ctx); 5159fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5160e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5161fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5162fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5163fcf5ef2aSThomas Huth } 5164fcf5ef2aSThomas Huth 5165fcf5ef2aSThomas Huth /* mtsr */ 5166fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5167fcf5ef2aSThomas Huth { 5168fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51699f0cf041SMatheus Ferst GEN_PRIV(ctx); 5170fcf5ef2aSThomas Huth #else 5171fcf5ef2aSThomas Huth TCGv t0; 5172fcf5ef2aSThomas Huth 51739f0cf041SMatheus Ferst CHK_SV(ctx); 51747058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5175fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5176fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5177fcf5ef2aSThomas Huth } 5178fcf5ef2aSThomas Huth 5179fcf5ef2aSThomas Huth /* mtsrin */ 5180fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5181fcf5ef2aSThomas Huth { 5182fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51839f0cf041SMatheus Ferst GEN_PRIV(ctx); 5184fcf5ef2aSThomas Huth #else 5185fcf5ef2aSThomas Huth TCGv t0; 51869f0cf041SMatheus Ferst CHK_SV(ctx); 5187fcf5ef2aSThomas Huth 5188fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5189e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5190fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5191fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5192fcf5ef2aSThomas Huth } 5193fcf5ef2aSThomas Huth 5194fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5195fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5196fcf5ef2aSThomas Huth 5197fcf5ef2aSThomas Huth /* mfsr */ 5198fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5199fcf5ef2aSThomas Huth { 5200fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52019f0cf041SMatheus Ferst GEN_PRIV(ctx); 5202fcf5ef2aSThomas Huth #else 5203fcf5ef2aSThomas Huth TCGv t0; 5204fcf5ef2aSThomas Huth 52059f0cf041SMatheus Ferst CHK_SV(ctx); 52067058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5207fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5208fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5209fcf5ef2aSThomas Huth } 5210fcf5ef2aSThomas Huth 5211fcf5ef2aSThomas Huth /* mfsrin */ 5212fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5213fcf5ef2aSThomas Huth { 5214fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52159f0cf041SMatheus Ferst GEN_PRIV(ctx); 5216fcf5ef2aSThomas Huth #else 5217fcf5ef2aSThomas Huth TCGv t0; 5218fcf5ef2aSThomas Huth 52199f0cf041SMatheus Ferst CHK_SV(ctx); 5220fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5221e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5222fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5223fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5224fcf5ef2aSThomas Huth } 5225fcf5ef2aSThomas Huth 5226fcf5ef2aSThomas Huth /* mtsr */ 5227fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5228fcf5ef2aSThomas Huth { 5229fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52309f0cf041SMatheus Ferst GEN_PRIV(ctx); 5231fcf5ef2aSThomas Huth #else 5232fcf5ef2aSThomas Huth TCGv t0; 5233fcf5ef2aSThomas Huth 52349f0cf041SMatheus Ferst CHK_SV(ctx); 52357058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5236fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5237fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5238fcf5ef2aSThomas Huth } 5239fcf5ef2aSThomas Huth 5240fcf5ef2aSThomas Huth /* mtsrin */ 5241fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5242fcf5ef2aSThomas Huth { 5243fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52449f0cf041SMatheus Ferst GEN_PRIV(ctx); 5245fcf5ef2aSThomas Huth #else 5246fcf5ef2aSThomas Huth TCGv t0; 5247fcf5ef2aSThomas Huth 52489f0cf041SMatheus Ferst CHK_SV(ctx); 5249fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5250e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5251fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5252fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5253fcf5ef2aSThomas Huth } 5254fcf5ef2aSThomas Huth 5255fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5256fcf5ef2aSThomas Huth 5257fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5258fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5259fcf5ef2aSThomas Huth 5260fcf5ef2aSThomas Huth /* tlbia */ 5261fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5262fcf5ef2aSThomas Huth { 5263fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5265fcf5ef2aSThomas Huth #else 52669f0cf041SMatheus Ferst CHK_HV(ctx); 5267fcf5ef2aSThomas Huth 5268fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5269fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5270fcf5ef2aSThomas Huth } 5271fcf5ef2aSThomas Huth 5272fcf5ef2aSThomas Huth /* tlbsync */ 5273fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5274fcf5ef2aSThomas Huth { 5275fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52769f0cf041SMatheus Ferst GEN_PRIV(ctx); 5277fcf5ef2aSThomas Huth #else 527891c60f12SCédric Le Goater 527991c60f12SCédric Le Goater if (ctx->gtse) { 52809f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 528191c60f12SCédric Le Goater } else { 52829f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 528391c60f12SCédric Le Goater } 5284fcf5ef2aSThomas Huth 5285fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5286fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5287fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5288fcf5ef2aSThomas Huth } 5289fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5290fcf5ef2aSThomas Huth } 5291fcf5ef2aSThomas Huth 5292fcf5ef2aSThomas Huth /*** External control ***/ 5293fcf5ef2aSThomas Huth /* Optional: */ 5294fcf5ef2aSThomas Huth 5295fcf5ef2aSThomas Huth /* eciwx */ 5296fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5297fcf5ef2aSThomas Huth { 5298fcf5ef2aSThomas Huth TCGv t0; 5299fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5300fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5301fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5302fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5303c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5304c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5305fcf5ef2aSThomas Huth } 5306fcf5ef2aSThomas Huth 5307fcf5ef2aSThomas Huth /* ecowx */ 5308fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5309fcf5ef2aSThomas Huth { 5310fcf5ef2aSThomas Huth TCGv t0; 5311fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5312fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5313fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5314fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5315c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5316c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5317fcf5ef2aSThomas Huth } 5318fcf5ef2aSThomas Huth 5319fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5320fcf5ef2aSThomas Huth 5321fcf5ef2aSThomas Huth /* tlbld */ 5322fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5323fcf5ef2aSThomas Huth { 5324fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53259f0cf041SMatheus Ferst GEN_PRIV(ctx); 5326fcf5ef2aSThomas Huth #else 53279f0cf041SMatheus Ferst CHK_SV(ctx); 5328fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5329fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5330fcf5ef2aSThomas Huth } 5331fcf5ef2aSThomas Huth 5332fcf5ef2aSThomas Huth /* tlbli */ 5333fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5334fcf5ef2aSThomas Huth { 5335fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53369f0cf041SMatheus Ferst GEN_PRIV(ctx); 5337fcf5ef2aSThomas Huth #else 53389f0cf041SMatheus Ferst CHK_SV(ctx); 5339fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5340fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5341fcf5ef2aSThomas Huth } 5342fcf5ef2aSThomas Huth 5343fcf5ef2aSThomas Huth /* BookE specific instructions */ 5344fcf5ef2aSThomas Huth 5345fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5346fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5347fcf5ef2aSThomas Huth { 5348fcf5ef2aSThomas Huth /* XXX: TODO */ 5349fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5350fcf5ef2aSThomas Huth } 5351fcf5ef2aSThomas Huth 5352fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5353fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5354fcf5ef2aSThomas Huth { 5355fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53569f0cf041SMatheus Ferst GEN_PRIV(ctx); 5357fcf5ef2aSThomas Huth #else 5358fcf5ef2aSThomas Huth TCGv t0; 5359fcf5ef2aSThomas Huth 53609f0cf041SMatheus Ferst CHK_SV(ctx); 5361fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5362fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5363fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5365fcf5ef2aSThomas Huth } 5366fcf5ef2aSThomas Huth 5367fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5368fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5369fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5370fcf5ef2aSThomas Huth { 5371fcf5ef2aSThomas Huth TCGv t0, t1; 5372fcf5ef2aSThomas Huth 53739723281fSRichard Henderson t0 = tcg_temp_new(); 53749723281fSRichard Henderson t1 = tcg_temp_new(); 5375fcf5ef2aSThomas Huth 5376fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5377fcf5ef2aSThomas Huth case 0x05: 5378fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5379fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5380fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5381fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5382fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5383fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5384fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5385fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5386fcf5ef2aSThomas Huth break; 5387fcf5ef2aSThomas Huth case 0x04: 5388fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5389fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5390fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5391fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5392fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5393fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5394fcf5ef2aSThomas Huth break; 5395fcf5ef2aSThomas Huth case 0x01: 5396fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5397fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5398fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5399fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5400fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5401fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5402fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5403fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5404fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5405fcf5ef2aSThomas Huth break; 5406fcf5ef2aSThomas Huth case 0x00: 5407fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5408fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5409fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5410fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5411fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5412fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5413fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5414fcf5ef2aSThomas Huth break; 5415fcf5ef2aSThomas Huth case 0x0D: 5416fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5417fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5418fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5419fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5420fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5421fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5422fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5423fcf5ef2aSThomas Huth break; 5424fcf5ef2aSThomas Huth case 0x0C: 5425fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5426fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5427fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5428fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5429fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5430fcf5ef2aSThomas Huth break; 5431fcf5ef2aSThomas Huth } 5432fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5433fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5434fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5435fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5436fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5437fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5438fcf5ef2aSThomas Huth } else { 5439fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5440fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5441fcf5ef2aSThomas Huth } 5442fcf5ef2aSThomas Huth 5443fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5444fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5445fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5446fcf5ef2aSThomas Huth 5447fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5448fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5449fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5450fcf5ef2aSThomas Huth } 5451fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5452fcf5ef2aSThomas Huth /* Signed */ 5453fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5454fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5455fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5456fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5457fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5458fcf5ef2aSThomas Huth /* Saturate */ 5459fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5460fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5461fcf5ef2aSThomas Huth } 5462fcf5ef2aSThomas Huth } else { 5463fcf5ef2aSThomas Huth /* Unsigned */ 5464fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5465fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5466fcf5ef2aSThomas Huth /* Saturate */ 5467fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5468fcf5ef2aSThomas Huth } 5469fcf5ef2aSThomas Huth } 5470fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5471fcf5ef2aSThomas Huth /* Check overflow */ 5472fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5473fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5474fcf5ef2aSThomas Huth } 5475fcf5ef2aSThomas Huth gen_set_label(l1); 5476fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5477fcf5ef2aSThomas Huth } 5478fcf5ef2aSThomas Huth } else { 5479fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5480fcf5ef2aSThomas Huth } 5481fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5482fcf5ef2aSThomas Huth /* Update Rc0 */ 5483fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5484fcf5ef2aSThomas Huth } 5485fcf5ef2aSThomas Huth } 5486fcf5ef2aSThomas Huth 5487fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5488fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5489fcf5ef2aSThomas Huth { \ 5490fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5491fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5492fcf5ef2aSThomas Huth } 5493fcf5ef2aSThomas Huth 5494fcf5ef2aSThomas Huth /* macchw - macchw. */ 5495fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5496fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5497fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5498fcf5ef2aSThomas Huth /* macchws - macchws. */ 5499fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5500fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5501fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5502fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5503fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5504fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5505fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5506fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5507fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5508fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5509fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5510fcf5ef2aSThomas Huth /* machhw - machhw. */ 5511fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5512fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5513fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5514fcf5ef2aSThomas Huth /* machhws - machhws. */ 5515fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5516fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5517fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5518fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5519fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5520fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5521fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5522fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5523fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5524fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5525fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5526fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5527fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5528fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5529fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5530fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5531fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5532fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5533fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5534fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5535fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5536fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5537fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5538fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5539fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5540fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5541fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5542fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5543fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5544fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5545fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5546fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5547fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5548fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5550fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5552fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5554fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5556fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5558fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5560fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5562fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5564fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5566fcf5ef2aSThomas Huth 5567fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5569fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5571fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5573fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5575fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5577fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5579fcf5ef2aSThomas Huth 5580fcf5ef2aSThomas Huth /* mfdcr */ 5581fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5582fcf5ef2aSThomas Huth { 5583fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55849f0cf041SMatheus Ferst GEN_PRIV(ctx); 5585fcf5ef2aSThomas Huth #else 5586fcf5ef2aSThomas Huth TCGv dcrn; 5587fcf5ef2aSThomas Huth 55889f0cf041SMatheus Ferst CHK_SV(ctx); 55897058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5590fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5591fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5592fcf5ef2aSThomas Huth } 5593fcf5ef2aSThomas Huth 5594fcf5ef2aSThomas Huth /* mtdcr */ 5595fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5596fcf5ef2aSThomas Huth { 5597fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55989f0cf041SMatheus Ferst GEN_PRIV(ctx); 5599fcf5ef2aSThomas Huth #else 5600fcf5ef2aSThomas Huth TCGv dcrn; 5601fcf5ef2aSThomas Huth 56029f0cf041SMatheus Ferst CHK_SV(ctx); 56037058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5604fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5605fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5606fcf5ef2aSThomas Huth } 5607fcf5ef2aSThomas Huth 5608fcf5ef2aSThomas Huth /* mfdcrx */ 5609fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5610fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5611fcf5ef2aSThomas Huth { 5612fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56139f0cf041SMatheus Ferst GEN_PRIV(ctx); 5614fcf5ef2aSThomas Huth #else 56159f0cf041SMatheus Ferst CHK_SV(ctx); 5616fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5617fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5618fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5619fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5620fcf5ef2aSThomas Huth } 5621fcf5ef2aSThomas Huth 5622fcf5ef2aSThomas Huth /* mtdcrx */ 5623fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5624fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5625fcf5ef2aSThomas Huth { 5626fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56279f0cf041SMatheus Ferst GEN_PRIV(ctx); 5628fcf5ef2aSThomas Huth #else 56299f0cf041SMatheus Ferst CHK_SV(ctx); 5630fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5631fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5632fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5633fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5634fcf5ef2aSThomas Huth } 5635fcf5ef2aSThomas Huth 5636fcf5ef2aSThomas Huth /* dccci */ 5637fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5638fcf5ef2aSThomas Huth { 56399f0cf041SMatheus Ferst CHK_SV(ctx); 5640fcf5ef2aSThomas Huth /* interpreted as no-op */ 5641fcf5ef2aSThomas Huth } 5642fcf5ef2aSThomas Huth 5643fcf5ef2aSThomas Huth /* dcread */ 5644fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5645fcf5ef2aSThomas Huth { 5646fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56479f0cf041SMatheus Ferst GEN_PRIV(ctx); 5648fcf5ef2aSThomas Huth #else 5649fcf5ef2aSThomas Huth TCGv EA, val; 5650fcf5ef2aSThomas Huth 56519f0cf041SMatheus Ferst CHK_SV(ctx); 5652fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5653fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5654fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5655fcf5ef2aSThomas Huth val = tcg_temp_new(); 5656fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5657fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5658fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5659fcf5ef2aSThomas Huth } 5660fcf5ef2aSThomas Huth 5661fcf5ef2aSThomas Huth /* icbt */ 5662fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5663fcf5ef2aSThomas Huth { 5664efe843d8SDavid Gibson /* 5665efe843d8SDavid Gibson * interpreted as no-op 5666efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5667efe843d8SDavid Gibson * does not generate any exception 5668fcf5ef2aSThomas Huth */ 5669fcf5ef2aSThomas Huth } 5670fcf5ef2aSThomas Huth 5671fcf5ef2aSThomas Huth /* iccci */ 5672fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5673fcf5ef2aSThomas Huth { 56749f0cf041SMatheus Ferst CHK_SV(ctx); 5675fcf5ef2aSThomas Huth /* interpreted as no-op */ 5676fcf5ef2aSThomas Huth } 5677fcf5ef2aSThomas Huth 5678fcf5ef2aSThomas Huth /* icread */ 5679fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5680fcf5ef2aSThomas Huth { 56819f0cf041SMatheus Ferst CHK_SV(ctx); 5682fcf5ef2aSThomas Huth /* interpreted as no-op */ 5683fcf5ef2aSThomas Huth } 5684fcf5ef2aSThomas Huth 5685fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5686fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5687fcf5ef2aSThomas Huth { 5688fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56899f0cf041SMatheus Ferst GEN_PRIV(ctx); 5690fcf5ef2aSThomas Huth #else 56919f0cf041SMatheus Ferst CHK_SV(ctx); 5692fcf5ef2aSThomas Huth /* Restore CPU state */ 5693fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 569459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5695fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5696fcf5ef2aSThomas Huth } 5697fcf5ef2aSThomas Huth 5698fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5699fcf5ef2aSThomas Huth { 5700fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57019f0cf041SMatheus Ferst GEN_PRIV(ctx); 5702fcf5ef2aSThomas Huth #else 57039f0cf041SMatheus Ferst CHK_SV(ctx); 5704fcf5ef2aSThomas Huth /* Restore CPU state */ 5705fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 570659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5707fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5708fcf5ef2aSThomas Huth } 5709fcf5ef2aSThomas Huth 5710fcf5ef2aSThomas Huth /* BookE specific */ 5711fcf5ef2aSThomas Huth 5712fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5713fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5714fcf5ef2aSThomas Huth { 5715fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57169f0cf041SMatheus Ferst GEN_PRIV(ctx); 5717fcf5ef2aSThomas Huth #else 57189f0cf041SMatheus Ferst CHK_SV(ctx); 5719fcf5ef2aSThomas Huth /* Restore CPU state */ 5720fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 572159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5722fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5723fcf5ef2aSThomas Huth } 5724fcf5ef2aSThomas Huth 5725fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5726fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5727fcf5ef2aSThomas Huth { 5728fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57299f0cf041SMatheus Ferst GEN_PRIV(ctx); 5730fcf5ef2aSThomas Huth #else 57319f0cf041SMatheus Ferst CHK_SV(ctx); 5732fcf5ef2aSThomas Huth /* Restore CPU state */ 5733fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 573459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5735fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5736fcf5ef2aSThomas Huth } 5737fcf5ef2aSThomas Huth 5738fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5739fcf5ef2aSThomas Huth 5740fcf5ef2aSThomas Huth /* tlbre */ 5741fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5742fcf5ef2aSThomas Huth { 5743fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57449f0cf041SMatheus Ferst GEN_PRIV(ctx); 5745fcf5ef2aSThomas Huth #else 57469f0cf041SMatheus Ferst CHK_SV(ctx); 5747fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5748fcf5ef2aSThomas Huth case 0: 5749fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5750fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5751fcf5ef2aSThomas Huth break; 5752fcf5ef2aSThomas Huth case 1: 5753fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5754fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5755fcf5ef2aSThomas Huth break; 5756fcf5ef2aSThomas Huth default: 5757fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5758fcf5ef2aSThomas Huth break; 5759fcf5ef2aSThomas Huth } 5760fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5761fcf5ef2aSThomas Huth } 5762fcf5ef2aSThomas Huth 5763fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5764fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5765fcf5ef2aSThomas Huth { 5766fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57679f0cf041SMatheus Ferst GEN_PRIV(ctx); 5768fcf5ef2aSThomas Huth #else 5769fcf5ef2aSThomas Huth TCGv t0; 5770fcf5ef2aSThomas Huth 57719f0cf041SMatheus Ferst CHK_SV(ctx); 5772fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5773fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5774fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5775fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5776fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5777fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5778fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5779fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5780fcf5ef2aSThomas Huth gen_set_label(l1); 5781fcf5ef2aSThomas Huth } 5782fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5783fcf5ef2aSThomas Huth } 5784fcf5ef2aSThomas Huth 5785fcf5ef2aSThomas Huth /* tlbwe */ 5786fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5787fcf5ef2aSThomas Huth { 5788fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57899f0cf041SMatheus Ferst GEN_PRIV(ctx); 5790fcf5ef2aSThomas Huth #else 57919f0cf041SMatheus Ferst CHK_SV(ctx); 5792fcf5ef2aSThomas Huth 5793fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5794fcf5ef2aSThomas Huth case 0: 5795fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5796fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5797fcf5ef2aSThomas Huth break; 5798fcf5ef2aSThomas Huth case 1: 5799fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5800fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5801fcf5ef2aSThomas Huth break; 5802fcf5ef2aSThomas Huth default: 5803fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5804fcf5ef2aSThomas Huth break; 5805fcf5ef2aSThomas Huth } 5806fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5807fcf5ef2aSThomas Huth } 5808fcf5ef2aSThomas Huth 5809fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5810fcf5ef2aSThomas Huth 5811fcf5ef2aSThomas Huth /* tlbre */ 5812fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5813fcf5ef2aSThomas Huth { 5814fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58159f0cf041SMatheus Ferst GEN_PRIV(ctx); 5816fcf5ef2aSThomas Huth #else 58179f0cf041SMatheus Ferst CHK_SV(ctx); 5818fcf5ef2aSThomas Huth 5819fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5820fcf5ef2aSThomas Huth case 0: 5821fcf5ef2aSThomas Huth case 1: 5822fcf5ef2aSThomas Huth case 2: 5823fcf5ef2aSThomas Huth { 58247058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5825fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5826fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5827fcf5ef2aSThomas Huth } 5828fcf5ef2aSThomas Huth break; 5829fcf5ef2aSThomas Huth default: 5830fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5831fcf5ef2aSThomas Huth break; 5832fcf5ef2aSThomas Huth } 5833fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5834fcf5ef2aSThomas Huth } 5835fcf5ef2aSThomas Huth 5836fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5837fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5838fcf5ef2aSThomas Huth { 5839fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58409f0cf041SMatheus Ferst GEN_PRIV(ctx); 5841fcf5ef2aSThomas Huth #else 5842fcf5ef2aSThomas Huth TCGv t0; 5843fcf5ef2aSThomas Huth 58449f0cf041SMatheus Ferst CHK_SV(ctx); 5845fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5846fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5847fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5848fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5849fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5850fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5851fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5852fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5853fcf5ef2aSThomas Huth gen_set_label(l1); 5854fcf5ef2aSThomas Huth } 5855fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5856fcf5ef2aSThomas Huth } 5857fcf5ef2aSThomas Huth 5858fcf5ef2aSThomas Huth /* tlbwe */ 5859fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5860fcf5ef2aSThomas Huth { 5861fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58629f0cf041SMatheus Ferst GEN_PRIV(ctx); 5863fcf5ef2aSThomas Huth #else 58649f0cf041SMatheus Ferst CHK_SV(ctx); 5865fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5866fcf5ef2aSThomas Huth case 0: 5867fcf5ef2aSThomas Huth case 1: 5868fcf5ef2aSThomas Huth case 2: 5869fcf5ef2aSThomas Huth { 58707058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5871fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5872fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5873fcf5ef2aSThomas Huth } 5874fcf5ef2aSThomas Huth break; 5875fcf5ef2aSThomas Huth default: 5876fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5877fcf5ef2aSThomas Huth break; 5878fcf5ef2aSThomas Huth } 5879fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5880fcf5ef2aSThomas Huth } 5881fcf5ef2aSThomas Huth 5882fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5883fcf5ef2aSThomas Huth 5884fcf5ef2aSThomas Huth /* tlbre */ 5885fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5886fcf5ef2aSThomas Huth { 5887fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58889f0cf041SMatheus Ferst GEN_PRIV(ctx); 5889fcf5ef2aSThomas Huth #else 58909f0cf041SMatheus Ferst CHK_SV(ctx); 5891fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5892fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5893fcf5ef2aSThomas Huth } 5894fcf5ef2aSThomas Huth 5895fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5896fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5897fcf5ef2aSThomas Huth { 5898fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58999f0cf041SMatheus Ferst GEN_PRIV(ctx); 5900fcf5ef2aSThomas Huth #else 5901fcf5ef2aSThomas Huth TCGv t0; 5902fcf5ef2aSThomas Huth 59039f0cf041SMatheus Ferst CHK_SV(ctx); 5904fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5905fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 59069d15d8e1SRichard Henderson tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5907fcf5ef2aSThomas Huth } else { 59089d15d8e1SRichard Henderson t0 = cpu_gpr[rB(ctx->opcode)]; 5909fcf5ef2aSThomas Huth } 5910fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5911fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5912fcf5ef2aSThomas Huth } 5913fcf5ef2aSThomas Huth 5914fcf5ef2aSThomas Huth /* tlbwe */ 5915fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5916fcf5ef2aSThomas Huth { 5917fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59189f0cf041SMatheus Ferst GEN_PRIV(ctx); 5919fcf5ef2aSThomas Huth #else 59209f0cf041SMatheus Ferst CHK_SV(ctx); 5921fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5922fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5923fcf5ef2aSThomas Huth } 5924fcf5ef2aSThomas Huth 5925fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5926fcf5ef2aSThomas Huth { 5927fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59289f0cf041SMatheus Ferst GEN_PRIV(ctx); 5929fcf5ef2aSThomas Huth #else 5930fcf5ef2aSThomas Huth TCGv t0; 5931fcf5ef2aSThomas Huth 59329f0cf041SMatheus Ferst CHK_SV(ctx); 5933fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5934fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5935fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5936fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5937fcf5ef2aSThomas Huth } 5938fcf5ef2aSThomas Huth 5939fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5940fcf5ef2aSThomas Huth { 5941fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59429f0cf041SMatheus Ferst GEN_PRIV(ctx); 5943fcf5ef2aSThomas Huth #else 5944fcf5ef2aSThomas Huth TCGv t0; 5945fcf5ef2aSThomas Huth 59469f0cf041SMatheus Ferst CHK_SV(ctx); 5947fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5948fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5949fcf5ef2aSThomas Huth 5950fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 5951fcf5ef2aSThomas Huth case 0: 5952fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 5953fcf5ef2aSThomas Huth break; 5954fcf5ef2aSThomas Huth case 1: 5955fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 5956fcf5ef2aSThomas Huth break; 5957fcf5ef2aSThomas Huth case 3: 5958fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 5959fcf5ef2aSThomas Huth break; 5960fcf5ef2aSThomas Huth default: 5961fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5962fcf5ef2aSThomas Huth break; 5963fcf5ef2aSThomas Huth } 5964fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5965fcf5ef2aSThomas Huth } 5966fcf5ef2aSThomas Huth 5967fcf5ef2aSThomas Huth /* wrtee */ 5968fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 5969fcf5ef2aSThomas Huth { 5970fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59719f0cf041SMatheus Ferst GEN_PRIV(ctx); 5972fcf5ef2aSThomas Huth #else 5973fcf5ef2aSThomas Huth TCGv t0; 5974fcf5ef2aSThomas Huth 59759f0cf041SMatheus Ferst CHK_SV(ctx); 5976fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5977fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5978fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5979fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 59802fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5981efe843d8SDavid Gibson /* 5982efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 5983efe843d8SDavid Gibson * just set msr_ee to 1 5984fcf5ef2aSThomas Huth */ 5985d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5986fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5987fcf5ef2aSThomas Huth } 5988fcf5ef2aSThomas Huth 5989fcf5ef2aSThomas Huth /* wrteei */ 5990fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 5991fcf5ef2aSThomas Huth { 5992fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59939f0cf041SMatheus Ferst GEN_PRIV(ctx); 5994fcf5ef2aSThomas Huth #else 59959f0cf041SMatheus Ferst CHK_SV(ctx); 5996fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 5997fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 59982fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5999fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6000d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6001fcf5ef2aSThomas Huth } else { 6002fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6003fcf5ef2aSThomas Huth } 6004fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6005fcf5ef2aSThomas Huth } 6006fcf5ef2aSThomas Huth 6007fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6008fcf5ef2aSThomas Huth 6009fcf5ef2aSThomas Huth /* dlmzb */ 6010fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6011fcf5ef2aSThomas Huth { 60127058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6013fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6014fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6015fcf5ef2aSThomas Huth } 6016fcf5ef2aSThomas Huth 6017fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6018fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6019fcf5ef2aSThomas Huth { 6020fcf5ef2aSThomas Huth /* interpreted as no-op */ 6021fcf5ef2aSThomas Huth } 6022fcf5ef2aSThomas Huth 6023fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6024fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6025fcf5ef2aSThomas Huth { 602627a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 602727a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 602827a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 602927a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 603027a3ea7eSBALATON Zoltan } 603127a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6032fcf5ef2aSThomas Huth } 6033fcf5ef2aSThomas Huth 6034fcf5ef2aSThomas Huth /* icbt */ 6035fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6036fcf5ef2aSThomas Huth { 6037efe843d8SDavid Gibson /* 6038efe843d8SDavid Gibson * interpreted as no-op 6039efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6040efe843d8SDavid Gibson * does not generate any exception 6041fcf5ef2aSThomas Huth */ 6042fcf5ef2aSThomas Huth } 6043fcf5ef2aSThomas Huth 6044fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6045fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6046fcf5ef2aSThomas Huth { 6047fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6048fcf5ef2aSThomas Huth 6049fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6050fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6051fcf5ef2aSThomas Huth } 6052fcf5ef2aSThomas Huth 6053fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6054fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6055fcf5ef2aSThomas Huth { 6056fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6057fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6058fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6059fcf5ef2aSThomas Huth 6060fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6061fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6062fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6063fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6064fcf5ef2aSThomas Huth } else { 6065fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6066fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6067fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6068fcf5ef2aSThomas Huth } 6069fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6070fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6071fcf5ef2aSThomas Huth } 6072fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6073fcf5ef2aSThomas Huth 6074fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6075fcf5ef2aSThomas Huth { 6076fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6077fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6078fcf5ef2aSThomas Huth return; 6079fcf5ef2aSThomas Huth } 6080fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6081fcf5ef2aSThomas Huth } 6082fcf5ef2aSThomas Huth 6083fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6084fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6085fcf5ef2aSThomas Huth { \ 6086fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6087fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6088fcf5ef2aSThomas Huth return; \ 6089fcf5ef2aSThomas Huth } \ 6090efe843d8SDavid Gibson /* \ 6091efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6092fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6093fcf5ef2aSThomas Huth * \ 6094fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6095fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6096fcf5ef2aSThomas Huth */ \ 6097fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6098fcf5ef2aSThomas Huth } 6099fcf5ef2aSThomas Huth 6100fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6101fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6102fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6103fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6104fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6105fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6106fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6107efe843d8SDavid Gibson 6108b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6109b8b4576eSSuraj Jitindar Singh { 6110efe843d8SDavid Gibson /* Do Nothing */ 6111b8b4576eSSuraj Jitindar Singh } 6112fcf5ef2aSThomas Huth 611380b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 611480b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 611580b8c1eeSNikunj A Dadhania { \ 6116efe843d8SDavid Gibson /* \ 6117efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6118efe843d8SDavid Gibson * implementation of the copy paste facility \ 611980b8c1eeSNikunj A Dadhania */ \ 612080b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 612180b8c1eeSNikunj A Dadhania } 612280b8c1eeSNikunj A Dadhania 612380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 612480b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 612580b8c1eeSNikunj A Dadhania 6126fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6127fcf5ef2aSThomas Huth { 6128fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6129fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6130fcf5ef2aSThomas Huth return; 6131fcf5ef2aSThomas Huth } 6132efe843d8SDavid Gibson /* 6133efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6134efe843d8SDavid Gibson * simple: 6135fcf5ef2aSThomas Huth * 6136fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6137fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6138fcf5ef2aSThomas Huth */ 6139fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6140fcf5ef2aSThomas Huth } 6141fcf5ef2aSThomas Huth 6142fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6143fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6144fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6145fcf5ef2aSThomas Huth { \ 61469f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6147fcf5ef2aSThomas Huth } 6148fcf5ef2aSThomas Huth 6149fcf5ef2aSThomas Huth #else 6150fcf5ef2aSThomas Huth 6151fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6152fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6153fcf5ef2aSThomas Huth { \ 61549f0cf041SMatheus Ferst CHK_SV(ctx); \ 6155fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6156fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6157fcf5ef2aSThomas Huth return; \ 6158fcf5ef2aSThomas Huth } \ 6159efe843d8SDavid Gibson /* \ 6160efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6161fcf5ef2aSThomas Huth * simple: \ 6162fcf5ef2aSThomas Huth * \ 6163fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6164fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6165fcf5ef2aSThomas Huth */ \ 6166fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6167fcf5ef2aSThomas Huth } 6168fcf5ef2aSThomas Huth 6169fcf5ef2aSThomas Huth #endif 6170fcf5ef2aSThomas Huth 6171fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6172fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6173fcf5ef2aSThomas Huth 61741a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 61751a404c91SMark Cave-Ayland { 6176e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 61771a404c91SMark Cave-Ayland } 61781a404c91SMark Cave-Ayland 61791a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 61801a404c91SMark Cave-Ayland { 6181e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 61824b65b6e7SVíctor Colombo /* 61834b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 61844b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 61854b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 61864b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 61874b65b6e7SVíctor Colombo * to be 0. 61884b65b6e7SVíctor Colombo */ 61894b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 61901a404c91SMark Cave-Ayland } 61911a404c91SMark Cave-Ayland 6192c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6193c4a18dbfSMark Cave-Ayland { 619437da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6195c4a18dbfSMark Cave-Ayland } 6196c4a18dbfSMark Cave-Ayland 6197c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6198c4a18dbfSMark Cave-Ayland { 619937da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6200c4a18dbfSMark Cave-Ayland } 6201c4a18dbfSMark Cave-Ayland 6202c9826ae9SRichard Henderson /* 6203f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6204f2aabda8SRichard Henderson */ 6205d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6206d39b2cc7SLuis Pires { 6207d39b2cc7SLuis Pires return x * 2; 6208d39b2cc7SLuis Pires } 6209d39b2cc7SLuis Pires 6210f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6211f2aabda8SRichard Henderson { 6212f2aabda8SRichard Henderson return x * 4; 6213f2aabda8SRichard Henderson } 6214f2aabda8SRichard Henderson 6215e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6216e10271e1SMatheus Ferst { 6217e10271e1SMatheus Ferst return x * 16; 6218e10271e1SMatheus Ferst } 6219e10271e1SMatheus Ferst 6220670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6221670f1da3SVíctor Colombo { 6222670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6223670f1da3SVíctor Colombo } 6224670f1da3SVíctor Colombo 6225f2aabda8SRichard Henderson /* 6226c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6227c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6228c9826ae9SRichard Henderson * proper variable. 6229c9826ae9SRichard Henderson */ 6230c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6231c9826ae9SRichard Henderson do { \ 6232c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6233c9826ae9SRichard Henderson return false; \ 6234c9826ae9SRichard Henderson } \ 6235c9826ae9SRichard Henderson } while (0) 6236c9826ae9SRichard Henderson 6237c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6238c9826ae9SRichard Henderson do { \ 6239c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6240c9826ae9SRichard Henderson return false; \ 6241c9826ae9SRichard Henderson } \ 6242c9826ae9SRichard Henderson } while (0) 6243c9826ae9SRichard Henderson 6244c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6245c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6246c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6247c9826ae9SRichard Henderson #else 6248c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6249c9826ae9SRichard Henderson #endif 6250c9826ae9SRichard Henderson 6251e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6252e2205a46SBruno Larsen do { \ 6253e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6254e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6255e2205a46SBruno Larsen return true; \ 6256e2205a46SBruno Larsen } \ 6257e2205a46SBruno Larsen } while (0) 6258e2205a46SBruno Larsen 62598226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 62608226cb2dSBruno Larsen (billionai) do { \ 62618226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 62628226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 62638226cb2dSBruno Larsen (billionai) return true; \ 62648226cb2dSBruno Larsen (billionai) } \ 62658226cb2dSBruno Larsen (billionai) } while (0) 62668226cb2dSBruno Larsen (billionai) 626786057426SFernando Valle #define REQUIRE_FPU(ctx) \ 626886057426SFernando Valle do { \ 626986057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 627086057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 627186057426SFernando Valle return true; \ 627286057426SFernando Valle } \ 627386057426SFernando Valle } while (0) 627486057426SFernando Valle 6275fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6276fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6277fc34e81aSMatheus Ferst do { \ 6278fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6279fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6280fc34e81aSMatheus Ferst return true; \ 6281fc34e81aSMatheus Ferst } \ 6282fc34e81aSMatheus Ferst } while (0) 6283fc34e81aSMatheus Ferst 6284fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6285fc34e81aSMatheus Ferst do { \ 6286e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6287fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6288fc34e81aSMatheus Ferst return true; \ 6289fc34e81aSMatheus Ferst } \ 6290fc34e81aSMatheus Ferst } while (0) 6291fc34e81aSMatheus Ferst #else 6292fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6293fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6294fc34e81aSMatheus Ferst #endif 6295fc34e81aSMatheus Ferst 6296f2aabda8SRichard Henderson /* 6297f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6298f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6299f2aabda8SRichard Henderson */ 6300f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6301f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6302f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 630319f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 630419f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 630519f0862dSLuis Pires { \ 630619f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 630719f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 630819f0862dSLuis Pires } 630919f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 631019f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 631119f0862dSLuis Pires { \ 631219f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 631319f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 631419f0862dSLuis Pires } 6315f2aabda8SRichard Henderson 6316f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6317f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6318f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 631919f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 632019f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 632119f0862dSLuis Pires { \ 632219f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 632319f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 632419f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 632519f0862dSLuis Pires } 6326f2aabda8SRichard Henderson 6327f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6328f2aabda8SRichard Henderson 6329f2aabda8SRichard Henderson 633099082815SRichard Henderson #include "decode-insn32.c.inc" 633199082815SRichard Henderson #include "decode-insn64.c.inc" 6332565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6333565cb109SGustavo Romero 6334725b2d4dSFernando Eckhardt Valle /* 6335725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6336725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6337725b2d4dSFernando Eckhardt Valle */ 6338725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6339725b2d4dSFernando Eckhardt Valle { 6340725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6341725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6342725b2d4dSFernando Eckhardt Valle d->si = a->si; 6343725b2d4dSFernando Eckhardt Valle if (a->r) { 6344725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6345725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6346725b2d4dSFernando Eckhardt Valle return false; 6347725b2d4dSFernando Eckhardt Valle } 6348725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6349725b2d4dSFernando Eckhardt Valle } 6350725b2d4dSFernando Eckhardt Valle return true; 6351725b2d4dSFernando Eckhardt Valle } 6352725b2d4dSFernando Eckhardt Valle 635399082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 635499082815SRichard Henderson 6355139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6356fcf5ef2aSThomas Huth 6357139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6358fcf5ef2aSThomas Huth 6359139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6360fcf5ef2aSThomas Huth 6361139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6362fcf5ef2aSThomas Huth 6363139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6364fcf5ef2aSThomas Huth 63651f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 63661f26c751SDaniel Henrique Barboza 636798f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 636898f43417SMatheus Ferst 6369016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6370016b6e1dSLeandro Lupori 637120e2d04eSLeandro Lupori /* Handles lfdp */ 63725cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 63735cb091a4SNikunj A Dadhania { 637420e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 63755cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 63765cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 63775cb091a4SNikunj A Dadhania } 63785cb091a4SNikunj A Dadhania } 63795cb091a4SNikunj A Dadhania return gen_invalid(ctx); 63805cb091a4SNikunj A Dadhania } 63815cb091a4SNikunj A Dadhania 638220e2d04eSLeandro Lupori /* Handles stfdp */ 6383e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6384e3001664SNikunj A Dadhania { 638520e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 638620e2d04eSLeandro Lupori /* stfdp */ 6387e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6388e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6389e3001664SNikunj A Dadhania } 6390e3001664SNikunj A Dadhania } 6391e3001664SNikunj A Dadhania return gen_invalid(ctx); 6392e3001664SNikunj A Dadhania } 6393e3001664SNikunj A Dadhania 63949d69cfa2SLijun Pan #if defined(TARGET_PPC64) 63959d69cfa2SLijun Pan /* brd */ 63969d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 63979d69cfa2SLijun Pan { 63989d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 63999d69cfa2SLijun Pan } 64009d69cfa2SLijun Pan 64019d69cfa2SLijun Pan /* brw */ 64029d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 64039d69cfa2SLijun Pan { 64049d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64059d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 64069d69cfa2SLijun Pan 64079d69cfa2SLijun Pan } 64089d69cfa2SLijun Pan 64099d69cfa2SLijun Pan /* brh */ 64109d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 64119d69cfa2SLijun Pan { 6412491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 64139d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 64149d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 64159d69cfa2SLijun Pan 64169d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6417491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6418491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 64199d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 64209d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 64219d69cfa2SLijun Pan } 64229d69cfa2SLijun Pan #endif 64239d69cfa2SLijun Pan 6424fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 64259d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64269d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 64279d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 64289d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 64299d69cfa2SLijun Pan #endif 6430fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6431fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6432fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6433fcf5ef2aSThomas Huth #endif 6434fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6435fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6436fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6437fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6438fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6439fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6440fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6441fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6442fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6443fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6444fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6445fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6446fcf5ef2aSThomas Huth #endif 6447fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6448fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6449fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6450fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6451fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6452fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6453fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 645480b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6455b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 645680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6457fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6458fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6459fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6460fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6461fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6462fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6463fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6464fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6465fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6466fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6467fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6468fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6469fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6470fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6471fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6472fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6473fcf5ef2aSThomas Huth #endif 6474fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6475fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6476fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6477fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6478fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6479fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6480fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6481fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6482fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6483fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6484fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6485fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6486fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6487fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6488fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6489fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6490fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6491fcf5ef2aSThomas Huth #endif 64925cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 64935cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 649472b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6495e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6496fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6497fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6498fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6499fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6500fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6501fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6502c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6503fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6504fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6505fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6506fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6507a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6508a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6509fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6510fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6511fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6512fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6513a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6514a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6515fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6516fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6517fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6518fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6519fcf5ef2aSThomas Huth #endif 6520fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 65210c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 65220c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 65230c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6524fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6525fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6526fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6527fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6528fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6529fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6530fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6531fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6532fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 65333c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 65343c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65353c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65363c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65373c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 65383c89b8d6SNicholas Piggin #endif 6539cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6540fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6541fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6542fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6543fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6544fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6545fcf5ef2aSThomas Huth #endif 65463c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65473c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 65483c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6549fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6550fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6551fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6552fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6553fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6554fcf5ef2aSThomas Huth #endif 6555fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6556fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6557fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6558fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6559fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6560fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6561fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6562fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6563fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6564b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6565fcf5ef2aSThomas Huth #endif 6566fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6567fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6568fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 656950728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6570fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6571fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 657250728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6573fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 657450728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6575fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 657650728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6577fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6578e64645baSBernhard Beschow GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6579fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 658050728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6581fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 658299d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6583fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6584fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 658550728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6586fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6587fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6588fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6589fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6590fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6591fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6592fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6593fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6594fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6595fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6596fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6597fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6598fcf5ef2aSThomas Huth #endif 6599fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6600efe843d8SDavid Gibson /* 6601efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6602efe843d8SDavid Gibson * different ISA versions 6603efe843d8SDavid Gibson */ 6604fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6605fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6606fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6607fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6608fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6609fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6610fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6611fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6612fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6613fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6614fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6615fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6616fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6617fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6618fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6619fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6620fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6621fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6622fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6623fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6624fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6625fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6626fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6627fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6628fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6629fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6630fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6631fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6632fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6633fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6634fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6635fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6636fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6637fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6638fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6639fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6640fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6641fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6642fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6643fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6644fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 664527a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6646fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6647fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 66480c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 66490c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6650fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6651fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6652fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6653fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6654fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6655fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6656fcf5ef2aSThomas Huth PPC2_ISA300), 6657fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6658fcf5ef2aSThomas Huth #endif 6659fcf5ef2aSThomas Huth 6660fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6661fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6662fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6663fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6664fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6665fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6666fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6667fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6668fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6669fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6670fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6671fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6672fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6673fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6674fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 66754c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6676fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6677fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6678fcf5ef2aSThomas Huth 6679fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6680fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6681fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6682fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6683fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6684fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6685fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6686fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6687fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6688fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6689fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6690fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6691fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6692fcf5ef2aSThomas Huth 6693fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6694fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6695fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6696fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6697fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6698fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6699fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6700fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6701fcf5ef2aSThomas Huth 6702fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6703fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6704fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6705fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6706fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6707fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6708fcf5ef2aSThomas Huth 6709fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6710fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6711fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6712fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6713fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6714fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6715fcf5ef2aSThomas Huth #endif 6716fcf5ef2aSThomas Huth 6717fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6718fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6719fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6720fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6721fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6722fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6723fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6724fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6725fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6726fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6727fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6728fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6729fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6730fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6731fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6732fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6733fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6734fcf5ef2aSThomas Huth 6735fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6736fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6737fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6738fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6739fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6740fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6741fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6742fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6743fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6744fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6745fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6746fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6747fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6748fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6749fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6750fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6751fcf5ef2aSThomas Huth #endif 6752fcf5ef2aSThomas Huth 6753fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6754fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6755fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6756fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6757fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6758fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6759fcf5ef2aSThomas Huth PPC_64B) 6760fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6761fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6762fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6763fcf5ef2aSThomas Huth PPC_64B), \ 6764fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6765fcf5ef2aSThomas Huth PPC_64B), \ 6766fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6767fcf5ef2aSThomas Huth PPC_64B) 6768fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6769fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6770fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6771fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6772fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6773fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6774fcf5ef2aSThomas Huth #endif 6775fcf5ef2aSThomas Huth 6776fcf5ef2aSThomas Huth #undef GEN_LDX_E 6777fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6778fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6779fcf5ef2aSThomas Huth 6780fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6781fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6782fcf5ef2aSThomas Huth 6783fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6784fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6785fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6786fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6787fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6788fcf5ef2aSThomas Huth #endif 6789fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6790fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6791fcf5ef2aSThomas Huth 679250728199SRoman Kapl /* External PID based load */ 679350728199SRoman Kapl #undef GEN_LDEPX 679450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 679550728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 679650728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 679750728199SRoman Kapl 679850728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 679950728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 680050728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 680150728199SRoman Kapl #if defined(TARGET_PPC64) 6802fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 680350728199SRoman Kapl #endif 680450728199SRoman Kapl 6805fcf5ef2aSThomas Huth #undef GEN_STX_E 6806fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 68070123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6808fcf5ef2aSThomas Huth 6809fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6810fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6811fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6812fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6813fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6814fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6815fcf5ef2aSThomas Huth #endif 6816fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6817fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6818fcf5ef2aSThomas Huth 681950728199SRoman Kapl #undef GEN_STEPX 682050728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 682150728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 682250728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 682350728199SRoman Kapl 682450728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 682550728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 682650728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 682750728199SRoman Kapl #if defined(TARGET_PPC64) 6828fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 682950728199SRoman Kapl #endif 683050728199SRoman Kapl 6831fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6832fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6833fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6834fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6835fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6836fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6837fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6838fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6839fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6840fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6841fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6842fcf5ef2aSThomas Huth 6843fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6844fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6845fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6846fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6847fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6848fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6849fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6850fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6851fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6852fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6853fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6854fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6855fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6856fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6857fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6858fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6859fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6860fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6861fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6862fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6863fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6864fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6865fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6866fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6867fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6868fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6869fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6870fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6871fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6872fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6873fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6874fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6875fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6876fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6877fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6878fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6879fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6880fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6881fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6882fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6883fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6884fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6885fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6886fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6887fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6888fcf5ef2aSThomas Huth 6889fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6890fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6891fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6892fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6893fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6894fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6895fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6896fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6897fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6898fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6899fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6900fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6901fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6902fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6903fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6904fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6905fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6906fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6907fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6908fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6909fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6910fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6911fcf5ef2aSThomas Huth 6912139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 6913fcf5ef2aSThomas Huth 6914139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 6915fcf5ef2aSThomas Huth 6916139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 6917fcf5ef2aSThomas Huth 6918139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 6919fcf5ef2aSThomas Huth }; 6920fcf5ef2aSThomas Huth 69217468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 69227468e2c8SBruno Larsen (billionai) /* Opcode types */ 69237468e2c8SBruno Larsen (billionai) enum { 69247468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 69257468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 69267468e2c8SBruno Larsen (billionai) }; 69277468e2c8SBruno Larsen (billionai) 69287468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 69297468e2c8SBruno Larsen (billionai) 69307468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 69317468e2c8SBruno Larsen (billionai) { 69327468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 69337468e2c8SBruno Larsen (billionai) } 69347468e2c8SBruno Larsen (billionai) 69357468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 69367468e2c8SBruno Larsen (billionai) { 69377468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 69387468e2c8SBruno Larsen (billionai) } 69397468e2c8SBruno Larsen (billionai) 69407468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 69417468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 69427468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 69437468e2c8SBruno Larsen (billionai) { 69447468e2c8SBruno Larsen (billionai) int i; 69457468e2c8SBruno Larsen (billionai) 69467468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 69477468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 69487468e2c8SBruno Larsen (billionai) } 69497468e2c8SBruno Larsen (billionai) } 69507468e2c8SBruno Larsen (billionai) 69517468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 69527468e2c8SBruno Larsen (billionai) { 69537468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 69547468e2c8SBruno Larsen (billionai) 69557468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 69567468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 69577468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 69587468e2c8SBruno Larsen (billionai) 69597468e2c8SBruno Larsen (billionai) return 0; 69607468e2c8SBruno Larsen (billionai) } 69617468e2c8SBruno Larsen (billionai) 69627468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 69637468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69647468e2c8SBruno Larsen (billionai) { 69657468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 69667468e2c8SBruno Larsen (billionai) return -1; 69677468e2c8SBruno Larsen (billionai) } 69687468e2c8SBruno Larsen (billionai) table[idx] = handler; 69697468e2c8SBruno Larsen (billionai) 69707468e2c8SBruno Larsen (billionai) return 0; 69717468e2c8SBruno Larsen (billionai) } 69727468e2c8SBruno Larsen (billionai) 69737468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 69747468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 69757468e2c8SBruno Larsen (billionai) { 69767468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 69777468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 69787468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 69797468e2c8SBruno Larsen (billionai) return -1; 69807468e2c8SBruno Larsen (billionai) } 69817468e2c8SBruno Larsen (billionai) 69827468e2c8SBruno Larsen (billionai) return 0; 69837468e2c8SBruno Larsen (billionai) } 69847468e2c8SBruno Larsen (billionai) 69857468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 69867468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69877468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69887468e2c8SBruno Larsen (billionai) { 69897468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 69907468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 69917468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 69927468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 69937468e2c8SBruno Larsen (billionai) return -1; 69947468e2c8SBruno Larsen (billionai) } 69957468e2c8SBruno Larsen (billionai) } else { 69967468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 69977468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 69987468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 69997468e2c8SBruno Larsen (billionai) return -1; 70007468e2c8SBruno Larsen (billionai) } 70017468e2c8SBruno Larsen (billionai) } 70027468e2c8SBruno Larsen (billionai) if (handler != NULL && 70037468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 70047468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 70057468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 70067468e2c8SBruno Larsen (billionai) return -1; 70077468e2c8SBruno Larsen (billionai) } 70087468e2c8SBruno Larsen (billionai) 70097468e2c8SBruno Larsen (billionai) return 0; 70107468e2c8SBruno Larsen (billionai) } 70117468e2c8SBruno Larsen (billionai) 70127468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 70137468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70147468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70157468e2c8SBruno Larsen (billionai) { 70167468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 70177468e2c8SBruno Larsen (billionai) } 70187468e2c8SBruno Larsen (billionai) 70197468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 70207468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70217468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 70227468e2c8SBruno Larsen (billionai) { 70237468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70247468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70257468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70267468e2c8SBruno Larsen (billionai) return -1; 70277468e2c8SBruno Larsen (billionai) } 70287468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 70297468e2c8SBruno Larsen (billionai) handler) < 0) { 70307468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70317468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70327468e2c8SBruno Larsen (billionai) return -1; 70337468e2c8SBruno Larsen (billionai) } 70347468e2c8SBruno Larsen (billionai) 70357468e2c8SBruno Larsen (billionai) return 0; 70367468e2c8SBruno Larsen (billionai) } 70377468e2c8SBruno Larsen (billionai) 70387468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 70397468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70407468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 70417468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70427468e2c8SBruno Larsen (billionai) { 70437468e2c8SBruno Larsen (billionai) opc_handler_t **table; 70447468e2c8SBruno Larsen (billionai) 70457468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70467468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70477468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70487468e2c8SBruno Larsen (billionai) return -1; 70497468e2c8SBruno Larsen (billionai) } 70507468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 70517468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 70527468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 70537468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70547468e2c8SBruno Larsen (billionai) return -1; 70557468e2c8SBruno Larsen (billionai) } 70567468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 70577468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 70587468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70597468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 70607468e2c8SBruno Larsen (billionai) return -1; 70617468e2c8SBruno Larsen (billionai) } 70627468e2c8SBruno Larsen (billionai) return 0; 70637468e2c8SBruno Larsen (billionai) } 70647468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 70657468e2c8SBruno Larsen (billionai) { 70667468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 70677468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 70687468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 70697468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70707468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 70717468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 70727468e2c8SBruno Larsen (billionai) return -1; 70737468e2c8SBruno Larsen (billionai) } 70747468e2c8SBruno Larsen (billionai) } else { 70757468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70767468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 70777468e2c8SBruno Larsen (billionai) return -1; 70787468e2c8SBruno Larsen (billionai) } 70797468e2c8SBruno Larsen (billionai) } 70807468e2c8SBruno Larsen (billionai) } else { 70817468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 70827468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 70837468e2c8SBruno Larsen (billionai) return -1; 70847468e2c8SBruno Larsen (billionai) } 70857468e2c8SBruno Larsen (billionai) } 70867468e2c8SBruno Larsen (billionai) } else { 70877468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 70887468e2c8SBruno Larsen (billionai) return -1; 70897468e2c8SBruno Larsen (billionai) } 70907468e2c8SBruno Larsen (billionai) } 70917468e2c8SBruno Larsen (billionai) 70927468e2c8SBruno Larsen (billionai) return 0; 70937468e2c8SBruno Larsen (billionai) } 70947468e2c8SBruno Larsen (billionai) 70957468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 70967468e2c8SBruno Larsen (billionai) { 70977468e2c8SBruno Larsen (billionai) int i, count, tmp; 70987468e2c8SBruno Larsen (billionai) 70997468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 71007468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 71017468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 71027468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71037468e2c8SBruno Larsen (billionai) } 71047468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 71057468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 71067468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 71077468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 71087468e2c8SBruno Larsen (billionai) if (tmp == 0) { 71097468e2c8SBruno Larsen (billionai) free(table[i]); 71107468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71117468e2c8SBruno Larsen (billionai) } else { 71127468e2c8SBruno Larsen (billionai) count++; 71137468e2c8SBruno Larsen (billionai) } 71147468e2c8SBruno Larsen (billionai) } else { 71157468e2c8SBruno Larsen (billionai) count++; 71167468e2c8SBruno Larsen (billionai) } 71177468e2c8SBruno Larsen (billionai) } 71187468e2c8SBruno Larsen (billionai) } 71197468e2c8SBruno Larsen (billionai) 71207468e2c8SBruno Larsen (billionai) return count; 71217468e2c8SBruno Larsen (billionai) } 71227468e2c8SBruno Larsen (billionai) 71237468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 71247468e2c8SBruno Larsen (billionai) { 71257468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 71267468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 71277468e2c8SBruno Larsen (billionai) } 71287468e2c8SBruno Larsen (billionai) } 71297468e2c8SBruno Larsen (billionai) 71307468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71317468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 71327468e2c8SBruno Larsen (billionai) { 71337468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 71347468e2c8SBruno Larsen (billionai) opcode_t *opc; 71357468e2c8SBruno Larsen (billionai) 71367468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 71377468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 71387468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 71397468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 71407468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 71417468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 71427468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 71437468e2c8SBruno Larsen (billionai) opc->opc3); 71447468e2c8SBruno Larsen (billionai) return; 71457468e2c8SBruno Larsen (billionai) } 71467468e2c8SBruno Larsen (billionai) } 71477468e2c8SBruno Larsen (billionai) } 71487468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 71497468e2c8SBruno Larsen (billionai) fflush(stdout); 71507468e2c8SBruno Larsen (billionai) fflush(stderr); 71517468e2c8SBruno Larsen (billionai) } 71527468e2c8SBruno Larsen (billionai) 71537468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 71547468e2c8SBruno Larsen (billionai) { 71557468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 71567468e2c8SBruno Larsen (billionai) int i, j, k; 71577468e2c8SBruno Larsen (billionai) 71587468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 71597468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 71607468e2c8SBruno Larsen (billionai) continue; 71617468e2c8SBruno Larsen (billionai) } 71627468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 71637468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 71647468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 71657468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 71667468e2c8SBruno Larsen (billionai) continue; 71677468e2c8SBruno Larsen (billionai) } 71687468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 71697468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 71707468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 71717468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 71727468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 71737468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 71747468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71757468e2c8SBruno Larsen (billionai) } 71767468e2c8SBruno Larsen (billionai) } 71777468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 71787468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71797468e2c8SBruno Larsen (billionai) } 71807468e2c8SBruno Larsen (billionai) } 71817468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 71827468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71837468e2c8SBruno Larsen (billionai) } 71847468e2c8SBruno Larsen (billionai) } 71857468e2c8SBruno Larsen (billionai) } 71867468e2c8SBruno Larsen (billionai) 71877468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 71887468e2c8SBruno Larsen (billionai) { 71897468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 71907468e2c8SBruno Larsen (billionai) 71917468e2c8SBruno Larsen (billionai) /* 71927468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 71937468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 71947468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 71957468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 71967468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 71977468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 71987468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 71997468e2c8SBruno Larsen (billionai) */ 72007468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 72017468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 72027468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 72037468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 72047468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 72057468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 72067468e2c8SBruno Larsen (billionai) } 72077468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 72087468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 72097468e2c8SBruno Larsen (billionai) return 0; 72107468e2c8SBruno Larsen (billionai) } 72117468e2c8SBruno Larsen (billionai) 7212624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7213624cb07fSRichard Henderson { 7214624cb07fSRichard Henderson opc_handler_t **table, *handler; 7215624cb07fSRichard Henderson uint32_t inval; 7216624cb07fSRichard Henderson 7217624cb07fSRichard Henderson ctx->opcode = insn; 7218624cb07fSRichard Henderson 7219624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7220624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7221624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7222624cb07fSRichard Henderson 7223624cb07fSRichard Henderson table = cpu->opcodes; 7224624cb07fSRichard Henderson handler = table[opc1(insn)]; 7225624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7226624cb07fSRichard Henderson table = ind_table(handler); 7227624cb07fSRichard Henderson handler = table[opc2(insn)]; 7228624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7229624cb07fSRichard Henderson table = ind_table(handler); 7230624cb07fSRichard Henderson handler = table[opc3(insn)]; 7231624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7232624cb07fSRichard Henderson table = ind_table(handler); 7233624cb07fSRichard Henderson handler = table[opc4(insn)]; 7234624cb07fSRichard Henderson } 7235624cb07fSRichard Henderson } 7236624cb07fSRichard Henderson } 7237624cb07fSRichard Henderson 7238624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7239624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7240624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7241624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7242624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7243624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7244624cb07fSRichard Henderson insn, ctx->cia); 7245624cb07fSRichard Henderson return false; 7246624cb07fSRichard Henderson } 7247624cb07fSRichard Henderson 7248624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7249624cb07fSRichard Henderson && Rc(insn))) { 7250624cb07fSRichard Henderson inval = handler->inval2; 7251624cb07fSRichard Henderson } else { 7252624cb07fSRichard Henderson inval = handler->inval1; 7253624cb07fSRichard Henderson } 7254624cb07fSRichard Henderson 7255624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7256624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7257624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7258624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7259624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7260624cb07fSRichard Henderson insn, ctx->cia); 7261624cb07fSRichard Henderson return false; 7262624cb07fSRichard Henderson } 7263624cb07fSRichard Henderson 7264624cb07fSRichard Henderson handler->handler(ctx); 7265624cb07fSRichard Henderson return true; 7266624cb07fSRichard Henderson } 7267624cb07fSRichard Henderson 7268b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7269fcf5ef2aSThomas Huth { 7270b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 72719c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 72722df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7273fcf5ef2aSThomas Huth 7274b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 72752df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7276d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 72772df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 72782df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7279b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7280b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7281b0c2d521SEmilio G. Cota ctx->access_type = -1; 7282d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 72832df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7284b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 72850e3bf489SRoman Kapl ctx->flags = env->flags; 7286fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72872df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7288b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7289fcf5ef2aSThomas Huth #endif 7290e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7291d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7292fcf5ef2aSThomas Huth 72932df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 72942df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 72952df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 72962df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 72972df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7298f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 72991db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7300f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7301f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 73028b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 73038b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 730446d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 73052df4fe7aSRichard Henderson 7306b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 73072df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 73082df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 73099498d103SRichard Henderson ctx->base.max_insns = 1; 7310efe843d8SDavid Gibson } 73112df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7312b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7313efe843d8SDavid Gibson } 731413b45575SRichard Henderson } 7315fcf5ef2aSThomas Huth 7316b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7317b0c2d521SEmilio G. Cota { 7318b0c2d521SEmilio G. Cota } 7319fcf5ef2aSThomas Huth 7320b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7321b0c2d521SEmilio G. Cota { 7322b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7323b0c2d521SEmilio G. Cota } 7324b0c2d521SEmilio G. Cota 732599082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 732699082815SRichard Henderson { 732799082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 732899082815SRichard Henderson return opc1(insn) == 1; 732999082815SRichard Henderson } 733099082815SRichard Henderson 7331b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7332b0c2d521SEmilio G. Cota { 7333b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 733428876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7335b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 733699082815SRichard Henderson target_ulong pc; 7337624cb07fSRichard Henderson uint32_t insn; 7338624cb07fSRichard Henderson bool ok; 7339b0c2d521SEmilio G. Cota 7340fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7341fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7342b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7343b0c2d521SEmilio G. Cota 734499082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 73454e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 734699082815SRichard Henderson ctx->base.pc_next = pc += 4; 7347fcf5ef2aSThomas Huth 734899082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 734999082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 735099082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 735199082815SRichard Henderson } else if ((pc & 63) == 0) { 735299082815SRichard Henderson /* 735399082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 735499082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 735599082815SRichard Henderson * 64-byte address boundary (system alignment error). 735699082815SRichard Henderson */ 735799082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 735899082815SRichard Henderson ok = true; 735999082815SRichard Henderson } else { 73604e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 73614e116893SIlya Leoshkevich need_byteswap(ctx)); 736299082815SRichard Henderson ctx->base.pc_next = pc += 4; 736399082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 736499082815SRichard Henderson } 7365624cb07fSRichard Henderson if (!ok) { 7366624cb07fSRichard Henderson gen_invalid(ctx); 7367fcf5ef2aSThomas Huth } 7368624cb07fSRichard Henderson 736964a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 737099082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 737164a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 737264a0f644SRichard Henderson } 7373fcf5ef2aSThomas Huth } 7374b0c2d521SEmilio G. Cota 7375b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7376b0c2d521SEmilio G. Cota { 7377b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7378a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7379a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7380b0c2d521SEmilio G. Cota 7381a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7382a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 73833d8a5b69SRichard Henderson return; 73843d8a5b69SRichard Henderson } 73853d8a5b69SRichard Henderson 7386a9b5b3d0SRichard Henderson /* Honor single stepping. */ 73879498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 73889498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7389a9b5b3d0SRichard Henderson switch (is_jmp) { 7390a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7391a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7392a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7393a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7394a9b5b3d0SRichard Henderson break; 7395a9b5b3d0SRichard Henderson case DISAS_EXIT: 7396a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7397a9b5b3d0SRichard Henderson break; 7398a9b5b3d0SRichard Henderson default: 7399a9b5b3d0SRichard Henderson g_assert_not_reached(); 7400fcf5ef2aSThomas Huth } 740113b45575SRichard Henderson 7402a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7403a9b5b3d0SRichard Henderson return; 7404a9b5b3d0SRichard Henderson } 7405a9b5b3d0SRichard Henderson 7406a9b5b3d0SRichard Henderson switch (is_jmp) { 7407a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7408a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 740946d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7410a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7411a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7412a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7413a9b5b3d0SRichard Henderson break; 7414a9b5b3d0SRichard Henderson } 7415a9b5b3d0SRichard Henderson /* fall through */ 7416a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7417a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7418a9b5b3d0SRichard Henderson /* fall through */ 7419a9b5b3d0SRichard Henderson case DISAS_CHAIN: 742046d396bdSDaniel Henrique Barboza /* 742146d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 742246d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 742346d396bdSDaniel Henrique Barboza */ 742446d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 742546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 742646d396bdSDaniel Henrique Barboza } 742746d396bdSDaniel Henrique Barboza 7428a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7429a9b5b3d0SRichard Henderson break; 7430a9b5b3d0SRichard Henderson 7431a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7432a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7433a9b5b3d0SRichard Henderson /* fall through */ 7434a9b5b3d0SRichard Henderson case DISAS_EXIT: 743546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 743607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7437a9b5b3d0SRichard Henderson break; 7438a9b5b3d0SRichard Henderson 7439a9b5b3d0SRichard Henderson default: 7440a9b5b3d0SRichard Henderson g_assert_not_reached(); 7441fcf5ef2aSThomas Huth } 7442fcf5ef2aSThomas Huth } 7443b0c2d521SEmilio G. Cota 74448eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 74458eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7446b0c2d521SEmilio G. Cota { 74478eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 74488eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7449b0c2d521SEmilio G. Cota } 7450b0c2d521SEmilio G. Cota 7451b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7452b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7453b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7454b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7455b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7456b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7457b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7458b0c2d521SEmilio G. Cota }; 7459b0c2d521SEmilio G. Cota 7460597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7461306c8721SRichard Henderson target_ulong pc, void *host_pc) 7462b0c2d521SEmilio G. Cota { 7463b0c2d521SEmilio G. Cota DisasContext ctx; 7464b0c2d521SEmilio G. Cota 7465306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7466fcf5ef2aSThomas Huth } 7467