1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char *p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 125fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 131fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 133fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 135fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 137dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 139dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 143fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 144fcf5ef2aSThomas Huth "reserve_addr"); 145253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 146253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 147253ce7b2SNikunj A Dadhania "reserve_val"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 150fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 153efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 154efe843d8SDavid Gibson "access_type"); 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth /* internal defines */ 158fcf5ef2aSThomas Huth struct DisasContext { 159b6bac4bcSEmilio G. Cota DisasContextBase base; 1602c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 161fcf5ef2aSThomas Huth uint32_t opcode; 162fcf5ef2aSThomas Huth uint32_t exception; 163fcf5ef2aSThomas Huth /* Routine used to access memory */ 164fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 165fcf5ef2aSThomas Huth bool lazy_tlb_flush; 166fcf5ef2aSThomas Huth bool need_access_type; 167fcf5ef2aSThomas Huth int mem_idx; 168fcf5ef2aSThomas Huth int access_type; 169fcf5ef2aSThomas Huth /* Translation flags */ 17014776ab5STony Nguyen MemOp default_tcg_memop_mask; 171fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 172fcf5ef2aSThomas Huth bool sf_mode; 173fcf5ef2aSThomas Huth bool has_cfar; 174fcf5ef2aSThomas Huth #endif 175fcf5ef2aSThomas Huth bool fpu_enabled; 176fcf5ef2aSThomas Huth bool altivec_enabled; 177fcf5ef2aSThomas Huth bool vsx_enabled; 178fcf5ef2aSThomas Huth bool spe_enabled; 179fcf5ef2aSThomas Huth bool tm_enabled; 180c6fd28fdSSuraj Jitindar Singh bool gtse; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188*a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 189*a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 190*a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 191*a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 192*a9b5b3d0SRichard Henderson 193fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 194fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 197fcf5ef2aSThomas Huth return ctx->le_mode; 198fcf5ef2aSThomas Huth #else 199fcf5ef2aSThomas Huth return !ctx->le_mode; 200fcf5ef2aSThomas Huth #endif 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 204fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 206fcf5ef2aSThomas Huth #else 207fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 208fcf5ef2aSThomas Huth #endif 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth struct opc_handler_t { 211fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 212fcf5ef2aSThomas Huth uint32_t inval1; 213fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 214fcf5ef2aSThomas Huth uint32_t inval2; 215fcf5ef2aSThomas Huth /* instruction type */ 216fcf5ef2aSThomas Huth uint64_t type; 217fcf5ef2aSThomas Huth /* extended instruction type */ 218fcf5ef2aSThomas Huth uint64_t type2; 219fcf5ef2aSThomas Huth /* handler */ 220fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 221fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 222fcf5ef2aSThomas Huth const char *oname; 223fcf5ef2aSThomas Huth #endif 224fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 225fcf5ef2aSThomas Huth uint64_t count; 226fcf5ef2aSThomas Huth #endif 227fcf5ef2aSThomas Huth }; 228fcf5ef2aSThomas Huth 2290e3bf489SRoman Kapl /* SPR load/store helpers */ 2300e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2310e3bf489SRoman Kapl { 2320e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2330e3bf489SRoman Kapl } 2340e3bf489SRoman Kapl 2350e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2360e3bf489SRoman Kapl { 2370e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2380e3bf489SRoman Kapl } 2390e3bf489SRoman Kapl 240fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 241fcf5ef2aSThomas Huth { 242fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 243fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 244fcf5ef2aSThomas Huth ctx->access_type = access_type; 245fcf5ef2aSThomas Huth } 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth 248fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 249fcf5ef2aSThomas Huth { 250fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 251fcf5ef2aSThomas Huth nip = (uint32_t)nip; 252fcf5ef2aSThomas Huth } 253fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 254fcf5ef2aSThomas Huth } 255fcf5ef2aSThomas Huth 256fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 257fcf5ef2aSThomas Huth { 258fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 259fcf5ef2aSThomas Huth 260efe843d8SDavid Gibson /* 261efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 262efe843d8SDavid Gibson * faulting instruction 263fcf5ef2aSThomas Huth */ 264fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 2652c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 266fcf5ef2aSThomas Huth } 267fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 268fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 269fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 270fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 271fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2723d8a5b69SRichard Henderson ctx->exception = excp; 2733d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 274fcf5ef2aSThomas Huth } 275fcf5ef2aSThomas Huth 276fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 277fcf5ef2aSThomas Huth { 278fcf5ef2aSThomas Huth TCGv_i32 t0; 279fcf5ef2aSThomas Huth 280efe843d8SDavid Gibson /* 281efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 282efe843d8SDavid Gibson * faulting instruction 283fcf5ef2aSThomas Huth */ 284fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 2852c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 286fcf5ef2aSThomas Huth } 287fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 288fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 289fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2903d8a5b69SRichard Henderson ctx->exception = excp; 2913d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 292fcf5ef2aSThomas Huth } 293fcf5ef2aSThomas Huth 294fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 295fcf5ef2aSThomas Huth target_ulong nip) 296fcf5ef2aSThomas Huth { 297fcf5ef2aSThomas Huth TCGv_i32 t0; 298fcf5ef2aSThomas Huth 299fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 300fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 301fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 302fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3033d8a5b69SRichard Henderson ctx->exception = excp; 3043d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 305fcf5ef2aSThomas Huth } 306fcf5ef2aSThomas Huth 307e150ac89SRoman Kapl /* 308e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 309e150ac89SRoman Kapl * SPR registers for this exception. 310e150ac89SRoman Kapl * 311e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 312e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3130e3bf489SRoman Kapl */ 314e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3150e3bf489SRoman Kapl { 3160e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3170e3bf489SRoman Kapl target_ulong dbsr = 0; 318e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3190e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 320e150ac89SRoman Kapl } else { 321e150ac89SRoman Kapl /* Must have been branch */ 3220e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3230e3bf489SRoman Kapl } 3240e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3250e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3260e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3270e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3280e3bf489SRoman Kapl tcg_temp_free(t0); 3290e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3300e3bf489SRoman Kapl } else { 331e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3320e3bf489SRoman Kapl } 3330e3bf489SRoman Kapl } 3340e3bf489SRoman Kapl 335fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 336fcf5ef2aSThomas Huth { 3372736fc61SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 3383d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 339fcf5ef2aSThomas Huth } 340fcf5ef2aSThomas Huth 341fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 342fcf5ef2aSThomas Huth { 343fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 344fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 345fcf5ef2aSThomas Huth } 346fcf5ef2aSThomas Huth 347fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 348fcf5ef2aSThomas Huth { 349fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 350fcf5ef2aSThomas Huth } 351fcf5ef2aSThomas Huth 352fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 353fcf5ef2aSThomas Huth { 354fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 355fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 358fcf5ef2aSThomas Huth /* Stop translation */ 359fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 360fcf5ef2aSThomas Huth { 361b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 362fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 363fcf5ef2aSThomas Huth } 364fcf5ef2aSThomas Huth 365fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 366fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 367fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 368fcf5ef2aSThomas Huth { 369fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 370fcf5ef2aSThomas Huth } 371fcf5ef2aSThomas Huth #endif 372fcf5ef2aSThomas Huth 37337f219c8SBruno Larsen (billionai) /*****************************************************************************/ 37437f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 37537f219c8SBruno Larsen (billionai) 376a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 37737f219c8SBruno Larsen (billionai) { 37837f219c8SBruno Larsen (billionai) #if 0 37937f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 38037f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 38137f219c8SBruno Larsen (billionai) #endif 38237f219c8SBruno Larsen (billionai) } 38337f219c8SBruno Larsen (billionai) 38437f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 38537f219c8SBruno Larsen (billionai) 38637f219c8SBruno Larsen (billionai) /* 38737f219c8SBruno Larsen (billionai) * Generic callbacks: 38837f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 38937f219c8SBruno Larsen (billionai) */ 39037f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 39137f219c8SBruno Larsen (billionai) { 39237f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39437f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 39537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39637f219c8SBruno Larsen (billionai) #endif 39737f219c8SBruno Larsen (billionai) } 39837f219c8SBruno Larsen (billionai) 399a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 40037f219c8SBruno Larsen (billionai) { 40137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 40237f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 40337f219c8SBruno Larsen (billionai) } 40437f219c8SBruno Larsen (billionai) 40537f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 40637f219c8SBruno Larsen (billionai) { 40737f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 40837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 40937f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 41037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 41137f219c8SBruno Larsen (billionai) #endif 41237f219c8SBruno Larsen (billionai) } 41337f219c8SBruno Larsen (billionai) 414a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 41537f219c8SBruno Larsen (billionai) { 41637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 41737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41837f219c8SBruno Larsen (billionai) } 41937f219c8SBruno Larsen (billionai) 42037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 421a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 42237f219c8SBruno Larsen (billionai) { 42337f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 42437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 42637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42837f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42937f219c8SBruno Larsen (billionai) #else 43037f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43137f219c8SBruno Larsen (billionai) #endif 43237f219c8SBruno Larsen (billionai) } 43337f219c8SBruno Larsen (billionai) 434a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 43537f219c8SBruno Larsen (billionai) { 43637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 43837f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 43937f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 44037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 44137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 44337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 44437f219c8SBruno Larsen (billionai) } 44537f219c8SBruno Larsen (billionai) 446a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 44737f219c8SBruno Larsen (billionai) { 44837f219c8SBruno Larsen (billionai) } 44937f219c8SBruno Larsen (billionai) 45037f219c8SBruno Larsen (billionai) #endif 45137f219c8SBruno Larsen (billionai) 45237f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 45337f219c8SBruno Larsen (billionai) /* XER */ 454a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 45537f219c8SBruno Larsen (billionai) { 45637f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 45737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 45837f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 45937f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 46037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 46137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 46237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 46337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 46437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 46537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 46637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46737f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 46837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 46937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 47137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47237f219c8SBruno Larsen (billionai) } 47337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 47437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 47537f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 47637f219c8SBruno Larsen (billionai) } 47737f219c8SBruno Larsen (billionai) 478a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 47937f219c8SBruno Larsen (billionai) { 48037f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 48137f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 48237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 48337f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 48437f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 48537f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 48637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 48737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 48837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 48937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 49037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 49137f219c8SBruno Larsen (billionai) } 49237f219c8SBruno Larsen (billionai) 49337f219c8SBruno Larsen (billionai) /* LR */ 494a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 49537f219c8SBruno Larsen (billionai) { 49637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 49737f219c8SBruno Larsen (billionai) } 49837f219c8SBruno Larsen (billionai) 499a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 50037f219c8SBruno Larsen (billionai) { 50137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 50237f219c8SBruno Larsen (billionai) } 50337f219c8SBruno Larsen (billionai) 50437f219c8SBruno Larsen (billionai) /* CFAR */ 50537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 506a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 50737f219c8SBruno Larsen (billionai) { 50837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 50937f219c8SBruno Larsen (billionai) } 51037f219c8SBruno Larsen (billionai) 511a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 51237f219c8SBruno Larsen (billionai) { 51337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 51437f219c8SBruno Larsen (billionai) } 51537f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 51637f219c8SBruno Larsen (billionai) 51737f219c8SBruno Larsen (billionai) /* CTR */ 518a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 51937f219c8SBruno Larsen (billionai) { 52037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 52137f219c8SBruno Larsen (billionai) } 52237f219c8SBruno Larsen (billionai) 523a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 52437f219c8SBruno Larsen (billionai) { 52537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 52637f219c8SBruno Larsen (billionai) } 52737f219c8SBruno Larsen (billionai) 52837f219c8SBruno Larsen (billionai) /* User read access to SPR */ 52937f219c8SBruno Larsen (billionai) /* USPRx */ 53037f219c8SBruno Larsen (billionai) /* UMMCRx */ 53137f219c8SBruno Larsen (billionai) /* UPMCx */ 53237f219c8SBruno Larsen (billionai) /* USIA */ 53337f219c8SBruno Larsen (billionai) /* UDECR */ 534a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 53537f219c8SBruno Larsen (billionai) { 53637f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 53737f219c8SBruno Larsen (billionai) } 53837f219c8SBruno Larsen (billionai) 53937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 540a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 54137f219c8SBruno Larsen (billionai) { 54237f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 54337f219c8SBruno Larsen (billionai) } 54437f219c8SBruno Larsen (billionai) #endif 54537f219c8SBruno Larsen (billionai) 54637f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 54737f219c8SBruno Larsen (billionai) /* DECR */ 54837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 549a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 55037f219c8SBruno Larsen (billionai) { 55137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 55237f219c8SBruno Larsen (billionai) gen_io_start(); 55337f219c8SBruno Larsen (billionai) } 55437f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 55537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 55637f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 55737f219c8SBruno Larsen (billionai) } 55837f219c8SBruno Larsen (billionai) } 55937f219c8SBruno Larsen (billionai) 560a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 56137f219c8SBruno Larsen (billionai) { 56237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 56337f219c8SBruno Larsen (billionai) gen_io_start(); 56437f219c8SBruno Larsen (billionai) } 56537f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 56637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 56737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 56837f219c8SBruno Larsen (billionai) } 56937f219c8SBruno Larsen (billionai) } 57037f219c8SBruno Larsen (billionai) #endif 57137f219c8SBruno Larsen (billionai) 57237f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 57337f219c8SBruno Larsen (billionai) /* Time base */ 574a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 57537f219c8SBruno Larsen (billionai) { 57637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 57737f219c8SBruno Larsen (billionai) gen_io_start(); 57837f219c8SBruno Larsen (billionai) } 57937f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 58037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 58137f219c8SBruno Larsen (billionai) gen_io_end(); 58237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 58337f219c8SBruno Larsen (billionai) } 58437f219c8SBruno Larsen (billionai) } 58537f219c8SBruno Larsen (billionai) 586a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 58737f219c8SBruno Larsen (billionai) { 58837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 58937f219c8SBruno Larsen (billionai) gen_io_start(); 59037f219c8SBruno Larsen (billionai) } 59137f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 59237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 59337f219c8SBruno Larsen (billionai) gen_io_end(); 59437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 59537f219c8SBruno Larsen (billionai) } 59637f219c8SBruno Larsen (billionai) } 59737f219c8SBruno Larsen (billionai) 598a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 59937f219c8SBruno Larsen (billionai) { 60037f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 60137f219c8SBruno Larsen (billionai) } 60237f219c8SBruno Larsen (billionai) 603a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 60437f219c8SBruno Larsen (billionai) { 60537f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 60637f219c8SBruno Larsen (billionai) } 60737f219c8SBruno Larsen (billionai) 60837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 609a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 61037f219c8SBruno Larsen (billionai) { 61137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 61237f219c8SBruno Larsen (billionai) gen_io_start(); 61337f219c8SBruno Larsen (billionai) } 61437f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 61537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 61637f219c8SBruno Larsen (billionai) gen_io_end(); 61737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 61837f219c8SBruno Larsen (billionai) } 61937f219c8SBruno Larsen (billionai) } 62037f219c8SBruno Larsen (billionai) 621a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 62237f219c8SBruno Larsen (billionai) { 62337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 62437f219c8SBruno Larsen (billionai) gen_io_start(); 62537f219c8SBruno Larsen (billionai) } 62637f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 62737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 62837f219c8SBruno Larsen (billionai) gen_io_end(); 62937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 63037f219c8SBruno Larsen (billionai) } 63137f219c8SBruno Larsen (billionai) } 63237f219c8SBruno Larsen (billionai) 633a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 63437f219c8SBruno Larsen (billionai) { 63537f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 63637f219c8SBruno Larsen (billionai) } 63737f219c8SBruno Larsen (billionai) 638a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 63937f219c8SBruno Larsen (billionai) { 64037f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 64137f219c8SBruno Larsen (billionai) } 64237f219c8SBruno Larsen (billionai) 64337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 644a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 64537f219c8SBruno Larsen (billionai) { 64637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 64737f219c8SBruno Larsen (billionai) gen_io_start(); 64837f219c8SBruno Larsen (billionai) } 64937f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 65037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 65137f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 65237f219c8SBruno Larsen (billionai) } 65337f219c8SBruno Larsen (billionai) } 65437f219c8SBruno Larsen (billionai) 655a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 65637f219c8SBruno Larsen (billionai) { 65737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 65837f219c8SBruno Larsen (billionai) gen_io_start(); 65937f219c8SBruno Larsen (billionai) } 66037f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 66137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 66237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 66337f219c8SBruno Larsen (billionai) } 66437f219c8SBruno Larsen (billionai) } 66537f219c8SBruno Larsen (billionai) 66637f219c8SBruno Larsen (billionai) /* HDECR */ 667a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 66837f219c8SBruno Larsen (billionai) { 66937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 67037f219c8SBruno Larsen (billionai) gen_io_start(); 67137f219c8SBruno Larsen (billionai) } 67237f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 67337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 67437f219c8SBruno Larsen (billionai) gen_io_end(); 67537f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 67637f219c8SBruno Larsen (billionai) } 67737f219c8SBruno Larsen (billionai) } 67837f219c8SBruno Larsen (billionai) 679a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 68037f219c8SBruno Larsen (billionai) { 68137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 68237f219c8SBruno Larsen (billionai) gen_io_start(); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 68537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 68637f219c8SBruno Larsen (billionai) gen_io_end(); 68737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 68837f219c8SBruno Larsen (billionai) } 68937f219c8SBruno Larsen (billionai) } 69037f219c8SBruno Larsen (billionai) 691a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 69237f219c8SBruno Larsen (billionai) { 69337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 69437f219c8SBruno Larsen (billionai) gen_io_start(); 69537f219c8SBruno Larsen (billionai) } 69637f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 69737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 69837f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 69937f219c8SBruno Larsen (billionai) } 70037f219c8SBruno Larsen (billionai) } 70137f219c8SBruno Larsen (billionai) 702a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 70337f219c8SBruno Larsen (billionai) { 70437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 70537f219c8SBruno Larsen (billionai) gen_io_start(); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 70837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 70937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 71037f219c8SBruno Larsen (billionai) } 71137f219c8SBruno Larsen (billionai) } 71237f219c8SBruno Larsen (billionai) 713a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 71437f219c8SBruno Larsen (billionai) { 71537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 71637f219c8SBruno Larsen (billionai) gen_io_start(); 71737f219c8SBruno Larsen (billionai) } 71837f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 71937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 72037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 72137f219c8SBruno Larsen (billionai) } 72237f219c8SBruno Larsen (billionai) } 72337f219c8SBruno Larsen (billionai) 72437f219c8SBruno Larsen (billionai) #endif 72537f219c8SBruno Larsen (billionai) #endif 72637f219c8SBruno Larsen (billionai) 72737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 72837f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 72937f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 730a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 73137f219c8SBruno Larsen (billionai) { 73237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 73337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 73437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 73537f219c8SBruno Larsen (billionai) } 73637f219c8SBruno Larsen (billionai) 737a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 73837f219c8SBruno Larsen (billionai) { 73937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 74237f219c8SBruno Larsen (billionai) } 74337f219c8SBruno Larsen (billionai) 744a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 74737f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 74837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74937f219c8SBruno Larsen (billionai) } 75037f219c8SBruno Larsen (billionai) 751a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 75237f219c8SBruno Larsen (billionai) { 75337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 75437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 75537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75637f219c8SBruno Larsen (billionai) } 75737f219c8SBruno Larsen (billionai) 758a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 75937f219c8SBruno Larsen (billionai) { 76037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 76137f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 76237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 76337f219c8SBruno Larsen (billionai) } 76437f219c8SBruno Larsen (billionai) 765a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 76637f219c8SBruno Larsen (billionai) { 76737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 76837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 76937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 77237f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 77337f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 774a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 77537f219c8SBruno Larsen (billionai) { 77637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 77737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 77837f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 77937f219c8SBruno Larsen (billionai) } 78037f219c8SBruno Larsen (billionai) 781a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 78237f219c8SBruno Larsen (billionai) { 78337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 78437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 78537f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 78637f219c8SBruno Larsen (billionai) } 78737f219c8SBruno Larsen (billionai) 788a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 78937f219c8SBruno Larsen (billionai) { 79037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 79137f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 79237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) 795a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 79637f219c8SBruno Larsen (billionai) { 79737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 79837f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 79937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 80037f219c8SBruno Larsen (billionai) } 80137f219c8SBruno Larsen (billionai) 802a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 80337f219c8SBruno Larsen (billionai) { 80437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 80537f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 80637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 80737f219c8SBruno Larsen (billionai) } 80837f219c8SBruno Larsen (billionai) 809a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 81037f219c8SBruno Larsen (billionai) { 81137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 81237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 81337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 81437f219c8SBruno Larsen (billionai) } 81537f219c8SBruno Larsen (billionai) 81637f219c8SBruno Larsen (billionai) /* SDR1 */ 817a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 81837f219c8SBruno Larsen (billionai) { 81937f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 82037f219c8SBruno Larsen (billionai) } 82137f219c8SBruno Larsen (billionai) 82237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 82337f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 82437f219c8SBruno Larsen (billionai) /* PIDR */ 825a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 82637f219c8SBruno Larsen (billionai) { 82737f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 82837f219c8SBruno Larsen (billionai) } 82937f219c8SBruno Larsen (billionai) 830a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 83137f219c8SBruno Larsen (billionai) { 83237f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 83337f219c8SBruno Larsen (billionai) } 83437f219c8SBruno Larsen (billionai) 835a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 83637f219c8SBruno Larsen (billionai) { 83737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 83837f219c8SBruno Larsen (billionai) } 83937f219c8SBruno Larsen (billionai) 840a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 84137f219c8SBruno Larsen (billionai) { 84237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 84337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 84437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 84537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 84637f219c8SBruno Larsen (billionai) } 847a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 84837f219c8SBruno Larsen (billionai) { 84937f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 85037f219c8SBruno Larsen (billionai) } 85137f219c8SBruno Larsen (billionai) 852a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 85337f219c8SBruno Larsen (billionai) { 85437f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 85537f219c8SBruno Larsen (billionai) } 85637f219c8SBruno Larsen (billionai) 85737f219c8SBruno Larsen (billionai) /* DPDES */ 858a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 85937f219c8SBruno Larsen (billionai) { 86037f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 86137f219c8SBruno Larsen (billionai) } 86237f219c8SBruno Larsen (billionai) 863a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 86437f219c8SBruno Larsen (billionai) { 86537f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 86637f219c8SBruno Larsen (billionai) } 86737f219c8SBruno Larsen (billionai) #endif 86837f219c8SBruno Larsen (billionai) #endif 86937f219c8SBruno Larsen (billionai) 87037f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 87137f219c8SBruno Larsen (billionai) /* RTC */ 872a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 87337f219c8SBruno Larsen (billionai) { 87437f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 87537f219c8SBruno Larsen (billionai) } 87637f219c8SBruno Larsen (billionai) 877a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 87837f219c8SBruno Larsen (billionai) { 87937f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 88037f219c8SBruno Larsen (billionai) } 88137f219c8SBruno Larsen (billionai) 88237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 883a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 88437f219c8SBruno Larsen (billionai) { 88537f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 88637f219c8SBruno Larsen (billionai) } 88737f219c8SBruno Larsen (billionai) 888a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 88937f219c8SBruno Larsen (billionai) { 89037f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 89137f219c8SBruno Larsen (billionai) } 89237f219c8SBruno Larsen (billionai) 893a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 89437f219c8SBruno Larsen (billionai) { 89537f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 89637f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 89737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 89837f219c8SBruno Larsen (billionai) } 89937f219c8SBruno Larsen (billionai) #endif 90037f219c8SBruno Larsen (billionai) 90137f219c8SBruno Larsen (billionai) /* Unified bats */ 90237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 903a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 90437f219c8SBruno Larsen (billionai) { 90537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 90637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 90737f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 90837f219c8SBruno Larsen (billionai) } 90937f219c8SBruno Larsen (billionai) 910a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 91137f219c8SBruno Larsen (billionai) { 91237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 91337f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 91437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91537f219c8SBruno Larsen (billionai) } 91637f219c8SBruno Larsen (billionai) 917a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 91837f219c8SBruno Larsen (billionai) { 91937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 92037f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 92137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92237f219c8SBruno Larsen (billionai) } 92337f219c8SBruno Larsen (billionai) #endif 92437f219c8SBruno Larsen (billionai) 92537f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 92637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 927a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 92837f219c8SBruno Larsen (billionai) { 92937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 93037f219c8SBruno Larsen (billionai) gen_io_start(); 93137f219c8SBruno Larsen (billionai) } 93237f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 93337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 93437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 93537f219c8SBruno Larsen (billionai) } 93637f219c8SBruno Larsen (billionai) } 93737f219c8SBruno Larsen (billionai) 938a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 93937f219c8SBruno Larsen (billionai) { 94037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 94137f219c8SBruno Larsen (billionai) gen_io_start(); 94237f219c8SBruno Larsen (billionai) } 94337f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 94437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 94537f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 94637f219c8SBruno Larsen (billionai) } 94737f219c8SBruno Larsen (billionai) } 94837f219c8SBruno Larsen (billionai) 949a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 95037f219c8SBruno Larsen (billionai) { 95137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 95237f219c8SBruno Larsen (billionai) gen_io_start(); 95337f219c8SBruno Larsen (billionai) } 95437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 95537f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 95637f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 95737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 95837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 95937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 96037f219c8SBruno Larsen (billionai) } 96137f219c8SBruno Larsen (billionai) } 96237f219c8SBruno Larsen (billionai) 963a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 96437f219c8SBruno Larsen (billionai) { 96537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 96637f219c8SBruno Larsen (billionai) gen_io_start(); 96737f219c8SBruno Larsen (billionai) } 96837f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 96937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 97037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 97137f219c8SBruno Larsen (billionai) } 97237f219c8SBruno Larsen (billionai) } 97337f219c8SBruno Larsen (billionai) 974a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 97537f219c8SBruno Larsen (billionai) { 97637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 97737f219c8SBruno Larsen (billionai) gen_io_start(); 97837f219c8SBruno Larsen (billionai) } 97937f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 98037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 98137f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 98237f219c8SBruno Larsen (billionai) } 98337f219c8SBruno Larsen (billionai) } 98437f219c8SBruno Larsen (billionai) 985a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 98637f219c8SBruno Larsen (billionai) { 98737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 98837f219c8SBruno Larsen (billionai) gen_io_start(); 98937f219c8SBruno Larsen (billionai) } 99037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 99137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 99237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 99337f219c8SBruno Larsen (billionai) } 99437f219c8SBruno Larsen (billionai) } 99537f219c8SBruno Larsen (billionai) #endif 99637f219c8SBruno Larsen (billionai) 99737f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 99837f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 99937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1000a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 100137f219c8SBruno Larsen (billionai) { 100237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 100337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 100437f219c8SBruno Larsen (billionai) } 100537f219c8SBruno Larsen (billionai) 1006a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 100737f219c8SBruno Larsen (billionai) { 100837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 100937f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 101037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 101137f219c8SBruno Larsen (billionai) } 101237f219c8SBruno Larsen (billionai) 1013a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 101437f219c8SBruno Larsen (billionai) { 101537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 101637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 101737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 101837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 101937f219c8SBruno Larsen (billionai) } 102037f219c8SBruno Larsen (billionai) #endif 102137f219c8SBruno Larsen (billionai) 102237f219c8SBruno Larsen (billionai) /* SPE specific registers */ 1023a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 102437f219c8SBruno Larsen (billionai) { 102537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 102637f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 102737f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 102837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 102937f219c8SBruno Larsen (billionai) } 103037f219c8SBruno Larsen (billionai) 1031a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 103237f219c8SBruno Larsen (billionai) { 103337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 103437f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 103537f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 103637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 103737f219c8SBruno Larsen (billionai) } 103837f219c8SBruno Larsen (billionai) 103937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 104037f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 1041a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 104237f219c8SBruno Larsen (billionai) { 104337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 104437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 104537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 104637f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 104737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 104837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 104937f219c8SBruno Larsen (billionai) } 105037f219c8SBruno Larsen (billionai) 1051a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 105237f219c8SBruno Larsen (billionai) { 105337f219c8SBruno Larsen (billionai) int sprn_offs; 105437f219c8SBruno Larsen (billionai) 105537f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 105637f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 105737f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 105837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 105937f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 106037f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 106137f219c8SBruno Larsen (billionai) } else { 106237f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 106337f219c8SBruno Larsen (billionai) sprn, sprn); 106437f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 106537f219c8SBruno Larsen (billionai) return; 106637f219c8SBruno Larsen (billionai) } 106737f219c8SBruno Larsen (billionai) 106837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 107037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 107137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 107237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107437f219c8SBruno Larsen (billionai) } 107537f219c8SBruno Larsen (billionai) #endif 107637f219c8SBruno Larsen (billionai) 107737f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 107837f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1079a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 108037f219c8SBruno Larsen (billionai) { 108137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 108337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 108437f219c8SBruno Larsen (billionai) 108537f219c8SBruno Larsen (billionai) /* 108637f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 108737f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 108837f219c8SBruno Larsen (billionai) */ 108937f219c8SBruno Larsen (billionai) 109037f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 109137f219c8SBruno Larsen (billionai) if (ctx->pr) { 109237f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 109337f219c8SBruno Larsen (billionai) } else { 109437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 109537f219c8SBruno Larsen (billionai) } 109637f219c8SBruno Larsen (billionai) 109737f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 109837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 109937f219c8SBruno Larsen (billionai) 110037f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 110137f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 110237f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 110337f219c8SBruno Larsen (billionai) 110437f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 110537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 110637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 110737f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 110837f219c8SBruno Larsen (billionai) 110937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 111037f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 111137f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 111237f219c8SBruno Larsen (billionai) } 111337f219c8SBruno Larsen (billionai) 1114a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 111537f219c8SBruno Larsen (billionai) { 111637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 111737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 111837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 111937f219c8SBruno Larsen (billionai) 112037f219c8SBruno Larsen (billionai) /* 112137f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 112237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 112337f219c8SBruno Larsen (billionai) */ 112437f219c8SBruno Larsen (billionai) 112537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 112637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 112737f219c8SBruno Larsen (billionai) 112837f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 112937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 113037f219c8SBruno Larsen (billionai) 113137f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 113237f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 113337f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 113437f219c8SBruno Larsen (billionai) 113537f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 113637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 113737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 113837f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 113937f219c8SBruno Larsen (billionai) 114037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 114137f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 114237f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 114337f219c8SBruno Larsen (billionai) } 114437f219c8SBruno Larsen (billionai) 1145a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 114637f219c8SBruno Larsen (billionai) { 114737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 114837f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 114937f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 115037f219c8SBruno Larsen (billionai) 115137f219c8SBruno Larsen (billionai) /* 115237f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 115337f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 115437f219c8SBruno Larsen (billionai) */ 115537f219c8SBruno Larsen (billionai) 115637f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 115737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 115837f219c8SBruno Larsen (billionai) 115937f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 116037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 116137f219c8SBruno Larsen (billionai) 116237f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 116337f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 116437f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 116537f219c8SBruno Larsen (billionai) 116637f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 116737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 116837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 116937f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 117037f219c8SBruno Larsen (billionai) 117137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 117237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 117337f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 117437f219c8SBruno Larsen (billionai) } 117537f219c8SBruno Larsen (billionai) #endif 117637f219c8SBruno Larsen (billionai) #endif 117737f219c8SBruno Larsen (billionai) 117837f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1179a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 118037f219c8SBruno Larsen (billionai) { 118137f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 118237f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 118337f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 118437f219c8SBruno Larsen (billionai) } 118537f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 118637f219c8SBruno Larsen (billionai) 118737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1188a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 118937f219c8SBruno Larsen (billionai) { 119037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 119137f219c8SBruno Larsen (billionai) 119237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 119337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 119437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 119537f219c8SBruno Larsen (billionai) } 119637f219c8SBruno Larsen (billionai) 1197a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 119837f219c8SBruno Larsen (billionai) { 119937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 120037f219c8SBruno Larsen (billionai) 120137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 120237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 120337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 120437f219c8SBruno Larsen (billionai) } 120537f219c8SBruno Larsen (billionai) 1206a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 120737f219c8SBruno Larsen (billionai) { 120837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 120937f219c8SBruno Larsen (billionai) 121037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 121137f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 121237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 121337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 121437f219c8SBruno Larsen (billionai) } 121537f219c8SBruno Larsen (billionai) 1216a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 121737f219c8SBruno Larsen (billionai) { 121837f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 121937f219c8SBruno Larsen (billionai) } 122037f219c8SBruno Larsen (billionai) 1221a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 122237f219c8SBruno Larsen (billionai) { 122337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 122437f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 122537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 122637f219c8SBruno Larsen (billionai) } 1227a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 122837f219c8SBruno Larsen (billionai) { 122937f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 123037f219c8SBruno Larsen (billionai) } 1231a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 123237f219c8SBruno Larsen (billionai) { 123337f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 123437f219c8SBruno Larsen (billionai) } 123537f219c8SBruno Larsen (billionai) 123637f219c8SBruno Larsen (billionai) #endif 123737f219c8SBruno Larsen (billionai) 123837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1239a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 124037f219c8SBruno Larsen (billionai) { 124137f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 124237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 124337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 124437f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 124537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 124637f219c8SBruno Larsen (billionai) tcg_temp_free(val); 124737f219c8SBruno Larsen (billionai) } 124837f219c8SBruno Larsen (billionai) 1249a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 125037f219c8SBruno Larsen (billionai) { 125137f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 125237f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 125337f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 125437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 125537f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 125637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 125737f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 125837f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 125937f219c8SBruno Larsen (billionai) } 126037f219c8SBruno Larsen (billionai) 126137f219c8SBruno Larsen (billionai) #endif 126237f219c8SBruno Larsen (billionai) 126337f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 126437f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 126537f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 126637f219c8SBruno Larsen (billionai) { 126737f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 126837f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 126937f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 127037f219c8SBruno Larsen (billionai) 127137f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 127237f219c8SBruno Larsen (billionai) 127337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 127437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 127537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 127637f219c8SBruno Larsen (billionai) } 127737f219c8SBruno Larsen (billionai) 127837f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 127937f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 128037f219c8SBruno Larsen (billionai) { 128137f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 128237f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 128337f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 128437f219c8SBruno Larsen (billionai) 128537f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 128637f219c8SBruno Larsen (billionai) 128737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 128837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 128937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 129037f219c8SBruno Larsen (billionai) } 129137f219c8SBruno Larsen (billionai) 1292a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 129337f219c8SBruno Larsen (billionai) { 129437f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 129537f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 129637f219c8SBruno Larsen (billionai) 129737f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 129837f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 129937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 130037f219c8SBruno Larsen (billionai) 130137f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 130237f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 130337f219c8SBruno Larsen (billionai) } 130437f219c8SBruno Larsen (billionai) 1305a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 130637f219c8SBruno Larsen (billionai) { 130737f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 130837f219c8SBruno Larsen (billionai) 130937f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 131037f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 131137f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 131237f219c8SBruno Larsen (billionai) 131337f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 131437f219c8SBruno Larsen (billionai) } 131537f219c8SBruno Larsen (billionai) 131637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1317a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 131837f219c8SBruno Larsen (billionai) { 131937f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 132037f219c8SBruno Larsen (billionai) 132137f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 132237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 132337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 132437f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 132537f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 132637f219c8SBruno Larsen (billionai) } 132737f219c8SBruno Larsen (billionai) 1328a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 132937f219c8SBruno Larsen (billionai) { 133037f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 133137f219c8SBruno Larsen (billionai) } 133237f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 133337f219c8SBruno Larsen (billionai) 1334a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 133537f219c8SBruno Larsen (billionai) { 133637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 133737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 133837f219c8SBruno Larsen (billionai) } 133937f219c8SBruno Larsen (billionai) 1340a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 134137f219c8SBruno Larsen (billionai) { 134237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 134337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 134437f219c8SBruno Larsen (billionai) } 134537f219c8SBruno Larsen (billionai) 1346a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 134737f219c8SBruno Larsen (billionai) { 134837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 134937f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 135037f219c8SBruno Larsen (billionai) } 135137f219c8SBruno Larsen (billionai) 1352a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 135337f219c8SBruno Larsen (billionai) { 135437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 135537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 135637f219c8SBruno Larsen (billionai) } 135737f219c8SBruno Larsen (billionai) 1358a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 135937f219c8SBruno Larsen (billionai) { 136037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 136137f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 136237f219c8SBruno Larsen (billionai) } 136337f219c8SBruno Larsen (billionai) 1364a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 136537f219c8SBruno Larsen (billionai) { 136637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 136737f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 136837f219c8SBruno Larsen (billionai) } 136937f219c8SBruno Larsen (billionai) 1370a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 137137f219c8SBruno Larsen (billionai) { 137237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 137337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 137437f219c8SBruno Larsen (billionai) } 137537f219c8SBruno Larsen (billionai) 1376a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 137737f219c8SBruno Larsen (billionai) { 137837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 137937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 138037f219c8SBruno Larsen (billionai) } 138137f219c8SBruno Larsen (billionai) 1382a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 138337f219c8SBruno Larsen (billionai) { 138437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 138537f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 138637f219c8SBruno Larsen (billionai) } 138737f219c8SBruno Larsen (billionai) 1388a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 138937f219c8SBruno Larsen (billionai) { 139037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 139137f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 139237f219c8SBruno Larsen (billionai) } 139337f219c8SBruno Larsen (billionai) #endif 139437f219c8SBruno Larsen (billionai) 1395fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1396fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1397fcf5ef2aSThomas Huth 1398fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1399fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1400fcf5ef2aSThomas Huth 1401fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1402fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1403fcf5ef2aSThomas Huth 1404fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1405fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1406fcf5ef2aSThomas Huth 1407fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1408fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1409fcf5ef2aSThomas Huth 1410fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1411fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1412fcf5ef2aSThomas Huth 1413fcf5ef2aSThomas Huth typedef struct opcode_t { 1414fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1415fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1416fcf5ef2aSThomas Huth unsigned char pad[4]; 1417fcf5ef2aSThomas Huth #endif 1418fcf5ef2aSThomas Huth opc_handler_t handler; 1419fcf5ef2aSThomas Huth const char *oname; 1420fcf5ef2aSThomas Huth } opcode_t; 1421fcf5ef2aSThomas Huth 1422fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1423fcf5ef2aSThomas Huth #define GEN_PRIV \ 1424fcf5ef2aSThomas Huth do { \ 1425fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1426fcf5ef2aSThomas Huth } while (0) 1427fcf5ef2aSThomas Huth 1428fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1429fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1430fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1431fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1432fcf5ef2aSThomas Huth #else 1433fcf5ef2aSThomas Huth #define CHK_HV \ 1434fcf5ef2aSThomas Huth do { \ 1435fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1436fcf5ef2aSThomas Huth GEN_PRIV; \ 1437fcf5ef2aSThomas Huth } \ 1438fcf5ef2aSThomas Huth } while (0) 1439fcf5ef2aSThomas Huth #define CHK_SV \ 1440fcf5ef2aSThomas Huth do { \ 1441fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1442fcf5ef2aSThomas Huth GEN_PRIV; \ 1443fcf5ef2aSThomas Huth } \ 1444fcf5ef2aSThomas Huth } while (0) 1445fcf5ef2aSThomas Huth #define CHK_HVRM \ 1446fcf5ef2aSThomas Huth do { \ 1447fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1448fcf5ef2aSThomas Huth GEN_PRIV; \ 1449fcf5ef2aSThomas Huth } \ 1450fcf5ef2aSThomas Huth } while (0) 1451fcf5ef2aSThomas Huth #endif 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth #define CHK_NONE 1454fcf5ef2aSThomas Huth 1455fcf5ef2aSThomas Huth /*****************************************************************************/ 1456fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1457fcf5ef2aSThomas Huth 1458fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 1459fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1460fcf5ef2aSThomas Huth { \ 1461fcf5ef2aSThomas Huth .opc1 = op1, \ 1462fcf5ef2aSThomas Huth .opc2 = op2, \ 1463fcf5ef2aSThomas Huth .opc3 = op3, \ 1464fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1465fcf5ef2aSThomas Huth .handler = { \ 1466fcf5ef2aSThomas Huth .inval1 = invl, \ 1467fcf5ef2aSThomas Huth .type = _typ, \ 1468fcf5ef2aSThomas Huth .type2 = _typ2, \ 1469fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1470fcf5ef2aSThomas Huth .oname = stringify(name), \ 1471fcf5ef2aSThomas Huth }, \ 1472fcf5ef2aSThomas Huth .oname = stringify(name), \ 1473fcf5ef2aSThomas Huth } 1474fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1475fcf5ef2aSThomas Huth { \ 1476fcf5ef2aSThomas Huth .opc1 = op1, \ 1477fcf5ef2aSThomas Huth .opc2 = op2, \ 1478fcf5ef2aSThomas Huth .opc3 = op3, \ 1479fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1480fcf5ef2aSThomas Huth .handler = { \ 1481fcf5ef2aSThomas Huth .inval1 = invl1, \ 1482fcf5ef2aSThomas Huth .inval2 = invl2, \ 1483fcf5ef2aSThomas Huth .type = _typ, \ 1484fcf5ef2aSThomas Huth .type2 = _typ2, \ 1485fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1486fcf5ef2aSThomas Huth .oname = stringify(name), \ 1487fcf5ef2aSThomas Huth }, \ 1488fcf5ef2aSThomas Huth .oname = stringify(name), \ 1489fcf5ef2aSThomas Huth } 1490fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1491fcf5ef2aSThomas Huth { \ 1492fcf5ef2aSThomas Huth .opc1 = op1, \ 1493fcf5ef2aSThomas Huth .opc2 = op2, \ 1494fcf5ef2aSThomas Huth .opc3 = op3, \ 1495fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1496fcf5ef2aSThomas Huth .handler = { \ 1497fcf5ef2aSThomas Huth .inval1 = invl, \ 1498fcf5ef2aSThomas Huth .type = _typ, \ 1499fcf5ef2aSThomas Huth .type2 = _typ2, \ 1500fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1501fcf5ef2aSThomas Huth .oname = onam, \ 1502fcf5ef2aSThomas Huth }, \ 1503fcf5ef2aSThomas Huth .oname = onam, \ 1504fcf5ef2aSThomas Huth } 1505fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1506fcf5ef2aSThomas Huth { \ 1507fcf5ef2aSThomas Huth .opc1 = op1, \ 1508fcf5ef2aSThomas Huth .opc2 = op2, \ 1509fcf5ef2aSThomas Huth .opc3 = op3, \ 1510fcf5ef2aSThomas Huth .opc4 = op4, \ 1511fcf5ef2aSThomas Huth .handler = { \ 1512fcf5ef2aSThomas Huth .inval1 = invl, \ 1513fcf5ef2aSThomas Huth .type = _typ, \ 1514fcf5ef2aSThomas Huth .type2 = _typ2, \ 1515fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1516fcf5ef2aSThomas Huth .oname = stringify(name), \ 1517fcf5ef2aSThomas Huth }, \ 1518fcf5ef2aSThomas Huth .oname = stringify(name), \ 1519fcf5ef2aSThomas Huth } 1520fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1521fcf5ef2aSThomas Huth { \ 1522fcf5ef2aSThomas Huth .opc1 = op1, \ 1523fcf5ef2aSThomas Huth .opc2 = op2, \ 1524fcf5ef2aSThomas Huth .opc3 = op3, \ 1525fcf5ef2aSThomas Huth .opc4 = op4, \ 1526fcf5ef2aSThomas Huth .handler = { \ 1527fcf5ef2aSThomas Huth .inval1 = invl, \ 1528fcf5ef2aSThomas Huth .type = _typ, \ 1529fcf5ef2aSThomas Huth .type2 = _typ2, \ 1530fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1531fcf5ef2aSThomas Huth .oname = onam, \ 1532fcf5ef2aSThomas Huth }, \ 1533fcf5ef2aSThomas Huth .oname = onam, \ 1534fcf5ef2aSThomas Huth } 1535fcf5ef2aSThomas Huth #else 1536fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1537fcf5ef2aSThomas Huth { \ 1538fcf5ef2aSThomas Huth .opc1 = op1, \ 1539fcf5ef2aSThomas Huth .opc2 = op2, \ 1540fcf5ef2aSThomas Huth .opc3 = op3, \ 1541fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1542fcf5ef2aSThomas Huth .handler = { \ 1543fcf5ef2aSThomas Huth .inval1 = invl, \ 1544fcf5ef2aSThomas Huth .type = _typ, \ 1545fcf5ef2aSThomas Huth .type2 = _typ2, \ 1546fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1547fcf5ef2aSThomas Huth }, \ 1548fcf5ef2aSThomas Huth .oname = stringify(name), \ 1549fcf5ef2aSThomas Huth } 1550fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1551fcf5ef2aSThomas Huth { \ 1552fcf5ef2aSThomas Huth .opc1 = op1, \ 1553fcf5ef2aSThomas Huth .opc2 = op2, \ 1554fcf5ef2aSThomas Huth .opc3 = op3, \ 1555fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1556fcf5ef2aSThomas Huth .handler = { \ 1557fcf5ef2aSThomas Huth .inval1 = invl1, \ 1558fcf5ef2aSThomas Huth .inval2 = invl2, \ 1559fcf5ef2aSThomas Huth .type = _typ, \ 1560fcf5ef2aSThomas Huth .type2 = _typ2, \ 1561fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1562fcf5ef2aSThomas Huth }, \ 1563fcf5ef2aSThomas Huth .oname = stringify(name), \ 1564fcf5ef2aSThomas Huth } 1565fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1566fcf5ef2aSThomas Huth { \ 1567fcf5ef2aSThomas Huth .opc1 = op1, \ 1568fcf5ef2aSThomas Huth .opc2 = op2, \ 1569fcf5ef2aSThomas Huth .opc3 = op3, \ 1570fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1571fcf5ef2aSThomas Huth .handler = { \ 1572fcf5ef2aSThomas Huth .inval1 = invl, \ 1573fcf5ef2aSThomas Huth .type = _typ, \ 1574fcf5ef2aSThomas Huth .type2 = _typ2, \ 1575fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1576fcf5ef2aSThomas Huth }, \ 1577fcf5ef2aSThomas Huth .oname = onam, \ 1578fcf5ef2aSThomas Huth } 1579fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1580fcf5ef2aSThomas Huth { \ 1581fcf5ef2aSThomas Huth .opc1 = op1, \ 1582fcf5ef2aSThomas Huth .opc2 = op2, \ 1583fcf5ef2aSThomas Huth .opc3 = op3, \ 1584fcf5ef2aSThomas Huth .opc4 = op4, \ 1585fcf5ef2aSThomas Huth .handler = { \ 1586fcf5ef2aSThomas Huth .inval1 = invl, \ 1587fcf5ef2aSThomas Huth .type = _typ, \ 1588fcf5ef2aSThomas Huth .type2 = _typ2, \ 1589fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1590fcf5ef2aSThomas Huth }, \ 1591fcf5ef2aSThomas Huth .oname = stringify(name), \ 1592fcf5ef2aSThomas Huth } 1593fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1594fcf5ef2aSThomas Huth { \ 1595fcf5ef2aSThomas Huth .opc1 = op1, \ 1596fcf5ef2aSThomas Huth .opc2 = op2, \ 1597fcf5ef2aSThomas Huth .opc3 = op3, \ 1598fcf5ef2aSThomas Huth .opc4 = op4, \ 1599fcf5ef2aSThomas Huth .handler = { \ 1600fcf5ef2aSThomas Huth .inval1 = invl, \ 1601fcf5ef2aSThomas Huth .type = _typ, \ 1602fcf5ef2aSThomas Huth .type2 = _typ2, \ 1603fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1604fcf5ef2aSThomas Huth }, \ 1605fcf5ef2aSThomas Huth .oname = onam, \ 1606fcf5ef2aSThomas Huth } 1607fcf5ef2aSThomas Huth #endif 1608fcf5ef2aSThomas Huth 1609fcf5ef2aSThomas Huth /* Invalid instruction */ 1610fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1611fcf5ef2aSThomas Huth { 1612fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1613fcf5ef2aSThomas Huth } 1614fcf5ef2aSThomas Huth 1615fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1616fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1617fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1618fcf5ef2aSThomas Huth .type = PPC_NONE, 1619fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1620fcf5ef2aSThomas Huth .handler = gen_invalid, 1621fcf5ef2aSThomas Huth }; 1622fcf5ef2aSThomas Huth 1623fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1624fcf5ef2aSThomas Huth 1625fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1626fcf5ef2aSThomas Huth { 1627fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1628b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1629b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1630fcf5ef2aSThomas Huth 1631b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1632b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1633efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1634efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1635b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1636efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1637efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1638b62b3686Spbonzini@redhat.com 1639b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1640fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1641b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1642fcf5ef2aSThomas Huth 1643fcf5ef2aSThomas Huth tcg_temp_free(t0); 1644b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1645b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1646fcf5ef2aSThomas Huth } 1647fcf5ef2aSThomas Huth 1648fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1649fcf5ef2aSThomas Huth { 1650fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1651fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1652fcf5ef2aSThomas Huth tcg_temp_free(t0); 1653fcf5ef2aSThomas Huth } 1654fcf5ef2aSThomas Huth 1655fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1656fcf5ef2aSThomas Huth { 1657fcf5ef2aSThomas Huth TCGv t0, t1; 1658fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1659fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1660fcf5ef2aSThomas Huth if (s) { 1661fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1662fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1663fcf5ef2aSThomas Huth } else { 1664fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1665fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1668fcf5ef2aSThomas Huth tcg_temp_free(t1); 1669fcf5ef2aSThomas Huth tcg_temp_free(t0); 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth 1672fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1673fcf5ef2aSThomas Huth { 1674fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1675fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1676fcf5ef2aSThomas Huth tcg_temp_free(t0); 1677fcf5ef2aSThomas Huth } 1678fcf5ef2aSThomas Huth 1679fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1680fcf5ef2aSThomas Huth { 1681fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1682fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1683fcf5ef2aSThomas Huth } else { 1684fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1685fcf5ef2aSThomas Huth } 1686fcf5ef2aSThomas Huth } 1687fcf5ef2aSThomas Huth 1688fcf5ef2aSThomas Huth /* cmp */ 1689fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1690fcf5ef2aSThomas Huth { 1691fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1692fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1693fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1694fcf5ef2aSThomas Huth } else { 1695fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1696fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1697fcf5ef2aSThomas Huth } 1698fcf5ef2aSThomas Huth } 1699fcf5ef2aSThomas Huth 1700fcf5ef2aSThomas Huth /* cmpi */ 1701fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1702fcf5ef2aSThomas Huth { 1703fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1704fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1705fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1706fcf5ef2aSThomas Huth } else { 1707fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1708fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1709fcf5ef2aSThomas Huth } 1710fcf5ef2aSThomas Huth } 1711fcf5ef2aSThomas Huth 1712fcf5ef2aSThomas Huth /* cmpl */ 1713fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1714fcf5ef2aSThomas Huth { 1715fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1716fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1717fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1718fcf5ef2aSThomas Huth } else { 1719fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1720fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1721fcf5ef2aSThomas Huth } 1722fcf5ef2aSThomas Huth } 1723fcf5ef2aSThomas Huth 1724fcf5ef2aSThomas Huth /* cmpli */ 1725fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1726fcf5ef2aSThomas Huth { 1727fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1728fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1729fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1730fcf5ef2aSThomas Huth } else { 1731fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1732fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1733fcf5ef2aSThomas Huth } 1734fcf5ef2aSThomas Huth } 1735fcf5ef2aSThomas Huth 1736fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1737fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1738fcf5ef2aSThomas Huth { 1739fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1740fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1741fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1742fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1743fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1744fcf5ef2aSThomas Huth 1745fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1746fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1747fcf5ef2aSThomas Huth 1748fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1749fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1750fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1751fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1752fcf5ef2aSThomas Huth 1753fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1754fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1755fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1756fcf5ef2aSThomas Huth 1757fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1758fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1759fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1760fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1761fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1762fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1763fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1764fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1765fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1766fcf5ef2aSThomas Huth } 1767efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1768fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1769fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1770fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1771fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1772fcf5ef2aSThomas Huth } 1773fcf5ef2aSThomas Huth 1774fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1775fcf5ef2aSThomas Huth /* cmpeqb */ 1776fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1777fcf5ef2aSThomas Huth { 1778fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1779fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1780fcf5ef2aSThomas Huth } 1781fcf5ef2aSThomas Huth #endif 1782fcf5ef2aSThomas Huth 1783fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1784fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1785fcf5ef2aSThomas Huth { 1786fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1787fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1788fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1789fcf5ef2aSThomas Huth TCGv zr; 1790fcf5ef2aSThomas Huth 1791fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1792fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1793fcf5ef2aSThomas Huth 1794fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1795fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1796fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1797fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1798fcf5ef2aSThomas Huth tcg_temp_free(zr); 1799fcf5ef2aSThomas Huth tcg_temp_free(t0); 1800fcf5ef2aSThomas Huth } 1801fcf5ef2aSThomas Huth 1802fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1803fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1804fcf5ef2aSThomas Huth { 1805fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1806fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1807fcf5ef2aSThomas Huth } 1808fcf5ef2aSThomas Huth 1809fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1810fcf5ef2aSThomas Huth 1811fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1812fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1813fcf5ef2aSThomas Huth { 1814fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1815fcf5ef2aSThomas Huth 1816fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1817fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1818fcf5ef2aSThomas Huth if (sub) { 1819fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1820fcf5ef2aSThomas Huth } else { 1821fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1822fcf5ef2aSThomas Huth } 1823fcf5ef2aSThomas Huth tcg_temp_free(t0); 1824fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1825dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1826dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1827dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1828fcf5ef2aSThomas Huth } 1829dc0ad844SNikunj A Dadhania } else { 1830dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1831dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1832dc0ad844SNikunj A Dadhania } 183338a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1834dc0ad844SNikunj A Dadhania } 1835fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1836fcf5ef2aSThomas Huth } 1837fcf5ef2aSThomas Huth 18386b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 18396b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 18404c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 18416b10d008SNikunj A Dadhania { 18426b10d008SNikunj A Dadhania TCGv t0; 18436b10d008SNikunj A Dadhania 18446b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 18456b10d008SNikunj A Dadhania return; 18466b10d008SNikunj A Dadhania } 18476b10d008SNikunj A Dadhania 18486b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 184933903d0aSNikunj A Dadhania if (sub) { 185033903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 185133903d0aSNikunj A Dadhania } else { 18526b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 185333903d0aSNikunj A Dadhania } 18546b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 18554c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 18566b10d008SNikunj A Dadhania tcg_temp_free(t0); 18576b10d008SNikunj A Dadhania } 18586b10d008SNikunj A Dadhania 1859fcf5ef2aSThomas Huth /* Common add function */ 1860fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 18614c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 18624c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1863fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1864fcf5ef2aSThomas Huth { 1865fcf5ef2aSThomas Huth TCGv t0 = ret; 1866fcf5ef2aSThomas Huth 1867fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1868fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1869fcf5ef2aSThomas Huth } 1870fcf5ef2aSThomas Huth 1871fcf5ef2aSThomas Huth if (compute_ca) { 1872fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1873efe843d8SDavid Gibson /* 1874efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1875efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1876efe843d8SDavid Gibson * produce the carry into bit 32. 1877efe843d8SDavid Gibson */ 1878fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1879fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1880fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1881fcf5ef2aSThomas Huth if (add_ca) { 18824c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1883fcf5ef2aSThomas Huth } 18844c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1885fcf5ef2aSThomas Huth tcg_temp_free(t1); 18864c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 18876b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 18884c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 18896b10d008SNikunj A Dadhania } 1890fcf5ef2aSThomas Huth } else { 1891fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1892fcf5ef2aSThomas Huth if (add_ca) { 18934c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 18944c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1895fcf5ef2aSThomas Huth } else { 18964c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1897fcf5ef2aSThomas Huth } 18984c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1899fcf5ef2aSThomas Huth tcg_temp_free(zero); 1900fcf5ef2aSThomas Huth } 1901fcf5ef2aSThomas Huth } else { 1902fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1903fcf5ef2aSThomas Huth if (add_ca) { 19044c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1905fcf5ef2aSThomas Huth } 1906fcf5ef2aSThomas Huth } 1907fcf5ef2aSThomas Huth 1908fcf5ef2aSThomas Huth if (compute_ov) { 1909fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1910fcf5ef2aSThomas Huth } 1911fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1912fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth 191511f4e8f8SRichard Henderson if (t0 != ret) { 1916fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1917fcf5ef2aSThomas Huth tcg_temp_free(t0); 1918fcf5ef2aSThomas Huth } 1919fcf5ef2aSThomas Huth } 1920fcf5ef2aSThomas Huth /* Add functions with two operands */ 19214c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1922fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1923fcf5ef2aSThomas Huth { \ 1924fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1925fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 19264c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1927fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1928fcf5ef2aSThomas Huth } 1929fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 19304c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1931fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1932fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1933fcf5ef2aSThomas Huth { \ 1934fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1935fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1936fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 19374c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1938fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1939fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1940fcf5ef2aSThomas Huth } 1941fcf5ef2aSThomas Huth 1942fcf5ef2aSThomas Huth /* add add. addo addo. */ 19434c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 19444c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1945fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 19464c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 19474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1948fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 19494c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 19504c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1951fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 19524c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 19534c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 19544c5920afSSuraj Jitindar Singh /* addex */ 19554c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1956fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 19574c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 19584c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1959fcf5ef2aSThomas Huth /* addi */ 1960fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 1961fcf5ef2aSThomas Huth { 1962fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1963fcf5ef2aSThomas Huth 1964fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1965fcf5ef2aSThomas Huth /* li case */ 1966fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 1967fcf5ef2aSThomas Huth } else { 1968fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1969fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 1970fcf5ef2aSThomas Huth } 1971fcf5ef2aSThomas Huth } 1972fcf5ef2aSThomas Huth /* addic addic.*/ 1973fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1974fcf5ef2aSThomas Huth { 1975fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1976fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 19774c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1978fcf5ef2aSThomas Huth tcg_temp_free(c); 1979fcf5ef2aSThomas Huth } 1980fcf5ef2aSThomas Huth 1981fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1982fcf5ef2aSThomas Huth { 1983fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1984fcf5ef2aSThomas Huth } 1985fcf5ef2aSThomas Huth 1986fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1987fcf5ef2aSThomas Huth { 1988fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1989fcf5ef2aSThomas Huth } 1990fcf5ef2aSThomas Huth 1991fcf5ef2aSThomas Huth /* addis */ 1992fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 1993fcf5ef2aSThomas Huth { 1994fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1995fcf5ef2aSThomas Huth 1996fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1997fcf5ef2aSThomas Huth /* lis case */ 1998fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 1999fcf5ef2aSThomas Huth } else { 2000fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 2001fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 2002fcf5ef2aSThomas Huth } 2003fcf5ef2aSThomas Huth } 2004fcf5ef2aSThomas Huth 2005fcf5ef2aSThomas Huth /* addpcis */ 2006fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 2007fcf5ef2aSThomas Huth { 2008fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 2009fcf5ef2aSThomas Huth 2010b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 2011fcf5ef2aSThomas Huth } 2012fcf5ef2aSThomas Huth 2013fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 2014fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2015fcf5ef2aSThomas Huth { 2016fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2017fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2018fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2019fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2020fcf5ef2aSThomas Huth 2021fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2022fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2023fcf5ef2aSThomas Huth if (sign) { 2024fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2025fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2026fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2027fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2028fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2029fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2030fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2031fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 2032fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2033fcf5ef2aSThomas Huth } else { 2034fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 2035fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2036fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2037fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 2038fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2039fcf5ef2aSThomas Huth } 2040fcf5ef2aSThomas Huth if (compute_ov) { 2041fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 2042c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2043c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 2044c44027ffSNikunj A Dadhania } 2045fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2046fcf5ef2aSThomas Huth } 2047fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2048fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2049fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2050fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2051fcf5ef2aSThomas Huth 2052efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2053fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2054fcf5ef2aSThomas Huth } 2055efe843d8SDavid Gibson } 2056fcf5ef2aSThomas Huth /* Div functions */ 2057fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 2058fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2059fcf5ef2aSThomas Huth { \ 2060fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2061fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2062fcf5ef2aSThomas Huth sign, compute_ov); \ 2063fcf5ef2aSThomas Huth } 2064fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 2065fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 2066fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 2067fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 2068fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 2069fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 2070fcf5ef2aSThomas Huth 2071fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 2072fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 2073fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 2074fcf5ef2aSThomas Huth { \ 2075fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 2076fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 2077fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 2078fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 2079fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 2080fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 2081fcf5ef2aSThomas Huth } \ 2082fcf5ef2aSThomas Huth } 2083fcf5ef2aSThomas Huth 2084fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 2085fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 2086fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 2087fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 2088fcf5ef2aSThomas Huth 2089fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2090fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 2091fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2092fcf5ef2aSThomas Huth { 2093fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2094fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2095fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2096fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2097fcf5ef2aSThomas Huth 2098fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2099fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2100fcf5ef2aSThomas Huth if (sign) { 2101fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2102fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2103fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2104fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2105fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2106fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2107fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2108fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 2109fcf5ef2aSThomas Huth } else { 2110fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 2111fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2112fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2113fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 2114fcf5ef2aSThomas Huth } 2115fcf5ef2aSThomas Huth if (compute_ov) { 2116fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 2117c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2118c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 2119c44027ffSNikunj A Dadhania } 2120fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2121fcf5ef2aSThomas Huth } 2122fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2123fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2124fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2125fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2126fcf5ef2aSThomas Huth 2127efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2128fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2129fcf5ef2aSThomas Huth } 2130efe843d8SDavid Gibson } 2131fcf5ef2aSThomas Huth 2132fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 2133fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2134fcf5ef2aSThomas Huth { \ 2135fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2136fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2137fcf5ef2aSThomas Huth sign, compute_ov); \ 2138fcf5ef2aSThomas Huth } 2139c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 2140fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 2141fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 2142c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 2143fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 2144fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 2145fcf5ef2aSThomas Huth 2146fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 2147fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 2148fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 2149fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 2150fcf5ef2aSThomas Huth #endif 2151fcf5ef2aSThomas Huth 2152fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 2153fcf5ef2aSThomas Huth TCGv arg2, int sign) 2154fcf5ef2aSThomas Huth { 2155fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2156fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2157fcf5ef2aSThomas Huth 2158fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2159fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2160fcf5ef2aSThomas Huth if (sign) { 2161fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2162fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2163fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2164fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2165fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2166fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2167fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2168fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2169fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2170fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 2171fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 2172fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2173fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2174fcf5ef2aSThomas Huth } else { 2175fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 2176fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 2177fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 2178fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 2179fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2180fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2181fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2182fcf5ef2aSThomas Huth } 2183fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2184fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2185fcf5ef2aSThomas Huth } 2186fcf5ef2aSThomas Huth 2187fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 2188fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2189fcf5ef2aSThomas Huth { \ 2190fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2191fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2192fcf5ef2aSThomas Huth sign); \ 2193fcf5ef2aSThomas Huth } 2194fcf5ef2aSThomas Huth 2195fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 2196fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 2197fcf5ef2aSThomas Huth 2198fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2199fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 2200fcf5ef2aSThomas Huth TCGv arg2, int sign) 2201fcf5ef2aSThomas Huth { 2202fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2203fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2204fcf5ef2aSThomas Huth 2205fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2206fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2207fcf5ef2aSThomas Huth if (sign) { 2208fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2209fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2210fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2211fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2212fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2213fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2214fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2215fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2216fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2217fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 2218fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2219fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2220fcf5ef2aSThomas Huth } else { 2221fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 2222fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2223fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2224fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2225fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2226fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2227fcf5ef2aSThomas Huth } 2228fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2229fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2230fcf5ef2aSThomas Huth } 2231fcf5ef2aSThomas Huth 2232fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2233fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2234fcf5ef2aSThomas Huth { \ 2235fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2236fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2237fcf5ef2aSThomas Huth sign); \ 2238fcf5ef2aSThomas Huth } 2239fcf5ef2aSThomas Huth 2240fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2241fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2242fcf5ef2aSThomas Huth #endif 2243fcf5ef2aSThomas Huth 2244fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2245fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2246fcf5ef2aSThomas Huth { 2247fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2248fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2249fcf5ef2aSThomas Huth 2250fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2251fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2252fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2253fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2254fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2255fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2256efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2257fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2258fcf5ef2aSThomas Huth } 2259efe843d8SDavid Gibson } 2260fcf5ef2aSThomas Huth 2261fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2262fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2263fcf5ef2aSThomas Huth { 2264fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2265fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2266fcf5ef2aSThomas Huth 2267fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2268fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2269fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2270fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2271fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2272fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2273efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2274fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2275fcf5ef2aSThomas Huth } 2276efe843d8SDavid Gibson } 2277fcf5ef2aSThomas Huth 2278fcf5ef2aSThomas Huth /* mullw mullw. */ 2279fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2280fcf5ef2aSThomas Huth { 2281fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2282fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2283fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2284fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2285fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2286fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2287fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2288fcf5ef2aSThomas Huth tcg_temp_free(t0); 2289fcf5ef2aSThomas Huth tcg_temp_free(t1); 2290fcf5ef2aSThomas Huth #else 2291fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2292fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2293fcf5ef2aSThomas Huth #endif 2294efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2295fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2296fcf5ef2aSThomas Huth } 2297efe843d8SDavid Gibson } 2298fcf5ef2aSThomas Huth 2299fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2300fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2301fcf5ef2aSThomas Huth { 2302fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2303fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2304fcf5ef2aSThomas Huth 2305fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2306fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2307fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2308fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2309fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2310fcf5ef2aSThomas Huth #else 2311fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2312fcf5ef2aSThomas Huth #endif 2313fcf5ef2aSThomas Huth 2314fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2315fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2316fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 231761aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 231861aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 231961aa9a69SNikunj A Dadhania } 2320fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2321fcf5ef2aSThomas Huth 2322fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2323fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2324efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2325fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2326fcf5ef2aSThomas Huth } 2327efe843d8SDavid Gibson } 2328fcf5ef2aSThomas Huth 2329fcf5ef2aSThomas Huth /* mulli */ 2330fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2331fcf5ef2aSThomas Huth { 2332fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2333fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2334fcf5ef2aSThomas Huth } 2335fcf5ef2aSThomas Huth 2336fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2337fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2338fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2339fcf5ef2aSThomas Huth { 2340fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2341fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2342fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2343fcf5ef2aSThomas Huth tcg_temp_free(lo); 2344fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2345fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2346fcf5ef2aSThomas Huth } 2347fcf5ef2aSThomas Huth } 2348fcf5ef2aSThomas Huth 2349fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2350fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2351fcf5ef2aSThomas Huth { 2352fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2353fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2354fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2355fcf5ef2aSThomas Huth tcg_temp_free(lo); 2356fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2357fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2358fcf5ef2aSThomas Huth } 2359fcf5ef2aSThomas Huth } 2360fcf5ef2aSThomas Huth 2361fcf5ef2aSThomas Huth /* mulld mulld. */ 2362fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2363fcf5ef2aSThomas Huth { 2364fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2365fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2366efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2367fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2368fcf5ef2aSThomas Huth } 2369efe843d8SDavid Gibson } 2370fcf5ef2aSThomas Huth 2371fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2372fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2373fcf5ef2aSThomas Huth { 2374fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2375fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2376fcf5ef2aSThomas Huth 2377fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2378fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2379fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2380fcf5ef2aSThomas Huth 2381fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2382fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 238361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 238461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 238561aa9a69SNikunj A Dadhania } 2386fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2387fcf5ef2aSThomas Huth 2388fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2389fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2390fcf5ef2aSThomas Huth 2391fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2392fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2393fcf5ef2aSThomas Huth } 2394fcf5ef2aSThomas Huth } 2395fcf5ef2aSThomas Huth #endif 2396fcf5ef2aSThomas Huth 2397fcf5ef2aSThomas Huth /* Common subf function */ 2398fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2399fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2400fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2401fcf5ef2aSThomas Huth { 2402fcf5ef2aSThomas Huth TCGv t0 = ret; 2403fcf5ef2aSThomas Huth 2404fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2405fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2406fcf5ef2aSThomas Huth } 2407fcf5ef2aSThomas Huth 2408fcf5ef2aSThomas Huth if (compute_ca) { 2409fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2410fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2411efe843d8SDavid Gibson /* 2412efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2413efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2414efe843d8SDavid Gibson * produce the carry into bit 32. 2415efe843d8SDavid Gibson */ 2416fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2417fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2418fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2419fcf5ef2aSThomas Huth if (add_ca) { 2420fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2421fcf5ef2aSThomas Huth } else { 2422fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2423fcf5ef2aSThomas Huth } 2424fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2425fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2426fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2427fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2428fcf5ef2aSThomas Huth tcg_temp_free(t1); 2429e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 243033903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 243133903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 243233903d0aSNikunj A Dadhania } 2433fcf5ef2aSThomas Huth } else if (add_ca) { 2434fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2435fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2436fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2437fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2438fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 24394c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2440fcf5ef2aSThomas Huth tcg_temp_free(zero); 2441fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2442fcf5ef2aSThomas Huth } else { 2443fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2444fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 24454c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2446fcf5ef2aSThomas Huth } 2447fcf5ef2aSThomas Huth } else if (add_ca) { 2448efe843d8SDavid Gibson /* 2449efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2450efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2451efe843d8SDavid Gibson */ 2452fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2453fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2454fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2455fcf5ef2aSThomas Huth } else { 2456fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2457fcf5ef2aSThomas Huth } 2458fcf5ef2aSThomas Huth 2459fcf5ef2aSThomas Huth if (compute_ov) { 2460fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2461fcf5ef2aSThomas Huth } 2462fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2463fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2464fcf5ef2aSThomas Huth } 2465fcf5ef2aSThomas Huth 246611f4e8f8SRichard Henderson if (t0 != ret) { 2467fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2468fcf5ef2aSThomas Huth tcg_temp_free(t0); 2469fcf5ef2aSThomas Huth } 2470fcf5ef2aSThomas Huth } 2471fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2472fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2473fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2474fcf5ef2aSThomas Huth { \ 2475fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2476fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2477fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2478fcf5ef2aSThomas Huth } 2479fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2480fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2481fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2482fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2483fcf5ef2aSThomas Huth { \ 2484fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2485fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2486fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2487fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2488fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2489fcf5ef2aSThomas Huth } 2490fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2491fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2492fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2493fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2494fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2495fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2496fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2497fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2498fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2499fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2500fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2501fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2502fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2503fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2504fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2505fcf5ef2aSThomas Huth 2506fcf5ef2aSThomas Huth /* subfic */ 2507fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2508fcf5ef2aSThomas Huth { 2509fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2510fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2511fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2512fcf5ef2aSThomas Huth tcg_temp_free(c); 2513fcf5ef2aSThomas Huth } 2514fcf5ef2aSThomas Huth 2515fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2516fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2517fcf5ef2aSThomas Huth { 2518fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2519fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2520fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2521fcf5ef2aSThomas Huth tcg_temp_free(zero); 2522fcf5ef2aSThomas Huth } 2523fcf5ef2aSThomas Huth 2524fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2525fcf5ef2aSThomas Huth { 25261480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 25271480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 25281480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 25291480d71cSNikunj A Dadhania } 2530fcf5ef2aSThomas Huth } 2531fcf5ef2aSThomas Huth 2532fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2533fcf5ef2aSThomas Huth { 2534fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2535fcf5ef2aSThomas Huth } 2536fcf5ef2aSThomas Huth 2537fcf5ef2aSThomas Huth /*** Integer logical ***/ 2538fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2539fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2540fcf5ef2aSThomas Huth { \ 2541fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2542fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2543fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2544fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2545fcf5ef2aSThomas Huth } 2546fcf5ef2aSThomas Huth 2547fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2548fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2549fcf5ef2aSThomas Huth { \ 2550fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2551fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2552fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2553fcf5ef2aSThomas Huth } 2554fcf5ef2aSThomas Huth 2555fcf5ef2aSThomas Huth /* and & and. */ 2556fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2557fcf5ef2aSThomas Huth /* andc & andc. */ 2558fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2559fcf5ef2aSThomas Huth 2560fcf5ef2aSThomas Huth /* andi. */ 2561fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2562fcf5ef2aSThomas Huth { 2563efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2564efe843d8SDavid Gibson UIMM(ctx->opcode)); 2565fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2566fcf5ef2aSThomas Huth } 2567fcf5ef2aSThomas Huth 2568fcf5ef2aSThomas Huth /* andis. */ 2569fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2570fcf5ef2aSThomas Huth { 2571efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2572efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2573fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2574fcf5ef2aSThomas Huth } 2575fcf5ef2aSThomas Huth 2576fcf5ef2aSThomas Huth /* cntlzw */ 2577fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2578fcf5ef2aSThomas Huth { 25799b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 25809b8514e5SRichard Henderson 25819b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 25829b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 25839b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 25849b8514e5SRichard Henderson tcg_temp_free_i32(t); 25859b8514e5SRichard Henderson 2586efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2587fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2588fcf5ef2aSThomas Huth } 2589efe843d8SDavid Gibson } 2590fcf5ef2aSThomas Huth 2591fcf5ef2aSThomas Huth /* cnttzw */ 2592fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2593fcf5ef2aSThomas Huth { 25949b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 25959b8514e5SRichard Henderson 25969b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 25979b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 25989b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 25999b8514e5SRichard Henderson tcg_temp_free_i32(t); 26009b8514e5SRichard Henderson 2601fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2602fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2603fcf5ef2aSThomas Huth } 2604fcf5ef2aSThomas Huth } 2605fcf5ef2aSThomas Huth 2606fcf5ef2aSThomas Huth /* eqv & eqv. */ 2607fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2608fcf5ef2aSThomas Huth /* extsb & extsb. */ 2609fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2610fcf5ef2aSThomas Huth /* extsh & extsh. */ 2611fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2612fcf5ef2aSThomas Huth /* nand & nand. */ 2613fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2614fcf5ef2aSThomas Huth /* nor & nor. */ 2615fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2616fcf5ef2aSThomas Huth 2617fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2618fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2619fcf5ef2aSThomas Huth { 2620fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2621fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2622fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2623fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2624fcf5ef2aSThomas Huth 2625fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2626b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2627fcf5ef2aSThomas Huth } 2628fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2629fcf5ef2aSThomas Huth 2630fcf5ef2aSThomas Huth /* or & or. */ 2631fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2632fcf5ef2aSThomas Huth { 2633fcf5ef2aSThomas Huth int rs, ra, rb; 2634fcf5ef2aSThomas Huth 2635fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2636fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2637fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2638fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2639fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2640efe843d8SDavid Gibson if (rs != rb) { 2641fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2642efe843d8SDavid Gibson } else { 2643fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2644efe843d8SDavid Gibson } 2645efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2646fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2647efe843d8SDavid Gibson } 2648fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2649fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2650fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2651fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2652fcf5ef2aSThomas Huth int prio = 0; 2653fcf5ef2aSThomas Huth 2654fcf5ef2aSThomas Huth switch (rs) { 2655fcf5ef2aSThomas Huth case 1: 2656fcf5ef2aSThomas Huth /* Set process priority to low */ 2657fcf5ef2aSThomas Huth prio = 2; 2658fcf5ef2aSThomas Huth break; 2659fcf5ef2aSThomas Huth case 6: 2660fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2661fcf5ef2aSThomas Huth prio = 3; 2662fcf5ef2aSThomas Huth break; 2663fcf5ef2aSThomas Huth case 2: 2664fcf5ef2aSThomas Huth /* Set process priority to normal */ 2665fcf5ef2aSThomas Huth prio = 4; 2666fcf5ef2aSThomas Huth break; 2667fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2668fcf5ef2aSThomas Huth case 31: 2669fcf5ef2aSThomas Huth if (!ctx->pr) { 2670fcf5ef2aSThomas Huth /* Set process priority to very low */ 2671fcf5ef2aSThomas Huth prio = 1; 2672fcf5ef2aSThomas Huth } 2673fcf5ef2aSThomas Huth break; 2674fcf5ef2aSThomas Huth case 5: 2675fcf5ef2aSThomas Huth if (!ctx->pr) { 2676fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2677fcf5ef2aSThomas Huth prio = 5; 2678fcf5ef2aSThomas Huth } 2679fcf5ef2aSThomas Huth break; 2680fcf5ef2aSThomas Huth case 3: 2681fcf5ef2aSThomas Huth if (!ctx->pr) { 2682fcf5ef2aSThomas Huth /* Set process priority to high */ 2683fcf5ef2aSThomas Huth prio = 6; 2684fcf5ef2aSThomas Huth } 2685fcf5ef2aSThomas Huth break; 2686fcf5ef2aSThomas Huth case 7: 2687fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2688fcf5ef2aSThomas Huth /* Set process priority to very high */ 2689fcf5ef2aSThomas Huth prio = 7; 2690fcf5ef2aSThomas Huth } 2691fcf5ef2aSThomas Huth break; 2692fcf5ef2aSThomas Huth #endif 2693fcf5ef2aSThomas Huth default: 2694fcf5ef2aSThomas Huth break; 2695fcf5ef2aSThomas Huth } 2696fcf5ef2aSThomas Huth if (prio) { 2697fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2698fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2699fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2700fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2701fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2702fcf5ef2aSThomas Huth tcg_temp_free(t0); 2703fcf5ef2aSThomas Huth } 2704fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2705efe843d8SDavid Gibson /* 2706efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2707efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2708efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2709efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2710fcf5ef2aSThomas Huth */ 2711fcf5ef2aSThomas Huth gen_pause(ctx); 2712fcf5ef2aSThomas Huth #endif 2713fcf5ef2aSThomas Huth #endif 2714fcf5ef2aSThomas Huth } 2715fcf5ef2aSThomas Huth } 2716fcf5ef2aSThomas Huth /* orc & orc. */ 2717fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2718fcf5ef2aSThomas Huth 2719fcf5ef2aSThomas Huth /* xor & xor. */ 2720fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2721fcf5ef2aSThomas Huth { 2722fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2723efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2724efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2725efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2726efe843d8SDavid Gibson } else { 2727fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2728efe843d8SDavid Gibson } 2729efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2730fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2731fcf5ef2aSThomas Huth } 2732efe843d8SDavid Gibson } 2733fcf5ef2aSThomas Huth 2734fcf5ef2aSThomas Huth /* ori */ 2735fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2736fcf5ef2aSThomas Huth { 2737fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2738fcf5ef2aSThomas Huth 2739fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2740fcf5ef2aSThomas Huth return; 2741fcf5ef2aSThomas Huth } 2742fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2743fcf5ef2aSThomas Huth } 2744fcf5ef2aSThomas Huth 2745fcf5ef2aSThomas Huth /* oris */ 2746fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2747fcf5ef2aSThomas Huth { 2748fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2751fcf5ef2aSThomas Huth /* NOP */ 2752fcf5ef2aSThomas Huth return; 2753fcf5ef2aSThomas Huth } 2754efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2755efe843d8SDavid Gibson uimm << 16); 2756fcf5ef2aSThomas Huth } 2757fcf5ef2aSThomas Huth 2758fcf5ef2aSThomas Huth /* xori */ 2759fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2760fcf5ef2aSThomas Huth { 2761fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2762fcf5ef2aSThomas Huth 2763fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2764fcf5ef2aSThomas Huth /* NOP */ 2765fcf5ef2aSThomas Huth return; 2766fcf5ef2aSThomas Huth } 2767fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2768fcf5ef2aSThomas Huth } 2769fcf5ef2aSThomas Huth 2770fcf5ef2aSThomas Huth /* xoris */ 2771fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2772fcf5ef2aSThomas Huth { 2773fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2774fcf5ef2aSThomas Huth 2775fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2776fcf5ef2aSThomas Huth /* NOP */ 2777fcf5ef2aSThomas Huth return; 2778fcf5ef2aSThomas Huth } 2779efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2780efe843d8SDavid Gibson uimm << 16); 2781fcf5ef2aSThomas Huth } 2782fcf5ef2aSThomas Huth 2783fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2784fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2785fcf5ef2aSThomas Huth { 2786fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2787fcf5ef2aSThomas Huth } 2788fcf5ef2aSThomas Huth 2789fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2790fcf5ef2aSThomas Huth { 279179770002SRichard Henderson #if defined(TARGET_PPC64) 2792fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 279379770002SRichard Henderson #else 279479770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 279579770002SRichard Henderson #endif 2796fcf5ef2aSThomas Huth } 2797fcf5ef2aSThomas Huth 2798fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2799fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2800fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2801fcf5ef2aSThomas Huth { 280279770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2803fcf5ef2aSThomas Huth } 2804fcf5ef2aSThomas Huth #endif 2805fcf5ef2aSThomas Huth 2806fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2807fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2808fcf5ef2aSThomas Huth { 2809fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2810fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2811fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2812fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2813fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2814fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2815fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2816fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2817fcf5ef2aSThomas Huth tcg_temp_free(t0); 2818fcf5ef2aSThomas Huth } 2819fcf5ef2aSThomas Huth 2820fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2821fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2822fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2823fcf5ef2aSThomas Huth { 2824fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2825fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2826fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2827fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2828fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2829fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2830fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2831fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2832fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2833fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2834fcf5ef2aSThomas Huth tcg_temp_free(t0); 2835fcf5ef2aSThomas Huth } 2836fcf5ef2aSThomas Huth #endif 2837fcf5ef2aSThomas Huth 2838fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2839fcf5ef2aSThomas Huth /* bpermd */ 2840fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2841fcf5ef2aSThomas Huth { 2842fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2843fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2844fcf5ef2aSThomas Huth } 2845fcf5ef2aSThomas Huth #endif 2846fcf5ef2aSThomas Huth 2847fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2848fcf5ef2aSThomas Huth /* extsw & extsw. */ 2849fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2850fcf5ef2aSThomas Huth 2851fcf5ef2aSThomas Huth /* cntlzd */ 2852fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2853fcf5ef2aSThomas Huth { 28549b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2855efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2856fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2857fcf5ef2aSThomas Huth } 2858efe843d8SDavid Gibson } 2859fcf5ef2aSThomas Huth 2860fcf5ef2aSThomas Huth /* cnttzd */ 2861fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2862fcf5ef2aSThomas Huth { 28639b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2864fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2865fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2866fcf5ef2aSThomas Huth } 2867fcf5ef2aSThomas Huth } 2868fcf5ef2aSThomas Huth 2869fcf5ef2aSThomas Huth /* darn */ 2870fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2871fcf5ef2aSThomas Huth { 2872fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2873fcf5ef2aSThomas Huth 28747e4357f6SRichard Henderson if (l > 2) { 28757e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 28767e4357f6SRichard Henderson } else { 28777e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28787e4357f6SRichard Henderson gen_io_start(); 28797e4357f6SRichard Henderson } 2880fcf5ef2aSThomas Huth if (l == 0) { 2881fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 28827e4357f6SRichard Henderson } else { 2883fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2884fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 28857e4357f6SRichard Henderson } 28867e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28877e4357f6SRichard Henderson gen_stop_exception(ctx); 28887e4357f6SRichard Henderson } 2889fcf5ef2aSThomas Huth } 2890fcf5ef2aSThomas Huth } 2891fcf5ef2aSThomas Huth #endif 2892fcf5ef2aSThomas Huth 2893fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2894fcf5ef2aSThomas Huth 2895fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2896fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2897fcf5ef2aSThomas Huth { 2898fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2899fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2900fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2901fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2902fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2903fcf5ef2aSThomas Huth 2904fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2905fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2906fcf5ef2aSThomas Huth } else { 2907fcf5ef2aSThomas Huth target_ulong mask; 2908c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2909fcf5ef2aSThomas Huth TCGv t1; 2910fcf5ef2aSThomas Huth 2911fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2912fcf5ef2aSThomas Huth mb += 32; 2913fcf5ef2aSThomas Huth me += 32; 2914fcf5ef2aSThomas Huth #endif 2915fcf5ef2aSThomas Huth mask = MASK(mb, me); 2916fcf5ef2aSThomas Huth 2917c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2918c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2919c4f6a4a3SDaniele Buono mask_in_32b = false; 2920c4f6a4a3SDaniele Buono } 2921c4f6a4a3SDaniele Buono #endif 2922fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2923c4f6a4a3SDaniele Buono if (mask_in_32b) { 2924fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2925fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2926fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2927fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2928fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2929fcf5ef2aSThomas Huth } else { 2930fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2931fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2932fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2933fcf5ef2aSThomas Huth #else 2934fcf5ef2aSThomas Huth g_assert_not_reached(); 2935fcf5ef2aSThomas Huth #endif 2936fcf5ef2aSThomas Huth } 2937fcf5ef2aSThomas Huth 2938fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2939fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2940fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2941fcf5ef2aSThomas Huth tcg_temp_free(t1); 2942fcf5ef2aSThomas Huth } 2943fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2944fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2945fcf5ef2aSThomas Huth } 2946fcf5ef2aSThomas Huth } 2947fcf5ef2aSThomas Huth 2948fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2949fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2950fcf5ef2aSThomas Huth { 2951fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2952fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 29537b4d326fSRichard Henderson int sh = SH(ctx->opcode); 29547b4d326fSRichard Henderson int mb = MB(ctx->opcode); 29557b4d326fSRichard Henderson int me = ME(ctx->opcode); 29567b4d326fSRichard Henderson int len = me - mb + 1; 29577b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2958fcf5ef2aSThomas Huth 29597b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 29607b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 29617b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 29627b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2963fcf5ef2aSThomas Huth } else { 2964fcf5ef2aSThomas Huth target_ulong mask; 2965c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2966fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2967fcf5ef2aSThomas Huth mb += 32; 2968fcf5ef2aSThomas Huth me += 32; 2969fcf5ef2aSThomas Huth #endif 2970fcf5ef2aSThomas Huth mask = MASK(mb, me); 2971c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2972c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2973c4f6a4a3SDaniele Buono mask_in_32b = false; 2974c4f6a4a3SDaniele Buono } 2975c4f6a4a3SDaniele Buono #endif 2976c4f6a4a3SDaniele Buono if (mask_in_32b) { 29777b4d326fSRichard Henderson if (sh == 0) { 29787b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 297994f040aaSVitaly Chikunov } else { 2980fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2981fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2982fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2983fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2984fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2985fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 298694f040aaSVitaly Chikunov } 2987fcf5ef2aSThomas Huth } else { 2988fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2989fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2990fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2991fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2992fcf5ef2aSThomas Huth #else 2993fcf5ef2aSThomas Huth g_assert_not_reached(); 2994fcf5ef2aSThomas Huth #endif 2995fcf5ef2aSThomas Huth } 2996fcf5ef2aSThomas Huth } 2997fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2998fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2999fcf5ef2aSThomas Huth } 3000fcf5ef2aSThomas Huth } 3001fcf5ef2aSThomas Huth 3002fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 3003fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 3004fcf5ef2aSThomas Huth { 3005fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3006fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3007fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3008fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 3009fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 3010fcf5ef2aSThomas Huth target_ulong mask; 3011c4f6a4a3SDaniele Buono bool mask_in_32b = true; 3012fcf5ef2aSThomas Huth 3013fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3014fcf5ef2aSThomas Huth mb += 32; 3015fcf5ef2aSThomas Huth me += 32; 3016fcf5ef2aSThomas Huth #endif 3017fcf5ef2aSThomas Huth mask = MASK(mb, me); 3018fcf5ef2aSThomas Huth 3019c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 3020c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 3021c4f6a4a3SDaniele Buono mask_in_32b = false; 3022c4f6a4a3SDaniele Buono } 3023c4f6a4a3SDaniele Buono #endif 3024c4f6a4a3SDaniele Buono if (mask_in_32b) { 3025fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3026fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3027fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 3028fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 3029fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 3030fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 3031fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 3032fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3033fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3034fcf5ef2aSThomas Huth } else { 3035fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3036fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 3037fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 3038fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 3039fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 3040fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 3041fcf5ef2aSThomas Huth #else 3042fcf5ef2aSThomas Huth g_assert_not_reached(); 3043fcf5ef2aSThomas Huth #endif 3044fcf5ef2aSThomas Huth } 3045fcf5ef2aSThomas Huth 3046fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 3047fcf5ef2aSThomas Huth 3048fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3049fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3050fcf5ef2aSThomas Huth } 3051fcf5ef2aSThomas Huth } 3052fcf5ef2aSThomas Huth 3053fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3054fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 3055fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3056fcf5ef2aSThomas Huth { \ 3057fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 3058fcf5ef2aSThomas Huth } \ 3059fcf5ef2aSThomas Huth \ 3060fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3061fcf5ef2aSThomas Huth { \ 3062fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 3063fcf5ef2aSThomas Huth } 3064fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 3065fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3066fcf5ef2aSThomas Huth { \ 3067fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 3068fcf5ef2aSThomas Huth } \ 3069fcf5ef2aSThomas Huth \ 3070fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3071fcf5ef2aSThomas Huth { \ 3072fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 3073fcf5ef2aSThomas Huth } \ 3074fcf5ef2aSThomas Huth \ 3075fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 3076fcf5ef2aSThomas Huth { \ 3077fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 3078fcf5ef2aSThomas Huth } \ 3079fcf5ef2aSThomas Huth \ 3080fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 3081fcf5ef2aSThomas Huth { \ 3082fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth 3085fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 3086fcf5ef2aSThomas Huth { 3087fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3088fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 30897b4d326fSRichard Henderson int len = me - mb + 1; 30907b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 3091fcf5ef2aSThomas Huth 30927b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 30937b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 30947b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 30957b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 3096fcf5ef2aSThomas Huth } else { 3097fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 3098fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3099fcf5ef2aSThomas Huth } 3100fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3101fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3102fcf5ef2aSThomas Huth } 3103fcf5ef2aSThomas Huth } 3104fcf5ef2aSThomas Huth 3105fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 3106fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 3107fcf5ef2aSThomas Huth { 3108fcf5ef2aSThomas Huth uint32_t sh, mb; 3109fcf5ef2aSThomas Huth 3110fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3111fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3112fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 3113fcf5ef2aSThomas Huth } 3114fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 3115fcf5ef2aSThomas Huth 3116fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 3117fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 3118fcf5ef2aSThomas Huth { 3119fcf5ef2aSThomas Huth uint32_t sh, me; 3120fcf5ef2aSThomas Huth 3121fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3122fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3123fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 3124fcf5ef2aSThomas Huth } 3125fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 3126fcf5ef2aSThomas Huth 3127fcf5ef2aSThomas Huth /* rldic - rldic. */ 3128fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 3129fcf5ef2aSThomas Huth { 3130fcf5ef2aSThomas Huth uint32_t sh, mb; 3131fcf5ef2aSThomas Huth 3132fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3133fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3134fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 3135fcf5ef2aSThomas Huth } 3136fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 3137fcf5ef2aSThomas Huth 3138fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 3139fcf5ef2aSThomas Huth { 3140fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3141fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3142fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3143fcf5ef2aSThomas Huth TCGv t0; 3144fcf5ef2aSThomas Huth 3145fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3146fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 3147fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 3148fcf5ef2aSThomas Huth tcg_temp_free(t0); 3149fcf5ef2aSThomas Huth 3150fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3151fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3152fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3153fcf5ef2aSThomas Huth } 3154fcf5ef2aSThomas Huth } 3155fcf5ef2aSThomas Huth 3156fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 3157fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 3158fcf5ef2aSThomas Huth { 3159fcf5ef2aSThomas Huth uint32_t mb; 3160fcf5ef2aSThomas Huth 3161fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3162fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 3163fcf5ef2aSThomas Huth } 3164fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 3165fcf5ef2aSThomas Huth 3166fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 3167fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 3168fcf5ef2aSThomas Huth { 3169fcf5ef2aSThomas Huth uint32_t me; 3170fcf5ef2aSThomas Huth 3171fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3172fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 3173fcf5ef2aSThomas Huth } 3174fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 3175fcf5ef2aSThomas Huth 3176fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 3177fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 3178fcf5ef2aSThomas Huth { 3179fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3180fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3181fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 3182fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 3183fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 3184fcf5ef2aSThomas Huth 3185fcf5ef2aSThomas Huth if (mb <= me) { 3186fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 3187fcf5ef2aSThomas Huth } else { 3188fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 3189fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3190fcf5ef2aSThomas Huth 3191fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 3192fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 3193fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 3194fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 3195fcf5ef2aSThomas Huth tcg_temp_free(t1); 3196fcf5ef2aSThomas Huth } 3197fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3198fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3199fcf5ef2aSThomas Huth } 3200fcf5ef2aSThomas Huth } 3201fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 3202fcf5ef2aSThomas Huth #endif 3203fcf5ef2aSThomas Huth 3204fcf5ef2aSThomas Huth /*** Integer shift ***/ 3205fcf5ef2aSThomas Huth 3206fcf5ef2aSThomas Huth /* slw & slw. */ 3207fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 3208fcf5ef2aSThomas Huth { 3209fcf5ef2aSThomas Huth TCGv t0, t1; 3210fcf5ef2aSThomas Huth 3211fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3212fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3213fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3214fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3215fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3216fcf5ef2aSThomas Huth #else 3217fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3218fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3219fcf5ef2aSThomas Huth #endif 3220fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3221fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3222fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3223fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3224fcf5ef2aSThomas Huth tcg_temp_free(t1); 3225fcf5ef2aSThomas Huth tcg_temp_free(t0); 3226fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 3227efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3228fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3229fcf5ef2aSThomas Huth } 3230efe843d8SDavid Gibson } 3231fcf5ef2aSThomas Huth 3232fcf5ef2aSThomas Huth /* sraw & sraw. */ 3233fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3234fcf5ef2aSThomas Huth { 3235fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3236fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3237efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3238fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3239fcf5ef2aSThomas Huth } 3240efe843d8SDavid Gibson } 3241fcf5ef2aSThomas Huth 3242fcf5ef2aSThomas Huth /* srawi & srawi. */ 3243fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3244fcf5ef2aSThomas Huth { 3245fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3246fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3247fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3248fcf5ef2aSThomas Huth if (sh == 0) { 3249fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3250fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3251af1c259fSSandipan Das if (is_isa300(ctx)) { 3252af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3253af1c259fSSandipan Das } 3254fcf5ef2aSThomas Huth } else { 3255fcf5ef2aSThomas Huth TCGv t0; 3256fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3257fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3258fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3259fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3260fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3261fcf5ef2aSThomas Huth tcg_temp_free(t0); 3262fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3263af1c259fSSandipan Das if (is_isa300(ctx)) { 3264af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3265af1c259fSSandipan Das } 3266fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3267fcf5ef2aSThomas Huth } 3268fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3269fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3270fcf5ef2aSThomas Huth } 3271fcf5ef2aSThomas Huth } 3272fcf5ef2aSThomas Huth 3273fcf5ef2aSThomas Huth /* srw & srw. */ 3274fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3275fcf5ef2aSThomas Huth { 3276fcf5ef2aSThomas Huth TCGv t0, t1; 3277fcf5ef2aSThomas Huth 3278fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3279fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3280fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3281fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3282fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3283fcf5ef2aSThomas Huth #else 3284fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3285fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3286fcf5ef2aSThomas Huth #endif 3287fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3288fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3289fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3290fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3291fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3292fcf5ef2aSThomas Huth tcg_temp_free(t1); 3293fcf5ef2aSThomas Huth tcg_temp_free(t0); 3294efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3295fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3296fcf5ef2aSThomas Huth } 3297efe843d8SDavid Gibson } 3298fcf5ef2aSThomas Huth 3299fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3300fcf5ef2aSThomas Huth /* sld & sld. */ 3301fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3302fcf5ef2aSThomas Huth { 3303fcf5ef2aSThomas Huth TCGv t0, t1; 3304fcf5ef2aSThomas Huth 3305fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3306fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3307fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3308fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3309fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3310fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3311fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3312fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3313fcf5ef2aSThomas Huth tcg_temp_free(t1); 3314fcf5ef2aSThomas Huth tcg_temp_free(t0); 3315efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3316fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3317fcf5ef2aSThomas Huth } 3318efe843d8SDavid Gibson } 3319fcf5ef2aSThomas Huth 3320fcf5ef2aSThomas Huth /* srad & srad. */ 3321fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3322fcf5ef2aSThomas Huth { 3323fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3324fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3325efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3326fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3327fcf5ef2aSThomas Huth } 3328efe843d8SDavid Gibson } 3329fcf5ef2aSThomas Huth /* sradi & sradi. */ 3330fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3331fcf5ef2aSThomas Huth { 3332fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3333fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3334fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3335fcf5ef2aSThomas Huth if (sh == 0) { 3336fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3337fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3338af1c259fSSandipan Das if (is_isa300(ctx)) { 3339af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3340af1c259fSSandipan Das } 3341fcf5ef2aSThomas Huth } else { 3342fcf5ef2aSThomas Huth TCGv t0; 3343fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3344fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3345fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3346fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3347fcf5ef2aSThomas Huth tcg_temp_free(t0); 3348fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3349af1c259fSSandipan Das if (is_isa300(ctx)) { 3350af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3351af1c259fSSandipan Das } 3352fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3353fcf5ef2aSThomas Huth } 3354fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3355fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3356fcf5ef2aSThomas Huth } 3357fcf5ef2aSThomas Huth } 3358fcf5ef2aSThomas Huth 3359fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3360fcf5ef2aSThomas Huth { 3361fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3362fcf5ef2aSThomas Huth } 3363fcf5ef2aSThomas Huth 3364fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3365fcf5ef2aSThomas Huth { 3366fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3367fcf5ef2aSThomas Huth } 3368fcf5ef2aSThomas Huth 3369fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3370fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3371fcf5ef2aSThomas Huth { 3372fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3373fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3374fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3375fcf5ef2aSThomas Huth 3376fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3377fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3378fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3379fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3380fcf5ef2aSThomas Huth } 3381fcf5ef2aSThomas Huth } 3382fcf5ef2aSThomas Huth 3383fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3384fcf5ef2aSThomas Huth { 3385fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3386fcf5ef2aSThomas Huth } 3387fcf5ef2aSThomas Huth 3388fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3389fcf5ef2aSThomas Huth { 3390fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3391fcf5ef2aSThomas Huth } 3392fcf5ef2aSThomas Huth 3393fcf5ef2aSThomas Huth /* srd & srd. */ 3394fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3395fcf5ef2aSThomas Huth { 3396fcf5ef2aSThomas Huth TCGv t0, t1; 3397fcf5ef2aSThomas Huth 3398fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3399fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3400fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3401fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3402fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3403fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3404fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3405fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3406fcf5ef2aSThomas Huth tcg_temp_free(t1); 3407fcf5ef2aSThomas Huth tcg_temp_free(t0); 3408efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3409fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3410fcf5ef2aSThomas Huth } 3411efe843d8SDavid Gibson } 3412fcf5ef2aSThomas Huth #endif 3413fcf5ef2aSThomas Huth 3414fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3415fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3416fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3417fcf5ef2aSThomas Huth target_long maskl) 3418fcf5ef2aSThomas Huth { 3419fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3420fcf5ef2aSThomas Huth 3421fcf5ef2aSThomas Huth simm &= ~maskl; 3422fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3423fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3424fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3425fcf5ef2aSThomas Huth } 3426fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3427fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3428fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3429fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3430fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3431fcf5ef2aSThomas Huth } 3432fcf5ef2aSThomas Huth } else { 3433fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3434fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3435fcf5ef2aSThomas Huth } else { 3436fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3437fcf5ef2aSThomas Huth } 3438fcf5ef2aSThomas Huth } 3439fcf5ef2aSThomas Huth } 3440fcf5ef2aSThomas Huth 3441fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3442fcf5ef2aSThomas Huth { 3443fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3444fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3445fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3446fcf5ef2aSThomas Huth } else { 3447fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3448fcf5ef2aSThomas Huth } 3449fcf5ef2aSThomas Huth } else { 3450fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3451fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3452fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3453fcf5ef2aSThomas Huth } 3454fcf5ef2aSThomas Huth } 3455fcf5ef2aSThomas Huth } 3456fcf5ef2aSThomas Huth 3457fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3458fcf5ef2aSThomas Huth { 3459fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3460fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3461fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3462fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3463fcf5ef2aSThomas Huth } else { 3464fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3465fcf5ef2aSThomas Huth } 3466fcf5ef2aSThomas Huth } 3467fcf5ef2aSThomas Huth 3468fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3469fcf5ef2aSThomas Huth target_long val) 3470fcf5ef2aSThomas Huth { 3471fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3472fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3473fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3474fcf5ef2aSThomas Huth } 3475fcf5ef2aSThomas Huth } 3476fcf5ef2aSThomas Huth 3477fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3478fcf5ef2aSThomas Huth { 3479fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3480fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3481fcf5ef2aSThomas Huth } 3482fcf5ef2aSThomas Huth 3483fcf5ef2aSThomas Huth /*** Integer load ***/ 3484fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3485fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3486fcf5ef2aSThomas Huth 3487fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3488fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3489fcf5ef2aSThomas Huth TCGv val, \ 3490fcf5ef2aSThomas Huth TCGv addr) \ 3491fcf5ef2aSThomas Huth { \ 3492fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3493fcf5ef2aSThomas Huth } 3494fcf5ef2aSThomas Huth 3495fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3496fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3497fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3498fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3499fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3500fcf5ef2aSThomas Huth 3501fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3502fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3503fcf5ef2aSThomas Huth 3504fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3505fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3506fcf5ef2aSThomas Huth TCGv_i64 val, \ 3507fcf5ef2aSThomas Huth TCGv addr) \ 3508fcf5ef2aSThomas Huth { \ 3509fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3510fcf5ef2aSThomas Huth } 3511fcf5ef2aSThomas Huth 3512fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3513fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3514fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3515fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3516fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3517fcf5ef2aSThomas Huth 3518fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3519fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3520fcf5ef2aSThomas Huth #endif 3521fcf5ef2aSThomas Huth 3522fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3523fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3524fcf5ef2aSThomas Huth TCGv val, \ 3525fcf5ef2aSThomas Huth TCGv addr) \ 3526fcf5ef2aSThomas Huth { \ 3527fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3528fcf5ef2aSThomas Huth } 3529fcf5ef2aSThomas Huth 3530fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3531fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3532fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3533fcf5ef2aSThomas Huth 3534fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3535fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3536fcf5ef2aSThomas Huth 3537fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3538fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3539fcf5ef2aSThomas Huth TCGv_i64 val, \ 3540fcf5ef2aSThomas Huth TCGv addr) \ 3541fcf5ef2aSThomas Huth { \ 3542fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3543fcf5ef2aSThomas Huth } 3544fcf5ef2aSThomas Huth 3545fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3546fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3547fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3548fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3549fcf5ef2aSThomas Huth 3550fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3551fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3552fcf5ef2aSThomas Huth #endif 3553fcf5ef2aSThomas Huth 3554fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 3555fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3556fcf5ef2aSThomas Huth { \ 3557fcf5ef2aSThomas Huth TCGv EA; \ 3558fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3559fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3560fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3561fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3562fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3563fcf5ef2aSThomas Huth } 3564fcf5ef2aSThomas Huth 3565fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 3566fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 3567fcf5ef2aSThomas Huth { \ 3568fcf5ef2aSThomas Huth TCGv EA; \ 3569fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3570fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3571fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3572fcf5ef2aSThomas Huth return; \ 3573fcf5ef2aSThomas Huth } \ 3574fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3575fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3576fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3577fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3578fcf5ef2aSThomas Huth else \ 3579fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3580fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3581fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3582fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3583fcf5ef2aSThomas Huth } 3584fcf5ef2aSThomas Huth 3585fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 3586fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3587fcf5ef2aSThomas Huth { \ 3588fcf5ef2aSThomas Huth TCGv EA; \ 3589fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3590fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3591fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3592fcf5ef2aSThomas Huth return; \ 3593fcf5ef2aSThomas Huth } \ 3594fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3595fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3596fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3597fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3598fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3599fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3600fcf5ef2aSThomas Huth } 3601fcf5ef2aSThomas Huth 3602fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3603fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3604fcf5ef2aSThomas Huth { \ 3605fcf5ef2aSThomas Huth TCGv EA; \ 3606fcf5ef2aSThomas Huth chk; \ 3607fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3608fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3609fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3610fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3611fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3612fcf5ef2aSThomas Huth } 3613fcf5ef2aSThomas Huth 3614fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3615fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3616fcf5ef2aSThomas Huth 3617fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3618fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3619fcf5ef2aSThomas Huth 3620fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 3621fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 3622fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 3623fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 3624fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 3625fcf5ef2aSThomas Huth 3626fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 3627fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 3628fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 3629fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 3630fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 3631fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 3632fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 3633fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 363450728199SRoman Kapl 363550728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 363650728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 363750728199SRoman Kapl { \ 363850728199SRoman Kapl TCGv EA; \ 363950728199SRoman Kapl CHK_SV; \ 364050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 364150728199SRoman Kapl EA = tcg_temp_new(); \ 364250728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 364350728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 364450728199SRoman Kapl tcg_temp_free(EA); \ 364550728199SRoman Kapl } 364650728199SRoman Kapl 364750728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 364850728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 364950728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 365050728199SRoman Kapl #if defined(TARGET_PPC64) 365150728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 365250728199SRoman Kapl #endif 365350728199SRoman Kapl 3654fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3655fcf5ef2aSThomas Huth /* lwaux */ 3656fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 3657fcf5ef2aSThomas Huth /* lwax */ 3658fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 3659fcf5ef2aSThomas Huth /* ldux */ 3660fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 3661fcf5ef2aSThomas Huth /* ldx */ 3662fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 3663fcf5ef2aSThomas Huth 3664fcf5ef2aSThomas Huth /* CI load/store variants */ 3665fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3666fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3667fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3668fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3669fcf5ef2aSThomas Huth 3670fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 3671fcf5ef2aSThomas Huth { 3672fcf5ef2aSThomas Huth TCGv EA; 3673fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3674fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 3675fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 3676fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3677fcf5ef2aSThomas Huth return; 3678fcf5ef2aSThomas Huth } 3679fcf5ef2aSThomas Huth } 3680fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3681fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3682fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3683fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 3684fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 3685fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3686fcf5ef2aSThomas Huth } else { 3687fcf5ef2aSThomas Huth /* ld - ldu */ 3688fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3689fcf5ef2aSThomas Huth } 3690efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3691fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3692efe843d8SDavid Gibson } 3693fcf5ef2aSThomas Huth tcg_temp_free(EA); 3694fcf5ef2aSThomas Huth } 3695fcf5ef2aSThomas Huth 3696fcf5ef2aSThomas Huth /* lq */ 3697fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3698fcf5ef2aSThomas Huth { 3699fcf5ef2aSThomas Huth int ra, rd; 370094bf2658SRichard Henderson TCGv EA, hi, lo; 3701fcf5ef2aSThomas Huth 3702fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3703fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3704fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3705fcf5ef2aSThomas Huth 3706fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3707fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3708fcf5ef2aSThomas Huth return; 3709fcf5ef2aSThomas Huth } 3710fcf5ef2aSThomas Huth 3711fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3712fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3713fcf5ef2aSThomas Huth return; 3714fcf5ef2aSThomas Huth } 3715fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3716fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3717fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3718fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3719fcf5ef2aSThomas Huth return; 3720fcf5ef2aSThomas Huth } 3721fcf5ef2aSThomas Huth 3722fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3723fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3724fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3725fcf5ef2aSThomas Huth 372694bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 372794bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 372894bf2658SRichard Henderson hi = cpu_gpr[rd]; 372994bf2658SRichard Henderson 373094bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3731f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 373294bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 373394bf2658SRichard Henderson if (ctx->le_mode) { 373494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 373594bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3736fcf5ef2aSThomas Huth } else { 373794bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 373894bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 373994bf2658SRichard Henderson } 374094bf2658SRichard Henderson tcg_temp_free_i32(oi); 374194bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3742f34ec0f6SRichard Henderson } else { 374394bf2658SRichard Henderson /* Restart with exclusive lock. */ 374494bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 374594bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3746f34ec0f6SRichard Henderson } 374794bf2658SRichard Henderson } else if (ctx->le_mode) { 374894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3749fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 375094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 375194bf2658SRichard Henderson } else { 375294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 375394bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 375494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3755fcf5ef2aSThomas Huth } 3756fcf5ef2aSThomas Huth tcg_temp_free(EA); 3757fcf5ef2aSThomas Huth } 3758fcf5ef2aSThomas Huth #endif 3759fcf5ef2aSThomas Huth 3760fcf5ef2aSThomas Huth /*** Integer store ***/ 3761fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3762fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3763fcf5ef2aSThomas Huth { \ 3764fcf5ef2aSThomas Huth TCGv EA; \ 3765fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3766fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3767fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3768fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3769fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3770fcf5ef2aSThomas Huth } 3771fcf5ef2aSThomas Huth 3772fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3773fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3774fcf5ef2aSThomas Huth { \ 3775fcf5ef2aSThomas Huth TCGv EA; \ 3776fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3777fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3778fcf5ef2aSThomas Huth return; \ 3779fcf5ef2aSThomas Huth } \ 3780fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3781fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3782fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3783fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3784fcf5ef2aSThomas Huth else \ 3785fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3786fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3787fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3788fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3789fcf5ef2aSThomas Huth } 3790fcf5ef2aSThomas Huth 3791fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3792fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3793fcf5ef2aSThomas Huth { \ 3794fcf5ef2aSThomas Huth TCGv EA; \ 3795fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3796fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3797fcf5ef2aSThomas Huth return; \ 3798fcf5ef2aSThomas Huth } \ 3799fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3800fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3801fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3802fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3803fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3804fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3805fcf5ef2aSThomas Huth } 3806fcf5ef2aSThomas Huth 3807fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3808fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3809fcf5ef2aSThomas Huth { \ 3810fcf5ef2aSThomas Huth TCGv EA; \ 3811fcf5ef2aSThomas Huth chk; \ 3812fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3813fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3814fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3815fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3816fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3817fcf5ef2aSThomas Huth } 3818fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3819fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3820fcf5ef2aSThomas Huth 3821fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3822fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3823fcf5ef2aSThomas Huth 3824fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3825fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3826fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3827fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3828fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3829fcf5ef2aSThomas Huth 3830fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3831fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3832fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3833fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3834fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3835fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 383650728199SRoman Kapl 383750728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 383850728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 383950728199SRoman Kapl { \ 384050728199SRoman Kapl TCGv EA; \ 384150728199SRoman Kapl CHK_SV; \ 384250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 384350728199SRoman Kapl EA = tcg_temp_new(); \ 384450728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 384550728199SRoman Kapl tcg_gen_qemu_st_tl( \ 384650728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 384750728199SRoman Kapl tcg_temp_free(EA); \ 384850728199SRoman Kapl } 384950728199SRoman Kapl 385050728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 385150728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 385250728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 385350728199SRoman Kapl #if defined(TARGET_PPC64) 385450728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 385550728199SRoman Kapl #endif 385650728199SRoman Kapl 3857fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3858fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3859fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3860fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3861fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3862fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3863fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3864fcf5ef2aSThomas Huth 3865fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3866fcf5ef2aSThomas Huth { 3867fcf5ef2aSThomas Huth int rs; 3868fcf5ef2aSThomas Huth TCGv EA; 3869fcf5ef2aSThomas Huth 3870fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3871fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3872fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3873fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3874f89ced5fSRichard Henderson TCGv hi, lo; 3875fcf5ef2aSThomas Huth 3876fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3877fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3878fcf5ef2aSThomas Huth } 3879fcf5ef2aSThomas Huth 3880fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3881fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3882fcf5ef2aSThomas Huth return; 3883fcf5ef2aSThomas Huth } 3884fcf5ef2aSThomas Huth 3885fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3886fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3887fcf5ef2aSThomas Huth return; 3888fcf5ef2aSThomas Huth } 3889fcf5ef2aSThomas Huth 3890fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3891fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3892fcf5ef2aSThomas Huth return; 3893fcf5ef2aSThomas Huth } 3894fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3895fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3896fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3897fcf5ef2aSThomas Huth 3898f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3899f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3900f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3901f89ced5fSRichard Henderson 3902f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3903f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3904f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3905f89ced5fSRichard Henderson if (ctx->le_mode) { 3906f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3907f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3908fcf5ef2aSThomas Huth } else { 3909f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3910f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3911f89ced5fSRichard Henderson } 3912f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3913f34ec0f6SRichard Henderson } else { 3914f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3915f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3916f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3917f34ec0f6SRichard Henderson } 3918f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3919f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3920fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3921f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3922f89ced5fSRichard Henderson } else { 3923f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3924f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3925f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3926fcf5ef2aSThomas Huth } 3927fcf5ef2aSThomas Huth tcg_temp_free(EA); 3928fcf5ef2aSThomas Huth } else { 3929fcf5ef2aSThomas Huth /* std / stdu */ 3930fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3931fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3932fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3933fcf5ef2aSThomas Huth return; 3934fcf5ef2aSThomas Huth } 3935fcf5ef2aSThomas Huth } 3936fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3937fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3938fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3939fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3940efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3941fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3942efe843d8SDavid Gibson } 3943fcf5ef2aSThomas Huth tcg_temp_free(EA); 3944fcf5ef2aSThomas Huth } 3945fcf5ef2aSThomas Huth } 3946fcf5ef2aSThomas Huth #endif 3947fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3948fcf5ef2aSThomas Huth 3949fcf5ef2aSThomas Huth /* lhbrx */ 3950fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3951fcf5ef2aSThomas Huth 3952fcf5ef2aSThomas Huth /* lwbrx */ 3953fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3954fcf5ef2aSThomas Huth 3955fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3956fcf5ef2aSThomas Huth /* ldbrx */ 3957fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3958fcf5ef2aSThomas Huth /* stdbrx */ 3959fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3960fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3961fcf5ef2aSThomas Huth 3962fcf5ef2aSThomas Huth /* sthbrx */ 3963fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3964fcf5ef2aSThomas Huth /* stwbrx */ 3965fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3966fcf5ef2aSThomas Huth 3967fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3968fcf5ef2aSThomas Huth 3969fcf5ef2aSThomas Huth /* lmw */ 3970fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3971fcf5ef2aSThomas Huth { 3972fcf5ef2aSThomas Huth TCGv t0; 3973fcf5ef2aSThomas Huth TCGv_i32 t1; 3974fcf5ef2aSThomas Huth 3975fcf5ef2aSThomas Huth if (ctx->le_mode) { 3976fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3977fcf5ef2aSThomas Huth return; 3978fcf5ef2aSThomas Huth } 3979fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3980fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3981fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3982fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3983fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3984fcf5ef2aSThomas Huth tcg_temp_free(t0); 3985fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3986fcf5ef2aSThomas Huth } 3987fcf5ef2aSThomas Huth 3988fcf5ef2aSThomas Huth /* stmw */ 3989fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3990fcf5ef2aSThomas Huth { 3991fcf5ef2aSThomas Huth TCGv t0; 3992fcf5ef2aSThomas Huth TCGv_i32 t1; 3993fcf5ef2aSThomas Huth 3994fcf5ef2aSThomas Huth if (ctx->le_mode) { 3995fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3996fcf5ef2aSThomas Huth return; 3997fcf5ef2aSThomas Huth } 3998fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3999fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4000fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 4001fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 4002fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 4003fcf5ef2aSThomas Huth tcg_temp_free(t0); 4004fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4005fcf5ef2aSThomas Huth } 4006fcf5ef2aSThomas Huth 4007fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 4008fcf5ef2aSThomas Huth 4009fcf5ef2aSThomas Huth /* lswi */ 4010efe843d8SDavid Gibson /* 4011efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 4012efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 4013efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 4014efe843d8SDavid Gibson * spec... 4015fcf5ef2aSThomas Huth */ 4016fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 4017fcf5ef2aSThomas Huth { 4018fcf5ef2aSThomas Huth TCGv t0; 4019fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4020fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4021fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 4022fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 4023fcf5ef2aSThomas Huth int nr; 4024fcf5ef2aSThomas Huth 4025fcf5ef2aSThomas Huth if (ctx->le_mode) { 4026fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4027fcf5ef2aSThomas Huth return; 4028fcf5ef2aSThomas Huth } 4029efe843d8SDavid Gibson if (nb == 0) { 4030fcf5ef2aSThomas Huth nb = 32; 4031efe843d8SDavid Gibson } 4032f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 4033fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 4034fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 4035fcf5ef2aSThomas Huth return; 4036fcf5ef2aSThomas Huth } 4037fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4038fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4039fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4040fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4041fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 4042fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 4043fcf5ef2aSThomas Huth tcg_temp_free(t0); 4044fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4045fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4046fcf5ef2aSThomas Huth } 4047fcf5ef2aSThomas Huth 4048fcf5ef2aSThomas Huth /* lswx */ 4049fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 4050fcf5ef2aSThomas Huth { 4051fcf5ef2aSThomas Huth TCGv t0; 4052fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 4053fcf5ef2aSThomas Huth 4054fcf5ef2aSThomas Huth if (ctx->le_mode) { 4055fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4056fcf5ef2aSThomas Huth return; 4057fcf5ef2aSThomas Huth } 4058fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4059fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4060fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4061fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 4062fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 4063fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 4064fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 4065fcf5ef2aSThomas Huth tcg_temp_free(t0); 4066fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4067fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4068fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4069fcf5ef2aSThomas Huth } 4070fcf5ef2aSThomas Huth 4071fcf5ef2aSThomas Huth /* stswi */ 4072fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 4073fcf5ef2aSThomas Huth { 4074fcf5ef2aSThomas Huth TCGv t0; 4075fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4076fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4077fcf5ef2aSThomas Huth 4078fcf5ef2aSThomas Huth if (ctx->le_mode) { 4079fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4080fcf5ef2aSThomas Huth return; 4081fcf5ef2aSThomas Huth } 4082fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4083fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4084fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4085efe843d8SDavid Gibson if (nb == 0) { 4086fcf5ef2aSThomas Huth nb = 32; 4087efe843d8SDavid Gibson } 4088fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4089fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4090fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4091fcf5ef2aSThomas Huth tcg_temp_free(t0); 4092fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4093fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4094fcf5ef2aSThomas Huth } 4095fcf5ef2aSThomas Huth 4096fcf5ef2aSThomas Huth /* stswx */ 4097fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 4098fcf5ef2aSThomas Huth { 4099fcf5ef2aSThomas Huth TCGv t0; 4100fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4101fcf5ef2aSThomas Huth 4102fcf5ef2aSThomas Huth if (ctx->le_mode) { 4103fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4104fcf5ef2aSThomas Huth return; 4105fcf5ef2aSThomas Huth } 4106fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4107fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4108fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4109fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4110fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 4111fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 4112fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4113fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4114fcf5ef2aSThomas Huth tcg_temp_free(t0); 4115fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4116fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4117fcf5ef2aSThomas Huth } 4118fcf5ef2aSThomas Huth 4119fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 4120fcf5ef2aSThomas Huth /* eieio */ 4121fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 4122fcf5ef2aSThomas Huth { 4123c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 4124c8fd8373SCédric Le Goater 4125c8fd8373SCédric Le Goater /* 4126c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 4127c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 4128c8fd8373SCédric Le Goater */ 4129c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 4130c8fd8373SCédric Le Goater /* 4131c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 4132c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 4133c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 4134c8fd8373SCédric Le Goater * complain to the user. 4135c8fd8373SCédric Le Goater */ 4136c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 4137c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 41382c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 4139c8fd8373SCédric Le Goater } else { 4140c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 4141c8fd8373SCédric Le Goater } 4142c8fd8373SCédric Le Goater } 4143c8fd8373SCédric Le Goater 4144c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 4145fcf5ef2aSThomas Huth } 4146fcf5ef2aSThomas Huth 4147fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4148fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 4149fcf5ef2aSThomas Huth { 4150fcf5ef2aSThomas Huth TCGv_i32 t; 4151fcf5ef2aSThomas Huth TCGLabel *l; 4152fcf5ef2aSThomas Huth 4153fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 4154fcf5ef2aSThomas Huth return; 4155fcf5ef2aSThomas Huth } 4156fcf5ef2aSThomas Huth l = gen_new_label(); 4157fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 4158fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4159fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 4160fcf5ef2aSThomas Huth if (global) { 4161fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 4162fcf5ef2aSThomas Huth } else { 4163fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 4164fcf5ef2aSThomas Huth } 4165fcf5ef2aSThomas Huth gen_set_label(l); 4166fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4167fcf5ef2aSThomas Huth } 4168fcf5ef2aSThomas Huth #else 4169fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 4170fcf5ef2aSThomas Huth #endif 4171fcf5ef2aSThomas Huth 4172fcf5ef2aSThomas Huth /* isync */ 4173fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 4174fcf5ef2aSThomas Huth { 4175fcf5ef2aSThomas Huth /* 4176fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 4177fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 4178fcf5ef2aSThomas Huth */ 4179fcf5ef2aSThomas Huth if (!ctx->pr) { 4180fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 4181fcf5ef2aSThomas Huth } 41824771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4183fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4184fcf5ef2aSThomas Huth } 4185fcf5ef2aSThomas Huth 4186fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 4187fcf5ef2aSThomas Huth 418814776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 41892a4e6c1bSRichard Henderson { 41902a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 41912a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 41922a4e6c1bSRichard Henderson 41932a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 41942a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 41952a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 41962a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 41972a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 41982a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 41992a4e6c1bSRichard Henderson tcg_temp_free(t0); 42002a4e6c1bSRichard Henderson } 42012a4e6c1bSRichard Henderson 4202fcf5ef2aSThomas Huth #define LARX(name, memop) \ 4203fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4204fcf5ef2aSThomas Huth { \ 42052a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 4206fcf5ef2aSThomas Huth } 4207fcf5ef2aSThomas Huth 4208fcf5ef2aSThomas Huth /* lwarx */ 4209fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 4210fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 4211fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 4212fcf5ef2aSThomas Huth 421314776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 421420923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 421520923c1dSRichard Henderson { 421620923c1dSRichard Henderson TCGv t = tcg_temp_new(); 421720923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 421820923c1dSRichard Henderson TCGv u = tcg_temp_new(); 421920923c1dSRichard Henderson 422020923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 422120923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 422220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 422320923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 422420923c1dSRichard Henderson 422520923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 422620923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 422720923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 422820923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 422920923c1dSRichard Henderson 423020923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 423120923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 423220923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 423320923c1dSRichard Henderson 423420923c1dSRichard Henderson tcg_temp_free(t); 423520923c1dSRichard Henderson tcg_temp_free(t2); 423620923c1dSRichard Henderson tcg_temp_free(u); 423720923c1dSRichard Henderson } 423820923c1dSRichard Henderson 423914776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 424020ba8504SRichard Henderson { 424120ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 424220ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 424320923c1dSRichard Henderson int rt = rD(ctx->opcode); 424420923c1dSRichard Henderson bool need_serial; 424520ba8504SRichard Henderson TCGv src, dst; 424620ba8504SRichard Henderson 424720ba8504SRichard Henderson gen_addr_register(ctx, EA); 424820923c1dSRichard Henderson dst = cpu_gpr[rt]; 424920923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 425020ba8504SRichard Henderson 425120923c1dSRichard Henderson need_serial = false; 425220ba8504SRichard Henderson memop |= MO_ALIGN; 425320ba8504SRichard Henderson switch (gpr_FC) { 425420ba8504SRichard Henderson case 0: /* Fetch and add */ 425520ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 425620ba8504SRichard Henderson break; 425720ba8504SRichard Henderson case 1: /* Fetch and xor */ 425820ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 425920ba8504SRichard Henderson break; 426020ba8504SRichard Henderson case 2: /* Fetch and or */ 426120ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 426220ba8504SRichard Henderson break; 426320ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 426420ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 426520ba8504SRichard Henderson break; 4266b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 4267b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 4268b8ce0f86SRichard Henderson break; 4269b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 4270b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 4271b8ce0f86SRichard Henderson break; 4272b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 4273b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 4274b8ce0f86SRichard Henderson break; 4275b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 4276b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 4277b8ce0f86SRichard Henderson break; 427820ba8504SRichard Henderson case 8: /* Swap */ 427920ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 428020ba8504SRichard Henderson break; 428120923c1dSRichard Henderson 428220923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 428320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 428420923c1dSRichard Henderson need_serial = true; 428520923c1dSRichard Henderson } else { 428620923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 428720923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 428820923c1dSRichard Henderson 428920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 429020923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 429120923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 429220923c1dSRichard Henderson } else { 429320923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 429420923c1dSRichard Henderson } 429520923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 429620923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 429720923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 429820923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 429920923c1dSRichard Henderson 430020923c1dSRichard Henderson tcg_temp_free(t0); 430120923c1dSRichard Henderson tcg_temp_free(t1); 430220923c1dSRichard Henderson } 430320ba8504SRichard Henderson break; 430420923c1dSRichard Henderson 430520923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 430620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 430720923c1dSRichard Henderson need_serial = true; 430820923c1dSRichard Henderson } else { 430920923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 431020923c1dSRichard Henderson } 431120923c1dSRichard Henderson break; 431220923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 431320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 431420923c1dSRichard Henderson need_serial = true; 431520923c1dSRichard Henderson } else { 431620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 431720923c1dSRichard Henderson } 431820923c1dSRichard Henderson break; 431920923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 432020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 432120923c1dSRichard Henderson need_serial = true; 432220923c1dSRichard Henderson } else { 432320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 432420923c1dSRichard Henderson } 432520923c1dSRichard Henderson break; 432620923c1dSRichard Henderson 432720ba8504SRichard Henderson default: 432820ba8504SRichard Henderson /* invoke data storage error handler */ 432920ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 433020ba8504SRichard Henderson } 433120ba8504SRichard Henderson tcg_temp_free(EA); 433220923c1dSRichard Henderson 433320923c1dSRichard Henderson if (need_serial) { 433420923c1dSRichard Henderson /* Restart with exclusive lock. */ 433520923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 433620923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 433720923c1dSRichard Henderson } 4338a68a6146SBalamuruhan S } 4339a68a6146SBalamuruhan S 434020ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 434120ba8504SRichard Henderson { 434220ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 434320ba8504SRichard Henderson } 434420ba8504SRichard Henderson 434520ba8504SRichard Henderson #ifdef TARGET_PPC64 434620ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 434720ba8504SRichard Henderson { 434820ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 434920ba8504SRichard Henderson } 4350a68a6146SBalamuruhan S #endif 4351a68a6146SBalamuruhan S 435214776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 43539deb041cSRichard Henderson { 43549deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 43559deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 43569deb041cSRichard Henderson TCGv src, discard; 43579deb041cSRichard Henderson 43589deb041cSRichard Henderson gen_addr_register(ctx, EA); 43599deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 43609deb041cSRichard Henderson discard = tcg_temp_new(); 43619deb041cSRichard Henderson 43629deb041cSRichard Henderson memop |= MO_ALIGN; 43639deb041cSRichard Henderson switch (gpr_FC) { 43649deb041cSRichard Henderson case 0: /* add and Store */ 43659deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43669deb041cSRichard Henderson break; 43679deb041cSRichard Henderson case 1: /* xor and Store */ 43689deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43699deb041cSRichard Henderson break; 43709deb041cSRichard Henderson case 2: /* Or and Store */ 43719deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43729deb041cSRichard Henderson break; 43739deb041cSRichard Henderson case 3: /* 'and' and Store */ 43749deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43759deb041cSRichard Henderson break; 43769deb041cSRichard Henderson case 4: /* Store max unsigned */ 4377b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4378b8ce0f86SRichard Henderson break; 43799deb041cSRichard Henderson case 5: /* Store max signed */ 4380b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4381b8ce0f86SRichard Henderson break; 43829deb041cSRichard Henderson case 6: /* Store min unsigned */ 4383b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4384b8ce0f86SRichard Henderson break; 43859deb041cSRichard Henderson case 7: /* Store min signed */ 4386b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4387b8ce0f86SRichard Henderson break; 43889deb041cSRichard Henderson case 24: /* Store twin */ 43897fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 43907fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 43917fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 43927fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 43937fbc2b20SRichard Henderson } else { 43947fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 43957fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 43967fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 43977fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 43987fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 43997fbc2b20SRichard Henderson 44007fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 44017fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 44027fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 44037fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 44047fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 44057fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 44067fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 44077fbc2b20SRichard Henderson 44087fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 44097fbc2b20SRichard Henderson tcg_temp_free(s2); 44107fbc2b20SRichard Henderson tcg_temp_free(s); 44117fbc2b20SRichard Henderson tcg_temp_free(t2); 44127fbc2b20SRichard Henderson tcg_temp_free(t); 44137fbc2b20SRichard Henderson } 44149deb041cSRichard Henderson break; 44159deb041cSRichard Henderson default: 44169deb041cSRichard Henderson /* invoke data storage error handler */ 44179deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 44189deb041cSRichard Henderson } 44199deb041cSRichard Henderson tcg_temp_free(discard); 44209deb041cSRichard Henderson tcg_temp_free(EA); 4421a3401188SBalamuruhan S } 4422a3401188SBalamuruhan S 44239deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 44249deb041cSRichard Henderson { 44259deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 44269deb041cSRichard Henderson } 44279deb041cSRichard Henderson 44289deb041cSRichard Henderson #ifdef TARGET_PPC64 44299deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 44309deb041cSRichard Henderson { 44319deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 44329deb041cSRichard Henderson } 4433a3401188SBalamuruhan S #endif 4434a3401188SBalamuruhan S 443514776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4436fcf5ef2aSThomas Huth { 4437253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4438253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4439d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4440d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4441fcf5ef2aSThomas Huth 4442d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4443d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4444d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4445d8b86898SRichard Henderson tcg_temp_free(t0); 4446253ce7b2SNikunj A Dadhania 4447253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4448253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4449253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4450253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4451253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4452253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4453253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4454253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4455253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4456253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4457253ce7b2SNikunj A Dadhania 4458fcf5ef2aSThomas Huth gen_set_label(l1); 44594771df23SNikunj A Dadhania 4460efe843d8SDavid Gibson /* 4461efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4462efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4463efe843d8SDavid Gibson */ 44644771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4465253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4466253ce7b2SNikunj A Dadhania 4467253ce7b2SNikunj A Dadhania gen_set_label(l2); 4468fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4469fcf5ef2aSThomas Huth } 4470fcf5ef2aSThomas Huth 4471fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4472fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4473fcf5ef2aSThomas Huth { \ 4474d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4475fcf5ef2aSThomas Huth } 4476fcf5ef2aSThomas Huth 4477fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4478fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4479fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4480fcf5ef2aSThomas Huth 4481fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4482fcf5ef2aSThomas Huth /* ldarx */ 4483fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4484fcf5ef2aSThomas Huth /* stdcx. */ 4485fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4486fcf5ef2aSThomas Huth 4487fcf5ef2aSThomas Huth /* lqarx */ 4488fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4489fcf5ef2aSThomas Huth { 4490fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 449194bf2658SRichard Henderson TCGv EA, hi, lo; 4492fcf5ef2aSThomas Huth 4493fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4494fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4495fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4496fcf5ef2aSThomas Huth return; 4497fcf5ef2aSThomas Huth } 4498fcf5ef2aSThomas Huth 4499fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 450094bf2658SRichard Henderson EA = tcg_temp_new(); 4501fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 450294bf2658SRichard Henderson 450394bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 450494bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 450594bf2658SRichard Henderson hi = cpu_gpr[rd]; 450694bf2658SRichard Henderson 450794bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4508f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 450994bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 451094bf2658SRichard Henderson if (ctx->le_mode) { 451194bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 451294bf2658SRichard Henderson ctx->mem_idx)); 451394bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4514fcf5ef2aSThomas Huth } else { 451594bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 451694bf2658SRichard Henderson ctx->mem_idx)); 451794bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4518fcf5ef2aSThomas Huth } 451994bf2658SRichard Henderson tcg_temp_free_i32(oi); 452094bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4521f34ec0f6SRichard Henderson } else { 452294bf2658SRichard Henderson /* Restart with exclusive lock. */ 452394bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 452494bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 452594bf2658SRichard Henderson tcg_temp_free(EA); 452694bf2658SRichard Henderson return; 4527f34ec0f6SRichard Henderson } 452894bf2658SRichard Henderson } else if (ctx->le_mode) { 452994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4530fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4531fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 453294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 453394bf2658SRichard Henderson } else { 453494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 453594bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 453694bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 453794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 453894bf2658SRichard Henderson } 4539fcf5ef2aSThomas Huth tcg_temp_free(EA); 454094bf2658SRichard Henderson 454194bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 454294bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4543fcf5ef2aSThomas Huth } 4544fcf5ef2aSThomas Huth 4545fcf5ef2aSThomas Huth /* stqcx. */ 4546fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4547fcf5ef2aSThomas Huth { 45484a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 45494a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4550fcf5ef2aSThomas Huth 45514a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4552fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4553fcf5ef2aSThomas Huth return; 4554fcf5ef2aSThomas Huth } 45554a9b3c5dSRichard Henderson 4556fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 45574a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4558fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4559fcf5ef2aSThomas Huth 45604a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 45614a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 45624a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4563fcf5ef2aSThomas Huth 45644a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4565f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 45664a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 45674a9b3c5dSRichard Henderson if (ctx->le_mode) { 4568f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4569f34ec0f6SRichard Henderson EA, lo, hi, oi); 4570fcf5ef2aSThomas Huth } else { 4571f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4572f34ec0f6SRichard Henderson EA, lo, hi, oi); 4573fcf5ef2aSThomas Huth } 4574f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4575f34ec0f6SRichard Henderson } else { 45764a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 45774a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 45784a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4579f34ec0f6SRichard Henderson } 4580fcf5ef2aSThomas Huth tcg_temp_free(EA); 45814a9b3c5dSRichard Henderson } else { 45824a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 45834a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 45844a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 45854a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4586fcf5ef2aSThomas Huth 45874a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 45884a9b3c5dSRichard Henderson tcg_temp_free(EA); 45894a9b3c5dSRichard Henderson 45904a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 45914a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 45924a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 45934a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 45944a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 45954a9b3c5dSRichard Henderson 45964a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 45974a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 45984a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 45994a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 46004a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 46014a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 46024a9b3c5dSRichard Henderson 46034a9b3c5dSRichard Henderson /* Success */ 46044a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 46054a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 46064a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 46074a9b3c5dSRichard Henderson 46084a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46094a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 46104a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 46114a9b3c5dSRichard Henderson 46124a9b3c5dSRichard Henderson gen_set_label(lab_fail); 46134a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46144a9b3c5dSRichard Henderson 46154a9b3c5dSRichard Henderson gen_set_label(lab_over); 46164a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 46174a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 46184a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 46194a9b3c5dSRichard Henderson } 46204a9b3c5dSRichard Henderson } 4621fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4622fcf5ef2aSThomas Huth 4623fcf5ef2aSThomas Huth /* sync */ 4624fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4625fcf5ef2aSThomas Huth { 4626fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4627fcf5ef2aSThomas Huth 4628fcf5ef2aSThomas Huth /* 4629fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4630fcf5ef2aSThomas Huth * 4631fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4632fcf5ef2aSThomas Huth * 4633fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4634fcf5ef2aSThomas Huth * check MSR_PR as well. 4635fcf5ef2aSThomas Huth */ 4636fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4637fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4638fcf5ef2aSThomas Huth } 46394771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4640fcf5ef2aSThomas Huth } 4641fcf5ef2aSThomas Huth 4642fcf5ef2aSThomas Huth /* wait */ 4643fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4644fcf5ef2aSThomas Huth { 4645fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4646fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4647fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4648fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4649fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4650b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4651fcf5ef2aSThomas Huth } 4652fcf5ef2aSThomas Huth 4653fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4654fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4655fcf5ef2aSThomas Huth { 4656fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4657fcf5ef2aSThomas Huth GEN_PRIV; 4658fcf5ef2aSThomas Huth #else 4659fcf5ef2aSThomas Huth TCGv_i32 t; 4660fcf5ef2aSThomas Huth 4661fcf5ef2aSThomas Huth CHK_HV; 4662fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4663fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4664fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4665154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4666154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4667fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4668fcf5ef2aSThomas Huth } 4669fcf5ef2aSThomas Huth 4670fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4671fcf5ef2aSThomas Huth { 4672fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4673fcf5ef2aSThomas Huth GEN_PRIV; 4674fcf5ef2aSThomas Huth #else 4675fcf5ef2aSThomas Huth TCGv_i32 t; 4676fcf5ef2aSThomas Huth 4677fcf5ef2aSThomas Huth CHK_HV; 4678fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4679fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4680fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4681154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4682154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4683fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4684fcf5ef2aSThomas Huth } 4685fcf5ef2aSThomas Huth 4686cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4687cdee0e72SNikunj A Dadhania { 468821c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 468921c0d66aSBenjamin Herrenschmidt GEN_PRIV; 469021c0d66aSBenjamin Herrenschmidt #else 469121c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 469221c0d66aSBenjamin Herrenschmidt 469321c0d66aSBenjamin Herrenschmidt CHK_HV; 469421c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 469521c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 469621c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 469721c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 469821c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 469921c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4700cdee0e72SNikunj A Dadhania } 4701cdee0e72SNikunj A Dadhania 4702fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4703fcf5ef2aSThomas Huth { 4704fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4705fcf5ef2aSThomas Huth GEN_PRIV; 4706fcf5ef2aSThomas Huth #else 4707fcf5ef2aSThomas Huth TCGv_i32 t; 4708fcf5ef2aSThomas Huth 4709fcf5ef2aSThomas Huth CHK_HV; 4710fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4711fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4712fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4713154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4714154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4715fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4716fcf5ef2aSThomas Huth } 4717fcf5ef2aSThomas Huth 4718fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4719fcf5ef2aSThomas Huth { 4720fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4721fcf5ef2aSThomas Huth GEN_PRIV; 4722fcf5ef2aSThomas Huth #else 4723fcf5ef2aSThomas Huth TCGv_i32 t; 4724fcf5ef2aSThomas Huth 4725fcf5ef2aSThomas Huth CHK_HV; 4726fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4727fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4728fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4729154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4730154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4731fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4732fcf5ef2aSThomas Huth } 4733fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4734fcf5ef2aSThomas Huth 4735fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4736fcf5ef2aSThomas Huth { 4737fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4738efe843d8SDavid Gibson if (ctx->has_cfar) { 4739fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4740efe843d8SDavid Gibson } 4741fcf5ef2aSThomas Huth #endif 4742fcf5ef2aSThomas Huth } 4743fcf5ef2aSThomas Huth 4744fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4745fcf5ef2aSThomas Huth { 4746fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4747fcf5ef2aSThomas Huth return false; 4748fcf5ef2aSThomas Huth } 4749fcf5ef2aSThomas Huth 4750fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4751b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4752fcf5ef2aSThomas Huth #else 4753fcf5ef2aSThomas Huth return true; 4754fcf5ef2aSThomas Huth #endif 4755fcf5ef2aSThomas Huth } 4756fcf5ef2aSThomas Huth 47570e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 47580e3bf489SRoman Kapl { 47590e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 47600e3bf489SRoman Kapl if (unlikely(sse)) { 47610e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 47620e3bf489SRoman Kapl gen_debug_exception(ctx); 47630e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4764e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 47650e3bf489SRoman Kapl gen_exception(ctx, excp); 47660e3bf489SRoman Kapl } 47670e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 47680e3bf489SRoman Kapl } else { 47690e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 47700e3bf489SRoman Kapl } 47710e3bf489SRoman Kapl } 47720e3bf489SRoman Kapl 4773fcf5ef2aSThomas Huth /*** Branch ***/ 4774c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4775fcf5ef2aSThomas Huth { 4776fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4777fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4778fcf5ef2aSThomas Huth } 4779fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4780fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4781fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 478207ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4783fcf5ef2aSThomas Huth } else { 4784fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 47850e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4786fcf5ef2aSThomas Huth } 4787fcf5ef2aSThomas Huth } 4788fcf5ef2aSThomas Huth 4789fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4790fcf5ef2aSThomas Huth { 4791fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4792fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4793fcf5ef2aSThomas Huth } 4794fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4795fcf5ef2aSThomas Huth } 4796fcf5ef2aSThomas Huth 4797fcf5ef2aSThomas Huth /* b ba bl bla */ 4798fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4799fcf5ef2aSThomas Huth { 4800fcf5ef2aSThomas Huth target_ulong li, target; 4801fcf5ef2aSThomas Huth 4802fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 4803fcf5ef2aSThomas Huth /* sign extend LI */ 4804fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4805fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4806fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 48072c2bcb1bSRichard Henderson target = ctx->cia + li; 4808fcf5ef2aSThomas Huth } else { 4809fcf5ef2aSThomas Huth target = li; 4810fcf5ef2aSThomas Huth } 4811fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4812b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4813fcf5ef2aSThomas Huth } 48142c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4815fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 4816fcf5ef2aSThomas Huth } 4817fcf5ef2aSThomas Huth 4818fcf5ef2aSThomas Huth #define BCOND_IM 0 4819fcf5ef2aSThomas Huth #define BCOND_LR 1 4820fcf5ef2aSThomas Huth #define BCOND_CTR 2 4821fcf5ef2aSThomas Huth #define BCOND_TAR 3 4822fcf5ef2aSThomas Huth 4823c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4824fcf5ef2aSThomas Huth { 4825fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4826fcf5ef2aSThomas Huth TCGLabel *l1; 4827fcf5ef2aSThomas Huth TCGv target; 4828fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 48290e3bf489SRoman Kapl 4830fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4831fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4832efe843d8SDavid Gibson if (type == BCOND_CTR) { 4833fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4834efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4835fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4836efe843d8SDavid Gibson } else { 4837fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4838efe843d8SDavid Gibson } 4839fcf5ef2aSThomas Huth } else { 4840f764718dSRichard Henderson target = NULL; 4841fcf5ef2aSThomas Huth } 4842efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4843b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4844efe843d8SDavid Gibson } 4845fcf5ef2aSThomas Huth l1 = gen_new_label(); 4846fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4847fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4848fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4849fa200c95SGreg Kurz 4850fa200c95SGreg Kurz if (type == BCOND_CTR) { 4851fa200c95SGreg Kurz /* 4852fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4853fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4854fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 485515d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 485615d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 485715d68c5eSGreg Kurz * it basically useless and thus never used in real code. 485815d68c5eSGreg Kurz * 485915d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 486015d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 486115d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 486215d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 486315d68c5eSGreg Kurz * doing anything else harmful. 4864fa200c95SGreg Kurz */ 4865d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4866fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 48679acc95cdSGreg Kurz tcg_temp_free(temp); 48689acc95cdSGreg Kurz tcg_temp_free(target); 4869fcf5ef2aSThomas Huth return; 4870fcf5ef2aSThomas Huth } 4871fa200c95SGreg Kurz 4872fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4873fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4874fa200c95SGreg Kurz } else { 4875fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4876fa200c95SGreg Kurz } 4877fa200c95SGreg Kurz if (bo & 0x2) { 4878fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4879fa200c95SGreg Kurz } else { 4880fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4881fa200c95SGreg Kurz } 4882fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4883fa200c95SGreg Kurz } else { 4884fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4885fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4886fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4887fcf5ef2aSThomas Huth } else { 4888fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4889fcf5ef2aSThomas Huth } 4890fcf5ef2aSThomas Huth if (bo & 0x2) { 4891fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4892fcf5ef2aSThomas Huth } else { 4893fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4894fcf5ef2aSThomas Huth } 4895fa200c95SGreg Kurz } 4896fcf5ef2aSThomas Huth tcg_temp_free(temp); 4897fcf5ef2aSThomas Huth } 4898fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4899fcf5ef2aSThomas Huth /* Test CR */ 4900fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4901fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4902fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4903fcf5ef2aSThomas Huth 4904fcf5ef2aSThomas Huth if (bo & 0x8) { 4905fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4906fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4907fcf5ef2aSThomas Huth } else { 4908fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4909fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4910fcf5ef2aSThomas Huth } 4911fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4912fcf5ef2aSThomas Huth } 49132c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4914fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4915fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4916fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 49172c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4918fcf5ef2aSThomas Huth } else { 4919fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4920fcf5ef2aSThomas Huth } 4921fcf5ef2aSThomas Huth } else { 4922fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4923fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4924fcf5ef2aSThomas Huth } else { 4925fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4926fcf5ef2aSThomas Huth } 49270e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4928c4a2e3a9SRichard Henderson tcg_temp_free(target); 4929c4a2e3a9SRichard Henderson } 4930fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 49310e3bf489SRoman Kapl /* fallthrough case */ 4932fcf5ef2aSThomas Huth gen_set_label(l1); 4933b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4934fcf5ef2aSThomas Huth } 4935fcf5ef2aSThomas Huth } 4936fcf5ef2aSThomas Huth 4937fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4938fcf5ef2aSThomas Huth { 4939fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4940fcf5ef2aSThomas Huth } 4941fcf5ef2aSThomas Huth 4942fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4943fcf5ef2aSThomas Huth { 4944fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4945fcf5ef2aSThomas Huth } 4946fcf5ef2aSThomas Huth 4947fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4948fcf5ef2aSThomas Huth { 4949fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4950fcf5ef2aSThomas Huth } 4951fcf5ef2aSThomas Huth 4952fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4953fcf5ef2aSThomas Huth { 4954fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4955fcf5ef2aSThomas Huth } 4956fcf5ef2aSThomas Huth 4957fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4958fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4959fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4960fcf5ef2aSThomas Huth { \ 4961fcf5ef2aSThomas Huth uint8_t bitmask; \ 4962fcf5ef2aSThomas Huth int sh; \ 4963fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4964fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4965fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4966fcf5ef2aSThomas Huth if (sh > 0) \ 4967fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4968fcf5ef2aSThomas Huth else if (sh < 0) \ 4969fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4970fcf5ef2aSThomas Huth else \ 4971fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4972fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4973fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4974fcf5ef2aSThomas Huth if (sh > 0) \ 4975fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4976fcf5ef2aSThomas Huth else if (sh < 0) \ 4977fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4978fcf5ef2aSThomas Huth else \ 4979fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4980fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4981fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4982fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4983fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4984fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4985fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4986fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4987fcf5ef2aSThomas Huth } 4988fcf5ef2aSThomas Huth 4989fcf5ef2aSThomas Huth /* crand */ 4990fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4991fcf5ef2aSThomas Huth /* crandc */ 4992fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4993fcf5ef2aSThomas Huth /* creqv */ 4994fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4995fcf5ef2aSThomas Huth /* crnand */ 4996fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4997fcf5ef2aSThomas Huth /* crnor */ 4998fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4999fcf5ef2aSThomas Huth /* cror */ 5000fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 5001fcf5ef2aSThomas Huth /* crorc */ 5002fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 5003fcf5ef2aSThomas Huth /* crxor */ 5004fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 5005fcf5ef2aSThomas Huth 5006fcf5ef2aSThomas Huth /* mcrf */ 5007fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 5008fcf5ef2aSThomas Huth { 5009fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 5010fcf5ef2aSThomas Huth } 5011fcf5ef2aSThomas Huth 5012fcf5ef2aSThomas Huth /*** System linkage ***/ 5013fcf5ef2aSThomas Huth 5014fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 5015fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 5016fcf5ef2aSThomas Huth { 5017fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5018fcf5ef2aSThomas Huth GEN_PRIV; 5019fcf5ef2aSThomas Huth #else 5020efe843d8SDavid Gibson /* 5021efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 5022fcf5ef2aSThomas Huth * processors compliant with arch 2.x 5023fcf5ef2aSThomas Huth */ 5024d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 5025fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5026fcf5ef2aSThomas Huth return; 5027fcf5ef2aSThomas Huth } 5028fcf5ef2aSThomas Huth /* Restore CPU state */ 5029fcf5ef2aSThomas Huth CHK_SV; 5030a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5031a59d628fSMaria Klimushenkova gen_io_start(); 5032a59d628fSMaria Klimushenkova } 50332c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 5034fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 5035fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5036fcf5ef2aSThomas Huth #endif 5037fcf5ef2aSThomas Huth } 5038fcf5ef2aSThomas Huth 5039fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5040fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 5041fcf5ef2aSThomas Huth { 5042fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5043fcf5ef2aSThomas Huth GEN_PRIV; 5044fcf5ef2aSThomas Huth #else 5045fcf5ef2aSThomas Huth /* Restore CPU state */ 5046fcf5ef2aSThomas Huth CHK_SV; 5047a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5048a59d628fSMaria Klimushenkova gen_io_start(); 5049a59d628fSMaria Klimushenkova } 50502c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 5051fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 5052fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5053fcf5ef2aSThomas Huth #endif 5054fcf5ef2aSThomas Huth } 5055fcf5ef2aSThomas Huth 50563c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 50573c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 50583c89b8d6SNicholas Piggin { 50593c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 50603c89b8d6SNicholas Piggin GEN_PRIV; 50613c89b8d6SNicholas Piggin #else 50623c89b8d6SNicholas Piggin /* Restore CPU state */ 50633c89b8d6SNicholas Piggin CHK_SV; 50643c89b8d6SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 50653c89b8d6SNicholas Piggin gen_io_start(); 50663c89b8d6SNicholas Piggin } 50672c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 50683c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 50693c89b8d6SNicholas Piggin gen_sync_exception(ctx); 50703c89b8d6SNicholas Piggin #endif 50713c89b8d6SNicholas Piggin } 50723c89b8d6SNicholas Piggin #endif 50733c89b8d6SNicholas Piggin 5074fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 5075fcf5ef2aSThomas Huth { 5076fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5077fcf5ef2aSThomas Huth GEN_PRIV; 5078fcf5ef2aSThomas Huth #else 5079fcf5ef2aSThomas Huth /* Restore CPU state */ 5080fcf5ef2aSThomas Huth CHK_HV; 5081fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 5082fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5083fcf5ef2aSThomas Huth #endif 5084fcf5ef2aSThomas Huth } 5085fcf5ef2aSThomas Huth #endif 5086fcf5ef2aSThomas Huth 5087fcf5ef2aSThomas Huth /* sc */ 5088fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5089fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 5090fcf5ef2aSThomas Huth #else 5091fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 50923c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 5093fcf5ef2aSThomas Huth #endif 5094fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 5095fcf5ef2aSThomas Huth { 5096fcf5ef2aSThomas Huth uint32_t lev; 5097fcf5ef2aSThomas Huth 5098fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 5099fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 5100fcf5ef2aSThomas Huth } 5101fcf5ef2aSThomas Huth 51023c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 51033c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 51043c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 51053c89b8d6SNicholas Piggin { 5106f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 51073c89b8d6SNicholas Piggin 5108f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 5109f43520e5SRichard Henderson if (ctx->exception == POWERPC_EXCP_NONE) { 51102c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 51113c89b8d6SNicholas Piggin } 5112f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 51133c89b8d6SNicholas Piggin 5114f43520e5SRichard Henderson /* This need not be exact, just not POWERPC_EXCP_NONE */ 5115f43520e5SRichard Henderson ctx->exception = POWERPC_SYSCALL_VECTORED; 51163c89b8d6SNicholas Piggin } 51173c89b8d6SNicholas Piggin #endif 51183c89b8d6SNicholas Piggin #endif 51193c89b8d6SNicholas Piggin 5120fcf5ef2aSThomas Huth /*** Trap ***/ 5121fcf5ef2aSThomas Huth 5122fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 5123fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 5124fcf5ef2aSThomas Huth { 5125fcf5ef2aSThomas Huth /* Trap never */ 5126fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 5127fcf5ef2aSThomas Huth return true; 5128fcf5ef2aSThomas Huth } 5129fcf5ef2aSThomas Huth /* Trap always */ 5130fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 5131fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 5132fcf5ef2aSThomas Huth return true; 5133fcf5ef2aSThomas Huth } 5134fcf5ef2aSThomas Huth return false; 5135fcf5ef2aSThomas Huth } 5136fcf5ef2aSThomas Huth 5137fcf5ef2aSThomas Huth /* tw */ 5138fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 5139fcf5ef2aSThomas Huth { 5140fcf5ef2aSThomas Huth TCGv_i32 t0; 5141fcf5ef2aSThomas Huth 5142fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5143fcf5ef2aSThomas Huth return; 5144fcf5ef2aSThomas Huth } 5145fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5146fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5147fcf5ef2aSThomas Huth t0); 5148fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5149fcf5ef2aSThomas Huth } 5150fcf5ef2aSThomas Huth 5151fcf5ef2aSThomas Huth /* twi */ 5152fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 5153fcf5ef2aSThomas Huth { 5154fcf5ef2aSThomas Huth TCGv t0; 5155fcf5ef2aSThomas Huth TCGv_i32 t1; 5156fcf5ef2aSThomas Huth 5157fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5158fcf5ef2aSThomas Huth return; 5159fcf5ef2aSThomas Huth } 5160fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5161fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5162fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5163fcf5ef2aSThomas Huth tcg_temp_free(t0); 5164fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5165fcf5ef2aSThomas Huth } 5166fcf5ef2aSThomas Huth 5167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5168fcf5ef2aSThomas Huth /* td */ 5169fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 5170fcf5ef2aSThomas Huth { 5171fcf5ef2aSThomas Huth TCGv_i32 t0; 5172fcf5ef2aSThomas Huth 5173fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5174fcf5ef2aSThomas Huth return; 5175fcf5ef2aSThomas Huth } 5176fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5177fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5178fcf5ef2aSThomas Huth t0); 5179fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5180fcf5ef2aSThomas Huth } 5181fcf5ef2aSThomas Huth 5182fcf5ef2aSThomas Huth /* tdi */ 5183fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 5184fcf5ef2aSThomas Huth { 5185fcf5ef2aSThomas Huth TCGv t0; 5186fcf5ef2aSThomas Huth TCGv_i32 t1; 5187fcf5ef2aSThomas Huth 5188fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5189fcf5ef2aSThomas Huth return; 5190fcf5ef2aSThomas Huth } 5191fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5192fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5193fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5194fcf5ef2aSThomas Huth tcg_temp_free(t0); 5195fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5196fcf5ef2aSThomas Huth } 5197fcf5ef2aSThomas Huth #endif 5198fcf5ef2aSThomas Huth 5199fcf5ef2aSThomas Huth /*** Processor control ***/ 5200fcf5ef2aSThomas Huth 5201fcf5ef2aSThomas Huth /* mcrxr */ 5202fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 5203fcf5ef2aSThomas Huth { 5204fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5205fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 5206fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5207fcf5ef2aSThomas Huth 5208fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 5209fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 5210fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 5211fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 5212fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 5213fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 5214fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 5215fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 5216fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5217fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5218fcf5ef2aSThomas Huth 5219fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 5220fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5221fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5222fcf5ef2aSThomas Huth } 5223fcf5ef2aSThomas Huth 5224b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 5225b63d0434SNikunj A Dadhania /* mcrxrx */ 5226b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 5227b63d0434SNikunj A Dadhania { 5228b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 5229b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 5230b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5231b63d0434SNikunj A Dadhania 5232b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 5233b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 5234b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 5235b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 5236b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 5237b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 5238b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 5239b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 5240b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 5241b63d0434SNikunj A Dadhania tcg_temp_free(t0); 5242b63d0434SNikunj A Dadhania tcg_temp_free(t1); 5243b63d0434SNikunj A Dadhania } 5244b63d0434SNikunj A Dadhania #endif 5245b63d0434SNikunj A Dadhania 5246fcf5ef2aSThomas Huth /* mfcr mfocrf */ 5247fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 5248fcf5ef2aSThomas Huth { 5249fcf5ef2aSThomas Huth uint32_t crm, crn; 5250fcf5ef2aSThomas Huth 5251fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 5252fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5253fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 5254fcf5ef2aSThomas Huth crn = ctz32(crm); 5255fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 5256fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 5257fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 5258fcf5ef2aSThomas Huth } 5259fcf5ef2aSThomas Huth } else { 5260fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5261fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 5262fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5263fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 5264fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5265fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 5266fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5267fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 5268fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5269fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 5270fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5271fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 5272fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5273fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 5274fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5275fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 5276fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5277fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5278fcf5ef2aSThomas Huth } 5279fcf5ef2aSThomas Huth } 5280fcf5ef2aSThomas Huth 5281fcf5ef2aSThomas Huth /* mfmsr */ 5282fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 5283fcf5ef2aSThomas Huth { 5284fcf5ef2aSThomas Huth CHK_SV; 5285fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 5286fcf5ef2aSThomas Huth } 5287fcf5ef2aSThomas Huth 5288fcf5ef2aSThomas Huth /* mfspr */ 5289fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 5290fcf5ef2aSThomas Huth { 5291fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 5292fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5293fcf5ef2aSThomas Huth 5294fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5295fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5296fcf5ef2aSThomas Huth #else 5297fcf5ef2aSThomas Huth if (ctx->pr) { 5298fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5299fcf5ef2aSThomas Huth } else if (ctx->hv) { 5300fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 5301fcf5ef2aSThomas Huth } else { 5302fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 5303fcf5ef2aSThomas Huth } 5304fcf5ef2aSThomas Huth #endif 5305fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 5306fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 5307fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 5308fcf5ef2aSThomas Huth } else { 5309fcf5ef2aSThomas Huth /* Privilege exception */ 5310efe843d8SDavid Gibson /* 5311efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 5312fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 5313fcf5ef2aSThomas Huth * allowing userland application to read the PVR 5314fcf5ef2aSThomas Huth */ 5315fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 531631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 531731085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 53182c2bcb1bSRichard Henderson ctx->cia); 5319fcf5ef2aSThomas Huth } 5320fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5321fcf5ef2aSThomas Huth } 5322fcf5ef2aSThomas Huth } else { 5323fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5324fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5325fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5326fcf5ef2aSThomas Huth /* This is a nop */ 5327fcf5ef2aSThomas Huth return; 5328fcf5ef2aSThomas Huth } 5329fcf5ef2aSThomas Huth /* Not defined */ 533031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 533131085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 53322c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5333fcf5ef2aSThomas Huth 5334efe843d8SDavid Gibson /* 5335efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5336efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5337fcf5ef2aSThomas Huth */ 5338fcf5ef2aSThomas Huth if (sprn & 0x10) { 5339fcf5ef2aSThomas Huth if (ctx->pr) { 5340fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5341fcf5ef2aSThomas Huth } 5342fcf5ef2aSThomas Huth } else { 5343fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5344fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5345fcf5ef2aSThomas Huth } 5346fcf5ef2aSThomas Huth } 5347fcf5ef2aSThomas Huth } 5348fcf5ef2aSThomas Huth } 5349fcf5ef2aSThomas Huth 5350fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5351fcf5ef2aSThomas Huth { 5352fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5353fcf5ef2aSThomas Huth } 5354fcf5ef2aSThomas Huth 5355fcf5ef2aSThomas Huth /* mftb */ 5356fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5357fcf5ef2aSThomas Huth { 5358fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5359fcf5ef2aSThomas Huth } 5360fcf5ef2aSThomas Huth 5361fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5362fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5363fcf5ef2aSThomas Huth { 5364fcf5ef2aSThomas Huth uint32_t crm, crn; 5365fcf5ef2aSThomas Huth 5366fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5367fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5368fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5369fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5370fcf5ef2aSThomas Huth crn = ctz32(crm); 5371fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5372fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5373fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5374fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5375fcf5ef2aSThomas Huth } 5376fcf5ef2aSThomas Huth } else { 5377fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5378fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5379fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5380fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5381fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5382fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5383fcf5ef2aSThomas Huth } 5384fcf5ef2aSThomas Huth } 5385fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5386fcf5ef2aSThomas Huth } 5387fcf5ef2aSThomas Huth } 5388fcf5ef2aSThomas Huth 5389fcf5ef2aSThomas Huth /* mtmsr */ 5390fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5391fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5392fcf5ef2aSThomas Huth { 5393fcf5ef2aSThomas Huth CHK_SV; 5394fcf5ef2aSThomas Huth 5395fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 53965ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 53975ed19506SNicholas Piggin gen_io_start(); 53985ed19506SNicholas Piggin } 5399fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54005ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5401fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54025ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5403efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5404efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54055ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5406efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54075ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54085ed19506SNicholas Piggin 54095ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5410fcf5ef2aSThomas Huth tcg_temp_free(t0); 54115ed19506SNicholas Piggin tcg_temp_free(t1); 54125ed19506SNicholas Piggin 5413fcf5ef2aSThomas Huth } else { 5414efe843d8SDavid Gibson /* 5415efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5416efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5417efe843d8SDavid Gibson * ppc_store_msr 5418fcf5ef2aSThomas Huth */ 5419b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5420fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5421fcf5ef2aSThomas Huth } 54225ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54235ed19506SNicholas Piggin gen_stop_exception(ctx); 5424fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5425fcf5ef2aSThomas Huth } 5426fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5427fcf5ef2aSThomas Huth 5428fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5429fcf5ef2aSThomas Huth { 5430fcf5ef2aSThomas Huth CHK_SV; 5431fcf5ef2aSThomas Huth 5432fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 54335ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54345ed19506SNicholas Piggin gen_io_start(); 54355ed19506SNicholas Piggin } 5436fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54375ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5438fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54395ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5440efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5441efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54425ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5443efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54445ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54455ed19506SNicholas Piggin 54465ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5447fcf5ef2aSThomas Huth tcg_temp_free(t0); 54485ed19506SNicholas Piggin tcg_temp_free(t1); 54495ed19506SNicholas Piggin 5450fcf5ef2aSThomas Huth } else { 5451fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5452fcf5ef2aSThomas Huth 5453efe843d8SDavid Gibson /* 5454efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5455efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5456efe843d8SDavid Gibson * ppc_store_msr 5457fcf5ef2aSThomas Huth */ 5458b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5459fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5460fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5461fcf5ef2aSThomas Huth #else 5462fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5463fcf5ef2aSThomas Huth #endif 5464fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5465fcf5ef2aSThomas Huth tcg_temp_free(msr); 5466fcf5ef2aSThomas Huth } 54675ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54685ed19506SNicholas Piggin gen_stop_exception(ctx); 5469fcf5ef2aSThomas Huth #endif 5470fcf5ef2aSThomas Huth } 5471fcf5ef2aSThomas Huth 5472fcf5ef2aSThomas Huth /* mtspr */ 5473fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5474fcf5ef2aSThomas Huth { 5475fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5476fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5477fcf5ef2aSThomas Huth 5478fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5479fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5480fcf5ef2aSThomas Huth #else 5481fcf5ef2aSThomas Huth if (ctx->pr) { 5482fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5483fcf5ef2aSThomas Huth } else if (ctx->hv) { 5484fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5485fcf5ef2aSThomas Huth } else { 5486fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5487fcf5ef2aSThomas Huth } 5488fcf5ef2aSThomas Huth #endif 5489fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5490fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5491fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5492fcf5ef2aSThomas Huth } else { 5493fcf5ef2aSThomas Huth /* Privilege exception */ 549431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 549531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 54962c2bcb1bSRichard Henderson ctx->cia); 5497fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5498fcf5ef2aSThomas Huth } 5499fcf5ef2aSThomas Huth } else { 5500fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5501fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5502fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5503fcf5ef2aSThomas Huth /* This is a nop */ 5504fcf5ef2aSThomas Huth return; 5505fcf5ef2aSThomas Huth } 5506fcf5ef2aSThomas Huth 5507fcf5ef2aSThomas Huth /* Not defined */ 550831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 550931085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 55102c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5511fcf5ef2aSThomas Huth 5512fcf5ef2aSThomas Huth 5513efe843d8SDavid Gibson /* 5514efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5515efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5516fcf5ef2aSThomas Huth */ 5517fcf5ef2aSThomas Huth if (sprn & 0x10) { 5518fcf5ef2aSThomas Huth if (ctx->pr) { 5519fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5520fcf5ef2aSThomas Huth } 5521fcf5ef2aSThomas Huth } else { 5522fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5523fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5524fcf5ef2aSThomas Huth } 5525fcf5ef2aSThomas Huth } 5526fcf5ef2aSThomas Huth } 5527fcf5ef2aSThomas Huth } 5528fcf5ef2aSThomas Huth 5529fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5530fcf5ef2aSThomas Huth /* setb */ 5531fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5532fcf5ef2aSThomas Huth { 5533fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5534fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5535fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5536fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5537fcf5ef2aSThomas Huth 5538fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5539fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5540fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5541fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5542fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5543fcf5ef2aSThomas Huth 5544fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5545fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5546fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5547fcf5ef2aSThomas Huth } 5548fcf5ef2aSThomas Huth #endif 5549fcf5ef2aSThomas Huth 5550fcf5ef2aSThomas Huth /*** Cache management ***/ 5551fcf5ef2aSThomas Huth 5552fcf5ef2aSThomas Huth /* dcbf */ 5553fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5554fcf5ef2aSThomas Huth { 5555fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5556fcf5ef2aSThomas Huth TCGv t0; 5557fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5558fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5559fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5560fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5561fcf5ef2aSThomas Huth tcg_temp_free(t0); 5562fcf5ef2aSThomas Huth } 5563fcf5ef2aSThomas Huth 556450728199SRoman Kapl /* dcbfep (external PID dcbf) */ 556550728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 556650728199SRoman Kapl { 556750728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 556850728199SRoman Kapl TCGv t0; 556950728199SRoman Kapl CHK_SV; 557050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 557150728199SRoman Kapl t0 = tcg_temp_new(); 557250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 557350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 557450728199SRoman Kapl tcg_temp_free(t0); 557550728199SRoman Kapl } 557650728199SRoman Kapl 5577fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5578fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5579fcf5ef2aSThomas Huth { 5580fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5581fcf5ef2aSThomas Huth GEN_PRIV; 5582fcf5ef2aSThomas Huth #else 5583fcf5ef2aSThomas Huth TCGv EA, val; 5584fcf5ef2aSThomas Huth 5585fcf5ef2aSThomas Huth CHK_SV; 5586fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5587fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5588fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5589fcf5ef2aSThomas Huth val = tcg_temp_new(); 5590fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5591fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5592fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5593fcf5ef2aSThomas Huth tcg_temp_free(val); 5594fcf5ef2aSThomas Huth tcg_temp_free(EA); 5595fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5596fcf5ef2aSThomas Huth } 5597fcf5ef2aSThomas Huth 5598fcf5ef2aSThomas Huth /* dcdst */ 5599fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5600fcf5ef2aSThomas Huth { 5601fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5602fcf5ef2aSThomas Huth TCGv t0; 5603fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5604fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5605fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5606fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5607fcf5ef2aSThomas Huth tcg_temp_free(t0); 5608fcf5ef2aSThomas Huth } 5609fcf5ef2aSThomas Huth 561050728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 561150728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 561250728199SRoman Kapl { 561350728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 561450728199SRoman Kapl TCGv t0; 561550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 561650728199SRoman Kapl t0 = tcg_temp_new(); 561750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 561850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 561950728199SRoman Kapl tcg_temp_free(t0); 562050728199SRoman Kapl } 562150728199SRoman Kapl 5622fcf5ef2aSThomas Huth /* dcbt */ 5623fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5624fcf5ef2aSThomas Huth { 5625efe843d8SDavid Gibson /* 5626efe843d8SDavid Gibson * interpreted as no-op 5627efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5628efe843d8SDavid Gibson * does not generate any exception 5629fcf5ef2aSThomas Huth */ 5630fcf5ef2aSThomas Huth } 5631fcf5ef2aSThomas Huth 563250728199SRoman Kapl /* dcbtep */ 563350728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 563450728199SRoman Kapl { 5635efe843d8SDavid Gibson /* 5636efe843d8SDavid Gibson * interpreted as no-op 5637efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5638efe843d8SDavid Gibson * does not generate any exception 563950728199SRoman Kapl */ 564050728199SRoman Kapl } 564150728199SRoman Kapl 5642fcf5ef2aSThomas Huth /* dcbtst */ 5643fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5644fcf5ef2aSThomas Huth { 5645efe843d8SDavid Gibson /* 5646efe843d8SDavid Gibson * interpreted as no-op 5647efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5648efe843d8SDavid Gibson * does not generate any exception 5649fcf5ef2aSThomas Huth */ 5650fcf5ef2aSThomas Huth } 5651fcf5ef2aSThomas Huth 565250728199SRoman Kapl /* dcbtstep */ 565350728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 565450728199SRoman Kapl { 5655efe843d8SDavid Gibson /* 5656efe843d8SDavid Gibson * interpreted as no-op 5657efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5658efe843d8SDavid Gibson * does not generate any exception 565950728199SRoman Kapl */ 566050728199SRoman Kapl } 566150728199SRoman Kapl 5662fcf5ef2aSThomas Huth /* dcbtls */ 5663fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5664fcf5ef2aSThomas Huth { 5665fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5666fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5667fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5668fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5669fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5670fcf5ef2aSThomas Huth tcg_temp_free(t0); 5671fcf5ef2aSThomas Huth } 5672fcf5ef2aSThomas Huth 5673fcf5ef2aSThomas Huth /* dcbz */ 5674fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5675fcf5ef2aSThomas Huth { 5676fcf5ef2aSThomas Huth TCGv tcgv_addr; 5677fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5678fcf5ef2aSThomas Huth 5679fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5680fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5681fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5682fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5683fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5684fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5685fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5686fcf5ef2aSThomas Huth } 5687fcf5ef2aSThomas Huth 568850728199SRoman Kapl /* dcbzep */ 568950728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 569050728199SRoman Kapl { 569150728199SRoman Kapl TCGv tcgv_addr; 569250728199SRoman Kapl TCGv_i32 tcgv_op; 569350728199SRoman Kapl 569450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 569550728199SRoman Kapl tcgv_addr = tcg_temp_new(); 569650728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 569750728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 569850728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 569950728199SRoman Kapl tcg_temp_free(tcgv_addr); 570050728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 570150728199SRoman Kapl } 570250728199SRoman Kapl 5703fcf5ef2aSThomas Huth /* dst / dstt */ 5704fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5705fcf5ef2aSThomas Huth { 5706fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5707fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5708fcf5ef2aSThomas Huth } else { 5709fcf5ef2aSThomas Huth /* interpreted as no-op */ 5710fcf5ef2aSThomas Huth } 5711fcf5ef2aSThomas Huth } 5712fcf5ef2aSThomas Huth 5713fcf5ef2aSThomas Huth /* dstst /dststt */ 5714fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5715fcf5ef2aSThomas Huth { 5716fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5717fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5718fcf5ef2aSThomas Huth } else { 5719fcf5ef2aSThomas Huth /* interpreted as no-op */ 5720fcf5ef2aSThomas Huth } 5721fcf5ef2aSThomas Huth 5722fcf5ef2aSThomas Huth } 5723fcf5ef2aSThomas Huth 5724fcf5ef2aSThomas Huth /* dss / dssall */ 5725fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5726fcf5ef2aSThomas Huth { 5727fcf5ef2aSThomas Huth /* interpreted as no-op */ 5728fcf5ef2aSThomas Huth } 5729fcf5ef2aSThomas Huth 5730fcf5ef2aSThomas Huth /* icbi */ 5731fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5732fcf5ef2aSThomas Huth { 5733fcf5ef2aSThomas Huth TCGv t0; 5734fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5735fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5736fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5737fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5738fcf5ef2aSThomas Huth tcg_temp_free(t0); 5739fcf5ef2aSThomas Huth } 5740fcf5ef2aSThomas Huth 574150728199SRoman Kapl /* icbiep */ 574250728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 574350728199SRoman Kapl { 574450728199SRoman Kapl TCGv t0; 574550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 574650728199SRoman Kapl t0 = tcg_temp_new(); 574750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 574850728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 574950728199SRoman Kapl tcg_temp_free(t0); 575050728199SRoman Kapl } 575150728199SRoman Kapl 5752fcf5ef2aSThomas Huth /* Optional: */ 5753fcf5ef2aSThomas Huth /* dcba */ 5754fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5755fcf5ef2aSThomas Huth { 5756efe843d8SDavid Gibson /* 5757efe843d8SDavid Gibson * interpreted as no-op 5758efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5759fcf5ef2aSThomas Huth * but does not generate any exception 5760fcf5ef2aSThomas Huth */ 5761fcf5ef2aSThomas Huth } 5762fcf5ef2aSThomas Huth 5763fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5764fcf5ef2aSThomas Huth /* Supervisor only: */ 5765fcf5ef2aSThomas Huth 5766fcf5ef2aSThomas Huth /* mfsr */ 5767fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5768fcf5ef2aSThomas Huth { 5769fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5770fcf5ef2aSThomas Huth GEN_PRIV; 5771fcf5ef2aSThomas Huth #else 5772fcf5ef2aSThomas Huth TCGv t0; 5773fcf5ef2aSThomas Huth 5774fcf5ef2aSThomas Huth CHK_SV; 5775fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5776fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5777fcf5ef2aSThomas Huth tcg_temp_free(t0); 5778fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5779fcf5ef2aSThomas Huth } 5780fcf5ef2aSThomas Huth 5781fcf5ef2aSThomas Huth /* mfsrin */ 5782fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5783fcf5ef2aSThomas Huth { 5784fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5785fcf5ef2aSThomas Huth GEN_PRIV; 5786fcf5ef2aSThomas Huth #else 5787fcf5ef2aSThomas Huth TCGv t0; 5788fcf5ef2aSThomas Huth 5789fcf5ef2aSThomas Huth CHK_SV; 5790fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5791e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5792fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5793fcf5ef2aSThomas Huth tcg_temp_free(t0); 5794fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5795fcf5ef2aSThomas Huth } 5796fcf5ef2aSThomas Huth 5797fcf5ef2aSThomas Huth /* mtsr */ 5798fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5799fcf5ef2aSThomas Huth { 5800fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5801fcf5ef2aSThomas Huth GEN_PRIV; 5802fcf5ef2aSThomas Huth #else 5803fcf5ef2aSThomas Huth TCGv t0; 5804fcf5ef2aSThomas Huth 5805fcf5ef2aSThomas Huth CHK_SV; 5806fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5807fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5808fcf5ef2aSThomas Huth tcg_temp_free(t0); 5809fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5810fcf5ef2aSThomas Huth } 5811fcf5ef2aSThomas Huth 5812fcf5ef2aSThomas Huth /* mtsrin */ 5813fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5814fcf5ef2aSThomas Huth { 5815fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5816fcf5ef2aSThomas Huth GEN_PRIV; 5817fcf5ef2aSThomas Huth #else 5818fcf5ef2aSThomas Huth TCGv t0; 5819fcf5ef2aSThomas Huth CHK_SV; 5820fcf5ef2aSThomas Huth 5821fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5822e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5823fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5824fcf5ef2aSThomas Huth tcg_temp_free(t0); 5825fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5826fcf5ef2aSThomas Huth } 5827fcf5ef2aSThomas Huth 5828fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5829fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5830fcf5ef2aSThomas Huth 5831fcf5ef2aSThomas Huth /* mfsr */ 5832fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5833fcf5ef2aSThomas Huth { 5834fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5835fcf5ef2aSThomas Huth GEN_PRIV; 5836fcf5ef2aSThomas Huth #else 5837fcf5ef2aSThomas Huth TCGv t0; 5838fcf5ef2aSThomas Huth 5839fcf5ef2aSThomas Huth CHK_SV; 5840fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5841fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5842fcf5ef2aSThomas Huth tcg_temp_free(t0); 5843fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5844fcf5ef2aSThomas Huth } 5845fcf5ef2aSThomas Huth 5846fcf5ef2aSThomas Huth /* mfsrin */ 5847fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5848fcf5ef2aSThomas Huth { 5849fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5850fcf5ef2aSThomas Huth GEN_PRIV; 5851fcf5ef2aSThomas Huth #else 5852fcf5ef2aSThomas Huth TCGv t0; 5853fcf5ef2aSThomas Huth 5854fcf5ef2aSThomas Huth CHK_SV; 5855fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5856e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5857fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5858fcf5ef2aSThomas Huth tcg_temp_free(t0); 5859fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5860fcf5ef2aSThomas Huth } 5861fcf5ef2aSThomas Huth 5862fcf5ef2aSThomas Huth /* mtsr */ 5863fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5864fcf5ef2aSThomas Huth { 5865fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5866fcf5ef2aSThomas Huth GEN_PRIV; 5867fcf5ef2aSThomas Huth #else 5868fcf5ef2aSThomas Huth TCGv t0; 5869fcf5ef2aSThomas Huth 5870fcf5ef2aSThomas Huth CHK_SV; 5871fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5872fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5873fcf5ef2aSThomas Huth tcg_temp_free(t0); 5874fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5875fcf5ef2aSThomas Huth } 5876fcf5ef2aSThomas Huth 5877fcf5ef2aSThomas Huth /* mtsrin */ 5878fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5879fcf5ef2aSThomas Huth { 5880fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5881fcf5ef2aSThomas Huth GEN_PRIV; 5882fcf5ef2aSThomas Huth #else 5883fcf5ef2aSThomas Huth TCGv t0; 5884fcf5ef2aSThomas Huth 5885fcf5ef2aSThomas Huth CHK_SV; 5886fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5887e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5888fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5889fcf5ef2aSThomas Huth tcg_temp_free(t0); 5890fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5891fcf5ef2aSThomas Huth } 5892fcf5ef2aSThomas Huth 5893fcf5ef2aSThomas Huth /* slbmte */ 5894fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5895fcf5ef2aSThomas Huth { 5896fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5897fcf5ef2aSThomas Huth GEN_PRIV; 5898fcf5ef2aSThomas Huth #else 5899fcf5ef2aSThomas Huth CHK_SV; 5900fcf5ef2aSThomas Huth 5901fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5902fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5903fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5904fcf5ef2aSThomas Huth } 5905fcf5ef2aSThomas Huth 5906fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5907fcf5ef2aSThomas Huth { 5908fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5909fcf5ef2aSThomas Huth GEN_PRIV; 5910fcf5ef2aSThomas Huth #else 5911fcf5ef2aSThomas Huth CHK_SV; 5912fcf5ef2aSThomas Huth 5913fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5914fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5915fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5916fcf5ef2aSThomas Huth } 5917fcf5ef2aSThomas Huth 5918fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5919fcf5ef2aSThomas Huth { 5920fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5921fcf5ef2aSThomas Huth GEN_PRIV; 5922fcf5ef2aSThomas Huth #else 5923fcf5ef2aSThomas Huth CHK_SV; 5924fcf5ef2aSThomas Huth 5925fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5926fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5927fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5928fcf5ef2aSThomas Huth } 5929fcf5ef2aSThomas Huth 5930fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5931fcf5ef2aSThomas Huth { 5932fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5933fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5934fcf5ef2aSThomas Huth #else 5935fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5936fcf5ef2aSThomas Huth 5937fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5938fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5939fcf5ef2aSThomas Huth return; 5940fcf5ef2aSThomas Huth } 5941fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5942fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5943fcf5ef2aSThomas Huth l1 = gen_new_label(); 5944fcf5ef2aSThomas Huth l2 = gen_new_label(); 5945fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5946fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5947efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5948fcf5ef2aSThomas Huth tcg_gen_br(l2); 5949fcf5ef2aSThomas Huth gen_set_label(l1); 5950fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5951fcf5ef2aSThomas Huth gen_set_label(l2); 5952fcf5ef2aSThomas Huth #endif 5953fcf5ef2aSThomas Huth } 5954fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5955fcf5ef2aSThomas Huth 5956fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5957fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5958fcf5ef2aSThomas Huth 5959fcf5ef2aSThomas Huth /* tlbia */ 5960fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5961fcf5ef2aSThomas Huth { 5962fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5963fcf5ef2aSThomas Huth GEN_PRIV; 5964fcf5ef2aSThomas Huth #else 5965fcf5ef2aSThomas Huth CHK_HV; 5966fcf5ef2aSThomas Huth 5967fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5968fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5969fcf5ef2aSThomas Huth } 5970fcf5ef2aSThomas Huth 5971fcf5ef2aSThomas Huth /* tlbiel */ 5972fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5973fcf5ef2aSThomas Huth { 5974fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5975fcf5ef2aSThomas Huth GEN_PRIV; 5976fcf5ef2aSThomas Huth #else 5977fcf5ef2aSThomas Huth CHK_SV; 5978fcf5ef2aSThomas Huth 5979fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5980fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5981fcf5ef2aSThomas Huth } 5982fcf5ef2aSThomas Huth 5983fcf5ef2aSThomas Huth /* tlbie */ 5984fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5985fcf5ef2aSThomas Huth { 5986fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5987fcf5ef2aSThomas Huth GEN_PRIV; 5988fcf5ef2aSThomas Huth #else 5989fcf5ef2aSThomas Huth TCGv_i32 t1; 5990c6fd28fdSSuraj Jitindar Singh 5991c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 599291c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5993c6fd28fdSSuraj Jitindar Singh } else { 5994c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5995c6fd28fdSSuraj Jitindar Singh } 5996fcf5ef2aSThomas Huth 5997fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5998fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5999fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 6000fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 6001fcf5ef2aSThomas Huth tcg_temp_free(t0); 6002fcf5ef2aSThomas Huth } else { 6003fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6004fcf5ef2aSThomas Huth } 6005fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 6006fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6007fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 6008fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6009fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6010fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6011fcf5ef2aSThomas Huth } 6012fcf5ef2aSThomas Huth 6013fcf5ef2aSThomas Huth /* tlbsync */ 6014fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 6015fcf5ef2aSThomas Huth { 6016fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6017fcf5ef2aSThomas Huth GEN_PRIV; 6018fcf5ef2aSThomas Huth #else 601991c60f12SCédric Le Goater 602091c60f12SCédric Le Goater if (ctx->gtse) { 602191c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 602291c60f12SCédric Le Goater } else { 602391c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 602491c60f12SCédric Le Goater } 6025fcf5ef2aSThomas Huth 6026fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 6027fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 6028fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 6029fcf5ef2aSThomas Huth } 6030fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6031fcf5ef2aSThomas Huth } 6032fcf5ef2aSThomas Huth 6033fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6034fcf5ef2aSThomas Huth /* slbia */ 6035fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 6036fcf5ef2aSThomas Huth { 6037fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6038fcf5ef2aSThomas Huth GEN_PRIV; 6039fcf5ef2aSThomas Huth #else 60400418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 60410418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 60420418bf78SNicholas Piggin 6043fcf5ef2aSThomas Huth CHK_SV; 6044fcf5ef2aSThomas Huth 60450418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 60463119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 6047fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6048fcf5ef2aSThomas Huth } 6049fcf5ef2aSThomas Huth 6050fcf5ef2aSThomas Huth /* slbie */ 6051fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 6052fcf5ef2aSThomas Huth { 6053fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6054fcf5ef2aSThomas Huth GEN_PRIV; 6055fcf5ef2aSThomas Huth #else 6056fcf5ef2aSThomas Huth CHK_SV; 6057fcf5ef2aSThomas Huth 6058fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6059fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6060fcf5ef2aSThomas Huth } 6061a63f1dfcSNikunj A Dadhania 6062a63f1dfcSNikunj A Dadhania /* slbieg */ 6063a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 6064a63f1dfcSNikunj A Dadhania { 6065a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 6066a63f1dfcSNikunj A Dadhania GEN_PRIV; 6067a63f1dfcSNikunj A Dadhania #else 6068a63f1dfcSNikunj A Dadhania CHK_SV; 6069a63f1dfcSNikunj A Dadhania 6070a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6071a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 6072a63f1dfcSNikunj A Dadhania } 6073a63f1dfcSNikunj A Dadhania 607462d897caSNikunj A Dadhania /* slbsync */ 607562d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 607662d897caSNikunj A Dadhania { 607762d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 607862d897caSNikunj A Dadhania GEN_PRIV; 607962d897caSNikunj A Dadhania #else 608062d897caSNikunj A Dadhania CHK_SV; 608162d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 608262d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 608362d897caSNikunj A Dadhania } 608462d897caSNikunj A Dadhania 6085fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6086fcf5ef2aSThomas Huth 6087fcf5ef2aSThomas Huth /*** External control ***/ 6088fcf5ef2aSThomas Huth /* Optional: */ 6089fcf5ef2aSThomas Huth 6090fcf5ef2aSThomas Huth /* eciwx */ 6091fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 6092fcf5ef2aSThomas Huth { 6093fcf5ef2aSThomas Huth TCGv t0; 6094fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6095fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6096fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6097fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6098c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6099c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6100fcf5ef2aSThomas Huth tcg_temp_free(t0); 6101fcf5ef2aSThomas Huth } 6102fcf5ef2aSThomas Huth 6103fcf5ef2aSThomas Huth /* ecowx */ 6104fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 6105fcf5ef2aSThomas Huth { 6106fcf5ef2aSThomas Huth TCGv t0; 6107fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6108fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6109fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6110fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6111c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6112c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6113fcf5ef2aSThomas Huth tcg_temp_free(t0); 6114fcf5ef2aSThomas Huth } 6115fcf5ef2aSThomas Huth 6116fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 6117fcf5ef2aSThomas Huth 6118fcf5ef2aSThomas Huth /* abs - abs. */ 6119fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 6120fcf5ef2aSThomas Huth { 6121fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6122fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6123fe21b785SRichard Henderson 6124fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6125efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6126fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6127fcf5ef2aSThomas Huth } 6128efe843d8SDavid Gibson } 6129fcf5ef2aSThomas Huth 6130fcf5ef2aSThomas Huth /* abso - abso. */ 6131fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 6132fcf5ef2aSThomas Huth { 6133fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6134fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6135fe21b785SRichard Henderson 6136fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 6137fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6138fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 6139efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6140fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6141fcf5ef2aSThomas Huth } 6142efe843d8SDavid Gibson } 6143fcf5ef2aSThomas Huth 6144fcf5ef2aSThomas Huth /* clcs */ 6145fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 6146fcf5ef2aSThomas Huth { 6147fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 6148fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6149fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6150fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 6151fcf5ef2aSThomas Huth } 6152fcf5ef2aSThomas Huth 6153fcf5ef2aSThomas Huth /* div - div. */ 6154fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 6155fcf5ef2aSThomas Huth { 6156fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6157fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6158efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6159fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6160fcf5ef2aSThomas Huth } 6161efe843d8SDavid Gibson } 6162fcf5ef2aSThomas Huth 6163fcf5ef2aSThomas Huth /* divo - divo. */ 6164fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 6165fcf5ef2aSThomas Huth { 6166fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6167fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6168efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6169fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6170fcf5ef2aSThomas Huth } 6171efe843d8SDavid Gibson } 6172fcf5ef2aSThomas Huth 6173fcf5ef2aSThomas Huth /* divs - divs. */ 6174fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 6175fcf5ef2aSThomas Huth { 6176fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6177fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6178efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6179fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6180fcf5ef2aSThomas Huth } 6181efe843d8SDavid Gibson } 6182fcf5ef2aSThomas Huth 6183fcf5ef2aSThomas Huth /* divso - divso. */ 6184fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 6185fcf5ef2aSThomas Huth { 6186fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 6187fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6188efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6189fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6190fcf5ef2aSThomas Huth } 6191efe843d8SDavid Gibson } 6192fcf5ef2aSThomas Huth 6193fcf5ef2aSThomas Huth /* doz - doz. */ 6194fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 6195fcf5ef2aSThomas Huth { 6196fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6197fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6198efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6199efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6200efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 6201efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 6202fcf5ef2aSThomas Huth tcg_gen_br(l2); 6203fcf5ef2aSThomas Huth gen_set_label(l1); 6204fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6205fcf5ef2aSThomas Huth gen_set_label(l2); 6206efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6207fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6208fcf5ef2aSThomas Huth } 6209efe843d8SDavid Gibson } 6210fcf5ef2aSThomas Huth 6211fcf5ef2aSThomas Huth /* dozo - dozo. */ 6212fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 6213fcf5ef2aSThomas Huth { 6214fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6215fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6216fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6217fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6218fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6219fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6220fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6221efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6222efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6223fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6224fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6225fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 6226fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6227fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 6228fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6229fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6230fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6231fcf5ef2aSThomas Huth tcg_gen_br(l2); 6232fcf5ef2aSThomas Huth gen_set_label(l1); 6233fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6234fcf5ef2aSThomas Huth gen_set_label(l2); 6235fcf5ef2aSThomas Huth tcg_temp_free(t0); 6236fcf5ef2aSThomas Huth tcg_temp_free(t1); 6237fcf5ef2aSThomas Huth tcg_temp_free(t2); 6238efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6239fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6240fcf5ef2aSThomas Huth } 6241efe843d8SDavid Gibson } 6242fcf5ef2aSThomas Huth 6243fcf5ef2aSThomas Huth /* dozi */ 6244fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 6245fcf5ef2aSThomas Huth { 6246fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 6247fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6248fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6249fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 6250fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 6251fcf5ef2aSThomas Huth tcg_gen_br(l2); 6252fcf5ef2aSThomas Huth gen_set_label(l1); 6253fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6254fcf5ef2aSThomas Huth gen_set_label(l2); 6255efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6256fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6257fcf5ef2aSThomas Huth } 6258efe843d8SDavid Gibson } 6259fcf5ef2aSThomas Huth 6260fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 6261fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 6262fcf5ef2aSThomas Huth { 6263fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6264fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 6265fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 6266fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 6267fcf5ef2aSThomas Huth 6268fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6269fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 6270fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6271fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 6272fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 6273fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 6274fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 6275efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6276fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 6277efe843d8SDavid Gibson } 6278fcf5ef2aSThomas Huth tcg_temp_free(t0); 6279fcf5ef2aSThomas Huth } 6280fcf5ef2aSThomas Huth 6281fcf5ef2aSThomas Huth /* maskg - maskg. */ 6282fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 6283fcf5ef2aSThomas Huth { 6284fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6285fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6286fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6287fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6288fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 6289fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 6290fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6291fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 6292fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 6293fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 6294fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 6295fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 6296fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 6297fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6298fcf5ef2aSThomas Huth gen_set_label(l1); 6299fcf5ef2aSThomas Huth tcg_temp_free(t0); 6300fcf5ef2aSThomas Huth tcg_temp_free(t1); 6301fcf5ef2aSThomas Huth tcg_temp_free(t2); 6302fcf5ef2aSThomas Huth tcg_temp_free(t3); 6303efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6304fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6305fcf5ef2aSThomas Huth } 6306efe843d8SDavid Gibson } 6307fcf5ef2aSThomas Huth 6308fcf5ef2aSThomas Huth /* maskir - maskir. */ 6309fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 6310fcf5ef2aSThomas Huth { 6311fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6312fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6313fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6314fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6315fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6316fcf5ef2aSThomas Huth tcg_temp_free(t0); 6317fcf5ef2aSThomas Huth tcg_temp_free(t1); 6318efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6319fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6320fcf5ef2aSThomas Huth } 6321efe843d8SDavid Gibson } 6322fcf5ef2aSThomas Huth 6323fcf5ef2aSThomas Huth /* mul - mul. */ 6324fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 6325fcf5ef2aSThomas Huth { 6326fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6327fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6328fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6329fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6330fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6331fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6332fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6333fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6334fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6335fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6336fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6337fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6338fcf5ef2aSThomas Huth tcg_temp_free(t2); 6339efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6340fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6341fcf5ef2aSThomas Huth } 6342efe843d8SDavid Gibson } 6343fcf5ef2aSThomas Huth 6344fcf5ef2aSThomas Huth /* mulo - mulo. */ 6345fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6346fcf5ef2aSThomas Huth { 6347fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6348fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6349fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6350fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6351fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6352fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6353fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6354fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6355fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6356fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6357fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6358fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6359fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6360fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6361fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6362fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6363fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6364fcf5ef2aSThomas Huth gen_set_label(l1); 6365fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6366fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6367fcf5ef2aSThomas Huth tcg_temp_free(t2); 6368efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6369fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6370fcf5ef2aSThomas Huth } 6371efe843d8SDavid Gibson } 6372fcf5ef2aSThomas Huth 6373fcf5ef2aSThomas Huth /* nabs - nabs. */ 6374fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6375fcf5ef2aSThomas Huth { 6376fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6377fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6378fe21b785SRichard Henderson 6379fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6380fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6381efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6382fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6383fcf5ef2aSThomas Huth } 6384efe843d8SDavid Gibson } 6385fcf5ef2aSThomas Huth 6386fcf5ef2aSThomas Huth /* nabso - nabso. */ 6387fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6388fcf5ef2aSThomas Huth { 6389fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6390fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6391fe21b785SRichard Henderson 6392fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6393fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6394fcf5ef2aSThomas Huth /* nabs never overflows */ 6395fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6396efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6397fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6398fcf5ef2aSThomas Huth } 6399efe843d8SDavid Gibson } 6400fcf5ef2aSThomas Huth 6401fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6402fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6403fcf5ef2aSThomas Huth { 6404fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6405fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6406fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6407fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6408fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6409fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6410efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6411efe843d8SDavid Gibson ~MASK(mb, me)); 6412fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6413fcf5ef2aSThomas Huth tcg_temp_free(t0); 6414efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6415fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6416fcf5ef2aSThomas Huth } 6417efe843d8SDavid Gibson } 6418fcf5ef2aSThomas Huth 6419fcf5ef2aSThomas Huth /* rrib - rrib. */ 6420fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6421fcf5ef2aSThomas Huth { 6422fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6423fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6424fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6425fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6426fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6427fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6428fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6429fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6430fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6431fcf5ef2aSThomas Huth tcg_temp_free(t0); 6432fcf5ef2aSThomas Huth tcg_temp_free(t1); 6433efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6434fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6435fcf5ef2aSThomas Huth } 6436efe843d8SDavid Gibson } 6437fcf5ef2aSThomas Huth 6438fcf5ef2aSThomas Huth /* sle - sle. */ 6439fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6440fcf5ef2aSThomas Huth { 6441fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6442fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6443fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6444fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6445fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6446fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6447fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6448fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6449fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6450fcf5ef2aSThomas Huth tcg_temp_free(t0); 6451fcf5ef2aSThomas Huth tcg_temp_free(t1); 6452efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6453fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6454fcf5ef2aSThomas Huth } 6455efe843d8SDavid Gibson } 6456fcf5ef2aSThomas Huth 6457fcf5ef2aSThomas Huth /* sleq - sleq. */ 6458fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6459fcf5ef2aSThomas Huth { 6460fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6461fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6462fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6463fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6464fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6465fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6466fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6467fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6468fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6469fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6470fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6471fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6472fcf5ef2aSThomas Huth tcg_temp_free(t0); 6473fcf5ef2aSThomas Huth tcg_temp_free(t1); 6474fcf5ef2aSThomas Huth tcg_temp_free(t2); 6475efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6476fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6477fcf5ef2aSThomas Huth } 6478efe843d8SDavid Gibson } 6479fcf5ef2aSThomas Huth 6480fcf5ef2aSThomas Huth /* sliq - sliq. */ 6481fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6482fcf5ef2aSThomas Huth { 6483fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6484fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6485fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6486fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6487fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6488fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6489fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6490fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6491fcf5ef2aSThomas Huth tcg_temp_free(t0); 6492fcf5ef2aSThomas Huth tcg_temp_free(t1); 6493efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6494fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6495fcf5ef2aSThomas Huth } 6496efe843d8SDavid Gibson } 6497fcf5ef2aSThomas Huth 6498fcf5ef2aSThomas Huth /* slliq - slliq. */ 6499fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6500fcf5ef2aSThomas Huth { 6501fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6502fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6503fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6504fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6505fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6506fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6507fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6508fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6509fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6510fcf5ef2aSThomas Huth tcg_temp_free(t0); 6511fcf5ef2aSThomas Huth tcg_temp_free(t1); 6512efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6513fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6514fcf5ef2aSThomas Huth } 6515efe843d8SDavid Gibson } 6516fcf5ef2aSThomas Huth 6517fcf5ef2aSThomas Huth /* sllq - sllq. */ 6518fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6519fcf5ef2aSThomas Huth { 6520fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6521fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6522fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6523fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6524fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6525fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6526fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6527fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6528fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6529fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6530fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6531fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6532fcf5ef2aSThomas Huth tcg_gen_br(l2); 6533fcf5ef2aSThomas Huth gen_set_label(l1); 6534fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6535fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6536fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6537fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6538fcf5ef2aSThomas Huth gen_set_label(l2); 6539fcf5ef2aSThomas Huth tcg_temp_free(t0); 6540fcf5ef2aSThomas Huth tcg_temp_free(t1); 6541fcf5ef2aSThomas Huth tcg_temp_free(t2); 6542efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6543fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6544fcf5ef2aSThomas Huth } 6545efe843d8SDavid Gibson } 6546fcf5ef2aSThomas Huth 6547fcf5ef2aSThomas Huth /* slq - slq. */ 6548fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6549fcf5ef2aSThomas Huth { 6550fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6551fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6552fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6553fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6554fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6555fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6556fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6557fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6558fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6559fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6560fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6561fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6562fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6563fcf5ef2aSThomas Huth gen_set_label(l1); 6564fcf5ef2aSThomas Huth tcg_temp_free(t0); 6565fcf5ef2aSThomas Huth tcg_temp_free(t1); 6566efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6567fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6568fcf5ef2aSThomas Huth } 6569efe843d8SDavid Gibson } 6570fcf5ef2aSThomas Huth 6571fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6572fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6573fcf5ef2aSThomas Huth { 6574fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6575fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6576fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6577fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6578fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6579fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6580fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6581fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6582fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6583fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6584fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6585fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6586fcf5ef2aSThomas Huth gen_set_label(l1); 6587fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6588fcf5ef2aSThomas Huth tcg_temp_free(t0); 6589fcf5ef2aSThomas Huth tcg_temp_free(t1); 6590efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6591fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6592fcf5ef2aSThomas Huth } 6593efe843d8SDavid Gibson } 6594fcf5ef2aSThomas Huth 6595fcf5ef2aSThomas Huth /* sraq - sraq. */ 6596fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6597fcf5ef2aSThomas Huth { 6598fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6599fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6600fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6601fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6602fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6603fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6604fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6605fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6606fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6607fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6608fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6609fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6610fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6611fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6612fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6613fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6614fcf5ef2aSThomas Huth gen_set_label(l1); 6615fcf5ef2aSThomas Huth tcg_temp_free(t0); 6616fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6617fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6618fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6619fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6620fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6621fcf5ef2aSThomas Huth gen_set_label(l2); 6622fcf5ef2aSThomas Huth tcg_temp_free(t1); 6623fcf5ef2aSThomas Huth tcg_temp_free(t2); 6624efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6625fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6626fcf5ef2aSThomas Huth } 6627efe843d8SDavid Gibson } 6628fcf5ef2aSThomas Huth 6629fcf5ef2aSThomas Huth /* sre - sre. */ 6630fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6631fcf5ef2aSThomas Huth { 6632fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6633fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6634fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6635fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6636fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6637fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6638fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6639fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6640fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6641fcf5ef2aSThomas Huth tcg_temp_free(t0); 6642fcf5ef2aSThomas Huth tcg_temp_free(t1); 6643efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6644fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6645fcf5ef2aSThomas Huth } 6646efe843d8SDavid Gibson } 6647fcf5ef2aSThomas Huth 6648fcf5ef2aSThomas Huth /* srea - srea. */ 6649fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6650fcf5ef2aSThomas Huth { 6651fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6652fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6653fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6654fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6655fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6656fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6657fcf5ef2aSThomas Huth tcg_temp_free(t0); 6658fcf5ef2aSThomas Huth tcg_temp_free(t1); 6659efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6660fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6661fcf5ef2aSThomas Huth } 6662efe843d8SDavid Gibson } 6663fcf5ef2aSThomas Huth 6664fcf5ef2aSThomas Huth /* sreq */ 6665fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6666fcf5ef2aSThomas Huth { 6667fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6668fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6669fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6670fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6671fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6672fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6673fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6674fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6675fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6676fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6677fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6678fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6679fcf5ef2aSThomas Huth tcg_temp_free(t0); 6680fcf5ef2aSThomas Huth tcg_temp_free(t1); 6681fcf5ef2aSThomas Huth tcg_temp_free(t2); 6682efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6683fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6684fcf5ef2aSThomas Huth } 6685efe843d8SDavid Gibson } 6686fcf5ef2aSThomas Huth 6687fcf5ef2aSThomas Huth /* sriq */ 6688fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6689fcf5ef2aSThomas Huth { 6690fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6691fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6692fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6693fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6694fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6695fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6696fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6697fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6698fcf5ef2aSThomas Huth tcg_temp_free(t0); 6699fcf5ef2aSThomas Huth tcg_temp_free(t1); 6700efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6701fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6702fcf5ef2aSThomas Huth } 6703efe843d8SDavid Gibson } 6704fcf5ef2aSThomas Huth 6705fcf5ef2aSThomas Huth /* srliq */ 6706fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6707fcf5ef2aSThomas Huth { 6708fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6709fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6710fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6711fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6712fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6713fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6714fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6715fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6716fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6717fcf5ef2aSThomas Huth tcg_temp_free(t0); 6718fcf5ef2aSThomas Huth tcg_temp_free(t1); 6719efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6720fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6721fcf5ef2aSThomas Huth } 6722efe843d8SDavid Gibson } 6723fcf5ef2aSThomas Huth 6724fcf5ef2aSThomas Huth /* srlq */ 6725fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6726fcf5ef2aSThomas Huth { 6727fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6728fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6729fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6730fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6731fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6732fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6733fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6734fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6735fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6736fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6737fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6738fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6739fcf5ef2aSThomas Huth tcg_gen_br(l2); 6740fcf5ef2aSThomas Huth gen_set_label(l1); 6741fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6742fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6743fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6744fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6745fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6746fcf5ef2aSThomas Huth gen_set_label(l2); 6747fcf5ef2aSThomas Huth tcg_temp_free(t0); 6748fcf5ef2aSThomas Huth tcg_temp_free(t1); 6749fcf5ef2aSThomas Huth tcg_temp_free(t2); 6750efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6751fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6752fcf5ef2aSThomas Huth } 6753efe843d8SDavid Gibson } 6754fcf5ef2aSThomas Huth 6755fcf5ef2aSThomas Huth /* srq */ 6756fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6757fcf5ef2aSThomas Huth { 6758fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6759fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6760fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6761fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6762fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6763fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6764fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6765fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6766fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6767fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6768fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6769fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6770fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6771fcf5ef2aSThomas Huth gen_set_label(l1); 6772fcf5ef2aSThomas Huth tcg_temp_free(t0); 6773fcf5ef2aSThomas Huth tcg_temp_free(t1); 6774efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6775fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6776fcf5ef2aSThomas Huth } 6777efe843d8SDavid Gibson } 6778fcf5ef2aSThomas Huth 6779fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6780fcf5ef2aSThomas Huth 6781fcf5ef2aSThomas Huth /* dsa */ 6782fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6783fcf5ef2aSThomas Huth { 6784fcf5ef2aSThomas Huth /* XXX: TODO */ 6785fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6786fcf5ef2aSThomas Huth } 6787fcf5ef2aSThomas Huth 6788fcf5ef2aSThomas Huth /* esa */ 6789fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6790fcf5ef2aSThomas Huth { 6791fcf5ef2aSThomas Huth /* XXX: TODO */ 6792fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6793fcf5ef2aSThomas Huth } 6794fcf5ef2aSThomas Huth 6795fcf5ef2aSThomas Huth /* mfrom */ 6796fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6797fcf5ef2aSThomas Huth { 6798fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6799fcf5ef2aSThomas Huth GEN_PRIV; 6800fcf5ef2aSThomas Huth #else 6801fcf5ef2aSThomas Huth CHK_SV; 6802fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6803fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6804fcf5ef2aSThomas Huth } 6805fcf5ef2aSThomas Huth 6806fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6807fcf5ef2aSThomas Huth 6808fcf5ef2aSThomas Huth /* tlbld */ 6809fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6810fcf5ef2aSThomas Huth { 6811fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6812fcf5ef2aSThomas Huth GEN_PRIV; 6813fcf5ef2aSThomas Huth #else 6814fcf5ef2aSThomas Huth CHK_SV; 6815fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6816fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6817fcf5ef2aSThomas Huth } 6818fcf5ef2aSThomas Huth 6819fcf5ef2aSThomas Huth /* tlbli */ 6820fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6821fcf5ef2aSThomas Huth { 6822fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6823fcf5ef2aSThomas Huth GEN_PRIV; 6824fcf5ef2aSThomas Huth #else 6825fcf5ef2aSThomas Huth CHK_SV; 6826fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6827fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6828fcf5ef2aSThomas Huth } 6829fcf5ef2aSThomas Huth 6830fcf5ef2aSThomas Huth /* 74xx TLB management */ 6831fcf5ef2aSThomas Huth 6832fcf5ef2aSThomas Huth /* tlbld */ 6833fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6834fcf5ef2aSThomas Huth { 6835fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6836fcf5ef2aSThomas Huth GEN_PRIV; 6837fcf5ef2aSThomas Huth #else 6838fcf5ef2aSThomas Huth CHK_SV; 6839fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6840fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6841fcf5ef2aSThomas Huth } 6842fcf5ef2aSThomas Huth 6843fcf5ef2aSThomas Huth /* tlbli */ 6844fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6845fcf5ef2aSThomas Huth { 6846fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6847fcf5ef2aSThomas Huth GEN_PRIV; 6848fcf5ef2aSThomas Huth #else 6849fcf5ef2aSThomas Huth CHK_SV; 6850fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6851fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6852fcf5ef2aSThomas Huth } 6853fcf5ef2aSThomas Huth 6854fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6855fcf5ef2aSThomas Huth 6856fcf5ef2aSThomas Huth /* clf */ 6857fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6858fcf5ef2aSThomas Huth { 6859fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6860fcf5ef2aSThomas Huth } 6861fcf5ef2aSThomas Huth 6862fcf5ef2aSThomas Huth /* cli */ 6863fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6864fcf5ef2aSThomas Huth { 6865fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6866fcf5ef2aSThomas Huth GEN_PRIV; 6867fcf5ef2aSThomas Huth #else 6868fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6869fcf5ef2aSThomas Huth CHK_SV; 6870fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6871fcf5ef2aSThomas Huth } 6872fcf5ef2aSThomas Huth 6873fcf5ef2aSThomas Huth /* dclst */ 6874fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6875fcf5ef2aSThomas Huth { 6876fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6877fcf5ef2aSThomas Huth } 6878fcf5ef2aSThomas Huth 6879fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6880fcf5ef2aSThomas Huth { 6881fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6882fcf5ef2aSThomas Huth GEN_PRIV; 6883fcf5ef2aSThomas Huth #else 6884fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6885fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6886fcf5ef2aSThomas Huth TCGv t0; 6887fcf5ef2aSThomas Huth 6888fcf5ef2aSThomas Huth CHK_SV; 6889fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6890fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6891e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6892fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6893fcf5ef2aSThomas Huth tcg_temp_free(t0); 6894efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6895fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6896efe843d8SDavid Gibson } 6897fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6898fcf5ef2aSThomas Huth } 6899fcf5ef2aSThomas Huth 6900fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6901fcf5ef2aSThomas Huth { 6902fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6903fcf5ef2aSThomas Huth GEN_PRIV; 6904fcf5ef2aSThomas Huth #else 6905fcf5ef2aSThomas Huth TCGv t0; 6906fcf5ef2aSThomas Huth 6907fcf5ef2aSThomas Huth CHK_SV; 6908fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6909fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6910fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6911fcf5ef2aSThomas Huth tcg_temp_free(t0); 6912fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6913fcf5ef2aSThomas Huth } 6914fcf5ef2aSThomas Huth 6915fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6916fcf5ef2aSThomas Huth { 6917fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6918fcf5ef2aSThomas Huth GEN_PRIV; 6919fcf5ef2aSThomas Huth #else 6920fcf5ef2aSThomas Huth CHK_SV; 6921fcf5ef2aSThomas Huth 6922fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 6923fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6924fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6925fcf5ef2aSThomas Huth } 6926fcf5ef2aSThomas Huth 6927fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6928fcf5ef2aSThomas Huth 6929fcf5ef2aSThomas Huth /* BookE specific instructions */ 6930fcf5ef2aSThomas Huth 6931fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6932fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6933fcf5ef2aSThomas Huth { 6934fcf5ef2aSThomas Huth /* XXX: TODO */ 6935fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6936fcf5ef2aSThomas Huth } 6937fcf5ef2aSThomas Huth 6938fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6939fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6940fcf5ef2aSThomas Huth { 6941fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6942fcf5ef2aSThomas Huth GEN_PRIV; 6943fcf5ef2aSThomas Huth #else 6944fcf5ef2aSThomas Huth TCGv t0; 6945fcf5ef2aSThomas Huth 6946fcf5ef2aSThomas Huth CHK_SV; 6947fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6948fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6949fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6950fcf5ef2aSThomas Huth tcg_temp_free(t0); 6951fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6952fcf5ef2aSThomas Huth } 6953fcf5ef2aSThomas Huth 6954fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6955fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6956fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6957fcf5ef2aSThomas Huth { 6958fcf5ef2aSThomas Huth TCGv t0, t1; 6959fcf5ef2aSThomas Huth 6960fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6961fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6962fcf5ef2aSThomas Huth 6963fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6964fcf5ef2aSThomas Huth case 0x05: 6965fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6966fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6967fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6968fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6969fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6970fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6971fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6972fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6973fcf5ef2aSThomas Huth break; 6974fcf5ef2aSThomas Huth case 0x04: 6975fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6976fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6977fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6978fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6979fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6980fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6981fcf5ef2aSThomas Huth break; 6982fcf5ef2aSThomas Huth case 0x01: 6983fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6984fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6985fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6986fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6987fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6988fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6989fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6990fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6991fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6992fcf5ef2aSThomas Huth break; 6993fcf5ef2aSThomas Huth case 0x00: 6994fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6995fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6996fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6997fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6998fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6999fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 7000fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 7001fcf5ef2aSThomas Huth break; 7002fcf5ef2aSThomas Huth case 0x0D: 7003fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 7004fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 7005fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 7006fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 7007fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7008fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 7009fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 7010fcf5ef2aSThomas Huth break; 7011fcf5ef2aSThomas Huth case 0x0C: 7012fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 7013fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 7014fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7015fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 7016fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 7017fcf5ef2aSThomas Huth break; 7018fcf5ef2aSThomas Huth } 7019fcf5ef2aSThomas Huth if (opc2 & 0x04) { 7020fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 7021fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 7022fcf5ef2aSThomas Huth if (opc2 & 0x02) { 7023fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 7024fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 7025fcf5ef2aSThomas Huth } else { 7026fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 7027fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 7028fcf5ef2aSThomas Huth } 7029fcf5ef2aSThomas Huth 7030fcf5ef2aSThomas Huth if (opc3 & 0x12) { 7031fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 7032fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7033fcf5ef2aSThomas Huth 7034fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7035fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 7036fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 7037fcf5ef2aSThomas Huth } 7038fcf5ef2aSThomas Huth if (opc3 & 0x01) { 7039fcf5ef2aSThomas Huth /* Signed */ 7040fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 7041fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 7042fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 7043fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 7044fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7045fcf5ef2aSThomas Huth /* Saturate */ 7046fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 7047fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 7048fcf5ef2aSThomas Huth } 7049fcf5ef2aSThomas Huth } else { 7050fcf5ef2aSThomas Huth /* Unsigned */ 7051fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 7052fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7053fcf5ef2aSThomas Huth /* Saturate */ 7054fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 7055fcf5ef2aSThomas Huth } 7056fcf5ef2aSThomas Huth } 7057fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7058fcf5ef2aSThomas Huth /* Check overflow */ 7059fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 7060fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 7061fcf5ef2aSThomas Huth } 7062fcf5ef2aSThomas Huth gen_set_label(l1); 7063fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 7064fcf5ef2aSThomas Huth } 7065fcf5ef2aSThomas Huth } else { 7066fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 7067fcf5ef2aSThomas Huth } 7068fcf5ef2aSThomas Huth tcg_temp_free(t0); 7069fcf5ef2aSThomas Huth tcg_temp_free(t1); 7070fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 7071fcf5ef2aSThomas Huth /* Update Rc0 */ 7072fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 7073fcf5ef2aSThomas Huth } 7074fcf5ef2aSThomas Huth } 7075fcf5ef2aSThomas Huth 7076fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7077fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 7078fcf5ef2aSThomas Huth { \ 7079fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 7080fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 7081fcf5ef2aSThomas Huth } 7082fcf5ef2aSThomas Huth 7083fcf5ef2aSThomas Huth /* macchw - macchw. */ 7084fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 7085fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 7086fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 7087fcf5ef2aSThomas Huth /* macchws - macchws. */ 7088fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 7089fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 7090fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 7091fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 7092fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 7093fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 7094fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 7095fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 7096fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 7097fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 7098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 7099fcf5ef2aSThomas Huth /* machhw - machhw. */ 7100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 7101fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 7102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 7103fcf5ef2aSThomas Huth /* machhws - machhws. */ 7104fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 7105fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 7106fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 7107fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 7108fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 7109fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 7110fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 7111fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 7112fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 7113fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 7114fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 7115fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 7116fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 7117fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 7118fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 7119fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 7120fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 7121fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 7122fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 7123fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 7124fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 7125fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 7126fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 7127fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 7128fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 7129fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 7130fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 7131fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 7132fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 7133fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 7134fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 7135fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 7136fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 7137fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 7138fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 7139fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 7140fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 7141fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 7142fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 7143fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 7144fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 7145fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 7146fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 7147fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 7148fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 7149fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 7150fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 7151fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 7152fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 7153fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 7154fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 7155fcf5ef2aSThomas Huth 7156fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 7157fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 7158fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 7159fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 7160fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 7161fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 7162fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7163fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 7164fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7165fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 7166fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7167fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 7168fcf5ef2aSThomas Huth 7169fcf5ef2aSThomas Huth /* mfdcr */ 7170fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 7171fcf5ef2aSThomas Huth { 7172fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7173fcf5ef2aSThomas Huth GEN_PRIV; 7174fcf5ef2aSThomas Huth #else 7175fcf5ef2aSThomas Huth TCGv dcrn; 7176fcf5ef2aSThomas Huth 7177fcf5ef2aSThomas Huth CHK_SV; 7178fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7179fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 7180fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7181fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7182fcf5ef2aSThomas Huth } 7183fcf5ef2aSThomas Huth 7184fcf5ef2aSThomas Huth /* mtdcr */ 7185fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 7186fcf5ef2aSThomas Huth { 7187fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7188fcf5ef2aSThomas Huth GEN_PRIV; 7189fcf5ef2aSThomas Huth #else 7190fcf5ef2aSThomas Huth TCGv dcrn; 7191fcf5ef2aSThomas Huth 7192fcf5ef2aSThomas Huth CHK_SV; 7193fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7194fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 7195fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7196fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7197fcf5ef2aSThomas Huth } 7198fcf5ef2aSThomas Huth 7199fcf5ef2aSThomas Huth /* mfdcrx */ 7200fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7201fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 7202fcf5ef2aSThomas Huth { 7203fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7204fcf5ef2aSThomas Huth GEN_PRIV; 7205fcf5ef2aSThomas Huth #else 7206fcf5ef2aSThomas Huth CHK_SV; 7207fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7208fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7209fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7210fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7211fcf5ef2aSThomas Huth } 7212fcf5ef2aSThomas Huth 7213fcf5ef2aSThomas Huth /* mtdcrx */ 7214fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7215fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 7216fcf5ef2aSThomas Huth { 7217fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7218fcf5ef2aSThomas Huth GEN_PRIV; 7219fcf5ef2aSThomas Huth #else 7220fcf5ef2aSThomas Huth CHK_SV; 7221fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7222fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7223fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7224fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7225fcf5ef2aSThomas Huth } 7226fcf5ef2aSThomas Huth 7227fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 7228fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 7229fcf5ef2aSThomas Huth { 7230fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7231fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7232fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7233fcf5ef2aSThomas Huth } 7234fcf5ef2aSThomas Huth 7235fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 7236fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 7237fcf5ef2aSThomas Huth { 7238fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7239fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7240fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7241fcf5ef2aSThomas Huth } 7242fcf5ef2aSThomas Huth 7243fcf5ef2aSThomas Huth /* dccci */ 7244fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 7245fcf5ef2aSThomas Huth { 7246fcf5ef2aSThomas Huth CHK_SV; 7247fcf5ef2aSThomas Huth /* interpreted as no-op */ 7248fcf5ef2aSThomas Huth } 7249fcf5ef2aSThomas Huth 7250fcf5ef2aSThomas Huth /* dcread */ 7251fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 7252fcf5ef2aSThomas Huth { 7253fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7254fcf5ef2aSThomas Huth GEN_PRIV; 7255fcf5ef2aSThomas Huth #else 7256fcf5ef2aSThomas Huth TCGv EA, val; 7257fcf5ef2aSThomas Huth 7258fcf5ef2aSThomas Huth CHK_SV; 7259fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 7260fcf5ef2aSThomas Huth EA = tcg_temp_new(); 7261fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 7262fcf5ef2aSThomas Huth val = tcg_temp_new(); 7263fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 7264fcf5ef2aSThomas Huth tcg_temp_free(val); 7265fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 7266fcf5ef2aSThomas Huth tcg_temp_free(EA); 7267fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7268fcf5ef2aSThomas Huth } 7269fcf5ef2aSThomas Huth 7270fcf5ef2aSThomas Huth /* icbt */ 7271fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 7272fcf5ef2aSThomas Huth { 7273efe843d8SDavid Gibson /* 7274efe843d8SDavid Gibson * interpreted as no-op 7275efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7276efe843d8SDavid Gibson * does not generate any exception 7277fcf5ef2aSThomas Huth */ 7278fcf5ef2aSThomas Huth } 7279fcf5ef2aSThomas Huth 7280fcf5ef2aSThomas Huth /* iccci */ 7281fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 7282fcf5ef2aSThomas Huth { 7283fcf5ef2aSThomas Huth CHK_SV; 7284fcf5ef2aSThomas Huth /* interpreted as no-op */ 7285fcf5ef2aSThomas Huth } 7286fcf5ef2aSThomas Huth 7287fcf5ef2aSThomas Huth /* icread */ 7288fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 7289fcf5ef2aSThomas Huth { 7290fcf5ef2aSThomas Huth CHK_SV; 7291fcf5ef2aSThomas Huth /* interpreted as no-op */ 7292fcf5ef2aSThomas Huth } 7293fcf5ef2aSThomas Huth 7294fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 7295fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 7296fcf5ef2aSThomas Huth { 7297fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7298fcf5ef2aSThomas Huth GEN_PRIV; 7299fcf5ef2aSThomas Huth #else 7300fcf5ef2aSThomas Huth CHK_SV; 7301fcf5ef2aSThomas Huth /* Restore CPU state */ 7302fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 7303fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7304fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7305fcf5ef2aSThomas Huth } 7306fcf5ef2aSThomas Huth 7307fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 7308fcf5ef2aSThomas Huth { 7309fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7310fcf5ef2aSThomas Huth GEN_PRIV; 7311fcf5ef2aSThomas Huth #else 7312fcf5ef2aSThomas Huth CHK_SV; 7313fcf5ef2aSThomas Huth /* Restore CPU state */ 7314fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 7315fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7316fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7317fcf5ef2aSThomas Huth } 7318fcf5ef2aSThomas Huth 7319fcf5ef2aSThomas Huth /* BookE specific */ 7320fcf5ef2aSThomas Huth 7321fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7322fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 7323fcf5ef2aSThomas Huth { 7324fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7325fcf5ef2aSThomas Huth GEN_PRIV; 7326fcf5ef2aSThomas Huth #else 7327fcf5ef2aSThomas Huth CHK_SV; 7328fcf5ef2aSThomas Huth /* Restore CPU state */ 7329fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 7330fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7331fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7332fcf5ef2aSThomas Huth } 7333fcf5ef2aSThomas Huth 7334fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7335fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 7336fcf5ef2aSThomas Huth { 7337fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7338fcf5ef2aSThomas Huth GEN_PRIV; 7339fcf5ef2aSThomas Huth #else 7340fcf5ef2aSThomas Huth CHK_SV; 7341fcf5ef2aSThomas Huth /* Restore CPU state */ 7342fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 7343fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7344fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7345fcf5ef2aSThomas Huth } 7346fcf5ef2aSThomas Huth 7347fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7348fcf5ef2aSThomas Huth 7349fcf5ef2aSThomas Huth /* tlbre */ 7350fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7351fcf5ef2aSThomas Huth { 7352fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7353fcf5ef2aSThomas Huth GEN_PRIV; 7354fcf5ef2aSThomas Huth #else 7355fcf5ef2aSThomas Huth CHK_SV; 7356fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7357fcf5ef2aSThomas Huth case 0: 7358fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7359fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7360fcf5ef2aSThomas Huth break; 7361fcf5ef2aSThomas Huth case 1: 7362fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7363fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7364fcf5ef2aSThomas Huth break; 7365fcf5ef2aSThomas Huth default: 7366fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7367fcf5ef2aSThomas Huth break; 7368fcf5ef2aSThomas Huth } 7369fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7370fcf5ef2aSThomas Huth } 7371fcf5ef2aSThomas Huth 7372fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7373fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7374fcf5ef2aSThomas Huth { 7375fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7376fcf5ef2aSThomas Huth GEN_PRIV; 7377fcf5ef2aSThomas Huth #else 7378fcf5ef2aSThomas Huth TCGv t0; 7379fcf5ef2aSThomas Huth 7380fcf5ef2aSThomas Huth CHK_SV; 7381fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7382fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7383fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7384fcf5ef2aSThomas Huth tcg_temp_free(t0); 7385fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7386fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7387fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7388fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7389fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7390fcf5ef2aSThomas Huth gen_set_label(l1); 7391fcf5ef2aSThomas Huth } 7392fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7393fcf5ef2aSThomas Huth } 7394fcf5ef2aSThomas Huth 7395fcf5ef2aSThomas Huth /* tlbwe */ 7396fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7397fcf5ef2aSThomas Huth { 7398fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7399fcf5ef2aSThomas Huth GEN_PRIV; 7400fcf5ef2aSThomas Huth #else 7401fcf5ef2aSThomas Huth CHK_SV; 7402fcf5ef2aSThomas Huth 7403fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7404fcf5ef2aSThomas Huth case 0: 7405fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7406fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7407fcf5ef2aSThomas Huth break; 7408fcf5ef2aSThomas Huth case 1: 7409fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7410fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7411fcf5ef2aSThomas Huth break; 7412fcf5ef2aSThomas Huth default: 7413fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7414fcf5ef2aSThomas Huth break; 7415fcf5ef2aSThomas Huth } 7416fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7417fcf5ef2aSThomas Huth } 7418fcf5ef2aSThomas Huth 7419fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7420fcf5ef2aSThomas Huth 7421fcf5ef2aSThomas Huth /* tlbre */ 7422fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7423fcf5ef2aSThomas Huth { 7424fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7425fcf5ef2aSThomas Huth GEN_PRIV; 7426fcf5ef2aSThomas Huth #else 7427fcf5ef2aSThomas Huth CHK_SV; 7428fcf5ef2aSThomas Huth 7429fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7430fcf5ef2aSThomas Huth case 0: 7431fcf5ef2aSThomas Huth case 1: 7432fcf5ef2aSThomas Huth case 2: 7433fcf5ef2aSThomas Huth { 7434fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7435fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7436fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7437fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7438fcf5ef2aSThomas Huth } 7439fcf5ef2aSThomas Huth break; 7440fcf5ef2aSThomas Huth default: 7441fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7442fcf5ef2aSThomas Huth break; 7443fcf5ef2aSThomas Huth } 7444fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7445fcf5ef2aSThomas Huth } 7446fcf5ef2aSThomas Huth 7447fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7448fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7449fcf5ef2aSThomas Huth { 7450fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7451fcf5ef2aSThomas Huth GEN_PRIV; 7452fcf5ef2aSThomas Huth #else 7453fcf5ef2aSThomas Huth TCGv t0; 7454fcf5ef2aSThomas Huth 7455fcf5ef2aSThomas Huth CHK_SV; 7456fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7457fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7458fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7459fcf5ef2aSThomas Huth tcg_temp_free(t0); 7460fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7461fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7462fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7463fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7464fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7465fcf5ef2aSThomas Huth gen_set_label(l1); 7466fcf5ef2aSThomas Huth } 7467fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7468fcf5ef2aSThomas Huth } 7469fcf5ef2aSThomas Huth 7470fcf5ef2aSThomas Huth /* tlbwe */ 7471fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7472fcf5ef2aSThomas Huth { 7473fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7474fcf5ef2aSThomas Huth GEN_PRIV; 7475fcf5ef2aSThomas Huth #else 7476fcf5ef2aSThomas Huth CHK_SV; 7477fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7478fcf5ef2aSThomas Huth case 0: 7479fcf5ef2aSThomas Huth case 1: 7480fcf5ef2aSThomas Huth case 2: 7481fcf5ef2aSThomas Huth { 7482fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7483fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7484fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7485fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7486fcf5ef2aSThomas Huth } 7487fcf5ef2aSThomas Huth break; 7488fcf5ef2aSThomas Huth default: 7489fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7490fcf5ef2aSThomas Huth break; 7491fcf5ef2aSThomas Huth } 7492fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7493fcf5ef2aSThomas Huth } 7494fcf5ef2aSThomas Huth 7495fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7496fcf5ef2aSThomas Huth 7497fcf5ef2aSThomas Huth /* tlbre */ 7498fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7499fcf5ef2aSThomas Huth { 7500fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7501fcf5ef2aSThomas Huth GEN_PRIV; 7502fcf5ef2aSThomas Huth #else 7503fcf5ef2aSThomas Huth CHK_SV; 7504fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7505fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7506fcf5ef2aSThomas Huth } 7507fcf5ef2aSThomas Huth 7508fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7509fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7510fcf5ef2aSThomas Huth { 7511fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7512fcf5ef2aSThomas Huth GEN_PRIV; 7513fcf5ef2aSThomas Huth #else 7514fcf5ef2aSThomas Huth TCGv t0; 7515fcf5ef2aSThomas Huth 7516fcf5ef2aSThomas Huth CHK_SV; 7517fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7518fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7519fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7520fcf5ef2aSThomas Huth } else { 7521fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7522fcf5ef2aSThomas Huth } 7523fcf5ef2aSThomas Huth 7524fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7525fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7526fcf5ef2aSThomas Huth tcg_temp_free(t0); 7527fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7528fcf5ef2aSThomas Huth } 7529fcf5ef2aSThomas Huth 7530fcf5ef2aSThomas Huth /* tlbwe */ 7531fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7532fcf5ef2aSThomas Huth { 7533fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7534fcf5ef2aSThomas Huth GEN_PRIV; 7535fcf5ef2aSThomas Huth #else 7536fcf5ef2aSThomas Huth CHK_SV; 7537fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7538fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7539fcf5ef2aSThomas Huth } 7540fcf5ef2aSThomas Huth 7541fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7542fcf5ef2aSThomas Huth { 7543fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7544fcf5ef2aSThomas Huth GEN_PRIV; 7545fcf5ef2aSThomas Huth #else 7546fcf5ef2aSThomas Huth TCGv t0; 7547fcf5ef2aSThomas Huth 7548fcf5ef2aSThomas Huth CHK_SV; 7549fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7550fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7551fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7552fcf5ef2aSThomas Huth tcg_temp_free(t0); 7553fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7554fcf5ef2aSThomas Huth } 7555fcf5ef2aSThomas Huth 7556fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7557fcf5ef2aSThomas Huth { 7558fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7559fcf5ef2aSThomas Huth GEN_PRIV; 7560fcf5ef2aSThomas Huth #else 7561fcf5ef2aSThomas Huth TCGv t0; 7562fcf5ef2aSThomas Huth 7563fcf5ef2aSThomas Huth CHK_SV; 7564fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7565fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7566fcf5ef2aSThomas Huth 7567fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7568fcf5ef2aSThomas Huth case 0: 7569fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7570fcf5ef2aSThomas Huth break; 7571fcf5ef2aSThomas Huth case 1: 7572fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7573fcf5ef2aSThomas Huth break; 7574fcf5ef2aSThomas Huth case 3: 7575fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7576fcf5ef2aSThomas Huth break; 7577fcf5ef2aSThomas Huth default: 7578fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7579fcf5ef2aSThomas Huth break; 7580fcf5ef2aSThomas Huth } 7581fcf5ef2aSThomas Huth 7582fcf5ef2aSThomas Huth tcg_temp_free(t0); 7583fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7584fcf5ef2aSThomas Huth } 7585fcf5ef2aSThomas Huth 7586fcf5ef2aSThomas Huth 7587fcf5ef2aSThomas Huth /* wrtee */ 7588fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7589fcf5ef2aSThomas Huth { 7590fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7591fcf5ef2aSThomas Huth GEN_PRIV; 7592fcf5ef2aSThomas Huth #else 7593fcf5ef2aSThomas Huth TCGv t0; 7594fcf5ef2aSThomas Huth 7595fcf5ef2aSThomas Huth CHK_SV; 7596fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7597fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7598fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7599fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7600fcf5ef2aSThomas Huth tcg_temp_free(t0); 7601efe843d8SDavid Gibson /* 7602efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7603efe843d8SDavid Gibson * just set msr_ee to 1 7604fcf5ef2aSThomas Huth */ 7605fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7606fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7607fcf5ef2aSThomas Huth } 7608fcf5ef2aSThomas Huth 7609fcf5ef2aSThomas Huth /* wrteei */ 7610fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7611fcf5ef2aSThomas Huth { 7612fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7613fcf5ef2aSThomas Huth GEN_PRIV; 7614fcf5ef2aSThomas Huth #else 7615fcf5ef2aSThomas Huth CHK_SV; 7616fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7617fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7618fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7619fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7620fcf5ef2aSThomas Huth } else { 7621fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7622fcf5ef2aSThomas Huth } 7623fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7624fcf5ef2aSThomas Huth } 7625fcf5ef2aSThomas Huth 7626fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7627fcf5ef2aSThomas Huth 7628fcf5ef2aSThomas Huth /* dlmzb */ 7629fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7630fcf5ef2aSThomas Huth { 7631fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7632fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7633fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7634fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7635fcf5ef2aSThomas Huth } 7636fcf5ef2aSThomas Huth 7637fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7638fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7639fcf5ef2aSThomas Huth { 7640fcf5ef2aSThomas Huth /* interpreted as no-op */ 7641fcf5ef2aSThomas Huth } 7642fcf5ef2aSThomas Huth 7643fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7644fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7645fcf5ef2aSThomas Huth { 764627a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 764727a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 764827a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 764927a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 765027a3ea7eSBALATON Zoltan } 765127a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7652fcf5ef2aSThomas Huth } 7653fcf5ef2aSThomas Huth 7654fcf5ef2aSThomas Huth /* icbt */ 7655fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7656fcf5ef2aSThomas Huth { 7657efe843d8SDavid Gibson /* 7658efe843d8SDavid Gibson * interpreted as no-op 7659efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7660efe843d8SDavid Gibson * does not generate any exception 7661fcf5ef2aSThomas Huth */ 7662fcf5ef2aSThomas Huth } 7663fcf5ef2aSThomas Huth 7664fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7665fcf5ef2aSThomas Huth 7666fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7667fcf5ef2aSThomas Huth { 7668fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7669fcf5ef2aSThomas Huth GEN_PRIV; 7670fcf5ef2aSThomas Huth #else 7671ebca5e6dSCédric Le Goater CHK_HV; 7672d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76737af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76747af1e7b0SCédric Le Goater } else { 7675fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76767af1e7b0SCédric Le Goater } 7677fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7678fcf5ef2aSThomas Huth } 7679fcf5ef2aSThomas Huth 7680fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7681fcf5ef2aSThomas Huth { 7682fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7683fcf5ef2aSThomas Huth GEN_PRIV; 7684fcf5ef2aSThomas Huth #else 7685ebca5e6dSCédric Le Goater CHK_HV; 7686d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76877af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76887af1e7b0SCédric Le Goater } else { 7689fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76907af1e7b0SCédric Le Goater } 7691fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7692fcf5ef2aSThomas Huth } 7693fcf5ef2aSThomas Huth 76945ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 76955ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 76965ba7ba1dSCédric Le Goater { 76975ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 76985ba7ba1dSCédric Le Goater GEN_PRIV; 76995ba7ba1dSCédric Le Goater #else 77005ba7ba1dSCédric Le Goater CHK_SV; 77015ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77025ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77035ba7ba1dSCédric Le Goater } 77045ba7ba1dSCédric Le Goater 77055ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 77065ba7ba1dSCédric Le Goater { 77075ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 77085ba7ba1dSCédric Le Goater GEN_PRIV; 77095ba7ba1dSCédric Le Goater #else 77105ba7ba1dSCédric Le Goater CHK_SV; 77115ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77125ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77135ba7ba1dSCédric Le Goater } 77145ba7ba1dSCédric Le Goater #endif 77155ba7ba1dSCédric Le Goater 77167af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 77177af1e7b0SCédric Le Goater { 77187af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 77197af1e7b0SCédric Le Goater GEN_PRIV; 77207af1e7b0SCédric Le Goater #else 77217af1e7b0SCédric Le Goater CHK_HV; 77227af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77237af1e7b0SCédric Le Goater /* interpreted as no-op */ 77247af1e7b0SCédric Le Goater } 7725fcf5ef2aSThomas Huth 7726fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7727fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7728fcf5ef2aSThomas Huth { 7729fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7730fcf5ef2aSThomas Huth 7731fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7732fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7733fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7734fcf5ef2aSThomas Huth } 7735fcf5ef2aSThomas Huth 7736fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7737fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7738fcf5ef2aSThomas Huth { 7739fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7740fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7741fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7742fcf5ef2aSThomas Huth 7743fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7744fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7745fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7746fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7747fcf5ef2aSThomas Huth } else { 7748fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7749fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7750fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7751fcf5ef2aSThomas Huth } 7752fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7753fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7754fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7755fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7756fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7757fcf5ef2aSThomas Huth } 7758fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7759fcf5ef2aSThomas Huth 7760fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7761fcf5ef2aSThomas Huth { 7762fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7763fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7764fcf5ef2aSThomas Huth return; 7765fcf5ef2aSThomas Huth } 7766fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7767fcf5ef2aSThomas Huth } 7768fcf5ef2aSThomas Huth 7769fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7770fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7771fcf5ef2aSThomas Huth { \ 7772fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7773fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7774fcf5ef2aSThomas Huth return; \ 7775fcf5ef2aSThomas Huth } \ 7776efe843d8SDavid Gibson /* \ 7777efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7778fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7779fcf5ef2aSThomas Huth * \ 7780fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7781fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7782fcf5ef2aSThomas Huth */ \ 7783fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7784fcf5ef2aSThomas Huth } 7785fcf5ef2aSThomas Huth 7786fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7787fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7788fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7789fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7790fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7791fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7792fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7793efe843d8SDavid Gibson 7794b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7795b8b4576eSSuraj Jitindar Singh { 7796efe843d8SDavid Gibson /* Do Nothing */ 7797b8b4576eSSuraj Jitindar Singh } 7798fcf5ef2aSThomas Huth 779980b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 780080b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 780180b8c1eeSNikunj A Dadhania { \ 7802efe843d8SDavid Gibson /* \ 7803efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7804efe843d8SDavid Gibson * implementation of the copy paste facility \ 780580b8c1eeSNikunj A Dadhania */ \ 780680b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 780780b8c1eeSNikunj A Dadhania } 780880b8c1eeSNikunj A Dadhania 780980b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 781080b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 781180b8c1eeSNikunj A Dadhania 7812fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7813fcf5ef2aSThomas Huth { 7814fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7815fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7816fcf5ef2aSThomas Huth return; 7817fcf5ef2aSThomas Huth } 7818efe843d8SDavid Gibson /* 7819efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7820efe843d8SDavid Gibson * simple: 7821fcf5ef2aSThomas Huth * 7822fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7823fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7824fcf5ef2aSThomas Huth */ 7825fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7826fcf5ef2aSThomas Huth } 7827fcf5ef2aSThomas Huth 7828fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7829fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7830fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7831fcf5ef2aSThomas Huth { \ 7832fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7833fcf5ef2aSThomas Huth } 7834fcf5ef2aSThomas Huth 7835fcf5ef2aSThomas Huth #else 7836fcf5ef2aSThomas Huth 7837fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7838fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7839fcf5ef2aSThomas Huth { \ 7840fcf5ef2aSThomas Huth CHK_SV; \ 7841fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7842fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7843fcf5ef2aSThomas Huth return; \ 7844fcf5ef2aSThomas Huth } \ 7845efe843d8SDavid Gibson /* \ 7846efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7847fcf5ef2aSThomas Huth * simple: \ 7848fcf5ef2aSThomas Huth * \ 7849fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7850fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7851fcf5ef2aSThomas Huth */ \ 7852fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7853fcf5ef2aSThomas Huth } 7854fcf5ef2aSThomas Huth 7855fcf5ef2aSThomas Huth #endif 7856fcf5ef2aSThomas Huth 7857fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7858fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7859fcf5ef2aSThomas Huth 78601a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 78611a404c91SMark Cave-Ayland { 7862e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 78631a404c91SMark Cave-Ayland } 78641a404c91SMark Cave-Ayland 78651a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 78661a404c91SMark Cave-Ayland { 7867e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 78681a404c91SMark Cave-Ayland } 78691a404c91SMark Cave-Ayland 7870c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7871c4a18dbfSMark Cave-Ayland { 787237da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7873c4a18dbfSMark Cave-Ayland } 7874c4a18dbfSMark Cave-Ayland 7875c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7876c4a18dbfSMark Cave-Ayland { 787737da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7878c4a18dbfSMark Cave-Ayland } 7879c4a18dbfSMark Cave-Ayland 7880139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7881fcf5ef2aSThomas Huth 7882139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7883fcf5ef2aSThomas Huth 7884139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7885fcf5ef2aSThomas Huth 7886139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7887fcf5ef2aSThomas Huth 7888139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7889fcf5ef2aSThomas Huth 78905cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 78915cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 78925cb091a4SNikunj A Dadhania { 78935cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 78945cb091a4SNikunj A Dadhania case 0: /* lfdp */ 78955cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 78965cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 78975cb091a4SNikunj A Dadhania } 78985cb091a4SNikunj A Dadhania break; 78995cb091a4SNikunj A Dadhania case 2: /* lxsd */ 79005cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79015cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 79025cb091a4SNikunj A Dadhania } 79035cb091a4SNikunj A Dadhania break; 79045cb091a4SNikunj A Dadhania case 3: /* lxssp */ 79055cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79065cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 79075cb091a4SNikunj A Dadhania } 79085cb091a4SNikunj A Dadhania break; 79095cb091a4SNikunj A Dadhania } 79105cb091a4SNikunj A Dadhania return gen_invalid(ctx); 79115cb091a4SNikunj A Dadhania } 79125cb091a4SNikunj A Dadhania 7913d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7914e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7915e3001664SNikunj A Dadhania { 7916e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7917e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7918e3001664SNikunj A Dadhania case 1: /* lxv */ 7919d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7920d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7921d59ba583SNikunj A Dadhania } 7922e3001664SNikunj A Dadhania break; 7923e3001664SNikunj A Dadhania case 5: /* stxv */ 7924d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7925d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7926d59ba583SNikunj A Dadhania } 7927e3001664SNikunj A Dadhania break; 7928e3001664SNikunj A Dadhania } 7929e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7930e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7931e3001664SNikunj A Dadhania case 0: /* stfdp */ 7932e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7933e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7934e3001664SNikunj A Dadhania } 7935e3001664SNikunj A Dadhania break; 7936e3001664SNikunj A Dadhania case 2: /* stxsd */ 7937e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7938e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7939e3001664SNikunj A Dadhania } 7940e3001664SNikunj A Dadhania break; 7941e3001664SNikunj A Dadhania case 3: /* stxssp */ 7942e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7943e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7944e3001664SNikunj A Dadhania } 7945e3001664SNikunj A Dadhania break; 7946e3001664SNikunj A Dadhania } 7947e3001664SNikunj A Dadhania } 7948e3001664SNikunj A Dadhania return gen_invalid(ctx); 7949e3001664SNikunj A Dadhania } 7950e3001664SNikunj A Dadhania 79519d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79529d69cfa2SLijun Pan /* brd */ 79539d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 79549d69cfa2SLijun Pan { 79559d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79569d69cfa2SLijun Pan } 79579d69cfa2SLijun Pan 79589d69cfa2SLijun Pan /* brw */ 79599d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 79609d69cfa2SLijun Pan { 79619d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79629d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 79639d69cfa2SLijun Pan 79649d69cfa2SLijun Pan } 79659d69cfa2SLijun Pan 79669d69cfa2SLijun Pan /* brh */ 79679d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 79689d69cfa2SLijun Pan { 79699d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 79709d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 79719d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 79729d69cfa2SLijun Pan 79739d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 79749d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 79759d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 79769d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 79779d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 79789d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 79799d69cfa2SLijun Pan 79809d69cfa2SLijun Pan tcg_temp_free_i64(t0); 79819d69cfa2SLijun Pan tcg_temp_free_i64(t1); 79829d69cfa2SLijun Pan tcg_temp_free_i64(t2); 79839d69cfa2SLijun Pan } 79849d69cfa2SLijun Pan #endif 79859d69cfa2SLijun Pan 7986fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 79879d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79889d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 79899d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 79909d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 79919d69cfa2SLijun Pan #endif 7992fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7993fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7994fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7995fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7996fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7997fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7998fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7999fcf5ef2aSThomas Huth #endif 8000fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 8001fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 8002fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 8003fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8004fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8005fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8006fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8007fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 8008fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 8009fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 8010fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 8011fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 8012fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8013fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8014fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 8015fcf5ef2aSThomas Huth #endif 8016fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 8017fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 8018fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8019fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8020fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8021fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 8022fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 802380b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 8024b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 802580b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 8026fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 8027fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 8028fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8029fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8030fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8031fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8032fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 8033fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 8034fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 8035fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8036fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 8037fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 8038fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 8039fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 8040fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 8041fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 8042fcf5ef2aSThomas Huth #endif 8043fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8044fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8045fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8046fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 8047fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 8048fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 8049fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 8050fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8051fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 8052fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 8053fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 8054fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 8055fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 8056fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 8057fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8058fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 8059fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8060fcf5ef2aSThomas Huth #endif 8061fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8062fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 8063fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 8064fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 8065fcf5ef2aSThomas Huth #endif 80665cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 80675cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8068d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 8069e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8070fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8071fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8072fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 8073fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 8074fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 8075fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 8076c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 8077fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 8078fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8079fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8080fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 8081a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 8082a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 8083fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8084fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8085fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 8086fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8087a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 8088a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 8089fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 8090fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 8091fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 8092fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 8093fcf5ef2aSThomas Huth #endif 8094fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 8095fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 8096c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 8097fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8098fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8099fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 8100fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 8101fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 8102fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 8103fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 8104fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8105fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 81063c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 81073c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81083c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81093c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81103c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 81113c89b8d6SNicholas Piggin #endif 8112cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8113fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8114fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8115fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8116fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8117fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 8118fcf5ef2aSThomas Huth #endif 81193c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81203c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 81213c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 8122fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 8123fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8125fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 8126fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 8127fcf5ef2aSThomas Huth #endif 8128fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 8129fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 8130fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 8131fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 8132fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 8133fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 8134fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8135fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 8136fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 8137b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 8138fcf5ef2aSThomas Huth #endif 8139fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 8140fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 8141fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 814250728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8143fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 8144fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 814550728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8146fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 814750728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8148fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 814950728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8150fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 8151fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 815250728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8153fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 815499d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 8155fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 8156fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 815750728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8158fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 8159fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 8160fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 8161fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 8162fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 8163fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8164fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 8165fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 8166fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8167fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 8168fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 8169fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8170fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 8171fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 8172fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 8173fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 8174fcf5ef2aSThomas Huth #endif 8175fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 8176efe843d8SDavid Gibson /* 8177efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 8178efe843d8SDavid Gibson * different ISA versions 8179efe843d8SDavid Gibson */ 8180fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 8181fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 8182c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 8183c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 8184fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 8185fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8186fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 8187fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 8188a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 818962d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8190fcf5ef2aSThomas Huth #endif 8191fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 8192fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 8193fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 8194fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 8195fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 8196fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 8197fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 8198fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 8199fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 8200fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 8201fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 8202fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8203fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 8204fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 8205fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 8206fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 8207fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 8208fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 8209fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 8210fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8211fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 8212fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 8213fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 8214fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 8215fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 8216fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 8217fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 8218fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 8219fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 8220fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 8221fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 8222fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 8223fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 8224fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 8225fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 8226fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 8227fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 8228fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 8229fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 8230fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 8231fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 8232fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 8233fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 8234fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 8235fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 8236fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 8237fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 8238fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 8239fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 8240fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8241fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8242fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 8243fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 8244fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8245fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8246fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 8247fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 8248fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 8249fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 8250fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 8251fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 8252fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 8253fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 8254fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 8255fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 8256fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 8257fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 8258fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 8259fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 8260fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 8261fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 8262fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 8263fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 8264fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 8265fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 8266fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 8267fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 8268fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 8269fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 8270fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 8271fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 8272fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8273fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 8274fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8275fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 8276fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8277fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 8278fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8279fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 8280fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8281fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 8282fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 8283fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 8284fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 82857af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 82867af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 8287fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8288fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8289fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8290fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8291fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 829227a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8293fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8294fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 82950c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 82960c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8297fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8298fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8299fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8300fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8301fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8302fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8303fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8304fcf5ef2aSThomas Huth PPC2_ISA300), 8305fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 83065ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 83075ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 83085ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 83095ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8310fcf5ef2aSThomas Huth #endif 8311fcf5ef2aSThomas Huth 8312fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8313fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8314fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8315fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8316fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8317fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8318fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8319fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8320fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8321fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8322fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8323fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8324fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8325fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8326fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 83274c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8328fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8329fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8330fcf5ef2aSThomas Huth 8331fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8332fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8333fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8334fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8335fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8336fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8337fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8338fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8339fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8340fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8341fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8342fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8343fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8344fcf5ef2aSThomas Huth 8345fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8346fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8347fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8348fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8349fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8350fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8351fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8352fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8353fcf5ef2aSThomas Huth 8354fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8355fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8356fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8357fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8358fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8359fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8360fcf5ef2aSThomas Huth 8361fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8362fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8363fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8364fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8365fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8366fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8367fcf5ef2aSThomas Huth #endif 8368fcf5ef2aSThomas Huth 8369fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8370fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8371fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8372fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8373fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8374fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8375fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8376fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8377fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8378fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8379fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8380fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8381fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8382fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8383fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8384fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8385fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8386fcf5ef2aSThomas Huth 8387fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8388fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8389fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8390fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8391fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8392fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8393fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8394fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8395fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8396fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8397fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8398fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8399fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8400fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8401fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8402fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8403fcf5ef2aSThomas Huth #endif 8404fcf5ef2aSThomas Huth 8405fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8406fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8407fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8408fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8409fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8410fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8411fcf5ef2aSThomas Huth PPC_64B) 8412fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8413fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8414fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8415fcf5ef2aSThomas Huth PPC_64B), \ 8416fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8417fcf5ef2aSThomas Huth PPC_64B), \ 8418fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8419fcf5ef2aSThomas Huth PPC_64B) 8420fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8421fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8422fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8423fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8424fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8425fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8426fcf5ef2aSThomas Huth #endif 8427fcf5ef2aSThomas Huth 8428fcf5ef2aSThomas Huth #undef GEN_LD 8429fcf5ef2aSThomas Huth #undef GEN_LDU 8430fcf5ef2aSThomas Huth #undef GEN_LDUX 8431fcf5ef2aSThomas Huth #undef GEN_LDX_E 8432fcf5ef2aSThomas Huth #undef GEN_LDS 8433fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 8434fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8435fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 8436fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 8437fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 8438fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8439fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8440fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8441fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 8442fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 8443fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 8444fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 8445fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 8446fcf5ef2aSThomas Huth 8447fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 8448fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 8449fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 8450fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 8451fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8452fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 8453fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 8454fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 8455fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 8456fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8457fcf5ef2aSThomas Huth 8458fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8459fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8460fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8461fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8462fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8463fcf5ef2aSThomas Huth #endif 8464fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8465fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8466fcf5ef2aSThomas Huth 846750728199SRoman Kapl /* External PID based load */ 846850728199SRoman Kapl #undef GEN_LDEPX 846950728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 847050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 847150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 847250728199SRoman Kapl 847350728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 847450728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 847550728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 847650728199SRoman Kapl #if defined(TARGET_PPC64) 847750728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 847850728199SRoman Kapl #endif 847950728199SRoman Kapl 8480fcf5ef2aSThomas Huth #undef GEN_ST 8481fcf5ef2aSThomas Huth #undef GEN_STU 8482fcf5ef2aSThomas Huth #undef GEN_STUX 8483fcf5ef2aSThomas Huth #undef GEN_STX_E 8484fcf5ef2aSThomas Huth #undef GEN_STS 8485fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8486fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8487fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8488fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8489fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8490fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8491fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 84920123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8493fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8494fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8495fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8496fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8497fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8498fcf5ef2aSThomas Huth 8499fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8500fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8501fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8502fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8503fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8504fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8505fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8506fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8507fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8508fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8509fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8510fcf5ef2aSThomas Huth #endif 8511fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8512fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8513fcf5ef2aSThomas Huth 851450728199SRoman Kapl #undef GEN_STEPX 851550728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 851650728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 851750728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 851850728199SRoman Kapl 851950728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 852050728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 852150728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 852250728199SRoman Kapl #if defined(TARGET_PPC64) 852350728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 852450728199SRoman Kapl #endif 852550728199SRoman Kapl 8526fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8527fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8528fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8529fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8530fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8531fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8532fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8533fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8534fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8535fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8536fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8537fcf5ef2aSThomas Huth 8538fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8539fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8540fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8541fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8542fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8543fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8544fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8545fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8546fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8547fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8583fcf5ef2aSThomas Huth 8584fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8585fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8586fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8587fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8588fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8589fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8590fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8591fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8592fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8593fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8594fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8595fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8596fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8597fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8598fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8599fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8600fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8601fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8602fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8603fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8604fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8605fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8606fcf5ef2aSThomas Huth 8607139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8608fcf5ef2aSThomas Huth 8609139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8610fcf5ef2aSThomas Huth 8611139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8612fcf5ef2aSThomas Huth 8613139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8614fcf5ef2aSThomas Huth 8615139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8616fcf5ef2aSThomas Huth }; 8617fcf5ef2aSThomas Huth 86187468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 86197468e2c8SBruno Larsen (billionai) /* Opcode types */ 86207468e2c8SBruno Larsen (billionai) enum { 86217468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 86227468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 86237468e2c8SBruno Larsen (billionai) }; 86247468e2c8SBruno Larsen (billionai) 86257468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 86267468e2c8SBruno Larsen (billionai) 86277468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 86287468e2c8SBruno Larsen (billionai) { 86297468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 86307468e2c8SBruno Larsen (billionai) } 86317468e2c8SBruno Larsen (billionai) 86327468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 86337468e2c8SBruno Larsen (billionai) { 86347468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 86357468e2c8SBruno Larsen (billionai) } 86367468e2c8SBruno Larsen (billionai) 86377468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 86387468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 86397468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 86407468e2c8SBruno Larsen (billionai) { 86417468e2c8SBruno Larsen (billionai) int i; 86427468e2c8SBruno Larsen (billionai) 86437468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 86447468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86457468e2c8SBruno Larsen (billionai) } 86467468e2c8SBruno Larsen (billionai) } 86477468e2c8SBruno Larsen (billionai) 86487468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 86497468e2c8SBruno Larsen (billionai) { 86507468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 86517468e2c8SBruno Larsen (billionai) 86527468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 86537468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 86547468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 86557468e2c8SBruno Larsen (billionai) 86567468e2c8SBruno Larsen (billionai) return 0; 86577468e2c8SBruno Larsen (billionai) } 86587468e2c8SBruno Larsen (billionai) 86597468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 86607468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86617468e2c8SBruno Larsen (billionai) { 86627468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 86637468e2c8SBruno Larsen (billionai) return -1; 86647468e2c8SBruno Larsen (billionai) } 86657468e2c8SBruno Larsen (billionai) table[idx] = handler; 86667468e2c8SBruno Larsen (billionai) 86677468e2c8SBruno Larsen (billionai) return 0; 86687468e2c8SBruno Larsen (billionai) } 86697468e2c8SBruno Larsen (billionai) 86707468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 86717468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 86727468e2c8SBruno Larsen (billionai) { 86737468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 86747468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 86757468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 86767468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 86777468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 86787468e2c8SBruno Larsen (billionai) ppc_opcodes[idx]->oname, handler->oname); 86797468e2c8SBruno Larsen (billionai) #endif 86807468e2c8SBruno Larsen (billionai) return -1; 86817468e2c8SBruno Larsen (billionai) } 86827468e2c8SBruno Larsen (billionai) 86837468e2c8SBruno Larsen (billionai) return 0; 86847468e2c8SBruno Larsen (billionai) } 86857468e2c8SBruno Larsen (billionai) 86867468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 86877468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86887468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86897468e2c8SBruno Larsen (billionai) { 86907468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 86917468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 86927468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 86937468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 86947468e2c8SBruno Larsen (billionai) return -1; 86957468e2c8SBruno Larsen (billionai) } 86967468e2c8SBruno Larsen (billionai) } else { 86977468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 86987468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 86997468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 87007468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 87017468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 87027468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 87037468e2c8SBruno Larsen (billionai) #endif 87047468e2c8SBruno Larsen (billionai) return -1; 87057468e2c8SBruno Larsen (billionai) } 87067468e2c8SBruno Larsen (billionai) } 87077468e2c8SBruno Larsen (billionai) if (handler != NULL && 87087468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 87097468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 87107468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 87117468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 87127468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 87137468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 87147468e2c8SBruno Larsen (billionai) #endif 87157468e2c8SBruno Larsen (billionai) return -1; 87167468e2c8SBruno Larsen (billionai) } 87177468e2c8SBruno Larsen (billionai) 87187468e2c8SBruno Larsen (billionai) return 0; 87197468e2c8SBruno Larsen (billionai) } 87207468e2c8SBruno Larsen (billionai) 87217468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 87227468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87237468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 87247468e2c8SBruno Larsen (billionai) { 87257468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 87267468e2c8SBruno Larsen (billionai) } 87277468e2c8SBruno Larsen (billionai) 87287468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 87297468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87307468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 87317468e2c8SBruno Larsen (billionai) { 87327468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 87337468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 87347468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 87357468e2c8SBruno Larsen (billionai) return -1; 87367468e2c8SBruno Larsen (billionai) } 87377468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 87387468e2c8SBruno Larsen (billionai) handler) < 0) { 87397468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 87407468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 87417468e2c8SBruno Larsen (billionai) return -1; 87427468e2c8SBruno Larsen (billionai) } 87437468e2c8SBruno Larsen (billionai) 87447468e2c8SBruno Larsen (billionai) return 0; 87457468e2c8SBruno Larsen (billionai) } 87467468e2c8SBruno Larsen (billionai) 87477468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 87487468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87497468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 87507468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 87517468e2c8SBruno Larsen (billionai) { 87527468e2c8SBruno Larsen (billionai) opc_handler_t **table; 87537468e2c8SBruno Larsen (billionai) 87547468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 87557468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 87567468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 87577468e2c8SBruno Larsen (billionai) return -1; 87587468e2c8SBruno Larsen (billionai) } 87597468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 87607468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 87617468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 87627468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 87637468e2c8SBruno Larsen (billionai) return -1; 87647468e2c8SBruno Larsen (billionai) } 87657468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 87667468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 87677468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 87687468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 87697468e2c8SBruno Larsen (billionai) return -1; 87707468e2c8SBruno Larsen (billionai) } 87717468e2c8SBruno Larsen (billionai) return 0; 87727468e2c8SBruno Larsen (billionai) } 87737468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 87747468e2c8SBruno Larsen (billionai) { 87757468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 87767468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 87777468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 87787468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 87797468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 87807468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 87817468e2c8SBruno Larsen (billionai) return -1; 87827468e2c8SBruno Larsen (billionai) } 87837468e2c8SBruno Larsen (billionai) } else { 87847468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 87857468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 87867468e2c8SBruno Larsen (billionai) return -1; 87877468e2c8SBruno Larsen (billionai) } 87887468e2c8SBruno Larsen (billionai) } 87897468e2c8SBruno Larsen (billionai) } else { 87907468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 87917468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 87927468e2c8SBruno Larsen (billionai) return -1; 87937468e2c8SBruno Larsen (billionai) } 87947468e2c8SBruno Larsen (billionai) } 87957468e2c8SBruno Larsen (billionai) } else { 87967468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 87977468e2c8SBruno Larsen (billionai) return -1; 87987468e2c8SBruno Larsen (billionai) } 87997468e2c8SBruno Larsen (billionai) } 88007468e2c8SBruno Larsen (billionai) 88017468e2c8SBruno Larsen (billionai) return 0; 88027468e2c8SBruno Larsen (billionai) } 88037468e2c8SBruno Larsen (billionai) 88047468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 88057468e2c8SBruno Larsen (billionai) { 88067468e2c8SBruno Larsen (billionai) int i, count, tmp; 88077468e2c8SBruno Larsen (billionai) 88087468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 88097468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 88107468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 88117468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88127468e2c8SBruno Larsen (billionai) } 88137468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 88147468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 88157468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 88167468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 88177468e2c8SBruno Larsen (billionai) if (tmp == 0) { 88187468e2c8SBruno Larsen (billionai) free(table[i]); 88197468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88207468e2c8SBruno Larsen (billionai) } else { 88217468e2c8SBruno Larsen (billionai) count++; 88227468e2c8SBruno Larsen (billionai) } 88237468e2c8SBruno Larsen (billionai) } else { 88247468e2c8SBruno Larsen (billionai) count++; 88257468e2c8SBruno Larsen (billionai) } 88267468e2c8SBruno Larsen (billionai) } 88277468e2c8SBruno Larsen (billionai) } 88287468e2c8SBruno Larsen (billionai) 88297468e2c8SBruno Larsen (billionai) return count; 88307468e2c8SBruno Larsen (billionai) } 88317468e2c8SBruno Larsen (billionai) 88327468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 88337468e2c8SBruno Larsen (billionai) { 88347468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 88357468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 88367468e2c8SBruno Larsen (billionai) } 88377468e2c8SBruno Larsen (billionai) } 88387468e2c8SBruno Larsen (billionai) 88397468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 88407468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 88417468e2c8SBruno Larsen (billionai) { 88427468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 88437468e2c8SBruno Larsen (billionai) opcode_t *opc; 88447468e2c8SBruno Larsen (billionai) 88457468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 88467468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 88477468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 88487468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 88497468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 88507468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 88517468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 88527468e2c8SBruno Larsen (billionai) opc->opc3); 88537468e2c8SBruno Larsen (billionai) return; 88547468e2c8SBruno Larsen (billionai) } 88557468e2c8SBruno Larsen (billionai) } 88567468e2c8SBruno Larsen (billionai) } 88577468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 88587468e2c8SBruno Larsen (billionai) fflush(stdout); 88597468e2c8SBruno Larsen (billionai) fflush(stderr); 88607468e2c8SBruno Larsen (billionai) } 88617468e2c8SBruno Larsen (billionai) 88627468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 88637468e2c8SBruno Larsen (billionai) { 88647468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 88657468e2c8SBruno Larsen (billionai) int i, j, k; 88667468e2c8SBruno Larsen (billionai) 88677468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 88687468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 88697468e2c8SBruno Larsen (billionai) continue; 88707468e2c8SBruno Larsen (billionai) } 88717468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 88727468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 88737468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 88747468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 88757468e2c8SBruno Larsen (billionai) continue; 88767468e2c8SBruno Larsen (billionai) } 88777468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 88787468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 88797468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 88807468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 88817468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 88827468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 88837468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88847468e2c8SBruno Larsen (billionai) } 88857468e2c8SBruno Larsen (billionai) } 88867468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 88877468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88887468e2c8SBruno Larsen (billionai) } 88897468e2c8SBruno Larsen (billionai) } 88907468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 88917468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88927468e2c8SBruno Larsen (billionai) } 88937468e2c8SBruno Larsen (billionai) } 88947468e2c8SBruno Larsen (billionai) } 88957468e2c8SBruno Larsen (billionai) 88967468e2c8SBruno Larsen (billionai) #if defined(PPC_DUMP_CPU) 88977468e2c8SBruno Larsen (billionai) static void dump_ppc_insns(CPUPPCState *env) 88987468e2c8SBruno Larsen (billionai) { 88997468e2c8SBruno Larsen (billionai) opc_handler_t **table, *handler; 89007468e2c8SBruno Larsen (billionai) const char *p, *q; 89017468e2c8SBruno Larsen (billionai) uint8_t opc1, opc2, opc3, opc4; 89027468e2c8SBruno Larsen (billionai) 89037468e2c8SBruno Larsen (billionai) printf("Instructions set:\n"); 89047468e2c8SBruno Larsen (billionai) /* opc1 is 6 bits long */ 89057468e2c8SBruno Larsen (billionai) for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 89067468e2c8SBruno Larsen (billionai) table = env->opcodes; 89077468e2c8SBruno Larsen (billionai) handler = table[opc1]; 89087468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89097468e2c8SBruno Larsen (billionai) /* opc2 is 5 bits long */ 89107468e2c8SBruno Larsen (billionai) for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 89117468e2c8SBruno Larsen (billionai) table = env->opcodes; 89127468e2c8SBruno Larsen (billionai) handler = env->opcodes[opc1]; 89137468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89147468e2c8SBruno Larsen (billionai) handler = table[opc2]; 89157468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89167468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89177468e2c8SBruno Larsen (billionai) /* opc3 is 5 bits long */ 89187468e2c8SBruno Larsen (billionai) for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 89197468e2c8SBruno Larsen (billionai) opc3++) { 89207468e2c8SBruno Larsen (billionai) handler = table[opc3]; 89217468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89227468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89237468e2c8SBruno Larsen (billionai) /* opc4 is 5 bits long */ 89247468e2c8SBruno Larsen (billionai) for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 89257468e2c8SBruno Larsen (billionai) opc4++) { 89267468e2c8SBruno Larsen (billionai) handler = table[opc4]; 89277468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89287468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x %02x -- " 89297468e2c8SBruno Larsen (billionai) "(%02d %04d %02d) : %s\n", 89307468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc4, 89317468e2c8SBruno Larsen (billionai) opc1, (opc3 << 5) | opc2, opc4, 89327468e2c8SBruno Larsen (billionai) handler->oname); 89337468e2c8SBruno Larsen (billionai) } 89347468e2c8SBruno Larsen (billionai) } 89357468e2c8SBruno Larsen (billionai) } else { 89367468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89377468e2c8SBruno Larsen (billionai) /* Special hack to properly dump SPE insns */ 89387468e2c8SBruno Larsen (billionai) p = strchr(handler->oname, '_'); 89397468e2c8SBruno Larsen (billionai) if (p == NULL) { 89407468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x (%02d %04d) : " 89417468e2c8SBruno Larsen (billionai) "%s\n", 89427468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc1, 89437468e2c8SBruno Larsen (billionai) (opc3 << 5) | opc2, 89447468e2c8SBruno Larsen (billionai) handler->oname); 89457468e2c8SBruno Larsen (billionai) } else { 89467468e2c8SBruno Larsen (billionai) q = "speundef"; 89477468e2c8SBruno Larsen (billionai) if ((p - handler->oname) != strlen(q) 89487468e2c8SBruno Larsen (billionai) || (memcmp(handler->oname, q, strlen(q)) 89497468e2c8SBruno Larsen (billionai) != 0)) { 89507468e2c8SBruno Larsen (billionai) /* First instruction */ 89517468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x" 89527468e2c8SBruno Larsen (billionai) "(%02d %04d) : %.*s\n", 89537468e2c8SBruno Larsen (billionai) opc1, opc2 << 1, opc3, opc1, 89547468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1), 89557468e2c8SBruno Larsen (billionai) (int)(p - handler->oname), 89567468e2c8SBruno Larsen (billionai) handler->oname); 89577468e2c8SBruno Larsen (billionai) } 89587468e2c8SBruno Larsen (billionai) if (strcmp(p + 1, q) != 0) { 89597468e2c8SBruno Larsen (billionai) /* Second instruction */ 89607468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x " 89617468e2c8SBruno Larsen (billionai) "(%02d %04d) : %s\n", opc1, 89627468e2c8SBruno Larsen (billionai) (opc2 << 1) | 1, opc3, opc1, 89637468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1) | 1, 89647468e2c8SBruno Larsen (billionai) p + 1); 89657468e2c8SBruno Larsen (billionai) } 89667468e2c8SBruno Larsen (billionai) } 89677468e2c8SBruno Larsen (billionai) } 89687468e2c8SBruno Larsen (billionai) } 89697468e2c8SBruno Larsen (billionai) } 89707468e2c8SBruno Larsen (billionai) } else { 89717468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89727468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 89737468e2c8SBruno Larsen (billionai) opc1, opc2, opc1, opc2, handler->oname); 89747468e2c8SBruno Larsen (billionai) } 89757468e2c8SBruno Larsen (billionai) } 89767468e2c8SBruno Larsen (billionai) } 89777468e2c8SBruno Larsen (billionai) } else { 89787468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89797468e2c8SBruno Larsen (billionai) printf("INSN: %02x -- -- (%02d ----) : %s\n", 89807468e2c8SBruno Larsen (billionai) opc1, opc1, handler->oname); 89817468e2c8SBruno Larsen (billionai) } 89827468e2c8SBruno Larsen (billionai) } 89837468e2c8SBruno Larsen (billionai) } 89847468e2c8SBruno Larsen (billionai) } 89857468e2c8SBruno Larsen (billionai) #endif 89867468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 89877468e2c8SBruno Larsen (billionai) { 89887468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 89897468e2c8SBruno Larsen (billionai) 89907468e2c8SBruno Larsen (billionai) /* 89917468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 89927468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 89937468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 89947468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 89957468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 89967468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 89977468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 89987468e2c8SBruno Larsen (billionai) */ 89997468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 90007468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 90017468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 90027468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 90037468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 90047468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 90057468e2c8SBruno Larsen (billionai) } 90067468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 90077468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 90087468e2c8SBruno Larsen (billionai) return 0; 90097468e2c8SBruno Larsen (billionai) } 90107468e2c8SBruno Larsen (billionai) 90117468e2c8SBruno Larsen (billionai) 901211cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 9013fcf5ef2aSThomas Huth { 9014fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9015fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 9016fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 9017fcf5ef2aSThomas Huth int op1, op2, op3; 9018fcf5ef2aSThomas Huth 9019fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 9020fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 9021fcf5ef2aSThomas Huth handler = t1[op1]; 9022fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9023fcf5ef2aSThomas Huth t2 = ind_table(handler); 9024fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 9025fcf5ef2aSThomas Huth handler = t2[op2]; 9026fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9027fcf5ef2aSThomas Huth t3 = ind_table(handler); 9028fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 9029fcf5ef2aSThomas Huth handler = t3[op3]; 9030efe843d8SDavid Gibson if (handler->count == 0) { 9031fcf5ef2aSThomas Huth continue; 9032efe843d8SDavid Gibson } 903311cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 9034fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9035fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 9036fcf5ef2aSThomas Huth handler->oname, 9037fcf5ef2aSThomas Huth handler->count, handler->count); 9038fcf5ef2aSThomas Huth } 9039fcf5ef2aSThomas Huth } else { 9040efe843d8SDavid Gibson if (handler->count == 0) { 9041fcf5ef2aSThomas Huth continue; 9042efe843d8SDavid Gibson } 904311cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 9044fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9045fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 9046fcf5ef2aSThomas Huth handler->count, handler->count); 9047fcf5ef2aSThomas Huth } 9048fcf5ef2aSThomas Huth } 9049fcf5ef2aSThomas Huth } else { 9050efe843d8SDavid Gibson if (handler->count == 0) { 9051fcf5ef2aSThomas Huth continue; 9052efe843d8SDavid Gibson } 905311cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 9054fcf5ef2aSThomas Huth " %" PRId64 "\n", 9055fcf5ef2aSThomas Huth op1, op1, handler->oname, 9056fcf5ef2aSThomas Huth handler->count, handler->count); 9057fcf5ef2aSThomas Huth } 9058fcf5ef2aSThomas Huth } 9059fcf5ef2aSThomas Huth #endif 9060fcf5ef2aSThomas Huth } 9061fcf5ef2aSThomas Huth 9062624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 9063624cb07fSRichard Henderson { 9064624cb07fSRichard Henderson opc_handler_t **table, *handler; 9065624cb07fSRichard Henderson uint32_t inval; 9066624cb07fSRichard Henderson 9067624cb07fSRichard Henderson ctx->opcode = insn; 9068624cb07fSRichard Henderson 9069624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 9070624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9071624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 9072624cb07fSRichard Henderson 9073624cb07fSRichard Henderson table = cpu->opcodes; 9074624cb07fSRichard Henderson handler = table[opc1(insn)]; 9075624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9076624cb07fSRichard Henderson table = ind_table(handler); 9077624cb07fSRichard Henderson handler = table[opc2(insn)]; 9078624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9079624cb07fSRichard Henderson table = ind_table(handler); 9080624cb07fSRichard Henderson handler = table[opc3(insn)]; 9081624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9082624cb07fSRichard Henderson table = ind_table(handler); 9083624cb07fSRichard Henderson handler = table[opc4(insn)]; 9084624cb07fSRichard Henderson } 9085624cb07fSRichard Henderson } 9086624cb07fSRichard Henderson } 9087624cb07fSRichard Henderson 9088624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 9089624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 9090624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 9091624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 9092624cb07fSRichard Henderson TARGET_FMT_lx "\n", 9093624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9094624cb07fSRichard Henderson insn, ctx->cia); 9095624cb07fSRichard Henderson return false; 9096624cb07fSRichard Henderson } 9097624cb07fSRichard Henderson 9098624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 9099624cb07fSRichard Henderson && Rc(insn))) { 9100624cb07fSRichard Henderson inval = handler->inval2; 9101624cb07fSRichard Henderson } else { 9102624cb07fSRichard Henderson inval = handler->inval1; 9103624cb07fSRichard Henderson } 9104624cb07fSRichard Henderson 9105624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 9106624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 9107624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 9108624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 9109624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9110624cb07fSRichard Henderson insn, ctx->cia); 9111624cb07fSRichard Henderson return false; 9112624cb07fSRichard Henderson } 9113624cb07fSRichard Henderson 9114624cb07fSRichard Henderson handler->handler(ctx); 9115624cb07fSRichard Henderson return true; 9116624cb07fSRichard Henderson } 9117624cb07fSRichard Henderson 9118b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 9119fcf5ef2aSThomas Huth { 9120b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 91219c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 91222df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 9123b0c2d521SEmilio G. Cota int bound; 9124fcf5ef2aSThomas Huth 9125b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 9126b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 91272df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 9128d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 91292df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 91302df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 9131b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 9132b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 9133b0c2d521SEmilio G. Cota ctx->access_type = -1; 9134d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 91352df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 9136b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 91370e3bf489SRoman Kapl ctx->flags = env->flags; 9138fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 91392df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 9140b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 9141fcf5ef2aSThomas Huth #endif 9142e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 9143e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 9144d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 9145fcf5ef2aSThomas Huth 91462df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 91472df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 91482df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 91492df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 91502df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 9151f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 91522df4fe7aSRichard Henderson 9153b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 91542df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 91552df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 9156efe843d8SDavid Gibson } 91572df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 9158b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 9159efe843d8SDavid Gibson } 9160b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9161b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 9162fcf5ef2aSThomas Huth } 9163b0c2d521SEmilio G. Cota 9164b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 9165b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 9166fcf5ef2aSThomas Huth } 9167fcf5ef2aSThomas Huth 9168b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 9169b0c2d521SEmilio G. Cota { 9170b0c2d521SEmilio G. Cota } 9171fcf5ef2aSThomas Huth 9172b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 9173b0c2d521SEmilio G. Cota { 9174b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 9175b0c2d521SEmilio G. Cota } 9176b0c2d521SEmilio G. Cota 9177b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 9178b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 9179b0c2d521SEmilio G. Cota { 9180b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9181b0c2d521SEmilio G. Cota 91822736fc61SRichard Henderson gen_update_nip(ctx, ctx->base.pc_next); 9183b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9184efe843d8SDavid Gibson /* 9185efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 9186efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 9187efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 9188efe843d8SDavid Gibson * setting tb->size below does the right thing. 9189efe843d8SDavid Gibson */ 9190b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9191b0c2d521SEmilio G. Cota return true; 9192fcf5ef2aSThomas Huth } 9193fcf5ef2aSThomas Huth 9194b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 9195b0c2d521SEmilio G. Cota { 9196b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 919728876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 9198b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 9199624cb07fSRichard Henderson uint32_t insn; 9200624cb07fSRichard Henderson bool ok; 9201b0c2d521SEmilio G. Cota 9202fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 9203fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 9204b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 9205b0c2d521SEmilio G. Cota 92062c2bcb1bSRichard Henderson ctx->cia = ctx->base.pc_next; 9207624cb07fSRichard Henderson insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); 9208b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9209fcf5ef2aSThomas Huth 9210624cb07fSRichard Henderson ok = decode_legacy(cpu, ctx, insn); 9211624cb07fSRichard Henderson if (!ok) { 9212624cb07fSRichard Henderson gen_invalid(ctx); 9213fcf5ef2aSThomas Huth } 9214624cb07fSRichard Henderson 9215fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9216fcf5ef2aSThomas Huth handler->count++; 9217fcf5ef2aSThomas Huth #endif 92183d8a5b69SRichard Henderson 9219fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 9220b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 9221b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 92223d8a5b69SRichard Henderson ctx->exception != POWERPC_EXCP_BRANCH && 92233d8a5b69SRichard Henderson ctx->base.is_jmp != DISAS_NORETURN)) { 9224e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 92250e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 9226fcf5ef2aSThomas Huth } 9227b0c2d521SEmilio G. Cota 9228fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 9229b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 9230b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 9231b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 9232fcf5ef2aSThomas Huth } 9233b0c2d521SEmilio G. Cota 9234*a9b5b3d0SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT) { 9235*a9b5b3d0SRichard Henderson switch (ctx->exception) { 9236*a9b5b3d0SRichard Henderson case POWERPC_EXCP_NONE: 9237*a9b5b3d0SRichard Henderson break; 9238*a9b5b3d0SRichard Henderson case POWERPC_EXCP_BRANCH: 9239*a9b5b3d0SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 9240*a9b5b3d0SRichard Henderson break; 9241*a9b5b3d0SRichard Henderson case POWERPC_EXCP_SYNC: 9242*a9b5b3d0SRichard Henderson case POWERPC_EXCP_STOP: 9243*a9b5b3d0SRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 9244*a9b5b3d0SRichard Henderson break; 9245*a9b5b3d0SRichard Henderson default: 9246*a9b5b3d0SRichard Henderson /* Every other ctx->exception should have set NORETURN. */ 9247*a9b5b3d0SRichard Henderson g_assert_not_reached(); 9248*a9b5b3d0SRichard Henderson } 92493d8a5b69SRichard Henderson } 9250fcf5ef2aSThomas Huth } 9251b0c2d521SEmilio G. Cota 9252b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 9253b0c2d521SEmilio G. Cota { 9254b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9255*a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 9256*a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 9257b0c2d521SEmilio G. Cota 9258*a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 9259*a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 92603d8a5b69SRichard Henderson return; 92613d8a5b69SRichard Henderson } 92623d8a5b69SRichard Henderson 9263*a9b5b3d0SRichard Henderson /* Honor single stepping. */ 9264b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9265*a9b5b3d0SRichard Henderson switch (is_jmp) { 9266*a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 9267*a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 9268*a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 9269*a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9270*a9b5b3d0SRichard Henderson break; 9271*a9b5b3d0SRichard Henderson case DISAS_EXIT: 9272*a9b5b3d0SRichard Henderson case DISAS_CHAIN: 9273*a9b5b3d0SRichard Henderson break; 9274*a9b5b3d0SRichard Henderson default: 9275*a9b5b3d0SRichard Henderson g_assert_not_reached(); 9276fcf5ef2aSThomas Huth } 9277*a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 9278*a9b5b3d0SRichard Henderson return; 9279*a9b5b3d0SRichard Henderson } 9280*a9b5b3d0SRichard Henderson 9281*a9b5b3d0SRichard Henderson switch (is_jmp) { 9282*a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 9283*a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 9284*a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 9285*a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9286*a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 9287*a9b5b3d0SRichard Henderson break; 9288*a9b5b3d0SRichard Henderson } 9289*a9b5b3d0SRichard Henderson /* fall through */ 9290*a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 9291*a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9292*a9b5b3d0SRichard Henderson /* fall through */ 9293*a9b5b3d0SRichard Henderson case DISAS_CHAIN: 9294*a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 9295*a9b5b3d0SRichard Henderson break; 9296*a9b5b3d0SRichard Henderson 9297*a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 9298*a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9299*a9b5b3d0SRichard Henderson /* fall through */ 9300*a9b5b3d0SRichard Henderson case DISAS_EXIT: 930107ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 9302*a9b5b3d0SRichard Henderson break; 9303*a9b5b3d0SRichard Henderson 9304*a9b5b3d0SRichard Henderson default: 9305*a9b5b3d0SRichard Henderson g_assert_not_reached(); 9306fcf5ef2aSThomas Huth } 9307fcf5ef2aSThomas Huth } 9308b0c2d521SEmilio G. Cota 9309b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 9310b0c2d521SEmilio G. Cota { 9311b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 9312b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 9313b0c2d521SEmilio G. Cota } 9314b0c2d521SEmilio G. Cota 9315b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 9316b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 9317b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 9318b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 9319b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 9320b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 9321b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 9322b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 9323b0c2d521SEmilio G. Cota }; 9324b0c2d521SEmilio G. Cota 93258b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 9326b0c2d521SEmilio G. Cota { 9327b0c2d521SEmilio G. Cota DisasContext ctx; 9328b0c2d521SEmilio G. Cota 93298b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 9330fcf5ef2aSThomas Huth } 9331fcf5ef2aSThomas Huth 9332fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 9333fcf5ef2aSThomas Huth target_ulong *data) 9334fcf5ef2aSThomas Huth { 9335fcf5ef2aSThomas Huth env->nip = data[0]; 9336fcf5ef2aSThomas Huth } 9337