1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50fcf5ef2aSThomas Huth 51fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 53fcf5ef2aSThomas Huth #else 54fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 55fcf5ef2aSThomas Huth #endif 56fcf5ef2aSThomas Huth /*****************************************************************************/ 57fcf5ef2aSThomas Huth /* Code translation helpers */ 58fcf5ef2aSThomas Huth 59fcf5ef2aSThomas Huth /* global register indexes */ 60fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 61fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 62fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 63fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 64fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 65fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 66fcf5ef2aSThomas Huth static TCGv cpu_nip; 67fcf5ef2aSThomas Huth static TCGv cpu_msr; 68fcf5ef2aSThomas Huth static TCGv cpu_ctr; 69fcf5ef2aSThomas Huth static TCGv cpu_lr; 70fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 71fcf5ef2aSThomas Huth static TCGv cpu_cfar; 72fcf5ef2aSThomas Huth #endif 73dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 74fcf5ef2aSThomas Huth static TCGv cpu_reserve; 75253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 76fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 77fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth void ppc_translate_init(void) 82fcf5ef2aSThomas Huth { 83fcf5ef2aSThomas Huth int i; 84fcf5ef2aSThomas Huth char *p; 85fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 86fcf5ef2aSThomas Huth 87fcf5ef2aSThomas Huth p = cpu_reg_names; 88fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 91fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 92fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 93fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 94fcf5ef2aSThomas Huth p += 5; 95fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 96fcf5ef2aSThomas Huth } 97fcf5ef2aSThomas Huth 98fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 99fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 100fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 101fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 102fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 103fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 105fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 106fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 107fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 108fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth } 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 112fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 124fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 125fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 126fcf5ef2aSThomas Huth #endif 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 130fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 132fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 134fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 135fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 136dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 138dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 139dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 142fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 143fcf5ef2aSThomas Huth "reserve_addr"); 144253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 145253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 146253ce7b2SNikunj A Dadhania "reserve_val"); 147fcf5ef2aSThomas Huth 148fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 149fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 152efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 153efe843d8SDavid Gibson "access_type"); 154fcf5ef2aSThomas Huth } 155fcf5ef2aSThomas Huth 156fcf5ef2aSThomas Huth /* internal defines */ 157fcf5ef2aSThomas Huth struct DisasContext { 158b6bac4bcSEmilio G. Cota DisasContextBase base; 1592c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 160fcf5ef2aSThomas Huth uint32_t opcode; 161fcf5ef2aSThomas Huth /* Routine used to access memory */ 162fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 163fcf5ef2aSThomas Huth bool lazy_tlb_flush; 164fcf5ef2aSThomas Huth bool need_access_type; 165fcf5ef2aSThomas Huth int mem_idx; 166fcf5ef2aSThomas Huth int access_type; 167fcf5ef2aSThomas Huth /* Translation flags */ 16814776ab5STony Nguyen MemOp default_tcg_memop_mask; 169fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 170fcf5ef2aSThomas Huth bool sf_mode; 171fcf5ef2aSThomas Huth bool has_cfar; 172fcf5ef2aSThomas Huth #endif 173fcf5ef2aSThomas Huth bool fpu_enabled; 174fcf5ef2aSThomas Huth bool altivec_enabled; 175fcf5ef2aSThomas Huth bool vsx_enabled; 176fcf5ef2aSThomas Huth bool spe_enabled; 177fcf5ef2aSThomas Huth bool tm_enabled; 178c6fd28fdSSuraj Jitindar Singh bool gtse; 179fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 180fcf5ef2aSThomas Huth int singlestep_enabled; 1810e3bf489SRoman Kapl uint32_t flags; 182fcf5ef2aSThomas Huth uint64_t insns_flags; 183fcf5ef2aSThomas Huth uint64_t insns_flags2; 184fcf5ef2aSThomas Huth }; 185fcf5ef2aSThomas Huth 186a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 187a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 188a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 189a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 190a9b5b3d0SRichard Henderson 191fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 192fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 193fcf5ef2aSThomas Huth { 194fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 195fcf5ef2aSThomas Huth return ctx->le_mode; 196fcf5ef2aSThomas Huth #else 197fcf5ef2aSThomas Huth return !ctx->le_mode; 198fcf5ef2aSThomas Huth #endif 199fcf5ef2aSThomas Huth } 200fcf5ef2aSThomas Huth 201fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 202fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 203fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 204fcf5ef2aSThomas Huth #else 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 206fcf5ef2aSThomas Huth #endif 207fcf5ef2aSThomas Huth 208fcf5ef2aSThomas Huth struct opc_handler_t { 209fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 210fcf5ef2aSThomas Huth uint32_t inval1; 211fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 212fcf5ef2aSThomas Huth uint32_t inval2; 213fcf5ef2aSThomas Huth /* instruction type */ 214fcf5ef2aSThomas Huth uint64_t type; 215fcf5ef2aSThomas Huth /* extended instruction type */ 216fcf5ef2aSThomas Huth uint64_t type2; 217fcf5ef2aSThomas Huth /* handler */ 218fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 219fcf5ef2aSThomas Huth }; 220fcf5ef2aSThomas Huth 2210e3bf489SRoman Kapl /* SPR load/store helpers */ 2220e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2230e3bf489SRoman Kapl { 2240e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2250e3bf489SRoman Kapl } 2260e3bf489SRoman Kapl 2270e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2280e3bf489SRoman Kapl { 2290e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2300e3bf489SRoman Kapl } 2310e3bf489SRoman Kapl 232fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 233fcf5ef2aSThomas Huth { 234fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 235fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 236fcf5ef2aSThomas Huth ctx->access_type = access_type; 237fcf5ef2aSThomas Huth } 238fcf5ef2aSThomas Huth } 239fcf5ef2aSThomas Huth 240fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 241fcf5ef2aSThomas Huth { 242fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 243fcf5ef2aSThomas Huth nip = (uint32_t)nip; 244fcf5ef2aSThomas Huth } 245fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth 248fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 249fcf5ef2aSThomas Huth { 250fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 251fcf5ef2aSThomas Huth 252efe843d8SDavid Gibson /* 253efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 254efe843d8SDavid Gibson * faulting instruction 255fcf5ef2aSThomas Huth */ 2562c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 257fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 258fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 259fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 260fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 261fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2623d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 263fcf5ef2aSThomas Huth } 264fcf5ef2aSThomas Huth 265fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 266fcf5ef2aSThomas Huth { 267fcf5ef2aSThomas Huth TCGv_i32 t0; 268fcf5ef2aSThomas Huth 269efe843d8SDavid Gibson /* 270efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 271efe843d8SDavid Gibson * faulting instruction 272fcf5ef2aSThomas Huth */ 2732c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 274fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 275fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 276fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2773d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 278fcf5ef2aSThomas Huth } 279fcf5ef2aSThomas Huth 280fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 281fcf5ef2aSThomas Huth target_ulong nip) 282fcf5ef2aSThomas Huth { 283fcf5ef2aSThomas Huth TCGv_i32 t0; 284fcf5ef2aSThomas Huth 285fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 286fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 287fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 288fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2893d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 290fcf5ef2aSThomas Huth } 291fcf5ef2aSThomas Huth 292f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 293f5b6daacSRichard Henderson { 294f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 295f5b6daacSRichard Henderson gen_io_start(); 296f5b6daacSRichard Henderson /* 297f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 298f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 299f5b6daacSRichard Henderson * decide if we need to return to the main loop. 300f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 301f5b6daacSRichard Henderson */ 302f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 303f5b6daacSRichard Henderson } 304f5b6daacSRichard Henderson } 305f5b6daacSRichard Henderson 306e150ac89SRoman Kapl /* 307e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 308e150ac89SRoman Kapl * SPR registers for this exception. 309e150ac89SRoman Kapl * 310e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 311e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3120e3bf489SRoman Kapl */ 313e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3140e3bf489SRoman Kapl { 3150e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3160e3bf489SRoman Kapl target_ulong dbsr = 0; 317e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3180e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 319e150ac89SRoman Kapl } else { 320e150ac89SRoman Kapl /* Must have been branch */ 3210e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3220e3bf489SRoman Kapl } 3230e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3240e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3250e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3260e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3270e3bf489SRoman Kapl tcg_temp_free(t0); 3280e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3290e3bf489SRoman Kapl } else { 330e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3310e3bf489SRoman Kapl } 3320e3bf489SRoman Kapl } 3330e3bf489SRoman Kapl 334fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 335fcf5ef2aSThomas Huth { 3362736fc61SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 3373d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 338fcf5ef2aSThomas Huth } 339fcf5ef2aSThomas Huth 340fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341fcf5ef2aSThomas Huth { 342fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 343fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344fcf5ef2aSThomas Huth } 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347fcf5ef2aSThomas Huth { 348fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349fcf5ef2aSThomas Huth } 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352fcf5ef2aSThomas Huth { 353fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 354fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 35737f219c8SBruno Larsen (billionai) /*****************************************************************************/ 35837f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 35937f219c8SBruno Larsen (billionai) 360a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36137f219c8SBruno Larsen (billionai) { 36237f219c8SBruno Larsen (billionai) #if 0 36337f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36437f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36537f219c8SBruno Larsen (billionai) #endif 36637f219c8SBruno Larsen (billionai) } 36737f219c8SBruno Larsen (billionai) 36837f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 36937f219c8SBruno Larsen (billionai) 37037f219c8SBruno Larsen (billionai) /* 37137f219c8SBruno Larsen (billionai) * Generic callbacks: 37237f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37337f219c8SBruno Larsen (billionai) */ 37437f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37537f219c8SBruno Larsen (billionai) { 37637f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 37837f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 37937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38037f219c8SBruno Larsen (billionai) #endif 38137f219c8SBruno Larsen (billionai) } 38237f219c8SBruno Larsen (billionai) 383a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38437f219c8SBruno Larsen (billionai) { 38537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38737f219c8SBruno Larsen (billionai) } 38837f219c8SBruno Larsen (billionai) 38937f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39037f219c8SBruno Larsen (billionai) { 39137f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39337f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39537f219c8SBruno Larsen (billionai) #endif 39637f219c8SBruno Larsen (billionai) } 39737f219c8SBruno Larsen (billionai) 398a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 39937f219c8SBruno Larsen (billionai) { 40037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40237f219c8SBruno Larsen (billionai) } 40337f219c8SBruno Larsen (billionai) 40437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 405a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 40637f219c8SBruno Larsen (billionai) { 40737f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 40837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 40937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 41037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 41137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 41237f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41337f219c8SBruno Larsen (billionai) #else 41437f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 41537f219c8SBruno Larsen (billionai) #endif 41637f219c8SBruno Larsen (billionai) } 41737f219c8SBruno Larsen (billionai) 418a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 41937f219c8SBruno Larsen (billionai) { 42037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 42237f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 42337f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 42437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 42537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 42837f219c8SBruno Larsen (billionai) } 42937f219c8SBruno Larsen (billionai) 430a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 43137f219c8SBruno Larsen (billionai) { 43237f219c8SBruno Larsen (billionai) } 43337f219c8SBruno Larsen (billionai) 43437f219c8SBruno Larsen (billionai) #endif 43537f219c8SBruno Larsen (billionai) 43637f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 43737f219c8SBruno Larsen (billionai) /* XER */ 438a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 43937f219c8SBruno Larsen (billionai) { 44037f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 44137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 44437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 44537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 44637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 44737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 44837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 44937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 45037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45137f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 45237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 45337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 45537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45637f219c8SBruno Larsen (billionai) } 45737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 45937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 46037f219c8SBruno Larsen (billionai) } 46137f219c8SBruno Larsen (billionai) 462a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 46337f219c8SBruno Larsen (billionai) { 46437f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 46537f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 46637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 46737f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 46837f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 46937f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 47037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 47137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 47237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 47337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 47437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 47537f219c8SBruno Larsen (billionai) } 47637f219c8SBruno Larsen (billionai) 47737f219c8SBruno Larsen (billionai) /* LR */ 478a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 47937f219c8SBruno Larsen (billionai) { 48037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 48137f219c8SBruno Larsen (billionai) } 48237f219c8SBruno Larsen (billionai) 483a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 48437f219c8SBruno Larsen (billionai) { 48537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 48637f219c8SBruno Larsen (billionai) } 48737f219c8SBruno Larsen (billionai) 48837f219c8SBruno Larsen (billionai) /* CFAR */ 48937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 490a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 49137f219c8SBruno Larsen (billionai) { 49237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 49337f219c8SBruno Larsen (billionai) } 49437f219c8SBruno Larsen (billionai) 495a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 49637f219c8SBruno Larsen (billionai) { 49737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 49837f219c8SBruno Larsen (billionai) } 49937f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 50037f219c8SBruno Larsen (billionai) 50137f219c8SBruno Larsen (billionai) /* CTR */ 502a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 50337f219c8SBruno Larsen (billionai) { 50437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 50537f219c8SBruno Larsen (billionai) } 50637f219c8SBruno Larsen (billionai) 507a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 50837f219c8SBruno Larsen (billionai) { 50937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 51037f219c8SBruno Larsen (billionai) } 51137f219c8SBruno Larsen (billionai) 51237f219c8SBruno Larsen (billionai) /* User read access to SPR */ 51337f219c8SBruno Larsen (billionai) /* USPRx */ 51437f219c8SBruno Larsen (billionai) /* UMMCRx */ 51537f219c8SBruno Larsen (billionai) /* UPMCx */ 51637f219c8SBruno Larsen (billionai) /* USIA */ 51737f219c8SBruno Larsen (billionai) /* UDECR */ 518a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 51937f219c8SBruno Larsen (billionai) { 52037f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 52137f219c8SBruno Larsen (billionai) } 52237f219c8SBruno Larsen (billionai) 52337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 524a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 52537f219c8SBruno Larsen (billionai) { 52637f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 52737f219c8SBruno Larsen (billionai) } 52837f219c8SBruno Larsen (billionai) #endif 52937f219c8SBruno Larsen (billionai) 53037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 53137f219c8SBruno Larsen (billionai) /* DECR */ 53237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 533a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 53437f219c8SBruno Larsen (billionai) { 535f5b6daacSRichard Henderson gen_icount_io_start(ctx); 53637f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 53737f219c8SBruno Larsen (billionai) } 53837f219c8SBruno Larsen (billionai) 539a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 54037f219c8SBruno Larsen (billionai) { 541f5b6daacSRichard Henderson gen_icount_io_start(ctx); 54237f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 54337f219c8SBruno Larsen (billionai) } 54437f219c8SBruno Larsen (billionai) #endif 54537f219c8SBruno Larsen (billionai) 54637f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 54737f219c8SBruno Larsen (billionai) /* Time base */ 548a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 54937f219c8SBruno Larsen (billionai) { 550f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55137f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 55237f219c8SBruno Larsen (billionai) } 55337f219c8SBruno Larsen (billionai) 554a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 55537f219c8SBruno Larsen (billionai) { 556f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55737f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 55837f219c8SBruno Larsen (billionai) } 55937f219c8SBruno Larsen (billionai) 560a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 56137f219c8SBruno Larsen (billionai) { 56237f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 56337f219c8SBruno Larsen (billionai) } 56437f219c8SBruno Larsen (billionai) 565a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 56637f219c8SBruno Larsen (billionai) { 56737f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 56837f219c8SBruno Larsen (billionai) } 56937f219c8SBruno Larsen (billionai) 57037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 571a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 57237f219c8SBruno Larsen (billionai) { 573f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57437f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 57537f219c8SBruno Larsen (billionai) } 57637f219c8SBruno Larsen (billionai) 577a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 57837f219c8SBruno Larsen (billionai) { 579f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58037f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 58137f219c8SBruno Larsen (billionai) } 58237f219c8SBruno Larsen (billionai) 583a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 58437f219c8SBruno Larsen (billionai) { 58537f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 58637f219c8SBruno Larsen (billionai) } 58737f219c8SBruno Larsen (billionai) 588a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 58937f219c8SBruno Larsen (billionai) { 59037f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 59137f219c8SBruno Larsen (billionai) } 59237f219c8SBruno Larsen (billionai) 59337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 594a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 59537f219c8SBruno Larsen (billionai) { 596f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59737f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 59837f219c8SBruno Larsen (billionai) } 59937f219c8SBruno Larsen (billionai) 600a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 60137f219c8SBruno Larsen (billionai) { 602f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60337f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 60437f219c8SBruno Larsen (billionai) } 60537f219c8SBruno Larsen (billionai) 60637f219c8SBruno Larsen (billionai) /* HDECR */ 607a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 60837f219c8SBruno Larsen (billionai) { 609f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61037f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 61137f219c8SBruno Larsen (billionai) } 61237f219c8SBruno Larsen (billionai) 613a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 61437f219c8SBruno Larsen (billionai) { 615f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61637f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 61737f219c8SBruno Larsen (billionai) } 61837f219c8SBruno Larsen (billionai) 619a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 62037f219c8SBruno Larsen (billionai) { 621f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62237f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 62337f219c8SBruno Larsen (billionai) } 62437f219c8SBruno Larsen (billionai) 625a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 62637f219c8SBruno Larsen (billionai) { 627f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62837f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 62937f219c8SBruno Larsen (billionai) } 63037f219c8SBruno Larsen (billionai) 631a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 63237f219c8SBruno Larsen (billionai) { 633f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63437f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 63537f219c8SBruno Larsen (billionai) } 63637f219c8SBruno Larsen (billionai) 63737f219c8SBruno Larsen (billionai) #endif 63837f219c8SBruno Larsen (billionai) #endif 63937f219c8SBruno Larsen (billionai) 64037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 64137f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 64237f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 643a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 64437f219c8SBruno Larsen (billionai) { 64537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 64637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 64737f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 64837f219c8SBruno Larsen (billionai) } 64937f219c8SBruno Larsen (billionai) 650a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 65137f219c8SBruno Larsen (billionai) { 65237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 65337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 65437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) 657a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 66037f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66237f219c8SBruno Larsen (billionai) } 66337f219c8SBruno Larsen (billionai) 664a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 66537f219c8SBruno Larsen (billionai) { 66637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 66737f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66937f219c8SBruno Larsen (billionai) } 67037f219c8SBruno Larsen (billionai) 671a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 67237f219c8SBruno Larsen (billionai) { 67337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 67437f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 67537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67637f219c8SBruno Larsen (billionai) } 67737f219c8SBruno Larsen (billionai) 678a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 67937f219c8SBruno Larsen (billionai) { 68037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 68137f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 68537f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 68637f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 687a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 68837f219c8SBruno Larsen (billionai) { 68937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69137f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 69237f219c8SBruno Larsen (billionai) } 69337f219c8SBruno Larsen (billionai) 694a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 69537f219c8SBruno Larsen (billionai) { 69637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69837f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 69937f219c8SBruno Larsen (billionai) } 70037f219c8SBruno Larsen (billionai) 701a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 70237f219c8SBruno Larsen (billionai) { 70337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 70437f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 70537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) 708a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 70937f219c8SBruno Larsen (billionai) { 71037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 71137f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) 715a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 71637f219c8SBruno Larsen (billionai) { 71737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 71837f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 71937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) 722a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 72337f219c8SBruno Larsen (billionai) { 72437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 72537f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 72937f219c8SBruno Larsen (billionai) /* SDR1 */ 730a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 73137f219c8SBruno Larsen (billionai) { 73237f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) } 73437f219c8SBruno Larsen (billionai) 73537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 73637f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 73737f219c8SBruno Larsen (billionai) /* PIDR */ 738a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 73937f219c8SBruno Larsen (billionai) { 74037f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 74137f219c8SBruno Larsen (billionai) } 74237f219c8SBruno Larsen (billionai) 743a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 74437f219c8SBruno Larsen (billionai) { 74537f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 74637f219c8SBruno Larsen (billionai) } 74737f219c8SBruno Larsen (billionai) 748a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 74937f219c8SBruno Larsen (billionai) { 75037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 75137f219c8SBruno Larsen (billionai) } 75237f219c8SBruno Larsen (billionai) 753a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 75437f219c8SBruno Larsen (billionai) { 75537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 75637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 75737f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 75837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 75937f219c8SBruno Larsen (billionai) } 760a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 76137f219c8SBruno Larsen (billionai) { 76237f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 76337f219c8SBruno Larsen (billionai) } 76437f219c8SBruno Larsen (billionai) 765a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 76637f219c8SBruno Larsen (billionai) { 76737f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 76837f219c8SBruno Larsen (billionai) } 76937f219c8SBruno Larsen (billionai) 77037f219c8SBruno Larsen (billionai) /* DPDES */ 771a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 77237f219c8SBruno Larsen (billionai) { 77337f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 77437f219c8SBruno Larsen (billionai) } 77537f219c8SBruno Larsen (billionai) 776a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 77737f219c8SBruno Larsen (billionai) { 77837f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 77937f219c8SBruno Larsen (billionai) } 78037f219c8SBruno Larsen (billionai) #endif 78137f219c8SBruno Larsen (billionai) #endif 78237f219c8SBruno Larsen (billionai) 78337f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 78437f219c8SBruno Larsen (billionai) /* RTC */ 785a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 78637f219c8SBruno Larsen (billionai) { 78737f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) 79537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 796a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 79737f219c8SBruno Larsen (billionai) { 79837f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 79937f219c8SBruno Larsen (billionai) } 80037f219c8SBruno Larsen (billionai) 801a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 80237f219c8SBruno Larsen (billionai) { 80337f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 80437f219c8SBruno Larsen (billionai) } 80537f219c8SBruno Larsen (billionai) 806a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 80737f219c8SBruno Larsen (billionai) { 80837f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 80937f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 810d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81137f219c8SBruno Larsen (billionai) } 81237f219c8SBruno Larsen (billionai) #endif 81337f219c8SBruno Larsen (billionai) 81437f219c8SBruno Larsen (billionai) /* Unified bats */ 81537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 816a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 81737f219c8SBruno Larsen (billionai) { 81837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 81937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 82037f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 82137f219c8SBruno Larsen (billionai) } 82237f219c8SBruno Larsen (billionai) 823a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 82437f219c8SBruno Larsen (billionai) { 82537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 82637f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 82737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 82837f219c8SBruno Larsen (billionai) } 82937f219c8SBruno Larsen (billionai) 830a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 83137f219c8SBruno Larsen (billionai) { 83237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 83337f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 83437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) #endif 83737f219c8SBruno Larsen (billionai) 83837f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 83937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 840a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 84137f219c8SBruno Larsen (billionai) { 842f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84337f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84437f219c8SBruno Larsen (billionai) } 84537f219c8SBruno Larsen (billionai) 846a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84737f219c8SBruno Larsen (billionai) { 848f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84937f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 85037f219c8SBruno Larsen (billionai) } 85137f219c8SBruno Larsen (billionai) 852a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85337f219c8SBruno Larsen (billionai) { 854f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85637f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85737f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 858d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 85937f219c8SBruno Larsen (billionai) } 86037f219c8SBruno Larsen (billionai) 861a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86237f219c8SBruno Larsen (billionai) { 863f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86437f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86537f219c8SBruno Larsen (billionai) } 86637f219c8SBruno Larsen (billionai) 867a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 86837f219c8SBruno Larsen (billionai) { 869f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 87137f219c8SBruno Larsen (billionai) } 87237f219c8SBruno Larsen (billionai) 873a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 87437f219c8SBruno Larsen (billionai) { 875f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87637f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 87737f219c8SBruno Larsen (billionai) } 87837f219c8SBruno Larsen (billionai) #endif 87937f219c8SBruno Larsen (billionai) 88037f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 88137f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 88237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 883a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 88437f219c8SBruno Larsen (billionai) { 88537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 88637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 88737f219c8SBruno Larsen (billionai) } 88837f219c8SBruno Larsen (billionai) 889a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 89037f219c8SBruno Larsen (billionai) { 89137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 89237f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 89337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89437f219c8SBruno Larsen (billionai) } 89537f219c8SBruno Larsen (billionai) 896a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 89737f219c8SBruno Larsen (billionai) { 89837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 89937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90237f219c8SBruno Larsen (billionai) } 90337f219c8SBruno Larsen (billionai) #endif 90437f219c8SBruno Larsen (billionai) 90537f219c8SBruno Larsen (billionai) /* SPE specific registers */ 906a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 90737f219c8SBruno Larsen (billionai) { 90837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 90937f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91037f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91237f219c8SBruno Larsen (billionai) } 91337f219c8SBruno Larsen (billionai) 914a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91537f219c8SBruno Larsen (billionai) { 91637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91737f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 91837f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92037f219c8SBruno Larsen (billionai) } 92137f219c8SBruno Larsen (billionai) 92237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92337f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 924a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92537f219c8SBruno Larsen (billionai) { 92637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 92837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 92937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93237f219c8SBruno Larsen (billionai) } 93337f219c8SBruno Larsen (billionai) 934a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93537f219c8SBruno Larsen (billionai) { 93637f219c8SBruno Larsen (billionai) int sprn_offs; 93737f219c8SBruno Larsen (billionai) 93837f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 93937f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 94037f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94437f219c8SBruno Larsen (billionai) } else { 94537f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 94637f219c8SBruno Larsen (billionai) sprn, sprn); 94737f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 94837f219c8SBruno Larsen (billionai) return; 94937f219c8SBruno Larsen (billionai) } 95037f219c8SBruno Larsen (billionai) 95137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 95737f219c8SBruno Larsen (billionai) } 95837f219c8SBruno Larsen (billionai) #endif 95937f219c8SBruno Larsen (billionai) 96037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 96137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 962a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96337f219c8SBruno Larsen (billionai) { 96437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96737f219c8SBruno Larsen (billionai) 96837f219c8SBruno Larsen (billionai) /* 96937f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 97037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97137f219c8SBruno Larsen (billionai) */ 97237f219c8SBruno Larsen (billionai) 97337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97437f219c8SBruno Larsen (billionai) if (ctx->pr) { 97537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97637f219c8SBruno Larsen (billionai) } else { 97737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97837f219c8SBruno Larsen (billionai) } 97937f219c8SBruno Larsen (billionai) 98037f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98237f219c8SBruno Larsen (billionai) 98337f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98437f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98537f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98637f219c8SBruno Larsen (billionai) 98737f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 98937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 99037f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 99137f219c8SBruno Larsen (billionai) 99237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 99337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 99437f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 99537f219c8SBruno Larsen (billionai) } 99637f219c8SBruno Larsen (billionai) 997a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 99837f219c8SBruno Larsen (billionai) { 99937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100237f219c8SBruno Larsen (billionai) 100337f219c8SBruno Larsen (billionai) /* 100437f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100637f219c8SBruno Larsen (billionai) */ 100737f219c8SBruno Larsen (billionai) 100837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101037f219c8SBruno Larsen (billionai) 101137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101337f219c8SBruno Larsen (billionai) 101437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101737f219c8SBruno Larsen (billionai) 101837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 102137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 102237f219c8SBruno Larsen (billionai) 102337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 102537f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 102637f219c8SBruno Larsen (billionai) } 102737f219c8SBruno Larsen (billionai) 1028a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 102937f219c8SBruno Larsen (billionai) { 103037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103337f219c8SBruno Larsen (billionai) 103437f219c8SBruno Larsen (billionai) /* 103537f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 103637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 103737f219c8SBruno Larsen (billionai) */ 103837f219c8SBruno Larsen (billionai) 103937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104137f219c8SBruno Larsen (billionai) 104237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 104437f219c8SBruno Larsen (billionai) 104537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 104637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 104737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 104837f219c8SBruno Larsen (billionai) 104937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 105237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 105337f219c8SBruno Larsen (billionai) 105437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 105637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 105737f219c8SBruno Larsen (billionai) } 105837f219c8SBruno Larsen (billionai) #endif 105937f219c8SBruno Larsen (billionai) #endif 106037f219c8SBruno Larsen (billionai) 106137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1062a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 106337f219c8SBruno Larsen (billionai) { 106437f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 106537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 106637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 106737f219c8SBruno Larsen (billionai) } 106837f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 106937f219c8SBruno Larsen (billionai) 107037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1071a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 107237f219c8SBruno Larsen (billionai) { 107337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107437f219c8SBruno Larsen (billionai) 107537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 107637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107837f219c8SBruno Larsen (billionai) } 107937f219c8SBruno Larsen (billionai) 1080a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 108137f219c8SBruno Larsen (billionai) { 108237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108337f219c8SBruno Larsen (billionai) 108437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 108537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108737f219c8SBruno Larsen (billionai) } 108837f219c8SBruno Larsen (billionai) 1089a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 109037f219c8SBruno Larsen (billionai) { 109137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109237f219c8SBruno Larsen (billionai) 109337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 109437f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 109537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109737f219c8SBruno Larsen (billionai) } 109837f219c8SBruno Larsen (billionai) 1099a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 110037f219c8SBruno Larsen (billionai) { 110137f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 110237f219c8SBruno Larsen (billionai) } 110337f219c8SBruno Larsen (billionai) 1104a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 110537f219c8SBruno Larsen (billionai) { 110637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 110737f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 110837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 110937f219c8SBruno Larsen (billionai) } 1110a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 111137f219c8SBruno Larsen (billionai) { 111237f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 111337f219c8SBruno Larsen (billionai) } 1114a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 111537f219c8SBruno Larsen (billionai) { 111637f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 111737f219c8SBruno Larsen (billionai) } 111837f219c8SBruno Larsen (billionai) 111937f219c8SBruno Larsen (billionai) #endif 112037f219c8SBruno Larsen (billionai) 112137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1122a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 112337f219c8SBruno Larsen (billionai) { 112437f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 112537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 112637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 112737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 112837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 112937f219c8SBruno Larsen (billionai) tcg_temp_free(val); 113037f219c8SBruno Larsen (billionai) } 113137f219c8SBruno Larsen (billionai) 1132a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 113337f219c8SBruno Larsen (billionai) { 113437f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 113537f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 113637f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 113737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 113837f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 113937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 114037f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 114137f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 114237f219c8SBruno Larsen (billionai) } 114337f219c8SBruno Larsen (billionai) 114437f219c8SBruno Larsen (billionai) #endif 114537f219c8SBruno Larsen (billionai) 114637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 114737f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 114837f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114937f219c8SBruno Larsen (billionai) { 115037f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 115137f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 115237f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 115337f219c8SBruno Larsen (billionai) 115437f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 115537f219c8SBruno Larsen (billionai) 115637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 115737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 115837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 115937f219c8SBruno Larsen (billionai) } 116037f219c8SBruno Larsen (billionai) 116137f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 116237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116337f219c8SBruno Larsen (billionai) { 116437f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 116537f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 116637f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 116937f219c8SBruno Larsen (billionai) 117037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 117337f219c8SBruno Larsen (billionai) } 117437f219c8SBruno Larsen (billionai) 1175a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 117637f219c8SBruno Larsen (billionai) { 117737f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 117837f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 117937f219c8SBruno Larsen (billionai) 118037f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 118237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 118337f219c8SBruno Larsen (billionai) 118437f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 118537f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 118637f219c8SBruno Larsen (billionai) } 118737f219c8SBruno Larsen (billionai) 1188a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 118937f219c8SBruno Larsen (billionai) { 119037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119137f219c8SBruno Larsen (billionai) 119237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119337f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 119437f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 119537f219c8SBruno Larsen (billionai) 119637f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 119737f219c8SBruno Larsen (billionai) } 119837f219c8SBruno Larsen (billionai) 119937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1200a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 120137f219c8SBruno Larsen (billionai) { 120237f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 120337f219c8SBruno Larsen (billionai) 120437f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 120537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 120637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 120737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 120837f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 120937f219c8SBruno Larsen (billionai) } 121037f219c8SBruno Larsen (billionai) 1211a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 121237f219c8SBruno Larsen (billionai) { 121337f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 121437f219c8SBruno Larsen (billionai) } 121537f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 121637f219c8SBruno Larsen (billionai) 1217a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 121837f219c8SBruno Larsen (billionai) { 121937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122137f219c8SBruno Larsen (billionai) } 122237f219c8SBruno Larsen (billionai) 1223a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 122437f219c8SBruno Larsen (billionai) { 122537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 122737f219c8SBruno Larsen (billionai) } 122837f219c8SBruno Larsen (billionai) 1229a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 123037f219c8SBruno Larsen (billionai) { 123137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123237f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123337f219c8SBruno Larsen (billionai) } 123437f219c8SBruno Larsen (billionai) 1235a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 123637f219c8SBruno Larsen (billionai) { 123737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123937f219c8SBruno Larsen (billionai) } 124037f219c8SBruno Larsen (billionai) 1241a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 124237f219c8SBruno Larsen (billionai) { 124337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124437f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124537f219c8SBruno Larsen (billionai) } 124637f219c8SBruno Larsen (billionai) 1247a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 124837f219c8SBruno Larsen (billionai) { 124937f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125037f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125137f219c8SBruno Larsen (billionai) } 125237f219c8SBruno Larsen (billionai) 1253a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 125437f219c8SBruno Larsen (billionai) { 125537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125737f219c8SBruno Larsen (billionai) } 125837f219c8SBruno Larsen (billionai) 1259a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 126037f219c8SBruno Larsen (billionai) { 126137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126337f219c8SBruno Larsen (billionai) } 126437f219c8SBruno Larsen (billionai) 1265a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 126637f219c8SBruno Larsen (billionai) { 126737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 126937f219c8SBruno Larsen (billionai) } 127037f219c8SBruno Larsen (billionai) 1271a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 127237f219c8SBruno Larsen (billionai) { 127337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 127537f219c8SBruno Larsen (billionai) } 127637f219c8SBruno Larsen (billionai) #endif 127737f219c8SBruno Larsen (billionai) 1278fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1279fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1280fcf5ef2aSThomas Huth 1281fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1282fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1283fcf5ef2aSThomas Huth 1284fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1285fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1286fcf5ef2aSThomas Huth 1287fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1288fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1289fcf5ef2aSThomas Huth 1290fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1291fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1292fcf5ef2aSThomas Huth 1293fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1294fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1295fcf5ef2aSThomas Huth 1296fcf5ef2aSThomas Huth typedef struct opcode_t { 1297fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1298fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1299fcf5ef2aSThomas Huth unsigned char pad[4]; 1300fcf5ef2aSThomas Huth #endif 1301fcf5ef2aSThomas Huth opc_handler_t handler; 1302fcf5ef2aSThomas Huth const char *oname; 1303fcf5ef2aSThomas Huth } opcode_t; 1304fcf5ef2aSThomas Huth 1305fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1306fcf5ef2aSThomas Huth #define GEN_PRIV \ 1307fcf5ef2aSThomas Huth do { \ 1308fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1309fcf5ef2aSThomas Huth } while (0) 1310fcf5ef2aSThomas Huth 1311fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1312fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1313fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1314fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1315fcf5ef2aSThomas Huth #else 1316fcf5ef2aSThomas Huth #define CHK_HV \ 1317fcf5ef2aSThomas Huth do { \ 1318fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1319fcf5ef2aSThomas Huth GEN_PRIV; \ 1320fcf5ef2aSThomas Huth } \ 1321fcf5ef2aSThomas Huth } while (0) 1322fcf5ef2aSThomas Huth #define CHK_SV \ 1323fcf5ef2aSThomas Huth do { \ 1324fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1325fcf5ef2aSThomas Huth GEN_PRIV; \ 1326fcf5ef2aSThomas Huth } \ 1327fcf5ef2aSThomas Huth } while (0) 1328fcf5ef2aSThomas Huth #define CHK_HVRM \ 1329fcf5ef2aSThomas Huth do { \ 1330fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1331fcf5ef2aSThomas Huth GEN_PRIV; \ 1332fcf5ef2aSThomas Huth } \ 1333fcf5ef2aSThomas Huth } while (0) 1334fcf5ef2aSThomas Huth #endif 1335fcf5ef2aSThomas Huth 1336fcf5ef2aSThomas Huth #define CHK_NONE 1337fcf5ef2aSThomas Huth 1338fcf5ef2aSThomas Huth /*****************************************************************************/ 1339fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1340fcf5ef2aSThomas Huth 1341fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1342fcf5ef2aSThomas Huth { \ 1343fcf5ef2aSThomas Huth .opc1 = op1, \ 1344fcf5ef2aSThomas Huth .opc2 = op2, \ 1345fcf5ef2aSThomas Huth .opc3 = op3, \ 1346fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1347fcf5ef2aSThomas Huth .handler = { \ 1348fcf5ef2aSThomas Huth .inval1 = invl, \ 1349fcf5ef2aSThomas Huth .type = _typ, \ 1350fcf5ef2aSThomas Huth .type2 = _typ2, \ 1351fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1352fcf5ef2aSThomas Huth }, \ 1353fcf5ef2aSThomas Huth .oname = stringify(name), \ 1354fcf5ef2aSThomas Huth } 1355fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1356fcf5ef2aSThomas Huth { \ 1357fcf5ef2aSThomas Huth .opc1 = op1, \ 1358fcf5ef2aSThomas Huth .opc2 = op2, \ 1359fcf5ef2aSThomas Huth .opc3 = op3, \ 1360fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1361fcf5ef2aSThomas Huth .handler = { \ 1362fcf5ef2aSThomas Huth .inval1 = invl1, \ 1363fcf5ef2aSThomas Huth .inval2 = invl2, \ 1364fcf5ef2aSThomas Huth .type = _typ, \ 1365fcf5ef2aSThomas Huth .type2 = _typ2, \ 1366fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1367fcf5ef2aSThomas Huth }, \ 1368fcf5ef2aSThomas Huth .oname = stringify(name), \ 1369fcf5ef2aSThomas Huth } 1370fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1371fcf5ef2aSThomas Huth { \ 1372fcf5ef2aSThomas Huth .opc1 = op1, \ 1373fcf5ef2aSThomas Huth .opc2 = op2, \ 1374fcf5ef2aSThomas Huth .opc3 = op3, \ 1375fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1376fcf5ef2aSThomas Huth .handler = { \ 1377fcf5ef2aSThomas Huth .inval1 = invl, \ 1378fcf5ef2aSThomas Huth .type = _typ, \ 1379fcf5ef2aSThomas Huth .type2 = _typ2, \ 1380fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1381fcf5ef2aSThomas Huth }, \ 1382fcf5ef2aSThomas Huth .oname = onam, \ 1383fcf5ef2aSThomas Huth } 1384fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1385fcf5ef2aSThomas Huth { \ 1386fcf5ef2aSThomas Huth .opc1 = op1, \ 1387fcf5ef2aSThomas Huth .opc2 = op2, \ 1388fcf5ef2aSThomas Huth .opc3 = op3, \ 1389fcf5ef2aSThomas Huth .opc4 = op4, \ 1390fcf5ef2aSThomas Huth .handler = { \ 1391fcf5ef2aSThomas Huth .inval1 = invl, \ 1392fcf5ef2aSThomas Huth .type = _typ, \ 1393fcf5ef2aSThomas Huth .type2 = _typ2, \ 1394fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1395fcf5ef2aSThomas Huth }, \ 1396fcf5ef2aSThomas Huth .oname = stringify(name), \ 1397fcf5ef2aSThomas Huth } 1398fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1399fcf5ef2aSThomas Huth { \ 1400fcf5ef2aSThomas Huth .opc1 = op1, \ 1401fcf5ef2aSThomas Huth .opc2 = op2, \ 1402fcf5ef2aSThomas Huth .opc3 = op3, \ 1403fcf5ef2aSThomas Huth .opc4 = op4, \ 1404fcf5ef2aSThomas Huth .handler = { \ 1405fcf5ef2aSThomas Huth .inval1 = invl, \ 1406fcf5ef2aSThomas Huth .type = _typ, \ 1407fcf5ef2aSThomas Huth .type2 = _typ2, \ 1408fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1409fcf5ef2aSThomas Huth }, \ 1410fcf5ef2aSThomas Huth .oname = onam, \ 1411fcf5ef2aSThomas Huth } 1412fcf5ef2aSThomas Huth 1413fcf5ef2aSThomas Huth /* Invalid instruction */ 1414fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1415fcf5ef2aSThomas Huth { 1416fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth 1419fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1420fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1421fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1422fcf5ef2aSThomas Huth .type = PPC_NONE, 1423fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1424fcf5ef2aSThomas Huth .handler = gen_invalid, 1425fcf5ef2aSThomas Huth }; 1426fcf5ef2aSThomas Huth 1427fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1428fcf5ef2aSThomas Huth 1429fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1430fcf5ef2aSThomas Huth { 1431fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1432b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1433b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1434fcf5ef2aSThomas Huth 1435b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1436b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1437efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1438efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1439b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1440efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1441efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1442b62b3686Spbonzini@redhat.com 1443b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1444fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1445b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1446fcf5ef2aSThomas Huth 1447fcf5ef2aSThomas Huth tcg_temp_free(t0); 1448b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1449b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1450fcf5ef2aSThomas Huth } 1451fcf5ef2aSThomas Huth 1452fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1453fcf5ef2aSThomas Huth { 1454fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1455fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1456fcf5ef2aSThomas Huth tcg_temp_free(t0); 1457fcf5ef2aSThomas Huth } 1458fcf5ef2aSThomas Huth 1459fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1460fcf5ef2aSThomas Huth { 1461fcf5ef2aSThomas Huth TCGv t0, t1; 1462fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1463fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1464fcf5ef2aSThomas Huth if (s) { 1465fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1466fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1467fcf5ef2aSThomas Huth } else { 1468fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1469fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1470fcf5ef2aSThomas Huth } 1471fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1472fcf5ef2aSThomas Huth tcg_temp_free(t1); 1473fcf5ef2aSThomas Huth tcg_temp_free(t0); 1474fcf5ef2aSThomas Huth } 1475fcf5ef2aSThomas Huth 1476fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1477fcf5ef2aSThomas Huth { 1478fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1479fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1480fcf5ef2aSThomas Huth tcg_temp_free(t0); 1481fcf5ef2aSThomas Huth } 1482fcf5ef2aSThomas Huth 1483fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1484fcf5ef2aSThomas Huth { 1485fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1486fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1487fcf5ef2aSThomas Huth } else { 1488fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1489fcf5ef2aSThomas Huth } 1490fcf5ef2aSThomas Huth } 1491fcf5ef2aSThomas Huth 1492fcf5ef2aSThomas Huth /* cmp */ 1493fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1494fcf5ef2aSThomas Huth { 1495fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1496fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1497fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1498fcf5ef2aSThomas Huth } else { 1499fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1500fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1501fcf5ef2aSThomas Huth } 1502fcf5ef2aSThomas Huth } 1503fcf5ef2aSThomas Huth 1504fcf5ef2aSThomas Huth /* cmpi */ 1505fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1506fcf5ef2aSThomas Huth { 1507fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1508fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1509fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1510fcf5ef2aSThomas Huth } else { 1511fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1512fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1513fcf5ef2aSThomas Huth } 1514fcf5ef2aSThomas Huth } 1515fcf5ef2aSThomas Huth 1516fcf5ef2aSThomas Huth /* cmpl */ 1517fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1518fcf5ef2aSThomas Huth { 1519fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1520fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1521fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1522fcf5ef2aSThomas Huth } else { 1523fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1524fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1525fcf5ef2aSThomas Huth } 1526fcf5ef2aSThomas Huth } 1527fcf5ef2aSThomas Huth 1528fcf5ef2aSThomas Huth /* cmpli */ 1529fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1530fcf5ef2aSThomas Huth { 1531fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1532fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1533fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1534fcf5ef2aSThomas Huth } else { 1535fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1536fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1537fcf5ef2aSThomas Huth } 1538fcf5ef2aSThomas Huth } 1539fcf5ef2aSThomas Huth 1540fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1541fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1542fcf5ef2aSThomas Huth { 1543fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1544fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1545fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1546fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1547fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1548fcf5ef2aSThomas Huth 1549fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1550fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1551fcf5ef2aSThomas Huth 1552fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1553fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1554fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1555fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1556fcf5ef2aSThomas Huth 1557fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1558fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1559fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1560fcf5ef2aSThomas Huth 1561fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1562fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1563fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1564fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1565fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1566fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1567fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1568fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1569fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1570fcf5ef2aSThomas Huth } 1571efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1572fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1573fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1574fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1575fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1576fcf5ef2aSThomas Huth } 1577fcf5ef2aSThomas Huth 1578fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1579fcf5ef2aSThomas Huth /* cmpeqb */ 1580fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1581fcf5ef2aSThomas Huth { 1582fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1583fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1584fcf5ef2aSThomas Huth } 1585fcf5ef2aSThomas Huth #endif 1586fcf5ef2aSThomas Huth 1587fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1588fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1589fcf5ef2aSThomas Huth { 1590fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1591fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1592fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1593fcf5ef2aSThomas Huth TCGv zr; 1594fcf5ef2aSThomas Huth 1595fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1596fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1597fcf5ef2aSThomas Huth 1598fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1599fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1600fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1601fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1602fcf5ef2aSThomas Huth tcg_temp_free(zr); 1603fcf5ef2aSThomas Huth tcg_temp_free(t0); 1604fcf5ef2aSThomas Huth } 1605fcf5ef2aSThomas Huth 1606fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1607fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1608fcf5ef2aSThomas Huth { 1609fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1610fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1611fcf5ef2aSThomas Huth } 1612fcf5ef2aSThomas Huth 1613fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1614fcf5ef2aSThomas Huth 1615fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1616fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1617fcf5ef2aSThomas Huth { 1618fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1619fcf5ef2aSThomas Huth 1620fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1621fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1622fcf5ef2aSThomas Huth if (sub) { 1623fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1624fcf5ef2aSThomas Huth } else { 1625fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1626fcf5ef2aSThomas Huth } 1627fcf5ef2aSThomas Huth tcg_temp_free(t0); 1628fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1629dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1630dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1631dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1632fcf5ef2aSThomas Huth } 1633dc0ad844SNikunj A Dadhania } else { 1634dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1635dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1636dc0ad844SNikunj A Dadhania } 163738a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1638dc0ad844SNikunj A Dadhania } 1639fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1640fcf5ef2aSThomas Huth } 1641fcf5ef2aSThomas Huth 16426b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 16436b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 16444c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 16456b10d008SNikunj A Dadhania { 16466b10d008SNikunj A Dadhania TCGv t0; 16476b10d008SNikunj A Dadhania 16486b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16496b10d008SNikunj A Dadhania return; 16506b10d008SNikunj A Dadhania } 16516b10d008SNikunj A Dadhania 16526b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 165333903d0aSNikunj A Dadhania if (sub) { 165433903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 165533903d0aSNikunj A Dadhania } else { 16566b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 165733903d0aSNikunj A Dadhania } 16586b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16594c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16606b10d008SNikunj A Dadhania tcg_temp_free(t0); 16616b10d008SNikunj A Dadhania } 16626b10d008SNikunj A Dadhania 1663fcf5ef2aSThomas Huth /* Common add function */ 1664fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16654c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16664c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1667fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1668fcf5ef2aSThomas Huth { 1669fcf5ef2aSThomas Huth TCGv t0 = ret; 1670fcf5ef2aSThomas Huth 1671fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1672fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1673fcf5ef2aSThomas Huth } 1674fcf5ef2aSThomas Huth 1675fcf5ef2aSThomas Huth if (compute_ca) { 1676fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1677efe843d8SDavid Gibson /* 1678efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1679efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1680efe843d8SDavid Gibson * produce the carry into bit 32. 1681efe843d8SDavid Gibson */ 1682fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1683fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1684fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1685fcf5ef2aSThomas Huth if (add_ca) { 16864c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1687fcf5ef2aSThomas Huth } 16884c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1689fcf5ef2aSThomas Huth tcg_temp_free(t1); 16904c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16916b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16924c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16936b10d008SNikunj A Dadhania } 1694fcf5ef2aSThomas Huth } else { 1695fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1696fcf5ef2aSThomas Huth if (add_ca) { 16974c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16984c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1699fcf5ef2aSThomas Huth } else { 17004c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1701fcf5ef2aSThomas Huth } 17024c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1703fcf5ef2aSThomas Huth tcg_temp_free(zero); 1704fcf5ef2aSThomas Huth } 1705fcf5ef2aSThomas Huth } else { 1706fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1707fcf5ef2aSThomas Huth if (add_ca) { 17084c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1709fcf5ef2aSThomas Huth } 1710fcf5ef2aSThomas Huth } 1711fcf5ef2aSThomas Huth 1712fcf5ef2aSThomas Huth if (compute_ov) { 1713fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1714fcf5ef2aSThomas Huth } 1715fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1716fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1717fcf5ef2aSThomas Huth } 1718fcf5ef2aSThomas Huth 171911f4e8f8SRichard Henderson if (t0 != ret) { 1720fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1721fcf5ef2aSThomas Huth tcg_temp_free(t0); 1722fcf5ef2aSThomas Huth } 1723fcf5ef2aSThomas Huth } 1724fcf5ef2aSThomas Huth /* Add functions with two operands */ 17254c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1726fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1727fcf5ef2aSThomas Huth { \ 1728fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1729fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 17304c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1731fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1732fcf5ef2aSThomas Huth } 1733fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 17344c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1735fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1736fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1737fcf5ef2aSThomas Huth { \ 1738fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1739fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1740fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 17414c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1742fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1743fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1744fcf5ef2aSThomas Huth } 1745fcf5ef2aSThomas Huth 1746fcf5ef2aSThomas Huth /* add add. addo addo. */ 17474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17484c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1749fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17504c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17514c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1752fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17534c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17544c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1755fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17564c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17574c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17584c5920afSSuraj Jitindar Singh /* addex */ 17594c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1760fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17614c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17624c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1763fcf5ef2aSThomas Huth /* addi */ 1764fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 1765fcf5ef2aSThomas Huth { 1766fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1767fcf5ef2aSThomas Huth 1768fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1769fcf5ef2aSThomas Huth /* li case */ 1770fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 1771fcf5ef2aSThomas Huth } else { 1772fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1773fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 1774fcf5ef2aSThomas Huth } 1775fcf5ef2aSThomas Huth } 1776fcf5ef2aSThomas Huth /* addic addic.*/ 1777fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1778fcf5ef2aSThomas Huth { 1779fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1780fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17814c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1782fcf5ef2aSThomas Huth tcg_temp_free(c); 1783fcf5ef2aSThomas Huth } 1784fcf5ef2aSThomas Huth 1785fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1786fcf5ef2aSThomas Huth { 1787fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1788fcf5ef2aSThomas Huth } 1789fcf5ef2aSThomas Huth 1790fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1791fcf5ef2aSThomas Huth { 1792fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1793fcf5ef2aSThomas Huth } 1794fcf5ef2aSThomas Huth 1795fcf5ef2aSThomas Huth /* addis */ 1796fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 1797fcf5ef2aSThomas Huth { 1798fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1799fcf5ef2aSThomas Huth 1800fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1801fcf5ef2aSThomas Huth /* lis case */ 1802fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 1803fcf5ef2aSThomas Huth } else { 1804fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1805fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 1806fcf5ef2aSThomas Huth } 1807fcf5ef2aSThomas Huth } 1808fcf5ef2aSThomas Huth 1809fcf5ef2aSThomas Huth /* addpcis */ 1810fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 1811fcf5ef2aSThomas Huth { 1812fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 1813fcf5ef2aSThomas Huth 1814b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 1815fcf5ef2aSThomas Huth } 1816fcf5ef2aSThomas Huth 1817fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1818fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1819fcf5ef2aSThomas Huth { 1820fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1821fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1822fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1823fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1824fcf5ef2aSThomas Huth 1825fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1826fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1827fcf5ef2aSThomas Huth if (sign) { 1828fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1829fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1830fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1831fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1832fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1833fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1834fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1835fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1836fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1837fcf5ef2aSThomas Huth } else { 1838fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1839fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1840fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1841fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1842fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1843fcf5ef2aSThomas Huth } 1844fcf5ef2aSThomas Huth if (compute_ov) { 1845fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1846c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1847c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1848c44027ffSNikunj A Dadhania } 1849fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1850fcf5ef2aSThomas Huth } 1851fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1852fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1853fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1854fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1855fcf5ef2aSThomas Huth 1856efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1857fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1858fcf5ef2aSThomas Huth } 1859efe843d8SDavid Gibson } 1860fcf5ef2aSThomas Huth /* Div functions */ 1861fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1862fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1863fcf5ef2aSThomas Huth { \ 1864fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1865fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1866fcf5ef2aSThomas Huth sign, compute_ov); \ 1867fcf5ef2aSThomas Huth } 1868fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1869fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1870fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1871fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1872fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1873fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1874fcf5ef2aSThomas Huth 1875fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1876fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1877fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1878fcf5ef2aSThomas Huth { \ 1879fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1880fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1881fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1882fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1883fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1884fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1885fcf5ef2aSThomas Huth } \ 1886fcf5ef2aSThomas Huth } 1887fcf5ef2aSThomas Huth 1888fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1889fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1890fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1891fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1892fcf5ef2aSThomas Huth 1893fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1894fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1895fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1896fcf5ef2aSThomas Huth { 1897fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1898fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1899fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1900fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1901fcf5ef2aSThomas Huth 1902fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1903fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1904fcf5ef2aSThomas Huth if (sign) { 1905fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1906fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1907fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1908fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1909fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1910fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1911fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1912fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1913fcf5ef2aSThomas Huth } else { 1914fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1915fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1916fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1917fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1918fcf5ef2aSThomas Huth } 1919fcf5ef2aSThomas Huth if (compute_ov) { 1920fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1921c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1922c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1923c44027ffSNikunj A Dadhania } 1924fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1925fcf5ef2aSThomas Huth } 1926fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1927fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1928fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1929fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1930fcf5ef2aSThomas Huth 1931efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1932fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1933fcf5ef2aSThomas Huth } 1934efe843d8SDavid Gibson } 1935fcf5ef2aSThomas Huth 1936fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1937fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1938fcf5ef2aSThomas Huth { \ 1939fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1940fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1941fcf5ef2aSThomas Huth sign, compute_ov); \ 1942fcf5ef2aSThomas Huth } 1943c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1944fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1945fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1946c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1947fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1948fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1949fcf5ef2aSThomas Huth 1950fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1951fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1952fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1953fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1954fcf5ef2aSThomas Huth #endif 1955fcf5ef2aSThomas Huth 1956fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1957fcf5ef2aSThomas Huth TCGv arg2, int sign) 1958fcf5ef2aSThomas Huth { 1959fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1960fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1961fcf5ef2aSThomas Huth 1962fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1963fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1964fcf5ef2aSThomas Huth if (sign) { 1965fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1966fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1967fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1968fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1969fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1970fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1971fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1972fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1973fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1974fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1975fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1976fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1977fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1978fcf5ef2aSThomas Huth } else { 1979fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1980fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1981fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1982fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1983fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1984fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1985fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1986fcf5ef2aSThomas Huth } 1987fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1988fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1989fcf5ef2aSThomas Huth } 1990fcf5ef2aSThomas Huth 1991fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1992fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1993fcf5ef2aSThomas Huth { \ 1994fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1995fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1996fcf5ef2aSThomas Huth sign); \ 1997fcf5ef2aSThomas Huth } 1998fcf5ef2aSThomas Huth 1999fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 2000fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 2001fcf5ef2aSThomas Huth 2002fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2003fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 2004fcf5ef2aSThomas Huth TCGv arg2, int sign) 2005fcf5ef2aSThomas Huth { 2006fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2007fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2008fcf5ef2aSThomas Huth 2009fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2010fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2011fcf5ef2aSThomas Huth if (sign) { 2012fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2013fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2014fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2015fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2016fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2017fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2018fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2019fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2020fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2021fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 2022fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2023fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2024fcf5ef2aSThomas Huth } else { 2025fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 2026fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2027fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2028fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2029fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2030fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2031fcf5ef2aSThomas Huth } 2032fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2033fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2034fcf5ef2aSThomas Huth } 2035fcf5ef2aSThomas Huth 2036fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2037fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2038fcf5ef2aSThomas Huth { \ 2039fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2040fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2041fcf5ef2aSThomas Huth sign); \ 2042fcf5ef2aSThomas Huth } 2043fcf5ef2aSThomas Huth 2044fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2045fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2046fcf5ef2aSThomas Huth #endif 2047fcf5ef2aSThomas Huth 2048fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2049fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2050fcf5ef2aSThomas Huth { 2051fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2052fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2053fcf5ef2aSThomas Huth 2054fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2055fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2056fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2057fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2058fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2059fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2060efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2061fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2062fcf5ef2aSThomas Huth } 2063efe843d8SDavid Gibson } 2064fcf5ef2aSThomas Huth 2065fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2066fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2067fcf5ef2aSThomas Huth { 2068fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2069fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2070fcf5ef2aSThomas Huth 2071fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2072fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2073fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2074fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2075fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2076fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2077efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2078fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2079fcf5ef2aSThomas Huth } 2080efe843d8SDavid Gibson } 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth /* mullw mullw. */ 2083fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2084fcf5ef2aSThomas Huth { 2085fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2086fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2087fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2088fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2089fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2090fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2091fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2092fcf5ef2aSThomas Huth tcg_temp_free(t0); 2093fcf5ef2aSThomas Huth tcg_temp_free(t1); 2094fcf5ef2aSThomas Huth #else 2095fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2096fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2097fcf5ef2aSThomas Huth #endif 2098efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2099fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2100fcf5ef2aSThomas Huth } 2101efe843d8SDavid Gibson } 2102fcf5ef2aSThomas Huth 2103fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2104fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2105fcf5ef2aSThomas Huth { 2106fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2107fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2108fcf5ef2aSThomas Huth 2109fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2110fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2111fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2112fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2113fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2114fcf5ef2aSThomas Huth #else 2115fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2116fcf5ef2aSThomas Huth #endif 2117fcf5ef2aSThomas Huth 2118fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2119fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2120fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 212161aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 212261aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 212361aa9a69SNikunj A Dadhania } 2124fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2125fcf5ef2aSThomas Huth 2126fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2127fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2128efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2129fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2130fcf5ef2aSThomas Huth } 2131efe843d8SDavid Gibson } 2132fcf5ef2aSThomas Huth 2133fcf5ef2aSThomas Huth /* mulli */ 2134fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2135fcf5ef2aSThomas Huth { 2136fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2137fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2138fcf5ef2aSThomas Huth } 2139fcf5ef2aSThomas Huth 2140fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2141fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2142fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2143fcf5ef2aSThomas Huth { 2144fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2145fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2146fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2147fcf5ef2aSThomas Huth tcg_temp_free(lo); 2148fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2149fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2150fcf5ef2aSThomas Huth } 2151fcf5ef2aSThomas Huth } 2152fcf5ef2aSThomas Huth 2153fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2154fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2155fcf5ef2aSThomas Huth { 2156fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2157fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2158fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2159fcf5ef2aSThomas Huth tcg_temp_free(lo); 2160fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2161fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2162fcf5ef2aSThomas Huth } 2163fcf5ef2aSThomas Huth } 2164fcf5ef2aSThomas Huth 2165fcf5ef2aSThomas Huth /* mulld mulld. */ 2166fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2167fcf5ef2aSThomas Huth { 2168fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2169fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2170efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2171fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2172fcf5ef2aSThomas Huth } 2173efe843d8SDavid Gibson } 2174fcf5ef2aSThomas Huth 2175fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2176fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2177fcf5ef2aSThomas Huth { 2178fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2179fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2180fcf5ef2aSThomas Huth 2181fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2182fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2183fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2184fcf5ef2aSThomas Huth 2185fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2186fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 218761aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 218861aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 218961aa9a69SNikunj A Dadhania } 2190fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2191fcf5ef2aSThomas Huth 2192fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2193fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2194fcf5ef2aSThomas Huth 2195fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2196fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2197fcf5ef2aSThomas Huth } 2198fcf5ef2aSThomas Huth } 2199fcf5ef2aSThomas Huth #endif 2200fcf5ef2aSThomas Huth 2201fcf5ef2aSThomas Huth /* Common subf function */ 2202fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2203fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2204fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2205fcf5ef2aSThomas Huth { 2206fcf5ef2aSThomas Huth TCGv t0 = ret; 2207fcf5ef2aSThomas Huth 2208fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2209fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2210fcf5ef2aSThomas Huth } 2211fcf5ef2aSThomas Huth 2212fcf5ef2aSThomas Huth if (compute_ca) { 2213fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2214fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2215efe843d8SDavid Gibson /* 2216efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2217efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2218efe843d8SDavid Gibson * produce the carry into bit 32. 2219efe843d8SDavid Gibson */ 2220fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2221fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2222fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2223fcf5ef2aSThomas Huth if (add_ca) { 2224fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2225fcf5ef2aSThomas Huth } else { 2226fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2227fcf5ef2aSThomas Huth } 2228fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2229fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2230fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2231fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2232fcf5ef2aSThomas Huth tcg_temp_free(t1); 2233e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 223433903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 223533903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 223633903d0aSNikunj A Dadhania } 2237fcf5ef2aSThomas Huth } else if (add_ca) { 2238fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2239fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2240fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2241fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2242fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 22434c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2244fcf5ef2aSThomas Huth tcg_temp_free(zero); 2245fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2246fcf5ef2aSThomas Huth } else { 2247fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2248fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 22494c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2250fcf5ef2aSThomas Huth } 2251fcf5ef2aSThomas Huth } else if (add_ca) { 2252efe843d8SDavid Gibson /* 2253efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2254efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2255efe843d8SDavid Gibson */ 2256fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2257fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2258fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2259fcf5ef2aSThomas Huth } else { 2260fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2261fcf5ef2aSThomas Huth } 2262fcf5ef2aSThomas Huth 2263fcf5ef2aSThomas Huth if (compute_ov) { 2264fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2265fcf5ef2aSThomas Huth } 2266fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2267fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2268fcf5ef2aSThomas Huth } 2269fcf5ef2aSThomas Huth 227011f4e8f8SRichard Henderson if (t0 != ret) { 2271fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2272fcf5ef2aSThomas Huth tcg_temp_free(t0); 2273fcf5ef2aSThomas Huth } 2274fcf5ef2aSThomas Huth } 2275fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2276fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2277fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2278fcf5ef2aSThomas Huth { \ 2279fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2280fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2281fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2282fcf5ef2aSThomas Huth } 2283fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2284fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2285fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2286fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2287fcf5ef2aSThomas Huth { \ 2288fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2289fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2290fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2291fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2292fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2293fcf5ef2aSThomas Huth } 2294fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2295fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2296fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2297fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2298fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2299fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2300fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2301fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2302fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2303fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2304fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2305fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2306fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2307fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2308fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2309fcf5ef2aSThomas Huth 2310fcf5ef2aSThomas Huth /* subfic */ 2311fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2312fcf5ef2aSThomas Huth { 2313fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2314fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2315fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2316fcf5ef2aSThomas Huth tcg_temp_free(c); 2317fcf5ef2aSThomas Huth } 2318fcf5ef2aSThomas Huth 2319fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2320fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2321fcf5ef2aSThomas Huth { 2322fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2323fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2324fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2325fcf5ef2aSThomas Huth tcg_temp_free(zero); 2326fcf5ef2aSThomas Huth } 2327fcf5ef2aSThomas Huth 2328fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2329fcf5ef2aSThomas Huth { 23301480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 23311480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 23321480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 23331480d71cSNikunj A Dadhania } 2334fcf5ef2aSThomas Huth } 2335fcf5ef2aSThomas Huth 2336fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2337fcf5ef2aSThomas Huth { 2338fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2339fcf5ef2aSThomas Huth } 2340fcf5ef2aSThomas Huth 2341fcf5ef2aSThomas Huth /*** Integer logical ***/ 2342fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2343fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2344fcf5ef2aSThomas Huth { \ 2345fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2346fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2347fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2348fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2349fcf5ef2aSThomas Huth } 2350fcf5ef2aSThomas Huth 2351fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2352fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2353fcf5ef2aSThomas Huth { \ 2354fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2355fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2356fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2357fcf5ef2aSThomas Huth } 2358fcf5ef2aSThomas Huth 2359fcf5ef2aSThomas Huth /* and & and. */ 2360fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2361fcf5ef2aSThomas Huth /* andc & andc. */ 2362fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2363fcf5ef2aSThomas Huth 2364fcf5ef2aSThomas Huth /* andi. */ 2365fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2366fcf5ef2aSThomas Huth { 2367efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2368efe843d8SDavid Gibson UIMM(ctx->opcode)); 2369fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2370fcf5ef2aSThomas Huth } 2371fcf5ef2aSThomas Huth 2372fcf5ef2aSThomas Huth /* andis. */ 2373fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2374fcf5ef2aSThomas Huth { 2375efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2376efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2377fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2378fcf5ef2aSThomas Huth } 2379fcf5ef2aSThomas Huth 2380fcf5ef2aSThomas Huth /* cntlzw */ 2381fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2382fcf5ef2aSThomas Huth { 23839b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23849b8514e5SRichard Henderson 23859b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23869b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23879b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23889b8514e5SRichard Henderson tcg_temp_free_i32(t); 23899b8514e5SRichard Henderson 2390efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2391fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2392fcf5ef2aSThomas Huth } 2393efe843d8SDavid Gibson } 2394fcf5ef2aSThomas Huth 2395fcf5ef2aSThomas Huth /* cnttzw */ 2396fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2397fcf5ef2aSThomas Huth { 23989b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23999b8514e5SRichard Henderson 24009b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 24019b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 24029b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 24039b8514e5SRichard Henderson tcg_temp_free_i32(t); 24049b8514e5SRichard Henderson 2405fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2406fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2407fcf5ef2aSThomas Huth } 2408fcf5ef2aSThomas Huth } 2409fcf5ef2aSThomas Huth 2410fcf5ef2aSThomas Huth /* eqv & eqv. */ 2411fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2412fcf5ef2aSThomas Huth /* extsb & extsb. */ 2413fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2414fcf5ef2aSThomas Huth /* extsh & extsh. */ 2415fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2416fcf5ef2aSThomas Huth /* nand & nand. */ 2417fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2418fcf5ef2aSThomas Huth /* nor & nor. */ 2419fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2420fcf5ef2aSThomas Huth 2421fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2422fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2423fcf5ef2aSThomas Huth { 2424fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2425fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2426fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2427fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2428fcf5ef2aSThomas Huth 2429fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2430b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2431fcf5ef2aSThomas Huth } 2432fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2433fcf5ef2aSThomas Huth 2434fcf5ef2aSThomas Huth /* or & or. */ 2435fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2436fcf5ef2aSThomas Huth { 2437fcf5ef2aSThomas Huth int rs, ra, rb; 2438fcf5ef2aSThomas Huth 2439fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2440fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2441fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2442fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2443fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2444efe843d8SDavid Gibson if (rs != rb) { 2445fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2446efe843d8SDavid Gibson } else { 2447fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2448efe843d8SDavid Gibson } 2449efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2450fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2451efe843d8SDavid Gibson } 2452fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2453fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2454fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2455fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2456fcf5ef2aSThomas Huth int prio = 0; 2457fcf5ef2aSThomas Huth 2458fcf5ef2aSThomas Huth switch (rs) { 2459fcf5ef2aSThomas Huth case 1: 2460fcf5ef2aSThomas Huth /* Set process priority to low */ 2461fcf5ef2aSThomas Huth prio = 2; 2462fcf5ef2aSThomas Huth break; 2463fcf5ef2aSThomas Huth case 6: 2464fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2465fcf5ef2aSThomas Huth prio = 3; 2466fcf5ef2aSThomas Huth break; 2467fcf5ef2aSThomas Huth case 2: 2468fcf5ef2aSThomas Huth /* Set process priority to normal */ 2469fcf5ef2aSThomas Huth prio = 4; 2470fcf5ef2aSThomas Huth break; 2471fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2472fcf5ef2aSThomas Huth case 31: 2473fcf5ef2aSThomas Huth if (!ctx->pr) { 2474fcf5ef2aSThomas Huth /* Set process priority to very low */ 2475fcf5ef2aSThomas Huth prio = 1; 2476fcf5ef2aSThomas Huth } 2477fcf5ef2aSThomas Huth break; 2478fcf5ef2aSThomas Huth case 5: 2479fcf5ef2aSThomas Huth if (!ctx->pr) { 2480fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2481fcf5ef2aSThomas Huth prio = 5; 2482fcf5ef2aSThomas Huth } 2483fcf5ef2aSThomas Huth break; 2484fcf5ef2aSThomas Huth case 3: 2485fcf5ef2aSThomas Huth if (!ctx->pr) { 2486fcf5ef2aSThomas Huth /* Set process priority to high */ 2487fcf5ef2aSThomas Huth prio = 6; 2488fcf5ef2aSThomas Huth } 2489fcf5ef2aSThomas Huth break; 2490fcf5ef2aSThomas Huth case 7: 2491fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2492fcf5ef2aSThomas Huth /* Set process priority to very high */ 2493fcf5ef2aSThomas Huth prio = 7; 2494fcf5ef2aSThomas Huth } 2495fcf5ef2aSThomas Huth break; 2496fcf5ef2aSThomas Huth #endif 2497fcf5ef2aSThomas Huth default: 2498fcf5ef2aSThomas Huth break; 2499fcf5ef2aSThomas Huth } 2500fcf5ef2aSThomas Huth if (prio) { 2501fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2502fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2503fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2504fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2505fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2506fcf5ef2aSThomas Huth tcg_temp_free(t0); 2507fcf5ef2aSThomas Huth } 2508fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2509efe843d8SDavid Gibson /* 2510efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2511efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2512efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2513efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2514fcf5ef2aSThomas Huth */ 2515fcf5ef2aSThomas Huth gen_pause(ctx); 2516fcf5ef2aSThomas Huth #endif 2517fcf5ef2aSThomas Huth #endif 2518fcf5ef2aSThomas Huth } 2519fcf5ef2aSThomas Huth } 2520fcf5ef2aSThomas Huth /* orc & orc. */ 2521fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2522fcf5ef2aSThomas Huth 2523fcf5ef2aSThomas Huth /* xor & xor. */ 2524fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2525fcf5ef2aSThomas Huth { 2526fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2527efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2528efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2529efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2530efe843d8SDavid Gibson } else { 2531fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2532efe843d8SDavid Gibson } 2533efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2534fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2535fcf5ef2aSThomas Huth } 2536efe843d8SDavid Gibson } 2537fcf5ef2aSThomas Huth 2538fcf5ef2aSThomas Huth /* ori */ 2539fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2540fcf5ef2aSThomas Huth { 2541fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2542fcf5ef2aSThomas Huth 2543fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2544fcf5ef2aSThomas Huth return; 2545fcf5ef2aSThomas Huth } 2546fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2547fcf5ef2aSThomas Huth } 2548fcf5ef2aSThomas Huth 2549fcf5ef2aSThomas Huth /* oris */ 2550fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2551fcf5ef2aSThomas Huth { 2552fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2553fcf5ef2aSThomas Huth 2554fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2555fcf5ef2aSThomas Huth /* NOP */ 2556fcf5ef2aSThomas Huth return; 2557fcf5ef2aSThomas Huth } 2558efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2559efe843d8SDavid Gibson uimm << 16); 2560fcf5ef2aSThomas Huth } 2561fcf5ef2aSThomas Huth 2562fcf5ef2aSThomas Huth /* xori */ 2563fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2564fcf5ef2aSThomas Huth { 2565fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2566fcf5ef2aSThomas Huth 2567fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2568fcf5ef2aSThomas Huth /* NOP */ 2569fcf5ef2aSThomas Huth return; 2570fcf5ef2aSThomas Huth } 2571fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2572fcf5ef2aSThomas Huth } 2573fcf5ef2aSThomas Huth 2574fcf5ef2aSThomas Huth /* xoris */ 2575fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2576fcf5ef2aSThomas Huth { 2577fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2578fcf5ef2aSThomas Huth 2579fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2580fcf5ef2aSThomas Huth /* NOP */ 2581fcf5ef2aSThomas Huth return; 2582fcf5ef2aSThomas Huth } 2583efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2584efe843d8SDavid Gibson uimm << 16); 2585fcf5ef2aSThomas Huth } 2586fcf5ef2aSThomas Huth 2587fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2588fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2589fcf5ef2aSThomas Huth { 2590fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2591fcf5ef2aSThomas Huth } 2592fcf5ef2aSThomas Huth 2593fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2594fcf5ef2aSThomas Huth { 259579770002SRichard Henderson #if defined(TARGET_PPC64) 2596fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 259779770002SRichard Henderson #else 259879770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 259979770002SRichard Henderson #endif 2600fcf5ef2aSThomas Huth } 2601fcf5ef2aSThomas Huth 2602fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2603fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2604fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2605fcf5ef2aSThomas Huth { 260679770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2607fcf5ef2aSThomas Huth } 2608fcf5ef2aSThomas Huth #endif 2609fcf5ef2aSThomas Huth 2610fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2611fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2612fcf5ef2aSThomas Huth { 2613fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2614fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2615fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2616fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2617fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2618fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2619fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2620fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2621fcf5ef2aSThomas Huth tcg_temp_free(t0); 2622fcf5ef2aSThomas Huth } 2623fcf5ef2aSThomas Huth 2624fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2625fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2626fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2627fcf5ef2aSThomas Huth { 2628fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2629fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2630fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2631fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2632fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2633fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2634fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2635fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2636fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2637fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2638fcf5ef2aSThomas Huth tcg_temp_free(t0); 2639fcf5ef2aSThomas Huth } 2640fcf5ef2aSThomas Huth #endif 2641fcf5ef2aSThomas Huth 2642fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2643fcf5ef2aSThomas Huth /* bpermd */ 2644fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2645fcf5ef2aSThomas Huth { 2646fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2647fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2648fcf5ef2aSThomas Huth } 2649fcf5ef2aSThomas Huth #endif 2650fcf5ef2aSThomas Huth 2651fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2652fcf5ef2aSThomas Huth /* extsw & extsw. */ 2653fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2654fcf5ef2aSThomas Huth 2655fcf5ef2aSThomas Huth /* cntlzd */ 2656fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2657fcf5ef2aSThomas Huth { 26589b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2659efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2660fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2661fcf5ef2aSThomas Huth } 2662efe843d8SDavid Gibson } 2663fcf5ef2aSThomas Huth 2664fcf5ef2aSThomas Huth /* cnttzd */ 2665fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2666fcf5ef2aSThomas Huth { 26679b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2668fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2669fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2670fcf5ef2aSThomas Huth } 2671fcf5ef2aSThomas Huth } 2672fcf5ef2aSThomas Huth 2673fcf5ef2aSThomas Huth /* darn */ 2674fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2675fcf5ef2aSThomas Huth { 2676fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2677fcf5ef2aSThomas Huth 26787e4357f6SRichard Henderson if (l > 2) { 26797e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 26807e4357f6SRichard Henderson } else { 2681f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2682fcf5ef2aSThomas Huth if (l == 0) { 2683fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26847e4357f6SRichard Henderson } else { 2685fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2686fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26877e4357f6SRichard Henderson } 2688fcf5ef2aSThomas Huth } 2689fcf5ef2aSThomas Huth } 2690fcf5ef2aSThomas Huth #endif 2691fcf5ef2aSThomas Huth 2692fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2693fcf5ef2aSThomas Huth 2694fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2695fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2696fcf5ef2aSThomas Huth { 2697fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2698fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2699fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2700fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2701fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2702fcf5ef2aSThomas Huth 2703fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2704fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2705fcf5ef2aSThomas Huth } else { 2706fcf5ef2aSThomas Huth target_ulong mask; 2707c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2708fcf5ef2aSThomas Huth TCGv t1; 2709fcf5ef2aSThomas Huth 2710fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2711fcf5ef2aSThomas Huth mb += 32; 2712fcf5ef2aSThomas Huth me += 32; 2713fcf5ef2aSThomas Huth #endif 2714fcf5ef2aSThomas Huth mask = MASK(mb, me); 2715fcf5ef2aSThomas Huth 2716c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2717c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2718c4f6a4a3SDaniele Buono mask_in_32b = false; 2719c4f6a4a3SDaniele Buono } 2720c4f6a4a3SDaniele Buono #endif 2721fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2722c4f6a4a3SDaniele Buono if (mask_in_32b) { 2723fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2724fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2725fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2726fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2727fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2728fcf5ef2aSThomas Huth } else { 2729fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2730fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2731fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2732fcf5ef2aSThomas Huth #else 2733fcf5ef2aSThomas Huth g_assert_not_reached(); 2734fcf5ef2aSThomas Huth #endif 2735fcf5ef2aSThomas Huth } 2736fcf5ef2aSThomas Huth 2737fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2738fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2739fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2740fcf5ef2aSThomas Huth tcg_temp_free(t1); 2741fcf5ef2aSThomas Huth } 2742fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2743fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2744fcf5ef2aSThomas Huth } 2745fcf5ef2aSThomas Huth } 2746fcf5ef2aSThomas Huth 2747fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2748fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2749fcf5ef2aSThomas Huth { 2750fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2751fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27527b4d326fSRichard Henderson int sh = SH(ctx->opcode); 27537b4d326fSRichard Henderson int mb = MB(ctx->opcode); 27547b4d326fSRichard Henderson int me = ME(ctx->opcode); 27557b4d326fSRichard Henderson int len = me - mb + 1; 27567b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2757fcf5ef2aSThomas Huth 27587b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 27597b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27607b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 27617b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2762fcf5ef2aSThomas Huth } else { 2763fcf5ef2aSThomas Huth target_ulong mask; 2764c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2765fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2766fcf5ef2aSThomas Huth mb += 32; 2767fcf5ef2aSThomas Huth me += 32; 2768fcf5ef2aSThomas Huth #endif 2769fcf5ef2aSThomas Huth mask = MASK(mb, me); 2770c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2771c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2772c4f6a4a3SDaniele Buono mask_in_32b = false; 2773c4f6a4a3SDaniele Buono } 2774c4f6a4a3SDaniele Buono #endif 2775c4f6a4a3SDaniele Buono if (mask_in_32b) { 27767b4d326fSRichard Henderson if (sh == 0) { 27777b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 277894f040aaSVitaly Chikunov } else { 2779fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2780fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2781fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2782fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2783fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2784fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 278594f040aaSVitaly Chikunov } 2786fcf5ef2aSThomas Huth } else { 2787fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2788fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2789fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2790fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2791fcf5ef2aSThomas Huth #else 2792fcf5ef2aSThomas Huth g_assert_not_reached(); 2793fcf5ef2aSThomas Huth #endif 2794fcf5ef2aSThomas Huth } 2795fcf5ef2aSThomas Huth } 2796fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2797fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2798fcf5ef2aSThomas Huth } 2799fcf5ef2aSThomas Huth } 2800fcf5ef2aSThomas Huth 2801fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2802fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2803fcf5ef2aSThomas Huth { 2804fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2805fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2806fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2807fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2808fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2809fcf5ef2aSThomas Huth target_ulong mask; 2810c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2811fcf5ef2aSThomas Huth 2812fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2813fcf5ef2aSThomas Huth mb += 32; 2814fcf5ef2aSThomas Huth me += 32; 2815fcf5ef2aSThomas Huth #endif 2816fcf5ef2aSThomas Huth mask = MASK(mb, me); 2817fcf5ef2aSThomas Huth 2818c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2819c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2820c4f6a4a3SDaniele Buono mask_in_32b = false; 2821c4f6a4a3SDaniele Buono } 2822c4f6a4a3SDaniele Buono #endif 2823c4f6a4a3SDaniele Buono if (mask_in_32b) { 2824fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2825fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2826fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2827fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2828fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2829fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2830fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2831fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2832fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2833fcf5ef2aSThomas Huth } else { 2834fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2835fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2836fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2837fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2838fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2839fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2840fcf5ef2aSThomas Huth #else 2841fcf5ef2aSThomas Huth g_assert_not_reached(); 2842fcf5ef2aSThomas Huth #endif 2843fcf5ef2aSThomas Huth } 2844fcf5ef2aSThomas Huth 2845fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2846fcf5ef2aSThomas Huth 2847fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2848fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth } 2851fcf5ef2aSThomas Huth 2852fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2853fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2854fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2855fcf5ef2aSThomas Huth { \ 2856fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2857fcf5ef2aSThomas Huth } \ 2858fcf5ef2aSThomas Huth \ 2859fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2860fcf5ef2aSThomas Huth { \ 2861fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2862fcf5ef2aSThomas Huth } 2863fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2864fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2865fcf5ef2aSThomas Huth { \ 2866fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2867fcf5ef2aSThomas Huth } \ 2868fcf5ef2aSThomas Huth \ 2869fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2870fcf5ef2aSThomas Huth { \ 2871fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2872fcf5ef2aSThomas Huth } \ 2873fcf5ef2aSThomas Huth \ 2874fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2875fcf5ef2aSThomas Huth { \ 2876fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2877fcf5ef2aSThomas Huth } \ 2878fcf5ef2aSThomas Huth \ 2879fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2880fcf5ef2aSThomas Huth { \ 2881fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2882fcf5ef2aSThomas Huth } 2883fcf5ef2aSThomas Huth 2884fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2885fcf5ef2aSThomas Huth { 2886fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2887fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28887b4d326fSRichard Henderson int len = me - mb + 1; 28897b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2890fcf5ef2aSThomas Huth 28917b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28927b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28937b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28947b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2895fcf5ef2aSThomas Huth } else { 2896fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2897fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2898fcf5ef2aSThomas Huth } 2899fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2900fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2901fcf5ef2aSThomas Huth } 2902fcf5ef2aSThomas Huth } 2903fcf5ef2aSThomas Huth 2904fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2905fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2906fcf5ef2aSThomas Huth { 2907fcf5ef2aSThomas Huth uint32_t sh, mb; 2908fcf5ef2aSThomas Huth 2909fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2910fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2911fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2912fcf5ef2aSThomas Huth } 2913fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2914fcf5ef2aSThomas Huth 2915fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2916fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2917fcf5ef2aSThomas Huth { 2918fcf5ef2aSThomas Huth uint32_t sh, me; 2919fcf5ef2aSThomas Huth 2920fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2921fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2922fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2923fcf5ef2aSThomas Huth } 2924fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2925fcf5ef2aSThomas Huth 2926fcf5ef2aSThomas Huth /* rldic - rldic. */ 2927fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2928fcf5ef2aSThomas Huth { 2929fcf5ef2aSThomas Huth uint32_t sh, mb; 2930fcf5ef2aSThomas Huth 2931fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2932fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2933fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2934fcf5ef2aSThomas Huth } 2935fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2936fcf5ef2aSThomas Huth 2937fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2938fcf5ef2aSThomas Huth { 2939fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2940fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2941fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2942fcf5ef2aSThomas Huth TCGv t0; 2943fcf5ef2aSThomas Huth 2944fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2945fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2946fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2947fcf5ef2aSThomas Huth tcg_temp_free(t0); 2948fcf5ef2aSThomas Huth 2949fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2950fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2951fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2952fcf5ef2aSThomas Huth } 2953fcf5ef2aSThomas Huth } 2954fcf5ef2aSThomas Huth 2955fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2956fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2957fcf5ef2aSThomas Huth { 2958fcf5ef2aSThomas Huth uint32_t mb; 2959fcf5ef2aSThomas Huth 2960fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2961fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2962fcf5ef2aSThomas Huth } 2963fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2964fcf5ef2aSThomas Huth 2965fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2966fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2967fcf5ef2aSThomas Huth { 2968fcf5ef2aSThomas Huth uint32_t me; 2969fcf5ef2aSThomas Huth 2970fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2971fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2972fcf5ef2aSThomas Huth } 2973fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2974fcf5ef2aSThomas Huth 2975fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2976fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2977fcf5ef2aSThomas Huth { 2978fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2979fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2980fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2981fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2982fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2983fcf5ef2aSThomas Huth 2984fcf5ef2aSThomas Huth if (mb <= me) { 2985fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2986fcf5ef2aSThomas Huth } else { 2987fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2988fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2989fcf5ef2aSThomas Huth 2990fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2991fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2992fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2993fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2994fcf5ef2aSThomas Huth tcg_temp_free(t1); 2995fcf5ef2aSThomas Huth } 2996fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2997fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2998fcf5ef2aSThomas Huth } 2999fcf5ef2aSThomas Huth } 3000fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 3001fcf5ef2aSThomas Huth #endif 3002fcf5ef2aSThomas Huth 3003fcf5ef2aSThomas Huth /*** Integer shift ***/ 3004fcf5ef2aSThomas Huth 3005fcf5ef2aSThomas Huth /* slw & slw. */ 3006fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 3007fcf5ef2aSThomas Huth { 3008fcf5ef2aSThomas Huth TCGv t0, t1; 3009fcf5ef2aSThomas Huth 3010fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3011fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3012fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3013fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3014fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3015fcf5ef2aSThomas Huth #else 3016fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3017fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3018fcf5ef2aSThomas Huth #endif 3019fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3020fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3021fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3022fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3023fcf5ef2aSThomas Huth tcg_temp_free(t1); 3024fcf5ef2aSThomas Huth tcg_temp_free(t0); 3025fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 3026efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3027fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3028fcf5ef2aSThomas Huth } 3029efe843d8SDavid Gibson } 3030fcf5ef2aSThomas Huth 3031fcf5ef2aSThomas Huth /* sraw & sraw. */ 3032fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3033fcf5ef2aSThomas Huth { 3034fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3035fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3036efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3037fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3038fcf5ef2aSThomas Huth } 3039efe843d8SDavid Gibson } 3040fcf5ef2aSThomas Huth 3041fcf5ef2aSThomas Huth /* srawi & srawi. */ 3042fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3043fcf5ef2aSThomas Huth { 3044fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3045fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3046fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3047fcf5ef2aSThomas Huth if (sh == 0) { 3048fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3049fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3050af1c259fSSandipan Das if (is_isa300(ctx)) { 3051af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3052af1c259fSSandipan Das } 3053fcf5ef2aSThomas Huth } else { 3054fcf5ef2aSThomas Huth TCGv t0; 3055fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3056fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3057fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3058fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3059fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3060fcf5ef2aSThomas Huth tcg_temp_free(t0); 3061fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3062af1c259fSSandipan Das if (is_isa300(ctx)) { 3063af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3064af1c259fSSandipan Das } 3065fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3066fcf5ef2aSThomas Huth } 3067fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3068fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3069fcf5ef2aSThomas Huth } 3070fcf5ef2aSThomas Huth } 3071fcf5ef2aSThomas Huth 3072fcf5ef2aSThomas Huth /* srw & srw. */ 3073fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3074fcf5ef2aSThomas Huth { 3075fcf5ef2aSThomas Huth TCGv t0, t1; 3076fcf5ef2aSThomas Huth 3077fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3078fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3079fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3080fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3081fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3082fcf5ef2aSThomas Huth #else 3083fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3084fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3085fcf5ef2aSThomas Huth #endif 3086fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3087fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3088fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3089fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3090fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3091fcf5ef2aSThomas Huth tcg_temp_free(t1); 3092fcf5ef2aSThomas Huth tcg_temp_free(t0); 3093efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3094fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3095fcf5ef2aSThomas Huth } 3096efe843d8SDavid Gibson } 3097fcf5ef2aSThomas Huth 3098fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3099fcf5ef2aSThomas Huth /* sld & sld. */ 3100fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3101fcf5ef2aSThomas Huth { 3102fcf5ef2aSThomas Huth TCGv t0, t1; 3103fcf5ef2aSThomas Huth 3104fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3105fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3106fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3107fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3108fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3109fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3110fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3111fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3112fcf5ef2aSThomas Huth tcg_temp_free(t1); 3113fcf5ef2aSThomas Huth tcg_temp_free(t0); 3114efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3115fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3116fcf5ef2aSThomas Huth } 3117efe843d8SDavid Gibson } 3118fcf5ef2aSThomas Huth 3119fcf5ef2aSThomas Huth /* srad & srad. */ 3120fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3121fcf5ef2aSThomas Huth { 3122fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3123fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3124efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3125fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3126fcf5ef2aSThomas Huth } 3127efe843d8SDavid Gibson } 3128fcf5ef2aSThomas Huth /* sradi & sradi. */ 3129fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3130fcf5ef2aSThomas Huth { 3131fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3132fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3133fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3134fcf5ef2aSThomas Huth if (sh == 0) { 3135fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3136fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3137af1c259fSSandipan Das if (is_isa300(ctx)) { 3138af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3139af1c259fSSandipan Das } 3140fcf5ef2aSThomas Huth } else { 3141fcf5ef2aSThomas Huth TCGv t0; 3142fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3143fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3144fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3145fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3146fcf5ef2aSThomas Huth tcg_temp_free(t0); 3147fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3148af1c259fSSandipan Das if (is_isa300(ctx)) { 3149af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3150af1c259fSSandipan Das } 3151fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3152fcf5ef2aSThomas Huth } 3153fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3154fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3155fcf5ef2aSThomas Huth } 3156fcf5ef2aSThomas Huth } 3157fcf5ef2aSThomas Huth 3158fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3159fcf5ef2aSThomas Huth { 3160fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3161fcf5ef2aSThomas Huth } 3162fcf5ef2aSThomas Huth 3163fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3164fcf5ef2aSThomas Huth { 3165fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3166fcf5ef2aSThomas Huth } 3167fcf5ef2aSThomas Huth 3168fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3169fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3170fcf5ef2aSThomas Huth { 3171fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3172fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3173fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3174fcf5ef2aSThomas Huth 3175fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3176fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3177fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3178fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3179fcf5ef2aSThomas Huth } 3180fcf5ef2aSThomas Huth } 3181fcf5ef2aSThomas Huth 3182fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3183fcf5ef2aSThomas Huth { 3184fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3185fcf5ef2aSThomas Huth } 3186fcf5ef2aSThomas Huth 3187fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3188fcf5ef2aSThomas Huth { 3189fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3190fcf5ef2aSThomas Huth } 3191fcf5ef2aSThomas Huth 3192fcf5ef2aSThomas Huth /* srd & srd. */ 3193fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3194fcf5ef2aSThomas Huth { 3195fcf5ef2aSThomas Huth TCGv t0, t1; 3196fcf5ef2aSThomas Huth 3197fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3198fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3199fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3200fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3201fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3202fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3203fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3204fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3205fcf5ef2aSThomas Huth tcg_temp_free(t1); 3206fcf5ef2aSThomas Huth tcg_temp_free(t0); 3207efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3208fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3209fcf5ef2aSThomas Huth } 3210efe843d8SDavid Gibson } 3211fcf5ef2aSThomas Huth #endif 3212fcf5ef2aSThomas Huth 3213fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3214fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3215fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3216fcf5ef2aSThomas Huth target_long maskl) 3217fcf5ef2aSThomas Huth { 3218fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3219fcf5ef2aSThomas Huth 3220fcf5ef2aSThomas Huth simm &= ~maskl; 3221fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3222fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3223fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3224fcf5ef2aSThomas Huth } 3225fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3226fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3227fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3228fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3229fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3230fcf5ef2aSThomas Huth } 3231fcf5ef2aSThomas Huth } else { 3232fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3233fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3234fcf5ef2aSThomas Huth } else { 3235fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3236fcf5ef2aSThomas Huth } 3237fcf5ef2aSThomas Huth } 3238fcf5ef2aSThomas Huth } 3239fcf5ef2aSThomas Huth 3240fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3241fcf5ef2aSThomas Huth { 3242fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3243fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3244fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3245fcf5ef2aSThomas Huth } else { 3246fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3247fcf5ef2aSThomas Huth } 3248fcf5ef2aSThomas Huth } else { 3249fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3250fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3251fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3252fcf5ef2aSThomas Huth } 3253fcf5ef2aSThomas Huth } 3254fcf5ef2aSThomas Huth } 3255fcf5ef2aSThomas Huth 3256fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3257fcf5ef2aSThomas Huth { 3258fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3259fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3260fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3261fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3262fcf5ef2aSThomas Huth } else { 3263fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3264fcf5ef2aSThomas Huth } 3265fcf5ef2aSThomas Huth } 3266fcf5ef2aSThomas Huth 3267fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3268fcf5ef2aSThomas Huth target_long val) 3269fcf5ef2aSThomas Huth { 3270fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3271fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3272fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3273fcf5ef2aSThomas Huth } 3274fcf5ef2aSThomas Huth } 3275fcf5ef2aSThomas Huth 3276fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3277fcf5ef2aSThomas Huth { 3278fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3279fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3280fcf5ef2aSThomas Huth } 3281fcf5ef2aSThomas Huth 3282fcf5ef2aSThomas Huth /*** Integer load ***/ 3283fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3284fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3285fcf5ef2aSThomas Huth 3286fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3287fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3288fcf5ef2aSThomas Huth TCGv val, \ 3289fcf5ef2aSThomas Huth TCGv addr) \ 3290fcf5ef2aSThomas Huth { \ 3291fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3292fcf5ef2aSThomas Huth } 3293fcf5ef2aSThomas Huth 3294fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3295fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3296fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3297fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3298fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3299fcf5ef2aSThomas Huth 3300fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3301fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3302fcf5ef2aSThomas Huth 3303fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3304fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3305fcf5ef2aSThomas Huth TCGv_i64 val, \ 3306fcf5ef2aSThomas Huth TCGv addr) \ 3307fcf5ef2aSThomas Huth { \ 3308fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3309fcf5ef2aSThomas Huth } 3310fcf5ef2aSThomas Huth 3311fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3312fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3313fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3314fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3315fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3316fcf5ef2aSThomas Huth 3317fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3318fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3319fcf5ef2aSThomas Huth #endif 3320fcf5ef2aSThomas Huth 3321fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3322fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3323fcf5ef2aSThomas Huth TCGv val, \ 3324fcf5ef2aSThomas Huth TCGv addr) \ 3325fcf5ef2aSThomas Huth { \ 3326fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3327fcf5ef2aSThomas Huth } 3328fcf5ef2aSThomas Huth 3329fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3330fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3331fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3332fcf5ef2aSThomas Huth 3333fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3334fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3335fcf5ef2aSThomas Huth 3336fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3337fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3338fcf5ef2aSThomas Huth TCGv_i64 val, \ 3339fcf5ef2aSThomas Huth TCGv addr) \ 3340fcf5ef2aSThomas Huth { \ 3341fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3342fcf5ef2aSThomas Huth } 3343fcf5ef2aSThomas Huth 3344fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3345fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3346fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3347fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3348fcf5ef2aSThomas Huth 3349fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3350fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3351fcf5ef2aSThomas Huth #endif 3352fcf5ef2aSThomas Huth 3353fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 3354fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3355fcf5ef2aSThomas Huth { \ 3356fcf5ef2aSThomas Huth TCGv EA; \ 3357fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3358fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3359fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3360fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3361fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3362fcf5ef2aSThomas Huth } 3363fcf5ef2aSThomas Huth 3364fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 3365fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 3366fcf5ef2aSThomas Huth { \ 3367fcf5ef2aSThomas Huth TCGv EA; \ 3368fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3369fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3370fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3371fcf5ef2aSThomas Huth return; \ 3372fcf5ef2aSThomas Huth } \ 3373fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3374fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3375fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3376fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3377fcf5ef2aSThomas Huth else \ 3378fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3379fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3380fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3381fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3382fcf5ef2aSThomas Huth } 3383fcf5ef2aSThomas Huth 3384fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 3385fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3386fcf5ef2aSThomas Huth { \ 3387fcf5ef2aSThomas Huth TCGv EA; \ 3388fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3389fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3390fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3391fcf5ef2aSThomas Huth return; \ 3392fcf5ef2aSThomas Huth } \ 3393fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3394fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3395fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3396fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3397fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3398fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3399fcf5ef2aSThomas Huth } 3400fcf5ef2aSThomas Huth 3401fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3402fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3403fcf5ef2aSThomas Huth { \ 3404fcf5ef2aSThomas Huth TCGv EA; \ 3405fcf5ef2aSThomas Huth chk; \ 3406fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3407fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3408fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3409fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3410fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3411fcf5ef2aSThomas Huth } 3412fcf5ef2aSThomas Huth 3413fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3414fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3415fcf5ef2aSThomas Huth 3416fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3417fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3418fcf5ef2aSThomas Huth 3419fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 3420fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 3421fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 3422fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 3423fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 3424fcf5ef2aSThomas Huth 3425fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 3426fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 3427fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 3428fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 3429fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 3430fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 3431fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 3432fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 343350728199SRoman Kapl 343450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 343550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 343650728199SRoman Kapl { \ 343750728199SRoman Kapl TCGv EA; \ 343850728199SRoman Kapl CHK_SV; \ 343950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 344050728199SRoman Kapl EA = tcg_temp_new(); \ 344150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 344250728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 344350728199SRoman Kapl tcg_temp_free(EA); \ 344450728199SRoman Kapl } 344550728199SRoman Kapl 344650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 344750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 344850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 344950728199SRoman Kapl #if defined(TARGET_PPC64) 345050728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 345150728199SRoman Kapl #endif 345250728199SRoman Kapl 3453fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3454fcf5ef2aSThomas Huth /* lwaux */ 3455fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 3456fcf5ef2aSThomas Huth /* lwax */ 3457fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 3458fcf5ef2aSThomas Huth /* ldux */ 3459fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 3460fcf5ef2aSThomas Huth /* ldx */ 3461fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 3462fcf5ef2aSThomas Huth 3463fcf5ef2aSThomas Huth /* CI load/store variants */ 3464fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3465fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3466fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3467fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3468fcf5ef2aSThomas Huth 3469fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 3470fcf5ef2aSThomas Huth { 3471fcf5ef2aSThomas Huth TCGv EA; 3472fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3473fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 3474fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 3475fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3476fcf5ef2aSThomas Huth return; 3477fcf5ef2aSThomas Huth } 3478fcf5ef2aSThomas Huth } 3479fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3480fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3481fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3482fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 3483fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 3484fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3485fcf5ef2aSThomas Huth } else { 3486fcf5ef2aSThomas Huth /* ld - ldu */ 3487fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3488fcf5ef2aSThomas Huth } 3489efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3490fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3491efe843d8SDavid Gibson } 3492fcf5ef2aSThomas Huth tcg_temp_free(EA); 3493fcf5ef2aSThomas Huth } 3494fcf5ef2aSThomas Huth 3495fcf5ef2aSThomas Huth /* lq */ 3496fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3497fcf5ef2aSThomas Huth { 3498fcf5ef2aSThomas Huth int ra, rd; 349994bf2658SRichard Henderson TCGv EA, hi, lo; 3500fcf5ef2aSThomas Huth 3501fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3502fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3503fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3504fcf5ef2aSThomas Huth 3505fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3506fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3507fcf5ef2aSThomas Huth return; 3508fcf5ef2aSThomas Huth } 3509fcf5ef2aSThomas Huth 3510fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3511fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3512fcf5ef2aSThomas Huth return; 3513fcf5ef2aSThomas Huth } 3514fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3515fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3516fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3517fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3518fcf5ef2aSThomas Huth return; 3519fcf5ef2aSThomas Huth } 3520fcf5ef2aSThomas Huth 3521fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3522fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3523fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3524fcf5ef2aSThomas Huth 352594bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 352694bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 352794bf2658SRichard Henderson hi = cpu_gpr[rd]; 352894bf2658SRichard Henderson 352994bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3530f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 353194bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 353294bf2658SRichard Henderson if (ctx->le_mode) { 353394bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 353494bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3535fcf5ef2aSThomas Huth } else { 353694bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 353794bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 353894bf2658SRichard Henderson } 353994bf2658SRichard Henderson tcg_temp_free_i32(oi); 354094bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3541f34ec0f6SRichard Henderson } else { 354294bf2658SRichard Henderson /* Restart with exclusive lock. */ 354394bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 354494bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3545f34ec0f6SRichard Henderson } 354694bf2658SRichard Henderson } else if (ctx->le_mode) { 354794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3548fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 354994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 355094bf2658SRichard Henderson } else { 355194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 355294bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 355394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3554fcf5ef2aSThomas Huth } 3555fcf5ef2aSThomas Huth tcg_temp_free(EA); 3556fcf5ef2aSThomas Huth } 3557fcf5ef2aSThomas Huth #endif 3558fcf5ef2aSThomas Huth 3559fcf5ef2aSThomas Huth /*** Integer store ***/ 3560fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3561fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3562fcf5ef2aSThomas Huth { \ 3563fcf5ef2aSThomas Huth TCGv EA; \ 3564fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3565fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3566fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3567fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3568fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3569fcf5ef2aSThomas Huth } 3570fcf5ef2aSThomas Huth 3571fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3572fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3573fcf5ef2aSThomas Huth { \ 3574fcf5ef2aSThomas Huth TCGv EA; \ 3575fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3576fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3577fcf5ef2aSThomas Huth return; \ 3578fcf5ef2aSThomas Huth } \ 3579fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3580fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3581fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3582fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3583fcf5ef2aSThomas Huth else \ 3584fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3585fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3586fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3587fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3588fcf5ef2aSThomas Huth } 3589fcf5ef2aSThomas Huth 3590fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3591fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3592fcf5ef2aSThomas Huth { \ 3593fcf5ef2aSThomas Huth TCGv EA; \ 3594fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3595fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3596fcf5ef2aSThomas Huth return; \ 3597fcf5ef2aSThomas Huth } \ 3598fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3599fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3600fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3601fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3602fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3603fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3604fcf5ef2aSThomas Huth } 3605fcf5ef2aSThomas Huth 3606fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3607fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3608fcf5ef2aSThomas Huth { \ 3609fcf5ef2aSThomas Huth TCGv EA; \ 3610fcf5ef2aSThomas Huth chk; \ 3611fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3612fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3613fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3614fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3615fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3616fcf5ef2aSThomas Huth } 3617fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3618fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3619fcf5ef2aSThomas Huth 3620fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3621fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3622fcf5ef2aSThomas Huth 3623fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3624fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3625fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3626fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3627fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3628fcf5ef2aSThomas Huth 3629fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3630fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3631fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3632fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3633fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3634fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 363550728199SRoman Kapl 363650728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 363750728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 363850728199SRoman Kapl { \ 363950728199SRoman Kapl TCGv EA; \ 364050728199SRoman Kapl CHK_SV; \ 364150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 364250728199SRoman Kapl EA = tcg_temp_new(); \ 364350728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 364450728199SRoman Kapl tcg_gen_qemu_st_tl( \ 364550728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 364650728199SRoman Kapl tcg_temp_free(EA); \ 364750728199SRoman Kapl } 364850728199SRoman Kapl 364950728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 365050728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 365150728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 365250728199SRoman Kapl #if defined(TARGET_PPC64) 365350728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 365450728199SRoman Kapl #endif 365550728199SRoman Kapl 3656fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3657fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3658fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3659fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3660fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3661fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3662fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3663fcf5ef2aSThomas Huth 3664fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3665fcf5ef2aSThomas Huth { 3666fcf5ef2aSThomas Huth int rs; 3667fcf5ef2aSThomas Huth TCGv EA; 3668fcf5ef2aSThomas Huth 3669fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3670fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3671fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3672fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3673f89ced5fSRichard Henderson TCGv hi, lo; 3674fcf5ef2aSThomas Huth 3675fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3676fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3677fcf5ef2aSThomas Huth } 3678fcf5ef2aSThomas Huth 3679fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3680fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3681fcf5ef2aSThomas Huth return; 3682fcf5ef2aSThomas Huth } 3683fcf5ef2aSThomas Huth 3684fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3685fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3686fcf5ef2aSThomas Huth return; 3687fcf5ef2aSThomas Huth } 3688fcf5ef2aSThomas Huth 3689fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3690fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3691fcf5ef2aSThomas Huth return; 3692fcf5ef2aSThomas Huth } 3693fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3694fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3695fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3696fcf5ef2aSThomas Huth 3697f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3698f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3699f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3700f89ced5fSRichard Henderson 3701f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3702f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3703f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3704f89ced5fSRichard Henderson if (ctx->le_mode) { 3705f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3706f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3707fcf5ef2aSThomas Huth } else { 3708f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3709f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3710f89ced5fSRichard Henderson } 3711f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3712f34ec0f6SRichard Henderson } else { 3713f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3714f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3715f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3716f34ec0f6SRichard Henderson } 3717f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3718f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3719fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3720f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3721f89ced5fSRichard Henderson } else { 3722f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3723f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3724f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3725fcf5ef2aSThomas Huth } 3726fcf5ef2aSThomas Huth tcg_temp_free(EA); 3727fcf5ef2aSThomas Huth } else { 3728fcf5ef2aSThomas Huth /* std / stdu */ 3729fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3730fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3731fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3732fcf5ef2aSThomas Huth return; 3733fcf5ef2aSThomas Huth } 3734fcf5ef2aSThomas Huth } 3735fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3736fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3737fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3738fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3739efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3740fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3741efe843d8SDavid Gibson } 3742fcf5ef2aSThomas Huth tcg_temp_free(EA); 3743fcf5ef2aSThomas Huth } 3744fcf5ef2aSThomas Huth } 3745fcf5ef2aSThomas Huth #endif 3746fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3747fcf5ef2aSThomas Huth 3748fcf5ef2aSThomas Huth /* lhbrx */ 3749fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3750fcf5ef2aSThomas Huth 3751fcf5ef2aSThomas Huth /* lwbrx */ 3752fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3753fcf5ef2aSThomas Huth 3754fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3755fcf5ef2aSThomas Huth /* ldbrx */ 3756fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3757fcf5ef2aSThomas Huth /* stdbrx */ 3758fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3759fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3760fcf5ef2aSThomas Huth 3761fcf5ef2aSThomas Huth /* sthbrx */ 3762fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3763fcf5ef2aSThomas Huth /* stwbrx */ 3764fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3765fcf5ef2aSThomas Huth 3766fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3767fcf5ef2aSThomas Huth 3768fcf5ef2aSThomas Huth /* lmw */ 3769fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3770fcf5ef2aSThomas Huth { 3771fcf5ef2aSThomas Huth TCGv t0; 3772fcf5ef2aSThomas Huth TCGv_i32 t1; 3773fcf5ef2aSThomas Huth 3774fcf5ef2aSThomas Huth if (ctx->le_mode) { 3775fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3776fcf5ef2aSThomas Huth return; 3777fcf5ef2aSThomas Huth } 3778fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3779fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3780fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3781fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3782fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3783fcf5ef2aSThomas Huth tcg_temp_free(t0); 3784fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3785fcf5ef2aSThomas Huth } 3786fcf5ef2aSThomas Huth 3787fcf5ef2aSThomas Huth /* stmw */ 3788fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3789fcf5ef2aSThomas Huth { 3790fcf5ef2aSThomas Huth TCGv t0; 3791fcf5ef2aSThomas Huth TCGv_i32 t1; 3792fcf5ef2aSThomas Huth 3793fcf5ef2aSThomas Huth if (ctx->le_mode) { 3794fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3795fcf5ef2aSThomas Huth return; 3796fcf5ef2aSThomas Huth } 3797fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3798fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3799fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3800fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3801fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3802fcf5ef2aSThomas Huth tcg_temp_free(t0); 3803fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3804fcf5ef2aSThomas Huth } 3805fcf5ef2aSThomas Huth 3806fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3807fcf5ef2aSThomas Huth 3808fcf5ef2aSThomas Huth /* lswi */ 3809efe843d8SDavid Gibson /* 3810efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3811efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3812efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3813efe843d8SDavid Gibson * spec... 3814fcf5ef2aSThomas Huth */ 3815fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3816fcf5ef2aSThomas Huth { 3817fcf5ef2aSThomas Huth TCGv t0; 3818fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3819fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3820fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3821fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3822fcf5ef2aSThomas Huth int nr; 3823fcf5ef2aSThomas Huth 3824fcf5ef2aSThomas Huth if (ctx->le_mode) { 3825fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3826fcf5ef2aSThomas Huth return; 3827fcf5ef2aSThomas Huth } 3828efe843d8SDavid Gibson if (nb == 0) { 3829fcf5ef2aSThomas Huth nb = 32; 3830efe843d8SDavid Gibson } 3831f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3832fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3833fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3834fcf5ef2aSThomas Huth return; 3835fcf5ef2aSThomas Huth } 3836fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3837fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3838fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3839fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3840fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3841fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3842fcf5ef2aSThomas Huth tcg_temp_free(t0); 3843fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3844fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3845fcf5ef2aSThomas Huth } 3846fcf5ef2aSThomas Huth 3847fcf5ef2aSThomas Huth /* lswx */ 3848fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3849fcf5ef2aSThomas Huth { 3850fcf5ef2aSThomas Huth TCGv t0; 3851fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3852fcf5ef2aSThomas Huth 3853fcf5ef2aSThomas Huth if (ctx->le_mode) { 3854fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3855fcf5ef2aSThomas Huth return; 3856fcf5ef2aSThomas Huth } 3857fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3858fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3859fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3860fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3861fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3862fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3863fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3864fcf5ef2aSThomas Huth tcg_temp_free(t0); 3865fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3866fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3867fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3868fcf5ef2aSThomas Huth } 3869fcf5ef2aSThomas Huth 3870fcf5ef2aSThomas Huth /* stswi */ 3871fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3872fcf5ef2aSThomas Huth { 3873fcf5ef2aSThomas Huth TCGv t0; 3874fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3875fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3876fcf5ef2aSThomas Huth 3877fcf5ef2aSThomas Huth if (ctx->le_mode) { 3878fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3879fcf5ef2aSThomas Huth return; 3880fcf5ef2aSThomas Huth } 3881fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3882fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3883fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3884efe843d8SDavid Gibson if (nb == 0) { 3885fcf5ef2aSThomas Huth nb = 32; 3886efe843d8SDavid Gibson } 3887fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3888fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3889fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3890fcf5ef2aSThomas Huth tcg_temp_free(t0); 3891fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3892fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3893fcf5ef2aSThomas Huth } 3894fcf5ef2aSThomas Huth 3895fcf5ef2aSThomas Huth /* stswx */ 3896fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3897fcf5ef2aSThomas Huth { 3898fcf5ef2aSThomas Huth TCGv t0; 3899fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3900fcf5ef2aSThomas Huth 3901fcf5ef2aSThomas Huth if (ctx->le_mode) { 3902fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3903fcf5ef2aSThomas Huth return; 3904fcf5ef2aSThomas Huth } 3905fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3906fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3907fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3908fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3909fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3910fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3911fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3912fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3913fcf5ef2aSThomas Huth tcg_temp_free(t0); 3914fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3915fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3916fcf5ef2aSThomas Huth } 3917fcf5ef2aSThomas Huth 3918fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3919fcf5ef2aSThomas Huth /* eieio */ 3920fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3921fcf5ef2aSThomas Huth { 3922c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3923c8fd8373SCédric Le Goater 3924c8fd8373SCédric Le Goater /* 3925c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3926c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3927c8fd8373SCédric Le Goater */ 3928c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3929c8fd8373SCédric Le Goater /* 3930c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3931c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3932c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3933c8fd8373SCédric Le Goater * complain to the user. 3934c8fd8373SCédric Le Goater */ 3935c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3936c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 39372c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3938c8fd8373SCédric Le Goater } else { 3939c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3940c8fd8373SCédric Le Goater } 3941c8fd8373SCédric Le Goater } 3942c8fd8373SCédric Le Goater 3943c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3944fcf5ef2aSThomas Huth } 3945fcf5ef2aSThomas Huth 3946fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3947fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3948fcf5ef2aSThomas Huth { 3949fcf5ef2aSThomas Huth TCGv_i32 t; 3950fcf5ef2aSThomas Huth TCGLabel *l; 3951fcf5ef2aSThomas Huth 3952fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3953fcf5ef2aSThomas Huth return; 3954fcf5ef2aSThomas Huth } 3955fcf5ef2aSThomas Huth l = gen_new_label(); 3956fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3957fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3958fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3959fcf5ef2aSThomas Huth if (global) { 3960fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3961fcf5ef2aSThomas Huth } else { 3962fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3963fcf5ef2aSThomas Huth } 3964fcf5ef2aSThomas Huth gen_set_label(l); 3965fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3966fcf5ef2aSThomas Huth } 3967fcf5ef2aSThomas Huth #else 3968fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3969fcf5ef2aSThomas Huth #endif 3970fcf5ef2aSThomas Huth 3971fcf5ef2aSThomas Huth /* isync */ 3972fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3973fcf5ef2aSThomas Huth { 3974fcf5ef2aSThomas Huth /* 3975fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3976fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3977fcf5ef2aSThomas Huth */ 3978fcf5ef2aSThomas Huth if (!ctx->pr) { 3979fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3980fcf5ef2aSThomas Huth } 39814771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3982d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3983fcf5ef2aSThomas Huth } 3984fcf5ef2aSThomas Huth 3985fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3986fcf5ef2aSThomas Huth 398714776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 39882a4e6c1bSRichard Henderson { 39892a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 39902a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 39912a4e6c1bSRichard Henderson 39922a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 39932a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 39942a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 39952a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 39962a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 39972a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 39982a4e6c1bSRichard Henderson tcg_temp_free(t0); 39992a4e6c1bSRichard Henderson } 40002a4e6c1bSRichard Henderson 4001fcf5ef2aSThomas Huth #define LARX(name, memop) \ 4002fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4003fcf5ef2aSThomas Huth { \ 40042a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 4005fcf5ef2aSThomas Huth } 4006fcf5ef2aSThomas Huth 4007fcf5ef2aSThomas Huth /* lwarx */ 4008fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 4009fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 4010fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 4011fcf5ef2aSThomas Huth 401214776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 401320923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 401420923c1dSRichard Henderson { 401520923c1dSRichard Henderson TCGv t = tcg_temp_new(); 401620923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 401720923c1dSRichard Henderson TCGv u = tcg_temp_new(); 401820923c1dSRichard Henderson 401920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 402020923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 402120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 402220923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 402320923c1dSRichard Henderson 402420923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 402520923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 402620923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 402720923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 402820923c1dSRichard Henderson 402920923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 403020923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 403120923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 403220923c1dSRichard Henderson 403320923c1dSRichard Henderson tcg_temp_free(t); 403420923c1dSRichard Henderson tcg_temp_free(t2); 403520923c1dSRichard Henderson tcg_temp_free(u); 403620923c1dSRichard Henderson } 403720923c1dSRichard Henderson 403814776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 403920ba8504SRichard Henderson { 404020ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 404120ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 404220923c1dSRichard Henderson int rt = rD(ctx->opcode); 404320923c1dSRichard Henderson bool need_serial; 404420ba8504SRichard Henderson TCGv src, dst; 404520ba8504SRichard Henderson 404620ba8504SRichard Henderson gen_addr_register(ctx, EA); 404720923c1dSRichard Henderson dst = cpu_gpr[rt]; 404820923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 404920ba8504SRichard Henderson 405020923c1dSRichard Henderson need_serial = false; 405120ba8504SRichard Henderson memop |= MO_ALIGN; 405220ba8504SRichard Henderson switch (gpr_FC) { 405320ba8504SRichard Henderson case 0: /* Fetch and add */ 405420ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 405520ba8504SRichard Henderson break; 405620ba8504SRichard Henderson case 1: /* Fetch and xor */ 405720ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 405820ba8504SRichard Henderson break; 405920ba8504SRichard Henderson case 2: /* Fetch and or */ 406020ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 406120ba8504SRichard Henderson break; 406220ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 406320ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 406420ba8504SRichard Henderson break; 4065b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 4066b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 4067b8ce0f86SRichard Henderson break; 4068b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 4069b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 4070b8ce0f86SRichard Henderson break; 4071b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 4072b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 4073b8ce0f86SRichard Henderson break; 4074b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 4075b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 4076b8ce0f86SRichard Henderson break; 407720ba8504SRichard Henderson case 8: /* Swap */ 407820ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 407920ba8504SRichard Henderson break; 408020923c1dSRichard Henderson 408120923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 408220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 408320923c1dSRichard Henderson need_serial = true; 408420923c1dSRichard Henderson } else { 408520923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 408620923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 408720923c1dSRichard Henderson 408820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 408920923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 409020923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 409120923c1dSRichard Henderson } else { 409220923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 409320923c1dSRichard Henderson } 409420923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 409520923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 409620923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 409720923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 409820923c1dSRichard Henderson 409920923c1dSRichard Henderson tcg_temp_free(t0); 410020923c1dSRichard Henderson tcg_temp_free(t1); 410120923c1dSRichard Henderson } 410220ba8504SRichard Henderson break; 410320923c1dSRichard Henderson 410420923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 410520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 410620923c1dSRichard Henderson need_serial = true; 410720923c1dSRichard Henderson } else { 410820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 410920923c1dSRichard Henderson } 411020923c1dSRichard Henderson break; 411120923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 411220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 411320923c1dSRichard Henderson need_serial = true; 411420923c1dSRichard Henderson } else { 411520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 411620923c1dSRichard Henderson } 411720923c1dSRichard Henderson break; 411820923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 411920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 412020923c1dSRichard Henderson need_serial = true; 412120923c1dSRichard Henderson } else { 412220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 412320923c1dSRichard Henderson } 412420923c1dSRichard Henderson break; 412520923c1dSRichard Henderson 412620ba8504SRichard Henderson default: 412720ba8504SRichard Henderson /* invoke data storage error handler */ 412820ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 412920ba8504SRichard Henderson } 413020ba8504SRichard Henderson tcg_temp_free(EA); 413120923c1dSRichard Henderson 413220923c1dSRichard Henderson if (need_serial) { 413320923c1dSRichard Henderson /* Restart with exclusive lock. */ 413420923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 413520923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 413620923c1dSRichard Henderson } 4137a68a6146SBalamuruhan S } 4138a68a6146SBalamuruhan S 413920ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 414020ba8504SRichard Henderson { 414120ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 414220ba8504SRichard Henderson } 414320ba8504SRichard Henderson 414420ba8504SRichard Henderson #ifdef TARGET_PPC64 414520ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 414620ba8504SRichard Henderson { 414720ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 414820ba8504SRichard Henderson } 4149a68a6146SBalamuruhan S #endif 4150a68a6146SBalamuruhan S 415114776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 41529deb041cSRichard Henderson { 41539deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 41549deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 41559deb041cSRichard Henderson TCGv src, discard; 41569deb041cSRichard Henderson 41579deb041cSRichard Henderson gen_addr_register(ctx, EA); 41589deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 41599deb041cSRichard Henderson discard = tcg_temp_new(); 41609deb041cSRichard Henderson 41619deb041cSRichard Henderson memop |= MO_ALIGN; 41629deb041cSRichard Henderson switch (gpr_FC) { 41639deb041cSRichard Henderson case 0: /* add and Store */ 41649deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 41659deb041cSRichard Henderson break; 41669deb041cSRichard Henderson case 1: /* xor and Store */ 41679deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 41689deb041cSRichard Henderson break; 41699deb041cSRichard Henderson case 2: /* Or and Store */ 41709deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 41719deb041cSRichard Henderson break; 41729deb041cSRichard Henderson case 3: /* 'and' and Store */ 41739deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 41749deb041cSRichard Henderson break; 41759deb041cSRichard Henderson case 4: /* Store max unsigned */ 4176b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4177b8ce0f86SRichard Henderson break; 41789deb041cSRichard Henderson case 5: /* Store max signed */ 4179b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4180b8ce0f86SRichard Henderson break; 41819deb041cSRichard Henderson case 6: /* Store min unsigned */ 4182b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4183b8ce0f86SRichard Henderson break; 41849deb041cSRichard Henderson case 7: /* Store min signed */ 4185b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4186b8ce0f86SRichard Henderson break; 41879deb041cSRichard Henderson case 24: /* Store twin */ 41887fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 41897fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 41907fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 41917fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 41927fbc2b20SRichard Henderson } else { 41937fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 41947fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 41957fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 41967fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 41977fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 41987fbc2b20SRichard Henderson 41997fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 42007fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 42017fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 42027fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 42037fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 42047fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 42057fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 42067fbc2b20SRichard Henderson 42077fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 42087fbc2b20SRichard Henderson tcg_temp_free(s2); 42097fbc2b20SRichard Henderson tcg_temp_free(s); 42107fbc2b20SRichard Henderson tcg_temp_free(t2); 42117fbc2b20SRichard Henderson tcg_temp_free(t); 42127fbc2b20SRichard Henderson } 42139deb041cSRichard Henderson break; 42149deb041cSRichard Henderson default: 42159deb041cSRichard Henderson /* invoke data storage error handler */ 42169deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 42179deb041cSRichard Henderson } 42189deb041cSRichard Henderson tcg_temp_free(discard); 42199deb041cSRichard Henderson tcg_temp_free(EA); 4220a3401188SBalamuruhan S } 4221a3401188SBalamuruhan S 42229deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 42239deb041cSRichard Henderson { 42249deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 42259deb041cSRichard Henderson } 42269deb041cSRichard Henderson 42279deb041cSRichard Henderson #ifdef TARGET_PPC64 42289deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 42299deb041cSRichard Henderson { 42309deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 42319deb041cSRichard Henderson } 4232a3401188SBalamuruhan S #endif 4233a3401188SBalamuruhan S 423414776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4235fcf5ef2aSThomas Huth { 4236253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4237253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4238d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4239d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4240fcf5ef2aSThomas Huth 4241d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4242d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4243d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4244d8b86898SRichard Henderson tcg_temp_free(t0); 4245253ce7b2SNikunj A Dadhania 4246253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4247253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4248253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4249253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4250253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4251253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4252253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4253253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4254253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4255253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4256253ce7b2SNikunj A Dadhania 4257fcf5ef2aSThomas Huth gen_set_label(l1); 42584771df23SNikunj A Dadhania 4259efe843d8SDavid Gibson /* 4260efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4261efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4262efe843d8SDavid Gibson */ 42634771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4264253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4265253ce7b2SNikunj A Dadhania 4266253ce7b2SNikunj A Dadhania gen_set_label(l2); 4267fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4268fcf5ef2aSThomas Huth } 4269fcf5ef2aSThomas Huth 4270fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4271fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4272fcf5ef2aSThomas Huth { \ 4273d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4274fcf5ef2aSThomas Huth } 4275fcf5ef2aSThomas Huth 4276fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4277fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4278fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4279fcf5ef2aSThomas Huth 4280fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4281fcf5ef2aSThomas Huth /* ldarx */ 4282fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4283fcf5ef2aSThomas Huth /* stdcx. */ 4284fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4285fcf5ef2aSThomas Huth 4286fcf5ef2aSThomas Huth /* lqarx */ 4287fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4288fcf5ef2aSThomas Huth { 4289fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 429094bf2658SRichard Henderson TCGv EA, hi, lo; 4291fcf5ef2aSThomas Huth 4292fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4293fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4294fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4295fcf5ef2aSThomas Huth return; 4296fcf5ef2aSThomas Huth } 4297fcf5ef2aSThomas Huth 4298fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 429994bf2658SRichard Henderson EA = tcg_temp_new(); 4300fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 430194bf2658SRichard Henderson 430294bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 430394bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 430494bf2658SRichard Henderson hi = cpu_gpr[rd]; 430594bf2658SRichard Henderson 430694bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4307f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 430894bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 430994bf2658SRichard Henderson if (ctx->le_mode) { 431094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 431194bf2658SRichard Henderson ctx->mem_idx)); 431294bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4313fcf5ef2aSThomas Huth } else { 431494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 431594bf2658SRichard Henderson ctx->mem_idx)); 431694bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4317fcf5ef2aSThomas Huth } 431894bf2658SRichard Henderson tcg_temp_free_i32(oi); 431994bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4320f34ec0f6SRichard Henderson } else { 432194bf2658SRichard Henderson /* Restart with exclusive lock. */ 432294bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 432394bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 432494bf2658SRichard Henderson tcg_temp_free(EA); 432594bf2658SRichard Henderson return; 4326f34ec0f6SRichard Henderson } 432794bf2658SRichard Henderson } else if (ctx->le_mode) { 432894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4329fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4330fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 433194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 433294bf2658SRichard Henderson } else { 433394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 433494bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 433594bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 433694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 433794bf2658SRichard Henderson } 4338fcf5ef2aSThomas Huth tcg_temp_free(EA); 433994bf2658SRichard Henderson 434094bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 434194bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4342fcf5ef2aSThomas Huth } 4343fcf5ef2aSThomas Huth 4344fcf5ef2aSThomas Huth /* stqcx. */ 4345fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4346fcf5ef2aSThomas Huth { 43474a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 43484a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4349fcf5ef2aSThomas Huth 43504a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4351fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4352fcf5ef2aSThomas Huth return; 4353fcf5ef2aSThomas Huth } 43544a9b3c5dSRichard Henderson 4355fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 43564a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4357fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4358fcf5ef2aSThomas Huth 43594a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 43604a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 43614a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4362fcf5ef2aSThomas Huth 43634a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4364f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 43654a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 43664a9b3c5dSRichard Henderson if (ctx->le_mode) { 4367f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4368f34ec0f6SRichard Henderson EA, lo, hi, oi); 4369fcf5ef2aSThomas Huth } else { 4370f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4371f34ec0f6SRichard Henderson EA, lo, hi, oi); 4372fcf5ef2aSThomas Huth } 4373f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4374f34ec0f6SRichard Henderson } else { 43754a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 43764a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 43774a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4378f34ec0f6SRichard Henderson } 4379fcf5ef2aSThomas Huth tcg_temp_free(EA); 43804a9b3c5dSRichard Henderson } else { 43814a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 43824a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 43834a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 43844a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4385fcf5ef2aSThomas Huth 43864a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 43874a9b3c5dSRichard Henderson tcg_temp_free(EA); 43884a9b3c5dSRichard Henderson 43894a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 43904a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 43914a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 43924a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 43934a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 43944a9b3c5dSRichard Henderson 43954a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 43964a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 43974a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 43984a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 43994a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 44004a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 44014a9b3c5dSRichard Henderson 44024a9b3c5dSRichard Henderson /* Success */ 44034a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 44044a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 44054a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 44064a9b3c5dSRichard Henderson 44074a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 44084a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 44094a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 44104a9b3c5dSRichard Henderson 44114a9b3c5dSRichard Henderson gen_set_label(lab_fail); 44124a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 44134a9b3c5dSRichard Henderson 44144a9b3c5dSRichard Henderson gen_set_label(lab_over); 44154a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 44164a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 44174a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 44184a9b3c5dSRichard Henderson } 44194a9b3c5dSRichard Henderson } 4420fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4421fcf5ef2aSThomas Huth 4422fcf5ef2aSThomas Huth /* sync */ 4423fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4424fcf5ef2aSThomas Huth { 4425fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4426fcf5ef2aSThomas Huth 4427fcf5ef2aSThomas Huth /* 4428fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4429fcf5ef2aSThomas Huth * 4430fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4431fcf5ef2aSThomas Huth * 4432fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4433fcf5ef2aSThomas Huth * check MSR_PR as well. 4434fcf5ef2aSThomas Huth */ 4435fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4436fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4437fcf5ef2aSThomas Huth } 44384771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4439fcf5ef2aSThomas Huth } 4440fcf5ef2aSThomas Huth 4441fcf5ef2aSThomas Huth /* wait */ 4442fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4443fcf5ef2aSThomas Huth { 4444fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4445fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4446fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4447fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4448fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4449b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4450fcf5ef2aSThomas Huth } 4451fcf5ef2aSThomas Huth 4452fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4453fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4454fcf5ef2aSThomas Huth { 4455fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4456fcf5ef2aSThomas Huth GEN_PRIV; 4457fcf5ef2aSThomas Huth #else 4458fcf5ef2aSThomas Huth TCGv_i32 t; 4459fcf5ef2aSThomas Huth 4460fcf5ef2aSThomas Huth CHK_HV; 4461fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4462fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4463fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4464154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4465154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4466fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4467fcf5ef2aSThomas Huth } 4468fcf5ef2aSThomas Huth 4469fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4470fcf5ef2aSThomas Huth { 4471fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4472fcf5ef2aSThomas Huth GEN_PRIV; 4473fcf5ef2aSThomas Huth #else 4474fcf5ef2aSThomas Huth TCGv_i32 t; 4475fcf5ef2aSThomas Huth 4476fcf5ef2aSThomas Huth CHK_HV; 4477fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4478fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4479fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4480154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4481154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4482fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4483fcf5ef2aSThomas Huth } 4484fcf5ef2aSThomas Huth 4485cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4486cdee0e72SNikunj A Dadhania { 448721c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 448821c0d66aSBenjamin Herrenschmidt GEN_PRIV; 448921c0d66aSBenjamin Herrenschmidt #else 449021c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 449121c0d66aSBenjamin Herrenschmidt 449221c0d66aSBenjamin Herrenschmidt CHK_HV; 449321c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 449421c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 449521c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 449621c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 449721c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 449821c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4499cdee0e72SNikunj A Dadhania } 4500cdee0e72SNikunj A Dadhania 4501fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4502fcf5ef2aSThomas Huth { 4503fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4504fcf5ef2aSThomas Huth GEN_PRIV; 4505fcf5ef2aSThomas Huth #else 4506fcf5ef2aSThomas Huth TCGv_i32 t; 4507fcf5ef2aSThomas Huth 4508fcf5ef2aSThomas Huth CHK_HV; 4509fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4510fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4511fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4512154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4513154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4514fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4515fcf5ef2aSThomas Huth } 4516fcf5ef2aSThomas Huth 4517fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4518fcf5ef2aSThomas Huth { 4519fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4520fcf5ef2aSThomas Huth GEN_PRIV; 4521fcf5ef2aSThomas Huth #else 4522fcf5ef2aSThomas Huth TCGv_i32 t; 4523fcf5ef2aSThomas Huth 4524fcf5ef2aSThomas Huth CHK_HV; 4525fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4526fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4527fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4528154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4529154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4530fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4531fcf5ef2aSThomas Huth } 4532fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4533fcf5ef2aSThomas Huth 4534fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4535fcf5ef2aSThomas Huth { 4536fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4537efe843d8SDavid Gibson if (ctx->has_cfar) { 4538fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4539efe843d8SDavid Gibson } 4540fcf5ef2aSThomas Huth #endif 4541fcf5ef2aSThomas Huth } 4542fcf5ef2aSThomas Huth 4543fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4544fcf5ef2aSThomas Huth { 4545fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4546fcf5ef2aSThomas Huth return false; 4547fcf5ef2aSThomas Huth } 4548fcf5ef2aSThomas Huth 4549fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4550b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4551fcf5ef2aSThomas Huth #else 4552fcf5ef2aSThomas Huth return true; 4553fcf5ef2aSThomas Huth #endif 4554fcf5ef2aSThomas Huth } 4555fcf5ef2aSThomas Huth 45560e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 45570e3bf489SRoman Kapl { 45580e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 45590e3bf489SRoman Kapl if (unlikely(sse)) { 45600e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 45610e3bf489SRoman Kapl gen_debug_exception(ctx); 45620e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4563e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 45640e3bf489SRoman Kapl gen_exception(ctx, excp); 45650032dbdbSRichard Henderson } else { 45660e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 45670032dbdbSRichard Henderson } 45680e3bf489SRoman Kapl } else { 45690e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 45700e3bf489SRoman Kapl } 45710e3bf489SRoman Kapl } 45720e3bf489SRoman Kapl 4573fcf5ef2aSThomas Huth /*** Branch ***/ 4574c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4575fcf5ef2aSThomas Huth { 4576fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4577fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4578fcf5ef2aSThomas Huth } 4579fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4580fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4581fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 458207ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4583fcf5ef2aSThomas Huth } else { 4584fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 45850e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4586fcf5ef2aSThomas Huth } 4587fcf5ef2aSThomas Huth } 4588fcf5ef2aSThomas Huth 4589fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4590fcf5ef2aSThomas Huth { 4591fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4592fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4593fcf5ef2aSThomas Huth } 4594fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4595fcf5ef2aSThomas Huth } 4596fcf5ef2aSThomas Huth 4597fcf5ef2aSThomas Huth /* b ba bl bla */ 4598fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4599fcf5ef2aSThomas Huth { 4600fcf5ef2aSThomas Huth target_ulong li, target; 4601fcf5ef2aSThomas Huth 4602fcf5ef2aSThomas Huth /* sign extend LI */ 4603fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4604fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4605fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 46062c2bcb1bSRichard Henderson target = ctx->cia + li; 4607fcf5ef2aSThomas Huth } else { 4608fcf5ef2aSThomas Huth target = li; 4609fcf5ef2aSThomas Huth } 4610fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4611b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4612fcf5ef2aSThomas Huth } 46132c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4614fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 46156086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4616fcf5ef2aSThomas Huth } 4617fcf5ef2aSThomas Huth 4618fcf5ef2aSThomas Huth #define BCOND_IM 0 4619fcf5ef2aSThomas Huth #define BCOND_LR 1 4620fcf5ef2aSThomas Huth #define BCOND_CTR 2 4621fcf5ef2aSThomas Huth #define BCOND_TAR 3 4622fcf5ef2aSThomas Huth 4623c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4624fcf5ef2aSThomas Huth { 4625fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4626fcf5ef2aSThomas Huth TCGLabel *l1; 4627fcf5ef2aSThomas Huth TCGv target; 46280e3bf489SRoman Kapl 4629fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4630fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4631efe843d8SDavid Gibson if (type == BCOND_CTR) { 4632fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4633efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4634fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4635efe843d8SDavid Gibson } else { 4636fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4637efe843d8SDavid Gibson } 4638fcf5ef2aSThomas Huth } else { 4639f764718dSRichard Henderson target = NULL; 4640fcf5ef2aSThomas Huth } 4641efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4642b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4643efe843d8SDavid Gibson } 4644fcf5ef2aSThomas Huth l1 = gen_new_label(); 4645fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4646fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4647fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4648fa200c95SGreg Kurz 4649fa200c95SGreg Kurz if (type == BCOND_CTR) { 4650fa200c95SGreg Kurz /* 4651fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4652fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4653fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 465415d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 465515d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 465615d68c5eSGreg Kurz * it basically useless and thus never used in real code. 465715d68c5eSGreg Kurz * 465815d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 465915d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 466015d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 466115d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 466215d68c5eSGreg Kurz * doing anything else harmful. 4663fa200c95SGreg Kurz */ 4664d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4665fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 46669acc95cdSGreg Kurz tcg_temp_free(temp); 46679acc95cdSGreg Kurz tcg_temp_free(target); 4668fcf5ef2aSThomas Huth return; 4669fcf5ef2aSThomas Huth } 4670fa200c95SGreg Kurz 4671fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4672fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4673fa200c95SGreg Kurz } else { 4674fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4675fa200c95SGreg Kurz } 4676fa200c95SGreg Kurz if (bo & 0x2) { 4677fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4678fa200c95SGreg Kurz } else { 4679fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4680fa200c95SGreg Kurz } 4681fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4682fa200c95SGreg Kurz } else { 4683fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4684fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4685fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4686fcf5ef2aSThomas Huth } else { 4687fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4688fcf5ef2aSThomas Huth } 4689fcf5ef2aSThomas Huth if (bo & 0x2) { 4690fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4691fcf5ef2aSThomas Huth } else { 4692fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4693fcf5ef2aSThomas Huth } 4694fa200c95SGreg Kurz } 4695fcf5ef2aSThomas Huth tcg_temp_free(temp); 4696fcf5ef2aSThomas Huth } 4697fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4698fcf5ef2aSThomas Huth /* Test CR */ 4699fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4700fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4701fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4702fcf5ef2aSThomas Huth 4703fcf5ef2aSThomas Huth if (bo & 0x8) { 4704fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4705fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4706fcf5ef2aSThomas Huth } else { 4707fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4708fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4709fcf5ef2aSThomas Huth } 4710fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4711fcf5ef2aSThomas Huth } 47122c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4713fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4714fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4715fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 47162c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4717fcf5ef2aSThomas Huth } else { 4718fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4719fcf5ef2aSThomas Huth } 4720fcf5ef2aSThomas Huth } else { 4721fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4722fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4723fcf5ef2aSThomas Huth } else { 4724fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4725fcf5ef2aSThomas Huth } 47260e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4727c4a2e3a9SRichard Henderson tcg_temp_free(target); 4728c4a2e3a9SRichard Henderson } 4729fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 47300e3bf489SRoman Kapl /* fallthrough case */ 4731fcf5ef2aSThomas Huth gen_set_label(l1); 4732b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4733fcf5ef2aSThomas Huth } 47346086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4735fcf5ef2aSThomas Huth } 4736fcf5ef2aSThomas Huth 4737fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4738fcf5ef2aSThomas Huth { 4739fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4740fcf5ef2aSThomas Huth } 4741fcf5ef2aSThomas Huth 4742fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4743fcf5ef2aSThomas Huth { 4744fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4745fcf5ef2aSThomas Huth } 4746fcf5ef2aSThomas Huth 4747fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4748fcf5ef2aSThomas Huth { 4749fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4750fcf5ef2aSThomas Huth } 4751fcf5ef2aSThomas Huth 4752fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4753fcf5ef2aSThomas Huth { 4754fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4755fcf5ef2aSThomas Huth } 4756fcf5ef2aSThomas Huth 4757fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4758fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4759fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4760fcf5ef2aSThomas Huth { \ 4761fcf5ef2aSThomas Huth uint8_t bitmask; \ 4762fcf5ef2aSThomas Huth int sh; \ 4763fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4764fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4765fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4766fcf5ef2aSThomas Huth if (sh > 0) \ 4767fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4768fcf5ef2aSThomas Huth else if (sh < 0) \ 4769fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4770fcf5ef2aSThomas Huth else \ 4771fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4772fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4773fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4774fcf5ef2aSThomas Huth if (sh > 0) \ 4775fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4776fcf5ef2aSThomas Huth else if (sh < 0) \ 4777fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4778fcf5ef2aSThomas Huth else \ 4779fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4780fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4781fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4782fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4783fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4784fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4785fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4786fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4787fcf5ef2aSThomas Huth } 4788fcf5ef2aSThomas Huth 4789fcf5ef2aSThomas Huth /* crand */ 4790fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4791fcf5ef2aSThomas Huth /* crandc */ 4792fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4793fcf5ef2aSThomas Huth /* creqv */ 4794fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4795fcf5ef2aSThomas Huth /* crnand */ 4796fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4797fcf5ef2aSThomas Huth /* crnor */ 4798fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4799fcf5ef2aSThomas Huth /* cror */ 4800fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4801fcf5ef2aSThomas Huth /* crorc */ 4802fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4803fcf5ef2aSThomas Huth /* crxor */ 4804fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4805fcf5ef2aSThomas Huth 4806fcf5ef2aSThomas Huth /* mcrf */ 4807fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4808fcf5ef2aSThomas Huth { 4809fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4810fcf5ef2aSThomas Huth } 4811fcf5ef2aSThomas Huth 4812fcf5ef2aSThomas Huth /*** System linkage ***/ 4813fcf5ef2aSThomas Huth 4814fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4815fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4816fcf5ef2aSThomas Huth { 4817fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4818fcf5ef2aSThomas Huth GEN_PRIV; 4819fcf5ef2aSThomas Huth #else 4820efe843d8SDavid Gibson /* 4821efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4822fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4823fcf5ef2aSThomas Huth */ 4824d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4825fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4826fcf5ef2aSThomas Huth return; 4827fcf5ef2aSThomas Huth } 4828fcf5ef2aSThomas Huth /* Restore CPU state */ 4829fcf5ef2aSThomas Huth CHK_SV; 4830f5b6daacSRichard Henderson gen_icount_io_start(ctx); 48312c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4832fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 483359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4834fcf5ef2aSThomas Huth #endif 4835fcf5ef2aSThomas Huth } 4836fcf5ef2aSThomas Huth 4837fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4838fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4839fcf5ef2aSThomas Huth { 4840fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4841fcf5ef2aSThomas Huth GEN_PRIV; 4842fcf5ef2aSThomas Huth #else 4843fcf5ef2aSThomas Huth /* Restore CPU state */ 4844fcf5ef2aSThomas Huth CHK_SV; 4845f5b6daacSRichard Henderson gen_icount_io_start(ctx); 48462c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4847fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 484859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4849fcf5ef2aSThomas Huth #endif 4850fcf5ef2aSThomas Huth } 4851fcf5ef2aSThomas Huth 48523c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 48533c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 48543c89b8d6SNicholas Piggin { 48553c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 48563c89b8d6SNicholas Piggin GEN_PRIV; 48573c89b8d6SNicholas Piggin #else 48583c89b8d6SNicholas Piggin /* Restore CPU state */ 48593c89b8d6SNicholas Piggin CHK_SV; 4860f5b6daacSRichard Henderson gen_icount_io_start(ctx); 48612c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 48623c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 486359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 48643c89b8d6SNicholas Piggin #endif 48653c89b8d6SNicholas Piggin } 48663c89b8d6SNicholas Piggin #endif 48673c89b8d6SNicholas Piggin 4868fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4869fcf5ef2aSThomas Huth { 4870fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4871fcf5ef2aSThomas Huth GEN_PRIV; 4872fcf5ef2aSThomas Huth #else 4873fcf5ef2aSThomas Huth /* Restore CPU state */ 4874fcf5ef2aSThomas Huth CHK_HV; 4875fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 487659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4877fcf5ef2aSThomas Huth #endif 4878fcf5ef2aSThomas Huth } 4879fcf5ef2aSThomas Huth #endif 4880fcf5ef2aSThomas Huth 4881fcf5ef2aSThomas Huth /* sc */ 4882fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4883fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4884fcf5ef2aSThomas Huth #else 4885fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 48863c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4887fcf5ef2aSThomas Huth #endif 4888fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4889fcf5ef2aSThomas Huth { 4890fcf5ef2aSThomas Huth uint32_t lev; 4891fcf5ef2aSThomas Huth 4892fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4893fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4894fcf5ef2aSThomas Huth } 4895fcf5ef2aSThomas Huth 48963c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 48973c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 48983c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 48993c89b8d6SNicholas Piggin { 4900f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 49013c89b8d6SNicholas Piggin 4902f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 49032c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4904f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 49053c89b8d6SNicholas Piggin 49067a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 49073c89b8d6SNicholas Piggin } 49083c89b8d6SNicholas Piggin #endif 49093c89b8d6SNicholas Piggin #endif 49103c89b8d6SNicholas Piggin 4911fcf5ef2aSThomas Huth /*** Trap ***/ 4912fcf5ef2aSThomas Huth 4913fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4914fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4915fcf5ef2aSThomas Huth { 4916fcf5ef2aSThomas Huth /* Trap never */ 4917fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4918fcf5ef2aSThomas Huth return true; 4919fcf5ef2aSThomas Huth } 4920fcf5ef2aSThomas Huth /* Trap always */ 4921fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4922fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4923fcf5ef2aSThomas Huth return true; 4924fcf5ef2aSThomas Huth } 4925fcf5ef2aSThomas Huth return false; 4926fcf5ef2aSThomas Huth } 4927fcf5ef2aSThomas Huth 4928fcf5ef2aSThomas Huth /* tw */ 4929fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4930fcf5ef2aSThomas Huth { 4931fcf5ef2aSThomas Huth TCGv_i32 t0; 4932fcf5ef2aSThomas Huth 4933fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4934fcf5ef2aSThomas Huth return; 4935fcf5ef2aSThomas Huth } 4936fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4937fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4938fcf5ef2aSThomas Huth t0); 4939fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4940fcf5ef2aSThomas Huth } 4941fcf5ef2aSThomas Huth 4942fcf5ef2aSThomas Huth /* twi */ 4943fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4944fcf5ef2aSThomas Huth { 4945fcf5ef2aSThomas Huth TCGv t0; 4946fcf5ef2aSThomas Huth TCGv_i32 t1; 4947fcf5ef2aSThomas Huth 4948fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4949fcf5ef2aSThomas Huth return; 4950fcf5ef2aSThomas Huth } 4951fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4952fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4953fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4954fcf5ef2aSThomas Huth tcg_temp_free(t0); 4955fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4956fcf5ef2aSThomas Huth } 4957fcf5ef2aSThomas Huth 4958fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4959fcf5ef2aSThomas Huth /* td */ 4960fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4961fcf5ef2aSThomas Huth { 4962fcf5ef2aSThomas Huth TCGv_i32 t0; 4963fcf5ef2aSThomas Huth 4964fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4965fcf5ef2aSThomas Huth return; 4966fcf5ef2aSThomas Huth } 4967fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4968fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4969fcf5ef2aSThomas Huth t0); 4970fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4971fcf5ef2aSThomas Huth } 4972fcf5ef2aSThomas Huth 4973fcf5ef2aSThomas Huth /* tdi */ 4974fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4975fcf5ef2aSThomas Huth { 4976fcf5ef2aSThomas Huth TCGv t0; 4977fcf5ef2aSThomas Huth TCGv_i32 t1; 4978fcf5ef2aSThomas Huth 4979fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4980fcf5ef2aSThomas Huth return; 4981fcf5ef2aSThomas Huth } 4982fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4983fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4984fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4985fcf5ef2aSThomas Huth tcg_temp_free(t0); 4986fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4987fcf5ef2aSThomas Huth } 4988fcf5ef2aSThomas Huth #endif 4989fcf5ef2aSThomas Huth 4990fcf5ef2aSThomas Huth /*** Processor control ***/ 4991fcf5ef2aSThomas Huth 4992fcf5ef2aSThomas Huth /* mcrxr */ 4993fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4994fcf5ef2aSThomas Huth { 4995fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4996fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4997fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4998fcf5ef2aSThomas Huth 4999fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 5000fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 5001fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 5002fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 5003fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 5004fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 5005fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 5006fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 5007fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5008fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5009fcf5ef2aSThomas Huth 5010fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 5011fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5012fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5013fcf5ef2aSThomas Huth } 5014fcf5ef2aSThomas Huth 5015b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 5016b63d0434SNikunj A Dadhania /* mcrxrx */ 5017b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 5018b63d0434SNikunj A Dadhania { 5019b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 5020b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 5021b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5022b63d0434SNikunj A Dadhania 5023b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 5024b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 5025b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 5026b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 5027b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 5028b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 5029b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 5030b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 5031b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 5032b63d0434SNikunj A Dadhania tcg_temp_free(t0); 5033b63d0434SNikunj A Dadhania tcg_temp_free(t1); 5034b63d0434SNikunj A Dadhania } 5035b63d0434SNikunj A Dadhania #endif 5036b63d0434SNikunj A Dadhania 5037fcf5ef2aSThomas Huth /* mfcr mfocrf */ 5038fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 5039fcf5ef2aSThomas Huth { 5040fcf5ef2aSThomas Huth uint32_t crm, crn; 5041fcf5ef2aSThomas Huth 5042fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 5043fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5044fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 5045fcf5ef2aSThomas Huth crn = ctz32(crm); 5046fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 5047fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 5048fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 5049fcf5ef2aSThomas Huth } 5050fcf5ef2aSThomas Huth } else { 5051fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5052fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 5053fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5054fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 5055fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5056fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 5057fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5058fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 5059fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5060fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 5061fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5062fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 5063fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5064fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 5065fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5066fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 5067fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5068fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5069fcf5ef2aSThomas Huth } 5070fcf5ef2aSThomas Huth } 5071fcf5ef2aSThomas Huth 5072fcf5ef2aSThomas Huth /* mfmsr */ 5073fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 5074fcf5ef2aSThomas Huth { 5075fcf5ef2aSThomas Huth CHK_SV; 5076fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 5077fcf5ef2aSThomas Huth } 5078fcf5ef2aSThomas Huth 5079fcf5ef2aSThomas Huth /* mfspr */ 5080fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 5081fcf5ef2aSThomas Huth { 5082fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 5083fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5084fcf5ef2aSThomas Huth 5085fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5086fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5087fcf5ef2aSThomas Huth #else 5088fcf5ef2aSThomas Huth if (ctx->pr) { 5089fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5090fcf5ef2aSThomas Huth } else if (ctx->hv) { 5091fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 5092fcf5ef2aSThomas Huth } else { 5093fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 5094fcf5ef2aSThomas Huth } 5095fcf5ef2aSThomas Huth #endif 5096fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 5097fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 5098fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 5099fcf5ef2aSThomas Huth } else { 5100fcf5ef2aSThomas Huth /* Privilege exception */ 5101efe843d8SDavid Gibson /* 5102efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 5103fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 5104fcf5ef2aSThomas Huth * allowing userland application to read the PVR 5105fcf5ef2aSThomas Huth */ 5106fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 510731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 510831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 51092c2bcb1bSRichard Henderson ctx->cia); 5110fcf5ef2aSThomas Huth } 5111fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5112fcf5ef2aSThomas Huth } 5113fcf5ef2aSThomas Huth } else { 5114fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5115fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5116fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5117fcf5ef2aSThomas Huth /* This is a nop */ 5118fcf5ef2aSThomas Huth return; 5119fcf5ef2aSThomas Huth } 5120fcf5ef2aSThomas Huth /* Not defined */ 512131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 512231085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 51232c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5124fcf5ef2aSThomas Huth 5125efe843d8SDavid Gibson /* 5126efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5127efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5128fcf5ef2aSThomas Huth */ 5129fcf5ef2aSThomas Huth if (sprn & 0x10) { 5130fcf5ef2aSThomas Huth if (ctx->pr) { 5131fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5132fcf5ef2aSThomas Huth } 5133fcf5ef2aSThomas Huth } else { 5134fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5135fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5136fcf5ef2aSThomas Huth } 5137fcf5ef2aSThomas Huth } 5138fcf5ef2aSThomas Huth } 5139fcf5ef2aSThomas Huth } 5140fcf5ef2aSThomas Huth 5141fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5142fcf5ef2aSThomas Huth { 5143fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5144fcf5ef2aSThomas Huth } 5145fcf5ef2aSThomas Huth 5146fcf5ef2aSThomas Huth /* mftb */ 5147fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5148fcf5ef2aSThomas Huth { 5149fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5150fcf5ef2aSThomas Huth } 5151fcf5ef2aSThomas Huth 5152fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5153fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5154fcf5ef2aSThomas Huth { 5155fcf5ef2aSThomas Huth uint32_t crm, crn; 5156fcf5ef2aSThomas Huth 5157fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5158fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5159fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5160fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5161fcf5ef2aSThomas Huth crn = ctz32(crm); 5162fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5163fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5164fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5165fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5166fcf5ef2aSThomas Huth } 5167fcf5ef2aSThomas Huth } else { 5168fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5169fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5170fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5171fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5172fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5173fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5174fcf5ef2aSThomas Huth } 5175fcf5ef2aSThomas Huth } 5176fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5177fcf5ef2aSThomas Huth } 5178fcf5ef2aSThomas Huth } 5179fcf5ef2aSThomas Huth 5180fcf5ef2aSThomas Huth /* mtmsr */ 5181fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5182fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5183fcf5ef2aSThomas Huth { 5184fcf5ef2aSThomas Huth CHK_SV; 5185fcf5ef2aSThomas Huth 5186fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5187f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5188fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 51895ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5190fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 51915ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5192efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5193efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 51945ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5195efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 51965ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 51975ed19506SNicholas Piggin 51985ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5199fcf5ef2aSThomas Huth tcg_temp_free(t0); 52005ed19506SNicholas Piggin tcg_temp_free(t1); 52015ed19506SNicholas Piggin 5202fcf5ef2aSThomas Huth } else { 5203efe843d8SDavid Gibson /* 5204efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5205efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5206efe843d8SDavid Gibson * ppc_store_msr 5207fcf5ef2aSThomas Huth */ 5208b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5209fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5210fcf5ef2aSThomas Huth } 52115ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5212d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5213fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5214fcf5ef2aSThomas Huth } 5215fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5216fcf5ef2aSThomas Huth 5217fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5218fcf5ef2aSThomas Huth { 5219fcf5ef2aSThomas Huth CHK_SV; 5220fcf5ef2aSThomas Huth 5221fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5222f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5223fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 52245ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5225fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 52265ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5227efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5228efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 52295ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5230efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 52315ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 52325ed19506SNicholas Piggin 52335ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5234fcf5ef2aSThomas Huth tcg_temp_free(t0); 52355ed19506SNicholas Piggin tcg_temp_free(t1); 52365ed19506SNicholas Piggin 5237fcf5ef2aSThomas Huth } else { 5238fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5239fcf5ef2aSThomas Huth 5240efe843d8SDavid Gibson /* 5241efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5242efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5243efe843d8SDavid Gibson * ppc_store_msr 5244fcf5ef2aSThomas Huth */ 5245b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5246fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5247fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5248fcf5ef2aSThomas Huth #else 5249fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5250fcf5ef2aSThomas Huth #endif 5251fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5252fcf5ef2aSThomas Huth tcg_temp_free(msr); 5253fcf5ef2aSThomas Huth } 52545ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5255d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5256fcf5ef2aSThomas Huth #endif 5257fcf5ef2aSThomas Huth } 5258fcf5ef2aSThomas Huth 5259fcf5ef2aSThomas Huth /* mtspr */ 5260fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5261fcf5ef2aSThomas Huth { 5262fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5263fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5264fcf5ef2aSThomas Huth 5265fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5266fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5267fcf5ef2aSThomas Huth #else 5268fcf5ef2aSThomas Huth if (ctx->pr) { 5269fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5270fcf5ef2aSThomas Huth } else if (ctx->hv) { 5271fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5272fcf5ef2aSThomas Huth } else { 5273fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5274fcf5ef2aSThomas Huth } 5275fcf5ef2aSThomas Huth #endif 5276fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5277fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5278fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5279fcf5ef2aSThomas Huth } else { 5280fcf5ef2aSThomas Huth /* Privilege exception */ 528131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 528231085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 52832c2bcb1bSRichard Henderson ctx->cia); 5284fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5285fcf5ef2aSThomas Huth } 5286fcf5ef2aSThomas Huth } else { 5287fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5288fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5289fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5290fcf5ef2aSThomas Huth /* This is a nop */ 5291fcf5ef2aSThomas Huth return; 5292fcf5ef2aSThomas Huth } 5293fcf5ef2aSThomas Huth 5294fcf5ef2aSThomas Huth /* Not defined */ 529531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 529631085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 52972c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5298fcf5ef2aSThomas Huth 5299fcf5ef2aSThomas Huth 5300efe843d8SDavid Gibson /* 5301efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5302efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5303fcf5ef2aSThomas Huth */ 5304fcf5ef2aSThomas Huth if (sprn & 0x10) { 5305fcf5ef2aSThomas Huth if (ctx->pr) { 5306fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5307fcf5ef2aSThomas Huth } 5308fcf5ef2aSThomas Huth } else { 5309fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5310fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5311fcf5ef2aSThomas Huth } 5312fcf5ef2aSThomas Huth } 5313fcf5ef2aSThomas Huth } 5314fcf5ef2aSThomas Huth } 5315fcf5ef2aSThomas Huth 5316fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5317fcf5ef2aSThomas Huth /* setb */ 5318fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5319fcf5ef2aSThomas Huth { 5320fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5321fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5322fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5323fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5324fcf5ef2aSThomas Huth 5325fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5326fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5327fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5328fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5329fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5330fcf5ef2aSThomas Huth 5331fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5332fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5333fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5334fcf5ef2aSThomas Huth } 5335fcf5ef2aSThomas Huth #endif 5336fcf5ef2aSThomas Huth 5337fcf5ef2aSThomas Huth /*** Cache management ***/ 5338fcf5ef2aSThomas Huth 5339fcf5ef2aSThomas Huth /* dcbf */ 5340fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5341fcf5ef2aSThomas Huth { 5342fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5343fcf5ef2aSThomas Huth TCGv t0; 5344fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5345fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5346fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5347fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5348fcf5ef2aSThomas Huth tcg_temp_free(t0); 5349fcf5ef2aSThomas Huth } 5350fcf5ef2aSThomas Huth 535150728199SRoman Kapl /* dcbfep (external PID dcbf) */ 535250728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 535350728199SRoman Kapl { 535450728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 535550728199SRoman Kapl TCGv t0; 535650728199SRoman Kapl CHK_SV; 535750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 535850728199SRoman Kapl t0 = tcg_temp_new(); 535950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 536050728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 536150728199SRoman Kapl tcg_temp_free(t0); 536250728199SRoman Kapl } 536350728199SRoman Kapl 5364fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5365fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5366fcf5ef2aSThomas Huth { 5367fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5368fcf5ef2aSThomas Huth GEN_PRIV; 5369fcf5ef2aSThomas Huth #else 5370fcf5ef2aSThomas Huth TCGv EA, val; 5371fcf5ef2aSThomas Huth 5372fcf5ef2aSThomas Huth CHK_SV; 5373fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5374fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5375fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5376fcf5ef2aSThomas Huth val = tcg_temp_new(); 5377fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5378fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5379fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5380fcf5ef2aSThomas Huth tcg_temp_free(val); 5381fcf5ef2aSThomas Huth tcg_temp_free(EA); 5382fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5383fcf5ef2aSThomas Huth } 5384fcf5ef2aSThomas Huth 5385fcf5ef2aSThomas Huth /* dcdst */ 5386fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5387fcf5ef2aSThomas Huth { 5388fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5389fcf5ef2aSThomas Huth TCGv t0; 5390fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5391fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5392fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5393fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5394fcf5ef2aSThomas Huth tcg_temp_free(t0); 5395fcf5ef2aSThomas Huth } 5396fcf5ef2aSThomas Huth 539750728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 539850728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 539950728199SRoman Kapl { 540050728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 540150728199SRoman Kapl TCGv t0; 540250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 540350728199SRoman Kapl t0 = tcg_temp_new(); 540450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 540550728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 540650728199SRoman Kapl tcg_temp_free(t0); 540750728199SRoman Kapl } 540850728199SRoman Kapl 5409fcf5ef2aSThomas Huth /* dcbt */ 5410fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5411fcf5ef2aSThomas Huth { 5412efe843d8SDavid Gibson /* 5413efe843d8SDavid Gibson * interpreted as no-op 5414efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5415efe843d8SDavid Gibson * does not generate any exception 5416fcf5ef2aSThomas Huth */ 5417fcf5ef2aSThomas Huth } 5418fcf5ef2aSThomas Huth 541950728199SRoman Kapl /* dcbtep */ 542050728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 542150728199SRoman Kapl { 5422efe843d8SDavid Gibson /* 5423efe843d8SDavid Gibson * interpreted as no-op 5424efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5425efe843d8SDavid Gibson * does not generate any exception 542650728199SRoman Kapl */ 542750728199SRoman Kapl } 542850728199SRoman Kapl 5429fcf5ef2aSThomas Huth /* dcbtst */ 5430fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5431fcf5ef2aSThomas Huth { 5432efe843d8SDavid Gibson /* 5433efe843d8SDavid Gibson * interpreted as no-op 5434efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5435efe843d8SDavid Gibson * does not generate any exception 5436fcf5ef2aSThomas Huth */ 5437fcf5ef2aSThomas Huth } 5438fcf5ef2aSThomas Huth 543950728199SRoman Kapl /* dcbtstep */ 544050728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 544150728199SRoman Kapl { 5442efe843d8SDavid Gibson /* 5443efe843d8SDavid Gibson * interpreted as no-op 5444efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5445efe843d8SDavid Gibson * does not generate any exception 544650728199SRoman Kapl */ 544750728199SRoman Kapl } 544850728199SRoman Kapl 5449fcf5ef2aSThomas Huth /* dcbtls */ 5450fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5451fcf5ef2aSThomas Huth { 5452fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5453fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5454fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5455fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5456fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5457fcf5ef2aSThomas Huth tcg_temp_free(t0); 5458fcf5ef2aSThomas Huth } 5459fcf5ef2aSThomas Huth 5460fcf5ef2aSThomas Huth /* dcbz */ 5461fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5462fcf5ef2aSThomas Huth { 5463fcf5ef2aSThomas Huth TCGv tcgv_addr; 5464fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5465fcf5ef2aSThomas Huth 5466fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5467fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5468fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5469fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5470fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5471fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5472fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5473fcf5ef2aSThomas Huth } 5474fcf5ef2aSThomas Huth 547550728199SRoman Kapl /* dcbzep */ 547650728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 547750728199SRoman Kapl { 547850728199SRoman Kapl TCGv tcgv_addr; 547950728199SRoman Kapl TCGv_i32 tcgv_op; 548050728199SRoman Kapl 548150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 548250728199SRoman Kapl tcgv_addr = tcg_temp_new(); 548350728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 548450728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 548550728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 548650728199SRoman Kapl tcg_temp_free(tcgv_addr); 548750728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 548850728199SRoman Kapl } 548950728199SRoman Kapl 5490fcf5ef2aSThomas Huth /* dst / dstt */ 5491fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5492fcf5ef2aSThomas Huth { 5493fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5494fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5495fcf5ef2aSThomas Huth } else { 5496fcf5ef2aSThomas Huth /* interpreted as no-op */ 5497fcf5ef2aSThomas Huth } 5498fcf5ef2aSThomas Huth } 5499fcf5ef2aSThomas Huth 5500fcf5ef2aSThomas Huth /* dstst /dststt */ 5501fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5502fcf5ef2aSThomas Huth { 5503fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5504fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5505fcf5ef2aSThomas Huth } else { 5506fcf5ef2aSThomas Huth /* interpreted as no-op */ 5507fcf5ef2aSThomas Huth } 5508fcf5ef2aSThomas Huth 5509fcf5ef2aSThomas Huth } 5510fcf5ef2aSThomas Huth 5511fcf5ef2aSThomas Huth /* dss / dssall */ 5512fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5513fcf5ef2aSThomas Huth { 5514fcf5ef2aSThomas Huth /* interpreted as no-op */ 5515fcf5ef2aSThomas Huth } 5516fcf5ef2aSThomas Huth 5517fcf5ef2aSThomas Huth /* icbi */ 5518fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5519fcf5ef2aSThomas Huth { 5520fcf5ef2aSThomas Huth TCGv t0; 5521fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5522fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5523fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5524fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5525fcf5ef2aSThomas Huth tcg_temp_free(t0); 5526fcf5ef2aSThomas Huth } 5527fcf5ef2aSThomas Huth 552850728199SRoman Kapl /* icbiep */ 552950728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 553050728199SRoman Kapl { 553150728199SRoman Kapl TCGv t0; 553250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 553350728199SRoman Kapl t0 = tcg_temp_new(); 553450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 553550728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 553650728199SRoman Kapl tcg_temp_free(t0); 553750728199SRoman Kapl } 553850728199SRoman Kapl 5539fcf5ef2aSThomas Huth /* Optional: */ 5540fcf5ef2aSThomas Huth /* dcba */ 5541fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5542fcf5ef2aSThomas Huth { 5543efe843d8SDavid Gibson /* 5544efe843d8SDavid Gibson * interpreted as no-op 5545efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5546fcf5ef2aSThomas Huth * but does not generate any exception 5547fcf5ef2aSThomas Huth */ 5548fcf5ef2aSThomas Huth } 5549fcf5ef2aSThomas Huth 5550fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5551fcf5ef2aSThomas Huth /* Supervisor only: */ 5552fcf5ef2aSThomas Huth 5553fcf5ef2aSThomas Huth /* mfsr */ 5554fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5555fcf5ef2aSThomas Huth { 5556fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5557fcf5ef2aSThomas Huth GEN_PRIV; 5558fcf5ef2aSThomas Huth #else 5559fcf5ef2aSThomas Huth TCGv t0; 5560fcf5ef2aSThomas Huth 5561fcf5ef2aSThomas Huth CHK_SV; 5562fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5563fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5564fcf5ef2aSThomas Huth tcg_temp_free(t0); 5565fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5566fcf5ef2aSThomas Huth } 5567fcf5ef2aSThomas Huth 5568fcf5ef2aSThomas Huth /* mfsrin */ 5569fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5570fcf5ef2aSThomas Huth { 5571fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5572fcf5ef2aSThomas Huth GEN_PRIV; 5573fcf5ef2aSThomas Huth #else 5574fcf5ef2aSThomas Huth TCGv t0; 5575fcf5ef2aSThomas Huth 5576fcf5ef2aSThomas Huth CHK_SV; 5577fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5578e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5579fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5580fcf5ef2aSThomas Huth tcg_temp_free(t0); 5581fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5582fcf5ef2aSThomas Huth } 5583fcf5ef2aSThomas Huth 5584fcf5ef2aSThomas Huth /* mtsr */ 5585fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5586fcf5ef2aSThomas Huth { 5587fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5588fcf5ef2aSThomas Huth GEN_PRIV; 5589fcf5ef2aSThomas Huth #else 5590fcf5ef2aSThomas Huth TCGv t0; 5591fcf5ef2aSThomas Huth 5592fcf5ef2aSThomas Huth CHK_SV; 5593fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5594fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5595fcf5ef2aSThomas Huth tcg_temp_free(t0); 5596fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5597fcf5ef2aSThomas Huth } 5598fcf5ef2aSThomas Huth 5599fcf5ef2aSThomas Huth /* mtsrin */ 5600fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5601fcf5ef2aSThomas Huth { 5602fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5603fcf5ef2aSThomas Huth GEN_PRIV; 5604fcf5ef2aSThomas Huth #else 5605fcf5ef2aSThomas Huth TCGv t0; 5606fcf5ef2aSThomas Huth CHK_SV; 5607fcf5ef2aSThomas Huth 5608fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5609e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5610fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5611fcf5ef2aSThomas Huth tcg_temp_free(t0); 5612fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5613fcf5ef2aSThomas Huth } 5614fcf5ef2aSThomas Huth 5615fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5616fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5617fcf5ef2aSThomas Huth 5618fcf5ef2aSThomas Huth /* mfsr */ 5619fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5620fcf5ef2aSThomas Huth { 5621fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5622fcf5ef2aSThomas Huth GEN_PRIV; 5623fcf5ef2aSThomas Huth #else 5624fcf5ef2aSThomas Huth TCGv t0; 5625fcf5ef2aSThomas Huth 5626fcf5ef2aSThomas Huth CHK_SV; 5627fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5628fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5629fcf5ef2aSThomas Huth tcg_temp_free(t0); 5630fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5631fcf5ef2aSThomas Huth } 5632fcf5ef2aSThomas Huth 5633fcf5ef2aSThomas Huth /* mfsrin */ 5634fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5635fcf5ef2aSThomas Huth { 5636fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5637fcf5ef2aSThomas Huth GEN_PRIV; 5638fcf5ef2aSThomas Huth #else 5639fcf5ef2aSThomas Huth TCGv t0; 5640fcf5ef2aSThomas Huth 5641fcf5ef2aSThomas Huth CHK_SV; 5642fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5643e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5644fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5645fcf5ef2aSThomas Huth tcg_temp_free(t0); 5646fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5647fcf5ef2aSThomas Huth } 5648fcf5ef2aSThomas Huth 5649fcf5ef2aSThomas Huth /* mtsr */ 5650fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5651fcf5ef2aSThomas Huth { 5652fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5653fcf5ef2aSThomas Huth GEN_PRIV; 5654fcf5ef2aSThomas Huth #else 5655fcf5ef2aSThomas Huth TCGv t0; 5656fcf5ef2aSThomas Huth 5657fcf5ef2aSThomas Huth CHK_SV; 5658fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5659fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5660fcf5ef2aSThomas Huth tcg_temp_free(t0); 5661fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5662fcf5ef2aSThomas Huth } 5663fcf5ef2aSThomas Huth 5664fcf5ef2aSThomas Huth /* mtsrin */ 5665fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5666fcf5ef2aSThomas Huth { 5667fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5668fcf5ef2aSThomas Huth GEN_PRIV; 5669fcf5ef2aSThomas Huth #else 5670fcf5ef2aSThomas Huth TCGv t0; 5671fcf5ef2aSThomas Huth 5672fcf5ef2aSThomas Huth CHK_SV; 5673fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5674e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5675fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5676fcf5ef2aSThomas Huth tcg_temp_free(t0); 5677fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5678fcf5ef2aSThomas Huth } 5679fcf5ef2aSThomas Huth 5680fcf5ef2aSThomas Huth /* slbmte */ 5681fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5682fcf5ef2aSThomas Huth { 5683fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5684fcf5ef2aSThomas Huth GEN_PRIV; 5685fcf5ef2aSThomas Huth #else 5686fcf5ef2aSThomas Huth CHK_SV; 5687fcf5ef2aSThomas Huth 5688fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5689fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5690fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5691fcf5ef2aSThomas Huth } 5692fcf5ef2aSThomas Huth 5693fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5694fcf5ef2aSThomas Huth { 5695fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5696fcf5ef2aSThomas Huth GEN_PRIV; 5697fcf5ef2aSThomas Huth #else 5698fcf5ef2aSThomas Huth CHK_SV; 5699fcf5ef2aSThomas Huth 5700fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5701fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5702fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5703fcf5ef2aSThomas Huth } 5704fcf5ef2aSThomas Huth 5705fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5706fcf5ef2aSThomas Huth { 5707fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5708fcf5ef2aSThomas Huth GEN_PRIV; 5709fcf5ef2aSThomas Huth #else 5710fcf5ef2aSThomas Huth CHK_SV; 5711fcf5ef2aSThomas Huth 5712fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5713fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5714fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5715fcf5ef2aSThomas Huth } 5716fcf5ef2aSThomas Huth 5717fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5718fcf5ef2aSThomas Huth { 5719fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5720fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5721fcf5ef2aSThomas Huth #else 5722fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5723fcf5ef2aSThomas Huth 5724fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5725fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5726fcf5ef2aSThomas Huth return; 5727fcf5ef2aSThomas Huth } 5728fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5729fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5730fcf5ef2aSThomas Huth l1 = gen_new_label(); 5731fcf5ef2aSThomas Huth l2 = gen_new_label(); 5732fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5733fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5734efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5735fcf5ef2aSThomas Huth tcg_gen_br(l2); 5736fcf5ef2aSThomas Huth gen_set_label(l1); 5737fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5738fcf5ef2aSThomas Huth gen_set_label(l2); 5739fcf5ef2aSThomas Huth #endif 5740fcf5ef2aSThomas Huth } 5741fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5742fcf5ef2aSThomas Huth 5743fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5744fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5745fcf5ef2aSThomas Huth 5746fcf5ef2aSThomas Huth /* tlbia */ 5747fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5748fcf5ef2aSThomas Huth { 5749fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5750fcf5ef2aSThomas Huth GEN_PRIV; 5751fcf5ef2aSThomas Huth #else 5752fcf5ef2aSThomas Huth CHK_HV; 5753fcf5ef2aSThomas Huth 5754fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5755fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5756fcf5ef2aSThomas Huth } 5757fcf5ef2aSThomas Huth 5758fcf5ef2aSThomas Huth /* tlbiel */ 5759fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5760fcf5ef2aSThomas Huth { 5761fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5762fcf5ef2aSThomas Huth GEN_PRIV; 5763fcf5ef2aSThomas Huth #else 5764fcf5ef2aSThomas Huth CHK_SV; 5765fcf5ef2aSThomas Huth 5766fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5767fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5768fcf5ef2aSThomas Huth } 5769fcf5ef2aSThomas Huth 5770fcf5ef2aSThomas Huth /* tlbie */ 5771fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5772fcf5ef2aSThomas Huth { 5773fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5774fcf5ef2aSThomas Huth GEN_PRIV; 5775fcf5ef2aSThomas Huth #else 5776fcf5ef2aSThomas Huth TCGv_i32 t1; 5777c6fd28fdSSuraj Jitindar Singh 5778c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 577991c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5780c6fd28fdSSuraj Jitindar Singh } else { 5781c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5782c6fd28fdSSuraj Jitindar Singh } 5783fcf5ef2aSThomas Huth 5784fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5785fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5786fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5787fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5788fcf5ef2aSThomas Huth tcg_temp_free(t0); 5789fcf5ef2aSThomas Huth } else { 5790fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5791fcf5ef2aSThomas Huth } 5792fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5793fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5794fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5795fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5796fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5797fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5798fcf5ef2aSThomas Huth } 5799fcf5ef2aSThomas Huth 5800fcf5ef2aSThomas Huth /* tlbsync */ 5801fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5802fcf5ef2aSThomas Huth { 5803fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5804fcf5ef2aSThomas Huth GEN_PRIV; 5805fcf5ef2aSThomas Huth #else 580691c60f12SCédric Le Goater 580791c60f12SCédric Le Goater if (ctx->gtse) { 580891c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 580991c60f12SCédric Le Goater } else { 581091c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 581191c60f12SCédric Le Goater } 5812fcf5ef2aSThomas Huth 5813fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5814fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5815fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5816fcf5ef2aSThomas Huth } 5817fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5818fcf5ef2aSThomas Huth } 5819fcf5ef2aSThomas Huth 5820fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5821fcf5ef2aSThomas Huth /* slbia */ 5822fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5823fcf5ef2aSThomas Huth { 5824fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5825fcf5ef2aSThomas Huth GEN_PRIV; 5826fcf5ef2aSThomas Huth #else 58270418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 58280418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 58290418bf78SNicholas Piggin 5830fcf5ef2aSThomas Huth CHK_SV; 5831fcf5ef2aSThomas Huth 58320418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 58333119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5834fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5835fcf5ef2aSThomas Huth } 5836fcf5ef2aSThomas Huth 5837fcf5ef2aSThomas Huth /* slbie */ 5838fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5839fcf5ef2aSThomas Huth { 5840fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5841fcf5ef2aSThomas Huth GEN_PRIV; 5842fcf5ef2aSThomas Huth #else 5843fcf5ef2aSThomas Huth CHK_SV; 5844fcf5ef2aSThomas Huth 5845fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5846fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5847fcf5ef2aSThomas Huth } 5848a63f1dfcSNikunj A Dadhania 5849a63f1dfcSNikunj A Dadhania /* slbieg */ 5850a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5851a63f1dfcSNikunj A Dadhania { 5852a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5853a63f1dfcSNikunj A Dadhania GEN_PRIV; 5854a63f1dfcSNikunj A Dadhania #else 5855a63f1dfcSNikunj A Dadhania CHK_SV; 5856a63f1dfcSNikunj A Dadhania 5857a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5858a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5859a63f1dfcSNikunj A Dadhania } 5860a63f1dfcSNikunj A Dadhania 586162d897caSNikunj A Dadhania /* slbsync */ 586262d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 586362d897caSNikunj A Dadhania { 586462d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 586562d897caSNikunj A Dadhania GEN_PRIV; 586662d897caSNikunj A Dadhania #else 586762d897caSNikunj A Dadhania CHK_SV; 586862d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 586962d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 587062d897caSNikunj A Dadhania } 587162d897caSNikunj A Dadhania 5872fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5873fcf5ef2aSThomas Huth 5874fcf5ef2aSThomas Huth /*** External control ***/ 5875fcf5ef2aSThomas Huth /* Optional: */ 5876fcf5ef2aSThomas Huth 5877fcf5ef2aSThomas Huth /* eciwx */ 5878fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5879fcf5ef2aSThomas Huth { 5880fcf5ef2aSThomas Huth TCGv t0; 5881fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5882fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5883fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5884fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5885c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5886c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5887fcf5ef2aSThomas Huth tcg_temp_free(t0); 5888fcf5ef2aSThomas Huth } 5889fcf5ef2aSThomas Huth 5890fcf5ef2aSThomas Huth /* ecowx */ 5891fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5892fcf5ef2aSThomas Huth { 5893fcf5ef2aSThomas Huth TCGv t0; 5894fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5895fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5896fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5897fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5898c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5899c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5900fcf5ef2aSThomas Huth tcg_temp_free(t0); 5901fcf5ef2aSThomas Huth } 5902fcf5ef2aSThomas Huth 5903fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5904fcf5ef2aSThomas Huth 5905fcf5ef2aSThomas Huth /* abs - abs. */ 5906fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5907fcf5ef2aSThomas Huth { 5908fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5909fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5910fe21b785SRichard Henderson 5911fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5912efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5913fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5914fcf5ef2aSThomas Huth } 5915efe843d8SDavid Gibson } 5916fcf5ef2aSThomas Huth 5917fcf5ef2aSThomas Huth /* abso - abso. */ 5918fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5919fcf5ef2aSThomas Huth { 5920fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5921fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5922fe21b785SRichard Henderson 5923fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5924fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5925fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5926efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5927fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5928fcf5ef2aSThomas Huth } 5929efe843d8SDavid Gibson } 5930fcf5ef2aSThomas Huth 5931fcf5ef2aSThomas Huth /* clcs */ 5932fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5933fcf5ef2aSThomas Huth { 5934fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5935fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5936fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5937fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5938fcf5ef2aSThomas Huth } 5939fcf5ef2aSThomas Huth 5940fcf5ef2aSThomas Huth /* div - div. */ 5941fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5942fcf5ef2aSThomas Huth { 5943fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5944fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5945efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5946fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5947fcf5ef2aSThomas Huth } 5948efe843d8SDavid Gibson } 5949fcf5ef2aSThomas Huth 5950fcf5ef2aSThomas Huth /* divo - divo. */ 5951fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5952fcf5ef2aSThomas Huth { 5953fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5954fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5955efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5956fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5957fcf5ef2aSThomas Huth } 5958efe843d8SDavid Gibson } 5959fcf5ef2aSThomas Huth 5960fcf5ef2aSThomas Huth /* divs - divs. */ 5961fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5962fcf5ef2aSThomas Huth { 5963fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5964fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5965efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5966fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5967fcf5ef2aSThomas Huth } 5968efe843d8SDavid Gibson } 5969fcf5ef2aSThomas Huth 5970fcf5ef2aSThomas Huth /* divso - divso. */ 5971fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5972fcf5ef2aSThomas Huth { 5973fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5974fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5975efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5976fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5977fcf5ef2aSThomas Huth } 5978efe843d8SDavid Gibson } 5979fcf5ef2aSThomas Huth 5980fcf5ef2aSThomas Huth /* doz - doz. */ 5981fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5982fcf5ef2aSThomas Huth { 5983fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5984fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5985efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5986efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5987efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5988efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5989fcf5ef2aSThomas Huth tcg_gen_br(l2); 5990fcf5ef2aSThomas Huth gen_set_label(l1); 5991fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5992fcf5ef2aSThomas Huth gen_set_label(l2); 5993efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5994fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5995fcf5ef2aSThomas Huth } 5996efe843d8SDavid Gibson } 5997fcf5ef2aSThomas Huth 5998fcf5ef2aSThomas Huth /* dozo - dozo. */ 5999fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 6000fcf5ef2aSThomas Huth { 6001fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6002fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6003fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6004fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6005fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6006fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6007fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6008efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6009efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6010fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6011fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6012fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 6013fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6014fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 6015fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6016fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6017fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6018fcf5ef2aSThomas Huth tcg_gen_br(l2); 6019fcf5ef2aSThomas Huth gen_set_label(l1); 6020fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6021fcf5ef2aSThomas Huth gen_set_label(l2); 6022fcf5ef2aSThomas Huth tcg_temp_free(t0); 6023fcf5ef2aSThomas Huth tcg_temp_free(t1); 6024fcf5ef2aSThomas Huth tcg_temp_free(t2); 6025efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6026fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6027fcf5ef2aSThomas Huth } 6028efe843d8SDavid Gibson } 6029fcf5ef2aSThomas Huth 6030fcf5ef2aSThomas Huth /* dozi */ 6031fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 6032fcf5ef2aSThomas Huth { 6033fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 6034fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6035fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6036fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 6037fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 6038fcf5ef2aSThomas Huth tcg_gen_br(l2); 6039fcf5ef2aSThomas Huth gen_set_label(l1); 6040fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6041fcf5ef2aSThomas Huth gen_set_label(l2); 6042efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6043fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6044fcf5ef2aSThomas Huth } 6045efe843d8SDavid Gibson } 6046fcf5ef2aSThomas Huth 6047fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 6048fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 6049fcf5ef2aSThomas Huth { 6050fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6051fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 6052fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 6053fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 6054fcf5ef2aSThomas Huth 6055fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6056fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 6057fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6058fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 6059fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 6060fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 6061fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 6062efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6063fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 6064efe843d8SDavid Gibson } 6065fcf5ef2aSThomas Huth tcg_temp_free(t0); 6066fcf5ef2aSThomas Huth } 6067fcf5ef2aSThomas Huth 6068fcf5ef2aSThomas Huth /* maskg - maskg. */ 6069fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 6070fcf5ef2aSThomas Huth { 6071fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6072fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6073fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6074fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6075fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 6076fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 6077fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6078fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 6079fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 6080fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 6081fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 6082fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 6083fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 6084fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6085fcf5ef2aSThomas Huth gen_set_label(l1); 6086fcf5ef2aSThomas Huth tcg_temp_free(t0); 6087fcf5ef2aSThomas Huth tcg_temp_free(t1); 6088fcf5ef2aSThomas Huth tcg_temp_free(t2); 6089fcf5ef2aSThomas Huth tcg_temp_free(t3); 6090efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6091fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6092fcf5ef2aSThomas Huth } 6093efe843d8SDavid Gibson } 6094fcf5ef2aSThomas Huth 6095fcf5ef2aSThomas Huth /* maskir - maskir. */ 6096fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 6097fcf5ef2aSThomas Huth { 6098fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6099fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6100fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6101fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6102fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6103fcf5ef2aSThomas Huth tcg_temp_free(t0); 6104fcf5ef2aSThomas Huth tcg_temp_free(t1); 6105efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6106fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6107fcf5ef2aSThomas Huth } 6108efe843d8SDavid Gibson } 6109fcf5ef2aSThomas Huth 6110fcf5ef2aSThomas Huth /* mul - mul. */ 6111fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 6112fcf5ef2aSThomas Huth { 6113fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6114fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6115fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6116fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6117fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6118fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6119fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6120fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6121fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6122fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6123fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6124fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6125fcf5ef2aSThomas Huth tcg_temp_free(t2); 6126efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6127fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6128fcf5ef2aSThomas Huth } 6129efe843d8SDavid Gibson } 6130fcf5ef2aSThomas Huth 6131fcf5ef2aSThomas Huth /* mulo - mulo. */ 6132fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6133fcf5ef2aSThomas Huth { 6134fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6135fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6136fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6137fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6138fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6139fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6140fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6141fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6142fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6143fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6144fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6145fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6146fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6147fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6148fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6149fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6150fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6151fcf5ef2aSThomas Huth gen_set_label(l1); 6152fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6153fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6154fcf5ef2aSThomas Huth tcg_temp_free(t2); 6155efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6156fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6157fcf5ef2aSThomas Huth } 6158efe843d8SDavid Gibson } 6159fcf5ef2aSThomas Huth 6160fcf5ef2aSThomas Huth /* nabs - nabs. */ 6161fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6162fcf5ef2aSThomas Huth { 6163fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6164fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6165fe21b785SRichard Henderson 6166fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6167fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6168efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6169fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6170fcf5ef2aSThomas Huth } 6171efe843d8SDavid Gibson } 6172fcf5ef2aSThomas Huth 6173fcf5ef2aSThomas Huth /* nabso - nabso. */ 6174fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6175fcf5ef2aSThomas Huth { 6176fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6177fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6178fe21b785SRichard Henderson 6179fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6180fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6181fcf5ef2aSThomas Huth /* nabs never overflows */ 6182fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6183efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6184fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6185fcf5ef2aSThomas Huth } 6186efe843d8SDavid Gibson } 6187fcf5ef2aSThomas Huth 6188fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6189fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6190fcf5ef2aSThomas Huth { 6191fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6192fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6193fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6194fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6195fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6196fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6197efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6198efe843d8SDavid Gibson ~MASK(mb, me)); 6199fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6200fcf5ef2aSThomas Huth tcg_temp_free(t0); 6201efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6202fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6203fcf5ef2aSThomas Huth } 6204efe843d8SDavid Gibson } 6205fcf5ef2aSThomas Huth 6206fcf5ef2aSThomas Huth /* rrib - rrib. */ 6207fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6208fcf5ef2aSThomas Huth { 6209fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6210fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6211fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6212fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6213fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6214fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6215fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6216fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6217fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6218fcf5ef2aSThomas Huth tcg_temp_free(t0); 6219fcf5ef2aSThomas Huth tcg_temp_free(t1); 6220efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6221fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6222fcf5ef2aSThomas Huth } 6223efe843d8SDavid Gibson } 6224fcf5ef2aSThomas Huth 6225fcf5ef2aSThomas Huth /* sle - sle. */ 6226fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6227fcf5ef2aSThomas Huth { 6228fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6229fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6230fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6231fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6232fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6233fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6234fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6235fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6236fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6237fcf5ef2aSThomas Huth tcg_temp_free(t0); 6238fcf5ef2aSThomas Huth tcg_temp_free(t1); 6239efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6240fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6241fcf5ef2aSThomas Huth } 6242efe843d8SDavid Gibson } 6243fcf5ef2aSThomas Huth 6244fcf5ef2aSThomas Huth /* sleq - sleq. */ 6245fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6246fcf5ef2aSThomas Huth { 6247fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6248fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6249fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6250fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6251fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6252fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6253fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6254fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6255fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6256fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6257fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6258fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6259fcf5ef2aSThomas Huth tcg_temp_free(t0); 6260fcf5ef2aSThomas Huth tcg_temp_free(t1); 6261fcf5ef2aSThomas Huth tcg_temp_free(t2); 6262efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6263fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6264fcf5ef2aSThomas Huth } 6265efe843d8SDavid Gibson } 6266fcf5ef2aSThomas Huth 6267fcf5ef2aSThomas Huth /* sliq - sliq. */ 6268fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6269fcf5ef2aSThomas Huth { 6270fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6271fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6272fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6273fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6274fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6275fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6276fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6277fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6278fcf5ef2aSThomas Huth tcg_temp_free(t0); 6279fcf5ef2aSThomas Huth tcg_temp_free(t1); 6280efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6281fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6282fcf5ef2aSThomas Huth } 6283efe843d8SDavid Gibson } 6284fcf5ef2aSThomas Huth 6285fcf5ef2aSThomas Huth /* slliq - slliq. */ 6286fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6287fcf5ef2aSThomas Huth { 6288fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6289fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6290fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6291fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6292fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6293fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6294fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6295fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6296fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6297fcf5ef2aSThomas Huth tcg_temp_free(t0); 6298fcf5ef2aSThomas Huth tcg_temp_free(t1); 6299efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6300fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6301fcf5ef2aSThomas Huth } 6302efe843d8SDavid Gibson } 6303fcf5ef2aSThomas Huth 6304fcf5ef2aSThomas Huth /* sllq - sllq. */ 6305fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6306fcf5ef2aSThomas Huth { 6307fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6308fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6309fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6310fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6311fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6312fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6313fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6314fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6315fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6316fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6317fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6318fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6319fcf5ef2aSThomas Huth tcg_gen_br(l2); 6320fcf5ef2aSThomas Huth gen_set_label(l1); 6321fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6322fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6323fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6324fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6325fcf5ef2aSThomas Huth gen_set_label(l2); 6326fcf5ef2aSThomas Huth tcg_temp_free(t0); 6327fcf5ef2aSThomas Huth tcg_temp_free(t1); 6328fcf5ef2aSThomas Huth tcg_temp_free(t2); 6329efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6330fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6331fcf5ef2aSThomas Huth } 6332efe843d8SDavid Gibson } 6333fcf5ef2aSThomas Huth 6334fcf5ef2aSThomas Huth /* slq - slq. */ 6335fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6336fcf5ef2aSThomas Huth { 6337fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6338fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6339fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6340fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6341fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6342fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6343fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6344fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6345fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6346fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6347fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6348fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6349fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6350fcf5ef2aSThomas Huth gen_set_label(l1); 6351fcf5ef2aSThomas Huth tcg_temp_free(t0); 6352fcf5ef2aSThomas Huth tcg_temp_free(t1); 6353efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6354fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6355fcf5ef2aSThomas Huth } 6356efe843d8SDavid Gibson } 6357fcf5ef2aSThomas Huth 6358fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6359fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6360fcf5ef2aSThomas Huth { 6361fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6362fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6363fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6364fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6365fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6366fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6367fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6368fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6369fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6370fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6371fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6372fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6373fcf5ef2aSThomas Huth gen_set_label(l1); 6374fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6375fcf5ef2aSThomas Huth tcg_temp_free(t0); 6376fcf5ef2aSThomas Huth tcg_temp_free(t1); 6377efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6378fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6379fcf5ef2aSThomas Huth } 6380efe843d8SDavid Gibson } 6381fcf5ef2aSThomas Huth 6382fcf5ef2aSThomas Huth /* sraq - sraq. */ 6383fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6384fcf5ef2aSThomas Huth { 6385fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6386fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6387fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6388fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6389fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6390fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6391fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6392fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6393fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6394fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6395fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6396fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6397fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6398fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6399fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6400fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6401fcf5ef2aSThomas Huth gen_set_label(l1); 6402fcf5ef2aSThomas Huth tcg_temp_free(t0); 6403fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6404fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6405fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6406fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6407fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6408fcf5ef2aSThomas Huth gen_set_label(l2); 6409fcf5ef2aSThomas Huth tcg_temp_free(t1); 6410fcf5ef2aSThomas Huth tcg_temp_free(t2); 6411efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6412fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6413fcf5ef2aSThomas Huth } 6414efe843d8SDavid Gibson } 6415fcf5ef2aSThomas Huth 6416fcf5ef2aSThomas Huth /* sre - sre. */ 6417fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6418fcf5ef2aSThomas Huth { 6419fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6420fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6421fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6422fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6423fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6424fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6425fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6426fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6427fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6428fcf5ef2aSThomas Huth tcg_temp_free(t0); 6429fcf5ef2aSThomas Huth tcg_temp_free(t1); 6430efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6431fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6432fcf5ef2aSThomas Huth } 6433efe843d8SDavid Gibson } 6434fcf5ef2aSThomas Huth 6435fcf5ef2aSThomas Huth /* srea - srea. */ 6436fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6437fcf5ef2aSThomas Huth { 6438fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6439fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6440fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6441fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6442fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6443fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6444fcf5ef2aSThomas Huth tcg_temp_free(t0); 6445fcf5ef2aSThomas Huth tcg_temp_free(t1); 6446efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6447fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6448fcf5ef2aSThomas Huth } 6449efe843d8SDavid Gibson } 6450fcf5ef2aSThomas Huth 6451fcf5ef2aSThomas Huth /* sreq */ 6452fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6453fcf5ef2aSThomas Huth { 6454fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6455fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6456fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6457fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6458fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6459fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6460fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6461fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6462fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6463fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6464fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6465fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6466fcf5ef2aSThomas Huth tcg_temp_free(t0); 6467fcf5ef2aSThomas Huth tcg_temp_free(t1); 6468fcf5ef2aSThomas Huth tcg_temp_free(t2); 6469efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6470fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6471fcf5ef2aSThomas Huth } 6472efe843d8SDavid Gibson } 6473fcf5ef2aSThomas Huth 6474fcf5ef2aSThomas Huth /* sriq */ 6475fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6476fcf5ef2aSThomas Huth { 6477fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6478fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6479fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6480fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6481fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6482fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6483fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6484fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6485fcf5ef2aSThomas Huth tcg_temp_free(t0); 6486fcf5ef2aSThomas Huth tcg_temp_free(t1); 6487efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6488fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6489fcf5ef2aSThomas Huth } 6490efe843d8SDavid Gibson } 6491fcf5ef2aSThomas Huth 6492fcf5ef2aSThomas Huth /* srliq */ 6493fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6494fcf5ef2aSThomas Huth { 6495fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6496fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6497fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6498fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6499fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6500fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6501fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6502fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6503fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6504fcf5ef2aSThomas Huth tcg_temp_free(t0); 6505fcf5ef2aSThomas Huth tcg_temp_free(t1); 6506efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6507fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6508fcf5ef2aSThomas Huth } 6509efe843d8SDavid Gibson } 6510fcf5ef2aSThomas Huth 6511fcf5ef2aSThomas Huth /* srlq */ 6512fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6513fcf5ef2aSThomas Huth { 6514fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6515fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6516fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6517fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6518fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6519fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6520fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6521fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6522fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6523fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6524fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6525fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6526fcf5ef2aSThomas Huth tcg_gen_br(l2); 6527fcf5ef2aSThomas Huth gen_set_label(l1); 6528fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6529fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6530fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6531fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6532fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6533fcf5ef2aSThomas Huth gen_set_label(l2); 6534fcf5ef2aSThomas Huth tcg_temp_free(t0); 6535fcf5ef2aSThomas Huth tcg_temp_free(t1); 6536fcf5ef2aSThomas Huth tcg_temp_free(t2); 6537efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6538fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6539fcf5ef2aSThomas Huth } 6540efe843d8SDavid Gibson } 6541fcf5ef2aSThomas Huth 6542fcf5ef2aSThomas Huth /* srq */ 6543fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6544fcf5ef2aSThomas Huth { 6545fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6546fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6547fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6548fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6549fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6550fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6551fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6552fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6553fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6554fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6555fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6556fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6557fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6558fcf5ef2aSThomas Huth gen_set_label(l1); 6559fcf5ef2aSThomas Huth tcg_temp_free(t0); 6560fcf5ef2aSThomas Huth tcg_temp_free(t1); 6561efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6562fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6563fcf5ef2aSThomas Huth } 6564efe843d8SDavid Gibson } 6565fcf5ef2aSThomas Huth 6566fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6567fcf5ef2aSThomas Huth 6568fcf5ef2aSThomas Huth /* dsa */ 6569fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6570fcf5ef2aSThomas Huth { 6571fcf5ef2aSThomas Huth /* XXX: TODO */ 6572fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6573fcf5ef2aSThomas Huth } 6574fcf5ef2aSThomas Huth 6575fcf5ef2aSThomas Huth /* esa */ 6576fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6577fcf5ef2aSThomas Huth { 6578fcf5ef2aSThomas Huth /* XXX: TODO */ 6579fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6580fcf5ef2aSThomas Huth } 6581fcf5ef2aSThomas Huth 6582fcf5ef2aSThomas Huth /* mfrom */ 6583fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6584fcf5ef2aSThomas Huth { 6585fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6586fcf5ef2aSThomas Huth GEN_PRIV; 6587fcf5ef2aSThomas Huth #else 6588fcf5ef2aSThomas Huth CHK_SV; 6589fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6590fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6591fcf5ef2aSThomas Huth } 6592fcf5ef2aSThomas Huth 6593fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6594fcf5ef2aSThomas Huth 6595fcf5ef2aSThomas Huth /* tlbld */ 6596fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6597fcf5ef2aSThomas Huth { 6598fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6599fcf5ef2aSThomas Huth GEN_PRIV; 6600fcf5ef2aSThomas Huth #else 6601fcf5ef2aSThomas Huth CHK_SV; 6602fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6603fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6604fcf5ef2aSThomas Huth } 6605fcf5ef2aSThomas Huth 6606fcf5ef2aSThomas Huth /* tlbli */ 6607fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6608fcf5ef2aSThomas Huth { 6609fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6610fcf5ef2aSThomas Huth GEN_PRIV; 6611fcf5ef2aSThomas Huth #else 6612fcf5ef2aSThomas Huth CHK_SV; 6613fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6614fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6615fcf5ef2aSThomas Huth } 6616fcf5ef2aSThomas Huth 6617fcf5ef2aSThomas Huth /* 74xx TLB management */ 6618fcf5ef2aSThomas Huth 6619fcf5ef2aSThomas Huth /* tlbld */ 6620fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6621fcf5ef2aSThomas Huth { 6622fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6623fcf5ef2aSThomas Huth GEN_PRIV; 6624fcf5ef2aSThomas Huth #else 6625fcf5ef2aSThomas Huth CHK_SV; 6626fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6627fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6628fcf5ef2aSThomas Huth } 6629fcf5ef2aSThomas Huth 6630fcf5ef2aSThomas Huth /* tlbli */ 6631fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6632fcf5ef2aSThomas Huth { 6633fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6634fcf5ef2aSThomas Huth GEN_PRIV; 6635fcf5ef2aSThomas Huth #else 6636fcf5ef2aSThomas Huth CHK_SV; 6637fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6638fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6639fcf5ef2aSThomas Huth } 6640fcf5ef2aSThomas Huth 6641fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6642fcf5ef2aSThomas Huth 6643fcf5ef2aSThomas Huth /* clf */ 6644fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6645fcf5ef2aSThomas Huth { 6646fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6647fcf5ef2aSThomas Huth } 6648fcf5ef2aSThomas Huth 6649fcf5ef2aSThomas Huth /* cli */ 6650fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6651fcf5ef2aSThomas Huth { 6652fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6653fcf5ef2aSThomas Huth GEN_PRIV; 6654fcf5ef2aSThomas Huth #else 6655fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6656fcf5ef2aSThomas Huth CHK_SV; 6657fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6658fcf5ef2aSThomas Huth } 6659fcf5ef2aSThomas Huth 6660fcf5ef2aSThomas Huth /* dclst */ 6661fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6662fcf5ef2aSThomas Huth { 6663fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6664fcf5ef2aSThomas Huth } 6665fcf5ef2aSThomas Huth 6666fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6667fcf5ef2aSThomas Huth { 6668fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6669fcf5ef2aSThomas Huth GEN_PRIV; 6670fcf5ef2aSThomas Huth #else 6671fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6672fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6673fcf5ef2aSThomas Huth TCGv t0; 6674fcf5ef2aSThomas Huth 6675fcf5ef2aSThomas Huth CHK_SV; 6676fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6677fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6678e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6679fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6680fcf5ef2aSThomas Huth tcg_temp_free(t0); 6681efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6682fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6683efe843d8SDavid Gibson } 6684fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6685fcf5ef2aSThomas Huth } 6686fcf5ef2aSThomas Huth 6687fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6688fcf5ef2aSThomas Huth { 6689fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6690fcf5ef2aSThomas Huth GEN_PRIV; 6691fcf5ef2aSThomas Huth #else 6692fcf5ef2aSThomas Huth TCGv t0; 6693fcf5ef2aSThomas Huth 6694fcf5ef2aSThomas Huth CHK_SV; 6695fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6696fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6697fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6698fcf5ef2aSThomas Huth tcg_temp_free(t0); 6699fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6700fcf5ef2aSThomas Huth } 6701fcf5ef2aSThomas Huth 6702fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6703fcf5ef2aSThomas Huth { 6704fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6705fcf5ef2aSThomas Huth GEN_PRIV; 6706fcf5ef2aSThomas Huth #else 6707fcf5ef2aSThomas Huth CHK_SV; 6708fcf5ef2aSThomas Huth 6709fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 671059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6711fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6712fcf5ef2aSThomas Huth } 6713fcf5ef2aSThomas Huth 6714fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6715fcf5ef2aSThomas Huth 6716fcf5ef2aSThomas Huth /* BookE specific instructions */ 6717fcf5ef2aSThomas Huth 6718fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6719fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6720fcf5ef2aSThomas Huth { 6721fcf5ef2aSThomas Huth /* XXX: TODO */ 6722fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6723fcf5ef2aSThomas Huth } 6724fcf5ef2aSThomas Huth 6725fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6726fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6727fcf5ef2aSThomas Huth { 6728fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6729fcf5ef2aSThomas Huth GEN_PRIV; 6730fcf5ef2aSThomas Huth #else 6731fcf5ef2aSThomas Huth TCGv t0; 6732fcf5ef2aSThomas Huth 6733fcf5ef2aSThomas Huth CHK_SV; 6734fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6735fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6736fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6737fcf5ef2aSThomas Huth tcg_temp_free(t0); 6738fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6739fcf5ef2aSThomas Huth } 6740fcf5ef2aSThomas Huth 6741fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6742fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6743fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6744fcf5ef2aSThomas Huth { 6745fcf5ef2aSThomas Huth TCGv t0, t1; 6746fcf5ef2aSThomas Huth 6747fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6748fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6749fcf5ef2aSThomas Huth 6750fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6751fcf5ef2aSThomas Huth case 0x05: 6752fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6753fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6754fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6755fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6756fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6757fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6758fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6759fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6760fcf5ef2aSThomas Huth break; 6761fcf5ef2aSThomas Huth case 0x04: 6762fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6763fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6764fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6765fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6766fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6767fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6768fcf5ef2aSThomas Huth break; 6769fcf5ef2aSThomas Huth case 0x01: 6770fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6771fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6772fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6773fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6774fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6775fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6776fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6777fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6778fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6779fcf5ef2aSThomas Huth break; 6780fcf5ef2aSThomas Huth case 0x00: 6781fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6782fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6783fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6784fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6785fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6786fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6787fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6788fcf5ef2aSThomas Huth break; 6789fcf5ef2aSThomas Huth case 0x0D: 6790fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6791fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6792fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6793fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6794fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6795fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6796fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6797fcf5ef2aSThomas Huth break; 6798fcf5ef2aSThomas Huth case 0x0C: 6799fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6800fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6801fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6802fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6803fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6804fcf5ef2aSThomas Huth break; 6805fcf5ef2aSThomas Huth } 6806fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6807fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6808fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6809fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6810fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6811fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6812fcf5ef2aSThomas Huth } else { 6813fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6814fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6815fcf5ef2aSThomas Huth } 6816fcf5ef2aSThomas Huth 6817fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6818fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6819fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6820fcf5ef2aSThomas Huth 6821fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6822fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6823fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6824fcf5ef2aSThomas Huth } 6825fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6826fcf5ef2aSThomas Huth /* Signed */ 6827fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6828fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6829fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6830fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6831fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6832fcf5ef2aSThomas Huth /* Saturate */ 6833fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6834fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6835fcf5ef2aSThomas Huth } 6836fcf5ef2aSThomas Huth } else { 6837fcf5ef2aSThomas Huth /* Unsigned */ 6838fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6839fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6840fcf5ef2aSThomas Huth /* Saturate */ 6841fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6842fcf5ef2aSThomas Huth } 6843fcf5ef2aSThomas Huth } 6844fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6845fcf5ef2aSThomas Huth /* Check overflow */ 6846fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6847fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6848fcf5ef2aSThomas Huth } 6849fcf5ef2aSThomas Huth gen_set_label(l1); 6850fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6851fcf5ef2aSThomas Huth } 6852fcf5ef2aSThomas Huth } else { 6853fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6854fcf5ef2aSThomas Huth } 6855fcf5ef2aSThomas Huth tcg_temp_free(t0); 6856fcf5ef2aSThomas Huth tcg_temp_free(t1); 6857fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6858fcf5ef2aSThomas Huth /* Update Rc0 */ 6859fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6860fcf5ef2aSThomas Huth } 6861fcf5ef2aSThomas Huth } 6862fcf5ef2aSThomas Huth 6863fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6864fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6865fcf5ef2aSThomas Huth { \ 6866fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6867fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6868fcf5ef2aSThomas Huth } 6869fcf5ef2aSThomas Huth 6870fcf5ef2aSThomas Huth /* macchw - macchw. */ 6871fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6872fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6873fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6874fcf5ef2aSThomas Huth /* macchws - macchws. */ 6875fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6876fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6877fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6878fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6879fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6880fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6881fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6882fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6883fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6884fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6885fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6886fcf5ef2aSThomas Huth /* machhw - machhw. */ 6887fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6888fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6889fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6890fcf5ef2aSThomas Huth /* machhws - machhws. */ 6891fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6892fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6893fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6894fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6895fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6896fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6897fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6898fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6899fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6900fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6901fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6902fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6903fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6904fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6905fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6906fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6907fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6908fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6909fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6910fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6911fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6912fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6913fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6914fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6915fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6916fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6917fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6918fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6919fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6920fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6921fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6922fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6923fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6924fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6925fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6926fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6927fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6928fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6929fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6930fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6931fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6932fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6933fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6934fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6935fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6936fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6937fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6938fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6939fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6940fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6941fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6942fcf5ef2aSThomas Huth 6943fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6944fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6945fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6946fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6947fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6948fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6949fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6950fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6951fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6952fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6953fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6954fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6955fcf5ef2aSThomas Huth 6956fcf5ef2aSThomas Huth /* mfdcr */ 6957fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6958fcf5ef2aSThomas Huth { 6959fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6960fcf5ef2aSThomas Huth GEN_PRIV; 6961fcf5ef2aSThomas Huth #else 6962fcf5ef2aSThomas Huth TCGv dcrn; 6963fcf5ef2aSThomas Huth 6964fcf5ef2aSThomas Huth CHK_SV; 6965fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6966fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6967fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6968fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6969fcf5ef2aSThomas Huth } 6970fcf5ef2aSThomas Huth 6971fcf5ef2aSThomas Huth /* mtdcr */ 6972fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6973fcf5ef2aSThomas Huth { 6974fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6975fcf5ef2aSThomas Huth GEN_PRIV; 6976fcf5ef2aSThomas Huth #else 6977fcf5ef2aSThomas Huth TCGv dcrn; 6978fcf5ef2aSThomas Huth 6979fcf5ef2aSThomas Huth CHK_SV; 6980fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6981fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6982fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6983fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6984fcf5ef2aSThomas Huth } 6985fcf5ef2aSThomas Huth 6986fcf5ef2aSThomas Huth /* mfdcrx */ 6987fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6988fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6989fcf5ef2aSThomas Huth { 6990fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6991fcf5ef2aSThomas Huth GEN_PRIV; 6992fcf5ef2aSThomas Huth #else 6993fcf5ef2aSThomas Huth CHK_SV; 6994fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6995fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6996fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6997fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6998fcf5ef2aSThomas Huth } 6999fcf5ef2aSThomas Huth 7000fcf5ef2aSThomas Huth /* mtdcrx */ 7001fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7002fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 7003fcf5ef2aSThomas Huth { 7004fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7005fcf5ef2aSThomas Huth GEN_PRIV; 7006fcf5ef2aSThomas Huth #else 7007fcf5ef2aSThomas Huth CHK_SV; 7008fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7009fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7010fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7011fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7012fcf5ef2aSThomas Huth } 7013fcf5ef2aSThomas Huth 7014fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 7015fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 7016fcf5ef2aSThomas Huth { 7017fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7018fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7019fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7020fcf5ef2aSThomas Huth } 7021fcf5ef2aSThomas Huth 7022fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 7023fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 7024fcf5ef2aSThomas Huth { 7025fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7026fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7027fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7028fcf5ef2aSThomas Huth } 7029fcf5ef2aSThomas Huth 7030fcf5ef2aSThomas Huth /* dccci */ 7031fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 7032fcf5ef2aSThomas Huth { 7033fcf5ef2aSThomas Huth CHK_SV; 7034fcf5ef2aSThomas Huth /* interpreted as no-op */ 7035fcf5ef2aSThomas Huth } 7036fcf5ef2aSThomas Huth 7037fcf5ef2aSThomas Huth /* dcread */ 7038fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 7039fcf5ef2aSThomas Huth { 7040fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7041fcf5ef2aSThomas Huth GEN_PRIV; 7042fcf5ef2aSThomas Huth #else 7043fcf5ef2aSThomas Huth TCGv EA, val; 7044fcf5ef2aSThomas Huth 7045fcf5ef2aSThomas Huth CHK_SV; 7046fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 7047fcf5ef2aSThomas Huth EA = tcg_temp_new(); 7048fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 7049fcf5ef2aSThomas Huth val = tcg_temp_new(); 7050fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 7051fcf5ef2aSThomas Huth tcg_temp_free(val); 7052fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 7053fcf5ef2aSThomas Huth tcg_temp_free(EA); 7054fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7055fcf5ef2aSThomas Huth } 7056fcf5ef2aSThomas Huth 7057fcf5ef2aSThomas Huth /* icbt */ 7058fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 7059fcf5ef2aSThomas Huth { 7060efe843d8SDavid Gibson /* 7061efe843d8SDavid Gibson * interpreted as no-op 7062efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7063efe843d8SDavid Gibson * does not generate any exception 7064fcf5ef2aSThomas Huth */ 7065fcf5ef2aSThomas Huth } 7066fcf5ef2aSThomas Huth 7067fcf5ef2aSThomas Huth /* iccci */ 7068fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 7069fcf5ef2aSThomas Huth { 7070fcf5ef2aSThomas Huth CHK_SV; 7071fcf5ef2aSThomas Huth /* interpreted as no-op */ 7072fcf5ef2aSThomas Huth } 7073fcf5ef2aSThomas Huth 7074fcf5ef2aSThomas Huth /* icread */ 7075fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 7076fcf5ef2aSThomas Huth { 7077fcf5ef2aSThomas Huth CHK_SV; 7078fcf5ef2aSThomas Huth /* interpreted as no-op */ 7079fcf5ef2aSThomas Huth } 7080fcf5ef2aSThomas Huth 7081fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 7082fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 7083fcf5ef2aSThomas Huth { 7084fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7085fcf5ef2aSThomas Huth GEN_PRIV; 7086fcf5ef2aSThomas Huth #else 7087fcf5ef2aSThomas Huth CHK_SV; 7088fcf5ef2aSThomas Huth /* Restore CPU state */ 7089fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 709059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7091fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7092fcf5ef2aSThomas Huth } 7093fcf5ef2aSThomas Huth 7094fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 7095fcf5ef2aSThomas Huth { 7096fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7097fcf5ef2aSThomas Huth GEN_PRIV; 7098fcf5ef2aSThomas Huth #else 7099fcf5ef2aSThomas Huth CHK_SV; 7100fcf5ef2aSThomas Huth /* Restore CPU state */ 7101fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 710259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7103fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7104fcf5ef2aSThomas Huth } 7105fcf5ef2aSThomas Huth 7106fcf5ef2aSThomas Huth /* BookE specific */ 7107fcf5ef2aSThomas Huth 7108fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7109fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 7110fcf5ef2aSThomas Huth { 7111fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7112fcf5ef2aSThomas Huth GEN_PRIV; 7113fcf5ef2aSThomas Huth #else 7114fcf5ef2aSThomas Huth CHK_SV; 7115fcf5ef2aSThomas Huth /* Restore CPU state */ 7116fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 711759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7118fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7119fcf5ef2aSThomas Huth } 7120fcf5ef2aSThomas Huth 7121fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7122fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 7123fcf5ef2aSThomas Huth { 7124fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7125fcf5ef2aSThomas Huth GEN_PRIV; 7126fcf5ef2aSThomas Huth #else 7127fcf5ef2aSThomas Huth CHK_SV; 7128fcf5ef2aSThomas Huth /* Restore CPU state */ 7129fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 713059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7131fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7132fcf5ef2aSThomas Huth } 7133fcf5ef2aSThomas Huth 7134fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7135fcf5ef2aSThomas Huth 7136fcf5ef2aSThomas Huth /* tlbre */ 7137fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7138fcf5ef2aSThomas Huth { 7139fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7140fcf5ef2aSThomas Huth GEN_PRIV; 7141fcf5ef2aSThomas Huth #else 7142fcf5ef2aSThomas Huth CHK_SV; 7143fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7144fcf5ef2aSThomas Huth case 0: 7145fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7146fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7147fcf5ef2aSThomas Huth break; 7148fcf5ef2aSThomas Huth case 1: 7149fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7150fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7151fcf5ef2aSThomas Huth break; 7152fcf5ef2aSThomas Huth default: 7153fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7154fcf5ef2aSThomas Huth break; 7155fcf5ef2aSThomas Huth } 7156fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7157fcf5ef2aSThomas Huth } 7158fcf5ef2aSThomas Huth 7159fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7160fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7161fcf5ef2aSThomas Huth { 7162fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7163fcf5ef2aSThomas Huth GEN_PRIV; 7164fcf5ef2aSThomas Huth #else 7165fcf5ef2aSThomas Huth TCGv t0; 7166fcf5ef2aSThomas Huth 7167fcf5ef2aSThomas Huth CHK_SV; 7168fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7169fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7170fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7171fcf5ef2aSThomas Huth tcg_temp_free(t0); 7172fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7173fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7174fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7175fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7176fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7177fcf5ef2aSThomas Huth gen_set_label(l1); 7178fcf5ef2aSThomas Huth } 7179fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7180fcf5ef2aSThomas Huth } 7181fcf5ef2aSThomas Huth 7182fcf5ef2aSThomas Huth /* tlbwe */ 7183fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7184fcf5ef2aSThomas Huth { 7185fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7186fcf5ef2aSThomas Huth GEN_PRIV; 7187fcf5ef2aSThomas Huth #else 7188fcf5ef2aSThomas Huth CHK_SV; 7189fcf5ef2aSThomas Huth 7190fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7191fcf5ef2aSThomas Huth case 0: 7192fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7193fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7194fcf5ef2aSThomas Huth break; 7195fcf5ef2aSThomas Huth case 1: 7196fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7197fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7198fcf5ef2aSThomas Huth break; 7199fcf5ef2aSThomas Huth default: 7200fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7201fcf5ef2aSThomas Huth break; 7202fcf5ef2aSThomas Huth } 7203fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7204fcf5ef2aSThomas Huth } 7205fcf5ef2aSThomas Huth 7206fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7207fcf5ef2aSThomas Huth 7208fcf5ef2aSThomas Huth /* tlbre */ 7209fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7210fcf5ef2aSThomas Huth { 7211fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7212fcf5ef2aSThomas Huth GEN_PRIV; 7213fcf5ef2aSThomas Huth #else 7214fcf5ef2aSThomas Huth CHK_SV; 7215fcf5ef2aSThomas Huth 7216fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7217fcf5ef2aSThomas Huth case 0: 7218fcf5ef2aSThomas Huth case 1: 7219fcf5ef2aSThomas Huth case 2: 7220fcf5ef2aSThomas Huth { 7221fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7222fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7223fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7224fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7225fcf5ef2aSThomas Huth } 7226fcf5ef2aSThomas Huth break; 7227fcf5ef2aSThomas Huth default: 7228fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7229fcf5ef2aSThomas Huth break; 7230fcf5ef2aSThomas Huth } 7231fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7232fcf5ef2aSThomas Huth } 7233fcf5ef2aSThomas Huth 7234fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7235fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7236fcf5ef2aSThomas Huth { 7237fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7238fcf5ef2aSThomas Huth GEN_PRIV; 7239fcf5ef2aSThomas Huth #else 7240fcf5ef2aSThomas Huth TCGv t0; 7241fcf5ef2aSThomas Huth 7242fcf5ef2aSThomas Huth CHK_SV; 7243fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7244fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7245fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7246fcf5ef2aSThomas Huth tcg_temp_free(t0); 7247fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7248fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7249fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7250fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7251fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7252fcf5ef2aSThomas Huth gen_set_label(l1); 7253fcf5ef2aSThomas Huth } 7254fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7255fcf5ef2aSThomas Huth } 7256fcf5ef2aSThomas Huth 7257fcf5ef2aSThomas Huth /* tlbwe */ 7258fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7259fcf5ef2aSThomas Huth { 7260fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7261fcf5ef2aSThomas Huth GEN_PRIV; 7262fcf5ef2aSThomas Huth #else 7263fcf5ef2aSThomas Huth CHK_SV; 7264fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7265fcf5ef2aSThomas Huth case 0: 7266fcf5ef2aSThomas Huth case 1: 7267fcf5ef2aSThomas Huth case 2: 7268fcf5ef2aSThomas Huth { 7269fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7270fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7271fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7272fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7273fcf5ef2aSThomas Huth } 7274fcf5ef2aSThomas Huth break; 7275fcf5ef2aSThomas Huth default: 7276fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7277fcf5ef2aSThomas Huth break; 7278fcf5ef2aSThomas Huth } 7279fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7280fcf5ef2aSThomas Huth } 7281fcf5ef2aSThomas Huth 7282fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7283fcf5ef2aSThomas Huth 7284fcf5ef2aSThomas Huth /* tlbre */ 7285fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7286fcf5ef2aSThomas Huth { 7287fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7288fcf5ef2aSThomas Huth GEN_PRIV; 7289fcf5ef2aSThomas Huth #else 7290fcf5ef2aSThomas Huth CHK_SV; 7291fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7292fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7293fcf5ef2aSThomas Huth } 7294fcf5ef2aSThomas Huth 7295fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7296fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7297fcf5ef2aSThomas Huth { 7298fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7299fcf5ef2aSThomas Huth GEN_PRIV; 7300fcf5ef2aSThomas Huth #else 7301fcf5ef2aSThomas Huth TCGv t0; 7302fcf5ef2aSThomas Huth 7303fcf5ef2aSThomas Huth CHK_SV; 7304fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7305fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7306fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7307fcf5ef2aSThomas Huth } else { 7308fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7309fcf5ef2aSThomas Huth } 7310fcf5ef2aSThomas Huth 7311fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7312fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7313fcf5ef2aSThomas Huth tcg_temp_free(t0); 7314fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7315fcf5ef2aSThomas Huth } 7316fcf5ef2aSThomas Huth 7317fcf5ef2aSThomas Huth /* tlbwe */ 7318fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7319fcf5ef2aSThomas Huth { 7320fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7321fcf5ef2aSThomas Huth GEN_PRIV; 7322fcf5ef2aSThomas Huth #else 7323fcf5ef2aSThomas Huth CHK_SV; 7324fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7325fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7326fcf5ef2aSThomas Huth } 7327fcf5ef2aSThomas Huth 7328fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7329fcf5ef2aSThomas Huth { 7330fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7331fcf5ef2aSThomas Huth GEN_PRIV; 7332fcf5ef2aSThomas Huth #else 7333fcf5ef2aSThomas Huth TCGv t0; 7334fcf5ef2aSThomas Huth 7335fcf5ef2aSThomas Huth CHK_SV; 7336fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7337fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7338fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7339fcf5ef2aSThomas Huth tcg_temp_free(t0); 7340fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7341fcf5ef2aSThomas Huth } 7342fcf5ef2aSThomas Huth 7343fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7344fcf5ef2aSThomas Huth { 7345fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7346fcf5ef2aSThomas Huth GEN_PRIV; 7347fcf5ef2aSThomas Huth #else 7348fcf5ef2aSThomas Huth TCGv t0; 7349fcf5ef2aSThomas Huth 7350fcf5ef2aSThomas Huth CHK_SV; 7351fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7352fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7353fcf5ef2aSThomas Huth 7354fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7355fcf5ef2aSThomas Huth case 0: 7356fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7357fcf5ef2aSThomas Huth break; 7358fcf5ef2aSThomas Huth case 1: 7359fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7360fcf5ef2aSThomas Huth break; 7361fcf5ef2aSThomas Huth case 3: 7362fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7363fcf5ef2aSThomas Huth break; 7364fcf5ef2aSThomas Huth default: 7365fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7366fcf5ef2aSThomas Huth break; 7367fcf5ef2aSThomas Huth } 7368fcf5ef2aSThomas Huth 7369fcf5ef2aSThomas Huth tcg_temp_free(t0); 7370fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7371fcf5ef2aSThomas Huth } 7372fcf5ef2aSThomas Huth 7373fcf5ef2aSThomas Huth 7374fcf5ef2aSThomas Huth /* wrtee */ 7375fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7376fcf5ef2aSThomas Huth { 7377fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7378fcf5ef2aSThomas Huth GEN_PRIV; 7379fcf5ef2aSThomas Huth #else 7380fcf5ef2aSThomas Huth TCGv t0; 7381fcf5ef2aSThomas Huth 7382fcf5ef2aSThomas Huth CHK_SV; 7383fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7384fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7385fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7386fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7387fcf5ef2aSThomas Huth tcg_temp_free(t0); 7388efe843d8SDavid Gibson /* 7389efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7390efe843d8SDavid Gibson * just set msr_ee to 1 7391fcf5ef2aSThomas Huth */ 7392d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7393fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7394fcf5ef2aSThomas Huth } 7395fcf5ef2aSThomas Huth 7396fcf5ef2aSThomas Huth /* wrteei */ 7397fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7398fcf5ef2aSThomas Huth { 7399fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7400fcf5ef2aSThomas Huth GEN_PRIV; 7401fcf5ef2aSThomas Huth #else 7402fcf5ef2aSThomas Huth CHK_SV; 7403fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7404fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7405fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7406d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7407fcf5ef2aSThomas Huth } else { 7408fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7409fcf5ef2aSThomas Huth } 7410fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7411fcf5ef2aSThomas Huth } 7412fcf5ef2aSThomas Huth 7413fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7414fcf5ef2aSThomas Huth 7415fcf5ef2aSThomas Huth /* dlmzb */ 7416fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7417fcf5ef2aSThomas Huth { 7418fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7419fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7420fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7421fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7422fcf5ef2aSThomas Huth } 7423fcf5ef2aSThomas Huth 7424fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7425fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7426fcf5ef2aSThomas Huth { 7427fcf5ef2aSThomas Huth /* interpreted as no-op */ 7428fcf5ef2aSThomas Huth } 7429fcf5ef2aSThomas Huth 7430fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7431fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7432fcf5ef2aSThomas Huth { 743327a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 743427a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 743527a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 743627a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 743727a3ea7eSBALATON Zoltan } 743827a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7439fcf5ef2aSThomas Huth } 7440fcf5ef2aSThomas Huth 7441fcf5ef2aSThomas Huth /* icbt */ 7442fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7443fcf5ef2aSThomas Huth { 7444efe843d8SDavid Gibson /* 7445efe843d8SDavid Gibson * interpreted as no-op 7446efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7447efe843d8SDavid Gibson * does not generate any exception 7448fcf5ef2aSThomas Huth */ 7449fcf5ef2aSThomas Huth } 7450fcf5ef2aSThomas Huth 7451fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7452fcf5ef2aSThomas Huth 7453fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7454fcf5ef2aSThomas Huth { 7455fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7456fcf5ef2aSThomas Huth GEN_PRIV; 7457fcf5ef2aSThomas Huth #else 7458ebca5e6dSCédric Le Goater CHK_HV; 7459d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 74607af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 74617af1e7b0SCédric Le Goater } else { 7462fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 74637af1e7b0SCédric Le Goater } 7464fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7465fcf5ef2aSThomas Huth } 7466fcf5ef2aSThomas Huth 7467fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7468fcf5ef2aSThomas Huth { 7469fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7470fcf5ef2aSThomas Huth GEN_PRIV; 7471fcf5ef2aSThomas Huth #else 7472ebca5e6dSCédric Le Goater CHK_HV; 7473d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 74747af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 74757af1e7b0SCédric Le Goater } else { 7476fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 74777af1e7b0SCédric Le Goater } 7478fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7479fcf5ef2aSThomas Huth } 7480fcf5ef2aSThomas Huth 74815ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 74825ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 74835ba7ba1dSCédric Le Goater { 74845ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 74855ba7ba1dSCédric Le Goater GEN_PRIV; 74865ba7ba1dSCédric Le Goater #else 74875ba7ba1dSCédric Le Goater CHK_SV; 74885ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 74895ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 74905ba7ba1dSCédric Le Goater } 74915ba7ba1dSCédric Le Goater 74925ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 74935ba7ba1dSCédric Le Goater { 74945ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 74955ba7ba1dSCédric Le Goater GEN_PRIV; 74965ba7ba1dSCédric Le Goater #else 74975ba7ba1dSCédric Le Goater CHK_SV; 74985ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 74995ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 75005ba7ba1dSCédric Le Goater } 75015ba7ba1dSCédric Le Goater #endif 75025ba7ba1dSCédric Le Goater 75037af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 75047af1e7b0SCédric Le Goater { 75057af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 75067af1e7b0SCédric Le Goater GEN_PRIV; 75077af1e7b0SCédric Le Goater #else 75087af1e7b0SCédric Le Goater CHK_HV; 75097af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 75107af1e7b0SCédric Le Goater /* interpreted as no-op */ 75117af1e7b0SCédric Le Goater } 7512fcf5ef2aSThomas Huth 7513fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7514fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7515fcf5ef2aSThomas Huth { 7516fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7517fcf5ef2aSThomas Huth 7518fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7519fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7520fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7521fcf5ef2aSThomas Huth } 7522fcf5ef2aSThomas Huth 7523fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7524fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7525fcf5ef2aSThomas Huth { 7526fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7527fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7528fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7529fcf5ef2aSThomas Huth 7530fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7531fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7532fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7533fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7534fcf5ef2aSThomas Huth } else { 7535fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7536fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7537fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7538fcf5ef2aSThomas Huth } 7539fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7540fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7541fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7542fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7543fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7544fcf5ef2aSThomas Huth } 7545fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7546fcf5ef2aSThomas Huth 7547fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7548fcf5ef2aSThomas Huth { 7549fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7550fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7551fcf5ef2aSThomas Huth return; 7552fcf5ef2aSThomas Huth } 7553fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7554fcf5ef2aSThomas Huth } 7555fcf5ef2aSThomas Huth 7556fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7557fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7558fcf5ef2aSThomas Huth { \ 7559fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7560fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7561fcf5ef2aSThomas Huth return; \ 7562fcf5ef2aSThomas Huth } \ 7563efe843d8SDavid Gibson /* \ 7564efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7565fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7566fcf5ef2aSThomas Huth * \ 7567fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7568fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7569fcf5ef2aSThomas Huth */ \ 7570fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7571fcf5ef2aSThomas Huth } 7572fcf5ef2aSThomas Huth 7573fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7574fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7575fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7576fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7577fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7578fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7579fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7580efe843d8SDavid Gibson 7581b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7582b8b4576eSSuraj Jitindar Singh { 7583efe843d8SDavid Gibson /* Do Nothing */ 7584b8b4576eSSuraj Jitindar Singh } 7585fcf5ef2aSThomas Huth 758680b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 758780b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 758880b8c1eeSNikunj A Dadhania { \ 7589efe843d8SDavid Gibson /* \ 7590efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7591efe843d8SDavid Gibson * implementation of the copy paste facility \ 759280b8c1eeSNikunj A Dadhania */ \ 759380b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 759480b8c1eeSNikunj A Dadhania } 759580b8c1eeSNikunj A Dadhania 759680b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 759780b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 759880b8c1eeSNikunj A Dadhania 7599fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7600fcf5ef2aSThomas Huth { 7601fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7602fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7603fcf5ef2aSThomas Huth return; 7604fcf5ef2aSThomas Huth } 7605efe843d8SDavid Gibson /* 7606efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7607efe843d8SDavid Gibson * simple: 7608fcf5ef2aSThomas Huth * 7609fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7610fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7611fcf5ef2aSThomas Huth */ 7612fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7613fcf5ef2aSThomas Huth } 7614fcf5ef2aSThomas Huth 7615fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7616fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7617fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7618fcf5ef2aSThomas Huth { \ 7619fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7620fcf5ef2aSThomas Huth } 7621fcf5ef2aSThomas Huth 7622fcf5ef2aSThomas Huth #else 7623fcf5ef2aSThomas Huth 7624fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7625fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7626fcf5ef2aSThomas Huth { \ 7627fcf5ef2aSThomas Huth CHK_SV; \ 7628fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7629fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7630fcf5ef2aSThomas Huth return; \ 7631fcf5ef2aSThomas Huth } \ 7632efe843d8SDavid Gibson /* \ 7633efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7634fcf5ef2aSThomas Huth * simple: \ 7635fcf5ef2aSThomas Huth * \ 7636fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7637fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7638fcf5ef2aSThomas Huth */ \ 7639fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7640fcf5ef2aSThomas Huth } 7641fcf5ef2aSThomas Huth 7642fcf5ef2aSThomas Huth #endif 7643fcf5ef2aSThomas Huth 7644fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7645fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7646fcf5ef2aSThomas Huth 76471a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 76481a404c91SMark Cave-Ayland { 7649e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 76501a404c91SMark Cave-Ayland } 76511a404c91SMark Cave-Ayland 76521a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 76531a404c91SMark Cave-Ayland { 7654e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 76551a404c91SMark Cave-Ayland } 76561a404c91SMark Cave-Ayland 7657c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7658c4a18dbfSMark Cave-Ayland { 765937da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7660c4a18dbfSMark Cave-Ayland } 7661c4a18dbfSMark Cave-Ayland 7662c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7663c4a18dbfSMark Cave-Ayland { 766437da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7665c4a18dbfSMark Cave-Ayland } 7666c4a18dbfSMark Cave-Ayland 7667c9826ae9SRichard Henderson /* 7668c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 7669c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 7670c9826ae9SRichard Henderson * proper variable. 7671c9826ae9SRichard Henderson */ 7672c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7673c9826ae9SRichard Henderson do { \ 7674c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7675c9826ae9SRichard Henderson return false; \ 7676c9826ae9SRichard Henderson } \ 7677c9826ae9SRichard Henderson } while (0) 7678c9826ae9SRichard Henderson 7679c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7680c9826ae9SRichard Henderson do { \ 7681c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7682c9826ae9SRichard Henderson return false; \ 7683c9826ae9SRichard Henderson } \ 7684c9826ae9SRichard Henderson } while (0) 7685c9826ae9SRichard Henderson 7686c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7687c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 7688c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 7689c9826ae9SRichard Henderson #else 7690c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7691c9826ae9SRichard Henderson #endif 7692c9826ae9SRichard Henderson 7693*99082815SRichard Henderson #include "decode-insn32.c.inc" 7694*99082815SRichard Henderson #include "decode-insn64.c.inc" 7695*99082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 7696*99082815SRichard Henderson 7697139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7698fcf5ef2aSThomas Huth 7699139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7700fcf5ef2aSThomas Huth 7701139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7702fcf5ef2aSThomas Huth 7703139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7704fcf5ef2aSThomas Huth 7705139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7706fcf5ef2aSThomas Huth 77075cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 77085cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 77095cb091a4SNikunj A Dadhania { 77105cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 77115cb091a4SNikunj A Dadhania case 0: /* lfdp */ 77125cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 77135cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 77145cb091a4SNikunj A Dadhania } 77155cb091a4SNikunj A Dadhania break; 77165cb091a4SNikunj A Dadhania case 2: /* lxsd */ 77175cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 77185cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 77195cb091a4SNikunj A Dadhania } 77205cb091a4SNikunj A Dadhania break; 77215cb091a4SNikunj A Dadhania case 3: /* lxssp */ 77225cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 77235cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 77245cb091a4SNikunj A Dadhania } 77255cb091a4SNikunj A Dadhania break; 77265cb091a4SNikunj A Dadhania } 77275cb091a4SNikunj A Dadhania return gen_invalid(ctx); 77285cb091a4SNikunj A Dadhania } 77295cb091a4SNikunj A Dadhania 7730d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7731e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7732e3001664SNikunj A Dadhania { 7733e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7734e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7735e3001664SNikunj A Dadhania case 1: /* lxv */ 7736d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7737d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7738d59ba583SNikunj A Dadhania } 7739e3001664SNikunj A Dadhania break; 7740e3001664SNikunj A Dadhania case 5: /* stxv */ 7741d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7742d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7743d59ba583SNikunj A Dadhania } 7744e3001664SNikunj A Dadhania break; 7745e3001664SNikunj A Dadhania } 7746e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7747e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7748e3001664SNikunj A Dadhania case 0: /* stfdp */ 7749e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7750e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7751e3001664SNikunj A Dadhania } 7752e3001664SNikunj A Dadhania break; 7753e3001664SNikunj A Dadhania case 2: /* stxsd */ 7754e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7755e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7756e3001664SNikunj A Dadhania } 7757e3001664SNikunj A Dadhania break; 7758e3001664SNikunj A Dadhania case 3: /* stxssp */ 7759e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7760e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7761e3001664SNikunj A Dadhania } 7762e3001664SNikunj A Dadhania break; 7763e3001664SNikunj A Dadhania } 7764e3001664SNikunj A Dadhania } 7765e3001664SNikunj A Dadhania return gen_invalid(ctx); 7766e3001664SNikunj A Dadhania } 7767e3001664SNikunj A Dadhania 77689d69cfa2SLijun Pan #if defined(TARGET_PPC64) 77699d69cfa2SLijun Pan /* brd */ 77709d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 77719d69cfa2SLijun Pan { 77729d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 77739d69cfa2SLijun Pan } 77749d69cfa2SLijun Pan 77759d69cfa2SLijun Pan /* brw */ 77769d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 77779d69cfa2SLijun Pan { 77789d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 77799d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 77809d69cfa2SLijun Pan 77819d69cfa2SLijun Pan } 77829d69cfa2SLijun Pan 77839d69cfa2SLijun Pan /* brh */ 77849d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 77859d69cfa2SLijun Pan { 77869d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 77879d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 77889d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 77899d69cfa2SLijun Pan 77909d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 77919d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 77929d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 77939d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 77949d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 77959d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 77969d69cfa2SLijun Pan 77979d69cfa2SLijun Pan tcg_temp_free_i64(t0); 77989d69cfa2SLijun Pan tcg_temp_free_i64(t1); 77999d69cfa2SLijun Pan tcg_temp_free_i64(t2); 78009d69cfa2SLijun Pan } 78019d69cfa2SLijun Pan #endif 78029d69cfa2SLijun Pan 7803fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 78049d69cfa2SLijun Pan #if defined(TARGET_PPC64) 78059d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 78069d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 78079d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 78089d69cfa2SLijun Pan #endif 7809fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7810fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7811fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7812fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7813fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7814fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7815fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7816fcf5ef2aSThomas Huth #endif 7817fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7818fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7819fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7820fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7821fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7822fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7823fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7824fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7825fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7826fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7827fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7828fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7829fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7830fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7831fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7832fcf5ef2aSThomas Huth #endif 7833fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7834fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7835fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7836fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7837fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7838fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7839fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 784080b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7841b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 784280b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7843fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7844fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7845fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7846fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7847fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7848fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7849fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7850fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7851fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7852fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7853fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7854fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7855fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7856fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7857fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7858fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7859fcf5ef2aSThomas Huth #endif 7860fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7861fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7862fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7863fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7864fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7865fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7866fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7867fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7868fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7869fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7870fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7871fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7872fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7873fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7874fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7875fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7876fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7877fcf5ef2aSThomas Huth #endif 7878fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7879fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 7880fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7881fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7882fcf5ef2aSThomas Huth #endif 78835cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 78845cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7885d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7886e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7887fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7888fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7889fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7890fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7891fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7892fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7893c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7894fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7895fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7896fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7897fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7898a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7899a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7900fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7901fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7902fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7903fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7904a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7905a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7906fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7907fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7908fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7909fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7910fcf5ef2aSThomas Huth #endif 7911fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7912fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7913c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7914fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7915fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7916fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7917fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7918fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7919fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7920fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7921fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7922fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 79233c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 79243c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 79253c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 79263c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 79273c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 79283c89b8d6SNicholas Piggin #endif 7929cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7930fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7931fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7932fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7933fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7934fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7935fcf5ef2aSThomas Huth #endif 79363c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 79373c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 79383c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7939fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7940fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7941fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7942fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7943fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7944fcf5ef2aSThomas Huth #endif 7945fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7946fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7947fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7948fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7949fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7950fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7951fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7952fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7953fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7954b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7955fcf5ef2aSThomas Huth #endif 7956fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7957fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7958fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 795950728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7960fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7961fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 796250728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7963fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 796450728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7965fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 796650728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7967fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7968fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 796950728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7970fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 797199d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7972fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7973fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 797450728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7975fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7976fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7977fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7978fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7979fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7980fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7981fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7982fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7983fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7984fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7985fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7986fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7987fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7988fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7989fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7990fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7991fcf5ef2aSThomas Huth #endif 7992fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7993efe843d8SDavid Gibson /* 7994efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7995efe843d8SDavid Gibson * different ISA versions 7996efe843d8SDavid Gibson */ 7997fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7998fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7999c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 8000c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 8001fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 8002fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8003fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 8004fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 8005a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 800662d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8007fcf5ef2aSThomas Huth #endif 8008fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 8009fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 8010fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 8011fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 8012fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 8013fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 8014fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 8015fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 8016fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 8017fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 8018fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 8019fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8020fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 8021fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 8022fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 8023fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 8024fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 8025fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 8026fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 8027fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8028fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 8029fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 8030fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 8031fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 8032fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 8033fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 8034fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 8035fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 8036fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 8037fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 8038fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 8039fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 8040fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 8041fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 8042fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 8043fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 8044fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 8045fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 8046fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 8047fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 8048fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 8049fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 8050fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 8051fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 8052fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 8053fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 8054fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 8055fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 8056fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 8057fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8058fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8059fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 8060fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 8061fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8062fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8063fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 8064fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 8065fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 8066fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 8067fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 8068fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 8069fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 8070fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 8071fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 8072fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 8073fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 8074fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 8075fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 8076fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 8077fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 8078fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 8079fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 8080fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 8081fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 8082fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 8083fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 8084fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 8085fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 8086fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 8087fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 8088fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 8089fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8090fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 8091fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8092fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 8093fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8094fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 8095fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8096fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 8097fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8098fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 8099fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 8100fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 8101fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 81027af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 81037af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 8104fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8105fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8106fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8107fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8108fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 810927a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8110fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8111fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 81120c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 81130c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8114fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8115fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8116fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8117fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8118fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8119fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8120fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8121fcf5ef2aSThomas Huth PPC2_ISA300), 8122fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 81235ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 81245ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 81255ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 81265ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8127fcf5ef2aSThomas Huth #endif 8128fcf5ef2aSThomas Huth 8129fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8130fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8131fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8132fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8133fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8134fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8135fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8136fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8137fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8138fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8139fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8140fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8141fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8142fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8143fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 81444c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8145fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8146fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8147fcf5ef2aSThomas Huth 8148fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8149fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8150fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8151fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8152fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8153fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8154fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8155fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8156fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8157fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8158fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8159fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8160fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8161fcf5ef2aSThomas Huth 8162fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8163fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8164fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8165fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8166fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8167fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8168fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8169fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8170fcf5ef2aSThomas Huth 8171fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8172fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8173fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8174fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8175fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8176fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8177fcf5ef2aSThomas Huth 8178fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8179fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8180fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8181fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8182fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8183fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8184fcf5ef2aSThomas Huth #endif 8185fcf5ef2aSThomas Huth 8186fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8187fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8188fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8189fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8190fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8191fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8192fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8193fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8194fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8195fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8196fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8197fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8198fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8199fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8200fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8201fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8202fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8203fcf5ef2aSThomas Huth 8204fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8205fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8206fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8207fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8208fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8209fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8210fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8211fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8212fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8213fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8214fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8215fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8216fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8217fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8218fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8219fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8220fcf5ef2aSThomas Huth #endif 8221fcf5ef2aSThomas Huth 8222fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8223fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8224fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8225fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8226fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8227fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8228fcf5ef2aSThomas Huth PPC_64B) 8229fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8230fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8231fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8232fcf5ef2aSThomas Huth PPC_64B), \ 8233fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8234fcf5ef2aSThomas Huth PPC_64B), \ 8235fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8236fcf5ef2aSThomas Huth PPC_64B) 8237fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8238fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8239fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8240fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8241fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8242fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8243fcf5ef2aSThomas Huth #endif 8244fcf5ef2aSThomas Huth 8245fcf5ef2aSThomas Huth #undef GEN_LD 8246fcf5ef2aSThomas Huth #undef GEN_LDU 8247fcf5ef2aSThomas Huth #undef GEN_LDUX 8248fcf5ef2aSThomas Huth #undef GEN_LDX_E 8249fcf5ef2aSThomas Huth #undef GEN_LDS 8250fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 8251fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8252fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 8253fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 8254fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 8255fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8256fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8257fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8258fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 8259fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 8260fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 8261fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 8262fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 8263fcf5ef2aSThomas Huth 8264fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 8265fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 8266fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 8267fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 8268fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8269fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 8270fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 8271fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 8272fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 8273fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8274fcf5ef2aSThomas Huth 8275fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8276fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8277fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8278fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8279fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8280fcf5ef2aSThomas Huth #endif 8281fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8282fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8283fcf5ef2aSThomas Huth 828450728199SRoman Kapl /* External PID based load */ 828550728199SRoman Kapl #undef GEN_LDEPX 828650728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 828750728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 828850728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 828950728199SRoman Kapl 829050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 829150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 829250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 829350728199SRoman Kapl #if defined(TARGET_PPC64) 829450728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 829550728199SRoman Kapl #endif 829650728199SRoman Kapl 8297fcf5ef2aSThomas Huth #undef GEN_ST 8298fcf5ef2aSThomas Huth #undef GEN_STU 8299fcf5ef2aSThomas Huth #undef GEN_STUX 8300fcf5ef2aSThomas Huth #undef GEN_STX_E 8301fcf5ef2aSThomas Huth #undef GEN_STS 8302fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8303fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8304fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8305fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8306fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8307fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8308fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 83090123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8310fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8311fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8312fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8313fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8314fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8315fcf5ef2aSThomas Huth 8316fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8317fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8318fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8319fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8320fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8321fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8322fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8323fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8324fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8325fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8326fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8327fcf5ef2aSThomas Huth #endif 8328fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8329fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8330fcf5ef2aSThomas Huth 833150728199SRoman Kapl #undef GEN_STEPX 833250728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 833350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 833450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 833550728199SRoman Kapl 833650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 833750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 833850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 833950728199SRoman Kapl #if defined(TARGET_PPC64) 834050728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 834150728199SRoman Kapl #endif 834250728199SRoman Kapl 8343fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8344fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8345fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8346fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8347fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8348fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8349fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8350fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8351fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8352fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8353fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8354fcf5ef2aSThomas Huth 8355fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8356fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8357fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8358fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8359fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8360fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8361fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8362fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8363fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8364fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8365fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8366fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8367fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8368fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8369fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8370fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8371fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8372fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8373fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8374fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8375fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8376fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8377fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8378fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8379fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8380fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8381fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8382fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8383fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8384fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8385fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8386fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8387fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8388fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8389fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8390fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8391fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8392fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8393fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8394fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8395fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8396fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8397fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8398fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8399fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8400fcf5ef2aSThomas Huth 8401fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8402fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8403fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8404fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8405fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8406fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8407fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8408fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8409fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8410fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8411fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8412fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8413fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8414fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8415fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8416fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8417fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8418fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8419fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8420fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8421fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8422fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8423fcf5ef2aSThomas Huth 8424139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8425fcf5ef2aSThomas Huth 8426139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8427fcf5ef2aSThomas Huth 8428139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8429fcf5ef2aSThomas Huth 8430139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8431fcf5ef2aSThomas Huth 8432139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8433fcf5ef2aSThomas Huth }; 8434fcf5ef2aSThomas Huth 84357468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 84367468e2c8SBruno Larsen (billionai) /* Opcode types */ 84377468e2c8SBruno Larsen (billionai) enum { 84387468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 84397468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 84407468e2c8SBruno Larsen (billionai) }; 84417468e2c8SBruno Larsen (billionai) 84427468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 84437468e2c8SBruno Larsen (billionai) 84447468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 84457468e2c8SBruno Larsen (billionai) { 84467468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 84477468e2c8SBruno Larsen (billionai) } 84487468e2c8SBruno Larsen (billionai) 84497468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 84507468e2c8SBruno Larsen (billionai) { 84517468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 84527468e2c8SBruno Larsen (billionai) } 84537468e2c8SBruno Larsen (billionai) 84547468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 84557468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 84567468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 84577468e2c8SBruno Larsen (billionai) { 84587468e2c8SBruno Larsen (billionai) int i; 84597468e2c8SBruno Larsen (billionai) 84607468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 84617468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 84627468e2c8SBruno Larsen (billionai) } 84637468e2c8SBruno Larsen (billionai) } 84647468e2c8SBruno Larsen (billionai) 84657468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 84667468e2c8SBruno Larsen (billionai) { 84677468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 84687468e2c8SBruno Larsen (billionai) 84697468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 84707468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 84717468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 84727468e2c8SBruno Larsen (billionai) 84737468e2c8SBruno Larsen (billionai) return 0; 84747468e2c8SBruno Larsen (billionai) } 84757468e2c8SBruno Larsen (billionai) 84767468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 84777468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 84787468e2c8SBruno Larsen (billionai) { 84797468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 84807468e2c8SBruno Larsen (billionai) return -1; 84817468e2c8SBruno Larsen (billionai) } 84827468e2c8SBruno Larsen (billionai) table[idx] = handler; 84837468e2c8SBruno Larsen (billionai) 84847468e2c8SBruno Larsen (billionai) return 0; 84857468e2c8SBruno Larsen (billionai) } 84867468e2c8SBruno Larsen (billionai) 84877468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 84887468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 84897468e2c8SBruno Larsen (billionai) { 84907468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 84917468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 84927468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 84937468e2c8SBruno Larsen (billionai) return -1; 84947468e2c8SBruno Larsen (billionai) } 84957468e2c8SBruno Larsen (billionai) 84967468e2c8SBruno Larsen (billionai) return 0; 84977468e2c8SBruno Larsen (billionai) } 84987468e2c8SBruno Larsen (billionai) 84997468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 85007468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 85017468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 85027468e2c8SBruno Larsen (billionai) { 85037468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 85047468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 85057468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 85067468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 85077468e2c8SBruno Larsen (billionai) return -1; 85087468e2c8SBruno Larsen (billionai) } 85097468e2c8SBruno Larsen (billionai) } else { 85107468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 85117468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 85127468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 85137468e2c8SBruno Larsen (billionai) return -1; 85147468e2c8SBruno Larsen (billionai) } 85157468e2c8SBruno Larsen (billionai) } 85167468e2c8SBruno Larsen (billionai) if (handler != NULL && 85177468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 85187468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 85197468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 85207468e2c8SBruno Larsen (billionai) return -1; 85217468e2c8SBruno Larsen (billionai) } 85227468e2c8SBruno Larsen (billionai) 85237468e2c8SBruno Larsen (billionai) return 0; 85247468e2c8SBruno Larsen (billionai) } 85257468e2c8SBruno Larsen (billionai) 85267468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 85277468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 85287468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 85297468e2c8SBruno Larsen (billionai) { 85307468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 85317468e2c8SBruno Larsen (billionai) } 85327468e2c8SBruno Larsen (billionai) 85337468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 85347468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 85357468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 85367468e2c8SBruno Larsen (billionai) { 85377468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 85387468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 85397468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 85407468e2c8SBruno Larsen (billionai) return -1; 85417468e2c8SBruno Larsen (billionai) } 85427468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 85437468e2c8SBruno Larsen (billionai) handler) < 0) { 85447468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 85457468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 85467468e2c8SBruno Larsen (billionai) return -1; 85477468e2c8SBruno Larsen (billionai) } 85487468e2c8SBruno Larsen (billionai) 85497468e2c8SBruno Larsen (billionai) return 0; 85507468e2c8SBruno Larsen (billionai) } 85517468e2c8SBruno Larsen (billionai) 85527468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 85537468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 85547468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 85557468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 85567468e2c8SBruno Larsen (billionai) { 85577468e2c8SBruno Larsen (billionai) opc_handler_t **table; 85587468e2c8SBruno Larsen (billionai) 85597468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 85607468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 85617468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 85627468e2c8SBruno Larsen (billionai) return -1; 85637468e2c8SBruno Larsen (billionai) } 85647468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 85657468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 85667468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 85677468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 85687468e2c8SBruno Larsen (billionai) return -1; 85697468e2c8SBruno Larsen (billionai) } 85707468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 85717468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 85727468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 85737468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 85747468e2c8SBruno Larsen (billionai) return -1; 85757468e2c8SBruno Larsen (billionai) } 85767468e2c8SBruno Larsen (billionai) return 0; 85777468e2c8SBruno Larsen (billionai) } 85787468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 85797468e2c8SBruno Larsen (billionai) { 85807468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 85817468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 85827468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 85837468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 85847468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 85857468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 85867468e2c8SBruno Larsen (billionai) return -1; 85877468e2c8SBruno Larsen (billionai) } 85887468e2c8SBruno Larsen (billionai) } else { 85897468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 85907468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 85917468e2c8SBruno Larsen (billionai) return -1; 85927468e2c8SBruno Larsen (billionai) } 85937468e2c8SBruno Larsen (billionai) } 85947468e2c8SBruno Larsen (billionai) } else { 85957468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 85967468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 85977468e2c8SBruno Larsen (billionai) return -1; 85987468e2c8SBruno Larsen (billionai) } 85997468e2c8SBruno Larsen (billionai) } 86007468e2c8SBruno Larsen (billionai) } else { 86017468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 86027468e2c8SBruno Larsen (billionai) return -1; 86037468e2c8SBruno Larsen (billionai) } 86047468e2c8SBruno Larsen (billionai) } 86057468e2c8SBruno Larsen (billionai) 86067468e2c8SBruno Larsen (billionai) return 0; 86077468e2c8SBruno Larsen (billionai) } 86087468e2c8SBruno Larsen (billionai) 86097468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 86107468e2c8SBruno Larsen (billionai) { 86117468e2c8SBruno Larsen (billionai) int i, count, tmp; 86127468e2c8SBruno Larsen (billionai) 86137468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 86147468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 86157468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 86167468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86177468e2c8SBruno Larsen (billionai) } 86187468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 86197468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 86207468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 86217468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 86227468e2c8SBruno Larsen (billionai) if (tmp == 0) { 86237468e2c8SBruno Larsen (billionai) free(table[i]); 86247468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86257468e2c8SBruno Larsen (billionai) } else { 86267468e2c8SBruno Larsen (billionai) count++; 86277468e2c8SBruno Larsen (billionai) } 86287468e2c8SBruno Larsen (billionai) } else { 86297468e2c8SBruno Larsen (billionai) count++; 86307468e2c8SBruno Larsen (billionai) } 86317468e2c8SBruno Larsen (billionai) } 86327468e2c8SBruno Larsen (billionai) } 86337468e2c8SBruno Larsen (billionai) 86347468e2c8SBruno Larsen (billionai) return count; 86357468e2c8SBruno Larsen (billionai) } 86367468e2c8SBruno Larsen (billionai) 86377468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 86387468e2c8SBruno Larsen (billionai) { 86397468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 86407468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 86417468e2c8SBruno Larsen (billionai) } 86427468e2c8SBruno Larsen (billionai) } 86437468e2c8SBruno Larsen (billionai) 86447468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 86457468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 86467468e2c8SBruno Larsen (billionai) { 86477468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 86487468e2c8SBruno Larsen (billionai) opcode_t *opc; 86497468e2c8SBruno Larsen (billionai) 86507468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 86517468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 86527468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 86537468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 86547468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 86557468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 86567468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 86577468e2c8SBruno Larsen (billionai) opc->opc3); 86587468e2c8SBruno Larsen (billionai) return; 86597468e2c8SBruno Larsen (billionai) } 86607468e2c8SBruno Larsen (billionai) } 86617468e2c8SBruno Larsen (billionai) } 86627468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 86637468e2c8SBruno Larsen (billionai) fflush(stdout); 86647468e2c8SBruno Larsen (billionai) fflush(stderr); 86657468e2c8SBruno Larsen (billionai) } 86667468e2c8SBruno Larsen (billionai) 86677468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 86687468e2c8SBruno Larsen (billionai) { 86697468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 86707468e2c8SBruno Larsen (billionai) int i, j, k; 86717468e2c8SBruno Larsen (billionai) 86727468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 86737468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 86747468e2c8SBruno Larsen (billionai) continue; 86757468e2c8SBruno Larsen (billionai) } 86767468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 86777468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 86787468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 86797468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 86807468e2c8SBruno Larsen (billionai) continue; 86817468e2c8SBruno Larsen (billionai) } 86827468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 86837468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 86847468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 86857468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 86867468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 86877468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 86887468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 86897468e2c8SBruno Larsen (billionai) } 86907468e2c8SBruno Larsen (billionai) } 86917468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 86927468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 86937468e2c8SBruno Larsen (billionai) } 86947468e2c8SBruno Larsen (billionai) } 86957468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 86967468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 86977468e2c8SBruno Larsen (billionai) } 86987468e2c8SBruno Larsen (billionai) } 86997468e2c8SBruno Larsen (billionai) } 87007468e2c8SBruno Larsen (billionai) 87017468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 87027468e2c8SBruno Larsen (billionai) { 87037468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 87047468e2c8SBruno Larsen (billionai) 87057468e2c8SBruno Larsen (billionai) /* 87067468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 87077468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 87087468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 87097468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 87107468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 87117468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 87127468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 87137468e2c8SBruno Larsen (billionai) */ 87147468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 87157468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 87167468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 87177468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 87187468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 87197468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 87207468e2c8SBruno Larsen (billionai) } 87217468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 87227468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 87237468e2c8SBruno Larsen (billionai) return 0; 87247468e2c8SBruno Larsen (billionai) } 87257468e2c8SBruno Larsen (billionai) 8726624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8727624cb07fSRichard Henderson { 8728624cb07fSRichard Henderson opc_handler_t **table, *handler; 8729624cb07fSRichard Henderson uint32_t inval; 8730624cb07fSRichard Henderson 8731624cb07fSRichard Henderson ctx->opcode = insn; 8732624cb07fSRichard Henderson 8733624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8734624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8735624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8736624cb07fSRichard Henderson 8737624cb07fSRichard Henderson table = cpu->opcodes; 8738624cb07fSRichard Henderson handler = table[opc1(insn)]; 8739624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8740624cb07fSRichard Henderson table = ind_table(handler); 8741624cb07fSRichard Henderson handler = table[opc2(insn)]; 8742624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8743624cb07fSRichard Henderson table = ind_table(handler); 8744624cb07fSRichard Henderson handler = table[opc3(insn)]; 8745624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8746624cb07fSRichard Henderson table = ind_table(handler); 8747624cb07fSRichard Henderson handler = table[opc4(insn)]; 8748624cb07fSRichard Henderson } 8749624cb07fSRichard Henderson } 8750624cb07fSRichard Henderson } 8751624cb07fSRichard Henderson 8752624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8753624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8754624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8755624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8756624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8757624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8758624cb07fSRichard Henderson insn, ctx->cia); 8759624cb07fSRichard Henderson return false; 8760624cb07fSRichard Henderson } 8761624cb07fSRichard Henderson 8762624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8763624cb07fSRichard Henderson && Rc(insn))) { 8764624cb07fSRichard Henderson inval = handler->inval2; 8765624cb07fSRichard Henderson } else { 8766624cb07fSRichard Henderson inval = handler->inval1; 8767624cb07fSRichard Henderson } 8768624cb07fSRichard Henderson 8769624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8770624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8771624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8772624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8773624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8774624cb07fSRichard Henderson insn, ctx->cia); 8775624cb07fSRichard Henderson return false; 8776624cb07fSRichard Henderson } 8777624cb07fSRichard Henderson 8778624cb07fSRichard Henderson handler->handler(ctx); 8779624cb07fSRichard Henderson return true; 8780624cb07fSRichard Henderson } 8781624cb07fSRichard Henderson 8782b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8783fcf5ef2aSThomas Huth { 8784b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 87859c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 87862df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8787fcf5ef2aSThomas Huth 8788b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 87892df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8790d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 87912df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 87922df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 8793b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 8794b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 8795b0c2d521SEmilio G. Cota ctx->access_type = -1; 8796d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 87972df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8798b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 87990e3bf489SRoman Kapl ctx->flags = env->flags; 8800fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 88012df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8802b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8803fcf5ef2aSThomas Huth #endif 8804e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8805e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 8806d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 8807fcf5ef2aSThomas Huth 88082df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 88092df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 88102df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 88112df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 88122df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8813f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 88142df4fe7aSRichard Henderson 8815b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 88162df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 88172df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 8818efe843d8SDavid Gibson } 88192df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 8820b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8821efe843d8SDavid Gibson } 8822b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 8823b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 8824fcf5ef2aSThomas Huth } 8825b0c2d521SEmilio G. Cota 882613b45575SRichard Henderson if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) { 882713b45575SRichard Henderson ctx->base.max_insns = 1; 8828fcf5ef2aSThomas Huth } 882913b45575SRichard Henderson } 8830fcf5ef2aSThomas Huth 8831b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8832b0c2d521SEmilio G. Cota { 8833b0c2d521SEmilio G. Cota } 8834fcf5ef2aSThomas Huth 8835b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8836b0c2d521SEmilio G. Cota { 8837b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 8838b0c2d521SEmilio G. Cota } 8839b0c2d521SEmilio G. Cota 8840b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 8841b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 8842b0c2d521SEmilio G. Cota { 8843b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8844b0c2d521SEmilio G. Cota 88452736fc61SRichard Henderson gen_update_nip(ctx, ctx->base.pc_next); 8846b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 8847efe843d8SDavid Gibson /* 8848efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 8849efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 8850efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 8851efe843d8SDavid Gibson * setting tb->size below does the right thing. 8852efe843d8SDavid Gibson */ 8853b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 8854b0c2d521SEmilio G. Cota return true; 8855fcf5ef2aSThomas Huth } 8856fcf5ef2aSThomas Huth 8857*99082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 8858*99082815SRichard Henderson { 8859*99082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 8860*99082815SRichard Henderson return opc1(insn) == 1; 8861*99082815SRichard Henderson } 8862*99082815SRichard Henderson 8863b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8864b0c2d521SEmilio G. Cota { 8865b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 886628876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 8867b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 8868*99082815SRichard Henderson target_ulong pc; 8869624cb07fSRichard Henderson uint32_t insn; 8870624cb07fSRichard Henderson bool ok; 8871b0c2d521SEmilio G. Cota 8872fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 8873fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8874b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8875b0c2d521SEmilio G. Cota 8876*99082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 8877*99082815SRichard Henderson insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); 8878*99082815SRichard Henderson ctx->base.pc_next = pc += 4; 8879fcf5ef2aSThomas Huth 8880*99082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 8881*99082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 8882*99082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 8883*99082815SRichard Henderson } else if ((pc & 63) == 0) { 8884*99082815SRichard Henderson /* 8885*99082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 8886*99082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 8887*99082815SRichard Henderson * 64-byte address boundary (system alignment error). 8888*99082815SRichard Henderson */ 8889*99082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 8890*99082815SRichard Henderson ok = true; 8891*99082815SRichard Henderson } else { 8892*99082815SRichard Henderson uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); 8893*99082815SRichard Henderson ctx->base.pc_next = pc += 4; 8894*99082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 8895*99082815SRichard Henderson } 8896624cb07fSRichard Henderson if (!ok) { 8897624cb07fSRichard Henderson gen_invalid(ctx); 8898fcf5ef2aSThomas Huth } 8899624cb07fSRichard Henderson 890064a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 8901*99082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 890264a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 890364a0f644SRichard Henderson } 890464a0f644SRichard Henderson 890551eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 8906fcf5ef2aSThomas Huth } 8907b0c2d521SEmilio G. Cota 8908b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8909b0c2d521SEmilio G. Cota { 8910b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8911a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 8912a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 891313b45575SRichard Henderson int sse; 8914b0c2d521SEmilio G. Cota 8915a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 8916a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 89173d8a5b69SRichard Henderson return; 89183d8a5b69SRichard Henderson } 89193d8a5b69SRichard Henderson 8920a9b5b3d0SRichard Henderson /* Honor single stepping. */ 892113b45575SRichard Henderson sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP); 892213b45575SRichard Henderson if (unlikely(sse)) { 8923a9b5b3d0SRichard Henderson switch (is_jmp) { 8924a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8925a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8926a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8927a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8928a9b5b3d0SRichard Henderson break; 8929a9b5b3d0SRichard Henderson case DISAS_EXIT: 8930a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8931a9b5b3d0SRichard Henderson break; 8932a9b5b3d0SRichard Henderson default: 8933a9b5b3d0SRichard Henderson g_assert_not_reached(); 8934fcf5ef2aSThomas Huth } 893513b45575SRichard Henderson 893613b45575SRichard Henderson if (sse & GDBSTUB_SINGLE_STEP) { 8937a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 8938a9b5b3d0SRichard Henderson return; 8939a9b5b3d0SRichard Henderson } 894013b45575SRichard Henderson /* else CPU_SINGLE_STEP... */ 894113b45575SRichard Henderson if (nip <= 0x100 || nip > 0xf00) { 894213b45575SRichard Henderson gen_exception(ctx, gen_prep_dbgex(ctx)); 894313b45575SRichard Henderson return; 894413b45575SRichard Henderson } 894513b45575SRichard Henderson } 8946a9b5b3d0SRichard Henderson 8947a9b5b3d0SRichard Henderson switch (is_jmp) { 8948a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8949a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 8950a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 8951a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8952a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 8953a9b5b3d0SRichard Henderson break; 8954a9b5b3d0SRichard Henderson } 8955a9b5b3d0SRichard Henderson /* fall through */ 8956a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8957a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8958a9b5b3d0SRichard Henderson /* fall through */ 8959a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8960a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 8961a9b5b3d0SRichard Henderson break; 8962a9b5b3d0SRichard Henderson 8963a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8964a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8965a9b5b3d0SRichard Henderson /* fall through */ 8966a9b5b3d0SRichard Henderson case DISAS_EXIT: 896707ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8968a9b5b3d0SRichard Henderson break; 8969a9b5b3d0SRichard Henderson 8970a9b5b3d0SRichard Henderson default: 8971a9b5b3d0SRichard Henderson g_assert_not_reached(); 8972fcf5ef2aSThomas Huth } 8973fcf5ef2aSThomas Huth } 8974b0c2d521SEmilio G. Cota 8975b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8976b0c2d521SEmilio G. Cota { 8977b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8978b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8979b0c2d521SEmilio G. Cota } 8980b0c2d521SEmilio G. Cota 8981b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8982b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8983b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8984b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8985b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 8986b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8987b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8988b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8989b0c2d521SEmilio G. Cota }; 8990b0c2d521SEmilio G. Cota 89918b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8992b0c2d521SEmilio G. Cota { 8993b0c2d521SEmilio G. Cota DisasContext ctx; 8994b0c2d521SEmilio G. Cota 89958b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8996fcf5ef2aSThomas Huth } 8997fcf5ef2aSThomas Huth 8998fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8999fcf5ef2aSThomas Huth target_ulong *data) 9000fcf5ef2aSThomas Huth { 9001fcf5ef2aSThomas Huth env->nip = data[0]; 9002fcf5ef2aSThomas Huth } 9003