1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33b6bac4bcSEmilio G. Cota #include "exec/translator.h" 34fcf5ef2aSThomas Huth #include "exec/log.h" 35f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3699e964efSFabiano Rosas #include "spr_common.h" 37eeaaefe9SLeandro Lupori #include "power8-pmu.h" 38fcf5ef2aSThomas Huth 393e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 403e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 41fcf5ef2aSThomas Huth 42d53106c9SRichard Henderson #define HELPER_H "helper.h" 43d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 44d53106c9SRichard Henderson #undef HELPER_H 45d53106c9SRichard Henderson 46fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 47fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 50efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76392d328aSNicholas Piggin static TCGv cpu_reserve_length; 77253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 78894448aeSRichard Henderson static TCGv cpu_reserve_val2; 79fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 80fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char *p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 125fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 131fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 133fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 135fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 137dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 139dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 143fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 144fcf5ef2aSThomas Huth "reserve_addr"); 145392d328aSNicholas Piggin cpu_reserve_length = tcg_global_mem_new(cpu_env, 146392d328aSNicholas Piggin offsetof(CPUPPCState, 147392d328aSNicholas Piggin reserve_length), 148392d328aSNicholas Piggin "reserve_length"); 149253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 150253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 151253ce7b2SNikunj A Dadhania "reserve_val"); 152894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 153894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 154894448aeSRichard Henderson "reserve_val2"); 155fcf5ef2aSThomas Huth 156fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 157fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 158fcf5ef2aSThomas Huth 159fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 160efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 161efe843d8SDavid Gibson "access_type"); 162fcf5ef2aSThomas Huth } 163fcf5ef2aSThomas Huth 164fcf5ef2aSThomas Huth /* internal defines */ 165fcf5ef2aSThomas Huth struct DisasContext { 166b6bac4bcSEmilio G. Cota DisasContextBase base; 1672c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 168fcf5ef2aSThomas Huth uint32_t opcode; 169fcf5ef2aSThomas Huth /* Routine used to access memory */ 170fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 171fcf5ef2aSThomas Huth bool lazy_tlb_flush; 172fcf5ef2aSThomas Huth bool need_access_type; 173fcf5ef2aSThomas Huth int mem_idx; 174fcf5ef2aSThomas Huth int access_type; 175fcf5ef2aSThomas Huth /* Translation flags */ 17614776ab5STony Nguyen MemOp default_tcg_memop_mask; 177fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 178fcf5ef2aSThomas Huth bool sf_mode; 179fcf5ef2aSThomas Huth bool has_cfar; 180fcf5ef2aSThomas Huth #endif 181fcf5ef2aSThomas Huth bool fpu_enabled; 182fcf5ef2aSThomas Huth bool altivec_enabled; 183fcf5ef2aSThomas Huth bool vsx_enabled; 184fcf5ef2aSThomas Huth bool spe_enabled; 185fcf5ef2aSThomas Huth bool tm_enabled; 186c6fd28fdSSuraj Jitindar Singh bool gtse; 1871db3632aSMatheus Ferst bool hr; 188f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 189f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1908b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1918b3d1c49SLeandro Lupori bool pmc_other; 19246d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 193fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 194fcf5ef2aSThomas Huth int singlestep_enabled; 1950e3bf489SRoman Kapl uint32_t flags; 196fcf5ef2aSThomas Huth uint64_t insns_flags; 197fcf5ef2aSThomas Huth uint64_t insns_flags2; 198fcf5ef2aSThomas Huth }; 199fcf5ef2aSThomas Huth 200a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 201a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 202a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 203a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 204a9b5b3d0SRichard Henderson 205fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 206fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 207fcf5ef2aSThomas Huth { 208ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 209fcf5ef2aSThomas Huth return ctx->le_mode; 210fcf5ef2aSThomas Huth #else 211fcf5ef2aSThomas Huth return !ctx->le_mode; 212fcf5ef2aSThomas Huth #endif 213fcf5ef2aSThomas Huth } 214fcf5ef2aSThomas Huth 215fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 216fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 217fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 218fcf5ef2aSThomas Huth #else 219fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 220fcf5ef2aSThomas Huth #endif 221fcf5ef2aSThomas Huth 222fcf5ef2aSThomas Huth struct opc_handler_t { 223fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 224fcf5ef2aSThomas Huth uint32_t inval1; 225fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 226fcf5ef2aSThomas Huth uint32_t inval2; 227fcf5ef2aSThomas Huth /* instruction type */ 228fcf5ef2aSThomas Huth uint64_t type; 229fcf5ef2aSThomas Huth /* extended instruction type */ 230fcf5ef2aSThomas Huth uint64_t type2; 231fcf5ef2aSThomas Huth /* handler */ 232fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 233fcf5ef2aSThomas Huth }; 234fcf5ef2aSThomas Huth 235b769d4c8SNicholas Piggin static inline bool gen_serialize(DisasContext *ctx) 236b769d4c8SNicholas Piggin { 237b769d4c8SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 238b769d4c8SNicholas Piggin /* Restart with exclusive lock. */ 239b769d4c8SNicholas Piggin gen_helper_exit_atomic(cpu_env); 240b769d4c8SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 241b769d4c8SNicholas Piggin return false; 242b769d4c8SNicholas Piggin } 243b769d4c8SNicholas Piggin return true; 244b769d4c8SNicholas Piggin } 245b769d4c8SNicholas Piggin 246b769d4c8SNicholas Piggin #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2473401ea3cSNicholas Piggin static inline bool gen_serialize_core_lpar(DisasContext *ctx) 248b769d4c8SNicholas Piggin { 2493401ea3cSNicholas Piggin if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 250b769d4c8SNicholas Piggin return gen_serialize(ctx); 251b769d4c8SNicholas Piggin } 252b769d4c8SNicholas Piggin 253b769d4c8SNicholas Piggin return true; 254b769d4c8SNicholas Piggin } 255b769d4c8SNicholas Piggin #endif 256b769d4c8SNicholas Piggin 2570e3bf489SRoman Kapl /* SPR load/store helpers */ 2580e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2590e3bf489SRoman Kapl { 2600e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2610e3bf489SRoman Kapl } 2620e3bf489SRoman Kapl 2630e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2640e3bf489SRoman Kapl { 2650e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2660e3bf489SRoman Kapl } 2670e3bf489SRoman Kapl 268fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 269fcf5ef2aSThomas Huth { 270fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 271fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 272fcf5ef2aSThomas Huth ctx->access_type = access_type; 273fcf5ef2aSThomas Huth } 274fcf5ef2aSThomas Huth } 275fcf5ef2aSThomas Huth 276fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 277fcf5ef2aSThomas Huth { 278fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 279fcf5ef2aSThomas Huth nip = (uint32_t)nip; 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 282fcf5ef2aSThomas Huth } 283fcf5ef2aSThomas Huth 284fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 285fcf5ef2aSThomas Huth { 286fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 287fcf5ef2aSThomas Huth 288efe843d8SDavid Gibson /* 289efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 290efe843d8SDavid Gibson * faulting instruction 291fcf5ef2aSThomas Huth */ 2922c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2937058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 2947058ff52SRichard Henderson t1 = tcg_constant_i32(error); 295fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 2963d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 297fcf5ef2aSThomas Huth } 298fcf5ef2aSThomas Huth 299fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 300fcf5ef2aSThomas Huth { 301fcf5ef2aSThomas Huth TCGv_i32 t0; 302fcf5ef2aSThomas Huth 303efe843d8SDavid Gibson /* 304efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 305efe843d8SDavid Gibson * faulting instruction 306fcf5ef2aSThomas Huth */ 3072c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 3087058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 309fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3103d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 311fcf5ef2aSThomas Huth } 312fcf5ef2aSThomas Huth 313fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 314fcf5ef2aSThomas Huth target_ulong nip) 315fcf5ef2aSThomas Huth { 316fcf5ef2aSThomas Huth TCGv_i32 t0; 317fcf5ef2aSThomas Huth 318fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 3197058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 320fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3213d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 322fcf5ef2aSThomas Huth } 323fcf5ef2aSThomas Huth 3242fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3252fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3262fdedcbcSMatheus Ferst { 327283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 3282fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3292fdedcbcSMatheus Ferst } 3302fdedcbcSMatheus Ferst #endif 3312fdedcbcSMatheus Ferst 332e150ac89SRoman Kapl /* 333e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 334e150ac89SRoman Kapl * SPR registers for this exception. 335e150ac89SRoman Kapl * 336e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 337e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3380e3bf489SRoman Kapl */ 339e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3400e3bf489SRoman Kapl { 3410e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3420e3bf489SRoman Kapl target_ulong dbsr = 0; 343e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3440e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 345e150ac89SRoman Kapl } else { 346e150ac89SRoman Kapl /* Must have been branch */ 3470e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3480e3bf489SRoman Kapl } 3490e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3500e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3510e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3520e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3530e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3540e3bf489SRoman Kapl } else { 355e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3560e3bf489SRoman Kapl } 3570e3bf489SRoman Kapl } 3580e3bf489SRoman Kapl 359fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 360fcf5ef2aSThomas Huth { 3619498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3623d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 363fcf5ef2aSThomas Huth } 364fcf5ef2aSThomas Huth 365fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 366fcf5ef2aSThomas Huth { 367fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 368fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 369fcf5ef2aSThomas Huth } 370fcf5ef2aSThomas Huth 371fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 372fcf5ef2aSThomas Huth { 373fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 374fcf5ef2aSThomas Huth } 375fcf5ef2aSThomas Huth 376fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 377fcf5ef2aSThomas Huth { 378fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 379fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 380fcf5ef2aSThomas Huth } 381fcf5ef2aSThomas Huth 38237f219c8SBruno Larsen (billionai) /*****************************************************************************/ 38337f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 38437f219c8SBruno Larsen (billionai) 385a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 38637f219c8SBruno Larsen (billionai) { 38737f219c8SBruno Larsen (billionai) #if 0 38837f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 38937f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 39037f219c8SBruno Larsen (billionai) #endif 39137f219c8SBruno Larsen (billionai) } 39237f219c8SBruno Larsen (billionai) 39337f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 39437f219c8SBruno Larsen (billionai) 39537f219c8SBruno Larsen (billionai) /* 39637f219c8SBruno Larsen (billionai) * Generic callbacks: 39737f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 39837f219c8SBruno Larsen (billionai) */ 39937f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 40037f219c8SBruno Larsen (billionai) { 40137f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4027058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 40337f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 40437f219c8SBruno Larsen (billionai) #endif 40537f219c8SBruno Larsen (billionai) } 40637f219c8SBruno Larsen (billionai) 407a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 40837f219c8SBruno Larsen (billionai) { 40937f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 41037f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 41137f219c8SBruno Larsen (billionai) } 41237f219c8SBruno Larsen (billionai) 41337f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 41437f219c8SBruno Larsen (billionai) { 41537f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4167058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 41737f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 41837f219c8SBruno Larsen (billionai) #endif 41937f219c8SBruno Larsen (billionai) } 42037f219c8SBruno Larsen (billionai) 421a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 42237f219c8SBruno Larsen (billionai) { 42337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 42437f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42537f219c8SBruno Larsen (billionai) } 42637f219c8SBruno Larsen (billionai) 427a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 42837f219c8SBruno Larsen (billionai) { 42937f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43137f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43437f219c8SBruno Larsen (billionai) #else 43537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43637f219c8SBruno Larsen (billionai) #endif 43737f219c8SBruno Larsen (billionai) } 43837f219c8SBruno Larsen (billionai) 4399cdfd1b9SNicholas Piggin void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 4409cdfd1b9SNicholas Piggin { 4419cdfd1b9SNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT)) { 4429cdfd1b9SNicholas Piggin spr_write_generic(ctx, sprn, gprn); 4439cdfd1b9SNicholas Piggin return; 4449cdfd1b9SNicholas Piggin } 4459cdfd1b9SNicholas Piggin 4469cdfd1b9SNicholas Piggin if (!gen_serialize(ctx)) { 4479cdfd1b9SNicholas Piggin return; 4489cdfd1b9SNicholas Piggin } 4499cdfd1b9SNicholas Piggin 4509cdfd1b9SNicholas Piggin gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn), 4519cdfd1b9SNicholas Piggin cpu_gpr[gprn]); 4529cdfd1b9SNicholas Piggin spr_store_dump_spr(sprn); 4539cdfd1b9SNicholas Piggin } 4549cdfd1b9SNicholas Piggin 455c5d98a7bSNicholas Piggin static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 456fbda88f7SNicholas Piggin { 457488aad11SNicholas Piggin /* This does not implement >1 thread */ 458488aad11SNicholas Piggin TCGv t0 = tcg_temp_new(); 459488aad11SNicholas Piggin TCGv t1 = tcg_temp_new(); 460488aad11SNicholas Piggin tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 461488aad11SNicholas Piggin tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 462488aad11SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 463488aad11SNicholas Piggin gen_store_spr(sprn, t1); 464c5d98a7bSNicholas Piggin } 465c5d98a7bSNicholas Piggin 466c5d98a7bSNicholas Piggin void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 467c5d98a7bSNicholas Piggin { 4683401ea3cSNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 4693401ea3cSNicholas Piggin /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 470c5d98a7bSNicholas Piggin spr_write_CTRL_ST(ctx, sprn, gprn); 471c5d98a7bSNicholas Piggin goto out; 472c5d98a7bSNicholas Piggin } 473c5d98a7bSNicholas Piggin 474c5d98a7bSNicholas Piggin if (!gen_serialize(ctx)) { 475c5d98a7bSNicholas Piggin return; 476c5d98a7bSNicholas Piggin } 477c5d98a7bSNicholas Piggin 478c5d98a7bSNicholas Piggin gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 479c5d98a7bSNicholas Piggin cpu_gpr[gprn]); 480c5d98a7bSNicholas Piggin out: 481488aad11SNicholas Piggin spr_store_dump_spr(sprn); 482fbda88f7SNicholas Piggin 483fbda88f7SNicholas Piggin /* 484fbda88f7SNicholas Piggin * SPR_CTRL writes must force a new translation block, 485fbda88f7SNicholas Piggin * allowing the PMU to calculate the run latch events with 486fbda88f7SNicholas Piggin * more accuracy. 487fbda88f7SNicholas Piggin */ 488fbda88f7SNicholas Piggin ctx->base.is_jmp = DISAS_EXIT_UPDATE; 489fbda88f7SNicholas Piggin } 490fbda88f7SNicholas Piggin 491fbda88f7SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 492a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 49337f219c8SBruno Larsen (billionai) { 49437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 49537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 49637f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 49737f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 49837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 49937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 50037f219c8SBruno Larsen (billionai) } 50137f219c8SBruno Larsen (billionai) 502a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 50337f219c8SBruno Larsen (billionai) { 50437f219c8SBruno Larsen (billionai) } 50537f219c8SBruno Larsen (billionai) 50637f219c8SBruno Larsen (billionai) #endif 50737f219c8SBruno Larsen (billionai) 50837f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 50937f219c8SBruno Larsen (billionai) /* XER */ 510a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 51137f219c8SBruno Larsen (billionai) { 51237f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 51337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 51437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 51537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 51637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 51737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 51837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 51937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 52037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 52137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 52237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 52337f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 52437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 52537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 52637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 52737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 52837f219c8SBruno Larsen (billionai) } 52937f219c8SBruno Larsen (billionai) } 53037f219c8SBruno Larsen (billionai) 531a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 53237f219c8SBruno Larsen (billionai) { 53337f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 53437f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 53537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 53637f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 53737f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 53837f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 53937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 54037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 54137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 54237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 54337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 54437f219c8SBruno Larsen (billionai) } 54537f219c8SBruno Larsen (billionai) 54637f219c8SBruno Larsen (billionai) /* LR */ 547a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 54837f219c8SBruno Larsen (billionai) { 54937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 55037f219c8SBruno Larsen (billionai) } 55137f219c8SBruno Larsen (billionai) 552a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 55337f219c8SBruno Larsen (billionai) { 55437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 55537f219c8SBruno Larsen (billionai) } 55637f219c8SBruno Larsen (billionai) 55737f219c8SBruno Larsen (billionai) /* CFAR */ 55837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 559a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 56037f219c8SBruno Larsen (billionai) { 56137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 56237f219c8SBruno Larsen (billionai) } 56337f219c8SBruno Larsen (billionai) 564a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 56537f219c8SBruno Larsen (billionai) { 56637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 56737f219c8SBruno Larsen (billionai) } 56837f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 56937f219c8SBruno Larsen (billionai) 57037f219c8SBruno Larsen (billionai) /* CTR */ 571a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 57237f219c8SBruno Larsen (billionai) { 57337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 57437f219c8SBruno Larsen (billionai) } 57537f219c8SBruno Larsen (billionai) 576a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 57737f219c8SBruno Larsen (billionai) { 57837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 57937f219c8SBruno Larsen (billionai) } 58037f219c8SBruno Larsen (billionai) 58137f219c8SBruno Larsen (billionai) /* User read access to SPR */ 58237f219c8SBruno Larsen (billionai) /* USPRx */ 58337f219c8SBruno Larsen (billionai) /* UMMCRx */ 58437f219c8SBruno Larsen (billionai) /* UPMCx */ 58537f219c8SBruno Larsen (billionai) /* USIA */ 58637f219c8SBruno Larsen (billionai) /* UDECR */ 587a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 58837f219c8SBruno Larsen (billionai) { 58937f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 59037f219c8SBruno Larsen (billionai) } 59137f219c8SBruno Larsen (billionai) 59237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 593a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 59437f219c8SBruno Larsen (billionai) { 59537f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 59637f219c8SBruno Larsen (billionai) } 59737f219c8SBruno Larsen (billionai) #endif 59837f219c8SBruno Larsen (billionai) 59937f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 60037f219c8SBruno Larsen (billionai) /* DECR */ 60137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 602a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 60337f219c8SBruno Larsen (billionai) { 604283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 60537f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 60637f219c8SBruno Larsen (billionai) } 60737f219c8SBruno Larsen (billionai) 608a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 60937f219c8SBruno Larsen (billionai) { 610283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 61137f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 61237f219c8SBruno Larsen (billionai) } 61337f219c8SBruno Larsen (billionai) #endif 61437f219c8SBruno Larsen (billionai) 61537f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 61637f219c8SBruno Larsen (billionai) /* Time base */ 617a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 61837f219c8SBruno Larsen (billionai) { 619283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 62037f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 62137f219c8SBruno Larsen (billionai) } 62237f219c8SBruno Larsen (billionai) 623a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 62437f219c8SBruno Larsen (billionai) { 625283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 62637f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 62737f219c8SBruno Larsen (billionai) } 62837f219c8SBruno Larsen (billionai) 629a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 63037f219c8SBruno Larsen (billionai) { 63137f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 63237f219c8SBruno Larsen (billionai) } 63337f219c8SBruno Larsen (billionai) 634a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 63537f219c8SBruno Larsen (billionai) { 63637f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 63737f219c8SBruno Larsen (billionai) } 63837f219c8SBruno Larsen (billionai) 63937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 640a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 64137f219c8SBruno Larsen (billionai) { 642283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 64337f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 64437f219c8SBruno Larsen (billionai) } 64537f219c8SBruno Larsen (billionai) 646a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 64737f219c8SBruno Larsen (billionai) { 648283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 64937f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 65037f219c8SBruno Larsen (billionai) } 65137f219c8SBruno Larsen (billionai) 652a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 65337f219c8SBruno Larsen (billionai) { 65437f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) 657a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 66037f219c8SBruno Larsen (billionai) } 66137f219c8SBruno Larsen (billionai) 66237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 663a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 66437f219c8SBruno Larsen (billionai) { 665283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 66637f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 66737f219c8SBruno Larsen (billionai) } 66837f219c8SBruno Larsen (billionai) 669a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 67037f219c8SBruno Larsen (billionai) { 671283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67237f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 67337f219c8SBruno Larsen (billionai) } 67437f219c8SBruno Larsen (billionai) 67537f219c8SBruno Larsen (billionai) /* HDECR */ 676a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 67737f219c8SBruno Larsen (billionai) { 678283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67937f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 68037f219c8SBruno Larsen (billionai) } 68137f219c8SBruno Larsen (billionai) 682a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 68337f219c8SBruno Larsen (billionai) { 684283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 68537f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 68637f219c8SBruno Larsen (billionai) } 68737f219c8SBruno Larsen (billionai) 688a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 68937f219c8SBruno Larsen (billionai) { 690283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 69137f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 69237f219c8SBruno Larsen (billionai) } 69337f219c8SBruno Larsen (billionai) 694a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 69537f219c8SBruno Larsen (billionai) { 696283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 69737f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 69837f219c8SBruno Larsen (billionai) } 69937f219c8SBruno Larsen (billionai) 700a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 70137f219c8SBruno Larsen (billionai) { 702283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 70337f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 70437f219c8SBruno Larsen (billionai) } 70537f219c8SBruno Larsen (billionai) 70637f219c8SBruno Larsen (billionai) #endif 70737f219c8SBruno Larsen (billionai) #endif 70837f219c8SBruno Larsen (billionai) 70937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 71037f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 71137f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 712a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 71337f219c8SBruno Larsen (billionai) { 71437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 71537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 71637f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 71737f219c8SBruno Larsen (billionai) } 71837f219c8SBruno Larsen (billionai) 719a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 72037f219c8SBruno Larsen (billionai) { 72137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 72237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 72337f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 72437f219c8SBruno Larsen (billionai) } 72537f219c8SBruno Larsen (billionai) 726a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 72737f219c8SBruno Larsen (billionai) { 7287058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 72937f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 73037f219c8SBruno Larsen (billionai) } 73137f219c8SBruno Larsen (billionai) 732a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 73337f219c8SBruno Larsen (billionai) { 7347058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 73537f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 73637f219c8SBruno Larsen (billionai) } 73737f219c8SBruno Larsen (billionai) 738a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 73937f219c8SBruno Larsen (billionai) { 7407058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 74137f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 74237f219c8SBruno Larsen (billionai) } 74337f219c8SBruno Larsen (billionai) 744a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 74537f219c8SBruno Larsen (billionai) { 7467058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 74737f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 74837f219c8SBruno Larsen (billionai) } 74937f219c8SBruno Larsen (billionai) 75037f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 75137f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 752a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 75337f219c8SBruno Larsen (billionai) { 75437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 75537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 75637f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 75737f219c8SBruno Larsen (billionai) } 75837f219c8SBruno Larsen (billionai) 759a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 76037f219c8SBruno Larsen (billionai) { 76137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 76237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 76337f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 76437f219c8SBruno Larsen (billionai) } 76537f219c8SBruno Larsen (billionai) 766a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 76737f219c8SBruno Larsen (billionai) { 7687058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 76937f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 772a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 77337f219c8SBruno Larsen (billionai) { 7747058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 77537f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 77637f219c8SBruno Larsen (billionai) } 77737f219c8SBruno Larsen (billionai) 778a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 77937f219c8SBruno Larsen (billionai) { 7807058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 78137f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 78237f219c8SBruno Larsen (billionai) } 78337f219c8SBruno Larsen (billionai) 784a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 78537f219c8SBruno Larsen (billionai) { 7867058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 78737f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 79037f219c8SBruno Larsen (billionai) /* SDR1 */ 791a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 79237f219c8SBruno Larsen (billionai) { 79337f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 79437f219c8SBruno Larsen (billionai) } 79537f219c8SBruno Larsen (billionai) 79637f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 79737f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 79837f219c8SBruno Larsen (billionai) /* PIDR */ 799a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 80037f219c8SBruno Larsen (billionai) { 80137f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 80237f219c8SBruno Larsen (billionai) } 80337f219c8SBruno Larsen (billionai) 804a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 80537f219c8SBruno Larsen (billionai) { 80637f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 80737f219c8SBruno Larsen (billionai) } 80837f219c8SBruno Larsen (billionai) 809a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 81037f219c8SBruno Larsen (billionai) { 81137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 81237f219c8SBruno Larsen (billionai) } 81337f219c8SBruno Larsen (billionai) 814a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 81537f219c8SBruno Larsen (billionai) { 81637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 81737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 81837f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 81937f219c8SBruno Larsen (billionai) } 820a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 82137f219c8SBruno Larsen (billionai) { 82237f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 82337f219c8SBruno Larsen (billionai) } 82437f219c8SBruno Larsen (billionai) 825a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 82637f219c8SBruno Larsen (billionai) { 82737f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 82837f219c8SBruno Larsen (billionai) } 82937f219c8SBruno Larsen (billionai) 83037f219c8SBruno Larsen (billionai) /* DPDES */ 831a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 83237f219c8SBruno Larsen (billionai) { 8333401ea3cSNicholas Piggin if (!gen_serialize_core_lpar(ctx)) { 834d24e80b2SNicholas Piggin return; 835d24e80b2SNicholas Piggin } 836d24e80b2SNicholas Piggin 83737f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 83837f219c8SBruno Larsen (billionai) } 83937f219c8SBruno Larsen (billionai) 840a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 84137f219c8SBruno Larsen (billionai) { 8423401ea3cSNicholas Piggin if (!gen_serialize_core_lpar(ctx)) { 843d24e80b2SNicholas Piggin return; 844d24e80b2SNicholas Piggin } 845d24e80b2SNicholas Piggin 84637f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 84737f219c8SBruno Larsen (billionai) } 84837f219c8SBruno Larsen (billionai) #endif 84937f219c8SBruno Larsen (billionai) #endif 85037f219c8SBruno Larsen (billionai) 85137f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 85237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 853a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 85437f219c8SBruno Larsen (billionai) { 855283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 85637f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 85737f219c8SBruno Larsen (billionai) } 85837f219c8SBruno Larsen (billionai) 859a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 86037f219c8SBruno Larsen (billionai) { 861283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 86237f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 86337f219c8SBruno Larsen (billionai) } 86437f219c8SBruno Larsen (billionai) 865a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 86637f219c8SBruno Larsen (billionai) { 867283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 86837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 86937f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 87037f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 871d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 87237f219c8SBruno Larsen (billionai) } 87337f219c8SBruno Larsen (billionai) 874a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 87537f219c8SBruno Larsen (billionai) { 876283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 87737f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 87837f219c8SBruno Larsen (billionai) } 87937f219c8SBruno Larsen (billionai) 880cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 881cbd8f17dSCédric Le Goater { 882283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 883cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 884cbd8f17dSCédric Le Goater } 885cbd8f17dSCédric Le Goater 886cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 887cbd8f17dSCédric Le Goater { 888283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 889cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 890cbd8f17dSCédric Le Goater } 891cbd8f17dSCédric Le Goater 892dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 893dd69d140SCédric Le Goater { 894dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 895dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 89647822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 897dd69d140SCédric Le Goater } 898dd69d140SCédric Le Goater 899a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 90037f219c8SBruno Larsen (billionai) { 901283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 90237f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 90337f219c8SBruno Larsen (billionai) } 90437f219c8SBruno Larsen (billionai) 905a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 90637f219c8SBruno Larsen (billionai) { 907283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 90837f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 90937f219c8SBruno Larsen (billionai) } 91037f219c8SBruno Larsen (billionai) #endif 91137f219c8SBruno Larsen (billionai) 912328c95fcSCédric Le Goater /* PIR */ 91337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 914a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 91537f219c8SBruno Larsen (billionai) { 91637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 91737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 91837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 91937f219c8SBruno Larsen (billionai) } 92037f219c8SBruno Larsen (billionai) #endif 92137f219c8SBruno Larsen (billionai) 92237f219c8SBruno Larsen (billionai) /* SPE specific registers */ 923a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 92437f219c8SBruno Larsen (billionai) { 92537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 92637f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92737f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 92837f219c8SBruno Larsen (billionai) } 92937f219c8SBruno Larsen (billionai) 930a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 93137f219c8SBruno Larsen (billionai) { 93237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 93337f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 93437f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 93537f219c8SBruno Larsen (billionai) } 93637f219c8SBruno Larsen (billionai) 93737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 93837f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 939a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 94037f219c8SBruno Larsen (billionai) { 94137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 94237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 94337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 94437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 94537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 94637f219c8SBruno Larsen (billionai) } 94737f219c8SBruno Larsen (billionai) 948a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 94937f219c8SBruno Larsen (billionai) { 95037f219c8SBruno Larsen (billionai) int sprn_offs; 95137f219c8SBruno Larsen (billionai) 95237f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 95337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 95437f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 95537f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 95637f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 95737f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 95837f219c8SBruno Larsen (billionai) } else { 9598e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9608e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9618e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 96237f219c8SBruno Larsen (billionai) return; 96337f219c8SBruno Larsen (billionai) } 96437f219c8SBruno Larsen (billionai) 96537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 96737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 96837f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 96937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 97037f219c8SBruno Larsen (billionai) } 97137f219c8SBruno Larsen (billionai) #endif 97237f219c8SBruno Larsen (billionai) 97337f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 97437f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 975a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 97637f219c8SBruno Larsen (billionai) { 97737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97837f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 97937f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 98037f219c8SBruno Larsen (billionai) 98137f219c8SBruno Larsen (billionai) /* 98237f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 98337f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 98437f219c8SBruno Larsen (billionai) */ 98537f219c8SBruno Larsen (billionai) 98637f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 98737f219c8SBruno Larsen (billionai) if (ctx->pr) { 98837f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 98937f219c8SBruno Larsen (billionai) } else { 99037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 99137f219c8SBruno Larsen (billionai) } 99237f219c8SBruno Larsen (billionai) 99337f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 99437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 99537f219c8SBruno Larsen (billionai) 99637f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 99737f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 99837f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 99937f219c8SBruno Larsen (billionai) 100037f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 100137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 100237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 100337f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 100437f219c8SBruno Larsen (billionai) } 100537f219c8SBruno Larsen (billionai) 1006a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 100737f219c8SBruno Larsen (billionai) { 100837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 101037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 101137f219c8SBruno Larsen (billionai) 101237f219c8SBruno Larsen (billionai) /* 101337f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 101437f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 101537f219c8SBruno Larsen (billionai) */ 101637f219c8SBruno Larsen (billionai) 101737f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 101837f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101937f219c8SBruno Larsen (billionai) 102037f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 102137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 102237f219c8SBruno Larsen (billionai) 102337f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 102437f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 102537f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 102637f219c8SBruno Larsen (billionai) 102737f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 102837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 103037f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 103137f219c8SBruno Larsen (billionai) } 103237f219c8SBruno Larsen (billionai) 1033a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 103437f219c8SBruno Larsen (billionai) { 103537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103837f219c8SBruno Larsen (billionai) 103937f219c8SBruno Larsen (billionai) /* 104037f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 104137f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 104237f219c8SBruno Larsen (billionai) */ 104337f219c8SBruno Larsen (billionai) 104437f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104637f219c8SBruno Larsen (billionai) 104737f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 104937f219c8SBruno Larsen (billionai) 105037f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 105137f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 105237f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 105337f219c8SBruno Larsen (billionai) 105437f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 105737f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 105837f219c8SBruno Larsen (billionai) } 105937f219c8SBruno Larsen (billionai) #endif 106037f219c8SBruno Larsen (billionai) #endif 106137f219c8SBruno Larsen (billionai) 106237f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1063a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 106437f219c8SBruno Larsen (billionai) { 106537f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 106637f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 106737f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 106837f219c8SBruno Larsen (billionai) } 106937f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 107037f219c8SBruno Larsen (billionai) 107137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1072a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 107337f219c8SBruno Larsen (billionai) { 107437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107537f219c8SBruno Larsen (billionai) 107637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 107737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107837f219c8SBruno Larsen (billionai) } 107937f219c8SBruno Larsen (billionai) 1080a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 108137f219c8SBruno Larsen (billionai) { 108237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108337f219c8SBruno Larsen (billionai) 108437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 108537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108637f219c8SBruno Larsen (billionai) } 108737f219c8SBruno Larsen (billionai) 1088a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 108937f219c8SBruno Larsen (billionai) { 109037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109137f219c8SBruno Larsen (billionai) 109237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 109337f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 109437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109537f219c8SBruno Larsen (billionai) } 109637f219c8SBruno Larsen (billionai) 1097a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 109837f219c8SBruno Larsen (billionai) { 109937f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 110037f219c8SBruno Larsen (billionai) } 110137f219c8SBruno Larsen (billionai) 1102a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 110337f219c8SBruno Larsen (billionai) { 11047058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 110537f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 110637f219c8SBruno Larsen (billionai) } 11077058ff52SRichard Henderson 1108a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 110937f219c8SBruno Larsen (billionai) { 111037f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 111137f219c8SBruno Larsen (billionai) } 11127058ff52SRichard Henderson 1113a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 111437f219c8SBruno Larsen (billionai) { 111537f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 111637f219c8SBruno Larsen (billionai) } 111737f219c8SBruno Larsen (billionai) 111837f219c8SBruno Larsen (billionai) #endif 111937f219c8SBruno Larsen (billionai) 112037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1121a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 112237f219c8SBruno Larsen (billionai) { 112337f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 112437f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 112537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 112637f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 112737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 112837f219c8SBruno Larsen (billionai) } 112937f219c8SBruno Larsen (billionai) 1130a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 113137f219c8SBruno Larsen (billionai) { 113237f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 113337f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 113437f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 113537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 113637f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 113737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 113837f219c8SBruno Larsen (billionai) } 113937f219c8SBruno Larsen (billionai) 114037f219c8SBruno Larsen (billionai) #endif 114137f219c8SBruno Larsen (billionai) 114237f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 114337f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 114437f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114537f219c8SBruno Larsen (billionai) { 11467058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11477058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11487058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 114937f219c8SBruno Larsen (billionai) 115037f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 115137f219c8SBruno Larsen (billionai) } 115237f219c8SBruno Larsen (billionai) 115337f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 115437f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 115537f219c8SBruno Larsen (billionai) { 11567058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11577058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11587058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 115937f219c8SBruno Larsen (billionai) 116037f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 116137f219c8SBruno Larsen (billionai) } 116237f219c8SBruno Larsen (billionai) 1163a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 116437f219c8SBruno Larsen (billionai) { 116537f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 116637f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 116937f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 117037f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 117137f219c8SBruno Larsen (billionai) } 117237f219c8SBruno Larsen (billionai) 1173a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 117437f219c8SBruno Larsen (billionai) { 117537f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 117637f219c8SBruno Larsen (billionai) 117737f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 117837f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 117937f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 118037f219c8SBruno Larsen (billionai) } 118137f219c8SBruno Larsen (billionai) 118237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1183a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 118437f219c8SBruno Larsen (billionai) { 118537f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 118637f219c8SBruno Larsen (billionai) 118737f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 118837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 118937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 119037f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 119137f219c8SBruno Larsen (billionai) } 119237f219c8SBruno Larsen (billionai) 1193b25f2ffaSNicholas Piggin void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1194b25f2ffaSNicholas Piggin { 1195b25f2ffaSNicholas Piggin gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1196b25f2ffaSNicholas Piggin } 1197b25f2ffaSNicholas Piggin 1198b25f2ffaSNicholas Piggin void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1199b25f2ffaSNicholas Piggin { 1200b25f2ffaSNicholas Piggin gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1201b25f2ffaSNicholas Piggin } 1202b25f2ffaSNicholas Piggin 1203a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 120437f219c8SBruno Larsen (billionai) { 1205c32654afSNicholas Piggin translator_io_start(&ctx->base); 120637f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 120737f219c8SBruno Larsen (billionai) } 120837f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 120937f219c8SBruno Larsen (billionai) 1210a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 121137f219c8SBruno Larsen (billionai) { 121237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 121337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 121437f219c8SBruno Larsen (billionai) } 121537f219c8SBruno Larsen (billionai) 1216a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 121737f219c8SBruno Larsen (billionai) { 121837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 121937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 122037f219c8SBruno Larsen (billionai) } 122137f219c8SBruno Larsen (billionai) 1222a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 122337f219c8SBruno Larsen (billionai) { 122437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122537f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122637f219c8SBruno Larsen (billionai) } 122737f219c8SBruno Larsen (billionai) 1228a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 122937f219c8SBruno Larsen (billionai) { 123037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123137f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123237f219c8SBruno Larsen (billionai) } 123337f219c8SBruno Larsen (billionai) 1234a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 123537f219c8SBruno Larsen (billionai) { 123637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123737f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 123837f219c8SBruno Larsen (billionai) } 123937f219c8SBruno Larsen (billionai) 1240a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 124137f219c8SBruno Larsen (billionai) { 124237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124337f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 124437f219c8SBruno Larsen (billionai) } 124537f219c8SBruno Larsen (billionai) 1246a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 124737f219c8SBruno Larsen (billionai) { 124837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124937f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125037f219c8SBruno Larsen (billionai) } 125137f219c8SBruno Larsen (billionai) 1252a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 125337f219c8SBruno Larsen (billionai) { 125437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 125637f219c8SBruno Larsen (billionai) } 125737f219c8SBruno Larsen (billionai) 1258a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 125937f219c8SBruno Larsen (billionai) { 126037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126137f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 126237f219c8SBruno Larsen (billionai) } 126337f219c8SBruno Larsen (billionai) 1264a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 126537f219c8SBruno Larsen (billionai) { 126637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126737f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 126837f219c8SBruno Larsen (billionai) } 1269395b5d5bSNicholas Miehlbradt 1270395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1271395b5d5bSNicholas Miehlbradt { 1272395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1273395b5d5bSNicholas Miehlbradt 1274395b5d5bSNicholas Miehlbradt /* 1275395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1276395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1277395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1278395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1279395b5d5bSNicholas Miehlbradt * 1280395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1281395b5d5bSNicholas Miehlbradt */ 1282395b5d5bSNicholas Miehlbradt 1283395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1284395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1285395b5d5bSNicholas Miehlbradt } 128637f219c8SBruno Larsen (billionai) #endif 128737f219c8SBruno Larsen (billionai) 1288fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1289fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1290fcf5ef2aSThomas Huth 1291fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1292fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1293fcf5ef2aSThomas Huth 1294fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1295fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1296fcf5ef2aSThomas Huth 1297fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1298fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1299fcf5ef2aSThomas Huth 1300fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1301fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1302fcf5ef2aSThomas Huth 1303fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1304fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1305fcf5ef2aSThomas Huth 1306fcf5ef2aSThomas Huth typedef struct opcode_t { 1307fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1308fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1309fcf5ef2aSThomas Huth unsigned char pad[4]; 1310fcf5ef2aSThomas Huth #endif 1311fcf5ef2aSThomas Huth opc_handler_t handler; 1312fcf5ef2aSThomas Huth const char *oname; 1313fcf5ef2aSThomas Huth } opcode_t; 1314fcf5ef2aSThomas Huth 13159f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 13169f0cf041SMatheus Ferst { 13179f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 13189f0cf041SMatheus Ferst } 13199f0cf041SMatheus Ferst 1320fcf5ef2aSThomas Huth /* Helpers for priv. check */ 13219f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1322fcf5ef2aSThomas Huth do { \ 13239f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1324fcf5ef2aSThomas Huth } while (0) 1325fcf5ef2aSThomas Huth 1326fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 13279f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 13289f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 13299f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1330fcf5ef2aSThomas Huth #else 13319f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1332fcf5ef2aSThomas Huth do { \ 1333fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 13349f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1335fcf5ef2aSThomas Huth } \ 1336fcf5ef2aSThomas Huth } while (0) 13379f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1338fcf5ef2aSThomas Huth do { \ 1339fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13409f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1341fcf5ef2aSThomas Huth } \ 1342fcf5ef2aSThomas Huth } while (0) 13439f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1344fcf5ef2aSThomas Huth do { \ 1345fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13469f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1347fcf5ef2aSThomas Huth } \ 1348fcf5ef2aSThomas Huth } while (0) 1349fcf5ef2aSThomas Huth #endif 1350fcf5ef2aSThomas Huth 13519f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1352fcf5ef2aSThomas Huth 1353fcf5ef2aSThomas Huth /*****************************************************************************/ 1354fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1355fcf5ef2aSThomas Huth 1356fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1357fcf5ef2aSThomas Huth { \ 1358fcf5ef2aSThomas Huth .opc1 = op1, \ 1359fcf5ef2aSThomas Huth .opc2 = op2, \ 1360fcf5ef2aSThomas Huth .opc3 = op3, \ 1361fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1362fcf5ef2aSThomas Huth .handler = { \ 1363fcf5ef2aSThomas Huth .inval1 = invl, \ 1364fcf5ef2aSThomas Huth .type = _typ, \ 1365fcf5ef2aSThomas Huth .type2 = _typ2, \ 1366fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1367fcf5ef2aSThomas Huth }, \ 1368fcf5ef2aSThomas Huth .oname = stringify(name), \ 1369fcf5ef2aSThomas Huth } 1370fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1371fcf5ef2aSThomas Huth { \ 1372fcf5ef2aSThomas Huth .opc1 = op1, \ 1373fcf5ef2aSThomas Huth .opc2 = op2, \ 1374fcf5ef2aSThomas Huth .opc3 = op3, \ 1375fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1376fcf5ef2aSThomas Huth .handler = { \ 1377fcf5ef2aSThomas Huth .inval1 = invl1, \ 1378fcf5ef2aSThomas Huth .inval2 = invl2, \ 1379fcf5ef2aSThomas Huth .type = _typ, \ 1380fcf5ef2aSThomas Huth .type2 = _typ2, \ 1381fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1382fcf5ef2aSThomas Huth }, \ 1383fcf5ef2aSThomas Huth .oname = stringify(name), \ 1384fcf5ef2aSThomas Huth } 1385fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1386fcf5ef2aSThomas Huth { \ 1387fcf5ef2aSThomas Huth .opc1 = op1, \ 1388fcf5ef2aSThomas Huth .opc2 = op2, \ 1389fcf5ef2aSThomas Huth .opc3 = op3, \ 1390fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1391fcf5ef2aSThomas Huth .handler = { \ 1392fcf5ef2aSThomas Huth .inval1 = invl, \ 1393fcf5ef2aSThomas Huth .type = _typ, \ 1394fcf5ef2aSThomas Huth .type2 = _typ2, \ 1395fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1396fcf5ef2aSThomas Huth }, \ 1397fcf5ef2aSThomas Huth .oname = onam, \ 1398fcf5ef2aSThomas Huth } 1399fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1400fcf5ef2aSThomas Huth { \ 1401fcf5ef2aSThomas Huth .opc1 = op1, \ 1402fcf5ef2aSThomas Huth .opc2 = op2, \ 1403fcf5ef2aSThomas Huth .opc3 = op3, \ 1404fcf5ef2aSThomas Huth .opc4 = op4, \ 1405fcf5ef2aSThomas Huth .handler = { \ 1406fcf5ef2aSThomas Huth .inval1 = invl, \ 1407fcf5ef2aSThomas Huth .type = _typ, \ 1408fcf5ef2aSThomas Huth .type2 = _typ2, \ 1409fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1410fcf5ef2aSThomas Huth }, \ 1411fcf5ef2aSThomas Huth .oname = stringify(name), \ 1412fcf5ef2aSThomas Huth } 1413fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1414fcf5ef2aSThomas Huth { \ 1415fcf5ef2aSThomas Huth .opc1 = op1, \ 1416fcf5ef2aSThomas Huth .opc2 = op2, \ 1417fcf5ef2aSThomas Huth .opc3 = op3, \ 1418fcf5ef2aSThomas Huth .opc4 = op4, \ 1419fcf5ef2aSThomas Huth .handler = { \ 1420fcf5ef2aSThomas Huth .inval1 = invl, \ 1421fcf5ef2aSThomas Huth .type = _typ, \ 1422fcf5ef2aSThomas Huth .type2 = _typ2, \ 1423fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1424fcf5ef2aSThomas Huth }, \ 1425fcf5ef2aSThomas Huth .oname = onam, \ 1426fcf5ef2aSThomas Huth } 1427fcf5ef2aSThomas Huth 1428fcf5ef2aSThomas Huth /* Invalid instruction */ 1429fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1430fcf5ef2aSThomas Huth { 1431fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1432fcf5ef2aSThomas Huth } 1433fcf5ef2aSThomas Huth 1434fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1435fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1436fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1437fcf5ef2aSThomas Huth .type = PPC_NONE, 1438fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1439fcf5ef2aSThomas Huth .handler = gen_invalid, 1440fcf5ef2aSThomas Huth }; 1441fcf5ef2aSThomas Huth 1442fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1443fcf5ef2aSThomas Huth 1444fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1445fcf5ef2aSThomas Huth { 1446fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1447b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1448b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1449fcf5ef2aSThomas Huth 1450b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1451b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1452efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1453efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1454b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1455efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1456efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1457b62b3686Spbonzini@redhat.com 1458b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1459fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1460b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1461fcf5ef2aSThomas Huth } 1462fcf5ef2aSThomas Huth 1463fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1464fcf5ef2aSThomas Huth { 14657058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1466fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1467fcf5ef2aSThomas Huth } 1468fcf5ef2aSThomas Huth 1469fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1470fcf5ef2aSThomas Huth { 1471fcf5ef2aSThomas Huth TCGv t0, t1; 1472fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1473fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1474fcf5ef2aSThomas Huth if (s) { 1475fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1476fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1477fcf5ef2aSThomas Huth } else { 1478fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1479fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1480fcf5ef2aSThomas Huth } 1481fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1482fcf5ef2aSThomas Huth } 1483fcf5ef2aSThomas Huth 1484fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1485fcf5ef2aSThomas Huth { 14867058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1487fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1488fcf5ef2aSThomas Huth } 1489fcf5ef2aSThomas Huth 1490fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1491fcf5ef2aSThomas Huth { 1492fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1493fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1494fcf5ef2aSThomas Huth } else { 1495fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1496fcf5ef2aSThomas Huth } 1497fcf5ef2aSThomas Huth } 1498fcf5ef2aSThomas Huth 1499fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1500fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1501fcf5ef2aSThomas Huth { 1502fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1503fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1504fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1505fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1506fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1507fcf5ef2aSThomas Huth 1508fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1509fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1510fcf5ef2aSThomas Huth 1511fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1512fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1513fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1514fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1515fcf5ef2aSThomas Huth 1516fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1517fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1518fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1519fcf5ef2aSThomas Huth 1520fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1521fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1522fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1523fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1524fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1525fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1526fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1527fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1528fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1529fcf5ef2aSThomas Huth } 1530efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1531fcf5ef2aSThomas Huth } 1532fcf5ef2aSThomas Huth 1533fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1534fcf5ef2aSThomas Huth /* cmpeqb */ 1535fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1536fcf5ef2aSThomas Huth { 1537fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1538fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1539fcf5ef2aSThomas Huth } 1540fcf5ef2aSThomas Huth #endif 1541fcf5ef2aSThomas Huth 1542fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1543fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1544fcf5ef2aSThomas Huth { 1545fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1546fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1547fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1548fcf5ef2aSThomas Huth TCGv zr; 1549fcf5ef2aSThomas Huth 1550fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1551fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1552fcf5ef2aSThomas Huth 15537058ff52SRichard Henderson zr = tcg_constant_tl(0); 1554fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1555fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1556fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1557fcf5ef2aSThomas Huth } 1558fcf5ef2aSThomas Huth 1559fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1560fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1561fcf5ef2aSThomas Huth { 1562fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1563fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1564fcf5ef2aSThomas Huth } 1565fcf5ef2aSThomas Huth 1566fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1567fcf5ef2aSThomas Huth 1568fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1569fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1570fcf5ef2aSThomas Huth { 1571fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1572fcf5ef2aSThomas Huth 1573fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1574fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1575fcf5ef2aSThomas Huth if (sub) { 1576fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1577fcf5ef2aSThomas Huth } else { 1578fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1579fcf5ef2aSThomas Huth } 1580fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1581dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1582dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1583dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1584fcf5ef2aSThomas Huth } 1585dc0ad844SNikunj A Dadhania } else { 1586dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1587dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1588dc0ad844SNikunj A Dadhania } 158938a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1590dc0ad844SNikunj A Dadhania } 1591fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1592fcf5ef2aSThomas Huth } 1593fcf5ef2aSThomas Huth 15946b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15956b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15964c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15976b10d008SNikunj A Dadhania { 15986b10d008SNikunj A Dadhania TCGv t0; 15996b10d008SNikunj A Dadhania 16006b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16016b10d008SNikunj A Dadhania return; 16026b10d008SNikunj A Dadhania } 16036b10d008SNikunj A Dadhania 16046b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 160533903d0aSNikunj A Dadhania if (sub) { 160633903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 160733903d0aSNikunj A Dadhania } else { 16086b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 160933903d0aSNikunj A Dadhania } 16106b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16114c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16126b10d008SNikunj A Dadhania } 16136b10d008SNikunj A Dadhania 1614fcf5ef2aSThomas Huth /* Common add function */ 1615fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16164c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16174c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1618fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1619fcf5ef2aSThomas Huth { 1620fcf5ef2aSThomas Huth TCGv t0 = ret; 1621fcf5ef2aSThomas Huth 1622fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1623fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1624fcf5ef2aSThomas Huth } 1625fcf5ef2aSThomas Huth 1626fcf5ef2aSThomas Huth if (compute_ca) { 1627fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1628efe843d8SDavid Gibson /* 1629efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1630efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1631efe843d8SDavid Gibson * produce the carry into bit 32. 1632efe843d8SDavid Gibson */ 1633fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1634fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1635fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1636fcf5ef2aSThomas Huth if (add_ca) { 16374c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1638fcf5ef2aSThomas Huth } 16394c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 16404c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16416b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16424c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16436b10d008SNikunj A Dadhania } 1644fcf5ef2aSThomas Huth } else { 16457058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 1646fcf5ef2aSThomas Huth if (add_ca) { 16474c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16484c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1649fcf5ef2aSThomas Huth } else { 16504c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1651fcf5ef2aSThomas Huth } 16524c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1653fcf5ef2aSThomas Huth } 1654fcf5ef2aSThomas Huth } else { 1655fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1656fcf5ef2aSThomas Huth if (add_ca) { 16574c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1658fcf5ef2aSThomas Huth } 1659fcf5ef2aSThomas Huth } 1660fcf5ef2aSThomas Huth 1661fcf5ef2aSThomas Huth if (compute_ov) { 1662fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1663fcf5ef2aSThomas Huth } 1664fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1665fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth 166811f4e8f8SRichard Henderson if (t0 != ret) { 1669fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth } 1672fcf5ef2aSThomas Huth /* Add functions with two operands */ 16734c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1674fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1675fcf5ef2aSThomas Huth { \ 1676fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1677fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16784c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1679fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1680fcf5ef2aSThomas Huth } 1681fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16824c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1683fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1684fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1685fcf5ef2aSThomas Huth { \ 16867058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 1687fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1688fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16894c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1690fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1691fcf5ef2aSThomas Huth } 1692fcf5ef2aSThomas Huth 1693fcf5ef2aSThomas Huth /* add add. addo addo. */ 16944c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16954c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1696fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16974c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16984c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1699fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17004c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17014c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1702fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17034c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17044c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17054c5920afSSuraj Jitindar Singh /* addex */ 17064c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1707fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17084c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17094c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1710fcf5ef2aSThomas Huth /* addic addic.*/ 1711fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1712fcf5ef2aSThomas Huth { 17137058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1714fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17154c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1716fcf5ef2aSThomas Huth } 1717fcf5ef2aSThomas Huth 1718fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1719fcf5ef2aSThomas Huth { 1720fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1721fcf5ef2aSThomas Huth } 1722fcf5ef2aSThomas Huth 1723fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1724fcf5ef2aSThomas Huth { 1725fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1726fcf5ef2aSThomas Huth } 1727fcf5ef2aSThomas Huth 1728fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1729fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1730fcf5ef2aSThomas Huth { 1731fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1732fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1733fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1734fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1735fcf5ef2aSThomas Huth 1736fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1737fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1738fcf5ef2aSThomas Huth if (sign) { 1739fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1740fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1741fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1742fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1743fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1744fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1745fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1746fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1747fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1748fcf5ef2aSThomas Huth } else { 1749fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1750fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1751fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1752fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1753fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1754fcf5ef2aSThomas Huth } 1755fcf5ef2aSThomas Huth if (compute_ov) { 1756fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1757c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1758c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1759c44027ffSNikunj A Dadhania } 1760fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1761fcf5ef2aSThomas Huth } 1762fcf5ef2aSThomas Huth 1763efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1764fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1765fcf5ef2aSThomas Huth } 1766efe843d8SDavid Gibson } 1767fcf5ef2aSThomas Huth /* Div functions */ 1768fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1769fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1770fcf5ef2aSThomas Huth { \ 1771fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1772fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1773fcf5ef2aSThomas Huth sign, compute_ov); \ 1774fcf5ef2aSThomas Huth } 1775fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1776fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1777fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1778fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1779fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1780fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1781fcf5ef2aSThomas Huth 1782fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1783fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1784fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1785fcf5ef2aSThomas Huth { \ 17867058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1787fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1788fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1789fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1790fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1791fcf5ef2aSThomas Huth } \ 1792fcf5ef2aSThomas Huth } 1793fcf5ef2aSThomas Huth 1794fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1795fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1796fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1797fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1798fcf5ef2aSThomas Huth 1799fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1800fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1801fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1802fcf5ef2aSThomas Huth { 1803fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1804fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1805fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1806fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1807fcf5ef2aSThomas Huth 1808fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1809fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1810fcf5ef2aSThomas Huth if (sign) { 1811fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1812fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1813fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1814fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1815fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1816fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1817fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1818fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1819fcf5ef2aSThomas Huth } else { 1820fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1821fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1822fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1823fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1824fcf5ef2aSThomas Huth } 1825fcf5ef2aSThomas Huth if (compute_ov) { 1826fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1827c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1828c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1829c44027ffSNikunj A Dadhania } 1830fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1831fcf5ef2aSThomas Huth } 1832fcf5ef2aSThomas Huth 1833efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1834fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1835fcf5ef2aSThomas Huth } 1836efe843d8SDavid Gibson } 1837fcf5ef2aSThomas Huth 1838fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1839fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1840fcf5ef2aSThomas Huth { \ 1841fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1842fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1843fcf5ef2aSThomas Huth sign, compute_ov); \ 1844fcf5ef2aSThomas Huth } 1845c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1846fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1847fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1848c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1849fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1850fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1851fcf5ef2aSThomas Huth 1852fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1853fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1854fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1855fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1856fcf5ef2aSThomas Huth #endif 1857fcf5ef2aSThomas Huth 1858fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1859fcf5ef2aSThomas Huth TCGv arg2, int sign) 1860fcf5ef2aSThomas Huth { 1861fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1862fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1863fcf5ef2aSThomas Huth 1864fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1865fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1866fcf5ef2aSThomas Huth if (sign) { 1867fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1868fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1869fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1870fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1871fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1872fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1873fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1874fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1875fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1876fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1877fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1878fcf5ef2aSThomas Huth } else { 18797058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(1); 18807058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(0); 1881fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1882a253231fSRichard Henderson tcg_gen_remu_i32(t0, t0, t1); 1883a253231fSRichard Henderson tcg_gen_extu_i32_tl(ret, t0); 1884fcf5ef2aSThomas Huth } 1885fcf5ef2aSThomas Huth } 1886fcf5ef2aSThomas Huth 1887fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1888fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1889fcf5ef2aSThomas Huth { \ 1890fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1891fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1892fcf5ef2aSThomas Huth sign); \ 1893fcf5ef2aSThomas Huth } 1894fcf5ef2aSThomas Huth 1895fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1896fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1897fcf5ef2aSThomas Huth 1898fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1899fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1900fcf5ef2aSThomas Huth TCGv arg2, int sign) 1901fcf5ef2aSThomas Huth { 1902fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1903fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1904fcf5ef2aSThomas Huth 1905fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1906fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1907fcf5ef2aSThomas Huth if (sign) { 1908fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1909fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1910fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1911fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1912fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1913fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1914fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1915fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1916fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1917fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1918fcf5ef2aSThomas Huth } else { 19197058ff52SRichard Henderson TCGv_i64 t2 = tcg_constant_i64(1); 19207058ff52SRichard Henderson TCGv_i64 t3 = tcg_constant_i64(0); 1921fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1922fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1923fcf5ef2aSThomas Huth } 1924fcf5ef2aSThomas Huth } 1925fcf5ef2aSThomas Huth 1926fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1927fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1928fcf5ef2aSThomas Huth { \ 1929fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1930fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1931fcf5ef2aSThomas Huth sign); \ 1932fcf5ef2aSThomas Huth } 1933fcf5ef2aSThomas Huth 1934fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1935fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1936fcf5ef2aSThomas Huth #endif 1937fcf5ef2aSThomas Huth 1938fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1939fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1940fcf5ef2aSThomas Huth { 1941fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1942fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1943fcf5ef2aSThomas Huth 1944fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1945fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1946fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1947fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1948efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1949fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1950fcf5ef2aSThomas Huth } 1951efe843d8SDavid Gibson } 1952fcf5ef2aSThomas Huth 1953fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1954fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1955fcf5ef2aSThomas Huth { 1956fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1957fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1958fcf5ef2aSThomas Huth 1959fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1960fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1961fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1962fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1963efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1964fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1965fcf5ef2aSThomas Huth } 1966efe843d8SDavid Gibson } 1967fcf5ef2aSThomas Huth 1968fcf5ef2aSThomas Huth /* mullw mullw. */ 1969fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1970fcf5ef2aSThomas Huth { 1971fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1972fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1973fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1974fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1975fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1976fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1977fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1978fcf5ef2aSThomas Huth #else 1979fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1980fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1981fcf5ef2aSThomas Huth #endif 1982efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1983fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1984fcf5ef2aSThomas Huth } 1985efe843d8SDavid Gibson } 1986fcf5ef2aSThomas Huth 1987fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1988fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1989fcf5ef2aSThomas Huth { 1990fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1991fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1992fcf5ef2aSThomas Huth 1993fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1994fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1995fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1996fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1997fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1998fcf5ef2aSThomas Huth #else 1999fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2000fcf5ef2aSThomas Huth #endif 2001fcf5ef2aSThomas Huth 2002fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2003fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2004fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 200561aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 200661aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 200761aa9a69SNikunj A Dadhania } 2008fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2009fcf5ef2aSThomas Huth 2010efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2011fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2012fcf5ef2aSThomas Huth } 2013efe843d8SDavid Gibson } 2014fcf5ef2aSThomas Huth 2015fcf5ef2aSThomas Huth /* mulli */ 2016fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2017fcf5ef2aSThomas Huth { 2018fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2019fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2020fcf5ef2aSThomas Huth } 2021fcf5ef2aSThomas Huth 2022fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2023fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2024fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2025fcf5ef2aSThomas Huth { 2026fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2027fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2028fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2029fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2030fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2031fcf5ef2aSThomas Huth } 2032fcf5ef2aSThomas Huth } 2033fcf5ef2aSThomas Huth 2034fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2035fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2036fcf5ef2aSThomas Huth { 2037fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2038fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2039fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2040fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2041fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2042fcf5ef2aSThomas Huth } 2043fcf5ef2aSThomas Huth } 2044fcf5ef2aSThomas Huth 2045fcf5ef2aSThomas Huth /* mulld mulld. */ 2046fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2047fcf5ef2aSThomas Huth { 2048fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2049fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2050efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2051fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2052fcf5ef2aSThomas Huth } 2053efe843d8SDavid Gibson } 2054fcf5ef2aSThomas Huth 2055fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2056fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2057fcf5ef2aSThomas Huth { 2058fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2059fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2060fcf5ef2aSThomas Huth 2061fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2062fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2063fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2064fcf5ef2aSThomas Huth 2065fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2066fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 206761aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 206861aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 206961aa9a69SNikunj A Dadhania } 2070fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2071fcf5ef2aSThomas Huth 2072fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2073fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2074fcf5ef2aSThomas Huth } 2075fcf5ef2aSThomas Huth } 2076fcf5ef2aSThomas Huth #endif 2077fcf5ef2aSThomas Huth 2078fcf5ef2aSThomas Huth /* Common subf function */ 2079fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2080fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2081fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2082fcf5ef2aSThomas Huth { 2083fcf5ef2aSThomas Huth TCGv t0 = ret; 2084fcf5ef2aSThomas Huth 2085fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2086fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2087fcf5ef2aSThomas Huth } 2088fcf5ef2aSThomas Huth 2089fcf5ef2aSThomas Huth if (compute_ca) { 2090fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2091fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2092efe843d8SDavid Gibson /* 2093efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2094efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2095efe843d8SDavid Gibson * produce the carry into bit 32. 2096efe843d8SDavid Gibson */ 2097fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2098fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2099fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2100fcf5ef2aSThomas Huth if (add_ca) { 2101fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2102fcf5ef2aSThomas Huth } else { 2103fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2104fcf5ef2aSThomas Huth } 2105fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2106fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2107fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2108e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 210933903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 211033903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 211133903d0aSNikunj A Dadhania } 2112fcf5ef2aSThomas Huth } else if (add_ca) { 2113fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2114fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 21157058ff52SRichard Henderson zero = tcg_constant_tl(0); 2116fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2117fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21184c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2119fcf5ef2aSThomas Huth } else { 2120fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2121fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21224c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2123fcf5ef2aSThomas Huth } 2124fcf5ef2aSThomas Huth } else if (add_ca) { 2125efe843d8SDavid Gibson /* 2126efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2127efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2128efe843d8SDavid Gibson */ 2129fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2130fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2131fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2132fcf5ef2aSThomas Huth } else { 2133fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2134fcf5ef2aSThomas Huth } 2135fcf5ef2aSThomas Huth 2136fcf5ef2aSThomas Huth if (compute_ov) { 2137fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2138fcf5ef2aSThomas Huth } 2139fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2140fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2141fcf5ef2aSThomas Huth } 2142fcf5ef2aSThomas Huth 214311f4e8f8SRichard Henderson if (t0 != ret) { 2144fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2145fcf5ef2aSThomas Huth } 2146fcf5ef2aSThomas Huth } 2147fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2148fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2149fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2150fcf5ef2aSThomas Huth { \ 2151fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2152fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2153fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2154fcf5ef2aSThomas Huth } 2155fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2156fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2157fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2158fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2159fcf5ef2aSThomas Huth { \ 21607058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 2161fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2162fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2163fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2164fcf5ef2aSThomas Huth } 2165fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2166fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2167fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2168fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2169fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2170fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2171fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2172fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2173fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2174fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2175fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2176fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2177fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2178fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2179fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2180fcf5ef2aSThomas Huth 2181fcf5ef2aSThomas Huth /* subfic */ 2182fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2183fcf5ef2aSThomas Huth { 21847058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2185fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2186fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2187fcf5ef2aSThomas Huth } 2188fcf5ef2aSThomas Huth 2189fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2190fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2191fcf5ef2aSThomas Huth { 21927058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 2193fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2194fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2195fcf5ef2aSThomas Huth } 2196fcf5ef2aSThomas Huth 2197fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2198fcf5ef2aSThomas Huth { 21991480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22001480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22011480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22021480d71cSNikunj A Dadhania } 2203fcf5ef2aSThomas Huth } 2204fcf5ef2aSThomas Huth 2205fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2206fcf5ef2aSThomas Huth { 2207fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2208fcf5ef2aSThomas Huth } 2209fcf5ef2aSThomas Huth 2210fcf5ef2aSThomas Huth /*** Integer logical ***/ 2211fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2212fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2213fcf5ef2aSThomas Huth { \ 2214fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2215fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2216fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2217fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2218fcf5ef2aSThomas Huth } 2219fcf5ef2aSThomas Huth 2220fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2221fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2222fcf5ef2aSThomas Huth { \ 2223fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2224fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2225fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2226fcf5ef2aSThomas Huth } 2227fcf5ef2aSThomas Huth 2228fcf5ef2aSThomas Huth /* and & and. */ 2229fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2230fcf5ef2aSThomas Huth /* andc & andc. */ 2231fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2232fcf5ef2aSThomas Huth 2233fcf5ef2aSThomas Huth /* andi. */ 2234fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2235fcf5ef2aSThomas Huth { 2236efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2237efe843d8SDavid Gibson UIMM(ctx->opcode)); 2238fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2239fcf5ef2aSThomas Huth } 2240fcf5ef2aSThomas Huth 2241fcf5ef2aSThomas Huth /* andis. */ 2242fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2243fcf5ef2aSThomas Huth { 2244efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2245efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2246fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2247fcf5ef2aSThomas Huth } 2248fcf5ef2aSThomas Huth 2249fcf5ef2aSThomas Huth /* cntlzw */ 2250fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2251fcf5ef2aSThomas Huth { 22529b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22539b8514e5SRichard Henderson 22549b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22559b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22569b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22579b8514e5SRichard Henderson 2258efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2259fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2260fcf5ef2aSThomas Huth } 2261efe843d8SDavid Gibson } 2262fcf5ef2aSThomas Huth 2263fcf5ef2aSThomas Huth /* cnttzw */ 2264fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2265fcf5ef2aSThomas Huth { 22669b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22679b8514e5SRichard Henderson 22689b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22699b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22709b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22719b8514e5SRichard Henderson 2272fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2273fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2274fcf5ef2aSThomas Huth } 2275fcf5ef2aSThomas Huth } 2276fcf5ef2aSThomas Huth 2277fcf5ef2aSThomas Huth /* eqv & eqv. */ 2278fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2279fcf5ef2aSThomas Huth /* extsb & extsb. */ 2280fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2281fcf5ef2aSThomas Huth /* extsh & extsh. */ 2282fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2283fcf5ef2aSThomas Huth /* nand & nand. */ 2284fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2285fcf5ef2aSThomas Huth /* nor & nor. */ 2286fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2287fcf5ef2aSThomas Huth 2288fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2289fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2290fcf5ef2aSThomas Huth { 22917058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(0); 2292fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2293fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2294fcf5ef2aSThomas Huth 2295fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2296b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2297fcf5ef2aSThomas Huth } 2298fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2299fcf5ef2aSThomas Huth 2300fcf5ef2aSThomas Huth /* or & or. */ 2301fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2302fcf5ef2aSThomas Huth { 2303fcf5ef2aSThomas Huth int rs, ra, rb; 2304fcf5ef2aSThomas Huth 2305fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2306fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2307fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2308fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2309fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2310efe843d8SDavid Gibson if (rs != rb) { 2311fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2312efe843d8SDavid Gibson } else { 2313fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2314efe843d8SDavid Gibson } 2315efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2316fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2317efe843d8SDavid Gibson } 2318fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2319fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2320fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2321fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2322fcf5ef2aSThomas Huth int prio = 0; 2323fcf5ef2aSThomas Huth 2324fcf5ef2aSThomas Huth switch (rs) { 2325fcf5ef2aSThomas Huth case 1: 2326fcf5ef2aSThomas Huth /* Set process priority to low */ 2327fcf5ef2aSThomas Huth prio = 2; 2328fcf5ef2aSThomas Huth break; 2329fcf5ef2aSThomas Huth case 6: 2330fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2331fcf5ef2aSThomas Huth prio = 3; 2332fcf5ef2aSThomas Huth break; 2333fcf5ef2aSThomas Huth case 2: 2334fcf5ef2aSThomas Huth /* Set process priority to normal */ 2335fcf5ef2aSThomas Huth prio = 4; 2336fcf5ef2aSThomas Huth break; 2337fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2338fcf5ef2aSThomas Huth case 31: 2339fcf5ef2aSThomas Huth if (!ctx->pr) { 2340fcf5ef2aSThomas Huth /* Set process priority to very low */ 2341fcf5ef2aSThomas Huth prio = 1; 2342fcf5ef2aSThomas Huth } 2343fcf5ef2aSThomas Huth break; 2344fcf5ef2aSThomas Huth case 5: 2345fcf5ef2aSThomas Huth if (!ctx->pr) { 2346fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2347fcf5ef2aSThomas Huth prio = 5; 2348fcf5ef2aSThomas Huth } 2349fcf5ef2aSThomas Huth break; 2350fcf5ef2aSThomas Huth case 3: 2351fcf5ef2aSThomas Huth if (!ctx->pr) { 2352fcf5ef2aSThomas Huth /* Set process priority to high */ 2353fcf5ef2aSThomas Huth prio = 6; 2354fcf5ef2aSThomas Huth } 2355fcf5ef2aSThomas Huth break; 2356fcf5ef2aSThomas Huth case 7: 2357fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2358fcf5ef2aSThomas Huth /* Set process priority to very high */ 2359fcf5ef2aSThomas Huth prio = 7; 2360fcf5ef2aSThomas Huth } 2361fcf5ef2aSThomas Huth break; 2362fcf5ef2aSThomas Huth #endif 2363fcf5ef2aSThomas Huth default: 2364fcf5ef2aSThomas Huth break; 2365fcf5ef2aSThomas Huth } 2366fcf5ef2aSThomas Huth if (prio) { 2367fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2368fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2369fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2370fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2371fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2372fcf5ef2aSThomas Huth } 2373fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2374efe843d8SDavid Gibson /* 2375efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2376efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2377efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2378efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2379fcf5ef2aSThomas Huth */ 2380fcf5ef2aSThomas Huth gen_pause(ctx); 2381fcf5ef2aSThomas Huth #endif 2382fcf5ef2aSThomas Huth #endif 2383fcf5ef2aSThomas Huth } 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth /* orc & orc. */ 2386fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2387fcf5ef2aSThomas Huth 2388fcf5ef2aSThomas Huth /* xor & xor. */ 2389fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2390fcf5ef2aSThomas Huth { 2391fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2392efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2393efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2394efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2395efe843d8SDavid Gibson } else { 2396fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2397efe843d8SDavid Gibson } 2398efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2399fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2400fcf5ef2aSThomas Huth } 2401efe843d8SDavid Gibson } 2402fcf5ef2aSThomas Huth 2403fcf5ef2aSThomas Huth /* ori */ 2404fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2405fcf5ef2aSThomas Huth { 2406fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2407fcf5ef2aSThomas Huth 2408fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2409fcf5ef2aSThomas Huth return; 2410fcf5ef2aSThomas Huth } 2411fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2412fcf5ef2aSThomas Huth } 2413fcf5ef2aSThomas Huth 2414fcf5ef2aSThomas Huth /* oris */ 2415fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2416fcf5ef2aSThomas Huth { 2417fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2418fcf5ef2aSThomas Huth 2419fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2420fcf5ef2aSThomas Huth /* NOP */ 2421fcf5ef2aSThomas Huth return; 2422fcf5ef2aSThomas Huth } 2423efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2424efe843d8SDavid Gibson uimm << 16); 2425fcf5ef2aSThomas Huth } 2426fcf5ef2aSThomas Huth 2427fcf5ef2aSThomas Huth /* xori */ 2428fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2429fcf5ef2aSThomas Huth { 2430fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2431fcf5ef2aSThomas Huth 2432fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2433fcf5ef2aSThomas Huth /* NOP */ 2434fcf5ef2aSThomas Huth return; 2435fcf5ef2aSThomas Huth } 2436fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2437fcf5ef2aSThomas Huth } 2438fcf5ef2aSThomas Huth 2439fcf5ef2aSThomas Huth /* xoris */ 2440fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2441fcf5ef2aSThomas Huth { 2442fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2443fcf5ef2aSThomas Huth 2444fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2445fcf5ef2aSThomas Huth /* NOP */ 2446fcf5ef2aSThomas Huth return; 2447fcf5ef2aSThomas Huth } 2448efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2449efe843d8SDavid Gibson uimm << 16); 2450fcf5ef2aSThomas Huth } 2451fcf5ef2aSThomas Huth 2452fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2453fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2454fcf5ef2aSThomas Huth { 2455fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2456fcf5ef2aSThomas Huth } 2457fcf5ef2aSThomas Huth 2458fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2459fcf5ef2aSThomas Huth { 246079770002SRichard Henderson #if defined(TARGET_PPC64) 2461fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 246279770002SRichard Henderson #else 246379770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 246479770002SRichard Henderson #endif 2465fcf5ef2aSThomas Huth } 2466fcf5ef2aSThomas Huth 2467fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2468fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2469fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2470fcf5ef2aSThomas Huth { 247179770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2472fcf5ef2aSThomas Huth } 2473fcf5ef2aSThomas Huth #endif 2474fcf5ef2aSThomas Huth 2475fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2476fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2477fcf5ef2aSThomas Huth { 2478fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2479fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2480fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2481fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2482fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2483fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2484fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2485fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2486fcf5ef2aSThomas Huth } 2487fcf5ef2aSThomas Huth 2488fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2489fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2490fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2491fcf5ef2aSThomas Huth { 2492fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2493fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2494fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2495fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2496fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2497fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2498fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2499fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2500fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2501fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2502fcf5ef2aSThomas Huth } 2503fcf5ef2aSThomas Huth #endif 2504fcf5ef2aSThomas Huth 2505fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2506fcf5ef2aSThomas Huth /* bpermd */ 2507fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2508fcf5ef2aSThomas Huth { 2509fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2510fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2511fcf5ef2aSThomas Huth } 2512fcf5ef2aSThomas Huth #endif 2513fcf5ef2aSThomas Huth 2514fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2515fcf5ef2aSThomas Huth /* extsw & extsw. */ 2516fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2517fcf5ef2aSThomas Huth 2518fcf5ef2aSThomas Huth /* cntlzd */ 2519fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2520fcf5ef2aSThomas Huth { 25219b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2522efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2523fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2524fcf5ef2aSThomas Huth } 2525efe843d8SDavid Gibson } 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth /* cnttzd */ 2528fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2529fcf5ef2aSThomas Huth { 25309b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2531fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2532fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2533fcf5ef2aSThomas Huth } 2534fcf5ef2aSThomas Huth } 2535fcf5ef2aSThomas Huth 2536fcf5ef2aSThomas Huth /* darn */ 2537fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2538fcf5ef2aSThomas Huth { 2539fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2540fcf5ef2aSThomas Huth 25417e4357f6SRichard Henderson if (l > 2) { 25427e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25437e4357f6SRichard Henderson } else { 2544283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 2545fcf5ef2aSThomas Huth if (l == 0) { 2546fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25477e4357f6SRichard Henderson } else { 2548fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2549fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25507e4357f6SRichard Henderson } 2551fcf5ef2aSThomas Huth } 2552fcf5ef2aSThomas Huth } 2553fcf5ef2aSThomas Huth #endif 2554fcf5ef2aSThomas Huth 2555fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2556fcf5ef2aSThomas Huth 2557fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2558fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2559fcf5ef2aSThomas Huth { 2560fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2561fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2562fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2563fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2564fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2565fcf5ef2aSThomas Huth 2566fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2567fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2568fcf5ef2aSThomas Huth } else { 2569fcf5ef2aSThomas Huth target_ulong mask; 2570c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2571fcf5ef2aSThomas Huth TCGv t1; 2572fcf5ef2aSThomas Huth 2573fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2574fcf5ef2aSThomas Huth mb += 32; 2575fcf5ef2aSThomas Huth me += 32; 2576fcf5ef2aSThomas Huth #endif 2577fcf5ef2aSThomas Huth mask = MASK(mb, me); 2578fcf5ef2aSThomas Huth 2579c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2580c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2581c4f6a4a3SDaniele Buono mask_in_32b = false; 2582c4f6a4a3SDaniele Buono } 2583c4f6a4a3SDaniele Buono #endif 2584fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2585c4f6a4a3SDaniele Buono if (mask_in_32b) { 2586fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2587fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2588fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2589fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2590fcf5ef2aSThomas Huth } else { 2591fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2592fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2593fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2594fcf5ef2aSThomas Huth #else 2595fcf5ef2aSThomas Huth g_assert_not_reached(); 2596fcf5ef2aSThomas Huth #endif 2597fcf5ef2aSThomas Huth } 2598fcf5ef2aSThomas Huth 2599fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2600fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2601fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2602fcf5ef2aSThomas Huth } 2603fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2604fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2605fcf5ef2aSThomas Huth } 2606fcf5ef2aSThomas Huth } 2607fcf5ef2aSThomas Huth 2608fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2609fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2610fcf5ef2aSThomas Huth { 2611fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2612fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26137b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26147b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26157b4d326fSRichard Henderson int me = ME(ctx->opcode); 26167b4d326fSRichard Henderson int len = me - mb + 1; 26177b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2618fcf5ef2aSThomas Huth 26197b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26207b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26217b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26227b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2623fcf5ef2aSThomas Huth } else { 2624fcf5ef2aSThomas Huth target_ulong mask; 2625c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2626fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2627fcf5ef2aSThomas Huth mb += 32; 2628fcf5ef2aSThomas Huth me += 32; 2629fcf5ef2aSThomas Huth #endif 2630fcf5ef2aSThomas Huth mask = MASK(mb, me); 2631c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2632c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2633c4f6a4a3SDaniele Buono mask_in_32b = false; 2634c4f6a4a3SDaniele Buono } 2635c4f6a4a3SDaniele Buono #endif 2636c4f6a4a3SDaniele Buono if (mask_in_32b) { 26377b4d326fSRichard Henderson if (sh == 0) { 26387b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 263994f040aaSVitaly Chikunov } else { 2640fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2641fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2642fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2643fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2644fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 264594f040aaSVitaly Chikunov } 2646fcf5ef2aSThomas Huth } else { 2647fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2648fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2649fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2650fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2651fcf5ef2aSThomas Huth #else 2652fcf5ef2aSThomas Huth g_assert_not_reached(); 2653fcf5ef2aSThomas Huth #endif 2654fcf5ef2aSThomas Huth } 2655fcf5ef2aSThomas Huth } 2656fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2657fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2658fcf5ef2aSThomas Huth } 2659fcf5ef2aSThomas Huth } 2660fcf5ef2aSThomas Huth 2661fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2662fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2663fcf5ef2aSThomas Huth { 2664fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2665fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2666fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2667fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2668fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2669fcf5ef2aSThomas Huth target_ulong mask; 2670c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2671fcf5ef2aSThomas Huth 2672fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2673fcf5ef2aSThomas Huth mb += 32; 2674fcf5ef2aSThomas Huth me += 32; 2675fcf5ef2aSThomas Huth #endif 2676fcf5ef2aSThomas Huth mask = MASK(mb, me); 2677fcf5ef2aSThomas Huth 2678c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2679c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2680c4f6a4a3SDaniele Buono mask_in_32b = false; 2681c4f6a4a3SDaniele Buono } 2682c4f6a4a3SDaniele Buono #endif 2683c4f6a4a3SDaniele Buono if (mask_in_32b) { 2684fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2685fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2686fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2687fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2688fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2689fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2690fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2691fcf5ef2aSThomas Huth } else { 2692fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2693fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2694fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2695fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2696fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2697fcf5ef2aSThomas Huth #else 2698fcf5ef2aSThomas Huth g_assert_not_reached(); 2699fcf5ef2aSThomas Huth #endif 2700fcf5ef2aSThomas Huth } 2701fcf5ef2aSThomas Huth 2702fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2703fcf5ef2aSThomas Huth 2704fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2705fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2706fcf5ef2aSThomas Huth } 2707fcf5ef2aSThomas Huth } 2708fcf5ef2aSThomas Huth 2709fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2710fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2711fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2712fcf5ef2aSThomas Huth { \ 2713fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2714fcf5ef2aSThomas Huth } \ 2715fcf5ef2aSThomas Huth \ 2716fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2717fcf5ef2aSThomas Huth { \ 2718fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2719fcf5ef2aSThomas Huth } 2720fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2721fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2722fcf5ef2aSThomas Huth { \ 2723fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2724fcf5ef2aSThomas Huth } \ 2725fcf5ef2aSThomas Huth \ 2726fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2727fcf5ef2aSThomas Huth { \ 2728fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2729fcf5ef2aSThomas Huth } \ 2730fcf5ef2aSThomas Huth \ 2731fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2732fcf5ef2aSThomas Huth { \ 2733fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2734fcf5ef2aSThomas Huth } \ 2735fcf5ef2aSThomas Huth \ 2736fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2737fcf5ef2aSThomas Huth { \ 2738fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2739fcf5ef2aSThomas Huth } 2740fcf5ef2aSThomas Huth 2741fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2742fcf5ef2aSThomas Huth { 2743fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2744fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27457b4d326fSRichard Henderson int len = me - mb + 1; 27467b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2747fcf5ef2aSThomas Huth 27487b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27497b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27507b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27517b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2752fcf5ef2aSThomas Huth } else { 2753fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2754fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2755fcf5ef2aSThomas Huth } 2756fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2757fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2758fcf5ef2aSThomas Huth } 2759fcf5ef2aSThomas Huth } 2760fcf5ef2aSThomas Huth 2761fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2762fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2763fcf5ef2aSThomas Huth { 2764fcf5ef2aSThomas Huth uint32_t sh, mb; 2765fcf5ef2aSThomas Huth 2766fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2767fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2768fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2769fcf5ef2aSThomas Huth } 2770fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2771fcf5ef2aSThomas Huth 2772fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2773fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2774fcf5ef2aSThomas Huth { 2775fcf5ef2aSThomas Huth uint32_t sh, me; 2776fcf5ef2aSThomas Huth 2777fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2778fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2779fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2780fcf5ef2aSThomas Huth } 2781fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2782fcf5ef2aSThomas Huth 2783fcf5ef2aSThomas Huth /* rldic - rldic. */ 2784fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2785fcf5ef2aSThomas Huth { 2786fcf5ef2aSThomas Huth uint32_t sh, mb; 2787fcf5ef2aSThomas Huth 2788fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2789fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2790fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2791fcf5ef2aSThomas Huth } 2792fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2793fcf5ef2aSThomas Huth 2794fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2795fcf5ef2aSThomas Huth { 2796fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2797fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2798fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2799fcf5ef2aSThomas Huth TCGv t0; 2800fcf5ef2aSThomas Huth 2801fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2802fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2803fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2804fcf5ef2aSThomas Huth 2805fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2806fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2807fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2808fcf5ef2aSThomas Huth } 2809fcf5ef2aSThomas Huth } 2810fcf5ef2aSThomas Huth 2811fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2812fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2813fcf5ef2aSThomas Huth { 2814fcf5ef2aSThomas Huth uint32_t mb; 2815fcf5ef2aSThomas Huth 2816fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2817fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2818fcf5ef2aSThomas Huth } 2819fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2820fcf5ef2aSThomas Huth 2821fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2822fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2823fcf5ef2aSThomas Huth { 2824fcf5ef2aSThomas Huth uint32_t me; 2825fcf5ef2aSThomas Huth 2826fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2827fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2828fcf5ef2aSThomas Huth } 2829fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2830fcf5ef2aSThomas Huth 2831fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2832fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2833fcf5ef2aSThomas Huth { 2834fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2835fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2836fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2837fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2838fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2839fcf5ef2aSThomas Huth 2840fcf5ef2aSThomas Huth if (mb <= me) { 2841fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2842fcf5ef2aSThomas Huth } else { 2843fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2844fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2845fcf5ef2aSThomas Huth 2846fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2847fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2848fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2849fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2850fcf5ef2aSThomas Huth } 2851fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2852fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2853fcf5ef2aSThomas Huth } 2854fcf5ef2aSThomas Huth } 2855fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2856fcf5ef2aSThomas Huth #endif 2857fcf5ef2aSThomas Huth 2858fcf5ef2aSThomas Huth /*** Integer shift ***/ 2859fcf5ef2aSThomas Huth 2860fcf5ef2aSThomas Huth /* slw & slw. */ 2861fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2862fcf5ef2aSThomas Huth { 2863fcf5ef2aSThomas Huth TCGv t0, t1; 2864fcf5ef2aSThomas Huth 2865fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2866fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2867fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2868fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2869fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2870fcf5ef2aSThomas Huth #else 2871fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2872fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2873fcf5ef2aSThomas Huth #endif 2874fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2875fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2876fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2877fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2878fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2879efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2880fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2881fcf5ef2aSThomas Huth } 2882efe843d8SDavid Gibson } 2883fcf5ef2aSThomas Huth 2884fcf5ef2aSThomas Huth /* sraw & sraw. */ 2885fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2886fcf5ef2aSThomas Huth { 2887fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2888fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2889efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2890fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2891fcf5ef2aSThomas Huth } 2892efe843d8SDavid Gibson } 2893fcf5ef2aSThomas Huth 2894fcf5ef2aSThomas Huth /* srawi & srawi. */ 2895fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2896fcf5ef2aSThomas Huth { 2897fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2898fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2899fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2900fcf5ef2aSThomas Huth if (sh == 0) { 2901fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2902fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2903af1c259fSSandipan Das if (is_isa300(ctx)) { 2904af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2905af1c259fSSandipan Das } 2906fcf5ef2aSThomas Huth } else { 2907fcf5ef2aSThomas Huth TCGv t0; 2908fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2909fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2910fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2911fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2912fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2913fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2914af1c259fSSandipan Das if (is_isa300(ctx)) { 2915af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2916af1c259fSSandipan Das } 2917fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2918fcf5ef2aSThomas Huth } 2919fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2920fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2921fcf5ef2aSThomas Huth } 2922fcf5ef2aSThomas Huth } 2923fcf5ef2aSThomas Huth 2924fcf5ef2aSThomas Huth /* srw & srw. */ 2925fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2926fcf5ef2aSThomas Huth { 2927fcf5ef2aSThomas Huth TCGv t0, t1; 2928fcf5ef2aSThomas Huth 2929fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2930fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2931fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2932fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2933fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2934fcf5ef2aSThomas Huth #else 2935fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2936fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2937fcf5ef2aSThomas Huth #endif 2938fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2939fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2940fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2941fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2942fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2943efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2944fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2945fcf5ef2aSThomas Huth } 2946efe843d8SDavid Gibson } 2947fcf5ef2aSThomas Huth 2948fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2949fcf5ef2aSThomas Huth /* sld & sld. */ 2950fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2951fcf5ef2aSThomas Huth { 2952fcf5ef2aSThomas Huth TCGv t0, t1; 2953fcf5ef2aSThomas Huth 2954fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2955fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2956fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2957fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2958fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2959fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2960fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2961fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2962efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2963fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2964fcf5ef2aSThomas Huth } 2965efe843d8SDavid Gibson } 2966fcf5ef2aSThomas Huth 2967fcf5ef2aSThomas Huth /* srad & srad. */ 2968fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2969fcf5ef2aSThomas Huth { 2970fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2971fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2972efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2973fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2974fcf5ef2aSThomas Huth } 2975efe843d8SDavid Gibson } 2976fcf5ef2aSThomas Huth /* sradi & sradi. */ 2977fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2978fcf5ef2aSThomas Huth { 2979fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2980fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2981fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2982fcf5ef2aSThomas Huth if (sh == 0) { 2983fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2984fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2985af1c259fSSandipan Das if (is_isa300(ctx)) { 2986af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2987af1c259fSSandipan Das } 2988fcf5ef2aSThomas Huth } else { 2989fcf5ef2aSThomas Huth TCGv t0; 2990fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2991fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2992fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2993fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2994fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2995af1c259fSSandipan Das if (is_isa300(ctx)) { 2996af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2997af1c259fSSandipan Das } 2998fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2999fcf5ef2aSThomas Huth } 3000fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3001fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3002fcf5ef2aSThomas Huth } 3003fcf5ef2aSThomas Huth } 3004fcf5ef2aSThomas Huth 3005fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3006fcf5ef2aSThomas Huth { 3007fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3008fcf5ef2aSThomas Huth } 3009fcf5ef2aSThomas Huth 3010fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3011fcf5ef2aSThomas Huth { 3012fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3013fcf5ef2aSThomas Huth } 3014fcf5ef2aSThomas Huth 3015fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3016fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3017fcf5ef2aSThomas Huth { 3018fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3019fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3020fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3021fcf5ef2aSThomas Huth 3022fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3023fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3024fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3025fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3026fcf5ef2aSThomas Huth } 3027fcf5ef2aSThomas Huth } 3028fcf5ef2aSThomas Huth 3029fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3030fcf5ef2aSThomas Huth { 3031fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3032fcf5ef2aSThomas Huth } 3033fcf5ef2aSThomas Huth 3034fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3035fcf5ef2aSThomas Huth { 3036fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3037fcf5ef2aSThomas Huth } 3038fcf5ef2aSThomas Huth 3039fcf5ef2aSThomas Huth /* srd & srd. */ 3040fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3041fcf5ef2aSThomas Huth { 3042fcf5ef2aSThomas Huth TCGv t0, t1; 3043fcf5ef2aSThomas Huth 3044fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3045fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3046fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3047fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3048fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3049fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3050fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3051fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3052efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3053fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3054fcf5ef2aSThomas Huth } 3055efe843d8SDavid Gibson } 3056fcf5ef2aSThomas Huth #endif 3057fcf5ef2aSThomas Huth 3058fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3059fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3060fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3061fcf5ef2aSThomas Huth target_long maskl) 3062fcf5ef2aSThomas Huth { 3063fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3064fcf5ef2aSThomas Huth 3065fcf5ef2aSThomas Huth simm &= ~maskl; 3066fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3067fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3068fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3069fcf5ef2aSThomas Huth } 3070fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3071fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3072fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3073fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3074fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3075fcf5ef2aSThomas Huth } 3076fcf5ef2aSThomas Huth } else { 3077fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3078fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3079fcf5ef2aSThomas Huth } else { 3080fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3081fcf5ef2aSThomas Huth } 3082fcf5ef2aSThomas Huth } 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth 3085fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3086fcf5ef2aSThomas Huth { 3087fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3088fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3089fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3090fcf5ef2aSThomas Huth } else { 3091fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3092fcf5ef2aSThomas Huth } 3093fcf5ef2aSThomas Huth } else { 3094fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3095fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3096fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3097fcf5ef2aSThomas Huth } 3098fcf5ef2aSThomas Huth } 3099fcf5ef2aSThomas Huth } 3100fcf5ef2aSThomas Huth 3101fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3102fcf5ef2aSThomas Huth { 3103fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3104fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3105fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3106fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3107fcf5ef2aSThomas Huth } else { 3108fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3109fcf5ef2aSThomas Huth } 3110fcf5ef2aSThomas Huth } 3111fcf5ef2aSThomas Huth 3112fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3113fcf5ef2aSThomas Huth target_long val) 3114fcf5ef2aSThomas Huth { 3115fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3116fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3117fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3118fcf5ef2aSThomas Huth } 3119fcf5ef2aSThomas Huth } 3120fcf5ef2aSThomas Huth 3121fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3122fcf5ef2aSThomas Huth { 3123fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3124fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3125fcf5ef2aSThomas Huth } 3126fcf5ef2aSThomas Huth 3127eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3128eb63efd9SFernando Eckhardt Valle { 3129eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3130eb63efd9SFernando Eckhardt Valle if (ra) { 3131eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3132eb63efd9SFernando Eckhardt Valle } else { 3133eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3134eb63efd9SFernando Eckhardt Valle } 3135eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3136eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3137eb63efd9SFernando Eckhardt Valle } 3138eb63efd9SFernando Eckhardt Valle return ea; 3139eb63efd9SFernando Eckhardt Valle } 3140eb63efd9SFernando Eckhardt Valle 3141fcf5ef2aSThomas Huth /*** Integer load ***/ 3142fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3143fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3144fcf5ef2aSThomas Huth 3145fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3146fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3147fcf5ef2aSThomas Huth TCGv val, \ 3148fcf5ef2aSThomas Huth TCGv addr) \ 3149fcf5ef2aSThomas Huth { \ 3150fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3151fcf5ef2aSThomas Huth } 3152fcf5ef2aSThomas Huth 3153fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3154fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3155fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3156fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3157fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3158fcf5ef2aSThomas Huth 3159fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3160fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3161fcf5ef2aSThomas Huth 3162fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3163fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3164fcf5ef2aSThomas Huth TCGv_i64 val, \ 3165fcf5ef2aSThomas Huth TCGv addr) \ 3166fcf5ef2aSThomas Huth { \ 3167fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3168fcf5ef2aSThomas Huth } 3169fcf5ef2aSThomas Huth 3170fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3171fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3172fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3173fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3174fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3175fcf5ef2aSThomas Huth 3176fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3177fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3178fcf5ef2aSThomas Huth #endif 3179fcf5ef2aSThomas Huth 3180fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3181fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3182fcf5ef2aSThomas Huth TCGv val, \ 3183fcf5ef2aSThomas Huth TCGv addr) \ 3184fcf5ef2aSThomas Huth { \ 3185fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3186fcf5ef2aSThomas Huth } 3187fcf5ef2aSThomas Huth 3188e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3189fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3190e8f4c8d6SRichard Henderson #endif 3191fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3192fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3193fcf5ef2aSThomas Huth 3194fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3195fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3196fcf5ef2aSThomas Huth 3197fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3198fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3199fcf5ef2aSThomas Huth TCGv_i64 val, \ 3200fcf5ef2aSThomas Huth TCGv addr) \ 3201fcf5ef2aSThomas Huth { \ 3202fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3203fcf5ef2aSThomas Huth } 3204fcf5ef2aSThomas Huth 3205fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3206fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3207fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3208fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3209fcf5ef2aSThomas Huth 3210fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3211fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3212fcf5ef2aSThomas Huth #endif 3213fcf5ef2aSThomas Huth 3214fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3215fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3216fcf5ef2aSThomas Huth { \ 3217fcf5ef2aSThomas Huth TCGv EA; \ 32189f0cf041SMatheus Ferst chk(ctx); \ 3219fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3220fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3221fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3222fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3223fcf5ef2aSThomas Huth } 3224fcf5ef2aSThomas Huth 3225fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3226fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3227fcf5ef2aSThomas Huth 3228fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3229fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3230fcf5ef2aSThomas Huth 323150728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 323250728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 323350728199SRoman Kapl { \ 323450728199SRoman Kapl TCGv EA; \ 32359f0cf041SMatheus Ferst CHK_SV(ctx); \ 323650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 323750728199SRoman Kapl EA = tcg_temp_new(); \ 323850728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 323950728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 324050728199SRoman Kapl } 324150728199SRoman Kapl 324250728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 324350728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 324450728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 324550728199SRoman Kapl #if defined(TARGET_PPC64) 3246fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 324750728199SRoman Kapl #endif 324850728199SRoman Kapl 3249fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3250fcf5ef2aSThomas Huth /* CI load/store variants */ 3251fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3252fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3253fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3254fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3255fcf5ef2aSThomas Huth #endif 3256fcf5ef2aSThomas Huth 3257fcf5ef2aSThomas Huth /*** Integer store ***/ 3258fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3259fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3260fcf5ef2aSThomas Huth { \ 3261fcf5ef2aSThomas Huth TCGv EA; \ 32629f0cf041SMatheus Ferst chk(ctx); \ 3263fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3264fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3265fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3266fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3267fcf5ef2aSThomas Huth } 3268fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3269fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3270fcf5ef2aSThomas Huth 3271fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3272fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3273fcf5ef2aSThomas Huth 327450728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 327550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 327650728199SRoman Kapl { \ 327750728199SRoman Kapl TCGv EA; \ 32789f0cf041SMatheus Ferst CHK_SV(ctx); \ 327950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 328050728199SRoman Kapl EA = tcg_temp_new(); \ 328150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 328250728199SRoman Kapl tcg_gen_qemu_st_tl( \ 328350728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 328450728199SRoman Kapl } 328550728199SRoman Kapl 328650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 328750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 328850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 328950728199SRoman Kapl #if defined(TARGET_PPC64) 3290fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 329150728199SRoman Kapl #endif 329250728199SRoman Kapl 3293fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3294fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3295fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3296fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3297fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3298fcf5ef2aSThomas Huth #endif 3299fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3300fcf5ef2aSThomas Huth 3301fcf5ef2aSThomas Huth /* lhbrx */ 3302fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3303fcf5ef2aSThomas Huth 3304fcf5ef2aSThomas Huth /* lwbrx */ 3305fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3306fcf5ef2aSThomas Huth 3307fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3308fcf5ef2aSThomas Huth /* ldbrx */ 3309fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3310fcf5ef2aSThomas Huth /* stdbrx */ 3311fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3312fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3313fcf5ef2aSThomas Huth 3314fcf5ef2aSThomas Huth /* sthbrx */ 3315fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3316fcf5ef2aSThomas Huth /* stwbrx */ 3317fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3318fcf5ef2aSThomas Huth 3319fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3320fcf5ef2aSThomas Huth 3321fcf5ef2aSThomas Huth /* lmw */ 3322fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3323fcf5ef2aSThomas Huth { 3324fcf5ef2aSThomas Huth TCGv t0; 3325fcf5ef2aSThomas Huth TCGv_i32 t1; 3326fcf5ef2aSThomas Huth 3327fcf5ef2aSThomas Huth if (ctx->le_mode) { 3328fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3329fcf5ef2aSThomas Huth return; 3330fcf5ef2aSThomas Huth } 3331fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3332fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33337058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 3334fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3335fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3336fcf5ef2aSThomas Huth } 3337fcf5ef2aSThomas Huth 3338fcf5ef2aSThomas Huth /* stmw */ 3339fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3340fcf5ef2aSThomas Huth { 3341fcf5ef2aSThomas Huth TCGv t0; 3342fcf5ef2aSThomas Huth TCGv_i32 t1; 3343fcf5ef2aSThomas Huth 3344fcf5ef2aSThomas Huth if (ctx->le_mode) { 3345fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3346fcf5ef2aSThomas Huth return; 3347fcf5ef2aSThomas Huth } 3348fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3349fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33507058ff52SRichard Henderson t1 = tcg_constant_i32(rS(ctx->opcode)); 3351fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3352fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3353fcf5ef2aSThomas Huth } 3354fcf5ef2aSThomas Huth 3355fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3356fcf5ef2aSThomas Huth 3357fcf5ef2aSThomas Huth /* lswi */ 3358efe843d8SDavid Gibson /* 3359efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3360efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3361efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3362efe843d8SDavid Gibson * spec... 3363fcf5ef2aSThomas Huth */ 3364fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3365fcf5ef2aSThomas Huth { 3366fcf5ef2aSThomas Huth TCGv t0; 3367fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3368fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3369fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3370fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3371fcf5ef2aSThomas Huth int nr; 3372fcf5ef2aSThomas Huth 3373fcf5ef2aSThomas Huth if (ctx->le_mode) { 3374fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3375fcf5ef2aSThomas Huth return; 3376fcf5ef2aSThomas Huth } 3377efe843d8SDavid Gibson if (nb == 0) { 3378fcf5ef2aSThomas Huth nb = 32; 3379efe843d8SDavid Gibson } 3380f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3381fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3382fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3383fcf5ef2aSThomas Huth return; 3384fcf5ef2aSThomas Huth } 3385fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3386fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3387fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 33887058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 33897058ff52SRichard Henderson t2 = tcg_constant_i32(start); 3390fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3391fcf5ef2aSThomas Huth } 3392fcf5ef2aSThomas Huth 3393fcf5ef2aSThomas Huth /* lswx */ 3394fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3395fcf5ef2aSThomas Huth { 3396fcf5ef2aSThomas Huth TCGv t0; 3397fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3398fcf5ef2aSThomas Huth 3399fcf5ef2aSThomas Huth if (ctx->le_mode) { 3400fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3401fcf5ef2aSThomas Huth return; 3402fcf5ef2aSThomas Huth } 3403fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3404fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3405fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 34067058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 34077058ff52SRichard Henderson t2 = tcg_constant_i32(rA(ctx->opcode)); 34087058ff52SRichard Henderson t3 = tcg_constant_i32(rB(ctx->opcode)); 3409fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3410fcf5ef2aSThomas Huth } 3411fcf5ef2aSThomas Huth 3412fcf5ef2aSThomas Huth /* stswi */ 3413fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3414fcf5ef2aSThomas Huth { 3415fcf5ef2aSThomas Huth TCGv t0; 3416fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3417fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3418fcf5ef2aSThomas Huth 3419fcf5ef2aSThomas Huth if (ctx->le_mode) { 3420fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3421fcf5ef2aSThomas Huth return; 3422fcf5ef2aSThomas Huth } 3423fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3424fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3425fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3426efe843d8SDavid Gibson if (nb == 0) { 3427fcf5ef2aSThomas Huth nb = 32; 3428efe843d8SDavid Gibson } 34297058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 34307058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3431fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3432fcf5ef2aSThomas Huth } 3433fcf5ef2aSThomas Huth 3434fcf5ef2aSThomas Huth /* stswx */ 3435fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3436fcf5ef2aSThomas Huth { 3437fcf5ef2aSThomas Huth TCGv t0; 3438fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3439fcf5ef2aSThomas Huth 3440fcf5ef2aSThomas Huth if (ctx->le_mode) { 3441fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3442fcf5ef2aSThomas Huth return; 3443fcf5ef2aSThomas Huth } 3444fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3445fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3446fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3447fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3448fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3449fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 34507058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3451fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3452fcf5ef2aSThomas Huth } 3453fcf5ef2aSThomas Huth 3454fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3455fcf5ef2aSThomas Huth /* eieio */ 3456fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3457fcf5ef2aSThomas Huth { 3458fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3459fcb830afSNicholas Piggin 3460fcb830afSNicholas Piggin /* 3461fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3462fcb830afSNicholas Piggin * operations in the set: 3463fcb830afSNicholas Piggin * - loads from CI memory. 3464fcb830afSNicholas Piggin * - stores to CI memory. 3465fcb830afSNicholas Piggin * - stores to WT memory. 3466fcb830afSNicholas Piggin * 3467fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3468fcb830afSNicholas Piggin * - stores to cacheble memory. 3469fcb830afSNicholas Piggin * 3470fcb830afSNicholas Piggin * It also serializes instructions: 3471fcb830afSNicholas Piggin * - dcbt and dcbst. 3472fcb830afSNicholas Piggin * 3473fcb830afSNicholas Piggin * It separately serializes: 3474fcb830afSNicholas Piggin * - tlbie and tlbsync. 3475fcb830afSNicholas Piggin * 3476fcb830afSNicholas Piggin * And separately serializes: 3477fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3478fcb830afSNicholas Piggin * 3479fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3480fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3481fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3482fcb830afSNicholas Piggin * serialization. 3483fcb830afSNicholas Piggin */ 3484c8fd8373SCédric Le Goater 3485c8fd8373SCédric Le Goater /* 3486c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3487c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3488c8fd8373SCédric Le Goater */ 3489c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3490c8fd8373SCédric Le Goater /* 3491c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3492c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3493c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3494c8fd8373SCédric Le Goater * complain to the user. 3495c8fd8373SCédric Le Goater */ 3496c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3497c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 34982c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3499c8fd8373SCédric Le Goater } else { 3500c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3501c8fd8373SCédric Le Goater } 3502c8fd8373SCédric Le Goater } 3503c8fd8373SCédric Le Goater 3504c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3505fcf5ef2aSThomas Huth } 3506fcf5ef2aSThomas Huth 3507fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3508fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3509fcf5ef2aSThomas Huth { 3510fcf5ef2aSThomas Huth TCGv_i32 t; 3511fcf5ef2aSThomas Huth TCGLabel *l; 3512fcf5ef2aSThomas Huth 3513fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3514fcf5ef2aSThomas Huth return; 3515fcf5ef2aSThomas Huth } 3516fcf5ef2aSThomas Huth l = gen_new_label(); 3517fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3518fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3519fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3520fcf5ef2aSThomas Huth if (global) { 3521fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3522fcf5ef2aSThomas Huth } else { 3523fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3524fcf5ef2aSThomas Huth } 3525fcf5ef2aSThomas Huth gen_set_label(l); 3526fcf5ef2aSThomas Huth } 3527fcf5ef2aSThomas Huth #else 3528fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3529fcf5ef2aSThomas Huth #endif 3530fcf5ef2aSThomas Huth 3531fcf5ef2aSThomas Huth /* isync */ 3532fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3533fcf5ef2aSThomas Huth { 3534fcf5ef2aSThomas Huth /* 3535fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3536fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3537fcf5ef2aSThomas Huth */ 3538fcf5ef2aSThomas Huth if (!ctx->pr) { 3539fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3540fcf5ef2aSThomas Huth } 35414771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3542d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3543fcf5ef2aSThomas Huth } 3544fcf5ef2aSThomas Huth 3545fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3546fcf5ef2aSThomas Huth 354714776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 35482a4e6c1bSRichard Henderson { 35492a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 35502a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 35512a4e6c1bSRichard Henderson 35522a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 35532a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 35542a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 35552a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 3556392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 35572a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 35582a4e6c1bSRichard Henderson } 35592a4e6c1bSRichard Henderson 3560fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3561fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3562fcf5ef2aSThomas Huth { \ 35632a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3564fcf5ef2aSThomas Huth } 3565fcf5ef2aSThomas Huth 3566fcf5ef2aSThomas Huth /* lwarx */ 3567fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3568fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3569fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3570fcf5ef2aSThomas Huth 357114776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 357220923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 357320923c1dSRichard Henderson { 357420923c1dSRichard Henderson TCGv t = tcg_temp_new(); 357520923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 357620923c1dSRichard Henderson TCGv u = tcg_temp_new(); 357720923c1dSRichard Henderson 357820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 357920923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 358020923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 358120923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 358220923c1dSRichard Henderson 358320923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 358420923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 358520923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 358620923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 358720923c1dSRichard Henderson 358820923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 358920923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 359020923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 359120923c1dSRichard Henderson } 359220923c1dSRichard Henderson 359314776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 359420ba8504SRichard Henderson { 359520ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 359620ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 359720923c1dSRichard Henderson int rt = rD(ctx->opcode); 359820923c1dSRichard Henderson bool need_serial; 359920ba8504SRichard Henderson TCGv src, dst; 360020ba8504SRichard Henderson 360120ba8504SRichard Henderson gen_addr_register(ctx, EA); 360220923c1dSRichard Henderson dst = cpu_gpr[rt]; 360320923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 360420ba8504SRichard Henderson 360520923c1dSRichard Henderson need_serial = false; 360620ba8504SRichard Henderson memop |= MO_ALIGN; 360720ba8504SRichard Henderson switch (gpr_FC) { 360820ba8504SRichard Henderson case 0: /* Fetch and add */ 360920ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 361020ba8504SRichard Henderson break; 361120ba8504SRichard Henderson case 1: /* Fetch and xor */ 361220ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 361320ba8504SRichard Henderson break; 361420ba8504SRichard Henderson case 2: /* Fetch and or */ 361520ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 361620ba8504SRichard Henderson break; 361720ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 361820ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 361920ba8504SRichard Henderson break; 3620b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3621b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3622b8ce0f86SRichard Henderson break; 3623b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3624b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3625b8ce0f86SRichard Henderson break; 3626b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3627b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3628b8ce0f86SRichard Henderson break; 3629b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3630b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3631b8ce0f86SRichard Henderson break; 363220ba8504SRichard Henderson case 8: /* Swap */ 363320ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 363420ba8504SRichard Henderson break; 363520923c1dSRichard Henderson 363620923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 363720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 363820923c1dSRichard Henderson need_serial = true; 363920923c1dSRichard Henderson } else { 364020923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 364120923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 364220923c1dSRichard Henderson 364320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 364420923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 364520923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 364620923c1dSRichard Henderson } else { 364720923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 364820923c1dSRichard Henderson } 364920923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 365020923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 365120923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 365220923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 365320923c1dSRichard Henderson } 365420ba8504SRichard Henderson break; 365520923c1dSRichard Henderson 365620923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 365720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 365820923c1dSRichard Henderson need_serial = true; 365920923c1dSRichard Henderson } else { 366020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 366120923c1dSRichard Henderson } 366220923c1dSRichard Henderson break; 366320923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 366420923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 366520923c1dSRichard Henderson need_serial = true; 366620923c1dSRichard Henderson } else { 366720923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 366820923c1dSRichard Henderson } 366920923c1dSRichard Henderson break; 367020923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 367120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 367220923c1dSRichard Henderson need_serial = true; 367320923c1dSRichard Henderson } else { 367420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 367520923c1dSRichard Henderson } 367620923c1dSRichard Henderson break; 367720923c1dSRichard Henderson 367820ba8504SRichard Henderson default: 367920ba8504SRichard Henderson /* invoke data storage error handler */ 368020ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 368120ba8504SRichard Henderson } 368220923c1dSRichard Henderson 368320923c1dSRichard Henderson if (need_serial) { 368420923c1dSRichard Henderson /* Restart with exclusive lock. */ 368520923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 368620923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 368720923c1dSRichard Henderson } 3688a68a6146SBalamuruhan S } 3689a68a6146SBalamuruhan S 369020ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 369120ba8504SRichard Henderson { 369220ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 369320ba8504SRichard Henderson } 369420ba8504SRichard Henderson 369520ba8504SRichard Henderson #ifdef TARGET_PPC64 369620ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 369720ba8504SRichard Henderson { 3698fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 369920ba8504SRichard Henderson } 3700a68a6146SBalamuruhan S #endif 3701a68a6146SBalamuruhan S 370214776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 37039deb041cSRichard Henderson { 37049deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 37059deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 37069deb041cSRichard Henderson TCGv src, discard; 37079deb041cSRichard Henderson 37089deb041cSRichard Henderson gen_addr_register(ctx, EA); 37099deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 37109deb041cSRichard Henderson discard = tcg_temp_new(); 37119deb041cSRichard Henderson 37129deb041cSRichard Henderson memop |= MO_ALIGN; 37139deb041cSRichard Henderson switch (gpr_FC) { 37149deb041cSRichard Henderson case 0: /* add and Store */ 37159deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37169deb041cSRichard Henderson break; 37179deb041cSRichard Henderson case 1: /* xor and Store */ 37189deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37199deb041cSRichard Henderson break; 37209deb041cSRichard Henderson case 2: /* Or and Store */ 37219deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37229deb041cSRichard Henderson break; 37239deb041cSRichard Henderson case 3: /* 'and' and Store */ 37249deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37259deb041cSRichard Henderson break; 37269deb041cSRichard Henderson case 4: /* Store max unsigned */ 3727b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3728b8ce0f86SRichard Henderson break; 37299deb041cSRichard Henderson case 5: /* Store max signed */ 3730b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3731b8ce0f86SRichard Henderson break; 37329deb041cSRichard Henderson case 6: /* Store min unsigned */ 3733b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3734b8ce0f86SRichard Henderson break; 37359deb041cSRichard Henderson case 7: /* Store min signed */ 3736b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3737b8ce0f86SRichard Henderson break; 37389deb041cSRichard Henderson case 24: /* Store twin */ 37397fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 37407fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 37417fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 37427fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 37437fbc2b20SRichard Henderson } else { 37447fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 37457fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 37467fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 37477fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 37487fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 37497fbc2b20SRichard Henderson 37507fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 37517fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 37527fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 37537fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 37547fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 37557fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 37567fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 37577fbc2b20SRichard Henderson } 37589deb041cSRichard Henderson break; 37599deb041cSRichard Henderson default: 37609deb041cSRichard Henderson /* invoke data storage error handler */ 37619deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 37629deb041cSRichard Henderson } 3763a3401188SBalamuruhan S } 3764a3401188SBalamuruhan S 37659deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 37669deb041cSRichard Henderson { 37679deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 37689deb041cSRichard Henderson } 37699deb041cSRichard Henderson 37709deb041cSRichard Henderson #ifdef TARGET_PPC64 37719deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 37729deb041cSRichard Henderson { 3773fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 37749deb041cSRichard Henderson } 3775a3401188SBalamuruhan S #endif 3776a3401188SBalamuruhan S 377714776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3778fcf5ef2aSThomas Huth { 377921ee07e7SNicholas Piggin TCGLabel *lfail; 378021ee07e7SNicholas Piggin TCGv EA; 378121ee07e7SNicholas Piggin TCGv cr0; 378221ee07e7SNicholas Piggin TCGv t0; 378321ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3784fcf5ef2aSThomas Huth 378521ee07e7SNicholas Piggin lfail = gen_new_label(); 378621ee07e7SNicholas Piggin EA = tcg_temp_new(); 378721ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3788253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 378921ee07e7SNicholas Piggin 379021ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 379121ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 379221ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 379321ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 379421ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 379521ee07e7SNicholas Piggin 3796253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 379721ee07e7SNicholas Piggin cpu_gpr[rs], ctx->mem_idx, 3798253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3799253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3800253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 380121ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3802253ce7b2SNikunj A Dadhania 380321ee07e7SNicholas Piggin gen_set_label(lfail); 380421ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3805fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3806fcf5ef2aSThomas Huth } 3807fcf5ef2aSThomas Huth 3808fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3809fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3810fcf5ef2aSThomas Huth { \ 3811d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3812fcf5ef2aSThomas Huth } 3813fcf5ef2aSThomas Huth 3814fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3815fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3816fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3817fcf5ef2aSThomas Huth 3818fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3819fcf5ef2aSThomas Huth /* ldarx */ 3820fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3821fcf5ef2aSThomas Huth /* stdcx. */ 3822fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3823fcf5ef2aSThomas Huth 3824fcf5ef2aSThomas Huth /* lqarx */ 3825fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3826fcf5ef2aSThomas Huth { 3827fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 382894bf2658SRichard Henderson TCGv EA, hi, lo; 382957b38ffdSRichard Henderson TCGv_i128 t16; 3830fcf5ef2aSThomas Huth 3831fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3832fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3833fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3834fcf5ef2aSThomas Huth return; 3835fcf5ef2aSThomas Huth } 3836fcf5ef2aSThomas Huth 3837fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 383894bf2658SRichard Henderson EA = tcg_temp_new(); 3839fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 384094bf2658SRichard Henderson 384194bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 384294bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 384394bf2658SRichard Henderson hi = cpu_gpr[rd]; 384494bf2658SRichard Henderson 384557b38ffdSRichard Henderson t16 = tcg_temp_new_i128(); 384657b38ffdSRichard Henderson tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 384757b38ffdSRichard Henderson tcg_gen_extr_i128_i64(lo, hi, t16); 384894bf2658SRichard Henderson 3849e025e8f5SNicholas Piggin tcg_gen_mov_tl(cpu_reserve, EA); 3850392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, 16); 385194bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 385294bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3853fcf5ef2aSThomas Huth } 3854fcf5ef2aSThomas Huth 3855fcf5ef2aSThomas Huth /* stqcx. */ 3856fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3857fcf5ef2aSThomas Huth { 385821ee07e7SNicholas Piggin TCGLabel *lfail; 3859894448aeSRichard Henderson TCGv EA, t0, t1; 386021ee07e7SNicholas Piggin TCGv cr0; 3861894448aeSRichard Henderson TCGv_i128 cmp, val; 386221ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3863fcf5ef2aSThomas Huth 38644a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3865fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3866fcf5ef2aSThomas Huth return; 3867fcf5ef2aSThomas Huth } 38684a9b3c5dSRichard Henderson 386921ee07e7SNicholas Piggin lfail = gen_new_label(); 38704a9b3c5dSRichard Henderson EA = tcg_temp_new(); 387121ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3872fcf5ef2aSThomas Huth 387321ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 387421ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 387521ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 387621ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 387721ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 38784a9b3c5dSRichard Henderson 3879894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 3880894448aeSRichard Henderson val = tcg_temp_new_i128(); 38814a9b3c5dSRichard Henderson 3882894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 38834a9b3c5dSRichard Henderson 3884894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3885894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 38864a9b3c5dSRichard Henderson 3887894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3888894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 3889894448aeSRichard Henderson 3890894448aeSRichard Henderson t0 = tcg_temp_new(); 3891894448aeSRichard Henderson t1 = tcg_temp_new(); 3892894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 3893894448aeSRichard Henderson 3894894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3895894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3896894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 3897894448aeSRichard Henderson 3898894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3899894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 390021ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3901894448aeSRichard Henderson 390221ee07e7SNicholas Piggin gen_set_label(lfail); 390321ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 39044a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 39054a9b3c5dSRichard Henderson } 3906fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3907fcf5ef2aSThomas Huth 3908fcf5ef2aSThomas Huth /* sync */ 3909fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3910fcf5ef2aSThomas Huth { 391103abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 3912fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3913fcf5ef2aSThomas Huth 391403abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 391503abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 391603abfd90SNicholas Piggin } 391703abfd90SNicholas Piggin 3918fcf5ef2aSThomas Huth /* 3919fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3920fcf5ef2aSThomas Huth * 3921fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3922fcf5ef2aSThomas Huth * 3923fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3924fcf5ef2aSThomas Huth * check MSR_PR as well. 3925fcf5ef2aSThomas Huth */ 3926fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3927fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3928fcf5ef2aSThomas Huth } 392903abfd90SNicholas Piggin 393003abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 3931fcf5ef2aSThomas Huth } 3932fcf5ef2aSThomas Huth 3933fcf5ef2aSThomas Huth /* wait */ 3934fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3935fcf5ef2aSThomas Huth { 39360c9717ffSNicholas Piggin uint32_t wc; 39370c9717ffSNicholas Piggin 39380c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 39390c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 39400c9717ffSNicholas Piggin 39410c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 39420c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 39430c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39440c9717ffSNicholas Piggin } else { 39450c9717ffSNicholas Piggin wc = 0; 39460c9717ffSNicholas Piggin } 39470c9717ffSNicholas Piggin 39480c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 39490c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 39500c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39510c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 39520c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 39530c9717ffSNicholas Piggin 39540c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 39550c9717ffSNicholas Piggin if (wc == 3) { 39560c9717ffSNicholas Piggin gen_invalid(ctx); 39570c9717ffSNicholas Piggin return; 39580c9717ffSNicholas Piggin } 39590c9717ffSNicholas Piggin 39600c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 39610c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 39620c9717ffSNicholas Piggin gen_invalid(ctx); 39630c9717ffSNicholas Piggin return; 39640c9717ffSNicholas Piggin } 39650c9717ffSNicholas Piggin 39660c9717ffSNicholas Piggin } else { /* ISA300 */ 39670c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 39680c9717ffSNicholas Piggin if (wc > 0) { 39690c9717ffSNicholas Piggin gen_invalid(ctx); 39700c9717ffSNicholas Piggin return; 39710c9717ffSNicholas Piggin } 39720c9717ffSNicholas Piggin } 39730c9717ffSNicholas Piggin 39740c9717ffSNicholas Piggin } else { 39750c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 39760c9717ffSNicholas Piggin gen_invalid(ctx); 39770c9717ffSNicholas Piggin return; 39780c9717ffSNicholas Piggin } 39790c9717ffSNicholas Piggin 39800c9717ffSNicholas Piggin /* 39810c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 39820c9717ffSNicholas Piggin * to occur. 39830c9717ffSNicholas Piggin */ 39840c9717ffSNicholas Piggin if (wc == 0) { 39857058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(1); 3986fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3987fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3988fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3989b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3990fcf5ef2aSThomas Huth } 3991fcf5ef2aSThomas Huth 39920c9717ffSNicholas Piggin /* 39930c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 39940c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 39950c9717ffSNicholas Piggin * 39960c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 39970c9717ffSNicholas Piggin * no-ops. 39980c9717ffSNicholas Piggin * 39990c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 40000c9717ffSNicholas Piggin * 40010c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 40020c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 40030c9717ffSNicholas Piggin * 40040c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 40050c9717ffSNicholas Piggin * 40060c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 40070c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 40080c9717ffSNicholas Piggin * can be implemented as a no-op. 40090c9717ffSNicholas Piggin * 40100c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 40110c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 40120c9717ffSNicholas Piggin * no-op. 40130c9717ffSNicholas Piggin * 40140c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 40150c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 40160c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 40170c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 40180c9717ffSNicholas Piggin * (if suboptimal). 40190c9717ffSNicholas Piggin */ 40200c9717ffSNicholas Piggin } 40210c9717ffSNicholas Piggin 4022fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4023fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4024fcf5ef2aSThomas Huth { 4025fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40269f0cf041SMatheus Ferst GEN_PRIV(ctx); 4027fcf5ef2aSThomas Huth #else 4028fcf5ef2aSThomas Huth TCGv_i32 t; 4029fcf5ef2aSThomas Huth 40309f0cf041SMatheus Ferst CHK_HV(ctx); 4031c32654afSNicholas Piggin translator_io_start(&ctx->base); 40327058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_DOZE); 4033fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4034154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4035154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4036fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4037fcf5ef2aSThomas Huth } 4038fcf5ef2aSThomas Huth 4039fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4040fcf5ef2aSThomas Huth { 4041fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40429f0cf041SMatheus Ferst GEN_PRIV(ctx); 4043fcf5ef2aSThomas Huth #else 4044fcf5ef2aSThomas Huth TCGv_i32 t; 4045fcf5ef2aSThomas Huth 40469f0cf041SMatheus Ferst CHK_HV(ctx); 4047c32654afSNicholas Piggin translator_io_start(&ctx->base); 40487058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_NAP); 4049fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4050154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4051154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4052fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4053fcf5ef2aSThomas Huth } 4054fcf5ef2aSThomas Huth 4055cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4056cdee0e72SNikunj A Dadhania { 405721c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 40589f0cf041SMatheus Ferst GEN_PRIV(ctx); 405921c0d66aSBenjamin Herrenschmidt #else 406021c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 406121c0d66aSBenjamin Herrenschmidt 40629f0cf041SMatheus Ferst CHK_HV(ctx); 4063c32654afSNicholas Piggin translator_io_start(&ctx->base); 40647058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_STOP); 406521c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 406621c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 406721c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 406821c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4069cdee0e72SNikunj A Dadhania } 4070cdee0e72SNikunj A Dadhania 4071fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4072fcf5ef2aSThomas Huth { 4073fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40749f0cf041SMatheus Ferst GEN_PRIV(ctx); 4075fcf5ef2aSThomas Huth #else 4076fcf5ef2aSThomas Huth TCGv_i32 t; 4077fcf5ef2aSThomas Huth 40789f0cf041SMatheus Ferst CHK_HV(ctx); 4079c32654afSNicholas Piggin translator_io_start(&ctx->base); 40807058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_SLEEP); 4081fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4082154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4083154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4084fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4085fcf5ef2aSThomas Huth } 4086fcf5ef2aSThomas Huth 4087fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4088fcf5ef2aSThomas Huth { 4089fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40909f0cf041SMatheus Ferst GEN_PRIV(ctx); 4091fcf5ef2aSThomas Huth #else 4092fcf5ef2aSThomas Huth TCGv_i32 t; 4093fcf5ef2aSThomas Huth 40949f0cf041SMatheus Ferst CHK_HV(ctx); 4095c32654afSNicholas Piggin translator_io_start(&ctx->base); 40967058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_RVWINKLE); 4097fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4098154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4099154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4100fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4101fcf5ef2aSThomas Huth } 4102fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4103fcf5ef2aSThomas Huth 4104fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4105fcf5ef2aSThomas Huth { 4106fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4107efe843d8SDavid Gibson if (ctx->has_cfar) { 4108fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4109efe843d8SDavid Gibson } 4110fcf5ef2aSThomas Huth #endif 4111fcf5ef2aSThomas Huth } 4112fcf5ef2aSThomas Huth 411346d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 411446d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 411546d396bdSDaniel Henrique Barboza { 411646d396bdSDaniel Henrique Barboza /* 411746d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 411846d396bdSDaniel Henrique Barboza * instructions. 411946d396bdSDaniel Henrique Barboza */ 412046d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 412146d396bdSDaniel Henrique Barboza return; 412246d396bdSDaniel Henrique Barboza } 412346d396bdSDaniel Henrique Barboza 412446d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4125eeaaefe9SLeandro Lupori TCGLabel *l; 4126eeaaefe9SLeandro Lupori TCGv t0; 4127eeaaefe9SLeandro Lupori 412846d396bdSDaniel Henrique Barboza /* 412946d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 413046d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 413146d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 413246d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 413346d396bdSDaniel Henrique Barboza */ 4134283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 413546d396bdSDaniel Henrique Barboza 4136eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4137eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4138eeaaefe9SLeandro Lupori l = gen_new_label(); 4139eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4140eeaaefe9SLeandro Lupori 4141eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4142eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4143eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4144eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4145eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4146eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4147eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4148eeaaefe9SLeandro Lupori } 4149eeaaefe9SLeandro Lupori 4150eeaaefe9SLeandro Lupori gen_set_label(l); 4151eeaaefe9SLeandro Lupori } else { 415246d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4153eeaaefe9SLeandro Lupori } 415446d396bdSDaniel Henrique Barboza #else 415546d396bdSDaniel Henrique Barboza /* 415646d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 415746d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 415846d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 415946d396bdSDaniel Henrique Barboza */ 416046d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 416146d396bdSDaniel Henrique Barboza 416246d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 416346d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 416446d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 416546d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 416646d396bdSDaniel Henrique Barboza } 416746d396bdSDaniel Henrique Barboza #else 416846d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 416946d396bdSDaniel Henrique Barboza { 417046d396bdSDaniel Henrique Barboza return; 417146d396bdSDaniel Henrique Barboza } 417246d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 417346d396bdSDaniel Henrique Barboza 4174fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4175fcf5ef2aSThomas Huth { 41762e718e66SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 41772e718e66SRichard Henderson return false; 41782e718e66SRichard Henderson } 41796e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4180fcf5ef2aSThomas Huth } 4181fcf5ef2aSThomas Huth 41820e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 41830e3bf489SRoman Kapl { 41849498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 41850e3bf489SRoman Kapl gen_debug_exception(ctx); 41860e3bf489SRoman Kapl } else { 418746d396bdSDaniel Henrique Barboza /* 418846d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 418946d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 419046d396bdSDaniel Henrique Barboza */ 419146d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 419246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 419346d396bdSDaniel Henrique Barboza } 419446d396bdSDaniel Henrique Barboza 41950e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 41960e3bf489SRoman Kapl } 41970e3bf489SRoman Kapl } 41980e3bf489SRoman Kapl 4199fcf5ef2aSThomas Huth /*** Branch ***/ 4200c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4201fcf5ef2aSThomas Huth { 4202fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4203fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4204fcf5ef2aSThomas Huth } 4205fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 420646d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4207fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4208fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 420907ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4210fcf5ef2aSThomas Huth } else { 4211fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 42120e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4213fcf5ef2aSThomas Huth } 4214fcf5ef2aSThomas Huth } 4215fcf5ef2aSThomas Huth 4216fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4217fcf5ef2aSThomas Huth { 4218fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4219fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4220fcf5ef2aSThomas Huth } 4221fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4222fcf5ef2aSThomas Huth } 4223fcf5ef2aSThomas Huth 4224fcf5ef2aSThomas Huth /* b ba bl bla */ 4225fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4226fcf5ef2aSThomas Huth { 4227fcf5ef2aSThomas Huth target_ulong li, target; 4228fcf5ef2aSThomas Huth 4229fcf5ef2aSThomas Huth /* sign extend LI */ 4230fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4231fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4232fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42332c2bcb1bSRichard Henderson target = ctx->cia + li; 4234fcf5ef2aSThomas Huth } else { 4235fcf5ef2aSThomas Huth target = li; 4236fcf5ef2aSThomas Huth } 4237fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4238b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4239fcf5ef2aSThomas Huth } 42402c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4241fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 42426086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4243fcf5ef2aSThomas Huth } 4244fcf5ef2aSThomas Huth 4245fcf5ef2aSThomas Huth #define BCOND_IM 0 4246fcf5ef2aSThomas Huth #define BCOND_LR 1 4247fcf5ef2aSThomas Huth #define BCOND_CTR 2 4248fcf5ef2aSThomas Huth #define BCOND_TAR 3 4249fcf5ef2aSThomas Huth 4250c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4251fcf5ef2aSThomas Huth { 4252fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4253fcf5ef2aSThomas Huth TCGLabel *l1; 4254fcf5ef2aSThomas Huth TCGv target; 42550e3bf489SRoman Kapl 4256fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 42579723281fSRichard Henderson target = tcg_temp_new(); 4258efe843d8SDavid Gibson if (type == BCOND_CTR) { 4259fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4260efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4261fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4262efe843d8SDavid Gibson } else { 4263fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4264efe843d8SDavid Gibson } 4265fcf5ef2aSThomas Huth } else { 4266f764718dSRichard Henderson target = NULL; 4267fcf5ef2aSThomas Huth } 4268efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4269b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4270efe843d8SDavid Gibson } 4271fcf5ef2aSThomas Huth l1 = gen_new_label(); 4272fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4273fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4274fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4275fa200c95SGreg Kurz 4276fa200c95SGreg Kurz if (type == BCOND_CTR) { 4277fa200c95SGreg Kurz /* 4278fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4279fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4280fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 428115d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 428215d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 428315d68c5eSGreg Kurz * it basically useless and thus never used in real code. 428415d68c5eSGreg Kurz * 428515d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 428615d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 428715d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 428815d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 428915d68c5eSGreg Kurz * doing anything else harmful. 4290fa200c95SGreg Kurz */ 4291d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4292fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4293fcf5ef2aSThomas Huth return; 4294fcf5ef2aSThomas Huth } 4295fa200c95SGreg Kurz 4296fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4297fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4298fa200c95SGreg Kurz } else { 4299fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4300fa200c95SGreg Kurz } 4301fa200c95SGreg Kurz if (bo & 0x2) { 4302fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4303fa200c95SGreg Kurz } else { 4304fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4305fa200c95SGreg Kurz } 4306fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4307fa200c95SGreg Kurz } else { 4308fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4309fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4310fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4311fcf5ef2aSThomas Huth } else { 4312fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4313fcf5ef2aSThomas Huth } 4314fcf5ef2aSThomas Huth if (bo & 0x2) { 4315fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4316fcf5ef2aSThomas Huth } else { 4317fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4318fcf5ef2aSThomas Huth } 4319fa200c95SGreg Kurz } 4320fcf5ef2aSThomas Huth } 4321fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4322fcf5ef2aSThomas Huth /* Test CR */ 4323fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4324fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4325fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4326fcf5ef2aSThomas Huth 4327fcf5ef2aSThomas Huth if (bo & 0x8) { 4328fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4329fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4330fcf5ef2aSThomas Huth } else { 4331fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4332fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4333fcf5ef2aSThomas Huth } 4334fcf5ef2aSThomas Huth } 43352c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4336fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4337fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4338fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43392c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4340fcf5ef2aSThomas Huth } else { 4341fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4342fcf5ef2aSThomas Huth } 4343fcf5ef2aSThomas Huth } else { 4344fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4345fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4346fcf5ef2aSThomas Huth } else { 4347fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4348fcf5ef2aSThomas Huth } 43490e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4350c4a2e3a9SRichard Henderson } 4351fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 43520e3bf489SRoman Kapl /* fallthrough case */ 4353fcf5ef2aSThomas Huth gen_set_label(l1); 4354b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4355fcf5ef2aSThomas Huth } 43566086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4357fcf5ef2aSThomas Huth } 4358fcf5ef2aSThomas Huth 4359fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4360fcf5ef2aSThomas Huth { 4361fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4362fcf5ef2aSThomas Huth } 4363fcf5ef2aSThomas Huth 4364fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4365fcf5ef2aSThomas Huth { 4366fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4367fcf5ef2aSThomas Huth } 4368fcf5ef2aSThomas Huth 4369fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4370fcf5ef2aSThomas Huth { 4371fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4372fcf5ef2aSThomas Huth } 4373fcf5ef2aSThomas Huth 4374fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4375fcf5ef2aSThomas Huth { 4376fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4377fcf5ef2aSThomas Huth } 4378fcf5ef2aSThomas Huth 4379fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4380fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4381fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4382fcf5ef2aSThomas Huth { \ 4383fcf5ef2aSThomas Huth uint8_t bitmask; \ 4384fcf5ef2aSThomas Huth int sh; \ 4385fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4386fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4387fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4388fcf5ef2aSThomas Huth if (sh > 0) \ 4389fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4390fcf5ef2aSThomas Huth else if (sh < 0) \ 4391fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4392fcf5ef2aSThomas Huth else \ 4393fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4394fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4395fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4396fcf5ef2aSThomas Huth if (sh > 0) \ 4397fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4398fcf5ef2aSThomas Huth else if (sh < 0) \ 4399fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4400fcf5ef2aSThomas Huth else \ 4401fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4402fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4403fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4404fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4405fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4406fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4407fcf5ef2aSThomas Huth } 4408fcf5ef2aSThomas Huth 4409fcf5ef2aSThomas Huth /* crand */ 4410fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4411fcf5ef2aSThomas Huth /* crandc */ 4412fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4413fcf5ef2aSThomas Huth /* creqv */ 4414fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4415fcf5ef2aSThomas Huth /* crnand */ 4416fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4417fcf5ef2aSThomas Huth /* crnor */ 4418fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4419fcf5ef2aSThomas Huth /* cror */ 4420fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4421fcf5ef2aSThomas Huth /* crorc */ 4422fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4423fcf5ef2aSThomas Huth /* crxor */ 4424fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4425fcf5ef2aSThomas Huth 4426fcf5ef2aSThomas Huth /* mcrf */ 4427fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4428fcf5ef2aSThomas Huth { 4429fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4430fcf5ef2aSThomas Huth } 4431fcf5ef2aSThomas Huth 4432fcf5ef2aSThomas Huth /*** System linkage ***/ 4433fcf5ef2aSThomas Huth 4434fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4435fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4436fcf5ef2aSThomas Huth { 4437fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44389f0cf041SMatheus Ferst GEN_PRIV(ctx); 4439fcf5ef2aSThomas Huth #else 4440efe843d8SDavid Gibson /* 4441efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4442fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4443fcf5ef2aSThomas Huth */ 4444d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4445fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4446fcf5ef2aSThomas Huth return; 4447fcf5ef2aSThomas Huth } 4448fcf5ef2aSThomas Huth /* Restore CPU state */ 44499f0cf041SMatheus Ferst CHK_SV(ctx); 4450283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44512c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4452fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 445359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4454fcf5ef2aSThomas Huth #endif 4455fcf5ef2aSThomas Huth } 4456fcf5ef2aSThomas Huth 4457fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4458fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4459fcf5ef2aSThomas Huth { 4460fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44619f0cf041SMatheus Ferst GEN_PRIV(ctx); 4462fcf5ef2aSThomas Huth #else 4463fcf5ef2aSThomas Huth /* Restore CPU state */ 44649f0cf041SMatheus Ferst CHK_SV(ctx); 4465283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44662c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4467fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 446859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4469fcf5ef2aSThomas Huth #endif 4470fcf5ef2aSThomas Huth } 4471fcf5ef2aSThomas Huth 44723c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44733c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 44743c89b8d6SNicholas Piggin { 44753c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 44769f0cf041SMatheus Ferst GEN_PRIV(ctx); 44773c89b8d6SNicholas Piggin #else 44783c89b8d6SNicholas Piggin /* Restore CPU state */ 44799f0cf041SMatheus Ferst CHK_SV(ctx); 4480283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44812c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 44823c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 448359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 44843c89b8d6SNicholas Piggin #endif 44853c89b8d6SNicholas Piggin } 44863c89b8d6SNicholas Piggin #endif 44873c89b8d6SNicholas Piggin 4488fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4489fcf5ef2aSThomas Huth { 4490fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44919f0cf041SMatheus Ferst GEN_PRIV(ctx); 4492fcf5ef2aSThomas Huth #else 4493fcf5ef2aSThomas Huth /* Restore CPU state */ 44949f0cf041SMatheus Ferst CHK_HV(ctx); 4495c32654afSNicholas Piggin translator_io_start(&ctx->base); 4496fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 449759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4498fcf5ef2aSThomas Huth #endif 4499fcf5ef2aSThomas Huth } 4500fcf5ef2aSThomas Huth #endif 4501fcf5ef2aSThomas Huth 4502fcf5ef2aSThomas Huth /* sc */ 4503fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4504fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4505fcf5ef2aSThomas Huth #else 4506fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4507fcf5ef2aSThomas Huth #endif 4508fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4509fcf5ef2aSThomas Huth { 4510fcf5ef2aSThomas Huth uint32_t lev; 4511fcf5ef2aSThomas Huth 4512984eda58SNicholas Piggin /* 4513984eda58SNicholas Piggin * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4514984eda58SNicholas Piggin * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4515984eda58SNicholas Piggin * for Ultravisor which TCG does not support, so just ignore the top 6. 4516984eda58SNicholas Piggin */ 4517984eda58SNicholas Piggin lev = (ctx->opcode >> 5) & 0x1; 4518fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4519fcf5ef2aSThomas Huth } 4520fcf5ef2aSThomas Huth 45213c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 45223c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45233c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 45243c89b8d6SNicholas Piggin { 4525f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 45263c89b8d6SNicholas Piggin 4527f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 45282c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4529f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 45303c89b8d6SNicholas Piggin 45317a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 45323c89b8d6SNicholas Piggin } 45333c89b8d6SNicholas Piggin #endif 45343c89b8d6SNicholas Piggin #endif 45353c89b8d6SNicholas Piggin 4536fcf5ef2aSThomas Huth /*** Trap ***/ 4537fcf5ef2aSThomas Huth 4538fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4539fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4540fcf5ef2aSThomas Huth { 4541fcf5ef2aSThomas Huth /* Trap never */ 4542fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4543fcf5ef2aSThomas Huth return true; 4544fcf5ef2aSThomas Huth } 4545fcf5ef2aSThomas Huth /* Trap always */ 4546fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4547fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4548fcf5ef2aSThomas Huth return true; 4549fcf5ef2aSThomas Huth } 4550fcf5ef2aSThomas Huth return false; 4551fcf5ef2aSThomas Huth } 4552fcf5ef2aSThomas Huth 4553fcf5ef2aSThomas Huth /* tw */ 4554fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4555fcf5ef2aSThomas Huth { 4556fcf5ef2aSThomas Huth TCGv_i32 t0; 4557fcf5ef2aSThomas Huth 4558fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4559fcf5ef2aSThomas Huth return; 4560fcf5ef2aSThomas Huth } 45617058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4562fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4563fcf5ef2aSThomas Huth t0); 4564fcf5ef2aSThomas Huth } 4565fcf5ef2aSThomas Huth 4566fcf5ef2aSThomas Huth /* twi */ 4567fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4568fcf5ef2aSThomas Huth { 4569fcf5ef2aSThomas Huth TCGv t0; 4570fcf5ef2aSThomas Huth TCGv_i32 t1; 4571fcf5ef2aSThomas Huth 4572fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4573fcf5ef2aSThomas Huth return; 4574fcf5ef2aSThomas Huth } 45757058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45767058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4577fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4578fcf5ef2aSThomas Huth } 4579fcf5ef2aSThomas Huth 4580fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4581fcf5ef2aSThomas Huth /* td */ 4582fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4583fcf5ef2aSThomas Huth { 4584fcf5ef2aSThomas Huth TCGv_i32 t0; 4585fcf5ef2aSThomas Huth 4586fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4587fcf5ef2aSThomas Huth return; 4588fcf5ef2aSThomas Huth } 45897058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4590fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4591fcf5ef2aSThomas Huth t0); 4592fcf5ef2aSThomas Huth } 4593fcf5ef2aSThomas Huth 4594fcf5ef2aSThomas Huth /* tdi */ 4595fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4596fcf5ef2aSThomas Huth { 4597fcf5ef2aSThomas Huth TCGv t0; 4598fcf5ef2aSThomas Huth TCGv_i32 t1; 4599fcf5ef2aSThomas Huth 4600fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4601fcf5ef2aSThomas Huth return; 4602fcf5ef2aSThomas Huth } 46037058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 46047058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4605fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4606fcf5ef2aSThomas Huth } 4607fcf5ef2aSThomas Huth #endif 4608fcf5ef2aSThomas Huth 4609fcf5ef2aSThomas Huth /*** Processor control ***/ 4610fcf5ef2aSThomas Huth 4611fcf5ef2aSThomas Huth /* mcrxr */ 4612fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4613fcf5ef2aSThomas Huth { 4614fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4615fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4616fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4617fcf5ef2aSThomas Huth 4618fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4619fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4620fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4621fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4622fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4623fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4624fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4625fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4626fcf5ef2aSThomas Huth 4627fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4628fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4629fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4630fcf5ef2aSThomas Huth } 4631fcf5ef2aSThomas Huth 4632b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4633b63d0434SNikunj A Dadhania /* mcrxrx */ 4634b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4635b63d0434SNikunj A Dadhania { 4636b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4637b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4638b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4639b63d0434SNikunj A Dadhania 4640b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4641b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4642b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4643b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4644b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4645b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4646b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4647b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4648b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4649b63d0434SNikunj A Dadhania } 4650b63d0434SNikunj A Dadhania #endif 4651b63d0434SNikunj A Dadhania 4652fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4653fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4654fcf5ef2aSThomas Huth { 4655fcf5ef2aSThomas Huth uint32_t crm, crn; 4656fcf5ef2aSThomas Huth 4657fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4658fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4659fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4660fcf5ef2aSThomas Huth crn = ctz32(crm); 4661fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4662fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4663fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4664fcf5ef2aSThomas Huth } 4665fcf5ef2aSThomas Huth } else { 4666fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4667fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4668fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4669fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4670fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4671fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4672fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4673fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4674fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4675fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4676fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4677fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4678fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4679fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4680fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4681fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4682fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4683fcf5ef2aSThomas Huth } 4684fcf5ef2aSThomas Huth } 4685fcf5ef2aSThomas Huth 4686fcf5ef2aSThomas Huth /* mfmsr */ 4687fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4688fcf5ef2aSThomas Huth { 46899f0cf041SMatheus Ferst CHK_SV(ctx); 4690fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4691fcf5ef2aSThomas Huth } 4692fcf5ef2aSThomas Huth 4693fcf5ef2aSThomas Huth /* mfspr */ 4694fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4695fcf5ef2aSThomas Huth { 4696fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4697fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4698fcf5ef2aSThomas Huth 4699fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4700fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4701fcf5ef2aSThomas Huth #else 4702fcf5ef2aSThomas Huth if (ctx->pr) { 4703fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4704fcf5ef2aSThomas Huth } else if (ctx->hv) { 4705fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4706fcf5ef2aSThomas Huth } else { 4707fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4708fcf5ef2aSThomas Huth } 4709fcf5ef2aSThomas Huth #endif 4710fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4711fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4712fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4713fcf5ef2aSThomas Huth } else { 4714fcf5ef2aSThomas Huth /* Privilege exception */ 4715efe843d8SDavid Gibson /* 4716efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4717fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4718fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4719fcf5ef2aSThomas Huth */ 4720fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 472131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 472231085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 47232c2bcb1bSRichard Henderson ctx->cia); 4724fcf5ef2aSThomas Huth } 4725fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4726fcf5ef2aSThomas Huth } 4727fcf5ef2aSThomas Huth } else { 4728fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4729fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4730fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4731fcf5ef2aSThomas Huth /* This is a nop */ 4732fcf5ef2aSThomas Huth return; 4733fcf5ef2aSThomas Huth } 4734fcf5ef2aSThomas Huth /* Not defined */ 473531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 473631085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 47372c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4738fcf5ef2aSThomas Huth 4739efe843d8SDavid Gibson /* 4740efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4741efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4742fcf5ef2aSThomas Huth */ 4743fcf5ef2aSThomas Huth if (sprn & 0x10) { 4744fcf5ef2aSThomas Huth if (ctx->pr) { 47451315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4746fcf5ef2aSThomas Huth } 4747fcf5ef2aSThomas Huth } else { 4748fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 47491315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4750fcf5ef2aSThomas Huth } 4751fcf5ef2aSThomas Huth } 4752fcf5ef2aSThomas Huth } 4753fcf5ef2aSThomas Huth } 4754fcf5ef2aSThomas Huth 4755fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4756fcf5ef2aSThomas Huth { 4757fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4758fcf5ef2aSThomas Huth } 4759fcf5ef2aSThomas Huth 4760fcf5ef2aSThomas Huth /* mftb */ 4761fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4762fcf5ef2aSThomas Huth { 4763fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4764fcf5ef2aSThomas Huth } 4765fcf5ef2aSThomas Huth 4766fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4767fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4768fcf5ef2aSThomas Huth { 4769fcf5ef2aSThomas Huth uint32_t crm, crn; 4770fcf5ef2aSThomas Huth 4771fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4772fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4773fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4774fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4775fcf5ef2aSThomas Huth crn = ctz32(crm); 4776fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4777fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4778fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4779fcf5ef2aSThomas Huth } 4780fcf5ef2aSThomas Huth } else { 4781fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4782fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4783fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4784fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4785fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4786fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4787fcf5ef2aSThomas Huth } 4788fcf5ef2aSThomas Huth } 4789fcf5ef2aSThomas Huth } 4790fcf5ef2aSThomas Huth } 4791fcf5ef2aSThomas Huth 4792fcf5ef2aSThomas Huth /* mtmsr */ 4793fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4794fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4795fcf5ef2aSThomas Huth { 4796caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4797caf590ddSNicholas Piggin gen_invalid(ctx); 4798caf590ddSNicholas Piggin return; 4799caf590ddSNicholas Piggin } 4800caf590ddSNicholas Piggin 48019f0cf041SMatheus Ferst CHK_SV(ctx); 4802fcf5ef2aSThomas Huth 4803fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48046fa5726bSMatheus Ferst TCGv t0, t1; 48056fa5726bSMatheus Ferst target_ulong mask; 48066fa5726bSMatheus Ferst 48076fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48086fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48096fa5726bSMatheus Ferst 4810283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 48116fa5726bSMatheus Ferst 4812fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48135ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48146fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4815fcf5ef2aSThomas Huth } else { 48166fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 48176fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 48186fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4819efe843d8SDavid Gibson /* 4820efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4821efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4822efe843d8SDavid Gibson * ppc_store_msr 4823fcf5ef2aSThomas Huth */ 4824b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4825fcf5ef2aSThomas Huth } 48266fa5726bSMatheus Ferst 48276fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48286fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48296fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48306fa5726bSMatheus Ferst 48316fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48326fa5726bSMatheus Ferst 48335ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4834d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4835fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4836fcf5ef2aSThomas Huth } 4837fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4838fcf5ef2aSThomas Huth 4839fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4840fcf5ef2aSThomas Huth { 48419f0cf041SMatheus Ferst CHK_SV(ctx); 4842fcf5ef2aSThomas Huth 4843fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48446fa5726bSMatheus Ferst TCGv t0, t1; 48456fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 48466fa5726bSMatheus Ferst 48476fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48486fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48496fa5726bSMatheus Ferst 4850283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 4851fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48525ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48536fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4854fcf5ef2aSThomas Huth } else { 48556fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 48566fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4857fcf5ef2aSThomas Huth 4858efe843d8SDavid Gibson /* 4859efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4860efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4861efe843d8SDavid Gibson * ppc_store_msr 4862fcf5ef2aSThomas Huth */ 4863b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4864fcf5ef2aSThomas Huth } 48656fa5726bSMatheus Ferst 48666fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48676fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48686fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48696fa5726bSMatheus Ferst 48706fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48716fa5726bSMatheus Ferst 48725ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4873d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4874fcf5ef2aSThomas Huth #endif 4875fcf5ef2aSThomas Huth } 4876fcf5ef2aSThomas Huth 4877fcf5ef2aSThomas Huth /* mtspr */ 4878fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4879fcf5ef2aSThomas Huth { 4880fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4881fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4882fcf5ef2aSThomas Huth 4883fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4884fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4885fcf5ef2aSThomas Huth #else 4886fcf5ef2aSThomas Huth if (ctx->pr) { 4887fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4888fcf5ef2aSThomas Huth } else if (ctx->hv) { 4889fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4890fcf5ef2aSThomas Huth } else { 4891fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4892fcf5ef2aSThomas Huth } 4893fcf5ef2aSThomas Huth #endif 4894fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4895fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4896fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4897fcf5ef2aSThomas Huth } else { 4898fcf5ef2aSThomas Huth /* Privilege exception */ 489931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 490031085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 49012c2bcb1bSRichard Henderson ctx->cia); 4902fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4903fcf5ef2aSThomas Huth } 4904fcf5ef2aSThomas Huth } else { 4905fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4906fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4907fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4908fcf5ef2aSThomas Huth /* This is a nop */ 4909fcf5ef2aSThomas Huth return; 4910fcf5ef2aSThomas Huth } 4911fcf5ef2aSThomas Huth 4912fcf5ef2aSThomas Huth /* Not defined */ 491331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 491431085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 49152c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4916fcf5ef2aSThomas Huth 4917fcf5ef2aSThomas Huth 4918efe843d8SDavid Gibson /* 4919efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4920efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4921fcf5ef2aSThomas Huth */ 4922fcf5ef2aSThomas Huth if (sprn & 0x10) { 4923fcf5ef2aSThomas Huth if (ctx->pr) { 49241315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4925fcf5ef2aSThomas Huth } 4926fcf5ef2aSThomas Huth } else { 4927fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 49281315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4929fcf5ef2aSThomas Huth } 4930fcf5ef2aSThomas Huth } 4931fcf5ef2aSThomas Huth } 4932fcf5ef2aSThomas Huth } 4933fcf5ef2aSThomas Huth 4934fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4935fcf5ef2aSThomas Huth /* setb */ 4936fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4937fcf5ef2aSThomas Huth { 4938fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 49396f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 49406f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 4941fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4942fcf5ef2aSThomas Huth 4943fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4944fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4945fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4946fcf5ef2aSThomas Huth } 4947fcf5ef2aSThomas Huth #endif 4948fcf5ef2aSThomas Huth 4949fcf5ef2aSThomas Huth /*** Cache management ***/ 4950fcf5ef2aSThomas Huth 4951fcf5ef2aSThomas Huth /* dcbf */ 4952fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4953fcf5ef2aSThomas Huth { 4954fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4955fcf5ef2aSThomas Huth TCGv t0; 4956fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4957fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4958fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4959fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4960fcf5ef2aSThomas Huth } 4961fcf5ef2aSThomas Huth 496250728199SRoman Kapl /* dcbfep (external PID dcbf) */ 496350728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 496450728199SRoman Kapl { 496550728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 496650728199SRoman Kapl TCGv t0; 49679f0cf041SMatheus Ferst CHK_SV(ctx); 496850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 496950728199SRoman Kapl t0 = tcg_temp_new(); 497050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 497150728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 497250728199SRoman Kapl } 497350728199SRoman Kapl 4974fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4975fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4976fcf5ef2aSThomas Huth { 4977fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 49789f0cf041SMatheus Ferst GEN_PRIV(ctx); 4979fcf5ef2aSThomas Huth #else 4980fcf5ef2aSThomas Huth TCGv EA, val; 4981fcf5ef2aSThomas Huth 49829f0cf041SMatheus Ferst CHK_SV(ctx); 4983fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4984fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4985fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4986fcf5ef2aSThomas Huth val = tcg_temp_new(); 4987fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4988fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4989fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4990fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4991fcf5ef2aSThomas Huth } 4992fcf5ef2aSThomas Huth 4993fcf5ef2aSThomas Huth /* dcdst */ 4994fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4995fcf5ef2aSThomas Huth { 4996fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4997fcf5ef2aSThomas Huth TCGv t0; 4998fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4999fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5000fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5001fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5002fcf5ef2aSThomas Huth } 5003fcf5ef2aSThomas Huth 500450728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 500550728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 500650728199SRoman Kapl { 500750728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 500850728199SRoman Kapl TCGv t0; 500950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 501050728199SRoman Kapl t0 = tcg_temp_new(); 501150728199SRoman Kapl gen_addr_reg_index(ctx, t0); 501250728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 501350728199SRoman Kapl } 501450728199SRoman Kapl 5015fcf5ef2aSThomas Huth /* dcbt */ 5016fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5017fcf5ef2aSThomas Huth { 5018efe843d8SDavid Gibson /* 5019efe843d8SDavid Gibson * interpreted as no-op 5020efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5021efe843d8SDavid Gibson * does not generate any exception 5022fcf5ef2aSThomas Huth */ 5023fcf5ef2aSThomas Huth } 5024fcf5ef2aSThomas Huth 502550728199SRoman Kapl /* dcbtep */ 502650728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 502750728199SRoman Kapl { 5028efe843d8SDavid Gibson /* 5029efe843d8SDavid Gibson * interpreted as no-op 5030efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5031efe843d8SDavid Gibson * does not generate any exception 503250728199SRoman Kapl */ 503350728199SRoman Kapl } 503450728199SRoman Kapl 5035fcf5ef2aSThomas Huth /* dcbtst */ 5036fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5037fcf5ef2aSThomas Huth { 5038efe843d8SDavid Gibson /* 5039efe843d8SDavid Gibson * interpreted as no-op 5040efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5041efe843d8SDavid Gibson * does not generate any exception 5042fcf5ef2aSThomas Huth */ 5043fcf5ef2aSThomas Huth } 5044fcf5ef2aSThomas Huth 504550728199SRoman Kapl /* dcbtstep */ 504650728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 504750728199SRoman Kapl { 5048efe843d8SDavid Gibson /* 5049efe843d8SDavid Gibson * interpreted as no-op 5050efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5051efe843d8SDavid Gibson * does not generate any exception 505250728199SRoman Kapl */ 505350728199SRoman Kapl } 505450728199SRoman Kapl 5055fcf5ef2aSThomas Huth /* dcbtls */ 5056fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5057fcf5ef2aSThomas Huth { 5058fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5059fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5060fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5061fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5062fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5063fcf5ef2aSThomas Huth } 5064fcf5ef2aSThomas Huth 5065e64645baSBernhard Beschow /* dcblc */ 5066e64645baSBernhard Beschow static void gen_dcblc(DisasContext *ctx) 5067e64645baSBernhard Beschow { 5068e64645baSBernhard Beschow /* 5069e64645baSBernhard Beschow * interpreted as no-op 5070e64645baSBernhard Beschow */ 5071e64645baSBernhard Beschow } 5072e64645baSBernhard Beschow 5073fcf5ef2aSThomas Huth /* dcbz */ 5074fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5075fcf5ef2aSThomas Huth { 5076fcf5ef2aSThomas Huth TCGv tcgv_addr; 5077fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5078fcf5ef2aSThomas Huth 5079fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5080fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 50817058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5082fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5083fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5084fcf5ef2aSThomas Huth } 5085fcf5ef2aSThomas Huth 508650728199SRoman Kapl /* dcbzep */ 508750728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 508850728199SRoman Kapl { 508950728199SRoman Kapl TCGv tcgv_addr; 509050728199SRoman Kapl TCGv_i32 tcgv_op; 509150728199SRoman Kapl 509250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 509350728199SRoman Kapl tcgv_addr = tcg_temp_new(); 50947058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 509550728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 509650728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 509750728199SRoman Kapl } 509850728199SRoman Kapl 5099fcf5ef2aSThomas Huth /* dst / dstt */ 5100fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5101fcf5ef2aSThomas Huth { 5102fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5103fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5104fcf5ef2aSThomas Huth } else { 5105fcf5ef2aSThomas Huth /* interpreted as no-op */ 5106fcf5ef2aSThomas Huth } 5107fcf5ef2aSThomas Huth } 5108fcf5ef2aSThomas Huth 5109fcf5ef2aSThomas Huth /* dstst /dststt */ 5110fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5111fcf5ef2aSThomas Huth { 5112fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5113fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5114fcf5ef2aSThomas Huth } else { 5115fcf5ef2aSThomas Huth /* interpreted as no-op */ 5116fcf5ef2aSThomas Huth } 5117fcf5ef2aSThomas Huth 5118fcf5ef2aSThomas Huth } 5119fcf5ef2aSThomas Huth 5120fcf5ef2aSThomas Huth /* dss / dssall */ 5121fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5122fcf5ef2aSThomas Huth { 5123fcf5ef2aSThomas Huth /* interpreted as no-op */ 5124fcf5ef2aSThomas Huth } 5125fcf5ef2aSThomas Huth 5126fcf5ef2aSThomas Huth /* icbi */ 5127fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5128fcf5ef2aSThomas Huth { 5129fcf5ef2aSThomas Huth TCGv t0; 5130fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5131fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5132fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5133fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5134fcf5ef2aSThomas Huth } 5135fcf5ef2aSThomas Huth 513650728199SRoman Kapl /* icbiep */ 513750728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 513850728199SRoman Kapl { 513950728199SRoman Kapl TCGv t0; 514050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 514150728199SRoman Kapl t0 = tcg_temp_new(); 514250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 514350728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 514450728199SRoman Kapl } 514550728199SRoman Kapl 5146fcf5ef2aSThomas Huth /* Optional: */ 5147fcf5ef2aSThomas Huth /* dcba */ 5148fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5149fcf5ef2aSThomas Huth { 5150efe843d8SDavid Gibson /* 5151efe843d8SDavid Gibson * interpreted as no-op 5152efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5153fcf5ef2aSThomas Huth * but does not generate any exception 5154fcf5ef2aSThomas Huth */ 5155fcf5ef2aSThomas Huth } 5156fcf5ef2aSThomas Huth 5157fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5158fcf5ef2aSThomas Huth /* Supervisor only: */ 5159fcf5ef2aSThomas Huth 5160fcf5ef2aSThomas Huth /* mfsr */ 5161fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5162fcf5ef2aSThomas Huth { 5163fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5165fcf5ef2aSThomas Huth #else 5166fcf5ef2aSThomas Huth TCGv t0; 5167fcf5ef2aSThomas Huth 51689f0cf041SMatheus Ferst CHK_SV(ctx); 51697058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5170fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5171fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5172fcf5ef2aSThomas Huth } 5173fcf5ef2aSThomas Huth 5174fcf5ef2aSThomas Huth /* mfsrin */ 5175fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5176fcf5ef2aSThomas Huth { 5177fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51789f0cf041SMatheus Ferst GEN_PRIV(ctx); 5179fcf5ef2aSThomas Huth #else 5180fcf5ef2aSThomas Huth TCGv t0; 5181fcf5ef2aSThomas Huth 51829f0cf041SMatheus Ferst CHK_SV(ctx); 5183fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5184e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5185fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5186fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5187fcf5ef2aSThomas Huth } 5188fcf5ef2aSThomas Huth 5189fcf5ef2aSThomas Huth /* mtsr */ 5190fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5191fcf5ef2aSThomas Huth { 5192fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51939f0cf041SMatheus Ferst GEN_PRIV(ctx); 5194fcf5ef2aSThomas Huth #else 5195fcf5ef2aSThomas Huth TCGv t0; 5196fcf5ef2aSThomas Huth 51979f0cf041SMatheus Ferst CHK_SV(ctx); 51987058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5199fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5200fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5201fcf5ef2aSThomas Huth } 5202fcf5ef2aSThomas Huth 5203fcf5ef2aSThomas Huth /* mtsrin */ 5204fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5205fcf5ef2aSThomas Huth { 5206fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52079f0cf041SMatheus Ferst GEN_PRIV(ctx); 5208fcf5ef2aSThomas Huth #else 5209fcf5ef2aSThomas Huth TCGv t0; 52109f0cf041SMatheus Ferst CHK_SV(ctx); 5211fcf5ef2aSThomas Huth 5212fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5213e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5214fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5215fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5216fcf5ef2aSThomas Huth } 5217fcf5ef2aSThomas Huth 5218fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5219fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5220fcf5ef2aSThomas Huth 5221fcf5ef2aSThomas Huth /* mfsr */ 5222fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5223fcf5ef2aSThomas Huth { 5224fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52259f0cf041SMatheus Ferst GEN_PRIV(ctx); 5226fcf5ef2aSThomas Huth #else 5227fcf5ef2aSThomas Huth TCGv t0; 5228fcf5ef2aSThomas Huth 52299f0cf041SMatheus Ferst CHK_SV(ctx); 52307058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5231fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5232fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5233fcf5ef2aSThomas Huth } 5234fcf5ef2aSThomas Huth 5235fcf5ef2aSThomas Huth /* mfsrin */ 5236fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5237fcf5ef2aSThomas Huth { 5238fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52399f0cf041SMatheus Ferst GEN_PRIV(ctx); 5240fcf5ef2aSThomas Huth #else 5241fcf5ef2aSThomas Huth TCGv t0; 5242fcf5ef2aSThomas Huth 52439f0cf041SMatheus Ferst CHK_SV(ctx); 5244fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5245e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5246fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5247fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5248fcf5ef2aSThomas Huth } 5249fcf5ef2aSThomas Huth 5250fcf5ef2aSThomas Huth /* mtsr */ 5251fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5252fcf5ef2aSThomas Huth { 5253fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52549f0cf041SMatheus Ferst GEN_PRIV(ctx); 5255fcf5ef2aSThomas Huth #else 5256fcf5ef2aSThomas Huth TCGv t0; 5257fcf5ef2aSThomas Huth 52589f0cf041SMatheus Ferst CHK_SV(ctx); 52597058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5260fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5261fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5262fcf5ef2aSThomas Huth } 5263fcf5ef2aSThomas Huth 5264fcf5ef2aSThomas Huth /* mtsrin */ 5265fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5266fcf5ef2aSThomas Huth { 5267fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52689f0cf041SMatheus Ferst GEN_PRIV(ctx); 5269fcf5ef2aSThomas Huth #else 5270fcf5ef2aSThomas Huth TCGv t0; 5271fcf5ef2aSThomas Huth 52729f0cf041SMatheus Ferst CHK_SV(ctx); 5273fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5274e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5275fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5276fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5277fcf5ef2aSThomas Huth } 5278fcf5ef2aSThomas Huth 5279fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5280fcf5ef2aSThomas Huth 5281fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5282fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5283fcf5ef2aSThomas Huth 5284fcf5ef2aSThomas Huth /* tlbia */ 5285fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5286fcf5ef2aSThomas Huth { 5287fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52889f0cf041SMatheus Ferst GEN_PRIV(ctx); 5289fcf5ef2aSThomas Huth #else 52909f0cf041SMatheus Ferst CHK_HV(ctx); 5291fcf5ef2aSThomas Huth 5292fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5293fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5294fcf5ef2aSThomas Huth } 5295fcf5ef2aSThomas Huth 5296fcf5ef2aSThomas Huth /* tlbsync */ 5297fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5298fcf5ef2aSThomas Huth { 5299fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53009f0cf041SMatheus Ferst GEN_PRIV(ctx); 5301fcf5ef2aSThomas Huth #else 530291c60f12SCédric Le Goater 530391c60f12SCédric Le Goater if (ctx->gtse) { 53049f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 530591c60f12SCédric Le Goater } else { 53069f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 530791c60f12SCédric Le Goater } 5308fcf5ef2aSThomas Huth 5309fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5310fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5311fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5312fcf5ef2aSThomas Huth } 5313fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5314fcf5ef2aSThomas Huth } 5315fcf5ef2aSThomas Huth 5316fcf5ef2aSThomas Huth /*** External control ***/ 5317fcf5ef2aSThomas Huth /* Optional: */ 5318fcf5ef2aSThomas Huth 5319fcf5ef2aSThomas Huth /* eciwx */ 5320fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5321fcf5ef2aSThomas Huth { 5322fcf5ef2aSThomas Huth TCGv t0; 5323fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5324fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5325fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5326fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5327c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5328c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5329fcf5ef2aSThomas Huth } 5330fcf5ef2aSThomas Huth 5331fcf5ef2aSThomas Huth /* ecowx */ 5332fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5333fcf5ef2aSThomas Huth { 5334fcf5ef2aSThomas Huth TCGv t0; 5335fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5336fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5337fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5338fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5339c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5340c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5341fcf5ef2aSThomas Huth } 5342fcf5ef2aSThomas Huth 5343fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5344fcf5ef2aSThomas Huth 5345fcf5ef2aSThomas Huth /* tlbld */ 5346fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5347fcf5ef2aSThomas Huth { 5348fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53499f0cf041SMatheus Ferst GEN_PRIV(ctx); 5350fcf5ef2aSThomas Huth #else 53519f0cf041SMatheus Ferst CHK_SV(ctx); 5352fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5353fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5354fcf5ef2aSThomas Huth } 5355fcf5ef2aSThomas Huth 5356fcf5ef2aSThomas Huth /* tlbli */ 5357fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5358fcf5ef2aSThomas Huth { 5359fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53609f0cf041SMatheus Ferst GEN_PRIV(ctx); 5361fcf5ef2aSThomas Huth #else 53629f0cf041SMatheus Ferst CHK_SV(ctx); 5363fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5365fcf5ef2aSThomas Huth } 5366fcf5ef2aSThomas Huth 5367fcf5ef2aSThomas Huth /* BookE specific instructions */ 5368fcf5ef2aSThomas Huth 5369fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5370fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5371fcf5ef2aSThomas Huth { 5372fcf5ef2aSThomas Huth /* XXX: TODO */ 5373fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5374fcf5ef2aSThomas Huth } 5375fcf5ef2aSThomas Huth 5376fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5377fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5378fcf5ef2aSThomas Huth { 5379fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53809f0cf041SMatheus Ferst GEN_PRIV(ctx); 5381fcf5ef2aSThomas Huth #else 5382fcf5ef2aSThomas Huth TCGv t0; 5383fcf5ef2aSThomas Huth 53849f0cf041SMatheus Ferst CHK_SV(ctx); 5385fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5386fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5387fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5388fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5389fcf5ef2aSThomas Huth } 5390fcf5ef2aSThomas Huth 5391fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5392fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5393fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5394fcf5ef2aSThomas Huth { 5395fcf5ef2aSThomas Huth TCGv t0, t1; 5396fcf5ef2aSThomas Huth 53979723281fSRichard Henderson t0 = tcg_temp_new(); 53989723281fSRichard Henderson t1 = tcg_temp_new(); 5399fcf5ef2aSThomas Huth 5400fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5401fcf5ef2aSThomas Huth case 0x05: 5402fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5403fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5404fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5405fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5406fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5407fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5408fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5409fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5410fcf5ef2aSThomas Huth break; 5411fcf5ef2aSThomas Huth case 0x04: 5412fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5413fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5414fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5415fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5416fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5417fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5418fcf5ef2aSThomas Huth break; 5419fcf5ef2aSThomas Huth case 0x01: 5420fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5421fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5422fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5423fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5424fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5425fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5426fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5427fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5428fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5429fcf5ef2aSThomas Huth break; 5430fcf5ef2aSThomas Huth case 0x00: 5431fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5432fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5433fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5434fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5435fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5436fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5437fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5438fcf5ef2aSThomas Huth break; 5439fcf5ef2aSThomas Huth case 0x0D: 5440fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5441fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5442fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5443fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5444fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5445fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5446fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5447fcf5ef2aSThomas Huth break; 5448fcf5ef2aSThomas Huth case 0x0C: 5449fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5450fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5451fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5452fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5453fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5454fcf5ef2aSThomas Huth break; 5455fcf5ef2aSThomas Huth } 5456fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5457fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5458fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5459fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5460fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5461fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5462fcf5ef2aSThomas Huth } else { 5463fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5464fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5465fcf5ef2aSThomas Huth } 5466fcf5ef2aSThomas Huth 5467fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5468fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5469fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5470fcf5ef2aSThomas Huth 5471fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5472fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5473fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5474fcf5ef2aSThomas Huth } 5475fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5476fcf5ef2aSThomas Huth /* Signed */ 5477fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5478fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5479fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5480fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5481fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5482fcf5ef2aSThomas Huth /* Saturate */ 5483fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5484fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5485fcf5ef2aSThomas Huth } 5486fcf5ef2aSThomas Huth } else { 5487fcf5ef2aSThomas Huth /* Unsigned */ 5488fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5489fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5490fcf5ef2aSThomas Huth /* Saturate */ 5491fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5492fcf5ef2aSThomas Huth } 5493fcf5ef2aSThomas Huth } 5494fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5495fcf5ef2aSThomas Huth /* Check overflow */ 5496fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5497fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5498fcf5ef2aSThomas Huth } 5499fcf5ef2aSThomas Huth gen_set_label(l1); 5500fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5501fcf5ef2aSThomas Huth } 5502fcf5ef2aSThomas Huth } else { 5503fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5504fcf5ef2aSThomas Huth } 5505fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5506fcf5ef2aSThomas Huth /* Update Rc0 */ 5507fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5508fcf5ef2aSThomas Huth } 5509fcf5ef2aSThomas Huth } 5510fcf5ef2aSThomas Huth 5511fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5512fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5513fcf5ef2aSThomas Huth { \ 5514fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5515fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5516fcf5ef2aSThomas Huth } 5517fcf5ef2aSThomas Huth 5518fcf5ef2aSThomas Huth /* macchw - macchw. */ 5519fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5520fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5521fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5522fcf5ef2aSThomas Huth /* macchws - macchws. */ 5523fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5524fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5525fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5526fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5527fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5528fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5529fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5530fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5531fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5532fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5533fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5534fcf5ef2aSThomas Huth /* machhw - machhw. */ 5535fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5536fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5537fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5538fcf5ef2aSThomas Huth /* machhws - machhws. */ 5539fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5540fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5541fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5542fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5543fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5544fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5545fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5546fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5547fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5548fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5550fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5552fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5554fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5556fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5558fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5560fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5562fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5564fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5566fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5568fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5570fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5572fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5574fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5576fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5578fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5580fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5582fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5583fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5584fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5585fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5586fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5587fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5588fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5589fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5590fcf5ef2aSThomas Huth 5591fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5592fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5593fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5594fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5595fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5596fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5597fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5598fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5599fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5600fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5601fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5602fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5603fcf5ef2aSThomas Huth 5604fcf5ef2aSThomas Huth /* mfdcr */ 5605fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5606fcf5ef2aSThomas Huth { 5607fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56089f0cf041SMatheus Ferst GEN_PRIV(ctx); 5609fcf5ef2aSThomas Huth #else 5610fcf5ef2aSThomas Huth TCGv dcrn; 5611fcf5ef2aSThomas Huth 56129f0cf041SMatheus Ferst CHK_SV(ctx); 56137058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5614fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5615fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5616fcf5ef2aSThomas Huth } 5617fcf5ef2aSThomas Huth 5618fcf5ef2aSThomas Huth /* mtdcr */ 5619fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5620fcf5ef2aSThomas Huth { 5621fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56229f0cf041SMatheus Ferst GEN_PRIV(ctx); 5623fcf5ef2aSThomas Huth #else 5624fcf5ef2aSThomas Huth TCGv dcrn; 5625fcf5ef2aSThomas Huth 56269f0cf041SMatheus Ferst CHK_SV(ctx); 56277058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5628fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5629fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5630fcf5ef2aSThomas Huth } 5631fcf5ef2aSThomas Huth 5632fcf5ef2aSThomas Huth /* mfdcrx */ 5633fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5634fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5635fcf5ef2aSThomas Huth { 5636fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56379f0cf041SMatheus Ferst GEN_PRIV(ctx); 5638fcf5ef2aSThomas Huth #else 56399f0cf041SMatheus Ferst CHK_SV(ctx); 5640fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5641fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5642fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5643fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5644fcf5ef2aSThomas Huth } 5645fcf5ef2aSThomas Huth 5646fcf5ef2aSThomas Huth /* mtdcrx */ 5647fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5648fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5649fcf5ef2aSThomas Huth { 5650fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56519f0cf041SMatheus Ferst GEN_PRIV(ctx); 5652fcf5ef2aSThomas Huth #else 56539f0cf041SMatheus Ferst CHK_SV(ctx); 5654fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5655fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5656fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5657fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5658fcf5ef2aSThomas Huth } 5659fcf5ef2aSThomas Huth 5660fcf5ef2aSThomas Huth /* dccci */ 5661fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5662fcf5ef2aSThomas Huth { 56639f0cf041SMatheus Ferst CHK_SV(ctx); 5664fcf5ef2aSThomas Huth /* interpreted as no-op */ 5665fcf5ef2aSThomas Huth } 5666fcf5ef2aSThomas Huth 5667fcf5ef2aSThomas Huth /* dcread */ 5668fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5669fcf5ef2aSThomas Huth { 5670fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56719f0cf041SMatheus Ferst GEN_PRIV(ctx); 5672fcf5ef2aSThomas Huth #else 5673fcf5ef2aSThomas Huth TCGv EA, val; 5674fcf5ef2aSThomas Huth 56759f0cf041SMatheus Ferst CHK_SV(ctx); 5676fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5677fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5678fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5679fcf5ef2aSThomas Huth val = tcg_temp_new(); 5680fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5681fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5682fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5683fcf5ef2aSThomas Huth } 5684fcf5ef2aSThomas Huth 5685fcf5ef2aSThomas Huth /* icbt */ 5686fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5687fcf5ef2aSThomas Huth { 5688efe843d8SDavid Gibson /* 5689efe843d8SDavid Gibson * interpreted as no-op 5690efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5691efe843d8SDavid Gibson * does not generate any exception 5692fcf5ef2aSThomas Huth */ 5693fcf5ef2aSThomas Huth } 5694fcf5ef2aSThomas Huth 5695fcf5ef2aSThomas Huth /* iccci */ 5696fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5697fcf5ef2aSThomas Huth { 56989f0cf041SMatheus Ferst CHK_SV(ctx); 5699fcf5ef2aSThomas Huth /* interpreted as no-op */ 5700fcf5ef2aSThomas Huth } 5701fcf5ef2aSThomas Huth 5702fcf5ef2aSThomas Huth /* icread */ 5703fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5704fcf5ef2aSThomas Huth { 57059f0cf041SMatheus Ferst CHK_SV(ctx); 5706fcf5ef2aSThomas Huth /* interpreted as no-op */ 5707fcf5ef2aSThomas Huth } 5708fcf5ef2aSThomas Huth 5709fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5710fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5711fcf5ef2aSThomas Huth { 5712fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57139f0cf041SMatheus Ferst GEN_PRIV(ctx); 5714fcf5ef2aSThomas Huth #else 57159f0cf041SMatheus Ferst CHK_SV(ctx); 5716fcf5ef2aSThomas Huth /* Restore CPU state */ 5717fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 571859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5719fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5720fcf5ef2aSThomas Huth } 5721fcf5ef2aSThomas Huth 5722fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5723fcf5ef2aSThomas Huth { 5724fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57259f0cf041SMatheus Ferst GEN_PRIV(ctx); 5726fcf5ef2aSThomas Huth #else 57279f0cf041SMatheus Ferst CHK_SV(ctx); 5728fcf5ef2aSThomas Huth /* Restore CPU state */ 5729fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 573059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5731fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5732fcf5ef2aSThomas Huth } 5733fcf5ef2aSThomas Huth 5734fcf5ef2aSThomas Huth /* BookE specific */ 5735fcf5ef2aSThomas Huth 5736fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5737fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5738fcf5ef2aSThomas Huth { 5739fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57409f0cf041SMatheus Ferst GEN_PRIV(ctx); 5741fcf5ef2aSThomas Huth #else 57429f0cf041SMatheus Ferst CHK_SV(ctx); 5743fcf5ef2aSThomas Huth /* Restore CPU state */ 5744fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 574559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5746fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5747fcf5ef2aSThomas Huth } 5748fcf5ef2aSThomas Huth 5749fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5750fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5751fcf5ef2aSThomas Huth { 5752fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57539f0cf041SMatheus Ferst GEN_PRIV(ctx); 5754fcf5ef2aSThomas Huth #else 57559f0cf041SMatheus Ferst CHK_SV(ctx); 5756fcf5ef2aSThomas Huth /* Restore CPU state */ 5757fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 575859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5759fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5760fcf5ef2aSThomas Huth } 5761fcf5ef2aSThomas Huth 5762fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5763fcf5ef2aSThomas Huth 5764fcf5ef2aSThomas Huth /* tlbre */ 5765fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5766fcf5ef2aSThomas Huth { 5767fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57689f0cf041SMatheus Ferst GEN_PRIV(ctx); 5769fcf5ef2aSThomas Huth #else 57709f0cf041SMatheus Ferst CHK_SV(ctx); 5771fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5772fcf5ef2aSThomas Huth case 0: 5773fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5774fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5775fcf5ef2aSThomas Huth break; 5776fcf5ef2aSThomas Huth case 1: 5777fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5778fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5779fcf5ef2aSThomas Huth break; 5780fcf5ef2aSThomas Huth default: 5781fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5782fcf5ef2aSThomas Huth break; 5783fcf5ef2aSThomas Huth } 5784fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5785fcf5ef2aSThomas Huth } 5786fcf5ef2aSThomas Huth 5787fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5788fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5789fcf5ef2aSThomas Huth { 5790fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57919f0cf041SMatheus Ferst GEN_PRIV(ctx); 5792fcf5ef2aSThomas Huth #else 5793fcf5ef2aSThomas Huth TCGv t0; 5794fcf5ef2aSThomas Huth 57959f0cf041SMatheus Ferst CHK_SV(ctx); 5796fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5797fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5798fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5799fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5800fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5801fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5802fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5803fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5804fcf5ef2aSThomas Huth gen_set_label(l1); 5805fcf5ef2aSThomas Huth } 5806fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5807fcf5ef2aSThomas Huth } 5808fcf5ef2aSThomas Huth 5809fcf5ef2aSThomas Huth /* tlbwe */ 5810fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5811fcf5ef2aSThomas Huth { 5812fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58139f0cf041SMatheus Ferst GEN_PRIV(ctx); 5814fcf5ef2aSThomas Huth #else 58159f0cf041SMatheus Ferst CHK_SV(ctx); 5816fcf5ef2aSThomas Huth 5817fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5818fcf5ef2aSThomas Huth case 0: 5819fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5820fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5821fcf5ef2aSThomas Huth break; 5822fcf5ef2aSThomas Huth case 1: 5823fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5824fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5825fcf5ef2aSThomas Huth break; 5826fcf5ef2aSThomas Huth default: 5827fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5828fcf5ef2aSThomas Huth break; 5829fcf5ef2aSThomas Huth } 5830fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5831fcf5ef2aSThomas Huth } 5832fcf5ef2aSThomas Huth 5833fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5834fcf5ef2aSThomas Huth 5835fcf5ef2aSThomas Huth /* tlbre */ 5836fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5837fcf5ef2aSThomas Huth { 5838fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58399f0cf041SMatheus Ferst GEN_PRIV(ctx); 5840fcf5ef2aSThomas Huth #else 58419f0cf041SMatheus Ferst CHK_SV(ctx); 5842fcf5ef2aSThomas Huth 5843fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5844fcf5ef2aSThomas Huth case 0: 5845fcf5ef2aSThomas Huth case 1: 5846fcf5ef2aSThomas Huth case 2: 5847fcf5ef2aSThomas Huth { 58487058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5849fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5850fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5851fcf5ef2aSThomas Huth } 5852fcf5ef2aSThomas Huth break; 5853fcf5ef2aSThomas Huth default: 5854fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5855fcf5ef2aSThomas Huth break; 5856fcf5ef2aSThomas Huth } 5857fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5858fcf5ef2aSThomas Huth } 5859fcf5ef2aSThomas Huth 5860fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5861fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5862fcf5ef2aSThomas Huth { 5863fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5865fcf5ef2aSThomas Huth #else 5866fcf5ef2aSThomas Huth TCGv t0; 5867fcf5ef2aSThomas Huth 58689f0cf041SMatheus Ferst CHK_SV(ctx); 5869fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5870fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5871fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5872fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5873fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5874fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5875fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5876fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5877fcf5ef2aSThomas Huth gen_set_label(l1); 5878fcf5ef2aSThomas Huth } 5879fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5880fcf5ef2aSThomas Huth } 5881fcf5ef2aSThomas Huth 5882fcf5ef2aSThomas Huth /* tlbwe */ 5883fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5884fcf5ef2aSThomas Huth { 5885fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58869f0cf041SMatheus Ferst GEN_PRIV(ctx); 5887fcf5ef2aSThomas Huth #else 58889f0cf041SMatheus Ferst CHK_SV(ctx); 5889fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5890fcf5ef2aSThomas Huth case 0: 5891fcf5ef2aSThomas Huth case 1: 5892fcf5ef2aSThomas Huth case 2: 5893fcf5ef2aSThomas Huth { 58947058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5895fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5896fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5897fcf5ef2aSThomas Huth } 5898fcf5ef2aSThomas Huth break; 5899fcf5ef2aSThomas Huth default: 5900fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5901fcf5ef2aSThomas Huth break; 5902fcf5ef2aSThomas Huth } 5903fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5904fcf5ef2aSThomas Huth } 5905fcf5ef2aSThomas Huth 5906fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5907fcf5ef2aSThomas Huth 5908fcf5ef2aSThomas Huth /* tlbre */ 5909fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5910fcf5ef2aSThomas Huth { 5911fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59129f0cf041SMatheus Ferst GEN_PRIV(ctx); 5913fcf5ef2aSThomas Huth #else 59149f0cf041SMatheus Ferst CHK_SV(ctx); 5915fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5916fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5917fcf5ef2aSThomas Huth } 5918fcf5ef2aSThomas Huth 5919fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5920fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5921fcf5ef2aSThomas Huth { 5922fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59239f0cf041SMatheus Ferst GEN_PRIV(ctx); 5924fcf5ef2aSThomas Huth #else 5925fcf5ef2aSThomas Huth TCGv t0; 5926fcf5ef2aSThomas Huth 59279f0cf041SMatheus Ferst CHK_SV(ctx); 5928fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5929fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 59309d15d8e1SRichard Henderson tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5931fcf5ef2aSThomas Huth } else { 59329d15d8e1SRichard Henderson t0 = cpu_gpr[rB(ctx->opcode)]; 5933fcf5ef2aSThomas Huth } 5934fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5935fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5936fcf5ef2aSThomas Huth } 5937fcf5ef2aSThomas Huth 5938fcf5ef2aSThomas Huth /* tlbwe */ 5939fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5940fcf5ef2aSThomas Huth { 5941fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59429f0cf041SMatheus Ferst GEN_PRIV(ctx); 5943fcf5ef2aSThomas Huth #else 59449f0cf041SMatheus Ferst CHK_SV(ctx); 5945fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5946fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5947fcf5ef2aSThomas Huth } 5948fcf5ef2aSThomas Huth 5949fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5950fcf5ef2aSThomas Huth { 5951fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59529f0cf041SMatheus Ferst GEN_PRIV(ctx); 5953fcf5ef2aSThomas Huth #else 5954fcf5ef2aSThomas Huth TCGv t0; 5955fcf5ef2aSThomas Huth 59569f0cf041SMatheus Ferst CHK_SV(ctx); 5957fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5958fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5959fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5960fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5961fcf5ef2aSThomas Huth } 5962fcf5ef2aSThomas Huth 5963fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5964fcf5ef2aSThomas Huth { 5965fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59669f0cf041SMatheus Ferst GEN_PRIV(ctx); 5967fcf5ef2aSThomas Huth #else 5968fcf5ef2aSThomas Huth TCGv t0; 5969fcf5ef2aSThomas Huth 59709f0cf041SMatheus Ferst CHK_SV(ctx); 5971fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5972fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5973fcf5ef2aSThomas Huth 5974fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 5975fcf5ef2aSThomas Huth case 0: 5976fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 5977fcf5ef2aSThomas Huth break; 5978fcf5ef2aSThomas Huth case 1: 5979fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 5980fcf5ef2aSThomas Huth break; 5981fcf5ef2aSThomas Huth case 3: 5982fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 5983fcf5ef2aSThomas Huth break; 5984fcf5ef2aSThomas Huth default: 5985fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5986fcf5ef2aSThomas Huth break; 5987fcf5ef2aSThomas Huth } 5988fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5989fcf5ef2aSThomas Huth } 5990fcf5ef2aSThomas Huth 5991fcf5ef2aSThomas Huth /* wrtee */ 5992fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 5993fcf5ef2aSThomas Huth { 5994fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59959f0cf041SMatheus Ferst GEN_PRIV(ctx); 5996fcf5ef2aSThomas Huth #else 5997fcf5ef2aSThomas Huth TCGv t0; 5998fcf5ef2aSThomas Huth 59999f0cf041SMatheus Ferst CHK_SV(ctx); 6000fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6001fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6002fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6003fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 60042fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6005efe843d8SDavid Gibson /* 6006efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6007efe843d8SDavid Gibson * just set msr_ee to 1 6008fcf5ef2aSThomas Huth */ 6009d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6010fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6011fcf5ef2aSThomas Huth } 6012fcf5ef2aSThomas Huth 6013fcf5ef2aSThomas Huth /* wrteei */ 6014fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6015fcf5ef2aSThomas Huth { 6016fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60179f0cf041SMatheus Ferst GEN_PRIV(ctx); 6018fcf5ef2aSThomas Huth #else 60199f0cf041SMatheus Ferst CHK_SV(ctx); 6020fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6021fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 60222fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6023fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6024d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6025fcf5ef2aSThomas Huth } else { 6026fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6027fcf5ef2aSThomas Huth } 6028fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6029fcf5ef2aSThomas Huth } 6030fcf5ef2aSThomas Huth 6031fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6032fcf5ef2aSThomas Huth 6033fcf5ef2aSThomas Huth /* dlmzb */ 6034fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6035fcf5ef2aSThomas Huth { 60367058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6037fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6038fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6039fcf5ef2aSThomas Huth } 6040fcf5ef2aSThomas Huth 6041fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6042fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6043fcf5ef2aSThomas Huth { 6044fcf5ef2aSThomas Huth /* interpreted as no-op */ 6045fcf5ef2aSThomas Huth } 6046fcf5ef2aSThomas Huth 6047fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6048fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6049fcf5ef2aSThomas Huth { 605027a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 605127a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 605227a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 605327a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 605427a3ea7eSBALATON Zoltan } 605527a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6056fcf5ef2aSThomas Huth } 6057fcf5ef2aSThomas Huth 6058fcf5ef2aSThomas Huth /* icbt */ 6059fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6060fcf5ef2aSThomas Huth { 6061efe843d8SDavid Gibson /* 6062efe843d8SDavid Gibson * interpreted as no-op 6063efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6064efe843d8SDavid Gibson * does not generate any exception 6065fcf5ef2aSThomas Huth */ 6066fcf5ef2aSThomas Huth } 6067fcf5ef2aSThomas Huth 6068fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6069fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6070fcf5ef2aSThomas Huth { 6071fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6072fcf5ef2aSThomas Huth 6073fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6074fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6075fcf5ef2aSThomas Huth } 6076fcf5ef2aSThomas Huth 6077fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6078fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6079fcf5ef2aSThomas Huth { 6080fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6081fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6082fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6083fcf5ef2aSThomas Huth 6084fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6085fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6086fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6087fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6088fcf5ef2aSThomas Huth } else { 6089fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6090fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6091fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6092fcf5ef2aSThomas Huth } 6093fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6094fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6095fcf5ef2aSThomas Huth } 6096fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6097fcf5ef2aSThomas Huth 6098fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6099fcf5ef2aSThomas Huth { 6100fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6101fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6102fcf5ef2aSThomas Huth return; 6103fcf5ef2aSThomas Huth } 6104fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6105fcf5ef2aSThomas Huth } 6106fcf5ef2aSThomas Huth 6107fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6108fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6109fcf5ef2aSThomas Huth { \ 6110fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6111fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6112fcf5ef2aSThomas Huth return; \ 6113fcf5ef2aSThomas Huth } \ 6114efe843d8SDavid Gibson /* \ 6115efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6116fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6117fcf5ef2aSThomas Huth * \ 6118fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6119fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6120fcf5ef2aSThomas Huth */ \ 6121fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6122fcf5ef2aSThomas Huth } 6123fcf5ef2aSThomas Huth 6124fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6125fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6126fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6127fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6128fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6129fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6130fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6131efe843d8SDavid Gibson 6132b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6133b8b4576eSSuraj Jitindar Singh { 6134efe843d8SDavid Gibson /* Do Nothing */ 6135b8b4576eSSuraj Jitindar Singh } 6136fcf5ef2aSThomas Huth 613780b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 613880b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 613980b8c1eeSNikunj A Dadhania { \ 6140efe843d8SDavid Gibson /* \ 6141efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6142efe843d8SDavid Gibson * implementation of the copy paste facility \ 614380b8c1eeSNikunj A Dadhania */ \ 614480b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 614580b8c1eeSNikunj A Dadhania } 614680b8c1eeSNikunj A Dadhania 614780b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 614880b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 614980b8c1eeSNikunj A Dadhania 6150fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6151fcf5ef2aSThomas Huth { 6152fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6153fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6154fcf5ef2aSThomas Huth return; 6155fcf5ef2aSThomas Huth } 6156efe843d8SDavid Gibson /* 6157efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6158efe843d8SDavid Gibson * simple: 6159fcf5ef2aSThomas Huth * 6160fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6161fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6162fcf5ef2aSThomas Huth */ 6163fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6164fcf5ef2aSThomas Huth } 6165fcf5ef2aSThomas Huth 6166fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6167fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6168fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6169fcf5ef2aSThomas Huth { \ 61709f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6171fcf5ef2aSThomas Huth } 6172fcf5ef2aSThomas Huth 6173fcf5ef2aSThomas Huth #else 6174fcf5ef2aSThomas Huth 6175fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6176fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6177fcf5ef2aSThomas Huth { \ 61789f0cf041SMatheus Ferst CHK_SV(ctx); \ 6179fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6180fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6181fcf5ef2aSThomas Huth return; \ 6182fcf5ef2aSThomas Huth } \ 6183efe843d8SDavid Gibson /* \ 6184efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6185fcf5ef2aSThomas Huth * simple: \ 6186fcf5ef2aSThomas Huth * \ 6187fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6188fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6189fcf5ef2aSThomas Huth */ \ 6190fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6191fcf5ef2aSThomas Huth } 6192fcf5ef2aSThomas Huth 6193fcf5ef2aSThomas Huth #endif 6194fcf5ef2aSThomas Huth 6195fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6196fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6197fcf5ef2aSThomas Huth 61981a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 61991a404c91SMark Cave-Ayland { 6200e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 62011a404c91SMark Cave-Ayland } 62021a404c91SMark Cave-Ayland 62031a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 62041a404c91SMark Cave-Ayland { 6205e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 62064b65b6e7SVíctor Colombo /* 62074b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 62084b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 62094b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 62104b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 62114b65b6e7SVíctor Colombo * to be 0. 62124b65b6e7SVíctor Colombo */ 62134b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 62141a404c91SMark Cave-Ayland } 62151a404c91SMark Cave-Ayland 6216c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6217c4a18dbfSMark Cave-Ayland { 621837da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6219c4a18dbfSMark Cave-Ayland } 6220c4a18dbfSMark Cave-Ayland 6221c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6222c4a18dbfSMark Cave-Ayland { 622337da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6224c4a18dbfSMark Cave-Ayland } 6225c4a18dbfSMark Cave-Ayland 6226c9826ae9SRichard Henderson /* 6227f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6228f2aabda8SRichard Henderson */ 6229d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6230d39b2cc7SLuis Pires { 6231d39b2cc7SLuis Pires return x * 2; 6232d39b2cc7SLuis Pires } 6233d39b2cc7SLuis Pires 6234f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6235f2aabda8SRichard Henderson { 6236f2aabda8SRichard Henderson return x * 4; 6237f2aabda8SRichard Henderson } 6238f2aabda8SRichard Henderson 6239e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6240e10271e1SMatheus Ferst { 6241e10271e1SMatheus Ferst return x * 16; 6242e10271e1SMatheus Ferst } 6243e10271e1SMatheus Ferst 6244670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6245670f1da3SVíctor Colombo { 6246670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6247670f1da3SVíctor Colombo } 6248670f1da3SVíctor Colombo 6249f2aabda8SRichard Henderson /* 6250c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6251c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6252c9826ae9SRichard Henderson * proper variable. 6253c9826ae9SRichard Henderson */ 6254c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6255c9826ae9SRichard Henderson do { \ 6256c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6257c9826ae9SRichard Henderson return false; \ 6258c9826ae9SRichard Henderson } \ 6259c9826ae9SRichard Henderson } while (0) 6260c9826ae9SRichard Henderson 6261c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6262c9826ae9SRichard Henderson do { \ 6263c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6264c9826ae9SRichard Henderson return false; \ 6265c9826ae9SRichard Henderson } \ 6266c9826ae9SRichard Henderson } while (0) 6267c9826ae9SRichard Henderson 6268c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6269c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6270c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6271c9826ae9SRichard Henderson #else 6272c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6273c9826ae9SRichard Henderson #endif 6274c9826ae9SRichard Henderson 6275e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6276e2205a46SBruno Larsen do { \ 6277e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6278e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6279e2205a46SBruno Larsen return true; \ 6280e2205a46SBruno Larsen } \ 6281e2205a46SBruno Larsen } while (0) 6282e2205a46SBruno Larsen 62838226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 62848226cb2dSBruno Larsen (billionai) do { \ 62858226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 62868226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 62878226cb2dSBruno Larsen (billionai) return true; \ 62888226cb2dSBruno Larsen (billionai) } \ 62898226cb2dSBruno Larsen (billionai) } while (0) 62908226cb2dSBruno Larsen (billionai) 629186057426SFernando Valle #define REQUIRE_FPU(ctx) \ 629286057426SFernando Valle do { \ 629386057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 629486057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 629586057426SFernando Valle return true; \ 629686057426SFernando Valle } \ 629786057426SFernando Valle } while (0) 629886057426SFernando Valle 6299fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6300fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6301fc34e81aSMatheus Ferst do { \ 6302fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6303fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6304fc34e81aSMatheus Ferst return true; \ 6305fc34e81aSMatheus Ferst } \ 6306fc34e81aSMatheus Ferst } while (0) 6307fc34e81aSMatheus Ferst 6308fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6309fc34e81aSMatheus Ferst do { \ 6310e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6311fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6312fc34e81aSMatheus Ferst return true; \ 6313fc34e81aSMatheus Ferst } \ 6314fc34e81aSMatheus Ferst } while (0) 6315fc34e81aSMatheus Ferst #else 6316fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6317fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6318fc34e81aSMatheus Ferst #endif 6319fc34e81aSMatheus Ferst 6320f2aabda8SRichard Henderson /* 6321f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6322f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6323f2aabda8SRichard Henderson */ 6324f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6325f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6326f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 632719f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 632819f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 632919f0862dSLuis Pires { \ 633019f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 633119f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 633219f0862dSLuis Pires } 633319f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 633419f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 633519f0862dSLuis Pires { \ 633619f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 633719f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 633819f0862dSLuis Pires } 6339f2aabda8SRichard Henderson 6340f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6341f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6342f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 634319f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 634419f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 634519f0862dSLuis Pires { \ 634619f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 634719f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 634819f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 634919f0862dSLuis Pires } 6350f2aabda8SRichard Henderson 6351f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6352f2aabda8SRichard Henderson 6353f2aabda8SRichard Henderson 635499082815SRichard Henderson #include "decode-insn32.c.inc" 635599082815SRichard Henderson #include "decode-insn64.c.inc" 6356565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6357565cb109SGustavo Romero 6358725b2d4dSFernando Eckhardt Valle /* 6359725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6360725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6361725b2d4dSFernando Eckhardt Valle */ 6362725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6363725b2d4dSFernando Eckhardt Valle { 6364725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6365725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6366725b2d4dSFernando Eckhardt Valle d->si = a->si; 6367725b2d4dSFernando Eckhardt Valle if (a->r) { 6368725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6369725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6370725b2d4dSFernando Eckhardt Valle return false; 6371725b2d4dSFernando Eckhardt Valle } 6372725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6373725b2d4dSFernando Eckhardt Valle } 6374725b2d4dSFernando Eckhardt Valle return true; 6375725b2d4dSFernando Eckhardt Valle } 6376725b2d4dSFernando Eckhardt Valle 637799082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 637899082815SRichard Henderson 6379139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6380fcf5ef2aSThomas Huth 6381139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6382fcf5ef2aSThomas Huth 6383139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6384fcf5ef2aSThomas Huth 6385139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6386fcf5ef2aSThomas Huth 6387139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6388fcf5ef2aSThomas Huth 63891f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 63901f26c751SDaniel Henrique Barboza 639198f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 639298f43417SMatheus Ferst 6393016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6394016b6e1dSLeandro Lupori 639520e2d04eSLeandro Lupori /* Handles lfdp */ 63965cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 63975cb091a4SNikunj A Dadhania { 639820e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 63995cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 64005cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 64015cb091a4SNikunj A Dadhania } 64025cb091a4SNikunj A Dadhania } 64035cb091a4SNikunj A Dadhania return gen_invalid(ctx); 64045cb091a4SNikunj A Dadhania } 64055cb091a4SNikunj A Dadhania 640620e2d04eSLeandro Lupori /* Handles stfdp */ 6407e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6408e3001664SNikunj A Dadhania { 640920e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 641020e2d04eSLeandro Lupori /* stfdp */ 6411e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6412e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6413e3001664SNikunj A Dadhania } 6414e3001664SNikunj A Dadhania } 6415e3001664SNikunj A Dadhania return gen_invalid(ctx); 6416e3001664SNikunj A Dadhania } 6417e3001664SNikunj A Dadhania 64189d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64199d69cfa2SLijun Pan /* brd */ 64209d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 64219d69cfa2SLijun Pan { 64229d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64239d69cfa2SLijun Pan } 64249d69cfa2SLijun Pan 64259d69cfa2SLijun Pan /* brw */ 64269d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 64279d69cfa2SLijun Pan { 64289d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64299d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 64309d69cfa2SLijun Pan 64319d69cfa2SLijun Pan } 64329d69cfa2SLijun Pan 64339d69cfa2SLijun Pan /* brh */ 64349d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 64359d69cfa2SLijun Pan { 6436491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 64379d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 64389d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 64399d69cfa2SLijun Pan 64409d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6441491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6442491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 64439d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 64449d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 64459d69cfa2SLijun Pan } 64469d69cfa2SLijun Pan #endif 64479d69cfa2SLijun Pan 6448fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 64499d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64509d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 64519d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 64529d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 64539d69cfa2SLijun Pan #endif 6454fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6455fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6456fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6457fcf5ef2aSThomas Huth #endif 6458fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6459fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6460fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6461fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6462fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6463fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6464fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6465fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6466fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6467fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6468fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6469fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6470fcf5ef2aSThomas Huth #endif 6471fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6472fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6473fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6474fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6475fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6476fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6477fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 647880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6479b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 648080b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6481fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6482fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6483fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6484fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6485fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6486fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6487fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6488fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6489fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6490fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6491fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6492fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6493fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6494fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6495fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6496fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6497fcf5ef2aSThomas Huth #endif 6498fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6499fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6500fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6501fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6502fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6503fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6504fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6505fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6506fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6507fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6508fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6509fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6510fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6511fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6512fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6513fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6514fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6515fcf5ef2aSThomas Huth #endif 65165cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 65175cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 651872b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6519e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6520fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6521fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6522fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6523fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6524fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6525fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6526c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6527fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6528fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6529fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6530fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6531a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6532a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6533fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6534fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6535fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6536fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6537a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6538a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6539fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6540fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6541fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6542fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6543fcf5ef2aSThomas Huth #endif 6544fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 65450c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 65460c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 65470c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6548fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6549fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6550fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6551fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6552fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6553fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6554fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6555fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6556fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 65573c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 65583c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65593c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65603c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65613c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 65623c89b8d6SNicholas Piggin #endif 6563cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6564fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6565fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6566fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6567fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6568fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6569fcf5ef2aSThomas Huth #endif 65703c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65713c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 65723c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6573fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6574fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6575fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6576fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6577fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6578fcf5ef2aSThomas Huth #endif 6579fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6580fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6581fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6582fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6583fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6584fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6585fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6586fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6587fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6588b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6589fcf5ef2aSThomas Huth #endif 6590fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6591fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6592fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 659350728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6594fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6595fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 659650728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6597fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 659850728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6599fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 660050728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6601fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6602e64645baSBernhard Beschow GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6603fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 660450728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6605fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 660699d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6607fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6608fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 660950728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6610fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6611fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6612fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6613fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6614fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6615fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6616fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6617fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6618fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6619fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6620fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6621fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6622fcf5ef2aSThomas Huth #endif 6623fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6624efe843d8SDavid Gibson /* 6625efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6626efe843d8SDavid Gibson * different ISA versions 6627efe843d8SDavid Gibson */ 6628fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6629fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6630fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6631fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6632fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6633fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6634fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6635fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6636fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6637fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6638fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6639fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6640fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6641fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6642fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6643fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6644fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6645fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6646fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6647fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6648fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6649fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6650fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6651fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6652fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6653fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6654fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6655fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6656fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6657fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6658fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6659fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6660fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6661fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6662fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6663fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6664fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6665fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6666fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6667fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6668fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 666927a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6670fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6671fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 66720c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 66730c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6674fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6675fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6676fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6677fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6678fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6679fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6680fcf5ef2aSThomas Huth PPC2_ISA300), 6681fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6682fcf5ef2aSThomas Huth #endif 6683fcf5ef2aSThomas Huth 6684fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6685fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6686fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6687fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6688fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6689fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6690fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6691fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6692fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6693fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6694fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6695fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6696fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6697fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6698fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 66994c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6700fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6701fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6702fcf5ef2aSThomas Huth 6703fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6704fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6705fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6706fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6707fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6708fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6709fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6710fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6711fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6712fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6713fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6714fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6715fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6716fcf5ef2aSThomas Huth 6717fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6718fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6719fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6720fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6721fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6722fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6723fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6724fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6725fcf5ef2aSThomas Huth 6726fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6727fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6728fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6729fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6730fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6731fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6732fcf5ef2aSThomas Huth 6733fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6734fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6735fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6736fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6737fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6738fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6739fcf5ef2aSThomas Huth #endif 6740fcf5ef2aSThomas Huth 6741fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6742fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6743fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6744fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6745fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6746fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6747fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6748fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6749fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6750fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6751fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6752fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6753fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6754fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6755fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6756fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6757fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6758fcf5ef2aSThomas Huth 6759fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6760fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6761fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6762fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6763fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6764fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6765fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6766fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6767fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6768fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6769fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6770fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6771fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6772fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6773fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6774fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6775fcf5ef2aSThomas Huth #endif 6776fcf5ef2aSThomas Huth 6777fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6778fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6779fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6780fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6781fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6782fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6783fcf5ef2aSThomas Huth PPC_64B) 6784fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6785fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6786fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6787fcf5ef2aSThomas Huth PPC_64B), \ 6788fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6789fcf5ef2aSThomas Huth PPC_64B), \ 6790fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6791fcf5ef2aSThomas Huth PPC_64B) 6792fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6793fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6794fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6795fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6796fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6797fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6798fcf5ef2aSThomas Huth #endif 6799fcf5ef2aSThomas Huth 6800fcf5ef2aSThomas Huth #undef GEN_LDX_E 6801fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6802fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6803fcf5ef2aSThomas Huth 6804fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6805fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6806fcf5ef2aSThomas Huth 6807fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6808fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6809fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6810fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6811fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6812fcf5ef2aSThomas Huth #endif 6813fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6814fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6815fcf5ef2aSThomas Huth 681650728199SRoman Kapl /* External PID based load */ 681750728199SRoman Kapl #undef GEN_LDEPX 681850728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 681950728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 682050728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 682150728199SRoman Kapl 682250728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 682350728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 682450728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 682550728199SRoman Kapl #if defined(TARGET_PPC64) 6826fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 682750728199SRoman Kapl #endif 682850728199SRoman Kapl 6829fcf5ef2aSThomas Huth #undef GEN_STX_E 6830fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 68310123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6832fcf5ef2aSThomas Huth 6833fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6834fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6835fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6836fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6837fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6838fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6839fcf5ef2aSThomas Huth #endif 6840fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6841fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6842fcf5ef2aSThomas Huth 684350728199SRoman Kapl #undef GEN_STEPX 684450728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 684550728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 684650728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 684750728199SRoman Kapl 684850728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 684950728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 685050728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 685150728199SRoman Kapl #if defined(TARGET_PPC64) 6852fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 685350728199SRoman Kapl #endif 685450728199SRoman Kapl 6855fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6856fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6857fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6858fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6859fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6860fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6861fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6862fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6863fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6864fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6865fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6866fcf5ef2aSThomas Huth 6867fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6868fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6869fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6870fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6871fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6872fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6873fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6874fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6875fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6876fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6877fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6878fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6879fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6880fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6881fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6882fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6883fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6884fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6885fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6886fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6887fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6888fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6889fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6890fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6891fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6892fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6893fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6894fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6895fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6896fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6897fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6898fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6899fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6900fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6901fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6902fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6903fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6904fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6905fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6906fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6907fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6908fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6909fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6910fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6911fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6912fcf5ef2aSThomas Huth 6913fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6914fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6915fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6916fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6917fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6918fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6919fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6920fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6921fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6922fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6923fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6924fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6925fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6926fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6927fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6928fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6929fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6930fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6931fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6932fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6933fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6934fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6935fcf5ef2aSThomas Huth 6936139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 6937fcf5ef2aSThomas Huth 6938139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 6939fcf5ef2aSThomas Huth 6940139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 6941fcf5ef2aSThomas Huth 6942139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 6943fcf5ef2aSThomas Huth }; 6944fcf5ef2aSThomas Huth 69457468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 69467468e2c8SBruno Larsen (billionai) /* Opcode types */ 69477468e2c8SBruno Larsen (billionai) enum { 69487468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 69497468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 69507468e2c8SBruno Larsen (billionai) }; 69517468e2c8SBruno Larsen (billionai) 69527468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 69537468e2c8SBruno Larsen (billionai) 69547468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 69557468e2c8SBruno Larsen (billionai) { 69567468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 69577468e2c8SBruno Larsen (billionai) } 69587468e2c8SBruno Larsen (billionai) 69597468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 69607468e2c8SBruno Larsen (billionai) { 69617468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 69627468e2c8SBruno Larsen (billionai) } 69637468e2c8SBruno Larsen (billionai) 69647468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 69657468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 69667468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 69677468e2c8SBruno Larsen (billionai) { 69687468e2c8SBruno Larsen (billionai) int i; 69697468e2c8SBruno Larsen (billionai) 69707468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 69717468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 69727468e2c8SBruno Larsen (billionai) } 69737468e2c8SBruno Larsen (billionai) } 69747468e2c8SBruno Larsen (billionai) 69757468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 69767468e2c8SBruno Larsen (billionai) { 69777468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 69787468e2c8SBruno Larsen (billionai) 69797468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 69807468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 69817468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 69827468e2c8SBruno Larsen (billionai) 69837468e2c8SBruno Larsen (billionai) return 0; 69847468e2c8SBruno Larsen (billionai) } 69857468e2c8SBruno Larsen (billionai) 69867468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 69877468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69887468e2c8SBruno Larsen (billionai) { 69897468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 69907468e2c8SBruno Larsen (billionai) return -1; 69917468e2c8SBruno Larsen (billionai) } 69927468e2c8SBruno Larsen (billionai) table[idx] = handler; 69937468e2c8SBruno Larsen (billionai) 69947468e2c8SBruno Larsen (billionai) return 0; 69957468e2c8SBruno Larsen (billionai) } 69967468e2c8SBruno Larsen (billionai) 69977468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 69987468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 69997468e2c8SBruno Larsen (billionai) { 70007468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 70017468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 70027468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 70037468e2c8SBruno Larsen (billionai) return -1; 70047468e2c8SBruno Larsen (billionai) } 70057468e2c8SBruno Larsen (billionai) 70067468e2c8SBruno Larsen (billionai) return 0; 70077468e2c8SBruno Larsen (billionai) } 70087468e2c8SBruno Larsen (billionai) 70097468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 70107468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70117468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70127468e2c8SBruno Larsen (billionai) { 70137468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 70147468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 70157468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 70167468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 70177468e2c8SBruno Larsen (billionai) return -1; 70187468e2c8SBruno Larsen (billionai) } 70197468e2c8SBruno Larsen (billionai) } else { 70207468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 70217468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 70227468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 70237468e2c8SBruno Larsen (billionai) return -1; 70247468e2c8SBruno Larsen (billionai) } 70257468e2c8SBruno Larsen (billionai) } 70267468e2c8SBruno Larsen (billionai) if (handler != NULL && 70277468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 70287468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 70297468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 70307468e2c8SBruno Larsen (billionai) return -1; 70317468e2c8SBruno Larsen (billionai) } 70327468e2c8SBruno Larsen (billionai) 70337468e2c8SBruno Larsen (billionai) return 0; 70347468e2c8SBruno Larsen (billionai) } 70357468e2c8SBruno Larsen (billionai) 70367468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 70377468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70387468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70397468e2c8SBruno Larsen (billionai) { 70407468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 70417468e2c8SBruno Larsen (billionai) } 70427468e2c8SBruno Larsen (billionai) 70437468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 70447468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70457468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 70467468e2c8SBruno Larsen (billionai) { 70477468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70487468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70497468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70507468e2c8SBruno Larsen (billionai) return -1; 70517468e2c8SBruno Larsen (billionai) } 70527468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 70537468e2c8SBruno Larsen (billionai) handler) < 0) { 70547468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70557468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70567468e2c8SBruno Larsen (billionai) return -1; 70577468e2c8SBruno Larsen (billionai) } 70587468e2c8SBruno Larsen (billionai) 70597468e2c8SBruno Larsen (billionai) return 0; 70607468e2c8SBruno Larsen (billionai) } 70617468e2c8SBruno Larsen (billionai) 70627468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 70637468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70647468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 70657468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70667468e2c8SBruno Larsen (billionai) { 70677468e2c8SBruno Larsen (billionai) opc_handler_t **table; 70687468e2c8SBruno Larsen (billionai) 70697468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70707468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70717468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70727468e2c8SBruno Larsen (billionai) return -1; 70737468e2c8SBruno Larsen (billionai) } 70747468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 70757468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 70767468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 70777468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70787468e2c8SBruno Larsen (billionai) return -1; 70797468e2c8SBruno Larsen (billionai) } 70807468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 70817468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 70827468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70837468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 70847468e2c8SBruno Larsen (billionai) return -1; 70857468e2c8SBruno Larsen (billionai) } 70867468e2c8SBruno Larsen (billionai) return 0; 70877468e2c8SBruno Larsen (billionai) } 70887468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 70897468e2c8SBruno Larsen (billionai) { 70907468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 70917468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 70927468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 70937468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70947468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 70957468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 70967468e2c8SBruno Larsen (billionai) return -1; 70977468e2c8SBruno Larsen (billionai) } 70987468e2c8SBruno Larsen (billionai) } else { 70997468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 71007468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 71017468e2c8SBruno Larsen (billionai) return -1; 71027468e2c8SBruno Larsen (billionai) } 71037468e2c8SBruno Larsen (billionai) } 71047468e2c8SBruno Larsen (billionai) } else { 71057468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 71067468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 71077468e2c8SBruno Larsen (billionai) return -1; 71087468e2c8SBruno Larsen (billionai) } 71097468e2c8SBruno Larsen (billionai) } 71107468e2c8SBruno Larsen (billionai) } else { 71117468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 71127468e2c8SBruno Larsen (billionai) return -1; 71137468e2c8SBruno Larsen (billionai) } 71147468e2c8SBruno Larsen (billionai) } 71157468e2c8SBruno Larsen (billionai) 71167468e2c8SBruno Larsen (billionai) return 0; 71177468e2c8SBruno Larsen (billionai) } 71187468e2c8SBruno Larsen (billionai) 71197468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 71207468e2c8SBruno Larsen (billionai) { 71217468e2c8SBruno Larsen (billionai) int i, count, tmp; 71227468e2c8SBruno Larsen (billionai) 71237468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 71247468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 71257468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 71267468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71277468e2c8SBruno Larsen (billionai) } 71287468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 71297468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 71307468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 71317468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 71327468e2c8SBruno Larsen (billionai) if (tmp == 0) { 71337468e2c8SBruno Larsen (billionai) free(table[i]); 71347468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71357468e2c8SBruno Larsen (billionai) } else { 71367468e2c8SBruno Larsen (billionai) count++; 71377468e2c8SBruno Larsen (billionai) } 71387468e2c8SBruno Larsen (billionai) } else { 71397468e2c8SBruno Larsen (billionai) count++; 71407468e2c8SBruno Larsen (billionai) } 71417468e2c8SBruno Larsen (billionai) } 71427468e2c8SBruno Larsen (billionai) } 71437468e2c8SBruno Larsen (billionai) 71447468e2c8SBruno Larsen (billionai) return count; 71457468e2c8SBruno Larsen (billionai) } 71467468e2c8SBruno Larsen (billionai) 71477468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 71487468e2c8SBruno Larsen (billionai) { 71497468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 71507468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 71517468e2c8SBruno Larsen (billionai) } 71527468e2c8SBruno Larsen (billionai) } 71537468e2c8SBruno Larsen (billionai) 71547468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71557468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 71567468e2c8SBruno Larsen (billionai) { 71577468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 71587468e2c8SBruno Larsen (billionai) opcode_t *opc; 71597468e2c8SBruno Larsen (billionai) 71607468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 71617468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 71627468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 71637468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 71647468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 71657468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 71667468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 71677468e2c8SBruno Larsen (billionai) opc->opc3); 71687468e2c8SBruno Larsen (billionai) return; 71697468e2c8SBruno Larsen (billionai) } 71707468e2c8SBruno Larsen (billionai) } 71717468e2c8SBruno Larsen (billionai) } 71727468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 71737468e2c8SBruno Larsen (billionai) fflush(stdout); 71747468e2c8SBruno Larsen (billionai) fflush(stderr); 71757468e2c8SBruno Larsen (billionai) } 71767468e2c8SBruno Larsen (billionai) 71777468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 71787468e2c8SBruno Larsen (billionai) { 71797468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 71807468e2c8SBruno Larsen (billionai) int i, j, k; 71817468e2c8SBruno Larsen (billionai) 71827468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 71837468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 71847468e2c8SBruno Larsen (billionai) continue; 71857468e2c8SBruno Larsen (billionai) } 71867468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 71877468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 71887468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 71897468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 71907468e2c8SBruno Larsen (billionai) continue; 71917468e2c8SBruno Larsen (billionai) } 71927468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 71937468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 71947468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 71957468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 71967468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 71977468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 71987468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71997468e2c8SBruno Larsen (billionai) } 72007468e2c8SBruno Larsen (billionai) } 72017468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 72027468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 72037468e2c8SBruno Larsen (billionai) } 72047468e2c8SBruno Larsen (billionai) } 72057468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 72067468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 72077468e2c8SBruno Larsen (billionai) } 72087468e2c8SBruno Larsen (billionai) } 72097468e2c8SBruno Larsen (billionai) } 72107468e2c8SBruno Larsen (billionai) 72117468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 72127468e2c8SBruno Larsen (billionai) { 72137468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 72147468e2c8SBruno Larsen (billionai) 72157468e2c8SBruno Larsen (billionai) /* 72167468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 72177468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 72187468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 72197468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 72207468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 72217468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 72227468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 72237468e2c8SBruno Larsen (billionai) */ 72247468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 72257468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 72267468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 72277468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 72287468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 72297468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 72307468e2c8SBruno Larsen (billionai) } 72317468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 72327468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 72337468e2c8SBruno Larsen (billionai) return 0; 72347468e2c8SBruno Larsen (billionai) } 72357468e2c8SBruno Larsen (billionai) 7236624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7237624cb07fSRichard Henderson { 7238624cb07fSRichard Henderson opc_handler_t **table, *handler; 7239624cb07fSRichard Henderson uint32_t inval; 7240624cb07fSRichard Henderson 7241624cb07fSRichard Henderson ctx->opcode = insn; 7242624cb07fSRichard Henderson 7243624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7244624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7245624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7246624cb07fSRichard Henderson 7247624cb07fSRichard Henderson table = cpu->opcodes; 7248624cb07fSRichard Henderson handler = table[opc1(insn)]; 7249624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7250624cb07fSRichard Henderson table = ind_table(handler); 7251624cb07fSRichard Henderson handler = table[opc2(insn)]; 7252624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7253624cb07fSRichard Henderson table = ind_table(handler); 7254624cb07fSRichard Henderson handler = table[opc3(insn)]; 7255624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7256624cb07fSRichard Henderson table = ind_table(handler); 7257624cb07fSRichard Henderson handler = table[opc4(insn)]; 7258624cb07fSRichard Henderson } 7259624cb07fSRichard Henderson } 7260624cb07fSRichard Henderson } 7261624cb07fSRichard Henderson 7262624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7263624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7264624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7265624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7266624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7267624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7268624cb07fSRichard Henderson insn, ctx->cia); 7269624cb07fSRichard Henderson return false; 7270624cb07fSRichard Henderson } 7271624cb07fSRichard Henderson 7272624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7273624cb07fSRichard Henderson && Rc(insn))) { 7274624cb07fSRichard Henderson inval = handler->inval2; 7275624cb07fSRichard Henderson } else { 7276624cb07fSRichard Henderson inval = handler->inval1; 7277624cb07fSRichard Henderson } 7278624cb07fSRichard Henderson 7279624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7280624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7281624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7282624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7283624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7284624cb07fSRichard Henderson insn, ctx->cia); 7285624cb07fSRichard Henderson return false; 7286624cb07fSRichard Henderson } 7287624cb07fSRichard Henderson 7288624cb07fSRichard Henderson handler->handler(ctx); 7289624cb07fSRichard Henderson return true; 7290624cb07fSRichard Henderson } 7291624cb07fSRichard Henderson 7292b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7293fcf5ef2aSThomas Huth { 7294b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 72959c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 72962df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7297fcf5ef2aSThomas Huth 7298b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 72992df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7300d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 73012df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 73022df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7303b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7304b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7305b0c2d521SEmilio G. Cota ctx->access_type = -1; 7306d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 73072df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7308b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 73090e3bf489SRoman Kapl ctx->flags = env->flags; 7310fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 73112df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7312b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7313fcf5ef2aSThomas Huth #endif 7314e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7315d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7316fcf5ef2aSThomas Huth 73172df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 73182df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 73192df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 73202df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 73212df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7322f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 73231db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7324f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7325f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 73268b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 73278b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 732846d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 73292df4fe7aSRichard Henderson 7330b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 73312df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 73322df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 73339498d103SRichard Henderson ctx->base.max_insns = 1; 7334efe843d8SDavid Gibson } 73352df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7336b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7337efe843d8SDavid Gibson } 733813b45575SRichard Henderson } 7339fcf5ef2aSThomas Huth 7340b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7341b0c2d521SEmilio G. Cota { 7342b0c2d521SEmilio G. Cota } 7343fcf5ef2aSThomas Huth 7344b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7345b0c2d521SEmilio G. Cota { 7346b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7347b0c2d521SEmilio G. Cota } 7348b0c2d521SEmilio G. Cota 734999082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 735099082815SRichard Henderson { 735199082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 735299082815SRichard Henderson return opc1(insn) == 1; 735399082815SRichard Henderson } 735499082815SRichard Henderson 7355b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7356b0c2d521SEmilio G. Cota { 7357b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 735828876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7359b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 736099082815SRichard Henderson target_ulong pc; 7361624cb07fSRichard Henderson uint32_t insn; 7362624cb07fSRichard Henderson bool ok; 7363b0c2d521SEmilio G. Cota 7364fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7365fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7366b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7367b0c2d521SEmilio G. Cota 736899082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 73694e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 737099082815SRichard Henderson ctx->base.pc_next = pc += 4; 7371fcf5ef2aSThomas Huth 737299082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 737399082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 737499082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 737599082815SRichard Henderson } else if ((pc & 63) == 0) { 737699082815SRichard Henderson /* 737799082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 737899082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 737999082815SRichard Henderson * 64-byte address boundary (system alignment error). 738099082815SRichard Henderson */ 738199082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 738299082815SRichard Henderson ok = true; 738399082815SRichard Henderson } else { 73844e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 73854e116893SIlya Leoshkevich need_byteswap(ctx)); 738699082815SRichard Henderson ctx->base.pc_next = pc += 4; 738799082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 738899082815SRichard Henderson } 7389624cb07fSRichard Henderson if (!ok) { 7390624cb07fSRichard Henderson gen_invalid(ctx); 7391fcf5ef2aSThomas Huth } 7392624cb07fSRichard Henderson 739364a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 739499082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 739564a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 739664a0f644SRichard Henderson } 7397fcf5ef2aSThomas Huth } 7398b0c2d521SEmilio G. Cota 7399b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7400b0c2d521SEmilio G. Cota { 7401b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7402a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7403a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7404b0c2d521SEmilio G. Cota 7405a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7406a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 74073d8a5b69SRichard Henderson return; 74083d8a5b69SRichard Henderson } 74093d8a5b69SRichard Henderson 7410a9b5b3d0SRichard Henderson /* Honor single stepping. */ 7411*98a18f4dSNicholas Piggin if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 7412a9b5b3d0SRichard Henderson switch (is_jmp) { 7413a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7414a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7415a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7416a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7417a9b5b3d0SRichard Henderson break; 7418a9b5b3d0SRichard Henderson case DISAS_EXIT: 7419a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7420a9b5b3d0SRichard Henderson break; 7421a9b5b3d0SRichard Henderson default: 7422a9b5b3d0SRichard Henderson g_assert_not_reached(); 7423fcf5ef2aSThomas Huth } 742413b45575SRichard Henderson 7425a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7426a9b5b3d0SRichard Henderson return; 7427a9b5b3d0SRichard Henderson } 7428a9b5b3d0SRichard Henderson 7429a9b5b3d0SRichard Henderson switch (is_jmp) { 7430a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7431a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 743246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7433a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7434a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7435a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7436a9b5b3d0SRichard Henderson break; 7437a9b5b3d0SRichard Henderson } 7438a9b5b3d0SRichard Henderson /* fall through */ 7439a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7440a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7441a9b5b3d0SRichard Henderson /* fall through */ 7442a9b5b3d0SRichard Henderson case DISAS_CHAIN: 744346d396bdSDaniel Henrique Barboza /* 744446d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 744546d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 744646d396bdSDaniel Henrique Barboza */ 744746d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 744846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 744946d396bdSDaniel Henrique Barboza } 745046d396bdSDaniel Henrique Barboza 7451a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7452a9b5b3d0SRichard Henderson break; 7453a9b5b3d0SRichard Henderson 7454a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7455a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7456a9b5b3d0SRichard Henderson /* fall through */ 7457a9b5b3d0SRichard Henderson case DISAS_EXIT: 745846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 745907ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7460a9b5b3d0SRichard Henderson break; 7461a9b5b3d0SRichard Henderson 7462a9b5b3d0SRichard Henderson default: 7463a9b5b3d0SRichard Henderson g_assert_not_reached(); 7464fcf5ef2aSThomas Huth } 7465fcf5ef2aSThomas Huth } 7466b0c2d521SEmilio G. Cota 74678eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 74688eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7469b0c2d521SEmilio G. Cota { 74708eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 74718eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7472b0c2d521SEmilio G. Cota } 7473b0c2d521SEmilio G. Cota 7474b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7475b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7476b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7477b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7478b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7479b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7480b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7481b0c2d521SEmilio G. Cota }; 7482b0c2d521SEmilio G. Cota 7483597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7484306c8721SRichard Henderson target_ulong pc, void *host_pc) 7485b0c2d521SEmilio G. Cota { 7486b0c2d521SEmilio G. Cota DisasContext ctx; 7487b0c2d521SEmilio G. Cota 7488306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7489fcf5ef2aSThomas Huth } 7490