1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth 41fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 42fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 43fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 46efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 47efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 157fcf5ef2aSThomas Huth uint32_t opcode; 158fcf5ef2aSThomas Huth uint32_t exception; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 177fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 178fcf5ef2aSThomas Huth int singlestep_enabled; 1790e3bf489SRoman Kapl uint32_t flags; 180fcf5ef2aSThomas Huth uint64_t insns_flags; 181fcf5ef2aSThomas Huth uint64_t insns_flags2; 182fcf5ef2aSThomas Huth }; 183fcf5ef2aSThomas Huth 184fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 185fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 186fcf5ef2aSThomas Huth { 187fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 188fcf5ef2aSThomas Huth return ctx->le_mode; 189fcf5ef2aSThomas Huth #else 190fcf5ef2aSThomas Huth return !ctx->le_mode; 191fcf5ef2aSThomas Huth #endif 192fcf5ef2aSThomas Huth } 193fcf5ef2aSThomas Huth 194fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 195fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 196fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 197fcf5ef2aSThomas Huth #else 198fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 199fcf5ef2aSThomas Huth #endif 200fcf5ef2aSThomas Huth 201fcf5ef2aSThomas Huth struct opc_handler_t { 202fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 203fcf5ef2aSThomas Huth uint32_t inval1; 204fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 205fcf5ef2aSThomas Huth uint32_t inval2; 206fcf5ef2aSThomas Huth /* instruction type */ 207fcf5ef2aSThomas Huth uint64_t type; 208fcf5ef2aSThomas Huth /* extended instruction type */ 209fcf5ef2aSThomas Huth uint64_t type2; 210fcf5ef2aSThomas Huth /* handler */ 211fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 212fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 213fcf5ef2aSThomas Huth const char *oname; 214fcf5ef2aSThomas Huth #endif 215fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 216fcf5ef2aSThomas Huth uint64_t count; 217fcf5ef2aSThomas Huth #endif 218fcf5ef2aSThomas Huth }; 219fcf5ef2aSThomas Huth 2200e3bf489SRoman Kapl /* SPR load/store helpers */ 2210e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2220e3bf489SRoman Kapl { 2230e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2240e3bf489SRoman Kapl } 2250e3bf489SRoman Kapl 2260e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2270e3bf489SRoman Kapl { 2280e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2290e3bf489SRoman Kapl } 2300e3bf489SRoman Kapl 231fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 232fcf5ef2aSThomas Huth { 233fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 234fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 235fcf5ef2aSThomas Huth ctx->access_type = access_type; 236fcf5ef2aSThomas Huth } 237fcf5ef2aSThomas Huth } 238fcf5ef2aSThomas Huth 239fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 240fcf5ef2aSThomas Huth { 241fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 242fcf5ef2aSThomas Huth nip = (uint32_t)nip; 243fcf5ef2aSThomas Huth } 244fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 245fcf5ef2aSThomas Huth } 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 248fcf5ef2aSThomas Huth { 249fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 250fcf5ef2aSThomas Huth 251efe843d8SDavid Gibson /* 252efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 253efe843d8SDavid Gibson * faulting instruction 254fcf5ef2aSThomas Huth */ 255fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 256b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 257fcf5ef2aSThomas Huth } 258fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 259fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 260fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 261fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 262fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 263fcf5ef2aSThomas Huth ctx->exception = (excp); 264fcf5ef2aSThomas Huth } 265fcf5ef2aSThomas Huth 266fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 267fcf5ef2aSThomas Huth { 268fcf5ef2aSThomas Huth TCGv_i32 t0; 269fcf5ef2aSThomas Huth 270efe843d8SDavid Gibson /* 271efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 272efe843d8SDavid Gibson * faulting instruction 273fcf5ef2aSThomas Huth */ 274fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 275b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 278fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 279fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 280fcf5ef2aSThomas Huth ctx->exception = (excp); 281fcf5ef2aSThomas Huth } 282fcf5ef2aSThomas Huth 283fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 284fcf5ef2aSThomas Huth target_ulong nip) 285fcf5ef2aSThomas Huth { 286fcf5ef2aSThomas Huth TCGv_i32 t0; 287fcf5ef2aSThomas Huth 288fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 289fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 290fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 291fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 292fcf5ef2aSThomas Huth ctx->exception = (excp); 293fcf5ef2aSThomas Huth } 294fcf5ef2aSThomas Huth 295e150ac89SRoman Kapl /* 296e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 297e150ac89SRoman Kapl * SPR registers for this exception. 298e150ac89SRoman Kapl * 299e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 300e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3010e3bf489SRoman Kapl */ 302e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3030e3bf489SRoman Kapl { 3040e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3050e3bf489SRoman Kapl target_ulong dbsr = 0; 306e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3070e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 308e150ac89SRoman Kapl } else { 309e150ac89SRoman Kapl /* Must have been branch */ 3100e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3110e3bf489SRoman Kapl } 3120e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3130e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3140e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3150e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3160e3bf489SRoman Kapl tcg_temp_free(t0); 3170e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3180e3bf489SRoman Kapl } else { 319e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3200e3bf489SRoman Kapl } 3210e3bf489SRoman Kapl } 3220e3bf489SRoman Kapl 323fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 324fcf5ef2aSThomas Huth { 325fcf5ef2aSThomas Huth TCGv_i32 t0; 326fcf5ef2aSThomas Huth 327efe843d8SDavid Gibson /* 328efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 329efe843d8SDavid Gibson * faulting instruction 330fcf5ef2aSThomas Huth */ 331fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 332fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 333b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 334fcf5ef2aSThomas Huth } 335fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 336fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 337fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 338fcf5ef2aSThomas Huth } 339fcf5ef2aSThomas Huth 340fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341fcf5ef2aSThomas Huth { 342fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 343fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344fcf5ef2aSThomas Huth } 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347fcf5ef2aSThomas Huth { 348fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349fcf5ef2aSThomas Huth } 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352fcf5ef2aSThomas Huth { 353fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 354fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 357fcf5ef2aSThomas Huth /* Stop translation */ 358fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 359fcf5ef2aSThomas Huth { 360b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 361fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 362fcf5ef2aSThomas Huth } 363fcf5ef2aSThomas Huth 364fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 365fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 366fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 367fcf5ef2aSThomas Huth { 368fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 369fcf5ef2aSThomas Huth } 370fcf5ef2aSThomas Huth #endif 371fcf5ef2aSThomas Huth 372fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 373fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 374fcf5ef2aSThomas Huth 375fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 376fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 377fcf5ef2aSThomas Huth 378fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 379fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 380fcf5ef2aSThomas Huth 381fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 382fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 383fcf5ef2aSThomas Huth 384fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 385fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 386fcf5ef2aSThomas Huth 387fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 388fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 389fcf5ef2aSThomas Huth 390fcf5ef2aSThomas Huth typedef struct opcode_t { 391fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 392fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 393fcf5ef2aSThomas Huth unsigned char pad[4]; 394fcf5ef2aSThomas Huth #endif 395fcf5ef2aSThomas Huth opc_handler_t handler; 396fcf5ef2aSThomas Huth const char *oname; 397fcf5ef2aSThomas Huth } opcode_t; 398fcf5ef2aSThomas Huth 399fcf5ef2aSThomas Huth /* Helpers for priv. check */ 400fcf5ef2aSThomas Huth #define GEN_PRIV \ 401fcf5ef2aSThomas Huth do { \ 402fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 403fcf5ef2aSThomas Huth } while (0) 404fcf5ef2aSThomas Huth 405fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 406fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 407fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 408fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 409fcf5ef2aSThomas Huth #else 410fcf5ef2aSThomas Huth #define CHK_HV \ 411fcf5ef2aSThomas Huth do { \ 412fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 413fcf5ef2aSThomas Huth GEN_PRIV; \ 414fcf5ef2aSThomas Huth } \ 415fcf5ef2aSThomas Huth } while (0) 416fcf5ef2aSThomas Huth #define CHK_SV \ 417fcf5ef2aSThomas Huth do { \ 418fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 419fcf5ef2aSThomas Huth GEN_PRIV; \ 420fcf5ef2aSThomas Huth } \ 421fcf5ef2aSThomas Huth } while (0) 422fcf5ef2aSThomas Huth #define CHK_HVRM \ 423fcf5ef2aSThomas Huth do { \ 424fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 425fcf5ef2aSThomas Huth GEN_PRIV; \ 426fcf5ef2aSThomas Huth } \ 427fcf5ef2aSThomas Huth } while (0) 428fcf5ef2aSThomas Huth #endif 429fcf5ef2aSThomas Huth 430fcf5ef2aSThomas Huth #define CHK_NONE 431fcf5ef2aSThomas Huth 432fcf5ef2aSThomas Huth /*****************************************************************************/ 433fcf5ef2aSThomas Huth /* PowerPC instructions table */ 434fcf5ef2aSThomas Huth 435fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 436fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 437fcf5ef2aSThomas Huth { \ 438fcf5ef2aSThomas Huth .opc1 = op1, \ 439fcf5ef2aSThomas Huth .opc2 = op2, \ 440fcf5ef2aSThomas Huth .opc3 = op3, \ 441fcf5ef2aSThomas Huth .opc4 = 0xff, \ 442fcf5ef2aSThomas Huth .handler = { \ 443fcf5ef2aSThomas Huth .inval1 = invl, \ 444fcf5ef2aSThomas Huth .type = _typ, \ 445fcf5ef2aSThomas Huth .type2 = _typ2, \ 446fcf5ef2aSThomas Huth .handler = &gen_##name, \ 447fcf5ef2aSThomas Huth .oname = stringify(name), \ 448fcf5ef2aSThomas Huth }, \ 449fcf5ef2aSThomas Huth .oname = stringify(name), \ 450fcf5ef2aSThomas Huth } 451fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 452fcf5ef2aSThomas Huth { \ 453fcf5ef2aSThomas Huth .opc1 = op1, \ 454fcf5ef2aSThomas Huth .opc2 = op2, \ 455fcf5ef2aSThomas Huth .opc3 = op3, \ 456fcf5ef2aSThomas Huth .opc4 = 0xff, \ 457fcf5ef2aSThomas Huth .handler = { \ 458fcf5ef2aSThomas Huth .inval1 = invl1, \ 459fcf5ef2aSThomas Huth .inval2 = invl2, \ 460fcf5ef2aSThomas Huth .type = _typ, \ 461fcf5ef2aSThomas Huth .type2 = _typ2, \ 462fcf5ef2aSThomas Huth .handler = &gen_##name, \ 463fcf5ef2aSThomas Huth .oname = stringify(name), \ 464fcf5ef2aSThomas Huth }, \ 465fcf5ef2aSThomas Huth .oname = stringify(name), \ 466fcf5ef2aSThomas Huth } 467fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 468fcf5ef2aSThomas Huth { \ 469fcf5ef2aSThomas Huth .opc1 = op1, \ 470fcf5ef2aSThomas Huth .opc2 = op2, \ 471fcf5ef2aSThomas Huth .opc3 = op3, \ 472fcf5ef2aSThomas Huth .opc4 = 0xff, \ 473fcf5ef2aSThomas Huth .handler = { \ 474fcf5ef2aSThomas Huth .inval1 = invl, \ 475fcf5ef2aSThomas Huth .type = _typ, \ 476fcf5ef2aSThomas Huth .type2 = _typ2, \ 477fcf5ef2aSThomas Huth .handler = &gen_##name, \ 478fcf5ef2aSThomas Huth .oname = onam, \ 479fcf5ef2aSThomas Huth }, \ 480fcf5ef2aSThomas Huth .oname = onam, \ 481fcf5ef2aSThomas Huth } 482fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 483fcf5ef2aSThomas Huth { \ 484fcf5ef2aSThomas Huth .opc1 = op1, \ 485fcf5ef2aSThomas Huth .opc2 = op2, \ 486fcf5ef2aSThomas Huth .opc3 = op3, \ 487fcf5ef2aSThomas Huth .opc4 = op4, \ 488fcf5ef2aSThomas Huth .handler = { \ 489fcf5ef2aSThomas Huth .inval1 = invl, \ 490fcf5ef2aSThomas Huth .type = _typ, \ 491fcf5ef2aSThomas Huth .type2 = _typ2, \ 492fcf5ef2aSThomas Huth .handler = &gen_##name, \ 493fcf5ef2aSThomas Huth .oname = stringify(name), \ 494fcf5ef2aSThomas Huth }, \ 495fcf5ef2aSThomas Huth .oname = stringify(name), \ 496fcf5ef2aSThomas Huth } 497fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 498fcf5ef2aSThomas Huth { \ 499fcf5ef2aSThomas Huth .opc1 = op1, \ 500fcf5ef2aSThomas Huth .opc2 = op2, \ 501fcf5ef2aSThomas Huth .opc3 = op3, \ 502fcf5ef2aSThomas Huth .opc4 = op4, \ 503fcf5ef2aSThomas Huth .handler = { \ 504fcf5ef2aSThomas Huth .inval1 = invl, \ 505fcf5ef2aSThomas Huth .type = _typ, \ 506fcf5ef2aSThomas Huth .type2 = _typ2, \ 507fcf5ef2aSThomas Huth .handler = &gen_##name, \ 508fcf5ef2aSThomas Huth .oname = onam, \ 509fcf5ef2aSThomas Huth }, \ 510fcf5ef2aSThomas Huth .oname = onam, \ 511fcf5ef2aSThomas Huth } 512fcf5ef2aSThomas Huth #else 513fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 514fcf5ef2aSThomas Huth { \ 515fcf5ef2aSThomas Huth .opc1 = op1, \ 516fcf5ef2aSThomas Huth .opc2 = op2, \ 517fcf5ef2aSThomas Huth .opc3 = op3, \ 518fcf5ef2aSThomas Huth .opc4 = 0xff, \ 519fcf5ef2aSThomas Huth .handler = { \ 520fcf5ef2aSThomas Huth .inval1 = invl, \ 521fcf5ef2aSThomas Huth .type = _typ, \ 522fcf5ef2aSThomas Huth .type2 = _typ2, \ 523fcf5ef2aSThomas Huth .handler = &gen_##name, \ 524fcf5ef2aSThomas Huth }, \ 525fcf5ef2aSThomas Huth .oname = stringify(name), \ 526fcf5ef2aSThomas Huth } 527fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 528fcf5ef2aSThomas Huth { \ 529fcf5ef2aSThomas Huth .opc1 = op1, \ 530fcf5ef2aSThomas Huth .opc2 = op2, \ 531fcf5ef2aSThomas Huth .opc3 = op3, \ 532fcf5ef2aSThomas Huth .opc4 = 0xff, \ 533fcf5ef2aSThomas Huth .handler = { \ 534fcf5ef2aSThomas Huth .inval1 = invl1, \ 535fcf5ef2aSThomas Huth .inval2 = invl2, \ 536fcf5ef2aSThomas Huth .type = _typ, \ 537fcf5ef2aSThomas Huth .type2 = _typ2, \ 538fcf5ef2aSThomas Huth .handler = &gen_##name, \ 539fcf5ef2aSThomas Huth }, \ 540fcf5ef2aSThomas Huth .oname = stringify(name), \ 541fcf5ef2aSThomas Huth } 542fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 543fcf5ef2aSThomas Huth { \ 544fcf5ef2aSThomas Huth .opc1 = op1, \ 545fcf5ef2aSThomas Huth .opc2 = op2, \ 546fcf5ef2aSThomas Huth .opc3 = op3, \ 547fcf5ef2aSThomas Huth .opc4 = 0xff, \ 548fcf5ef2aSThomas Huth .handler = { \ 549fcf5ef2aSThomas Huth .inval1 = invl, \ 550fcf5ef2aSThomas Huth .type = _typ, \ 551fcf5ef2aSThomas Huth .type2 = _typ2, \ 552fcf5ef2aSThomas Huth .handler = &gen_##name, \ 553fcf5ef2aSThomas Huth }, \ 554fcf5ef2aSThomas Huth .oname = onam, \ 555fcf5ef2aSThomas Huth } 556fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 557fcf5ef2aSThomas Huth { \ 558fcf5ef2aSThomas Huth .opc1 = op1, \ 559fcf5ef2aSThomas Huth .opc2 = op2, \ 560fcf5ef2aSThomas Huth .opc3 = op3, \ 561fcf5ef2aSThomas Huth .opc4 = op4, \ 562fcf5ef2aSThomas Huth .handler = { \ 563fcf5ef2aSThomas Huth .inval1 = invl, \ 564fcf5ef2aSThomas Huth .type = _typ, \ 565fcf5ef2aSThomas Huth .type2 = _typ2, \ 566fcf5ef2aSThomas Huth .handler = &gen_##name, \ 567fcf5ef2aSThomas Huth }, \ 568fcf5ef2aSThomas Huth .oname = stringify(name), \ 569fcf5ef2aSThomas Huth } 570fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 571fcf5ef2aSThomas Huth { \ 572fcf5ef2aSThomas Huth .opc1 = op1, \ 573fcf5ef2aSThomas Huth .opc2 = op2, \ 574fcf5ef2aSThomas Huth .opc3 = op3, \ 575fcf5ef2aSThomas Huth .opc4 = op4, \ 576fcf5ef2aSThomas Huth .handler = { \ 577fcf5ef2aSThomas Huth .inval1 = invl, \ 578fcf5ef2aSThomas Huth .type = _typ, \ 579fcf5ef2aSThomas Huth .type2 = _typ2, \ 580fcf5ef2aSThomas Huth .handler = &gen_##name, \ 581fcf5ef2aSThomas Huth }, \ 582fcf5ef2aSThomas Huth .oname = onam, \ 583fcf5ef2aSThomas Huth } 584fcf5ef2aSThomas Huth #endif 585fcf5ef2aSThomas Huth 586fcf5ef2aSThomas Huth /* Invalid instruction */ 587fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 588fcf5ef2aSThomas Huth { 589fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 590fcf5ef2aSThomas Huth } 591fcf5ef2aSThomas Huth 592fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 593fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 594fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 595fcf5ef2aSThomas Huth .type = PPC_NONE, 596fcf5ef2aSThomas Huth .type2 = PPC_NONE, 597fcf5ef2aSThomas Huth .handler = gen_invalid, 598fcf5ef2aSThomas Huth }; 599fcf5ef2aSThomas Huth 600fcf5ef2aSThomas Huth /*** Integer comparison ***/ 601fcf5ef2aSThomas Huth 602fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 603fcf5ef2aSThomas Huth { 604fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 605b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 606b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 607fcf5ef2aSThomas Huth 608b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 609b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 610efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 611efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 612b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 613efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 614efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 615b62b3686Spbonzini@redhat.com 616b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 617fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 618b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 619fcf5ef2aSThomas Huth 620fcf5ef2aSThomas Huth tcg_temp_free(t0); 621b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 622b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 623fcf5ef2aSThomas Huth } 624fcf5ef2aSThomas Huth 625fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 626fcf5ef2aSThomas Huth { 627fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 628fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 629fcf5ef2aSThomas Huth tcg_temp_free(t0); 630fcf5ef2aSThomas Huth } 631fcf5ef2aSThomas Huth 632fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 633fcf5ef2aSThomas Huth { 634fcf5ef2aSThomas Huth TCGv t0, t1; 635fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 636fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 637fcf5ef2aSThomas Huth if (s) { 638fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 639fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 640fcf5ef2aSThomas Huth } else { 641fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 642fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 643fcf5ef2aSThomas Huth } 644fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 645fcf5ef2aSThomas Huth tcg_temp_free(t1); 646fcf5ef2aSThomas Huth tcg_temp_free(t0); 647fcf5ef2aSThomas Huth } 648fcf5ef2aSThomas Huth 649fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 650fcf5ef2aSThomas Huth { 651fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 652fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 653fcf5ef2aSThomas Huth tcg_temp_free(t0); 654fcf5ef2aSThomas Huth } 655fcf5ef2aSThomas Huth 656fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 657fcf5ef2aSThomas Huth { 658fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 659fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 660fcf5ef2aSThomas Huth } else { 661fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 662fcf5ef2aSThomas Huth } 663fcf5ef2aSThomas Huth } 664fcf5ef2aSThomas Huth 665fcf5ef2aSThomas Huth /* cmp */ 666fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 667fcf5ef2aSThomas Huth { 668fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 669fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 670fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 671fcf5ef2aSThomas Huth } else { 672fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 673fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 674fcf5ef2aSThomas Huth } 675fcf5ef2aSThomas Huth } 676fcf5ef2aSThomas Huth 677fcf5ef2aSThomas Huth /* cmpi */ 678fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 679fcf5ef2aSThomas Huth { 680fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 681fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 682fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 683fcf5ef2aSThomas Huth } else { 684fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 685fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 686fcf5ef2aSThomas Huth } 687fcf5ef2aSThomas Huth } 688fcf5ef2aSThomas Huth 689fcf5ef2aSThomas Huth /* cmpl */ 690fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 691fcf5ef2aSThomas Huth { 692fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 693fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 694fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 695fcf5ef2aSThomas Huth } else { 696fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 697fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 698fcf5ef2aSThomas Huth } 699fcf5ef2aSThomas Huth } 700fcf5ef2aSThomas Huth 701fcf5ef2aSThomas Huth /* cmpli */ 702fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 703fcf5ef2aSThomas Huth { 704fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 705fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 706fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 707fcf5ef2aSThomas Huth } else { 708fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 709fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 710fcf5ef2aSThomas Huth } 711fcf5ef2aSThomas Huth } 712fcf5ef2aSThomas Huth 713fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 714fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 715fcf5ef2aSThomas Huth { 716fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 717fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 718fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 719fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 720fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 721fcf5ef2aSThomas Huth 722fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 723fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 724fcf5ef2aSThomas Huth 725fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 726fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 727fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 728fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 729fcf5ef2aSThomas Huth 730fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 731fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 732fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 733fcf5ef2aSThomas Huth 734fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 735fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 736fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 737fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 738fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 739fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 740fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 741fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 742fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 743fcf5ef2aSThomas Huth } 744efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 745fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 746fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 747fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 748fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 749fcf5ef2aSThomas Huth } 750fcf5ef2aSThomas Huth 751fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 752fcf5ef2aSThomas Huth /* cmpeqb */ 753fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 754fcf5ef2aSThomas Huth { 755fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 756fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 757fcf5ef2aSThomas Huth } 758fcf5ef2aSThomas Huth #endif 759fcf5ef2aSThomas Huth 760fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 761fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 762fcf5ef2aSThomas Huth { 763fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 764fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 765fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 766fcf5ef2aSThomas Huth TCGv zr; 767fcf5ef2aSThomas Huth 768fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 769fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 770fcf5ef2aSThomas Huth 771fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 772fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 773fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 774fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 775fcf5ef2aSThomas Huth tcg_temp_free(zr); 776fcf5ef2aSThomas Huth tcg_temp_free(t0); 777fcf5ef2aSThomas Huth } 778fcf5ef2aSThomas Huth 779fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 780fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 781fcf5ef2aSThomas Huth { 782fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 783fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 784fcf5ef2aSThomas Huth } 785fcf5ef2aSThomas Huth 786fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 787fcf5ef2aSThomas Huth 788fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 789fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 790fcf5ef2aSThomas Huth { 791fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 792fcf5ef2aSThomas Huth 793fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 794fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 795fcf5ef2aSThomas Huth if (sub) { 796fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 797fcf5ef2aSThomas Huth } else { 798fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 799fcf5ef2aSThomas Huth } 800fcf5ef2aSThomas Huth tcg_temp_free(t0); 801fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 802dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 803dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 804dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 805fcf5ef2aSThomas Huth } 806dc0ad844SNikunj A Dadhania } else { 807dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 808dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 809dc0ad844SNikunj A Dadhania } 81038a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 811dc0ad844SNikunj A Dadhania } 812fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 813fcf5ef2aSThomas Huth } 814fcf5ef2aSThomas Huth 8156b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8166b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 8174c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 8186b10d008SNikunj A Dadhania { 8196b10d008SNikunj A Dadhania TCGv t0; 8206b10d008SNikunj A Dadhania 8216b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8226b10d008SNikunj A Dadhania return; 8236b10d008SNikunj A Dadhania } 8246b10d008SNikunj A Dadhania 8256b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 82633903d0aSNikunj A Dadhania if (sub) { 82733903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 82833903d0aSNikunj A Dadhania } else { 8296b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 83033903d0aSNikunj A Dadhania } 8316b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 8324c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 8336b10d008SNikunj A Dadhania tcg_temp_free(t0); 8346b10d008SNikunj A Dadhania } 8356b10d008SNikunj A Dadhania 836fcf5ef2aSThomas Huth /* Common add function */ 837fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 8384c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 8394c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 840fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 841fcf5ef2aSThomas Huth { 842fcf5ef2aSThomas Huth TCGv t0 = ret; 843fcf5ef2aSThomas Huth 844fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 845fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 846fcf5ef2aSThomas Huth } 847fcf5ef2aSThomas Huth 848fcf5ef2aSThomas Huth if (compute_ca) { 849fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 850efe843d8SDavid Gibson /* 851efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 852efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 853efe843d8SDavid Gibson * produce the carry into bit 32. 854efe843d8SDavid Gibson */ 855fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 856fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 857fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 858fcf5ef2aSThomas Huth if (add_ca) { 8594c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 860fcf5ef2aSThomas Huth } 8614c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 862fcf5ef2aSThomas Huth tcg_temp_free(t1); 8634c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 8646b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 8654c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 8666b10d008SNikunj A Dadhania } 867fcf5ef2aSThomas Huth } else { 868fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 869fcf5ef2aSThomas Huth if (add_ca) { 8704c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 8714c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 872fcf5ef2aSThomas Huth } else { 8734c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 874fcf5ef2aSThomas Huth } 8754c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 876fcf5ef2aSThomas Huth tcg_temp_free(zero); 877fcf5ef2aSThomas Huth } 878fcf5ef2aSThomas Huth } else { 879fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 880fcf5ef2aSThomas Huth if (add_ca) { 8814c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 882fcf5ef2aSThomas Huth } 883fcf5ef2aSThomas Huth } 884fcf5ef2aSThomas Huth 885fcf5ef2aSThomas Huth if (compute_ov) { 886fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 887fcf5ef2aSThomas Huth } 888fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 889fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 890fcf5ef2aSThomas Huth } 891fcf5ef2aSThomas Huth 89211f4e8f8SRichard Henderson if (t0 != ret) { 893fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 894fcf5ef2aSThomas Huth tcg_temp_free(t0); 895fcf5ef2aSThomas Huth } 896fcf5ef2aSThomas Huth } 897fcf5ef2aSThomas Huth /* Add functions with two operands */ 8984c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 899fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 900fcf5ef2aSThomas Huth { \ 901fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 902fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 9034c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 904fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 905fcf5ef2aSThomas Huth } 906fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 9074c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 908fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 909fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 910fcf5ef2aSThomas Huth { \ 911fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 912fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 913fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 9144c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 915fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 916fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 917fcf5ef2aSThomas Huth } 918fcf5ef2aSThomas Huth 919fcf5ef2aSThomas Huth /* add add. addo addo. */ 9204c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 9214c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 922fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 9234c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 9244c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 925fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 9264c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 9274c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 928fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 9294c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 9304c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 9314c5920afSSuraj Jitindar Singh /* addex */ 9324c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 933fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 9344c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 9354c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 936fcf5ef2aSThomas Huth /* addi */ 937fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 938fcf5ef2aSThomas Huth { 939fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 940fcf5ef2aSThomas Huth 941fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 942fcf5ef2aSThomas Huth /* li case */ 943fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 944fcf5ef2aSThomas Huth } else { 945fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 946fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 947fcf5ef2aSThomas Huth } 948fcf5ef2aSThomas Huth } 949fcf5ef2aSThomas Huth /* addic addic.*/ 950fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 951fcf5ef2aSThomas Huth { 952fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 953fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 9544c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 955fcf5ef2aSThomas Huth tcg_temp_free(c); 956fcf5ef2aSThomas Huth } 957fcf5ef2aSThomas Huth 958fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 959fcf5ef2aSThomas Huth { 960fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 961fcf5ef2aSThomas Huth } 962fcf5ef2aSThomas Huth 963fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 964fcf5ef2aSThomas Huth { 965fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 966fcf5ef2aSThomas Huth } 967fcf5ef2aSThomas Huth 968fcf5ef2aSThomas Huth /* addis */ 969fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 970fcf5ef2aSThomas Huth { 971fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 972fcf5ef2aSThomas Huth 973fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 974fcf5ef2aSThomas Huth /* lis case */ 975fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 976fcf5ef2aSThomas Huth } else { 977fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 978fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 979fcf5ef2aSThomas Huth } 980fcf5ef2aSThomas Huth } 981fcf5ef2aSThomas Huth 982fcf5ef2aSThomas Huth /* addpcis */ 983fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 984fcf5ef2aSThomas Huth { 985fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 986fcf5ef2aSThomas Huth 987b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 988fcf5ef2aSThomas Huth } 989fcf5ef2aSThomas Huth 990fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 991fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 992fcf5ef2aSThomas Huth { 993fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 994fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 995fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 996fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 997fcf5ef2aSThomas Huth 998fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 999fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1000fcf5ef2aSThomas Huth if (sign) { 1001fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1002fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1003fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1004fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1005fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1006fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1007fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1008fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1009fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1010fcf5ef2aSThomas Huth } else { 1011fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1012fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1013fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1014fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1015fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1016fcf5ef2aSThomas Huth } 1017fcf5ef2aSThomas Huth if (compute_ov) { 1018fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1019c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1020c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1021c44027ffSNikunj A Dadhania } 1022fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1023fcf5ef2aSThomas Huth } 1024fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1025fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1026fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1027fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1028fcf5ef2aSThomas Huth 1029efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1030fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1031fcf5ef2aSThomas Huth } 1032efe843d8SDavid Gibson } 1033fcf5ef2aSThomas Huth /* Div functions */ 1034fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1035fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1036fcf5ef2aSThomas Huth { \ 1037fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1038fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1039fcf5ef2aSThomas Huth sign, compute_ov); \ 1040fcf5ef2aSThomas Huth } 1041fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1042fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1043fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1044fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1045fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1046fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1047fcf5ef2aSThomas Huth 1048fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1049fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1050fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1051fcf5ef2aSThomas Huth { \ 1052fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1053fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1054fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1055fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1056fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1057fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1058fcf5ef2aSThomas Huth } \ 1059fcf5ef2aSThomas Huth } 1060fcf5ef2aSThomas Huth 1061fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1062fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1063fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1064fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1065fcf5ef2aSThomas Huth 1066fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1067fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1068fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1069fcf5ef2aSThomas Huth { 1070fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1071fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1072fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1073fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1074fcf5ef2aSThomas Huth 1075fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1076fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1077fcf5ef2aSThomas Huth if (sign) { 1078fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1079fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1080fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1081fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1082fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1083fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1084fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1085fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1086fcf5ef2aSThomas Huth } else { 1087fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1088fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1089fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1090fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1091fcf5ef2aSThomas Huth } 1092fcf5ef2aSThomas Huth if (compute_ov) { 1093fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1094c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1095c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1096c44027ffSNikunj A Dadhania } 1097fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1098fcf5ef2aSThomas Huth } 1099fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1100fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1101fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1102fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1103fcf5ef2aSThomas Huth 1104efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1105fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1106fcf5ef2aSThomas Huth } 1107efe843d8SDavid Gibson } 1108fcf5ef2aSThomas Huth 1109fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1110fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1111fcf5ef2aSThomas Huth { \ 1112fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1113fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1114fcf5ef2aSThomas Huth sign, compute_ov); \ 1115fcf5ef2aSThomas Huth } 1116c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1117fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1118fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1119c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1120fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1121fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1122fcf5ef2aSThomas Huth 1123fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1124fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1125fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1126fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1127fcf5ef2aSThomas Huth #endif 1128fcf5ef2aSThomas Huth 1129fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1130fcf5ef2aSThomas Huth TCGv arg2, int sign) 1131fcf5ef2aSThomas Huth { 1132fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1133fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1134fcf5ef2aSThomas Huth 1135fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1136fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1137fcf5ef2aSThomas Huth if (sign) { 1138fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1139fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1140fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1141fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1142fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1143fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1144fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1145fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1146fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1147fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1148fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1149fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1150fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1151fcf5ef2aSThomas Huth } else { 1152fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1153fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1154fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1155fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1156fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1157fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1158fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1159fcf5ef2aSThomas Huth } 1160fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1161fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1162fcf5ef2aSThomas Huth } 1163fcf5ef2aSThomas Huth 1164fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1165fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1166fcf5ef2aSThomas Huth { \ 1167fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1168fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1169fcf5ef2aSThomas Huth sign); \ 1170fcf5ef2aSThomas Huth } 1171fcf5ef2aSThomas Huth 1172fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1173fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1174fcf5ef2aSThomas Huth 1175fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1176fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1177fcf5ef2aSThomas Huth TCGv arg2, int sign) 1178fcf5ef2aSThomas Huth { 1179fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1180fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1181fcf5ef2aSThomas Huth 1182fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1183fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1184fcf5ef2aSThomas Huth if (sign) { 1185fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1186fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1187fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1188fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1189fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1190fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1191fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1192fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1193fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1194fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1195fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1196fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1197fcf5ef2aSThomas Huth } else { 1198fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1199fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1200fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1201fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1202fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1203fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1204fcf5ef2aSThomas Huth } 1205fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1206fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1207fcf5ef2aSThomas Huth } 1208fcf5ef2aSThomas Huth 1209fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1210fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1211fcf5ef2aSThomas Huth { \ 1212fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1213fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1214fcf5ef2aSThomas Huth sign); \ 1215fcf5ef2aSThomas Huth } 1216fcf5ef2aSThomas Huth 1217fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1218fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1219fcf5ef2aSThomas Huth #endif 1220fcf5ef2aSThomas Huth 1221fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1222fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1223fcf5ef2aSThomas Huth { 1224fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1225fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1226fcf5ef2aSThomas Huth 1227fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1228fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1229fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1230fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1231fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1232fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1233efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1234fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1235fcf5ef2aSThomas Huth } 1236efe843d8SDavid Gibson } 1237fcf5ef2aSThomas Huth 1238fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1239fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1240fcf5ef2aSThomas Huth { 1241fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1242fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1243fcf5ef2aSThomas Huth 1244fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1245fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1246fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1247fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1248fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1249fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1250efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1251fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1252fcf5ef2aSThomas Huth } 1253efe843d8SDavid Gibson } 1254fcf5ef2aSThomas Huth 1255fcf5ef2aSThomas Huth /* mullw mullw. */ 1256fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1257fcf5ef2aSThomas Huth { 1258fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1259fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1260fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1261fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1262fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1263fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1264fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1265fcf5ef2aSThomas Huth tcg_temp_free(t0); 1266fcf5ef2aSThomas Huth tcg_temp_free(t1); 1267fcf5ef2aSThomas Huth #else 1268fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1269fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1270fcf5ef2aSThomas Huth #endif 1271efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1272fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1273fcf5ef2aSThomas Huth } 1274efe843d8SDavid Gibson } 1275fcf5ef2aSThomas Huth 1276fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1277fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1278fcf5ef2aSThomas Huth { 1279fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1280fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1281fcf5ef2aSThomas Huth 1282fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1283fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1284fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1285fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1286fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1287fcf5ef2aSThomas Huth #else 1288fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1289fcf5ef2aSThomas Huth #endif 1290fcf5ef2aSThomas Huth 1291fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1292fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1293fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 129461aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 129561aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 129661aa9a69SNikunj A Dadhania } 1297fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1298fcf5ef2aSThomas Huth 1299fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1300fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1301efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1302fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1303fcf5ef2aSThomas Huth } 1304efe843d8SDavid Gibson } 1305fcf5ef2aSThomas Huth 1306fcf5ef2aSThomas Huth /* mulli */ 1307fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1308fcf5ef2aSThomas Huth { 1309fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1310fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1311fcf5ef2aSThomas Huth } 1312fcf5ef2aSThomas Huth 1313fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1314fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1315fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1316fcf5ef2aSThomas Huth { 1317fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1318fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1319fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1320fcf5ef2aSThomas Huth tcg_temp_free(lo); 1321fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1322fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1323fcf5ef2aSThomas Huth } 1324fcf5ef2aSThomas Huth } 1325fcf5ef2aSThomas Huth 1326fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1327fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1328fcf5ef2aSThomas Huth { 1329fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1330fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1331fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1332fcf5ef2aSThomas Huth tcg_temp_free(lo); 1333fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1334fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1335fcf5ef2aSThomas Huth } 1336fcf5ef2aSThomas Huth } 1337fcf5ef2aSThomas Huth 1338fcf5ef2aSThomas Huth /* mulld mulld. */ 1339fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1340fcf5ef2aSThomas Huth { 1341fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1342fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1343efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1344fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1345fcf5ef2aSThomas Huth } 1346efe843d8SDavid Gibson } 1347fcf5ef2aSThomas Huth 1348fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1349fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1350fcf5ef2aSThomas Huth { 1351fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1352fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1353fcf5ef2aSThomas Huth 1354fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1355fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1356fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1357fcf5ef2aSThomas Huth 1358fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1359fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 136061aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 136161aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 136261aa9a69SNikunj A Dadhania } 1363fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1364fcf5ef2aSThomas Huth 1365fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1366fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1367fcf5ef2aSThomas Huth 1368fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1369fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1370fcf5ef2aSThomas Huth } 1371fcf5ef2aSThomas Huth } 1372fcf5ef2aSThomas Huth #endif 1373fcf5ef2aSThomas Huth 1374fcf5ef2aSThomas Huth /* Common subf function */ 1375fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1376fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1377fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1378fcf5ef2aSThomas Huth { 1379fcf5ef2aSThomas Huth TCGv t0 = ret; 1380fcf5ef2aSThomas Huth 1381fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1382fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1383fcf5ef2aSThomas Huth } 1384fcf5ef2aSThomas Huth 1385fcf5ef2aSThomas Huth if (compute_ca) { 1386fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1387fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1388efe843d8SDavid Gibson /* 1389efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1390efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1391efe843d8SDavid Gibson * produce the carry into bit 32. 1392efe843d8SDavid Gibson */ 1393fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1394fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1395fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1396fcf5ef2aSThomas Huth if (add_ca) { 1397fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1398fcf5ef2aSThomas Huth } else { 1399fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1400fcf5ef2aSThomas Huth } 1401fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1402fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1403fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1404fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1405fcf5ef2aSThomas Huth tcg_temp_free(t1); 1406e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 140733903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 140833903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 140933903d0aSNikunj A Dadhania } 1410fcf5ef2aSThomas Huth } else if (add_ca) { 1411fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1412fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1413fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1414fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1415fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 14164c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1417fcf5ef2aSThomas Huth tcg_temp_free(zero); 1418fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1419fcf5ef2aSThomas Huth } else { 1420fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1421fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 14224c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1423fcf5ef2aSThomas Huth } 1424fcf5ef2aSThomas Huth } else if (add_ca) { 1425efe843d8SDavid Gibson /* 1426efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 1427efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1428efe843d8SDavid Gibson */ 1429fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1430fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1431fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1432fcf5ef2aSThomas Huth } else { 1433fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1434fcf5ef2aSThomas Huth } 1435fcf5ef2aSThomas Huth 1436fcf5ef2aSThomas Huth if (compute_ov) { 1437fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1438fcf5ef2aSThomas Huth } 1439fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1440fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1441fcf5ef2aSThomas Huth } 1442fcf5ef2aSThomas Huth 144311f4e8f8SRichard Henderson if (t0 != ret) { 1444fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1445fcf5ef2aSThomas Huth tcg_temp_free(t0); 1446fcf5ef2aSThomas Huth } 1447fcf5ef2aSThomas Huth } 1448fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1449fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1450fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1451fcf5ef2aSThomas Huth { \ 1452fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1453fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1454fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1455fcf5ef2aSThomas Huth } 1456fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1457fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1458fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1459fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1460fcf5ef2aSThomas Huth { \ 1461fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1462fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1463fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1464fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1465fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1466fcf5ef2aSThomas Huth } 1467fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1468fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1469fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1470fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1471fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1472fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1473fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1474fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1475fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1476fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1477fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1478fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1479fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1480fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1481fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1482fcf5ef2aSThomas Huth 1483fcf5ef2aSThomas Huth /* subfic */ 1484fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1485fcf5ef2aSThomas Huth { 1486fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1487fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1488fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1489fcf5ef2aSThomas Huth tcg_temp_free(c); 1490fcf5ef2aSThomas Huth } 1491fcf5ef2aSThomas Huth 1492fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1493fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1494fcf5ef2aSThomas Huth { 1495fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1496fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1497fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1498fcf5ef2aSThomas Huth tcg_temp_free(zero); 1499fcf5ef2aSThomas Huth } 1500fcf5ef2aSThomas Huth 1501fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1502fcf5ef2aSThomas Huth { 15031480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 15041480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 15051480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 15061480d71cSNikunj A Dadhania } 1507fcf5ef2aSThomas Huth } 1508fcf5ef2aSThomas Huth 1509fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1510fcf5ef2aSThomas Huth { 1511fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1512fcf5ef2aSThomas Huth } 1513fcf5ef2aSThomas Huth 1514fcf5ef2aSThomas Huth /*** Integer logical ***/ 1515fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1516fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1517fcf5ef2aSThomas Huth { \ 1518fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1519fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1520fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1521fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1522fcf5ef2aSThomas Huth } 1523fcf5ef2aSThomas Huth 1524fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1525fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1526fcf5ef2aSThomas Huth { \ 1527fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1528fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1529fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1530fcf5ef2aSThomas Huth } 1531fcf5ef2aSThomas Huth 1532fcf5ef2aSThomas Huth /* and & and. */ 1533fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1534fcf5ef2aSThomas Huth /* andc & andc. */ 1535fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1536fcf5ef2aSThomas Huth 1537fcf5ef2aSThomas Huth /* andi. */ 1538fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1539fcf5ef2aSThomas Huth { 1540efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1541efe843d8SDavid Gibson UIMM(ctx->opcode)); 1542fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1543fcf5ef2aSThomas Huth } 1544fcf5ef2aSThomas Huth 1545fcf5ef2aSThomas Huth /* andis. */ 1546fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1547fcf5ef2aSThomas Huth { 1548efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1549efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 1550fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1551fcf5ef2aSThomas Huth } 1552fcf5ef2aSThomas Huth 1553fcf5ef2aSThomas Huth /* cntlzw */ 1554fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1555fcf5ef2aSThomas Huth { 15569b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15579b8514e5SRichard Henderson 15589b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15599b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15609b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15619b8514e5SRichard Henderson tcg_temp_free_i32(t); 15629b8514e5SRichard Henderson 1563efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1564fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1565fcf5ef2aSThomas Huth } 1566efe843d8SDavid Gibson } 1567fcf5ef2aSThomas Huth 1568fcf5ef2aSThomas Huth /* cnttzw */ 1569fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1570fcf5ef2aSThomas Huth { 15719b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15729b8514e5SRichard Henderson 15739b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15749b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15759b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15769b8514e5SRichard Henderson tcg_temp_free_i32(t); 15779b8514e5SRichard Henderson 1578fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1579fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1580fcf5ef2aSThomas Huth } 1581fcf5ef2aSThomas Huth } 1582fcf5ef2aSThomas Huth 1583fcf5ef2aSThomas Huth /* eqv & eqv. */ 1584fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1585fcf5ef2aSThomas Huth /* extsb & extsb. */ 1586fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1587fcf5ef2aSThomas Huth /* extsh & extsh. */ 1588fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1589fcf5ef2aSThomas Huth /* nand & nand. */ 1590fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1591fcf5ef2aSThomas Huth /* nor & nor. */ 1592fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1593fcf5ef2aSThomas Huth 1594fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1595fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1596fcf5ef2aSThomas Huth { 1597fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1598fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1599fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1600fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1601fcf5ef2aSThomas Huth 1602fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1603b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1604fcf5ef2aSThomas Huth } 1605fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1606fcf5ef2aSThomas Huth 1607fcf5ef2aSThomas Huth /* or & or. */ 1608fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1609fcf5ef2aSThomas Huth { 1610fcf5ef2aSThomas Huth int rs, ra, rb; 1611fcf5ef2aSThomas Huth 1612fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1613fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1614fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1615fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1616fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1617efe843d8SDavid Gibson if (rs != rb) { 1618fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1619efe843d8SDavid Gibson } else { 1620fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1621efe843d8SDavid Gibson } 1622efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1623fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1624efe843d8SDavid Gibson } 1625fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1626fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1627fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1628fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1629fcf5ef2aSThomas Huth int prio = 0; 1630fcf5ef2aSThomas Huth 1631fcf5ef2aSThomas Huth switch (rs) { 1632fcf5ef2aSThomas Huth case 1: 1633fcf5ef2aSThomas Huth /* Set process priority to low */ 1634fcf5ef2aSThomas Huth prio = 2; 1635fcf5ef2aSThomas Huth break; 1636fcf5ef2aSThomas Huth case 6: 1637fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1638fcf5ef2aSThomas Huth prio = 3; 1639fcf5ef2aSThomas Huth break; 1640fcf5ef2aSThomas Huth case 2: 1641fcf5ef2aSThomas Huth /* Set process priority to normal */ 1642fcf5ef2aSThomas Huth prio = 4; 1643fcf5ef2aSThomas Huth break; 1644fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1645fcf5ef2aSThomas Huth case 31: 1646fcf5ef2aSThomas Huth if (!ctx->pr) { 1647fcf5ef2aSThomas Huth /* Set process priority to very low */ 1648fcf5ef2aSThomas Huth prio = 1; 1649fcf5ef2aSThomas Huth } 1650fcf5ef2aSThomas Huth break; 1651fcf5ef2aSThomas Huth case 5: 1652fcf5ef2aSThomas Huth if (!ctx->pr) { 1653fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1654fcf5ef2aSThomas Huth prio = 5; 1655fcf5ef2aSThomas Huth } 1656fcf5ef2aSThomas Huth break; 1657fcf5ef2aSThomas Huth case 3: 1658fcf5ef2aSThomas Huth if (!ctx->pr) { 1659fcf5ef2aSThomas Huth /* Set process priority to high */ 1660fcf5ef2aSThomas Huth prio = 6; 1661fcf5ef2aSThomas Huth } 1662fcf5ef2aSThomas Huth break; 1663fcf5ef2aSThomas Huth case 7: 1664fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1665fcf5ef2aSThomas Huth /* Set process priority to very high */ 1666fcf5ef2aSThomas Huth prio = 7; 1667fcf5ef2aSThomas Huth } 1668fcf5ef2aSThomas Huth break; 1669fcf5ef2aSThomas Huth #endif 1670fcf5ef2aSThomas Huth default: 1671fcf5ef2aSThomas Huth break; 1672fcf5ef2aSThomas Huth } 1673fcf5ef2aSThomas Huth if (prio) { 1674fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1675fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1676fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1677fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1678fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1679fcf5ef2aSThomas Huth tcg_temp_free(t0); 1680fcf5ef2aSThomas Huth } 1681fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1682efe843d8SDavid Gibson /* 1683efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 1684efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 1685efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 1686efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 1687fcf5ef2aSThomas Huth */ 1688fcf5ef2aSThomas Huth gen_pause(ctx); 1689fcf5ef2aSThomas Huth #endif 1690fcf5ef2aSThomas Huth #endif 1691fcf5ef2aSThomas Huth } 1692fcf5ef2aSThomas Huth } 1693fcf5ef2aSThomas Huth /* orc & orc. */ 1694fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1695fcf5ef2aSThomas Huth 1696fcf5ef2aSThomas Huth /* xor & xor. */ 1697fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1698fcf5ef2aSThomas Huth { 1699fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1700efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 1701efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1702efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 1703efe843d8SDavid Gibson } else { 1704fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1705efe843d8SDavid Gibson } 1706efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1707fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1708fcf5ef2aSThomas Huth } 1709efe843d8SDavid Gibson } 1710fcf5ef2aSThomas Huth 1711fcf5ef2aSThomas Huth /* ori */ 1712fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1713fcf5ef2aSThomas Huth { 1714fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1715fcf5ef2aSThomas Huth 1716fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1717fcf5ef2aSThomas Huth return; 1718fcf5ef2aSThomas Huth } 1719fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1720fcf5ef2aSThomas Huth } 1721fcf5ef2aSThomas Huth 1722fcf5ef2aSThomas Huth /* oris */ 1723fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1724fcf5ef2aSThomas Huth { 1725fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1726fcf5ef2aSThomas Huth 1727fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1728fcf5ef2aSThomas Huth /* NOP */ 1729fcf5ef2aSThomas Huth return; 1730fcf5ef2aSThomas Huth } 1731efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1732efe843d8SDavid Gibson uimm << 16); 1733fcf5ef2aSThomas Huth } 1734fcf5ef2aSThomas Huth 1735fcf5ef2aSThomas Huth /* xori */ 1736fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1737fcf5ef2aSThomas Huth { 1738fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1739fcf5ef2aSThomas Huth 1740fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1741fcf5ef2aSThomas Huth /* NOP */ 1742fcf5ef2aSThomas Huth return; 1743fcf5ef2aSThomas Huth } 1744fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1745fcf5ef2aSThomas Huth } 1746fcf5ef2aSThomas Huth 1747fcf5ef2aSThomas Huth /* xoris */ 1748fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1749fcf5ef2aSThomas Huth { 1750fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1751fcf5ef2aSThomas Huth 1752fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1753fcf5ef2aSThomas Huth /* NOP */ 1754fcf5ef2aSThomas Huth return; 1755fcf5ef2aSThomas Huth } 1756efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1757efe843d8SDavid Gibson uimm << 16); 1758fcf5ef2aSThomas Huth } 1759fcf5ef2aSThomas Huth 1760fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1761fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1762fcf5ef2aSThomas Huth { 1763fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1764fcf5ef2aSThomas Huth } 1765fcf5ef2aSThomas Huth 1766fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1767fcf5ef2aSThomas Huth { 176879770002SRichard Henderson #if defined(TARGET_PPC64) 1769fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 177079770002SRichard Henderson #else 177179770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 177279770002SRichard Henderson #endif 1773fcf5ef2aSThomas Huth } 1774fcf5ef2aSThomas Huth 1775fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1776fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1777fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1778fcf5ef2aSThomas Huth { 177979770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1780fcf5ef2aSThomas Huth } 1781fcf5ef2aSThomas Huth #endif 1782fcf5ef2aSThomas Huth 1783fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1784fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1785fcf5ef2aSThomas Huth { 1786fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1787fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1788fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1789fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1790fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1791fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1792fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1793fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1794fcf5ef2aSThomas Huth tcg_temp_free(t0); 1795fcf5ef2aSThomas Huth } 1796fcf5ef2aSThomas Huth 1797fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1798fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1799fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1800fcf5ef2aSThomas Huth { 1801fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1802fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1803fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1804fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1805fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1806fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1807fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1808fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1809fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1810fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1811fcf5ef2aSThomas Huth tcg_temp_free(t0); 1812fcf5ef2aSThomas Huth } 1813fcf5ef2aSThomas Huth #endif 1814fcf5ef2aSThomas Huth 1815fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1816fcf5ef2aSThomas Huth /* bpermd */ 1817fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1818fcf5ef2aSThomas Huth { 1819fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1820fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1821fcf5ef2aSThomas Huth } 1822fcf5ef2aSThomas Huth #endif 1823fcf5ef2aSThomas Huth 1824fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1825fcf5ef2aSThomas Huth /* extsw & extsw. */ 1826fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1827fcf5ef2aSThomas Huth 1828fcf5ef2aSThomas Huth /* cntlzd */ 1829fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1830fcf5ef2aSThomas Huth { 18319b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1832efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1833fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1834fcf5ef2aSThomas Huth } 1835efe843d8SDavid Gibson } 1836fcf5ef2aSThomas Huth 1837fcf5ef2aSThomas Huth /* cnttzd */ 1838fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1839fcf5ef2aSThomas Huth { 18409b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1841fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1842fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1843fcf5ef2aSThomas Huth } 1844fcf5ef2aSThomas Huth } 1845fcf5ef2aSThomas Huth 1846fcf5ef2aSThomas Huth /* darn */ 1847fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1848fcf5ef2aSThomas Huth { 1849fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1850fcf5ef2aSThomas Huth 18517e4357f6SRichard Henderson if (l > 2) { 18527e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 18537e4357f6SRichard Henderson } else { 18547e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 18557e4357f6SRichard Henderson gen_io_start(); 18567e4357f6SRichard Henderson } 1857fcf5ef2aSThomas Huth if (l == 0) { 1858fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 18597e4357f6SRichard Henderson } else { 1860fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1861fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 18627e4357f6SRichard Henderson } 18637e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 18647e4357f6SRichard Henderson gen_stop_exception(ctx); 18657e4357f6SRichard Henderson } 1866fcf5ef2aSThomas Huth } 1867fcf5ef2aSThomas Huth } 1868fcf5ef2aSThomas Huth #endif 1869fcf5ef2aSThomas Huth 1870fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1871fcf5ef2aSThomas Huth 1872fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1873fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1874fcf5ef2aSThomas Huth { 1875fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1876fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1877fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1878fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1879fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1880fcf5ef2aSThomas Huth 1881fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 1882fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1883fcf5ef2aSThomas Huth } else { 1884fcf5ef2aSThomas Huth target_ulong mask; 1885fcf5ef2aSThomas Huth TCGv t1; 1886fcf5ef2aSThomas Huth 1887fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1888fcf5ef2aSThomas Huth mb += 32; 1889fcf5ef2aSThomas Huth me += 32; 1890fcf5ef2aSThomas Huth #endif 1891fcf5ef2aSThomas Huth mask = MASK(mb, me); 1892fcf5ef2aSThomas Huth 1893fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1894fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1895fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1896fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1897fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1898fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1899fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1900fcf5ef2aSThomas Huth } else { 1901fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1902fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1903fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1904fcf5ef2aSThomas Huth #else 1905fcf5ef2aSThomas Huth g_assert_not_reached(); 1906fcf5ef2aSThomas Huth #endif 1907fcf5ef2aSThomas Huth } 1908fcf5ef2aSThomas Huth 1909fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1910fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1911fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1912fcf5ef2aSThomas Huth tcg_temp_free(t1); 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1915fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1916fcf5ef2aSThomas Huth } 1917fcf5ef2aSThomas Huth } 1918fcf5ef2aSThomas Huth 1919fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1920fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1921fcf5ef2aSThomas Huth { 1922fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1923fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 19247b4d326fSRichard Henderson int sh = SH(ctx->opcode); 19257b4d326fSRichard Henderson int mb = MB(ctx->opcode); 19267b4d326fSRichard Henderson int me = ME(ctx->opcode); 19277b4d326fSRichard Henderson int len = me - mb + 1; 19287b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1929fcf5ef2aSThomas Huth 19307b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 19317b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 19327b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 19337b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1934fcf5ef2aSThomas Huth } else { 1935fcf5ef2aSThomas Huth target_ulong mask; 1936fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1937fcf5ef2aSThomas Huth mb += 32; 1938fcf5ef2aSThomas Huth me += 32; 1939fcf5ef2aSThomas Huth #endif 1940fcf5ef2aSThomas Huth mask = MASK(mb, me); 1941*94f040aaSVitaly Chikunov if (mask <= 0xffffffffu) { 19427b4d326fSRichard Henderson if (sh == 0) { 19437b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 1944*94f040aaSVitaly Chikunov } else { 1945fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1946fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1947fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1948fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1949fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1950fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1951*94f040aaSVitaly Chikunov } 1952fcf5ef2aSThomas Huth } else { 1953fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1954fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1955fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1956fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1957fcf5ef2aSThomas Huth #else 1958fcf5ef2aSThomas Huth g_assert_not_reached(); 1959fcf5ef2aSThomas Huth #endif 1960fcf5ef2aSThomas Huth } 1961fcf5ef2aSThomas Huth } 1962fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1963fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1964fcf5ef2aSThomas Huth } 1965fcf5ef2aSThomas Huth } 1966fcf5ef2aSThomas Huth 1967fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1968fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1969fcf5ef2aSThomas Huth { 1970fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1971fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1972fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1973fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1974fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1975fcf5ef2aSThomas Huth target_ulong mask; 1976fcf5ef2aSThomas Huth 1977fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1978fcf5ef2aSThomas Huth mb += 32; 1979fcf5ef2aSThomas Huth me += 32; 1980fcf5ef2aSThomas Huth #endif 1981fcf5ef2aSThomas Huth mask = MASK(mb, me); 1982fcf5ef2aSThomas Huth 1983fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1984fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1985fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1986fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1987fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1988fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1989fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1990fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1991fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1992fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1993fcf5ef2aSThomas Huth } else { 1994fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1995fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1996fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1997fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1998fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1999fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2000fcf5ef2aSThomas Huth #else 2001fcf5ef2aSThomas Huth g_assert_not_reached(); 2002fcf5ef2aSThomas Huth #endif 2003fcf5ef2aSThomas Huth } 2004fcf5ef2aSThomas Huth 2005fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2006fcf5ef2aSThomas Huth 2007fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2008fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2009fcf5ef2aSThomas Huth } 2010fcf5ef2aSThomas Huth } 2011fcf5ef2aSThomas Huth 2012fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2013fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2014fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2015fcf5ef2aSThomas Huth { \ 2016fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2017fcf5ef2aSThomas Huth } \ 2018fcf5ef2aSThomas Huth \ 2019fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2020fcf5ef2aSThomas Huth { \ 2021fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2022fcf5ef2aSThomas Huth } 2023fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2024fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2025fcf5ef2aSThomas Huth { \ 2026fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2027fcf5ef2aSThomas Huth } \ 2028fcf5ef2aSThomas Huth \ 2029fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2030fcf5ef2aSThomas Huth { \ 2031fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2032fcf5ef2aSThomas Huth } \ 2033fcf5ef2aSThomas Huth \ 2034fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2035fcf5ef2aSThomas Huth { \ 2036fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2037fcf5ef2aSThomas Huth } \ 2038fcf5ef2aSThomas Huth \ 2039fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2040fcf5ef2aSThomas Huth { \ 2041fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2042fcf5ef2aSThomas Huth } 2043fcf5ef2aSThomas Huth 2044fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2045fcf5ef2aSThomas Huth { 2046fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2047fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20487b4d326fSRichard Henderson int len = me - mb + 1; 20497b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2050fcf5ef2aSThomas Huth 20517b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20527b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20537b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20547b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2055fcf5ef2aSThomas Huth } else { 2056fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2057fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2058fcf5ef2aSThomas Huth } 2059fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2060fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2061fcf5ef2aSThomas Huth } 2062fcf5ef2aSThomas Huth } 2063fcf5ef2aSThomas Huth 2064fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2065fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2066fcf5ef2aSThomas Huth { 2067fcf5ef2aSThomas Huth uint32_t sh, mb; 2068fcf5ef2aSThomas Huth 2069fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2070fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2071fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2072fcf5ef2aSThomas Huth } 2073fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2074fcf5ef2aSThomas Huth 2075fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2076fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2077fcf5ef2aSThomas Huth { 2078fcf5ef2aSThomas Huth uint32_t sh, me; 2079fcf5ef2aSThomas Huth 2080fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2081fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2082fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2083fcf5ef2aSThomas Huth } 2084fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2085fcf5ef2aSThomas Huth 2086fcf5ef2aSThomas Huth /* rldic - rldic. */ 2087fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2088fcf5ef2aSThomas Huth { 2089fcf5ef2aSThomas Huth uint32_t sh, mb; 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2092fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2093fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2094fcf5ef2aSThomas Huth } 2095fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2096fcf5ef2aSThomas Huth 2097fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2098fcf5ef2aSThomas Huth { 2099fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2100fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2101fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2102fcf5ef2aSThomas Huth TCGv t0; 2103fcf5ef2aSThomas Huth 2104fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2105fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2106fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2107fcf5ef2aSThomas Huth tcg_temp_free(t0); 2108fcf5ef2aSThomas Huth 2109fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2110fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2111fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2112fcf5ef2aSThomas Huth } 2113fcf5ef2aSThomas Huth } 2114fcf5ef2aSThomas Huth 2115fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2116fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2117fcf5ef2aSThomas Huth { 2118fcf5ef2aSThomas Huth uint32_t mb; 2119fcf5ef2aSThomas Huth 2120fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2121fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2122fcf5ef2aSThomas Huth } 2123fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2124fcf5ef2aSThomas Huth 2125fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2126fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2127fcf5ef2aSThomas Huth { 2128fcf5ef2aSThomas Huth uint32_t me; 2129fcf5ef2aSThomas Huth 2130fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2131fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2132fcf5ef2aSThomas Huth } 2133fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2134fcf5ef2aSThomas Huth 2135fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2136fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2137fcf5ef2aSThomas Huth { 2138fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2139fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2140fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2141fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2142fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2143fcf5ef2aSThomas Huth 2144fcf5ef2aSThomas Huth if (mb <= me) { 2145fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2146fcf5ef2aSThomas Huth } else { 2147fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2148fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2149fcf5ef2aSThomas Huth 2150fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2151fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2152fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2153fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2154fcf5ef2aSThomas Huth tcg_temp_free(t1); 2155fcf5ef2aSThomas Huth } 2156fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2157fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2158fcf5ef2aSThomas Huth } 2159fcf5ef2aSThomas Huth } 2160fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2161fcf5ef2aSThomas Huth #endif 2162fcf5ef2aSThomas Huth 2163fcf5ef2aSThomas Huth /*** Integer shift ***/ 2164fcf5ef2aSThomas Huth 2165fcf5ef2aSThomas Huth /* slw & slw. */ 2166fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2167fcf5ef2aSThomas Huth { 2168fcf5ef2aSThomas Huth TCGv t0, t1; 2169fcf5ef2aSThomas Huth 2170fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2171fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2172fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2173fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2174fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2175fcf5ef2aSThomas Huth #else 2176fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2177fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2178fcf5ef2aSThomas Huth #endif 2179fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2180fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2181fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2182fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2183fcf5ef2aSThomas Huth tcg_temp_free(t1); 2184fcf5ef2aSThomas Huth tcg_temp_free(t0); 2185fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2186efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2187fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2188fcf5ef2aSThomas Huth } 2189efe843d8SDavid Gibson } 2190fcf5ef2aSThomas Huth 2191fcf5ef2aSThomas Huth /* sraw & sraw. */ 2192fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2193fcf5ef2aSThomas Huth { 2194fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2195fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2196efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2197fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2198fcf5ef2aSThomas Huth } 2199efe843d8SDavid Gibson } 2200fcf5ef2aSThomas Huth 2201fcf5ef2aSThomas Huth /* srawi & srawi. */ 2202fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2203fcf5ef2aSThomas Huth { 2204fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2205fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2206fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2207fcf5ef2aSThomas Huth if (sh == 0) { 2208fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2209fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2210af1c259fSSandipan Das if (is_isa300(ctx)) { 2211af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2212af1c259fSSandipan Das } 2213fcf5ef2aSThomas Huth } else { 2214fcf5ef2aSThomas Huth TCGv t0; 2215fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2216fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2217fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2218fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2219fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2220fcf5ef2aSThomas Huth tcg_temp_free(t0); 2221fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2222af1c259fSSandipan Das if (is_isa300(ctx)) { 2223af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2224af1c259fSSandipan Das } 2225fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2226fcf5ef2aSThomas Huth } 2227fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2228fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2229fcf5ef2aSThomas Huth } 2230fcf5ef2aSThomas Huth } 2231fcf5ef2aSThomas Huth 2232fcf5ef2aSThomas Huth /* srw & srw. */ 2233fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2234fcf5ef2aSThomas Huth { 2235fcf5ef2aSThomas Huth TCGv t0, t1; 2236fcf5ef2aSThomas Huth 2237fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2238fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2239fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2240fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2241fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2242fcf5ef2aSThomas Huth #else 2243fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2244fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2245fcf5ef2aSThomas Huth #endif 2246fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2247fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2248fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2249fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2250fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2251fcf5ef2aSThomas Huth tcg_temp_free(t1); 2252fcf5ef2aSThomas Huth tcg_temp_free(t0); 2253efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2254fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2255fcf5ef2aSThomas Huth } 2256efe843d8SDavid Gibson } 2257fcf5ef2aSThomas Huth 2258fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2259fcf5ef2aSThomas Huth /* sld & sld. */ 2260fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2261fcf5ef2aSThomas Huth { 2262fcf5ef2aSThomas Huth TCGv t0, t1; 2263fcf5ef2aSThomas Huth 2264fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2265fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2266fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2267fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2268fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2269fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2270fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2271fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2272fcf5ef2aSThomas Huth tcg_temp_free(t1); 2273fcf5ef2aSThomas Huth tcg_temp_free(t0); 2274efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2275fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2276fcf5ef2aSThomas Huth } 2277efe843d8SDavid Gibson } 2278fcf5ef2aSThomas Huth 2279fcf5ef2aSThomas Huth /* srad & srad. */ 2280fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2281fcf5ef2aSThomas Huth { 2282fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2283fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2284efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2285fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2286fcf5ef2aSThomas Huth } 2287efe843d8SDavid Gibson } 2288fcf5ef2aSThomas Huth /* sradi & sradi. */ 2289fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2290fcf5ef2aSThomas Huth { 2291fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2292fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2293fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2294fcf5ef2aSThomas Huth if (sh == 0) { 2295fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2296fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2297af1c259fSSandipan Das if (is_isa300(ctx)) { 2298af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2299af1c259fSSandipan Das } 2300fcf5ef2aSThomas Huth } else { 2301fcf5ef2aSThomas Huth TCGv t0; 2302fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2303fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2304fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2305fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2306fcf5ef2aSThomas Huth tcg_temp_free(t0); 2307fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2308af1c259fSSandipan Das if (is_isa300(ctx)) { 2309af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2310af1c259fSSandipan Das } 2311fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2312fcf5ef2aSThomas Huth } 2313fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2314fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2315fcf5ef2aSThomas Huth } 2316fcf5ef2aSThomas Huth } 2317fcf5ef2aSThomas Huth 2318fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2319fcf5ef2aSThomas Huth { 2320fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2321fcf5ef2aSThomas Huth } 2322fcf5ef2aSThomas Huth 2323fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2324fcf5ef2aSThomas Huth { 2325fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2326fcf5ef2aSThomas Huth } 2327fcf5ef2aSThomas Huth 2328fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2329fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2330fcf5ef2aSThomas Huth { 2331fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2332fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2333fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2334fcf5ef2aSThomas Huth 2335fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2336fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2337fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2338fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2339fcf5ef2aSThomas Huth } 2340fcf5ef2aSThomas Huth } 2341fcf5ef2aSThomas Huth 2342fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2343fcf5ef2aSThomas Huth { 2344fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2345fcf5ef2aSThomas Huth } 2346fcf5ef2aSThomas Huth 2347fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2348fcf5ef2aSThomas Huth { 2349fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2350fcf5ef2aSThomas Huth } 2351fcf5ef2aSThomas Huth 2352fcf5ef2aSThomas Huth /* srd & srd. */ 2353fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2354fcf5ef2aSThomas Huth { 2355fcf5ef2aSThomas Huth TCGv t0, t1; 2356fcf5ef2aSThomas Huth 2357fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2358fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2359fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2360fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2361fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2362fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2363fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2364fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2365fcf5ef2aSThomas Huth tcg_temp_free(t1); 2366fcf5ef2aSThomas Huth tcg_temp_free(t0); 2367efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2368fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2369fcf5ef2aSThomas Huth } 2370efe843d8SDavid Gibson } 2371fcf5ef2aSThomas Huth #endif 2372fcf5ef2aSThomas Huth 2373fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2374fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2375fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2376fcf5ef2aSThomas Huth target_long maskl) 2377fcf5ef2aSThomas Huth { 2378fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2379fcf5ef2aSThomas Huth 2380fcf5ef2aSThomas Huth simm &= ~maskl; 2381fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2382fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2383fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2386fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2387fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2388fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2389fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2390fcf5ef2aSThomas Huth } 2391fcf5ef2aSThomas Huth } else { 2392fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2393fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2394fcf5ef2aSThomas Huth } else { 2395fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2396fcf5ef2aSThomas Huth } 2397fcf5ef2aSThomas Huth } 2398fcf5ef2aSThomas Huth } 2399fcf5ef2aSThomas Huth 2400fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2401fcf5ef2aSThomas Huth { 2402fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2403fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2404fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2405fcf5ef2aSThomas Huth } else { 2406fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2407fcf5ef2aSThomas Huth } 2408fcf5ef2aSThomas Huth } else { 2409fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2410fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2411fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2412fcf5ef2aSThomas Huth } 2413fcf5ef2aSThomas Huth } 2414fcf5ef2aSThomas Huth } 2415fcf5ef2aSThomas Huth 2416fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2417fcf5ef2aSThomas Huth { 2418fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2419fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2420fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2421fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2422fcf5ef2aSThomas Huth } else { 2423fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2424fcf5ef2aSThomas Huth } 2425fcf5ef2aSThomas Huth } 2426fcf5ef2aSThomas Huth 2427fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2428fcf5ef2aSThomas Huth target_long val) 2429fcf5ef2aSThomas Huth { 2430fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2431fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2432fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2433fcf5ef2aSThomas Huth } 2434fcf5ef2aSThomas Huth } 2435fcf5ef2aSThomas Huth 2436fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2437fcf5ef2aSThomas Huth { 2438fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2439fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2440fcf5ef2aSThomas Huth } 2441fcf5ef2aSThomas Huth 2442fcf5ef2aSThomas Huth /*** Integer load ***/ 2443fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2444fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2445fcf5ef2aSThomas Huth 2446fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2447fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2448fcf5ef2aSThomas Huth TCGv val, \ 2449fcf5ef2aSThomas Huth TCGv addr) \ 2450fcf5ef2aSThomas Huth { \ 2451fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2452fcf5ef2aSThomas Huth } 2453fcf5ef2aSThomas Huth 2454fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2455fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2456fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2457fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2458fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2459fcf5ef2aSThomas Huth 2460fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2461fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2462fcf5ef2aSThomas Huth 2463fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2464fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2465fcf5ef2aSThomas Huth TCGv_i64 val, \ 2466fcf5ef2aSThomas Huth TCGv addr) \ 2467fcf5ef2aSThomas Huth { \ 2468fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2469fcf5ef2aSThomas Huth } 2470fcf5ef2aSThomas Huth 2471fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2472fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2473fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2474fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2475fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2476fcf5ef2aSThomas Huth 2477fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2478fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2479fcf5ef2aSThomas Huth #endif 2480fcf5ef2aSThomas Huth 2481fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2482fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2483fcf5ef2aSThomas Huth TCGv val, \ 2484fcf5ef2aSThomas Huth TCGv addr) \ 2485fcf5ef2aSThomas Huth { \ 2486fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2487fcf5ef2aSThomas Huth } 2488fcf5ef2aSThomas Huth 2489fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2490fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2491fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2492fcf5ef2aSThomas Huth 2493fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2494fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2495fcf5ef2aSThomas Huth 2496fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2497fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2498fcf5ef2aSThomas Huth TCGv_i64 val, \ 2499fcf5ef2aSThomas Huth TCGv addr) \ 2500fcf5ef2aSThomas Huth { \ 2501fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2502fcf5ef2aSThomas Huth } 2503fcf5ef2aSThomas Huth 2504fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2505fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2506fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2507fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2508fcf5ef2aSThomas Huth 2509fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2510fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2511fcf5ef2aSThomas Huth #endif 2512fcf5ef2aSThomas Huth 2513fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2514fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2515fcf5ef2aSThomas Huth { \ 2516fcf5ef2aSThomas Huth TCGv EA; \ 2517fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2518fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2519fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2520fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2521fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2522fcf5ef2aSThomas Huth } 2523fcf5ef2aSThomas Huth 2524fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2525fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2526fcf5ef2aSThomas Huth { \ 2527fcf5ef2aSThomas Huth TCGv EA; \ 2528fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2529fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2530fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2531fcf5ef2aSThomas Huth return; \ 2532fcf5ef2aSThomas Huth } \ 2533fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2534fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2535fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2536fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2537fcf5ef2aSThomas Huth else \ 2538fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2539fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2540fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2541fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2542fcf5ef2aSThomas Huth } 2543fcf5ef2aSThomas Huth 2544fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2545fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2546fcf5ef2aSThomas Huth { \ 2547fcf5ef2aSThomas Huth TCGv EA; \ 2548fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2549fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2550fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2551fcf5ef2aSThomas Huth return; \ 2552fcf5ef2aSThomas Huth } \ 2553fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2554fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2555fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2556fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2557fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2558fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2559fcf5ef2aSThomas Huth } 2560fcf5ef2aSThomas Huth 2561fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2562fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2563fcf5ef2aSThomas Huth { \ 2564fcf5ef2aSThomas Huth TCGv EA; \ 2565fcf5ef2aSThomas Huth chk; \ 2566fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2567fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2568fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2569fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2570fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2571fcf5ef2aSThomas Huth } 2572fcf5ef2aSThomas Huth 2573fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2574fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2575fcf5ef2aSThomas Huth 2576fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2577fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2578fcf5ef2aSThomas Huth 2579fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2580fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2581fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2582fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2583fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2584fcf5ef2aSThomas Huth 2585fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2586fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2587fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2588fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2589fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2590fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2591fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2592fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 259350728199SRoman Kapl 259450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 259550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 259650728199SRoman Kapl { \ 259750728199SRoman Kapl TCGv EA; \ 259850728199SRoman Kapl CHK_SV; \ 259950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 260050728199SRoman Kapl EA = tcg_temp_new(); \ 260150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 260250728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 260350728199SRoman Kapl tcg_temp_free(EA); \ 260450728199SRoman Kapl } 260550728199SRoman Kapl 260650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 260750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 260850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 260950728199SRoman Kapl #if defined(TARGET_PPC64) 261050728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 261150728199SRoman Kapl #endif 261250728199SRoman Kapl 2613fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2614fcf5ef2aSThomas Huth /* lwaux */ 2615fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2616fcf5ef2aSThomas Huth /* lwax */ 2617fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2618fcf5ef2aSThomas Huth /* ldux */ 2619fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2620fcf5ef2aSThomas Huth /* ldx */ 2621fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2622fcf5ef2aSThomas Huth 2623fcf5ef2aSThomas Huth /* CI load/store variants */ 2624fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2625fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2626fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2627fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2628fcf5ef2aSThomas Huth 2629fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2630fcf5ef2aSThomas Huth { 2631fcf5ef2aSThomas Huth TCGv EA; 2632fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2633fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2634fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2635fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2636fcf5ef2aSThomas Huth return; 2637fcf5ef2aSThomas Huth } 2638fcf5ef2aSThomas Huth } 2639fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2640fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2641fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2642fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2643fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2644fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2645fcf5ef2aSThomas Huth } else { 2646fcf5ef2aSThomas Huth /* ld - ldu */ 2647fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2648fcf5ef2aSThomas Huth } 2649efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 2650fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2651efe843d8SDavid Gibson } 2652fcf5ef2aSThomas Huth tcg_temp_free(EA); 2653fcf5ef2aSThomas Huth } 2654fcf5ef2aSThomas Huth 2655fcf5ef2aSThomas Huth /* lq */ 2656fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2657fcf5ef2aSThomas Huth { 2658fcf5ef2aSThomas Huth int ra, rd; 265994bf2658SRichard Henderson TCGv EA, hi, lo; 2660fcf5ef2aSThomas Huth 2661fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2662fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2663fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2664fcf5ef2aSThomas Huth 2665fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2666fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2667fcf5ef2aSThomas Huth return; 2668fcf5ef2aSThomas Huth } 2669fcf5ef2aSThomas Huth 2670fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2671fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2672fcf5ef2aSThomas Huth return; 2673fcf5ef2aSThomas Huth } 2674fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2675fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2676fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2677fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2678fcf5ef2aSThomas Huth return; 2679fcf5ef2aSThomas Huth } 2680fcf5ef2aSThomas Huth 2681fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2682fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2683fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2684fcf5ef2aSThomas Huth 268594bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 268694bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 268794bf2658SRichard Henderson hi = cpu_gpr[rd]; 268894bf2658SRichard Henderson 268994bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2690f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 269194bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 269294bf2658SRichard Henderson if (ctx->le_mode) { 269394bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 269494bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2695fcf5ef2aSThomas Huth } else { 269694bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 269794bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 269894bf2658SRichard Henderson } 269994bf2658SRichard Henderson tcg_temp_free_i32(oi); 270094bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2701f34ec0f6SRichard Henderson } else { 270294bf2658SRichard Henderson /* Restart with exclusive lock. */ 270394bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 270494bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2705f34ec0f6SRichard Henderson } 270694bf2658SRichard Henderson } else if (ctx->le_mode) { 270794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2708fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 270994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 271094bf2658SRichard Henderson } else { 271194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 271294bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 271394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2714fcf5ef2aSThomas Huth } 2715fcf5ef2aSThomas Huth tcg_temp_free(EA); 2716fcf5ef2aSThomas Huth } 2717fcf5ef2aSThomas Huth #endif 2718fcf5ef2aSThomas Huth 2719fcf5ef2aSThomas Huth /*** Integer store ***/ 2720fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2721fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2722fcf5ef2aSThomas Huth { \ 2723fcf5ef2aSThomas Huth TCGv EA; \ 2724fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2725fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2726fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2727fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2728fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2729fcf5ef2aSThomas Huth } 2730fcf5ef2aSThomas Huth 2731fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2732fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2733fcf5ef2aSThomas Huth { \ 2734fcf5ef2aSThomas Huth TCGv EA; \ 2735fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2736fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2737fcf5ef2aSThomas Huth return; \ 2738fcf5ef2aSThomas Huth } \ 2739fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2740fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2741fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2742fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2743fcf5ef2aSThomas Huth else \ 2744fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2745fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2746fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2747fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2748fcf5ef2aSThomas Huth } 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2751fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2752fcf5ef2aSThomas Huth { \ 2753fcf5ef2aSThomas Huth TCGv EA; \ 2754fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2755fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2756fcf5ef2aSThomas Huth return; \ 2757fcf5ef2aSThomas Huth } \ 2758fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2759fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2760fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2761fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2762fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2763fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2764fcf5ef2aSThomas Huth } 2765fcf5ef2aSThomas Huth 2766fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2767fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2768fcf5ef2aSThomas Huth { \ 2769fcf5ef2aSThomas Huth TCGv EA; \ 2770fcf5ef2aSThomas Huth chk; \ 2771fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2772fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2773fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2774fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2775fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2776fcf5ef2aSThomas Huth } 2777fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2778fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2779fcf5ef2aSThomas Huth 2780fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2781fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2782fcf5ef2aSThomas Huth 2783fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2784fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2785fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2786fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2787fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2788fcf5ef2aSThomas Huth 2789fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2790fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2791fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2792fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2793fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2794fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 279550728199SRoman Kapl 279650728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 279750728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 279850728199SRoman Kapl { \ 279950728199SRoman Kapl TCGv EA; \ 280050728199SRoman Kapl CHK_SV; \ 280150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 280250728199SRoman Kapl EA = tcg_temp_new(); \ 280350728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 280450728199SRoman Kapl tcg_gen_qemu_st_tl( \ 280550728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 280650728199SRoman Kapl tcg_temp_free(EA); \ 280750728199SRoman Kapl } 280850728199SRoman Kapl 280950728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 281050728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 281150728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 281250728199SRoman Kapl #if defined(TARGET_PPC64) 281350728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 281450728199SRoman Kapl #endif 281550728199SRoman Kapl 2816fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2817fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2818fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2819fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2820fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2821fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2822fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2823fcf5ef2aSThomas Huth 2824fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2825fcf5ef2aSThomas Huth { 2826fcf5ef2aSThomas Huth int rs; 2827fcf5ef2aSThomas Huth TCGv EA; 2828fcf5ef2aSThomas Huth 2829fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2830fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2831fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2832fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2833f89ced5fSRichard Henderson TCGv hi, lo; 2834fcf5ef2aSThomas Huth 2835fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2836fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2837fcf5ef2aSThomas Huth } 2838fcf5ef2aSThomas Huth 2839fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2840fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2841fcf5ef2aSThomas Huth return; 2842fcf5ef2aSThomas Huth } 2843fcf5ef2aSThomas Huth 2844fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2845fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2846fcf5ef2aSThomas Huth return; 2847fcf5ef2aSThomas Huth } 2848fcf5ef2aSThomas Huth 2849fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2850fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2851fcf5ef2aSThomas Huth return; 2852fcf5ef2aSThomas Huth } 2853fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2854fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2855fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2856fcf5ef2aSThomas Huth 2857f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 2858f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 2859f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 2860f89ced5fSRichard Henderson 2861f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2862f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 2863f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 2864f89ced5fSRichard Henderson if (ctx->le_mode) { 2865f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2866f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2867fcf5ef2aSThomas Huth } else { 2868f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2869f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2870f89ced5fSRichard Henderson } 2871f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 2872f34ec0f6SRichard Henderson } else { 2873f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 2874f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 2875f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2876f34ec0f6SRichard Henderson } 2877f89ced5fSRichard Henderson } else if (ctx->le_mode) { 2878f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2879fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2880f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2881f89ced5fSRichard Henderson } else { 2882f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2883f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 2884f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2885fcf5ef2aSThomas Huth } 2886fcf5ef2aSThomas Huth tcg_temp_free(EA); 2887fcf5ef2aSThomas Huth } else { 2888fcf5ef2aSThomas Huth /* std / stdu */ 2889fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2890fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2891fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2892fcf5ef2aSThomas Huth return; 2893fcf5ef2aSThomas Huth } 2894fcf5ef2aSThomas Huth } 2895fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2896fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2897fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2898fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2899efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 2900fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2901efe843d8SDavid Gibson } 2902fcf5ef2aSThomas Huth tcg_temp_free(EA); 2903fcf5ef2aSThomas Huth } 2904fcf5ef2aSThomas Huth } 2905fcf5ef2aSThomas Huth #endif 2906fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2907fcf5ef2aSThomas Huth 2908fcf5ef2aSThomas Huth /* lhbrx */ 2909fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2910fcf5ef2aSThomas Huth 2911fcf5ef2aSThomas Huth /* lwbrx */ 2912fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2913fcf5ef2aSThomas Huth 2914fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2915fcf5ef2aSThomas Huth /* ldbrx */ 2916fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2917fcf5ef2aSThomas Huth /* stdbrx */ 2918fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2919fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2920fcf5ef2aSThomas Huth 2921fcf5ef2aSThomas Huth /* sthbrx */ 2922fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2923fcf5ef2aSThomas Huth /* stwbrx */ 2924fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2925fcf5ef2aSThomas Huth 2926fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2927fcf5ef2aSThomas Huth 2928fcf5ef2aSThomas Huth /* lmw */ 2929fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2930fcf5ef2aSThomas Huth { 2931fcf5ef2aSThomas Huth TCGv t0; 2932fcf5ef2aSThomas Huth TCGv_i32 t1; 2933fcf5ef2aSThomas Huth 2934fcf5ef2aSThomas Huth if (ctx->le_mode) { 2935fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2936fcf5ef2aSThomas Huth return; 2937fcf5ef2aSThomas Huth } 2938fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2939fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2940fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2941fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2942fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2943fcf5ef2aSThomas Huth tcg_temp_free(t0); 2944fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2945fcf5ef2aSThomas Huth } 2946fcf5ef2aSThomas Huth 2947fcf5ef2aSThomas Huth /* stmw */ 2948fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2949fcf5ef2aSThomas Huth { 2950fcf5ef2aSThomas Huth TCGv t0; 2951fcf5ef2aSThomas Huth TCGv_i32 t1; 2952fcf5ef2aSThomas Huth 2953fcf5ef2aSThomas Huth if (ctx->le_mode) { 2954fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2955fcf5ef2aSThomas Huth return; 2956fcf5ef2aSThomas Huth } 2957fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2958fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2959fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2960fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2961fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2962fcf5ef2aSThomas Huth tcg_temp_free(t0); 2963fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2964fcf5ef2aSThomas Huth } 2965fcf5ef2aSThomas Huth 2966fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2967fcf5ef2aSThomas Huth 2968fcf5ef2aSThomas Huth /* lswi */ 2969efe843d8SDavid Gibson /* 2970efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 2971efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 2972efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 2973efe843d8SDavid Gibson * spec... 2974fcf5ef2aSThomas Huth */ 2975fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2976fcf5ef2aSThomas Huth { 2977fcf5ef2aSThomas Huth TCGv t0; 2978fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2979fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2980fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2981fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2982fcf5ef2aSThomas Huth int nr; 2983fcf5ef2aSThomas Huth 2984fcf5ef2aSThomas Huth if (ctx->le_mode) { 2985fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2986fcf5ef2aSThomas Huth return; 2987fcf5ef2aSThomas Huth } 2988efe843d8SDavid Gibson if (nb == 0) { 2989fcf5ef2aSThomas Huth nb = 32; 2990efe843d8SDavid Gibson } 2991f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 2992fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2993fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2994fcf5ef2aSThomas Huth return; 2995fcf5ef2aSThomas Huth } 2996fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2997fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2998fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2999fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3000fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3001fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3002fcf5ef2aSThomas Huth tcg_temp_free(t0); 3003fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3004fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3005fcf5ef2aSThomas Huth } 3006fcf5ef2aSThomas Huth 3007fcf5ef2aSThomas Huth /* lswx */ 3008fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3009fcf5ef2aSThomas Huth { 3010fcf5ef2aSThomas Huth TCGv t0; 3011fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3012fcf5ef2aSThomas Huth 3013fcf5ef2aSThomas Huth if (ctx->le_mode) { 3014fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3015fcf5ef2aSThomas Huth return; 3016fcf5ef2aSThomas Huth } 3017fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3018fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3019fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3020fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3021fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3022fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3023fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3024fcf5ef2aSThomas Huth tcg_temp_free(t0); 3025fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3026fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3027fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3028fcf5ef2aSThomas Huth } 3029fcf5ef2aSThomas Huth 3030fcf5ef2aSThomas Huth /* stswi */ 3031fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3032fcf5ef2aSThomas Huth { 3033fcf5ef2aSThomas Huth TCGv t0; 3034fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3035fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3036fcf5ef2aSThomas Huth 3037fcf5ef2aSThomas Huth if (ctx->le_mode) { 3038fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3039fcf5ef2aSThomas Huth return; 3040fcf5ef2aSThomas Huth } 3041fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3042fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3043fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3044efe843d8SDavid Gibson if (nb == 0) { 3045fcf5ef2aSThomas Huth nb = 32; 3046efe843d8SDavid Gibson } 3047fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3048fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3049fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3050fcf5ef2aSThomas Huth tcg_temp_free(t0); 3051fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3052fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3053fcf5ef2aSThomas Huth } 3054fcf5ef2aSThomas Huth 3055fcf5ef2aSThomas Huth /* stswx */ 3056fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3057fcf5ef2aSThomas Huth { 3058fcf5ef2aSThomas Huth TCGv t0; 3059fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3060fcf5ef2aSThomas Huth 3061fcf5ef2aSThomas Huth if (ctx->le_mode) { 3062fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3063fcf5ef2aSThomas Huth return; 3064fcf5ef2aSThomas Huth } 3065fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3066fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3067fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3068fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3069fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3070fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3071fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3072fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3073fcf5ef2aSThomas Huth tcg_temp_free(t0); 3074fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3075fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3076fcf5ef2aSThomas Huth } 3077fcf5ef2aSThomas Huth 3078fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3079fcf5ef2aSThomas Huth /* eieio */ 3080fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3081fcf5ef2aSThomas Huth { 3082c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3083c8fd8373SCédric Le Goater 3084c8fd8373SCédric Le Goater /* 3085c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3086c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3087c8fd8373SCédric Le Goater */ 3088c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3089c8fd8373SCédric Le Goater /* 3090c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3091c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3092c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3093c8fd8373SCédric Le Goater * complain to the user. 3094c8fd8373SCédric Le Goater */ 3095c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3096c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3097c8fd8373SCédric Le Goater TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3098c8fd8373SCédric Le Goater } else { 3099c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3100c8fd8373SCédric Le Goater } 3101c8fd8373SCédric Le Goater } 3102c8fd8373SCédric Le Goater 3103c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3104fcf5ef2aSThomas Huth } 3105fcf5ef2aSThomas Huth 3106fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3107fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3108fcf5ef2aSThomas Huth { 3109fcf5ef2aSThomas Huth TCGv_i32 t; 3110fcf5ef2aSThomas Huth TCGLabel *l; 3111fcf5ef2aSThomas Huth 3112fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3113fcf5ef2aSThomas Huth return; 3114fcf5ef2aSThomas Huth } 3115fcf5ef2aSThomas Huth l = gen_new_label(); 3116fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3117fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3118fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3119fcf5ef2aSThomas Huth if (global) { 3120fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3121fcf5ef2aSThomas Huth } else { 3122fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3123fcf5ef2aSThomas Huth } 3124fcf5ef2aSThomas Huth gen_set_label(l); 3125fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3126fcf5ef2aSThomas Huth } 3127fcf5ef2aSThomas Huth #else 3128fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3129fcf5ef2aSThomas Huth #endif 3130fcf5ef2aSThomas Huth 3131fcf5ef2aSThomas Huth /* isync */ 3132fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3133fcf5ef2aSThomas Huth { 3134fcf5ef2aSThomas Huth /* 3135fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3136fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3137fcf5ef2aSThomas Huth */ 3138fcf5ef2aSThomas Huth if (!ctx->pr) { 3139fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3140fcf5ef2aSThomas Huth } 31414771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3142fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3143fcf5ef2aSThomas Huth } 3144fcf5ef2aSThomas Huth 3145fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3146fcf5ef2aSThomas Huth 314714776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 31482a4e6c1bSRichard Henderson { 31492a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 31502a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 31512a4e6c1bSRichard Henderson 31522a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 31532a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 31542a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 31552a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 31562a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 31572a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 31582a4e6c1bSRichard Henderson tcg_temp_free(t0); 31592a4e6c1bSRichard Henderson } 31602a4e6c1bSRichard Henderson 3161fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3162fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3163fcf5ef2aSThomas Huth { \ 31642a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3165fcf5ef2aSThomas Huth } 3166fcf5ef2aSThomas Huth 3167fcf5ef2aSThomas Huth /* lwarx */ 3168fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3169fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3170fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3171fcf5ef2aSThomas Huth 317214776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 317320923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 317420923c1dSRichard Henderson { 317520923c1dSRichard Henderson TCGv t = tcg_temp_new(); 317620923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 317720923c1dSRichard Henderson TCGv u = tcg_temp_new(); 317820923c1dSRichard Henderson 317920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 318020923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 318120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 318220923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 318320923c1dSRichard Henderson 318420923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 318520923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 318620923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 318720923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 318820923c1dSRichard Henderson 318920923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 319020923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 319120923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 319220923c1dSRichard Henderson 319320923c1dSRichard Henderson tcg_temp_free(t); 319420923c1dSRichard Henderson tcg_temp_free(t2); 319520923c1dSRichard Henderson tcg_temp_free(u); 319620923c1dSRichard Henderson } 319720923c1dSRichard Henderson 319814776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 319920ba8504SRichard Henderson { 320020ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 320120ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 320220923c1dSRichard Henderson int rt = rD(ctx->opcode); 320320923c1dSRichard Henderson bool need_serial; 320420ba8504SRichard Henderson TCGv src, dst; 320520ba8504SRichard Henderson 320620ba8504SRichard Henderson gen_addr_register(ctx, EA); 320720923c1dSRichard Henderson dst = cpu_gpr[rt]; 320820923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 320920ba8504SRichard Henderson 321020923c1dSRichard Henderson need_serial = false; 321120ba8504SRichard Henderson memop |= MO_ALIGN; 321220ba8504SRichard Henderson switch (gpr_FC) { 321320ba8504SRichard Henderson case 0: /* Fetch and add */ 321420ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 321520ba8504SRichard Henderson break; 321620ba8504SRichard Henderson case 1: /* Fetch and xor */ 321720ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 321820ba8504SRichard Henderson break; 321920ba8504SRichard Henderson case 2: /* Fetch and or */ 322020ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 322120ba8504SRichard Henderson break; 322220ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 322320ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 322420ba8504SRichard Henderson break; 3225b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3226b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3227b8ce0f86SRichard Henderson break; 3228b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3229b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3230b8ce0f86SRichard Henderson break; 3231b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3232b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3233b8ce0f86SRichard Henderson break; 3234b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3235b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3236b8ce0f86SRichard Henderson break; 323720ba8504SRichard Henderson case 8: /* Swap */ 323820ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 323920ba8504SRichard Henderson break; 324020923c1dSRichard Henderson 324120923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 324220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 324320923c1dSRichard Henderson need_serial = true; 324420923c1dSRichard Henderson } else { 324520923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 324620923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 324720923c1dSRichard Henderson 324820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 324920923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 325020923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 325120923c1dSRichard Henderson } else { 325220923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 325320923c1dSRichard Henderson } 325420923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 325520923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 325620923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 325720923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 325820923c1dSRichard Henderson 325920923c1dSRichard Henderson tcg_temp_free(t0); 326020923c1dSRichard Henderson tcg_temp_free(t1); 326120923c1dSRichard Henderson } 326220ba8504SRichard Henderson break; 326320923c1dSRichard Henderson 326420923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 326520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 326620923c1dSRichard Henderson need_serial = true; 326720923c1dSRichard Henderson } else { 326820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 326920923c1dSRichard Henderson } 327020923c1dSRichard Henderson break; 327120923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 327220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 327320923c1dSRichard Henderson need_serial = true; 327420923c1dSRichard Henderson } else { 327520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 327620923c1dSRichard Henderson } 327720923c1dSRichard Henderson break; 327820923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 327920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 328020923c1dSRichard Henderson need_serial = true; 328120923c1dSRichard Henderson } else { 328220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 328320923c1dSRichard Henderson } 328420923c1dSRichard Henderson break; 328520923c1dSRichard Henderson 328620ba8504SRichard Henderson default: 328720ba8504SRichard Henderson /* invoke data storage error handler */ 328820ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 328920ba8504SRichard Henderson } 329020ba8504SRichard Henderson tcg_temp_free(EA); 329120923c1dSRichard Henderson 329220923c1dSRichard Henderson if (need_serial) { 329320923c1dSRichard Henderson /* Restart with exclusive lock. */ 329420923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 329520923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 329620923c1dSRichard Henderson } 3297a68a6146SBalamuruhan S } 3298a68a6146SBalamuruhan S 329920ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 330020ba8504SRichard Henderson { 330120ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 330220ba8504SRichard Henderson } 330320ba8504SRichard Henderson 330420ba8504SRichard Henderson #ifdef TARGET_PPC64 330520ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 330620ba8504SRichard Henderson { 330720ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 330820ba8504SRichard Henderson } 3309a68a6146SBalamuruhan S #endif 3310a68a6146SBalamuruhan S 331114776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 33129deb041cSRichard Henderson { 33139deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 33149deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 33159deb041cSRichard Henderson TCGv src, discard; 33169deb041cSRichard Henderson 33179deb041cSRichard Henderson gen_addr_register(ctx, EA); 33189deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 33199deb041cSRichard Henderson discard = tcg_temp_new(); 33209deb041cSRichard Henderson 33219deb041cSRichard Henderson memop |= MO_ALIGN; 33229deb041cSRichard Henderson switch (gpr_FC) { 33239deb041cSRichard Henderson case 0: /* add and Store */ 33249deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33259deb041cSRichard Henderson break; 33269deb041cSRichard Henderson case 1: /* xor and Store */ 33279deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33289deb041cSRichard Henderson break; 33299deb041cSRichard Henderson case 2: /* Or and Store */ 33309deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33319deb041cSRichard Henderson break; 33329deb041cSRichard Henderson case 3: /* 'and' and Store */ 33339deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33349deb041cSRichard Henderson break; 33359deb041cSRichard Henderson case 4: /* Store max unsigned */ 3336b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3337b8ce0f86SRichard Henderson break; 33389deb041cSRichard Henderson case 5: /* Store max signed */ 3339b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3340b8ce0f86SRichard Henderson break; 33419deb041cSRichard Henderson case 6: /* Store min unsigned */ 3342b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3343b8ce0f86SRichard Henderson break; 33449deb041cSRichard Henderson case 7: /* Store min signed */ 3345b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3346b8ce0f86SRichard Henderson break; 33479deb041cSRichard Henderson case 24: /* Store twin */ 33487fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 33497fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 33507fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 33517fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 33527fbc2b20SRichard Henderson } else { 33537fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 33547fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 33557fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 33567fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 33577fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 33587fbc2b20SRichard Henderson 33597fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 33607fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 33617fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 33627fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 33637fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 33647fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 33657fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 33667fbc2b20SRichard Henderson 33677fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 33687fbc2b20SRichard Henderson tcg_temp_free(s2); 33697fbc2b20SRichard Henderson tcg_temp_free(s); 33707fbc2b20SRichard Henderson tcg_temp_free(t2); 33717fbc2b20SRichard Henderson tcg_temp_free(t); 33727fbc2b20SRichard Henderson } 33739deb041cSRichard Henderson break; 33749deb041cSRichard Henderson default: 33759deb041cSRichard Henderson /* invoke data storage error handler */ 33769deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 33779deb041cSRichard Henderson } 33789deb041cSRichard Henderson tcg_temp_free(discard); 33799deb041cSRichard Henderson tcg_temp_free(EA); 3380a3401188SBalamuruhan S } 3381a3401188SBalamuruhan S 33829deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 33839deb041cSRichard Henderson { 33849deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 33859deb041cSRichard Henderson } 33869deb041cSRichard Henderson 33879deb041cSRichard Henderson #ifdef TARGET_PPC64 33889deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 33899deb041cSRichard Henderson { 33909deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 33919deb041cSRichard Henderson } 3392a3401188SBalamuruhan S #endif 3393a3401188SBalamuruhan S 339414776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3395fcf5ef2aSThomas Huth { 3396253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3397253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3398d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3399d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3400fcf5ef2aSThomas Huth 3401d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3402d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3403d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3404d8b86898SRichard Henderson tcg_temp_free(t0); 3405253ce7b2SNikunj A Dadhania 3406253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3407253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3408253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3409253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3410253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3411253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3412253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3413253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3414253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3415253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3416253ce7b2SNikunj A Dadhania 3417fcf5ef2aSThomas Huth gen_set_label(l1); 34184771df23SNikunj A Dadhania 3419efe843d8SDavid Gibson /* 3420efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3421efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3422efe843d8SDavid Gibson */ 34234771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3424253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3425253ce7b2SNikunj A Dadhania 3426253ce7b2SNikunj A Dadhania gen_set_label(l2); 3427fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3428fcf5ef2aSThomas Huth } 3429fcf5ef2aSThomas Huth 3430fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3431fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3432fcf5ef2aSThomas Huth { \ 3433d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3434fcf5ef2aSThomas Huth } 3435fcf5ef2aSThomas Huth 3436fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3437fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3438fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3439fcf5ef2aSThomas Huth 3440fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3441fcf5ef2aSThomas Huth /* ldarx */ 3442fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3443fcf5ef2aSThomas Huth /* stdcx. */ 3444fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3445fcf5ef2aSThomas Huth 3446fcf5ef2aSThomas Huth /* lqarx */ 3447fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3448fcf5ef2aSThomas Huth { 3449fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 345094bf2658SRichard Henderson TCGv EA, hi, lo; 3451fcf5ef2aSThomas Huth 3452fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3453fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3454fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3455fcf5ef2aSThomas Huth return; 3456fcf5ef2aSThomas Huth } 3457fcf5ef2aSThomas Huth 3458fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 345994bf2658SRichard Henderson EA = tcg_temp_new(); 3460fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 346194bf2658SRichard Henderson 346294bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 346394bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 346494bf2658SRichard Henderson hi = cpu_gpr[rd]; 346594bf2658SRichard Henderson 346694bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3467f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 346894bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 346994bf2658SRichard Henderson if (ctx->le_mode) { 347094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 347194bf2658SRichard Henderson ctx->mem_idx)); 347294bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3473fcf5ef2aSThomas Huth } else { 347494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 347594bf2658SRichard Henderson ctx->mem_idx)); 347694bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3477fcf5ef2aSThomas Huth } 347894bf2658SRichard Henderson tcg_temp_free_i32(oi); 347994bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3480f34ec0f6SRichard Henderson } else { 348194bf2658SRichard Henderson /* Restart with exclusive lock. */ 348294bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 348394bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 348494bf2658SRichard Henderson tcg_temp_free(EA); 348594bf2658SRichard Henderson return; 3486f34ec0f6SRichard Henderson } 348794bf2658SRichard Henderson } else if (ctx->le_mode) { 348894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3489fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3490fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 349194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 349294bf2658SRichard Henderson } else { 349394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 349494bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 349594bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 349694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 349794bf2658SRichard Henderson } 3498fcf5ef2aSThomas Huth tcg_temp_free(EA); 349994bf2658SRichard Henderson 350094bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 350194bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3502fcf5ef2aSThomas Huth } 3503fcf5ef2aSThomas Huth 3504fcf5ef2aSThomas Huth /* stqcx. */ 3505fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3506fcf5ef2aSThomas Huth { 35074a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 35084a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3509fcf5ef2aSThomas Huth 35104a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3511fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3512fcf5ef2aSThomas Huth return; 3513fcf5ef2aSThomas Huth } 35144a9b3c5dSRichard Henderson 3515fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 35164a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3517fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3518fcf5ef2aSThomas Huth 35194a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 35204a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 35214a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3522fcf5ef2aSThomas Huth 35234a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3524f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 35254a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 35264a9b3c5dSRichard Henderson if (ctx->le_mode) { 3527f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3528f34ec0f6SRichard Henderson EA, lo, hi, oi); 3529fcf5ef2aSThomas Huth } else { 3530f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3531f34ec0f6SRichard Henderson EA, lo, hi, oi); 3532fcf5ef2aSThomas Huth } 3533f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 3534f34ec0f6SRichard Henderson } else { 35354a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 35364a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 35374a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3538f34ec0f6SRichard Henderson } 3539fcf5ef2aSThomas Huth tcg_temp_free(EA); 35404a9b3c5dSRichard Henderson } else { 35414a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 35424a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 35434a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 35444a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 3545fcf5ef2aSThomas Huth 35464a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 35474a9b3c5dSRichard Henderson tcg_temp_free(EA); 35484a9b3c5dSRichard Henderson 35494a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 35504a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35514a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 35524a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 35534a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35544a9b3c5dSRichard Henderson 35554a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35564a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 35574a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35584a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 35594a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 35604a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35614a9b3c5dSRichard Henderson 35624a9b3c5dSRichard Henderson /* Success */ 35634a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 35644a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35654a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 35664a9b3c5dSRichard Henderson 35674a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35684a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 35694a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 35704a9b3c5dSRichard Henderson 35714a9b3c5dSRichard Henderson gen_set_label(lab_fail); 35724a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35734a9b3c5dSRichard Henderson 35744a9b3c5dSRichard Henderson gen_set_label(lab_over); 35754a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 35764a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 35774a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 35784a9b3c5dSRichard Henderson } 35794a9b3c5dSRichard Henderson } 3580fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3581fcf5ef2aSThomas Huth 3582fcf5ef2aSThomas Huth /* sync */ 3583fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3584fcf5ef2aSThomas Huth { 3585fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3586fcf5ef2aSThomas Huth 3587fcf5ef2aSThomas Huth /* 3588fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3589fcf5ef2aSThomas Huth * 3590fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3591fcf5ef2aSThomas Huth * 3592fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3593fcf5ef2aSThomas Huth * check MSR_PR as well. 3594fcf5ef2aSThomas Huth */ 3595fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3596fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3597fcf5ef2aSThomas Huth } 35984771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3599fcf5ef2aSThomas Huth } 3600fcf5ef2aSThomas Huth 3601fcf5ef2aSThomas Huth /* wait */ 3602fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3603fcf5ef2aSThomas Huth { 3604fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3605fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3606fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3607fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3608fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3609b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3610fcf5ef2aSThomas Huth } 3611fcf5ef2aSThomas Huth 3612fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3613fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3614fcf5ef2aSThomas Huth { 3615fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3616fcf5ef2aSThomas Huth GEN_PRIV; 3617fcf5ef2aSThomas Huth #else 3618fcf5ef2aSThomas Huth TCGv_i32 t; 3619fcf5ef2aSThomas Huth 3620fcf5ef2aSThomas Huth CHK_HV; 3621fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3622fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3623fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3624154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3625154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3626fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3627fcf5ef2aSThomas Huth } 3628fcf5ef2aSThomas Huth 3629fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3630fcf5ef2aSThomas Huth { 3631fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3632fcf5ef2aSThomas Huth GEN_PRIV; 3633fcf5ef2aSThomas Huth #else 3634fcf5ef2aSThomas Huth TCGv_i32 t; 3635fcf5ef2aSThomas Huth 3636fcf5ef2aSThomas Huth CHK_HV; 3637fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3638fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3639fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3640154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3641154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3642fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3643fcf5ef2aSThomas Huth } 3644fcf5ef2aSThomas Huth 3645cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3646cdee0e72SNikunj A Dadhania { 364721c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 364821c0d66aSBenjamin Herrenschmidt GEN_PRIV; 364921c0d66aSBenjamin Herrenschmidt #else 365021c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 365121c0d66aSBenjamin Herrenschmidt 365221c0d66aSBenjamin Herrenschmidt CHK_HV; 365321c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 365421c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 365521c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 365621c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 365721c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 365821c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 3659cdee0e72SNikunj A Dadhania } 3660cdee0e72SNikunj A Dadhania 3661fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3662fcf5ef2aSThomas Huth { 3663fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3664fcf5ef2aSThomas Huth GEN_PRIV; 3665fcf5ef2aSThomas Huth #else 3666fcf5ef2aSThomas Huth TCGv_i32 t; 3667fcf5ef2aSThomas Huth 3668fcf5ef2aSThomas Huth CHK_HV; 3669fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3670fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3671fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3672154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3673154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3674fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3675fcf5ef2aSThomas Huth } 3676fcf5ef2aSThomas Huth 3677fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3678fcf5ef2aSThomas Huth { 3679fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3680fcf5ef2aSThomas Huth GEN_PRIV; 3681fcf5ef2aSThomas Huth #else 3682fcf5ef2aSThomas Huth TCGv_i32 t; 3683fcf5ef2aSThomas Huth 3684fcf5ef2aSThomas Huth CHK_HV; 3685fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3686fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3687fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3688154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3689154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3690fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3691fcf5ef2aSThomas Huth } 3692fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3693fcf5ef2aSThomas Huth 3694fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3695fcf5ef2aSThomas Huth { 3696fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3697efe843d8SDavid Gibson if (ctx->has_cfar) { 3698fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3699efe843d8SDavid Gibson } 3700fcf5ef2aSThomas Huth #endif 3701fcf5ef2aSThomas Huth } 3702fcf5ef2aSThomas Huth 3703fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3704fcf5ef2aSThomas Huth { 3705fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3706fcf5ef2aSThomas Huth return false; 3707fcf5ef2aSThomas Huth } 3708fcf5ef2aSThomas Huth 3709fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3710b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3711fcf5ef2aSThomas Huth #else 3712fcf5ef2aSThomas Huth return true; 3713fcf5ef2aSThomas Huth #endif 3714fcf5ef2aSThomas Huth } 3715fcf5ef2aSThomas Huth 37160e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 37170e3bf489SRoman Kapl { 37180e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 37190e3bf489SRoman Kapl if (unlikely(sse)) { 37200e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 37210e3bf489SRoman Kapl gen_debug_exception(ctx); 37220e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3723e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 37240e3bf489SRoman Kapl gen_exception(ctx, excp); 37250e3bf489SRoman Kapl } 37260e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 37270e3bf489SRoman Kapl } else { 37280e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 37290e3bf489SRoman Kapl } 37300e3bf489SRoman Kapl } 37310e3bf489SRoman Kapl 3732fcf5ef2aSThomas Huth /*** Branch ***/ 3733c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3734fcf5ef2aSThomas Huth { 3735fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3736fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3737fcf5ef2aSThomas Huth } 3738fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3739fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3740fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 374107ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 3742fcf5ef2aSThomas Huth } else { 3743fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 37440e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3745fcf5ef2aSThomas Huth } 3746fcf5ef2aSThomas Huth } 3747fcf5ef2aSThomas Huth 3748fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3749fcf5ef2aSThomas Huth { 3750fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3751fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3752fcf5ef2aSThomas Huth } 3753fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3754fcf5ef2aSThomas Huth } 3755fcf5ef2aSThomas Huth 3756fcf5ef2aSThomas Huth /* b ba bl bla */ 3757fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3758fcf5ef2aSThomas Huth { 3759fcf5ef2aSThomas Huth target_ulong li, target; 3760fcf5ef2aSThomas Huth 3761fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3762fcf5ef2aSThomas Huth /* sign extend LI */ 3763fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3764fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3765fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3766b6bac4bcSEmilio G. Cota target = ctx->base.pc_next + li - 4; 3767fcf5ef2aSThomas Huth } else { 3768fcf5ef2aSThomas Huth target = li; 3769fcf5ef2aSThomas Huth } 3770fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3771b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3772fcf5ef2aSThomas Huth } 3773b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3774fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3775fcf5ef2aSThomas Huth } 3776fcf5ef2aSThomas Huth 3777fcf5ef2aSThomas Huth #define BCOND_IM 0 3778fcf5ef2aSThomas Huth #define BCOND_LR 1 3779fcf5ef2aSThomas Huth #define BCOND_CTR 2 3780fcf5ef2aSThomas Huth #define BCOND_TAR 3 3781fcf5ef2aSThomas Huth 3782c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 3783fcf5ef2aSThomas Huth { 3784fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3785fcf5ef2aSThomas Huth TCGLabel *l1; 3786fcf5ef2aSThomas Huth TCGv target; 3787fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 37880e3bf489SRoman Kapl 3789fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3790fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3791efe843d8SDavid Gibson if (type == BCOND_CTR) { 3792fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3793efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 3794fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3795efe843d8SDavid Gibson } else { 3796fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3797efe843d8SDavid Gibson } 3798fcf5ef2aSThomas Huth } else { 3799f764718dSRichard Henderson target = NULL; 3800fcf5ef2aSThomas Huth } 3801efe843d8SDavid Gibson if (LK(ctx->opcode)) { 3802b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3803efe843d8SDavid Gibson } 3804fcf5ef2aSThomas Huth l1 = gen_new_label(); 3805fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3806fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3807fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3808fa200c95SGreg Kurz 3809fa200c95SGreg Kurz if (type == BCOND_CTR) { 3810fa200c95SGreg Kurz /* 3811fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 3812fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 3813fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 381415d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 381515d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 381615d68c5eSGreg Kurz * it basically useless and thus never used in real code. 381715d68c5eSGreg Kurz * 381815d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 381915d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 382015d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 382115d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 382215d68c5eSGreg Kurz * doing anything else harmful. 3823fa200c95SGreg Kurz */ 3824d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 3825fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 38269acc95cdSGreg Kurz tcg_temp_free(temp); 38279acc95cdSGreg Kurz tcg_temp_free(target); 3828fcf5ef2aSThomas Huth return; 3829fcf5ef2aSThomas Huth } 3830fa200c95SGreg Kurz 3831fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 3832fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 3833fa200c95SGreg Kurz } else { 3834fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 3835fa200c95SGreg Kurz } 3836fa200c95SGreg Kurz if (bo & 0x2) { 3837fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3838fa200c95SGreg Kurz } else { 3839fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3840fa200c95SGreg Kurz } 3841fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3842fa200c95SGreg Kurz } else { 3843fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3844fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3845fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3846fcf5ef2aSThomas Huth } else { 3847fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3848fcf5ef2aSThomas Huth } 3849fcf5ef2aSThomas Huth if (bo & 0x2) { 3850fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3851fcf5ef2aSThomas Huth } else { 3852fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3853fcf5ef2aSThomas Huth } 3854fa200c95SGreg Kurz } 3855fcf5ef2aSThomas Huth tcg_temp_free(temp); 3856fcf5ef2aSThomas Huth } 3857fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3858fcf5ef2aSThomas Huth /* Test CR */ 3859fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3860fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3861fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3862fcf5ef2aSThomas Huth 3863fcf5ef2aSThomas Huth if (bo & 0x8) { 3864fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3865fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3866fcf5ef2aSThomas Huth } else { 3867fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3868fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3869fcf5ef2aSThomas Huth } 3870fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3871fcf5ef2aSThomas Huth } 3872b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3873fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3874fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3875fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3876b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3877fcf5ef2aSThomas Huth } else { 3878fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3879fcf5ef2aSThomas Huth } 3880fcf5ef2aSThomas Huth } else { 3881fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3882fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3883fcf5ef2aSThomas Huth } else { 3884fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3885fcf5ef2aSThomas Huth } 38860e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3887c4a2e3a9SRichard Henderson tcg_temp_free(target); 3888c4a2e3a9SRichard Henderson } 3889fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 38900e3bf489SRoman Kapl /* fallthrough case */ 3891fcf5ef2aSThomas Huth gen_set_label(l1); 3892b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 3893fcf5ef2aSThomas Huth } 3894fcf5ef2aSThomas Huth } 3895fcf5ef2aSThomas Huth 3896fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3897fcf5ef2aSThomas Huth { 3898fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3899fcf5ef2aSThomas Huth } 3900fcf5ef2aSThomas Huth 3901fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3902fcf5ef2aSThomas Huth { 3903fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3904fcf5ef2aSThomas Huth } 3905fcf5ef2aSThomas Huth 3906fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3907fcf5ef2aSThomas Huth { 3908fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3909fcf5ef2aSThomas Huth } 3910fcf5ef2aSThomas Huth 3911fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3912fcf5ef2aSThomas Huth { 3913fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3914fcf5ef2aSThomas Huth } 3915fcf5ef2aSThomas Huth 3916fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3917fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3918fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3919fcf5ef2aSThomas Huth { \ 3920fcf5ef2aSThomas Huth uint8_t bitmask; \ 3921fcf5ef2aSThomas Huth int sh; \ 3922fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3923fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3924fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3925fcf5ef2aSThomas Huth if (sh > 0) \ 3926fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3927fcf5ef2aSThomas Huth else if (sh < 0) \ 3928fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3929fcf5ef2aSThomas Huth else \ 3930fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3931fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3932fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3933fcf5ef2aSThomas Huth if (sh > 0) \ 3934fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3935fcf5ef2aSThomas Huth else if (sh < 0) \ 3936fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3937fcf5ef2aSThomas Huth else \ 3938fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3939fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3940fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3941fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3942fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3943fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3944fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3945fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3946fcf5ef2aSThomas Huth } 3947fcf5ef2aSThomas Huth 3948fcf5ef2aSThomas Huth /* crand */ 3949fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3950fcf5ef2aSThomas Huth /* crandc */ 3951fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3952fcf5ef2aSThomas Huth /* creqv */ 3953fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3954fcf5ef2aSThomas Huth /* crnand */ 3955fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3956fcf5ef2aSThomas Huth /* crnor */ 3957fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3958fcf5ef2aSThomas Huth /* cror */ 3959fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3960fcf5ef2aSThomas Huth /* crorc */ 3961fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3962fcf5ef2aSThomas Huth /* crxor */ 3963fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3964fcf5ef2aSThomas Huth 3965fcf5ef2aSThomas Huth /* mcrf */ 3966fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3967fcf5ef2aSThomas Huth { 3968fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3969fcf5ef2aSThomas Huth } 3970fcf5ef2aSThomas Huth 3971fcf5ef2aSThomas Huth /*** System linkage ***/ 3972fcf5ef2aSThomas Huth 3973fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3974fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3975fcf5ef2aSThomas Huth { 3976fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3977fcf5ef2aSThomas Huth GEN_PRIV; 3978fcf5ef2aSThomas Huth #else 3979efe843d8SDavid Gibson /* 3980efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 3981fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3982fcf5ef2aSThomas Huth */ 3983d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 3984fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3985fcf5ef2aSThomas Huth return; 3986fcf5ef2aSThomas Huth } 3987fcf5ef2aSThomas Huth /* Restore CPU state */ 3988fcf5ef2aSThomas Huth CHK_SV; 3989a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3990a59d628fSMaria Klimushenkova gen_io_start(); 3991a59d628fSMaria Klimushenkova } 3992b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3993fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3994fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3995fcf5ef2aSThomas Huth #endif 3996fcf5ef2aSThomas Huth } 3997fcf5ef2aSThomas Huth 3998fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3999fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4000fcf5ef2aSThomas Huth { 4001fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4002fcf5ef2aSThomas Huth GEN_PRIV; 4003fcf5ef2aSThomas Huth #else 4004fcf5ef2aSThomas Huth /* Restore CPU state */ 4005fcf5ef2aSThomas Huth CHK_SV; 4006a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4007a59d628fSMaria Klimushenkova gen_io_start(); 4008a59d628fSMaria Klimushenkova } 4009b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 4010fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 4011fcf5ef2aSThomas Huth gen_sync_exception(ctx); 4012fcf5ef2aSThomas Huth #endif 4013fcf5ef2aSThomas Huth } 4014fcf5ef2aSThomas Huth 4015fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4016fcf5ef2aSThomas Huth { 4017fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4018fcf5ef2aSThomas Huth GEN_PRIV; 4019fcf5ef2aSThomas Huth #else 4020fcf5ef2aSThomas Huth /* Restore CPU state */ 4021fcf5ef2aSThomas Huth CHK_HV; 4022fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 4023fcf5ef2aSThomas Huth gen_sync_exception(ctx); 4024fcf5ef2aSThomas Huth #endif 4025fcf5ef2aSThomas Huth } 4026fcf5ef2aSThomas Huth #endif 4027fcf5ef2aSThomas Huth 4028fcf5ef2aSThomas Huth /* sc */ 4029fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4030fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4031fcf5ef2aSThomas Huth #else 4032fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4033fcf5ef2aSThomas Huth #endif 4034fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4035fcf5ef2aSThomas Huth { 4036fcf5ef2aSThomas Huth uint32_t lev; 4037fcf5ef2aSThomas Huth 4038fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4039fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4040fcf5ef2aSThomas Huth } 4041fcf5ef2aSThomas Huth 4042fcf5ef2aSThomas Huth /*** Trap ***/ 4043fcf5ef2aSThomas Huth 4044fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4045fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4046fcf5ef2aSThomas Huth { 4047fcf5ef2aSThomas Huth /* Trap never */ 4048fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4049fcf5ef2aSThomas Huth return true; 4050fcf5ef2aSThomas Huth } 4051fcf5ef2aSThomas Huth /* Trap always */ 4052fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4053fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4054fcf5ef2aSThomas Huth return true; 4055fcf5ef2aSThomas Huth } 4056fcf5ef2aSThomas Huth return false; 4057fcf5ef2aSThomas Huth } 4058fcf5ef2aSThomas Huth 4059fcf5ef2aSThomas Huth /* tw */ 4060fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4061fcf5ef2aSThomas Huth { 4062fcf5ef2aSThomas Huth TCGv_i32 t0; 4063fcf5ef2aSThomas Huth 4064fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4065fcf5ef2aSThomas Huth return; 4066fcf5ef2aSThomas Huth } 4067fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4068fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4069fcf5ef2aSThomas Huth t0); 4070fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4071fcf5ef2aSThomas Huth } 4072fcf5ef2aSThomas Huth 4073fcf5ef2aSThomas Huth /* twi */ 4074fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4075fcf5ef2aSThomas Huth { 4076fcf5ef2aSThomas Huth TCGv t0; 4077fcf5ef2aSThomas Huth TCGv_i32 t1; 4078fcf5ef2aSThomas Huth 4079fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4080fcf5ef2aSThomas Huth return; 4081fcf5ef2aSThomas Huth } 4082fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4083fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4084fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4085fcf5ef2aSThomas Huth tcg_temp_free(t0); 4086fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4087fcf5ef2aSThomas Huth } 4088fcf5ef2aSThomas Huth 4089fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4090fcf5ef2aSThomas Huth /* td */ 4091fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4092fcf5ef2aSThomas Huth { 4093fcf5ef2aSThomas Huth TCGv_i32 t0; 4094fcf5ef2aSThomas Huth 4095fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4096fcf5ef2aSThomas Huth return; 4097fcf5ef2aSThomas Huth } 4098fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4099fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4100fcf5ef2aSThomas Huth t0); 4101fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4102fcf5ef2aSThomas Huth } 4103fcf5ef2aSThomas Huth 4104fcf5ef2aSThomas Huth /* tdi */ 4105fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4106fcf5ef2aSThomas Huth { 4107fcf5ef2aSThomas Huth TCGv t0; 4108fcf5ef2aSThomas Huth TCGv_i32 t1; 4109fcf5ef2aSThomas Huth 4110fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4111fcf5ef2aSThomas Huth return; 4112fcf5ef2aSThomas Huth } 4113fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4114fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4115fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4116fcf5ef2aSThomas Huth tcg_temp_free(t0); 4117fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4118fcf5ef2aSThomas Huth } 4119fcf5ef2aSThomas Huth #endif 4120fcf5ef2aSThomas Huth 4121fcf5ef2aSThomas Huth /*** Processor control ***/ 4122fcf5ef2aSThomas Huth 4123dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 4124fcf5ef2aSThomas Huth { 4125fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4126fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4127fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4128fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 4129fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4130fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4131fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4132fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 4133fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 4134fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 4135dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 4136dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4137dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4138dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4139dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4140dd09c361SNikunj A Dadhania } 4141fcf5ef2aSThomas Huth tcg_temp_free(t0); 4142fcf5ef2aSThomas Huth tcg_temp_free(t1); 4143fcf5ef2aSThomas Huth tcg_temp_free(t2); 4144fcf5ef2aSThomas Huth } 4145fcf5ef2aSThomas Huth 4146fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 4147fcf5ef2aSThomas Huth { 4148dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 4149fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 4150dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 4151dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 4152dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 4153dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4154dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 41551bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 41561bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 41571bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4158fcf5ef2aSThomas Huth } 4159fcf5ef2aSThomas Huth 4160fcf5ef2aSThomas Huth /* mcrxr */ 4161fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4162fcf5ef2aSThomas Huth { 4163fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4164fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4165fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4166fcf5ef2aSThomas Huth 4167fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4168fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4169fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4170fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4171fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4172fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4173fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4174fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4175fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4176fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4177fcf5ef2aSThomas Huth 4178fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4179fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4180fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4181fcf5ef2aSThomas Huth } 4182fcf5ef2aSThomas Huth 4183b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4184b63d0434SNikunj A Dadhania /* mcrxrx */ 4185b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4186b63d0434SNikunj A Dadhania { 4187b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4188b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4189b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4190b63d0434SNikunj A Dadhania 4191b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4192b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4193b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4194b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4195b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4196b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4197b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4198b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4199b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4200b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4201b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4202b63d0434SNikunj A Dadhania } 4203b63d0434SNikunj A Dadhania #endif 4204b63d0434SNikunj A Dadhania 4205fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4206fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4207fcf5ef2aSThomas Huth { 4208fcf5ef2aSThomas Huth uint32_t crm, crn; 4209fcf5ef2aSThomas Huth 4210fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4211fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4212fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4213fcf5ef2aSThomas Huth crn = ctz32(crm); 4214fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4215fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4216fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4217fcf5ef2aSThomas Huth } 4218fcf5ef2aSThomas Huth } else { 4219fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4220fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4221fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4222fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4223fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4224fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4225fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4226fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4227fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4228fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4229fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4230fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4231fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4232fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4233fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4234fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4235fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4236fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4237fcf5ef2aSThomas Huth } 4238fcf5ef2aSThomas Huth } 4239fcf5ef2aSThomas Huth 4240fcf5ef2aSThomas Huth /* mfmsr */ 4241fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4242fcf5ef2aSThomas Huth { 4243fcf5ef2aSThomas Huth CHK_SV; 4244fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4245fcf5ef2aSThomas Huth } 4246fcf5ef2aSThomas Huth 4247fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4248fcf5ef2aSThomas Huth { 4249fcf5ef2aSThomas Huth #if 0 4250fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4251fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 4252fcf5ef2aSThomas Huth #endif 4253fcf5ef2aSThomas Huth } 4254fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 4255fcf5ef2aSThomas Huth 4256fcf5ef2aSThomas Huth /* mfspr */ 4257fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4258fcf5ef2aSThomas Huth { 4259fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4260fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4261fcf5ef2aSThomas Huth 4262fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4263fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4264fcf5ef2aSThomas Huth #else 4265fcf5ef2aSThomas Huth if (ctx->pr) { 4266fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4267fcf5ef2aSThomas Huth } else if (ctx->hv) { 4268fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4269fcf5ef2aSThomas Huth } else { 4270fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4271fcf5ef2aSThomas Huth } 4272fcf5ef2aSThomas Huth #endif 4273fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4274fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4275fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4276fcf5ef2aSThomas Huth } else { 4277fcf5ef2aSThomas Huth /* Privilege exception */ 4278efe843d8SDavid Gibson /* 4279efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4280fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4281fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4282fcf5ef2aSThomas Huth */ 4283fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 428431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 428531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4286b6bac4bcSEmilio G. Cota ctx->base.pc_next - 4); 4287fcf5ef2aSThomas Huth } 4288fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4289fcf5ef2aSThomas Huth } 4290fcf5ef2aSThomas Huth } else { 4291fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4292fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4293fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4294fcf5ef2aSThomas Huth /* This is a nop */ 4295fcf5ef2aSThomas Huth return; 4296fcf5ef2aSThomas Huth } 4297fcf5ef2aSThomas Huth /* Not defined */ 429831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 429931085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 4300b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4301fcf5ef2aSThomas Huth 4302efe843d8SDavid Gibson /* 4303efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4304efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4305fcf5ef2aSThomas Huth */ 4306fcf5ef2aSThomas Huth if (sprn & 0x10) { 4307fcf5ef2aSThomas Huth if (ctx->pr) { 4308fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4309fcf5ef2aSThomas Huth } 4310fcf5ef2aSThomas Huth } else { 4311fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4312fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4313fcf5ef2aSThomas Huth } 4314fcf5ef2aSThomas Huth } 4315fcf5ef2aSThomas Huth } 4316fcf5ef2aSThomas Huth } 4317fcf5ef2aSThomas Huth 4318fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4319fcf5ef2aSThomas Huth { 4320fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4321fcf5ef2aSThomas Huth } 4322fcf5ef2aSThomas Huth 4323fcf5ef2aSThomas Huth /* mftb */ 4324fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4325fcf5ef2aSThomas Huth { 4326fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4327fcf5ef2aSThomas Huth } 4328fcf5ef2aSThomas Huth 4329fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4330fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4331fcf5ef2aSThomas Huth { 4332fcf5ef2aSThomas Huth uint32_t crm, crn; 4333fcf5ef2aSThomas Huth 4334fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4335fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4336fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4337fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4338fcf5ef2aSThomas Huth crn = ctz32(crm); 4339fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4340fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4341fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4342fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4343fcf5ef2aSThomas Huth } 4344fcf5ef2aSThomas Huth } else { 4345fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4346fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4347fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4348fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4349fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4350fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4351fcf5ef2aSThomas Huth } 4352fcf5ef2aSThomas Huth } 4353fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4354fcf5ef2aSThomas Huth } 4355fcf5ef2aSThomas Huth } 4356fcf5ef2aSThomas Huth 4357fcf5ef2aSThomas Huth /* mtmsr */ 4358fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4359fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4360fcf5ef2aSThomas Huth { 4361fcf5ef2aSThomas Huth CHK_SV; 4362fcf5ef2aSThomas Huth 4363fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4364fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4365fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4366fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4367efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4368efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 4369efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_msr, cpu_msr, 4370efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4371fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4372fcf5ef2aSThomas Huth tcg_temp_free(t0); 4373fcf5ef2aSThomas Huth } else { 4374efe843d8SDavid Gibson /* 4375efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4376efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4377efe843d8SDavid Gibson * ppc_store_msr 4378fcf5ef2aSThomas Huth */ 4379b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4380b8edea50SPavel Dovgalyuk gen_io_start(); 4381b8edea50SPavel Dovgalyuk } 4382b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4383fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4384fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4385fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4386fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4387fcf5ef2aSThomas Huth } 4388fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4389fcf5ef2aSThomas Huth } 4390fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4391fcf5ef2aSThomas Huth 4392fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4393fcf5ef2aSThomas Huth { 4394fcf5ef2aSThomas Huth CHK_SV; 4395fcf5ef2aSThomas Huth 4396fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4397fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4398fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4399fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4400efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4401efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 4402efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_msr, cpu_msr, 4403efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4404fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4405fcf5ef2aSThomas Huth tcg_temp_free(t0); 4406fcf5ef2aSThomas Huth } else { 4407fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4408fcf5ef2aSThomas Huth 4409efe843d8SDavid Gibson /* 4410efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4411efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4412efe843d8SDavid Gibson * ppc_store_msr 4413fcf5ef2aSThomas Huth */ 4414b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4415b8edea50SPavel Dovgalyuk gen_io_start(); 4416b8edea50SPavel Dovgalyuk } 4417b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4418fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4419fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4420fcf5ef2aSThomas Huth #else 4421fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4422fcf5ef2aSThomas Huth #endif 4423fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4424fcf5ef2aSThomas Huth tcg_temp_free(msr); 4425fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4426fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4427fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4428fcf5ef2aSThomas Huth } 4429fcf5ef2aSThomas Huth #endif 4430fcf5ef2aSThomas Huth } 4431fcf5ef2aSThomas Huth 4432fcf5ef2aSThomas Huth /* mtspr */ 4433fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4434fcf5ef2aSThomas Huth { 4435fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4436fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4437fcf5ef2aSThomas Huth 4438fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4439fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4440fcf5ef2aSThomas Huth #else 4441fcf5ef2aSThomas Huth if (ctx->pr) { 4442fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4443fcf5ef2aSThomas Huth } else if (ctx->hv) { 4444fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4445fcf5ef2aSThomas Huth } else { 4446fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4447fcf5ef2aSThomas Huth } 4448fcf5ef2aSThomas Huth #endif 4449fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4450fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4451fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4452fcf5ef2aSThomas Huth } else { 4453fcf5ef2aSThomas Huth /* Privilege exception */ 445431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 445531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 445631085338SThomas Huth ctx->base.pc_next - 4); 4457fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4458fcf5ef2aSThomas Huth } 4459fcf5ef2aSThomas Huth } else { 4460fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4461fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4462fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4463fcf5ef2aSThomas Huth /* This is a nop */ 4464fcf5ef2aSThomas Huth return; 4465fcf5ef2aSThomas Huth } 4466fcf5ef2aSThomas Huth 4467fcf5ef2aSThomas Huth /* Not defined */ 446831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 446931085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 4470b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4471fcf5ef2aSThomas Huth 4472fcf5ef2aSThomas Huth 4473efe843d8SDavid Gibson /* 4474efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4475efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4476fcf5ef2aSThomas Huth */ 4477fcf5ef2aSThomas Huth if (sprn & 0x10) { 4478fcf5ef2aSThomas Huth if (ctx->pr) { 4479fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4480fcf5ef2aSThomas Huth } 4481fcf5ef2aSThomas Huth } else { 4482fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4483fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4484fcf5ef2aSThomas Huth } 4485fcf5ef2aSThomas Huth } 4486fcf5ef2aSThomas Huth } 4487fcf5ef2aSThomas Huth } 4488fcf5ef2aSThomas Huth 4489fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4490fcf5ef2aSThomas Huth /* setb */ 4491fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4492fcf5ef2aSThomas Huth { 4493fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4494fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4495fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4496fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4497fcf5ef2aSThomas Huth 4498fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4499fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4500fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4501fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4502fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4503fcf5ef2aSThomas Huth 4504fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4505fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4506fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4507fcf5ef2aSThomas Huth } 4508fcf5ef2aSThomas Huth #endif 4509fcf5ef2aSThomas Huth 4510fcf5ef2aSThomas Huth /*** Cache management ***/ 4511fcf5ef2aSThomas Huth 4512fcf5ef2aSThomas Huth /* dcbf */ 4513fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4514fcf5ef2aSThomas Huth { 4515fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4516fcf5ef2aSThomas Huth TCGv t0; 4517fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4518fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4519fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4520fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4521fcf5ef2aSThomas Huth tcg_temp_free(t0); 4522fcf5ef2aSThomas Huth } 4523fcf5ef2aSThomas Huth 452450728199SRoman Kapl /* dcbfep (external PID dcbf) */ 452550728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 452650728199SRoman Kapl { 452750728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 452850728199SRoman Kapl TCGv t0; 452950728199SRoman Kapl CHK_SV; 453050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 453150728199SRoman Kapl t0 = tcg_temp_new(); 453250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 453350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 453450728199SRoman Kapl tcg_temp_free(t0); 453550728199SRoman Kapl } 453650728199SRoman Kapl 4537fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4538fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4539fcf5ef2aSThomas Huth { 4540fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4541fcf5ef2aSThomas Huth GEN_PRIV; 4542fcf5ef2aSThomas Huth #else 4543fcf5ef2aSThomas Huth TCGv EA, val; 4544fcf5ef2aSThomas Huth 4545fcf5ef2aSThomas Huth CHK_SV; 4546fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4547fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4548fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4549fcf5ef2aSThomas Huth val = tcg_temp_new(); 4550fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4551fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4552fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4553fcf5ef2aSThomas Huth tcg_temp_free(val); 4554fcf5ef2aSThomas Huth tcg_temp_free(EA); 4555fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4556fcf5ef2aSThomas Huth } 4557fcf5ef2aSThomas Huth 4558fcf5ef2aSThomas Huth /* dcdst */ 4559fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4560fcf5ef2aSThomas Huth { 4561fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4562fcf5ef2aSThomas Huth TCGv t0; 4563fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4564fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4565fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4566fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4567fcf5ef2aSThomas Huth tcg_temp_free(t0); 4568fcf5ef2aSThomas Huth } 4569fcf5ef2aSThomas Huth 457050728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 457150728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 457250728199SRoman Kapl { 457350728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 457450728199SRoman Kapl TCGv t0; 457550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 457650728199SRoman Kapl t0 = tcg_temp_new(); 457750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 457850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 457950728199SRoman Kapl tcg_temp_free(t0); 458050728199SRoman Kapl } 458150728199SRoman Kapl 4582fcf5ef2aSThomas Huth /* dcbt */ 4583fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4584fcf5ef2aSThomas Huth { 4585efe843d8SDavid Gibson /* 4586efe843d8SDavid Gibson * interpreted as no-op 4587efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4588efe843d8SDavid Gibson * does not generate any exception 4589fcf5ef2aSThomas Huth */ 4590fcf5ef2aSThomas Huth } 4591fcf5ef2aSThomas Huth 459250728199SRoman Kapl /* dcbtep */ 459350728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 459450728199SRoman Kapl { 4595efe843d8SDavid Gibson /* 4596efe843d8SDavid Gibson * interpreted as no-op 4597efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4598efe843d8SDavid Gibson * does not generate any exception 459950728199SRoman Kapl */ 460050728199SRoman Kapl } 460150728199SRoman Kapl 4602fcf5ef2aSThomas Huth /* dcbtst */ 4603fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4604fcf5ef2aSThomas Huth { 4605efe843d8SDavid Gibson /* 4606efe843d8SDavid Gibson * interpreted as no-op 4607efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4608efe843d8SDavid Gibson * does not generate any exception 4609fcf5ef2aSThomas Huth */ 4610fcf5ef2aSThomas Huth } 4611fcf5ef2aSThomas Huth 461250728199SRoman Kapl /* dcbtstep */ 461350728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 461450728199SRoman Kapl { 4615efe843d8SDavid Gibson /* 4616efe843d8SDavid Gibson * interpreted as no-op 4617efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4618efe843d8SDavid Gibson * does not generate any exception 461950728199SRoman Kapl */ 462050728199SRoman Kapl } 462150728199SRoman Kapl 4622fcf5ef2aSThomas Huth /* dcbtls */ 4623fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4624fcf5ef2aSThomas Huth { 4625fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4626fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4627fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4628fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4629fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4630fcf5ef2aSThomas Huth tcg_temp_free(t0); 4631fcf5ef2aSThomas Huth } 4632fcf5ef2aSThomas Huth 4633fcf5ef2aSThomas Huth /* dcbz */ 4634fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4635fcf5ef2aSThomas Huth { 4636fcf5ef2aSThomas Huth TCGv tcgv_addr; 4637fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4638fcf5ef2aSThomas Huth 4639fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4640fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4641fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4642fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4643fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4644fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4645fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4646fcf5ef2aSThomas Huth } 4647fcf5ef2aSThomas Huth 464850728199SRoman Kapl /* dcbzep */ 464950728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 465050728199SRoman Kapl { 465150728199SRoman Kapl TCGv tcgv_addr; 465250728199SRoman Kapl TCGv_i32 tcgv_op; 465350728199SRoman Kapl 465450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 465550728199SRoman Kapl tcgv_addr = tcg_temp_new(); 465650728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 465750728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 465850728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 465950728199SRoman Kapl tcg_temp_free(tcgv_addr); 466050728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 466150728199SRoman Kapl } 466250728199SRoman Kapl 4663fcf5ef2aSThomas Huth /* dst / dstt */ 4664fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4665fcf5ef2aSThomas Huth { 4666fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4667fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4668fcf5ef2aSThomas Huth } else { 4669fcf5ef2aSThomas Huth /* interpreted as no-op */ 4670fcf5ef2aSThomas Huth } 4671fcf5ef2aSThomas Huth } 4672fcf5ef2aSThomas Huth 4673fcf5ef2aSThomas Huth /* dstst /dststt */ 4674fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4675fcf5ef2aSThomas Huth { 4676fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4677fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4678fcf5ef2aSThomas Huth } else { 4679fcf5ef2aSThomas Huth /* interpreted as no-op */ 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth 4682fcf5ef2aSThomas Huth } 4683fcf5ef2aSThomas Huth 4684fcf5ef2aSThomas Huth /* dss / dssall */ 4685fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4686fcf5ef2aSThomas Huth { 4687fcf5ef2aSThomas Huth /* interpreted as no-op */ 4688fcf5ef2aSThomas Huth } 4689fcf5ef2aSThomas Huth 4690fcf5ef2aSThomas Huth /* icbi */ 4691fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4692fcf5ef2aSThomas Huth { 4693fcf5ef2aSThomas Huth TCGv t0; 4694fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4695fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4696fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4697fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4698fcf5ef2aSThomas Huth tcg_temp_free(t0); 4699fcf5ef2aSThomas Huth } 4700fcf5ef2aSThomas Huth 470150728199SRoman Kapl /* icbiep */ 470250728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 470350728199SRoman Kapl { 470450728199SRoman Kapl TCGv t0; 470550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 470650728199SRoman Kapl t0 = tcg_temp_new(); 470750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 470850728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 470950728199SRoman Kapl tcg_temp_free(t0); 471050728199SRoman Kapl } 471150728199SRoman Kapl 4712fcf5ef2aSThomas Huth /* Optional: */ 4713fcf5ef2aSThomas Huth /* dcba */ 4714fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4715fcf5ef2aSThomas Huth { 4716efe843d8SDavid Gibson /* 4717efe843d8SDavid Gibson * interpreted as no-op 4718efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 4719fcf5ef2aSThomas Huth * but does not generate any exception 4720fcf5ef2aSThomas Huth */ 4721fcf5ef2aSThomas Huth } 4722fcf5ef2aSThomas Huth 4723fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4724fcf5ef2aSThomas Huth /* Supervisor only: */ 4725fcf5ef2aSThomas Huth 4726fcf5ef2aSThomas Huth /* mfsr */ 4727fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4728fcf5ef2aSThomas Huth { 4729fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4730fcf5ef2aSThomas Huth GEN_PRIV; 4731fcf5ef2aSThomas Huth #else 4732fcf5ef2aSThomas Huth TCGv t0; 4733fcf5ef2aSThomas Huth 4734fcf5ef2aSThomas Huth CHK_SV; 4735fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4736fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4737fcf5ef2aSThomas Huth tcg_temp_free(t0); 4738fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4739fcf5ef2aSThomas Huth } 4740fcf5ef2aSThomas Huth 4741fcf5ef2aSThomas Huth /* mfsrin */ 4742fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4743fcf5ef2aSThomas Huth { 4744fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4745fcf5ef2aSThomas Huth GEN_PRIV; 4746fcf5ef2aSThomas Huth #else 4747fcf5ef2aSThomas Huth TCGv t0; 4748fcf5ef2aSThomas Huth 4749fcf5ef2aSThomas Huth CHK_SV; 4750fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4751e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4752fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4753fcf5ef2aSThomas Huth tcg_temp_free(t0); 4754fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4755fcf5ef2aSThomas Huth } 4756fcf5ef2aSThomas Huth 4757fcf5ef2aSThomas Huth /* mtsr */ 4758fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4759fcf5ef2aSThomas Huth { 4760fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4761fcf5ef2aSThomas Huth GEN_PRIV; 4762fcf5ef2aSThomas Huth #else 4763fcf5ef2aSThomas Huth TCGv t0; 4764fcf5ef2aSThomas Huth 4765fcf5ef2aSThomas Huth CHK_SV; 4766fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4767fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4768fcf5ef2aSThomas Huth tcg_temp_free(t0); 4769fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4770fcf5ef2aSThomas Huth } 4771fcf5ef2aSThomas Huth 4772fcf5ef2aSThomas Huth /* mtsrin */ 4773fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4774fcf5ef2aSThomas Huth { 4775fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4776fcf5ef2aSThomas Huth GEN_PRIV; 4777fcf5ef2aSThomas Huth #else 4778fcf5ef2aSThomas Huth TCGv t0; 4779fcf5ef2aSThomas Huth CHK_SV; 4780fcf5ef2aSThomas Huth 4781fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4782e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4783fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4784fcf5ef2aSThomas Huth tcg_temp_free(t0); 4785fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4786fcf5ef2aSThomas Huth } 4787fcf5ef2aSThomas Huth 4788fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4789fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4790fcf5ef2aSThomas Huth 4791fcf5ef2aSThomas Huth /* mfsr */ 4792fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4793fcf5ef2aSThomas Huth { 4794fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4795fcf5ef2aSThomas Huth GEN_PRIV; 4796fcf5ef2aSThomas Huth #else 4797fcf5ef2aSThomas Huth TCGv t0; 4798fcf5ef2aSThomas Huth 4799fcf5ef2aSThomas Huth CHK_SV; 4800fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4801fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4802fcf5ef2aSThomas Huth tcg_temp_free(t0); 4803fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4804fcf5ef2aSThomas Huth } 4805fcf5ef2aSThomas Huth 4806fcf5ef2aSThomas Huth /* mfsrin */ 4807fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4808fcf5ef2aSThomas Huth { 4809fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4810fcf5ef2aSThomas Huth GEN_PRIV; 4811fcf5ef2aSThomas Huth #else 4812fcf5ef2aSThomas Huth TCGv t0; 4813fcf5ef2aSThomas Huth 4814fcf5ef2aSThomas Huth CHK_SV; 4815fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4816e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4817fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4818fcf5ef2aSThomas Huth tcg_temp_free(t0); 4819fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4820fcf5ef2aSThomas Huth } 4821fcf5ef2aSThomas Huth 4822fcf5ef2aSThomas Huth /* mtsr */ 4823fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4824fcf5ef2aSThomas Huth { 4825fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4826fcf5ef2aSThomas Huth GEN_PRIV; 4827fcf5ef2aSThomas Huth #else 4828fcf5ef2aSThomas Huth TCGv t0; 4829fcf5ef2aSThomas Huth 4830fcf5ef2aSThomas Huth CHK_SV; 4831fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4832fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4833fcf5ef2aSThomas Huth tcg_temp_free(t0); 4834fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4835fcf5ef2aSThomas Huth } 4836fcf5ef2aSThomas Huth 4837fcf5ef2aSThomas Huth /* mtsrin */ 4838fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4839fcf5ef2aSThomas Huth { 4840fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4841fcf5ef2aSThomas Huth GEN_PRIV; 4842fcf5ef2aSThomas Huth #else 4843fcf5ef2aSThomas Huth TCGv t0; 4844fcf5ef2aSThomas Huth 4845fcf5ef2aSThomas Huth CHK_SV; 4846fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4847e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4848fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4849fcf5ef2aSThomas Huth tcg_temp_free(t0); 4850fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4851fcf5ef2aSThomas Huth } 4852fcf5ef2aSThomas Huth 4853fcf5ef2aSThomas Huth /* slbmte */ 4854fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4855fcf5ef2aSThomas Huth { 4856fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4857fcf5ef2aSThomas Huth GEN_PRIV; 4858fcf5ef2aSThomas Huth #else 4859fcf5ef2aSThomas Huth CHK_SV; 4860fcf5ef2aSThomas Huth 4861fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4862fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4863fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4864fcf5ef2aSThomas Huth } 4865fcf5ef2aSThomas Huth 4866fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4867fcf5ef2aSThomas Huth { 4868fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4869fcf5ef2aSThomas Huth GEN_PRIV; 4870fcf5ef2aSThomas Huth #else 4871fcf5ef2aSThomas Huth CHK_SV; 4872fcf5ef2aSThomas Huth 4873fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4874fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4875fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4876fcf5ef2aSThomas Huth } 4877fcf5ef2aSThomas Huth 4878fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4879fcf5ef2aSThomas Huth { 4880fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4881fcf5ef2aSThomas Huth GEN_PRIV; 4882fcf5ef2aSThomas Huth #else 4883fcf5ef2aSThomas Huth CHK_SV; 4884fcf5ef2aSThomas Huth 4885fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4886fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4887fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4888fcf5ef2aSThomas Huth } 4889fcf5ef2aSThomas Huth 4890fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4891fcf5ef2aSThomas Huth { 4892fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4893fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4894fcf5ef2aSThomas Huth #else 4895fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4896fcf5ef2aSThomas Huth 4897fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4898fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4899fcf5ef2aSThomas Huth return; 4900fcf5ef2aSThomas Huth } 4901fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4902fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4903fcf5ef2aSThomas Huth l1 = gen_new_label(); 4904fcf5ef2aSThomas Huth l2 = gen_new_label(); 4905fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4906fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4907efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4908fcf5ef2aSThomas Huth tcg_gen_br(l2); 4909fcf5ef2aSThomas Huth gen_set_label(l1); 4910fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4911fcf5ef2aSThomas Huth gen_set_label(l2); 4912fcf5ef2aSThomas Huth #endif 4913fcf5ef2aSThomas Huth } 4914fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4915fcf5ef2aSThomas Huth 4916fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4917fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4918fcf5ef2aSThomas Huth 4919fcf5ef2aSThomas Huth /* tlbia */ 4920fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4921fcf5ef2aSThomas Huth { 4922fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4923fcf5ef2aSThomas Huth GEN_PRIV; 4924fcf5ef2aSThomas Huth #else 4925fcf5ef2aSThomas Huth CHK_HV; 4926fcf5ef2aSThomas Huth 4927fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4928fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4929fcf5ef2aSThomas Huth } 4930fcf5ef2aSThomas Huth 4931fcf5ef2aSThomas Huth /* tlbiel */ 4932fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4933fcf5ef2aSThomas Huth { 4934fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4935fcf5ef2aSThomas Huth GEN_PRIV; 4936fcf5ef2aSThomas Huth #else 4937fcf5ef2aSThomas Huth CHK_SV; 4938fcf5ef2aSThomas Huth 4939fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4940fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4941fcf5ef2aSThomas Huth } 4942fcf5ef2aSThomas Huth 4943fcf5ef2aSThomas Huth /* tlbie */ 4944fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4945fcf5ef2aSThomas Huth { 4946fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4947fcf5ef2aSThomas Huth GEN_PRIV; 4948fcf5ef2aSThomas Huth #else 4949fcf5ef2aSThomas Huth TCGv_i32 t1; 4950c6fd28fdSSuraj Jitindar Singh 4951c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 495291c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4953c6fd28fdSSuraj Jitindar Singh } else { 4954c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 4955c6fd28fdSSuraj Jitindar Singh } 4956fcf5ef2aSThomas Huth 4957fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4958fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4959fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4960fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4961fcf5ef2aSThomas Huth tcg_temp_free(t0); 4962fcf5ef2aSThomas Huth } else { 4963fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4964fcf5ef2aSThomas Huth } 4965fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4966fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4967fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4968fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4969fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4970fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4971fcf5ef2aSThomas Huth } 4972fcf5ef2aSThomas Huth 4973fcf5ef2aSThomas Huth /* tlbsync */ 4974fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4975fcf5ef2aSThomas Huth { 4976fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4977fcf5ef2aSThomas Huth GEN_PRIV; 4978fcf5ef2aSThomas Huth #else 497991c60f12SCédric Le Goater 498091c60f12SCédric Le Goater if (ctx->gtse) { 498191c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 498291c60f12SCédric Le Goater } else { 498391c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 498491c60f12SCédric Le Goater } 4985fcf5ef2aSThomas Huth 4986fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4987fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4988fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4989fcf5ef2aSThomas Huth } 4990fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4991fcf5ef2aSThomas Huth } 4992fcf5ef2aSThomas Huth 4993fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4994fcf5ef2aSThomas Huth /* slbia */ 4995fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 4996fcf5ef2aSThomas Huth { 4997fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4998fcf5ef2aSThomas Huth GEN_PRIV; 4999fcf5ef2aSThomas Huth #else 5000fcf5ef2aSThomas Huth CHK_SV; 5001fcf5ef2aSThomas Huth 5002fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 5003fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5004fcf5ef2aSThomas Huth } 5005fcf5ef2aSThomas Huth 5006fcf5ef2aSThomas Huth /* slbie */ 5007fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5008fcf5ef2aSThomas Huth { 5009fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5010fcf5ef2aSThomas Huth GEN_PRIV; 5011fcf5ef2aSThomas Huth #else 5012fcf5ef2aSThomas Huth CHK_SV; 5013fcf5ef2aSThomas Huth 5014fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5015fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5016fcf5ef2aSThomas Huth } 5017a63f1dfcSNikunj A Dadhania 5018a63f1dfcSNikunj A Dadhania /* slbieg */ 5019a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5020a63f1dfcSNikunj A Dadhania { 5021a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5022a63f1dfcSNikunj A Dadhania GEN_PRIV; 5023a63f1dfcSNikunj A Dadhania #else 5024a63f1dfcSNikunj A Dadhania CHK_SV; 5025a63f1dfcSNikunj A Dadhania 5026a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5027a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5028a63f1dfcSNikunj A Dadhania } 5029a63f1dfcSNikunj A Dadhania 503062d897caSNikunj A Dadhania /* slbsync */ 503162d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 503262d897caSNikunj A Dadhania { 503362d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 503462d897caSNikunj A Dadhania GEN_PRIV; 503562d897caSNikunj A Dadhania #else 503662d897caSNikunj A Dadhania CHK_SV; 503762d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 503862d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 503962d897caSNikunj A Dadhania } 504062d897caSNikunj A Dadhania 5041fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5042fcf5ef2aSThomas Huth 5043fcf5ef2aSThomas Huth /*** External control ***/ 5044fcf5ef2aSThomas Huth /* Optional: */ 5045fcf5ef2aSThomas Huth 5046fcf5ef2aSThomas Huth /* eciwx */ 5047fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5048fcf5ef2aSThomas Huth { 5049fcf5ef2aSThomas Huth TCGv t0; 5050fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5051fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5052fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5053fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5054c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5055c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5056fcf5ef2aSThomas Huth tcg_temp_free(t0); 5057fcf5ef2aSThomas Huth } 5058fcf5ef2aSThomas Huth 5059fcf5ef2aSThomas Huth /* ecowx */ 5060fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5061fcf5ef2aSThomas Huth { 5062fcf5ef2aSThomas Huth TCGv t0; 5063fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5064fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5065fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5066fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5067c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5068c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5069fcf5ef2aSThomas Huth tcg_temp_free(t0); 5070fcf5ef2aSThomas Huth } 5071fcf5ef2aSThomas Huth 5072fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5073fcf5ef2aSThomas Huth 5074fcf5ef2aSThomas Huth /* abs - abs. */ 5075fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5076fcf5ef2aSThomas Huth { 5077fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5078fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5079fe21b785SRichard Henderson 5080fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5081efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5082fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5083fcf5ef2aSThomas Huth } 5084efe843d8SDavid Gibson } 5085fcf5ef2aSThomas Huth 5086fcf5ef2aSThomas Huth /* abso - abso. */ 5087fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5088fcf5ef2aSThomas Huth { 5089fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5090fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5091fe21b785SRichard Henderson 5092fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5093fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5094fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5095efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5096fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5097fcf5ef2aSThomas Huth } 5098efe843d8SDavid Gibson } 5099fcf5ef2aSThomas Huth 5100fcf5ef2aSThomas Huth /* clcs */ 5101fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5102fcf5ef2aSThomas Huth { 5103fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5104fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5105fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5106fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5107fcf5ef2aSThomas Huth } 5108fcf5ef2aSThomas Huth 5109fcf5ef2aSThomas Huth /* div - div. */ 5110fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5111fcf5ef2aSThomas Huth { 5112fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5113fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5114efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5115fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5116fcf5ef2aSThomas Huth } 5117efe843d8SDavid Gibson } 5118fcf5ef2aSThomas Huth 5119fcf5ef2aSThomas Huth /* divo - divo. */ 5120fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5121fcf5ef2aSThomas Huth { 5122fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5123fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5124efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5125fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5126fcf5ef2aSThomas Huth } 5127efe843d8SDavid Gibson } 5128fcf5ef2aSThomas Huth 5129fcf5ef2aSThomas Huth /* divs - divs. */ 5130fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5131fcf5ef2aSThomas Huth { 5132fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5133fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5134efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5135fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5136fcf5ef2aSThomas Huth } 5137efe843d8SDavid Gibson } 5138fcf5ef2aSThomas Huth 5139fcf5ef2aSThomas Huth /* divso - divso. */ 5140fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5141fcf5ef2aSThomas Huth { 5142fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5143fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5144efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5145fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5146fcf5ef2aSThomas Huth } 5147efe843d8SDavid Gibson } 5148fcf5ef2aSThomas Huth 5149fcf5ef2aSThomas Huth /* doz - doz. */ 5150fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5151fcf5ef2aSThomas Huth { 5152fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5153fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5154efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5155efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5156efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5157efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5158fcf5ef2aSThomas Huth tcg_gen_br(l2); 5159fcf5ef2aSThomas Huth gen_set_label(l1); 5160fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5161fcf5ef2aSThomas Huth gen_set_label(l2); 5162efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5163fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5164fcf5ef2aSThomas Huth } 5165efe843d8SDavid Gibson } 5166fcf5ef2aSThomas Huth 5167fcf5ef2aSThomas Huth /* dozo - dozo. */ 5168fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5169fcf5ef2aSThomas Huth { 5170fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5171fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5172fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5173fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5174fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5175fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5176fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5177efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5178efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5179fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5180fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5181fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5182fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5183fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5184fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5185fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5186fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5187fcf5ef2aSThomas Huth tcg_gen_br(l2); 5188fcf5ef2aSThomas Huth gen_set_label(l1); 5189fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5190fcf5ef2aSThomas Huth gen_set_label(l2); 5191fcf5ef2aSThomas Huth tcg_temp_free(t0); 5192fcf5ef2aSThomas Huth tcg_temp_free(t1); 5193fcf5ef2aSThomas Huth tcg_temp_free(t2); 5194efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5195fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5196fcf5ef2aSThomas Huth } 5197efe843d8SDavid Gibson } 5198fcf5ef2aSThomas Huth 5199fcf5ef2aSThomas Huth /* dozi */ 5200fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5201fcf5ef2aSThomas Huth { 5202fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5203fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5204fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5205fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5206fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5207fcf5ef2aSThomas Huth tcg_gen_br(l2); 5208fcf5ef2aSThomas Huth gen_set_label(l1); 5209fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5210fcf5ef2aSThomas Huth gen_set_label(l2); 5211efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5212fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5213fcf5ef2aSThomas Huth } 5214efe843d8SDavid Gibson } 5215fcf5ef2aSThomas Huth 5216fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5217fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5218fcf5ef2aSThomas Huth { 5219fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5220fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5221fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5222fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5223fcf5ef2aSThomas Huth 5224fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5225fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5226fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5227fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5228fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5229fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5230fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5231efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5232fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5233efe843d8SDavid Gibson } 5234fcf5ef2aSThomas Huth tcg_temp_free(t0); 5235fcf5ef2aSThomas Huth } 5236fcf5ef2aSThomas Huth 5237fcf5ef2aSThomas Huth /* maskg - maskg. */ 5238fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5239fcf5ef2aSThomas Huth { 5240fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5241fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5242fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5243fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5244fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5245fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5246fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5247fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5248fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5249fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5250fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5251fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5252fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5253fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5254fcf5ef2aSThomas Huth gen_set_label(l1); 5255fcf5ef2aSThomas Huth tcg_temp_free(t0); 5256fcf5ef2aSThomas Huth tcg_temp_free(t1); 5257fcf5ef2aSThomas Huth tcg_temp_free(t2); 5258fcf5ef2aSThomas Huth tcg_temp_free(t3); 5259efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5260fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5261fcf5ef2aSThomas Huth } 5262efe843d8SDavid Gibson } 5263fcf5ef2aSThomas Huth 5264fcf5ef2aSThomas Huth /* maskir - maskir. */ 5265fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5266fcf5ef2aSThomas Huth { 5267fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5268fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5269fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5270fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5271fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5272fcf5ef2aSThomas Huth tcg_temp_free(t0); 5273fcf5ef2aSThomas Huth tcg_temp_free(t1); 5274efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5275fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5276fcf5ef2aSThomas Huth } 5277efe843d8SDavid Gibson } 5278fcf5ef2aSThomas Huth 5279fcf5ef2aSThomas Huth /* mul - mul. */ 5280fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5281fcf5ef2aSThomas Huth { 5282fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5283fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5284fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5285fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5286fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5287fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5288fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5289fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5290fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5291fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5292fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5293fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5294fcf5ef2aSThomas Huth tcg_temp_free(t2); 5295efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5296fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5297fcf5ef2aSThomas Huth } 5298efe843d8SDavid Gibson } 5299fcf5ef2aSThomas Huth 5300fcf5ef2aSThomas Huth /* mulo - mulo. */ 5301fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5302fcf5ef2aSThomas Huth { 5303fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5304fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5305fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5306fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5307fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5308fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5309fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5310fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5311fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5312fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5313fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5314fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5315fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5316fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5317fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5318fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5319fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5320fcf5ef2aSThomas Huth gen_set_label(l1); 5321fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5322fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5323fcf5ef2aSThomas Huth tcg_temp_free(t2); 5324efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5325fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5326fcf5ef2aSThomas Huth } 5327efe843d8SDavid Gibson } 5328fcf5ef2aSThomas Huth 5329fcf5ef2aSThomas Huth /* nabs - nabs. */ 5330fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5331fcf5ef2aSThomas Huth { 5332fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5333fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5334fe21b785SRichard Henderson 5335fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5336fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5337efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5338fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5339fcf5ef2aSThomas Huth } 5340efe843d8SDavid Gibson } 5341fcf5ef2aSThomas Huth 5342fcf5ef2aSThomas Huth /* nabso - nabso. */ 5343fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5344fcf5ef2aSThomas Huth { 5345fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5346fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5347fe21b785SRichard Henderson 5348fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5349fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5350fcf5ef2aSThomas Huth /* nabs never overflows */ 5351fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5352efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5353fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5354fcf5ef2aSThomas Huth } 5355efe843d8SDavid Gibson } 5356fcf5ef2aSThomas Huth 5357fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5358fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5359fcf5ef2aSThomas Huth { 5360fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5361fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5362fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5363fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5364fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5365fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5366efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5367efe843d8SDavid Gibson ~MASK(mb, me)); 5368fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5369fcf5ef2aSThomas Huth tcg_temp_free(t0); 5370efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5371fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5372fcf5ef2aSThomas Huth } 5373efe843d8SDavid Gibson } 5374fcf5ef2aSThomas Huth 5375fcf5ef2aSThomas Huth /* rrib - rrib. */ 5376fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5377fcf5ef2aSThomas Huth { 5378fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5379fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5380fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5381fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5382fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5383fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5384fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5385fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5386fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5387fcf5ef2aSThomas Huth tcg_temp_free(t0); 5388fcf5ef2aSThomas Huth tcg_temp_free(t1); 5389efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5390fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5391fcf5ef2aSThomas Huth } 5392efe843d8SDavid Gibson } 5393fcf5ef2aSThomas Huth 5394fcf5ef2aSThomas Huth /* sle - sle. */ 5395fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5396fcf5ef2aSThomas Huth { 5397fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5398fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5399fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5400fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5401fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5402fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5403fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5404fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5405fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5406fcf5ef2aSThomas Huth tcg_temp_free(t0); 5407fcf5ef2aSThomas Huth tcg_temp_free(t1); 5408efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5409fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5410fcf5ef2aSThomas Huth } 5411efe843d8SDavid Gibson } 5412fcf5ef2aSThomas Huth 5413fcf5ef2aSThomas Huth /* sleq - sleq. */ 5414fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5415fcf5ef2aSThomas Huth { 5416fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5417fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5418fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5419fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5420fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5421fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5422fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5423fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5424fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5425fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5426fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5427fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5428fcf5ef2aSThomas Huth tcg_temp_free(t0); 5429fcf5ef2aSThomas Huth tcg_temp_free(t1); 5430fcf5ef2aSThomas Huth tcg_temp_free(t2); 5431efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5432fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5433fcf5ef2aSThomas Huth } 5434efe843d8SDavid Gibson } 5435fcf5ef2aSThomas Huth 5436fcf5ef2aSThomas Huth /* sliq - sliq. */ 5437fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5438fcf5ef2aSThomas Huth { 5439fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5440fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5441fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5442fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5443fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5444fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5445fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5446fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5447fcf5ef2aSThomas Huth tcg_temp_free(t0); 5448fcf5ef2aSThomas Huth tcg_temp_free(t1); 5449efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5450fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5451fcf5ef2aSThomas Huth } 5452efe843d8SDavid Gibson } 5453fcf5ef2aSThomas Huth 5454fcf5ef2aSThomas Huth /* slliq - slliq. */ 5455fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5456fcf5ef2aSThomas Huth { 5457fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5458fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5459fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5460fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5461fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5462fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5463fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5464fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5465fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5466fcf5ef2aSThomas Huth tcg_temp_free(t0); 5467fcf5ef2aSThomas Huth tcg_temp_free(t1); 5468efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5469fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5470fcf5ef2aSThomas Huth } 5471efe843d8SDavid Gibson } 5472fcf5ef2aSThomas Huth 5473fcf5ef2aSThomas Huth /* sllq - sllq. */ 5474fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5475fcf5ef2aSThomas Huth { 5476fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5477fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5478fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5479fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5480fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5481fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5482fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5483fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5484fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5485fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5486fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5487fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5488fcf5ef2aSThomas Huth tcg_gen_br(l2); 5489fcf5ef2aSThomas Huth gen_set_label(l1); 5490fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5491fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5492fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5493fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5494fcf5ef2aSThomas Huth gen_set_label(l2); 5495fcf5ef2aSThomas Huth tcg_temp_free(t0); 5496fcf5ef2aSThomas Huth tcg_temp_free(t1); 5497fcf5ef2aSThomas Huth tcg_temp_free(t2); 5498efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5499fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5500fcf5ef2aSThomas Huth } 5501efe843d8SDavid Gibson } 5502fcf5ef2aSThomas Huth 5503fcf5ef2aSThomas Huth /* slq - slq. */ 5504fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5505fcf5ef2aSThomas Huth { 5506fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5507fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5508fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5509fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5510fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5511fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5512fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5513fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5514fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5515fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5516fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5517fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5518fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5519fcf5ef2aSThomas Huth gen_set_label(l1); 5520fcf5ef2aSThomas Huth tcg_temp_free(t0); 5521fcf5ef2aSThomas Huth tcg_temp_free(t1); 5522efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5523fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5524fcf5ef2aSThomas Huth } 5525efe843d8SDavid Gibson } 5526fcf5ef2aSThomas Huth 5527fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5528fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5529fcf5ef2aSThomas Huth { 5530fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5531fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5532fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5533fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5534fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5535fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5536fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5537fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5538fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5539fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5540fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5541fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5542fcf5ef2aSThomas Huth gen_set_label(l1); 5543fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5544fcf5ef2aSThomas Huth tcg_temp_free(t0); 5545fcf5ef2aSThomas Huth tcg_temp_free(t1); 5546efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5547fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5548fcf5ef2aSThomas Huth } 5549efe843d8SDavid Gibson } 5550fcf5ef2aSThomas Huth 5551fcf5ef2aSThomas Huth /* sraq - sraq. */ 5552fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5553fcf5ef2aSThomas Huth { 5554fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5555fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5556fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5557fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5558fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5559fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5560fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5561fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5562fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5563fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5564fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5565fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5566fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5567fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5568fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5569fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5570fcf5ef2aSThomas Huth gen_set_label(l1); 5571fcf5ef2aSThomas Huth tcg_temp_free(t0); 5572fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5573fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5574fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5575fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5576fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5577fcf5ef2aSThomas Huth gen_set_label(l2); 5578fcf5ef2aSThomas Huth tcg_temp_free(t1); 5579fcf5ef2aSThomas Huth tcg_temp_free(t2); 5580efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5581fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5582fcf5ef2aSThomas Huth } 5583efe843d8SDavid Gibson } 5584fcf5ef2aSThomas Huth 5585fcf5ef2aSThomas Huth /* sre - sre. */ 5586fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5587fcf5ef2aSThomas Huth { 5588fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5589fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5590fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5591fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5592fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5593fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5594fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5595fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5596fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5597fcf5ef2aSThomas Huth tcg_temp_free(t0); 5598fcf5ef2aSThomas Huth tcg_temp_free(t1); 5599efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5600fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5601fcf5ef2aSThomas Huth } 5602efe843d8SDavid Gibson } 5603fcf5ef2aSThomas Huth 5604fcf5ef2aSThomas Huth /* srea - srea. */ 5605fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5606fcf5ef2aSThomas Huth { 5607fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5608fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5609fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5610fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5611fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5612fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5613fcf5ef2aSThomas Huth tcg_temp_free(t0); 5614fcf5ef2aSThomas Huth tcg_temp_free(t1); 5615efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5616fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5617fcf5ef2aSThomas Huth } 5618efe843d8SDavid Gibson } 5619fcf5ef2aSThomas Huth 5620fcf5ef2aSThomas Huth /* sreq */ 5621fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5622fcf5ef2aSThomas Huth { 5623fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5624fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5625fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5626fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5627fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5628fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5629fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5630fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5631fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5632fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5633fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5634fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5635fcf5ef2aSThomas Huth tcg_temp_free(t0); 5636fcf5ef2aSThomas Huth tcg_temp_free(t1); 5637fcf5ef2aSThomas Huth tcg_temp_free(t2); 5638efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5639fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5640fcf5ef2aSThomas Huth } 5641efe843d8SDavid Gibson } 5642fcf5ef2aSThomas Huth 5643fcf5ef2aSThomas Huth /* sriq */ 5644fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5645fcf5ef2aSThomas Huth { 5646fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5647fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5648fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5649fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5650fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5651fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5652fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5653fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5654fcf5ef2aSThomas Huth tcg_temp_free(t0); 5655fcf5ef2aSThomas Huth tcg_temp_free(t1); 5656efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5657fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5658fcf5ef2aSThomas Huth } 5659efe843d8SDavid Gibson } 5660fcf5ef2aSThomas Huth 5661fcf5ef2aSThomas Huth /* srliq */ 5662fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5663fcf5ef2aSThomas Huth { 5664fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5665fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5666fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5667fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5668fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5669fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5670fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5671fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5672fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5673fcf5ef2aSThomas Huth tcg_temp_free(t0); 5674fcf5ef2aSThomas Huth tcg_temp_free(t1); 5675efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5676fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5677fcf5ef2aSThomas Huth } 5678efe843d8SDavid Gibson } 5679fcf5ef2aSThomas Huth 5680fcf5ef2aSThomas Huth /* srlq */ 5681fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5682fcf5ef2aSThomas Huth { 5683fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5684fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5685fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5686fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5687fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5688fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5689fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5690fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5691fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5692fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5693fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5694fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5695fcf5ef2aSThomas Huth tcg_gen_br(l2); 5696fcf5ef2aSThomas Huth gen_set_label(l1); 5697fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5698fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5699fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5700fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5701fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5702fcf5ef2aSThomas Huth gen_set_label(l2); 5703fcf5ef2aSThomas Huth tcg_temp_free(t0); 5704fcf5ef2aSThomas Huth tcg_temp_free(t1); 5705fcf5ef2aSThomas Huth tcg_temp_free(t2); 5706efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5707fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5708fcf5ef2aSThomas Huth } 5709efe843d8SDavid Gibson } 5710fcf5ef2aSThomas Huth 5711fcf5ef2aSThomas Huth /* srq */ 5712fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5713fcf5ef2aSThomas Huth { 5714fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5715fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5716fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5717fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5718fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5719fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5720fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5721fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5722fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5723fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5724fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5725fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5726fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5727fcf5ef2aSThomas Huth gen_set_label(l1); 5728fcf5ef2aSThomas Huth tcg_temp_free(t0); 5729fcf5ef2aSThomas Huth tcg_temp_free(t1); 5730efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5731fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5732fcf5ef2aSThomas Huth } 5733efe843d8SDavid Gibson } 5734fcf5ef2aSThomas Huth 5735fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5736fcf5ef2aSThomas Huth 5737fcf5ef2aSThomas Huth /* dsa */ 5738fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5739fcf5ef2aSThomas Huth { 5740fcf5ef2aSThomas Huth /* XXX: TODO */ 5741fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5742fcf5ef2aSThomas Huth } 5743fcf5ef2aSThomas Huth 5744fcf5ef2aSThomas Huth /* esa */ 5745fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5746fcf5ef2aSThomas Huth { 5747fcf5ef2aSThomas Huth /* XXX: TODO */ 5748fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5749fcf5ef2aSThomas Huth } 5750fcf5ef2aSThomas Huth 5751fcf5ef2aSThomas Huth /* mfrom */ 5752fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5753fcf5ef2aSThomas Huth { 5754fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5755fcf5ef2aSThomas Huth GEN_PRIV; 5756fcf5ef2aSThomas Huth #else 5757fcf5ef2aSThomas Huth CHK_SV; 5758fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5759fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5760fcf5ef2aSThomas Huth } 5761fcf5ef2aSThomas Huth 5762fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5763fcf5ef2aSThomas Huth 5764fcf5ef2aSThomas Huth /* tlbld */ 5765fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5766fcf5ef2aSThomas Huth { 5767fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5768fcf5ef2aSThomas Huth GEN_PRIV; 5769fcf5ef2aSThomas Huth #else 5770fcf5ef2aSThomas Huth CHK_SV; 5771fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5772fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5773fcf5ef2aSThomas Huth } 5774fcf5ef2aSThomas Huth 5775fcf5ef2aSThomas Huth /* tlbli */ 5776fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5777fcf5ef2aSThomas Huth { 5778fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5779fcf5ef2aSThomas Huth GEN_PRIV; 5780fcf5ef2aSThomas Huth #else 5781fcf5ef2aSThomas Huth CHK_SV; 5782fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5783fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5784fcf5ef2aSThomas Huth } 5785fcf5ef2aSThomas Huth 5786fcf5ef2aSThomas Huth /* 74xx TLB management */ 5787fcf5ef2aSThomas Huth 5788fcf5ef2aSThomas Huth /* tlbld */ 5789fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5790fcf5ef2aSThomas Huth { 5791fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5792fcf5ef2aSThomas Huth GEN_PRIV; 5793fcf5ef2aSThomas Huth #else 5794fcf5ef2aSThomas Huth CHK_SV; 5795fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5796fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5797fcf5ef2aSThomas Huth } 5798fcf5ef2aSThomas Huth 5799fcf5ef2aSThomas Huth /* tlbli */ 5800fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5801fcf5ef2aSThomas Huth { 5802fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5803fcf5ef2aSThomas Huth GEN_PRIV; 5804fcf5ef2aSThomas Huth #else 5805fcf5ef2aSThomas Huth CHK_SV; 5806fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5807fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5808fcf5ef2aSThomas Huth } 5809fcf5ef2aSThomas Huth 5810fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5811fcf5ef2aSThomas Huth 5812fcf5ef2aSThomas Huth /* clf */ 5813fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5814fcf5ef2aSThomas Huth { 5815fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5816fcf5ef2aSThomas Huth } 5817fcf5ef2aSThomas Huth 5818fcf5ef2aSThomas Huth /* cli */ 5819fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5820fcf5ef2aSThomas Huth { 5821fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5822fcf5ef2aSThomas Huth GEN_PRIV; 5823fcf5ef2aSThomas Huth #else 5824fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5825fcf5ef2aSThomas Huth CHK_SV; 5826fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5827fcf5ef2aSThomas Huth } 5828fcf5ef2aSThomas Huth 5829fcf5ef2aSThomas Huth /* dclst */ 5830fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5831fcf5ef2aSThomas Huth { 5832fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5833fcf5ef2aSThomas Huth } 5834fcf5ef2aSThomas Huth 5835fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5836fcf5ef2aSThomas Huth { 5837fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5838fcf5ef2aSThomas Huth GEN_PRIV; 5839fcf5ef2aSThomas Huth #else 5840fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5841fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5842fcf5ef2aSThomas Huth TCGv t0; 5843fcf5ef2aSThomas Huth 5844fcf5ef2aSThomas Huth CHK_SV; 5845fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5846fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5847e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 5848fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5849fcf5ef2aSThomas Huth tcg_temp_free(t0); 5850efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 5851fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5852efe843d8SDavid Gibson } 5853fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5854fcf5ef2aSThomas Huth } 5855fcf5ef2aSThomas Huth 5856fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5857fcf5ef2aSThomas Huth { 5858fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5859fcf5ef2aSThomas Huth GEN_PRIV; 5860fcf5ef2aSThomas Huth #else 5861fcf5ef2aSThomas Huth TCGv t0; 5862fcf5ef2aSThomas Huth 5863fcf5ef2aSThomas Huth CHK_SV; 5864fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5865fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5866fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5867fcf5ef2aSThomas Huth tcg_temp_free(t0); 5868fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5869fcf5ef2aSThomas Huth } 5870fcf5ef2aSThomas Huth 5871fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5872fcf5ef2aSThomas Huth { 5873fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5874fcf5ef2aSThomas Huth GEN_PRIV; 5875fcf5ef2aSThomas Huth #else 5876fcf5ef2aSThomas Huth CHK_SV; 5877fcf5ef2aSThomas Huth 5878fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5879fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5880fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5881fcf5ef2aSThomas Huth } 5882fcf5ef2aSThomas Huth 5883fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5884fcf5ef2aSThomas Huth 5885fcf5ef2aSThomas Huth /* BookE specific instructions */ 5886fcf5ef2aSThomas Huth 5887fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5888fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5889fcf5ef2aSThomas Huth { 5890fcf5ef2aSThomas Huth /* XXX: TODO */ 5891fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5892fcf5ef2aSThomas Huth } 5893fcf5ef2aSThomas Huth 5894fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5895fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5896fcf5ef2aSThomas Huth { 5897fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5898fcf5ef2aSThomas Huth GEN_PRIV; 5899fcf5ef2aSThomas Huth #else 5900fcf5ef2aSThomas Huth TCGv t0; 5901fcf5ef2aSThomas Huth 5902fcf5ef2aSThomas Huth CHK_SV; 5903fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5904fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5905fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5906fcf5ef2aSThomas Huth tcg_temp_free(t0); 5907fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5908fcf5ef2aSThomas Huth } 5909fcf5ef2aSThomas Huth 5910fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5911fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5912fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5913fcf5ef2aSThomas Huth { 5914fcf5ef2aSThomas Huth TCGv t0, t1; 5915fcf5ef2aSThomas Huth 5916fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5917fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5918fcf5ef2aSThomas Huth 5919fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5920fcf5ef2aSThomas Huth case 0x05: 5921fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5922fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5923fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5924fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5925fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5926fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5927fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5928fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5929fcf5ef2aSThomas Huth break; 5930fcf5ef2aSThomas Huth case 0x04: 5931fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5932fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5933fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5934fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5935fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5936fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5937fcf5ef2aSThomas Huth break; 5938fcf5ef2aSThomas Huth case 0x01: 5939fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5940fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5941fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5942fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5943fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5944fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5945fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5946fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5947fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5948fcf5ef2aSThomas Huth break; 5949fcf5ef2aSThomas Huth case 0x00: 5950fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5951fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5952fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5953fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5954fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5955fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5956fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5957fcf5ef2aSThomas Huth break; 5958fcf5ef2aSThomas Huth case 0x0D: 5959fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5960fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5961fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5962fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5963fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5964fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5965fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5966fcf5ef2aSThomas Huth break; 5967fcf5ef2aSThomas Huth case 0x0C: 5968fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5969fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5970fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5971fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5972fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5973fcf5ef2aSThomas Huth break; 5974fcf5ef2aSThomas Huth } 5975fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5976fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5977fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5978fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5979fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5980fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5981fcf5ef2aSThomas Huth } else { 5982fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5983fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5984fcf5ef2aSThomas Huth } 5985fcf5ef2aSThomas Huth 5986fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5987fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5988fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5989fcf5ef2aSThomas Huth 5990fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5991fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5992fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5993fcf5ef2aSThomas Huth } 5994fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5995fcf5ef2aSThomas Huth /* Signed */ 5996fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5997fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5998fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5999fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6000fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6001fcf5ef2aSThomas Huth /* Saturate */ 6002fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6003fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6004fcf5ef2aSThomas Huth } 6005fcf5ef2aSThomas Huth } else { 6006fcf5ef2aSThomas Huth /* Unsigned */ 6007fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6008fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6009fcf5ef2aSThomas Huth /* Saturate */ 6010fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6011fcf5ef2aSThomas Huth } 6012fcf5ef2aSThomas Huth } 6013fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6014fcf5ef2aSThomas Huth /* Check overflow */ 6015fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6016fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6017fcf5ef2aSThomas Huth } 6018fcf5ef2aSThomas Huth gen_set_label(l1); 6019fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6020fcf5ef2aSThomas Huth } 6021fcf5ef2aSThomas Huth } else { 6022fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6023fcf5ef2aSThomas Huth } 6024fcf5ef2aSThomas Huth tcg_temp_free(t0); 6025fcf5ef2aSThomas Huth tcg_temp_free(t1); 6026fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6027fcf5ef2aSThomas Huth /* Update Rc0 */ 6028fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6029fcf5ef2aSThomas Huth } 6030fcf5ef2aSThomas Huth } 6031fcf5ef2aSThomas Huth 6032fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6033fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6034fcf5ef2aSThomas Huth { \ 6035fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6036fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6037fcf5ef2aSThomas Huth } 6038fcf5ef2aSThomas Huth 6039fcf5ef2aSThomas Huth /* macchw - macchw. */ 6040fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6041fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6042fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6043fcf5ef2aSThomas Huth /* macchws - macchws. */ 6044fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6045fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6046fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6047fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6048fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6049fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6050fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6051fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6052fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6053fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6054fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6055fcf5ef2aSThomas Huth /* machhw - machhw. */ 6056fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6057fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6058fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6059fcf5ef2aSThomas Huth /* machhws - machhws. */ 6060fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6061fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6062fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6063fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6064fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6065fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6066fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6067fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6068fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6069fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6070fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6071fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6072fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6073fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6074fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6075fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6076fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6077fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6078fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6079fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6080fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6081fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6082fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6083fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6084fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6085fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6086fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6087fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6088fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6089fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6090fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6091fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6092fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6093fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6094fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6095fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6096fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6097fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6099fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6101fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6103fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6104fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6105fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6106fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6107fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6108fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6109fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6110fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6111fcf5ef2aSThomas Huth 6112fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6114fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6116fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6118fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6120fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6122fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6124fcf5ef2aSThomas Huth 6125fcf5ef2aSThomas Huth /* mfdcr */ 6126fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6127fcf5ef2aSThomas Huth { 6128fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6129fcf5ef2aSThomas Huth GEN_PRIV; 6130fcf5ef2aSThomas Huth #else 6131fcf5ef2aSThomas Huth TCGv dcrn; 6132fcf5ef2aSThomas Huth 6133fcf5ef2aSThomas Huth CHK_SV; 6134fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6135fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6136fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6137fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6138fcf5ef2aSThomas Huth } 6139fcf5ef2aSThomas Huth 6140fcf5ef2aSThomas Huth /* mtdcr */ 6141fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6142fcf5ef2aSThomas Huth { 6143fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6144fcf5ef2aSThomas Huth GEN_PRIV; 6145fcf5ef2aSThomas Huth #else 6146fcf5ef2aSThomas Huth TCGv dcrn; 6147fcf5ef2aSThomas Huth 6148fcf5ef2aSThomas Huth CHK_SV; 6149fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6150fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6151fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6152fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6153fcf5ef2aSThomas Huth } 6154fcf5ef2aSThomas Huth 6155fcf5ef2aSThomas Huth /* mfdcrx */ 6156fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6157fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6158fcf5ef2aSThomas Huth { 6159fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6160fcf5ef2aSThomas Huth GEN_PRIV; 6161fcf5ef2aSThomas Huth #else 6162fcf5ef2aSThomas Huth CHK_SV; 6163fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6164fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6165fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6166fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6167fcf5ef2aSThomas Huth } 6168fcf5ef2aSThomas Huth 6169fcf5ef2aSThomas Huth /* mtdcrx */ 6170fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6171fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6172fcf5ef2aSThomas Huth { 6173fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6174fcf5ef2aSThomas Huth GEN_PRIV; 6175fcf5ef2aSThomas Huth #else 6176fcf5ef2aSThomas Huth CHK_SV; 6177fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6178fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6179fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6180fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6181fcf5ef2aSThomas Huth } 6182fcf5ef2aSThomas Huth 6183fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6184fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6185fcf5ef2aSThomas Huth { 6186fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6187fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6188fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6189fcf5ef2aSThomas Huth } 6190fcf5ef2aSThomas Huth 6191fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6192fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6193fcf5ef2aSThomas Huth { 6194fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6195fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6196fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6197fcf5ef2aSThomas Huth } 6198fcf5ef2aSThomas Huth 6199fcf5ef2aSThomas Huth /* dccci */ 6200fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6201fcf5ef2aSThomas Huth { 6202fcf5ef2aSThomas Huth CHK_SV; 6203fcf5ef2aSThomas Huth /* interpreted as no-op */ 6204fcf5ef2aSThomas Huth } 6205fcf5ef2aSThomas Huth 6206fcf5ef2aSThomas Huth /* dcread */ 6207fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6208fcf5ef2aSThomas Huth { 6209fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6210fcf5ef2aSThomas Huth GEN_PRIV; 6211fcf5ef2aSThomas Huth #else 6212fcf5ef2aSThomas Huth TCGv EA, val; 6213fcf5ef2aSThomas Huth 6214fcf5ef2aSThomas Huth CHK_SV; 6215fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6216fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6217fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6218fcf5ef2aSThomas Huth val = tcg_temp_new(); 6219fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6220fcf5ef2aSThomas Huth tcg_temp_free(val); 6221fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6222fcf5ef2aSThomas Huth tcg_temp_free(EA); 6223fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6224fcf5ef2aSThomas Huth } 6225fcf5ef2aSThomas Huth 6226fcf5ef2aSThomas Huth /* icbt */ 6227fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6228fcf5ef2aSThomas Huth { 6229efe843d8SDavid Gibson /* 6230efe843d8SDavid Gibson * interpreted as no-op 6231efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6232efe843d8SDavid Gibson * does not generate any exception 6233fcf5ef2aSThomas Huth */ 6234fcf5ef2aSThomas Huth } 6235fcf5ef2aSThomas Huth 6236fcf5ef2aSThomas Huth /* iccci */ 6237fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6238fcf5ef2aSThomas Huth { 6239fcf5ef2aSThomas Huth CHK_SV; 6240fcf5ef2aSThomas Huth /* interpreted as no-op */ 6241fcf5ef2aSThomas Huth } 6242fcf5ef2aSThomas Huth 6243fcf5ef2aSThomas Huth /* icread */ 6244fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6245fcf5ef2aSThomas Huth { 6246fcf5ef2aSThomas Huth CHK_SV; 6247fcf5ef2aSThomas Huth /* interpreted as no-op */ 6248fcf5ef2aSThomas Huth } 6249fcf5ef2aSThomas Huth 6250fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6251fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6252fcf5ef2aSThomas Huth { 6253fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6254fcf5ef2aSThomas Huth GEN_PRIV; 6255fcf5ef2aSThomas Huth #else 6256fcf5ef2aSThomas Huth CHK_SV; 6257fcf5ef2aSThomas Huth /* Restore CPU state */ 6258fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 6259fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6260fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6261fcf5ef2aSThomas Huth } 6262fcf5ef2aSThomas Huth 6263fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6264fcf5ef2aSThomas Huth { 6265fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6266fcf5ef2aSThomas Huth GEN_PRIV; 6267fcf5ef2aSThomas Huth #else 6268fcf5ef2aSThomas Huth CHK_SV; 6269fcf5ef2aSThomas Huth /* Restore CPU state */ 6270fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 6271fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6272fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6273fcf5ef2aSThomas Huth } 6274fcf5ef2aSThomas Huth 6275fcf5ef2aSThomas Huth /* BookE specific */ 6276fcf5ef2aSThomas Huth 6277fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6278fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6279fcf5ef2aSThomas Huth { 6280fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6281fcf5ef2aSThomas Huth GEN_PRIV; 6282fcf5ef2aSThomas Huth #else 6283fcf5ef2aSThomas Huth CHK_SV; 6284fcf5ef2aSThomas Huth /* Restore CPU state */ 6285fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 6286fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6287fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6288fcf5ef2aSThomas Huth } 6289fcf5ef2aSThomas Huth 6290fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6291fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6292fcf5ef2aSThomas Huth { 6293fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6294fcf5ef2aSThomas Huth GEN_PRIV; 6295fcf5ef2aSThomas Huth #else 6296fcf5ef2aSThomas Huth CHK_SV; 6297fcf5ef2aSThomas Huth /* Restore CPU state */ 6298fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 6299fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6300fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6301fcf5ef2aSThomas Huth } 6302fcf5ef2aSThomas Huth 6303fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6304fcf5ef2aSThomas Huth 6305fcf5ef2aSThomas Huth /* tlbre */ 6306fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6307fcf5ef2aSThomas Huth { 6308fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6309fcf5ef2aSThomas Huth GEN_PRIV; 6310fcf5ef2aSThomas Huth #else 6311fcf5ef2aSThomas Huth CHK_SV; 6312fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6313fcf5ef2aSThomas Huth case 0: 6314fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6315fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6316fcf5ef2aSThomas Huth break; 6317fcf5ef2aSThomas Huth case 1: 6318fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6319fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6320fcf5ef2aSThomas Huth break; 6321fcf5ef2aSThomas Huth default: 6322fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6323fcf5ef2aSThomas Huth break; 6324fcf5ef2aSThomas Huth } 6325fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6326fcf5ef2aSThomas Huth } 6327fcf5ef2aSThomas Huth 6328fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6329fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6330fcf5ef2aSThomas Huth { 6331fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6332fcf5ef2aSThomas Huth GEN_PRIV; 6333fcf5ef2aSThomas Huth #else 6334fcf5ef2aSThomas Huth TCGv t0; 6335fcf5ef2aSThomas Huth 6336fcf5ef2aSThomas Huth CHK_SV; 6337fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6338fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6339fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6340fcf5ef2aSThomas Huth tcg_temp_free(t0); 6341fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6342fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6343fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6344fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6345fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6346fcf5ef2aSThomas Huth gen_set_label(l1); 6347fcf5ef2aSThomas Huth } 6348fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6349fcf5ef2aSThomas Huth } 6350fcf5ef2aSThomas Huth 6351fcf5ef2aSThomas Huth /* tlbwe */ 6352fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6353fcf5ef2aSThomas Huth { 6354fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6355fcf5ef2aSThomas Huth GEN_PRIV; 6356fcf5ef2aSThomas Huth #else 6357fcf5ef2aSThomas Huth CHK_SV; 6358fcf5ef2aSThomas Huth 6359fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6360fcf5ef2aSThomas Huth case 0: 6361fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6362fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6363fcf5ef2aSThomas Huth break; 6364fcf5ef2aSThomas Huth case 1: 6365fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6366fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6367fcf5ef2aSThomas Huth break; 6368fcf5ef2aSThomas Huth default: 6369fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6370fcf5ef2aSThomas Huth break; 6371fcf5ef2aSThomas Huth } 6372fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6373fcf5ef2aSThomas Huth } 6374fcf5ef2aSThomas Huth 6375fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6376fcf5ef2aSThomas Huth 6377fcf5ef2aSThomas Huth /* tlbre */ 6378fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6379fcf5ef2aSThomas Huth { 6380fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6381fcf5ef2aSThomas Huth GEN_PRIV; 6382fcf5ef2aSThomas Huth #else 6383fcf5ef2aSThomas Huth CHK_SV; 6384fcf5ef2aSThomas Huth 6385fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6386fcf5ef2aSThomas Huth case 0: 6387fcf5ef2aSThomas Huth case 1: 6388fcf5ef2aSThomas Huth case 2: 6389fcf5ef2aSThomas Huth { 6390fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6391fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6392fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6393fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6394fcf5ef2aSThomas Huth } 6395fcf5ef2aSThomas Huth break; 6396fcf5ef2aSThomas Huth default: 6397fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6398fcf5ef2aSThomas Huth break; 6399fcf5ef2aSThomas Huth } 6400fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6401fcf5ef2aSThomas Huth } 6402fcf5ef2aSThomas Huth 6403fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6404fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6405fcf5ef2aSThomas Huth { 6406fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6407fcf5ef2aSThomas Huth GEN_PRIV; 6408fcf5ef2aSThomas Huth #else 6409fcf5ef2aSThomas Huth TCGv t0; 6410fcf5ef2aSThomas Huth 6411fcf5ef2aSThomas Huth CHK_SV; 6412fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6413fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6414fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6415fcf5ef2aSThomas Huth tcg_temp_free(t0); 6416fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6417fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6418fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6419fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6420fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6421fcf5ef2aSThomas Huth gen_set_label(l1); 6422fcf5ef2aSThomas Huth } 6423fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6424fcf5ef2aSThomas Huth } 6425fcf5ef2aSThomas Huth 6426fcf5ef2aSThomas Huth /* tlbwe */ 6427fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6428fcf5ef2aSThomas Huth { 6429fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6430fcf5ef2aSThomas Huth GEN_PRIV; 6431fcf5ef2aSThomas Huth #else 6432fcf5ef2aSThomas Huth CHK_SV; 6433fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6434fcf5ef2aSThomas Huth case 0: 6435fcf5ef2aSThomas Huth case 1: 6436fcf5ef2aSThomas Huth case 2: 6437fcf5ef2aSThomas Huth { 6438fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6439fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6440fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6441fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6442fcf5ef2aSThomas Huth } 6443fcf5ef2aSThomas Huth break; 6444fcf5ef2aSThomas Huth default: 6445fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6446fcf5ef2aSThomas Huth break; 6447fcf5ef2aSThomas Huth } 6448fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6449fcf5ef2aSThomas Huth } 6450fcf5ef2aSThomas Huth 6451fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6452fcf5ef2aSThomas Huth 6453fcf5ef2aSThomas Huth /* tlbre */ 6454fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6455fcf5ef2aSThomas Huth { 6456fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6457fcf5ef2aSThomas Huth GEN_PRIV; 6458fcf5ef2aSThomas Huth #else 6459fcf5ef2aSThomas Huth CHK_SV; 6460fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6461fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6462fcf5ef2aSThomas Huth } 6463fcf5ef2aSThomas Huth 6464fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6465fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6466fcf5ef2aSThomas Huth { 6467fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6468fcf5ef2aSThomas Huth GEN_PRIV; 6469fcf5ef2aSThomas Huth #else 6470fcf5ef2aSThomas Huth TCGv t0; 6471fcf5ef2aSThomas Huth 6472fcf5ef2aSThomas Huth CHK_SV; 6473fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6474fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6475fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6476fcf5ef2aSThomas Huth } else { 6477fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6478fcf5ef2aSThomas Huth } 6479fcf5ef2aSThomas Huth 6480fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6481fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6482fcf5ef2aSThomas Huth tcg_temp_free(t0); 6483fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6484fcf5ef2aSThomas Huth } 6485fcf5ef2aSThomas Huth 6486fcf5ef2aSThomas Huth /* tlbwe */ 6487fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6488fcf5ef2aSThomas Huth { 6489fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6490fcf5ef2aSThomas Huth GEN_PRIV; 6491fcf5ef2aSThomas Huth #else 6492fcf5ef2aSThomas Huth CHK_SV; 6493fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6494fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6495fcf5ef2aSThomas Huth } 6496fcf5ef2aSThomas Huth 6497fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6498fcf5ef2aSThomas Huth { 6499fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6500fcf5ef2aSThomas Huth GEN_PRIV; 6501fcf5ef2aSThomas Huth #else 6502fcf5ef2aSThomas Huth TCGv t0; 6503fcf5ef2aSThomas Huth 6504fcf5ef2aSThomas Huth CHK_SV; 6505fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6506fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6507fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6508fcf5ef2aSThomas Huth tcg_temp_free(t0); 6509fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6510fcf5ef2aSThomas Huth } 6511fcf5ef2aSThomas Huth 6512fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6513fcf5ef2aSThomas Huth { 6514fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6515fcf5ef2aSThomas Huth GEN_PRIV; 6516fcf5ef2aSThomas Huth #else 6517fcf5ef2aSThomas Huth TCGv t0; 6518fcf5ef2aSThomas Huth 6519fcf5ef2aSThomas Huth CHK_SV; 6520fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6521fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6522fcf5ef2aSThomas Huth 6523fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 6524fcf5ef2aSThomas Huth case 0: 6525fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6526fcf5ef2aSThomas Huth break; 6527fcf5ef2aSThomas Huth case 1: 6528fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6529fcf5ef2aSThomas Huth break; 6530fcf5ef2aSThomas Huth case 3: 6531fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6532fcf5ef2aSThomas Huth break; 6533fcf5ef2aSThomas Huth default: 6534fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6535fcf5ef2aSThomas Huth break; 6536fcf5ef2aSThomas Huth } 6537fcf5ef2aSThomas Huth 6538fcf5ef2aSThomas Huth tcg_temp_free(t0); 6539fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6540fcf5ef2aSThomas Huth } 6541fcf5ef2aSThomas Huth 6542fcf5ef2aSThomas Huth 6543fcf5ef2aSThomas Huth /* wrtee */ 6544fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6545fcf5ef2aSThomas Huth { 6546fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6547fcf5ef2aSThomas Huth GEN_PRIV; 6548fcf5ef2aSThomas Huth #else 6549fcf5ef2aSThomas Huth TCGv t0; 6550fcf5ef2aSThomas Huth 6551fcf5ef2aSThomas Huth CHK_SV; 6552fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6553fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6554fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6555fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6556fcf5ef2aSThomas Huth tcg_temp_free(t0); 6557efe843d8SDavid Gibson /* 6558efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6559efe843d8SDavid Gibson * just set msr_ee to 1 6560fcf5ef2aSThomas Huth */ 6561fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6562fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6563fcf5ef2aSThomas Huth } 6564fcf5ef2aSThomas Huth 6565fcf5ef2aSThomas Huth /* wrteei */ 6566fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6567fcf5ef2aSThomas Huth { 6568fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6569fcf5ef2aSThomas Huth GEN_PRIV; 6570fcf5ef2aSThomas Huth #else 6571fcf5ef2aSThomas Huth CHK_SV; 6572fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6573fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6574fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6575fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6576fcf5ef2aSThomas Huth } else { 6577fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6578fcf5ef2aSThomas Huth } 6579fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6580fcf5ef2aSThomas Huth } 6581fcf5ef2aSThomas Huth 6582fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6583fcf5ef2aSThomas Huth 6584fcf5ef2aSThomas Huth /* dlmzb */ 6585fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6586fcf5ef2aSThomas Huth { 6587fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6588fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6589fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6590fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6591fcf5ef2aSThomas Huth } 6592fcf5ef2aSThomas Huth 6593fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6594fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6595fcf5ef2aSThomas Huth { 6596fcf5ef2aSThomas Huth /* interpreted as no-op */ 6597fcf5ef2aSThomas Huth } 6598fcf5ef2aSThomas Huth 6599fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6600fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6601fcf5ef2aSThomas Huth { 660227a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 660327a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 660427a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 660527a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 660627a3ea7eSBALATON Zoltan } 660727a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6608fcf5ef2aSThomas Huth } 6609fcf5ef2aSThomas Huth 6610fcf5ef2aSThomas Huth /* icbt */ 6611fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6612fcf5ef2aSThomas Huth { 6613efe843d8SDavid Gibson /* 6614efe843d8SDavid Gibson * interpreted as no-op 6615efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6616efe843d8SDavid Gibson * does not generate any exception 6617fcf5ef2aSThomas Huth */ 6618fcf5ef2aSThomas Huth } 6619fcf5ef2aSThomas Huth 6620fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6621fcf5ef2aSThomas Huth 6622fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6623fcf5ef2aSThomas Huth { 6624fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6625fcf5ef2aSThomas Huth GEN_PRIV; 6626fcf5ef2aSThomas Huth #else 6627ebca5e6dSCédric Le Goater CHK_HV; 6628d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 66297af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 66307af1e7b0SCédric Le Goater } else { 6631fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 66327af1e7b0SCédric Le Goater } 6633fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6634fcf5ef2aSThomas Huth } 6635fcf5ef2aSThomas Huth 6636fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6637fcf5ef2aSThomas Huth { 6638fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6639fcf5ef2aSThomas Huth GEN_PRIV; 6640fcf5ef2aSThomas Huth #else 6641ebca5e6dSCédric Le Goater CHK_HV; 6642d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 66437af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 66447af1e7b0SCédric Le Goater } else { 6645fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 66467af1e7b0SCédric Le Goater } 6647fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6648fcf5ef2aSThomas Huth } 6649fcf5ef2aSThomas Huth 66505ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 66515ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 66525ba7ba1dSCédric Le Goater { 66535ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 66545ba7ba1dSCédric Le Goater GEN_PRIV; 66555ba7ba1dSCédric Le Goater #else 66565ba7ba1dSCédric Le Goater CHK_SV; 66575ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 66585ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 66595ba7ba1dSCédric Le Goater } 66605ba7ba1dSCédric Le Goater 66615ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 66625ba7ba1dSCédric Le Goater { 66635ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 66645ba7ba1dSCédric Le Goater GEN_PRIV; 66655ba7ba1dSCédric Le Goater #else 66665ba7ba1dSCédric Le Goater CHK_SV; 66675ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 66685ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 66695ba7ba1dSCédric Le Goater } 66705ba7ba1dSCédric Le Goater #endif 66715ba7ba1dSCédric Le Goater 66727af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 66737af1e7b0SCédric Le Goater { 66747af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 66757af1e7b0SCédric Le Goater GEN_PRIV; 66767af1e7b0SCédric Le Goater #else 66777af1e7b0SCédric Le Goater CHK_HV; 66787af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 66797af1e7b0SCédric Le Goater /* interpreted as no-op */ 66807af1e7b0SCédric Le Goater } 6681fcf5ef2aSThomas Huth 6682fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6683fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6684fcf5ef2aSThomas Huth { 6685fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6686fcf5ef2aSThomas Huth 6687fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6688fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6689fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6690fcf5ef2aSThomas Huth } 6691fcf5ef2aSThomas Huth 6692fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6693fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6694fcf5ef2aSThomas Huth { 6695fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6696fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6697fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6698fcf5ef2aSThomas Huth 6699fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6700fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6701fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6702fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6703fcf5ef2aSThomas Huth } else { 6704fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6705fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6706fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6707fcf5ef2aSThomas Huth } 6708fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6709fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6710fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6711fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6712fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6713fcf5ef2aSThomas Huth } 6714fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6715fcf5ef2aSThomas Huth 6716fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6717fcf5ef2aSThomas Huth { 6718fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6719fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6720fcf5ef2aSThomas Huth return; 6721fcf5ef2aSThomas Huth } 6722fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6723fcf5ef2aSThomas Huth } 6724fcf5ef2aSThomas Huth 6725fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6726fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6727fcf5ef2aSThomas Huth { \ 6728fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6729fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6730fcf5ef2aSThomas Huth return; \ 6731fcf5ef2aSThomas Huth } \ 6732efe843d8SDavid Gibson /* \ 6733efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6734fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6735fcf5ef2aSThomas Huth * \ 6736fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6737fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6738fcf5ef2aSThomas Huth */ \ 6739fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6740fcf5ef2aSThomas Huth } 6741fcf5ef2aSThomas Huth 6742fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6743fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6744fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6745fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6746fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6747fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6748fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6749efe843d8SDavid Gibson 6750b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6751b8b4576eSSuraj Jitindar Singh { 6752efe843d8SDavid Gibson /* Do Nothing */ 6753b8b4576eSSuraj Jitindar Singh } 6754fcf5ef2aSThomas Huth 675580b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 675680b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 675780b8c1eeSNikunj A Dadhania { \ 6758efe843d8SDavid Gibson /* \ 6759efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6760efe843d8SDavid Gibson * implementation of the copy paste facility \ 676180b8c1eeSNikunj A Dadhania */ \ 676280b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 676380b8c1eeSNikunj A Dadhania } 676480b8c1eeSNikunj A Dadhania 676580b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 676680b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 676780b8c1eeSNikunj A Dadhania 6768fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6769fcf5ef2aSThomas Huth { 6770fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6771fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6772fcf5ef2aSThomas Huth return; 6773fcf5ef2aSThomas Huth } 6774efe843d8SDavid Gibson /* 6775efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6776efe843d8SDavid Gibson * simple: 6777fcf5ef2aSThomas Huth * 6778fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6779fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6780fcf5ef2aSThomas Huth */ 6781fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6782fcf5ef2aSThomas Huth } 6783fcf5ef2aSThomas Huth 6784fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6785fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6786fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6787fcf5ef2aSThomas Huth { \ 6788fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6789fcf5ef2aSThomas Huth } 6790fcf5ef2aSThomas Huth 6791fcf5ef2aSThomas Huth #else 6792fcf5ef2aSThomas Huth 6793fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6794fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6795fcf5ef2aSThomas Huth { \ 6796fcf5ef2aSThomas Huth CHK_SV; \ 6797fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6798fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6799fcf5ef2aSThomas Huth return; \ 6800fcf5ef2aSThomas Huth } \ 6801efe843d8SDavid Gibson /* \ 6802efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6803fcf5ef2aSThomas Huth * simple: \ 6804fcf5ef2aSThomas Huth * \ 6805fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6806fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6807fcf5ef2aSThomas Huth */ \ 6808fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6809fcf5ef2aSThomas Huth } 6810fcf5ef2aSThomas Huth 6811fcf5ef2aSThomas Huth #endif 6812fcf5ef2aSThomas Huth 6813fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6814fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6815fcf5ef2aSThomas Huth 68161a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 68171a404c91SMark Cave-Ayland { 6818e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 68191a404c91SMark Cave-Ayland } 68201a404c91SMark Cave-Ayland 68211a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 68221a404c91SMark Cave-Ayland { 6823e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 68241a404c91SMark Cave-Ayland } 68251a404c91SMark Cave-Ayland 6826c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6827c4a18dbfSMark Cave-Ayland { 682837da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6829c4a18dbfSMark Cave-Ayland } 6830c4a18dbfSMark Cave-Ayland 6831c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6832c4a18dbfSMark Cave-Ayland { 683337da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6834c4a18dbfSMark Cave-Ayland } 6835c4a18dbfSMark Cave-Ayland 6836fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6837fcf5ef2aSThomas Huth 6838fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6839fcf5ef2aSThomas Huth 6840fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6841fcf5ef2aSThomas Huth 6842fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6843fcf5ef2aSThomas Huth 6844fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6845fcf5ef2aSThomas Huth 68465cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 68475cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 68485cb091a4SNikunj A Dadhania { 68495cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 68505cb091a4SNikunj A Dadhania case 0: /* lfdp */ 68515cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 68525cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 68535cb091a4SNikunj A Dadhania } 68545cb091a4SNikunj A Dadhania break; 68555cb091a4SNikunj A Dadhania case 2: /* lxsd */ 68565cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 68575cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 68585cb091a4SNikunj A Dadhania } 68595cb091a4SNikunj A Dadhania break; 68605cb091a4SNikunj A Dadhania case 3: /* lxssp */ 68615cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 68625cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 68635cb091a4SNikunj A Dadhania } 68645cb091a4SNikunj A Dadhania break; 68655cb091a4SNikunj A Dadhania } 68665cb091a4SNikunj A Dadhania return gen_invalid(ctx); 68675cb091a4SNikunj A Dadhania } 68685cb091a4SNikunj A Dadhania 6869d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6870e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6871e3001664SNikunj A Dadhania { 6872e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6873e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6874e3001664SNikunj A Dadhania case 1: /* lxv */ 6875d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6876d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6877d59ba583SNikunj A Dadhania } 6878e3001664SNikunj A Dadhania break; 6879e3001664SNikunj A Dadhania case 5: /* stxv */ 6880d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6881d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6882d59ba583SNikunj A Dadhania } 6883e3001664SNikunj A Dadhania break; 6884e3001664SNikunj A Dadhania } 6885e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6886e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6887e3001664SNikunj A Dadhania case 0: /* stfdp */ 6888e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6889e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6890e3001664SNikunj A Dadhania } 6891e3001664SNikunj A Dadhania break; 6892e3001664SNikunj A Dadhania case 2: /* stxsd */ 6893e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6894e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6895e3001664SNikunj A Dadhania } 6896e3001664SNikunj A Dadhania break; 6897e3001664SNikunj A Dadhania case 3: /* stxssp */ 6898e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6899e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6900e3001664SNikunj A Dadhania } 6901e3001664SNikunj A Dadhania break; 6902e3001664SNikunj A Dadhania } 6903e3001664SNikunj A Dadhania } 6904e3001664SNikunj A Dadhania return gen_invalid(ctx); 6905e3001664SNikunj A Dadhania } 6906e3001664SNikunj A Dadhania 6907fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6908fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6909fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6910fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6911fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6912fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6913fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6914fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6915fcf5ef2aSThomas Huth #endif 6916fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6917fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6918fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6919fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6920fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6921fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6922fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6923fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6924fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6925fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6926fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6927fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6928fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6929fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6930fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6931fcf5ef2aSThomas Huth #endif 6932fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6933fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6934fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6935fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6936fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6937fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6938fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 693980b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6940b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 694180b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6942fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6943fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6944fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6945fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6946fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6947fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6948fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6949fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6950fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6951fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6952fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6953fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6954fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6955fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6956fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6957fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6958fcf5ef2aSThomas Huth #endif 6959fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6960fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6961fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6962fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6963fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6964fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6965fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6966fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6967fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6968fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6969fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6970fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6971fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6972fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6973fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6974fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6975fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6976fcf5ef2aSThomas Huth #endif 6977fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6978fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6979fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6980fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6981fcf5ef2aSThomas Huth #endif 69825cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 69835cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6984d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6985e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6986fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6987fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6988fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6989fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6990fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6991fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6992c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6993fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6994fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6995fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6996fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6997a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6998a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6999fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7000fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7001fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7002fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7003a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7004a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7005fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7006fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7007fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7008fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7009fcf5ef2aSThomas Huth #endif 7010fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7011fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7012c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7013fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7014fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7015fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7016fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7017fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7018fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7019fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7020fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7021fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 7022cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7023fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7024fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7025fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7026fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7027fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7028fcf5ef2aSThomas Huth #endif 7029fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 7030fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7031fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7032fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7033fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7034fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7035fcf5ef2aSThomas Huth #endif 7036fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7037fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7038fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7039fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7040fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7041fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7042fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7043fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7044fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7045b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7046fcf5ef2aSThomas Huth #endif 7047fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7048fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7049fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 705050728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7051fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7052fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 705350728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7054fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 705550728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7056fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 705750728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7058fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7059fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 706050728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7061fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 706299d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7063fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7064fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 706550728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7066fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7067fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7068fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7069fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7070fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7071fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7072fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7073fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7074fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7075fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7076fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7077fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7078fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7079fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7080fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7081fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7082fcf5ef2aSThomas Huth #endif 7083fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7084efe843d8SDavid Gibson /* 7085efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7086efe843d8SDavid Gibson * different ISA versions 7087efe843d8SDavid Gibson */ 7088fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7089fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7090c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7091c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7092fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7093fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7094fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7095fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7096a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 709762d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7098fcf5ef2aSThomas Huth #endif 7099fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7100fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7101fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7102fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7103fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7104fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7105fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7106fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7107fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7108fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7109fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7110fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7111fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7112fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7113fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7114fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7115fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7116fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7117fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7118fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7119fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7120fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7121fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7122fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7123fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7124fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7125fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7126fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7127fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7128fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7129fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7130fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7131fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7132fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7133fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7134fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7135fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7136fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7137fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7138fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7139fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7140fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7141fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7142fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7143fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7144fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7145fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7146fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7147fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7148fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7149fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7150fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7151fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7152fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7153fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7154fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7155fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7156fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7157fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7158fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7159fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7160fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7161fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7162fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7163fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7164fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7165fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7166fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7167fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7168fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7169fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7170fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7171fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7172fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7173fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7174fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7175fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7176fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7177fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7178fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7179fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7180fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7181fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7182fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7183fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7184fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7185fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7186fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7187fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7188fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7189fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7190fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7191fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7192fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 71937af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 71947af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7195fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7196fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7197fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7198fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7199fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 720027a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7201fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7202fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 72030c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 72040c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7205fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7206fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7207fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7208fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7209fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7210fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7211fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7212fcf5ef2aSThomas Huth PPC2_ISA300), 7213fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 72145ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 72155ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 72165ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 72175ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 7218fcf5ef2aSThomas Huth #endif 7219fcf5ef2aSThomas Huth 7220fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7221fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7222fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7223fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7224fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7225fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7226fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7227fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7228fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7229fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7230fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7231fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7232fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7233fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7234fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 72354c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7236fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7237fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7238fcf5ef2aSThomas Huth 7239fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7240fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7241fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7242fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7243fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7244fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7245fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7246fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7247fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7248fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7249fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7250fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7251fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7252fcf5ef2aSThomas Huth 7253fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7254fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7255fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7256fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7257fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7258fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7259fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7260fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7261fcf5ef2aSThomas Huth 7262fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7263fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7264fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7265fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7266fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7267fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7268fcf5ef2aSThomas Huth 7269fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7270fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7271fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7272fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7273fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7274fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7275fcf5ef2aSThomas Huth #endif 7276fcf5ef2aSThomas Huth 7277fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7278fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7279fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7280fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7281fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7282fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7283fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7284fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7285fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7286fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7287fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7288fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7289fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7290fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7291fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7292fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7293fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7294fcf5ef2aSThomas Huth 7295fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7296fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7297fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7298fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7299fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7300fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7301fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7302fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7303fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7304fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7305fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7306fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7307fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7308fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7309fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7310fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7311fcf5ef2aSThomas Huth #endif 7312fcf5ef2aSThomas Huth 7313fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7314fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7315fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7316fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7317fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7318fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7319fcf5ef2aSThomas Huth PPC_64B) 7320fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7321fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7322fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7323fcf5ef2aSThomas Huth PPC_64B), \ 7324fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7325fcf5ef2aSThomas Huth PPC_64B), \ 7326fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7327fcf5ef2aSThomas Huth PPC_64B) 7328fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7329fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7330fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7331fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7332fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7333fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7334fcf5ef2aSThomas Huth #endif 7335fcf5ef2aSThomas Huth 7336fcf5ef2aSThomas Huth #undef GEN_LD 7337fcf5ef2aSThomas Huth #undef GEN_LDU 7338fcf5ef2aSThomas Huth #undef GEN_LDUX 7339fcf5ef2aSThomas Huth #undef GEN_LDX_E 7340fcf5ef2aSThomas Huth #undef GEN_LDS 7341fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 7342fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7343fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 7344fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7345fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7346fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7347fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7348fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7349fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 7350fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 7351fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 7352fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7353fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7354fcf5ef2aSThomas Huth 7355fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7356fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7357fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7358fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7359fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7360fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7361fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7362fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7363fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7364fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7365fcf5ef2aSThomas Huth 7366fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7367fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7368fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7369fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7370fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7371fcf5ef2aSThomas Huth #endif 7372fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7373fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7374fcf5ef2aSThomas Huth 737550728199SRoman Kapl /* External PID based load */ 737650728199SRoman Kapl #undef GEN_LDEPX 737750728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 737850728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 737950728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 738050728199SRoman Kapl 738150728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 738250728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 738350728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 738450728199SRoman Kapl #if defined(TARGET_PPC64) 738550728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 738650728199SRoman Kapl #endif 738750728199SRoman Kapl 7388fcf5ef2aSThomas Huth #undef GEN_ST 7389fcf5ef2aSThomas Huth #undef GEN_STU 7390fcf5ef2aSThomas Huth #undef GEN_STUX 7391fcf5ef2aSThomas Huth #undef GEN_STX_E 7392fcf5ef2aSThomas Huth #undef GEN_STS 7393fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 7394fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7395fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 7396fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7397fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 7398fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7399fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 74000123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7401fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 7402fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 7403fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 7404fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7405fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 7406fcf5ef2aSThomas Huth 7407fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7408fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7409fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7410fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7411fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7412fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7413fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7414fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7415fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7416fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7417fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7418fcf5ef2aSThomas Huth #endif 7419fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7420fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7421fcf5ef2aSThomas Huth 742250728199SRoman Kapl #undef GEN_STEPX 742350728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 742450728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 742550728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 742650728199SRoman Kapl 742750728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 742850728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 742950728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 743050728199SRoman Kapl #if defined(TARGET_PPC64) 743150728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 743250728199SRoman Kapl #endif 743350728199SRoman Kapl 7434fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7435fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7436fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7437fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7438fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7439fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7440fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7441fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7442fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7443fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7444fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7445fcf5ef2aSThomas Huth 7446fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7447fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7448fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7449fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7450fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7451fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7452fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7453fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7454fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7455fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7456fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7457fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7458fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7459fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7460fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7461fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7462fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7463fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7464fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7465fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7466fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7467fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7468fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7469fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7470fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7471fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7472fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7473fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7474fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7475fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7476fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7477fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7478fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7479fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7480fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7481fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7482fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7483fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7484fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7485fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7486fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7487fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7488fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7489fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7490fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7491fcf5ef2aSThomas Huth 7492fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7493fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7494fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7495fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7496fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7497fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7498fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7499fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7500fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7501fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7502fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7503fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7504fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7505fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7506fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7507fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7508fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7509fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7510fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7511fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7512fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7513fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7514fcf5ef2aSThomas Huth 7515fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 7516fcf5ef2aSThomas Huth 7517fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 7518fcf5ef2aSThomas Huth 7519fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 7520fcf5ef2aSThomas Huth 7521fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 7522fcf5ef2aSThomas Huth 7523fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 7524fcf5ef2aSThomas Huth }; 7525fcf5ef2aSThomas Huth 7526fcf5ef2aSThomas Huth #include "helper_regs.h" 75275b27a92dSPaolo Bonzini #include "translate_init.inc.c" 7528fcf5ef2aSThomas Huth 7529fcf5ef2aSThomas Huth /*****************************************************************************/ 7530fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 753190c84c56SMarkus Armbruster void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7532fcf5ef2aSThomas Huth { 7533fcf5ef2aSThomas Huth #define RGPL 4 7534fcf5ef2aSThomas Huth #define RFPL 4 7535fcf5ef2aSThomas Huth 7536fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7537fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 7538fcf5ef2aSThomas Huth int i; 7539fcf5ef2aSThomas Huth 754090c84c56SMarkus Armbruster qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7541fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7542fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 7543fcf5ef2aSThomas Huth cs->cpu_index); 754490c84c56SMarkus Armbruster qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7545fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 7546fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 7547fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 7548fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 754990c84c56SMarkus Armbruster qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7550fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7551a8dafa52SSuraj Jitindar Singh " DECR " TARGET_FMT_lu 7552fcf5ef2aSThomas Huth #endif 7553fcf5ef2aSThomas Huth "\n", 7554fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7555fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7556fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 7557fcf5ef2aSThomas Huth #endif 7558fcf5ef2aSThomas Huth ); 7559fcf5ef2aSThomas Huth #endif 7560fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7561efe843d8SDavid Gibson if ((i & (RGPL - 1)) == 0) { 756290c84c56SMarkus Armbruster qemu_fprintf(f, "GPR%02d", i); 7563efe843d8SDavid Gibson } 756490c84c56SMarkus Armbruster qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7565efe843d8SDavid Gibson if ((i & (RGPL - 1)) == (RGPL - 1)) { 756690c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 7567fcf5ef2aSThomas Huth } 7568efe843d8SDavid Gibson } 756990c84c56SMarkus Armbruster qemu_fprintf(f, "CR "); 7570fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 757190c84c56SMarkus Armbruster qemu_fprintf(f, "%01x", env->crf[i]); 757290c84c56SMarkus Armbruster qemu_fprintf(f, " ["); 7573fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 7574fcf5ef2aSThomas Huth char a = '-'; 7575efe843d8SDavid Gibson if (env->crf[i] & 0x08) { 7576fcf5ef2aSThomas Huth a = 'L'; 7577efe843d8SDavid Gibson } else if (env->crf[i] & 0x04) { 7578fcf5ef2aSThomas Huth a = 'G'; 7579efe843d8SDavid Gibson } else if (env->crf[i] & 0x02) { 7580fcf5ef2aSThomas Huth a = 'E'; 7581efe843d8SDavid Gibson } 758290c84c56SMarkus Armbruster qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7583fcf5ef2aSThomas Huth } 758490c84c56SMarkus Armbruster qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7585fcf5ef2aSThomas Huth env->reserve_addr); 7586685f1ce2SRichard Henderson 7587685f1ce2SRichard Henderson if (flags & CPU_DUMP_FPU) { 7588fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7589685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == 0) { 759090c84c56SMarkus Armbruster qemu_fprintf(f, "FPR%02d", i); 7591685f1ce2SRichard Henderson } 759290c84c56SMarkus Armbruster qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7593685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == (RFPL - 1)) { 759490c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 7595fcf5ef2aSThomas Huth } 7596685f1ce2SRichard Henderson } 759790c84c56SMarkus Armbruster qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7598685f1ce2SRichard Henderson } 7599685f1ce2SRichard Henderson 7600fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 760190c84c56SMarkus Armbruster qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7602fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7603fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7604fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7605fcf5ef2aSThomas Huth 760690c84c56SMarkus Armbruster qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7607fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7608fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7609fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7610fcf5ef2aSThomas Huth 761190c84c56SMarkus Armbruster qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7612fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7613fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7614fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7615fcf5ef2aSThomas Huth 7616fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7617fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7618a790e82bSBenjamin Herrenschmidt env->excp_model == POWERPC_EXCP_POWER8 || 7619a790e82bSBenjamin Herrenschmidt env->excp_model == POWERPC_EXCP_POWER9) { 762090c84c56SMarkus Armbruster qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7621fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7622fcf5ef2aSThomas Huth } 7623fcf5ef2aSThomas Huth #endif 7624fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 762590c84c56SMarkus Armbruster qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7626fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7627fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7628fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7629fcf5ef2aSThomas Huth 763090c84c56SMarkus Armbruster qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7631fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7632fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7633fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7634fcf5ef2aSThomas Huth 763590c84c56SMarkus Armbruster qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7636fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7637fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7638fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7639fcf5ef2aSThomas Huth 764090c84c56SMarkus Armbruster qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7641fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7642fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7643fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7644fcf5ef2aSThomas Huth 7645fcf5ef2aSThomas Huth /* FSL-specific */ 764690c84c56SMarkus Armbruster qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7647fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7648fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7649fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7650fcf5ef2aSThomas Huth 7651fcf5ef2aSThomas Huth /* 7652fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7653fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7654fcf5ef2aSThomas Huth */ 7655fcf5ef2aSThomas Huth } 7656fcf5ef2aSThomas Huth 7657fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7658fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 765990c84c56SMarkus Armbruster qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7660fcf5ef2aSThomas Huth } 7661fcf5ef2aSThomas Huth #endif 7662fcf5ef2aSThomas Huth 7663efe843d8SDavid Gibson if (env->spr_cb[SPR_LPCR].name) { 766490c84c56SMarkus Armbruster qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7665efe843d8SDavid Gibson } 7666d801a61eSSuraj Jitindar Singh 76670941d728SDavid Gibson switch (env->mmu_model) { 7668fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7669fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7670fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7671fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7672fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 76730941d728SDavid Gibson case POWERPC_MMU_64B: 76740941d728SDavid Gibson case POWERPC_MMU_2_03: 76750941d728SDavid Gibson case POWERPC_MMU_2_06: 76760941d728SDavid Gibson case POWERPC_MMU_2_07: 76770941d728SDavid Gibson case POWERPC_MMU_3_00: 7678fcf5ef2aSThomas Huth #endif 76794f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 768090c84c56SMarkus Armbruster qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 76814f4f28ffSSuraj Jitindar Singh } 76824a7518e0SCédric Le Goater if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 768390c84c56SMarkus Armbruster qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 76844a7518e0SCédric Le Goater } 768590c84c56SMarkus Armbruster qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7686fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7687fcf5ef2aSThomas Huth break; 7688fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 768990c84c56SMarkus Armbruster qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7690fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7691fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7692fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7693fcf5ef2aSThomas Huth 769490c84c56SMarkus Armbruster qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7695fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7696fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7697fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7698fcf5ef2aSThomas Huth 769990c84c56SMarkus Armbruster qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7700fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7701fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7702fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7703fcf5ef2aSThomas Huth break; 7704fcf5ef2aSThomas Huth default: 7705fcf5ef2aSThomas Huth break; 7706fcf5ef2aSThomas Huth } 7707fcf5ef2aSThomas Huth #endif 7708fcf5ef2aSThomas Huth 7709fcf5ef2aSThomas Huth #undef RGPL 7710fcf5ef2aSThomas Huth #undef RFPL 7711fcf5ef2aSThomas Huth } 7712fcf5ef2aSThomas Huth 771311cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 7714fcf5ef2aSThomas Huth { 7715fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7716fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7717fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7718fcf5ef2aSThomas Huth int op1, op2, op3; 7719fcf5ef2aSThomas Huth 7720fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7721fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7722fcf5ef2aSThomas Huth handler = t1[op1]; 7723fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7724fcf5ef2aSThomas Huth t2 = ind_table(handler); 7725fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7726fcf5ef2aSThomas Huth handler = t2[op2]; 7727fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7728fcf5ef2aSThomas Huth t3 = ind_table(handler); 7729fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7730fcf5ef2aSThomas Huth handler = t3[op3]; 7731efe843d8SDavid Gibson if (handler->count == 0) { 7732fcf5ef2aSThomas Huth continue; 7733efe843d8SDavid Gibson } 773411cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 7735fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7736fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7737fcf5ef2aSThomas Huth handler->oname, 7738fcf5ef2aSThomas Huth handler->count, handler->count); 7739fcf5ef2aSThomas Huth } 7740fcf5ef2aSThomas Huth } else { 7741efe843d8SDavid Gibson if (handler->count == 0) { 7742fcf5ef2aSThomas Huth continue; 7743efe843d8SDavid Gibson } 774411cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 7745fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7746fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7747fcf5ef2aSThomas Huth handler->count, handler->count); 7748fcf5ef2aSThomas Huth } 7749fcf5ef2aSThomas Huth } 7750fcf5ef2aSThomas Huth } else { 7751efe843d8SDavid Gibson if (handler->count == 0) { 7752fcf5ef2aSThomas Huth continue; 7753efe843d8SDavid Gibson } 775411cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 7755fcf5ef2aSThomas Huth " %" PRId64 "\n", 7756fcf5ef2aSThomas Huth op1, op1, handler->oname, 7757fcf5ef2aSThomas Huth handler->count, handler->count); 7758fcf5ef2aSThomas Huth } 7759fcf5ef2aSThomas Huth } 7760fcf5ef2aSThomas Huth #endif 7761fcf5ef2aSThomas Huth } 7762fcf5ef2aSThomas Huth 7763b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7764fcf5ef2aSThomas Huth { 7765b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 77669c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 7767b0c2d521SEmilio G. Cota int bound; 7768fcf5ef2aSThomas Huth 7769b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 7770b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 7771b0c2d521SEmilio G. Cota ctx->pr = msr_pr; 7772b0c2d521SEmilio G. Cota ctx->mem_idx = env->dmmu_idx; 7773b0c2d521SEmilio G. Cota ctx->dr = msr_dr; 7774fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7775b0c2d521SEmilio G. Cota ctx->hv = msr_hv || !env->has_hv_mode; 7776fcf5ef2aSThomas Huth #endif 7777b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7778b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7779b0c2d521SEmilio G. Cota ctx->access_type = -1; 7780b0c2d521SEmilio G. Cota ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7781b0c2d521SEmilio G. Cota ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7782b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 77830e3bf489SRoman Kapl ctx->flags = env->flags; 7784fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7785b0c2d521SEmilio G. Cota ctx->sf_mode = msr_is_64bit(env, env->msr); 7786b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7787fcf5ef2aSThomas Huth #endif 7788e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7789e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 7790e69ba2b4SDavid Gibson || (env->mmu_model & POWERPC_MMU_64B); 7791fcf5ef2aSThomas Huth 7792b0c2d521SEmilio G. Cota ctx->fpu_enabled = !!msr_fp; 7793efe843d8SDavid Gibson if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { 7794b0c2d521SEmilio G. Cota ctx->spe_enabled = !!msr_spe; 7795efe843d8SDavid Gibson } else { 7796b0c2d521SEmilio G. Cota ctx->spe_enabled = false; 7797efe843d8SDavid Gibson } 7798efe843d8SDavid Gibson if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { 7799b0c2d521SEmilio G. Cota ctx->altivec_enabled = !!msr_vr; 7800efe843d8SDavid Gibson } else { 7801b0c2d521SEmilio G. Cota ctx->altivec_enabled = false; 7802efe843d8SDavid Gibson } 7803fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7804b0c2d521SEmilio G. Cota ctx->vsx_enabled = !!msr_vsx; 7805fcf5ef2aSThomas Huth } else { 7806b0c2d521SEmilio G. Cota ctx->vsx_enabled = false; 7807fcf5ef2aSThomas Huth } 7808fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7809fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7810b0c2d521SEmilio G. Cota ctx->tm_enabled = !!msr_tm; 7811fcf5ef2aSThomas Huth } else { 7812b0c2d521SEmilio G. Cota ctx->tm_enabled = false; 7813fcf5ef2aSThomas Huth } 7814fcf5ef2aSThomas Huth #endif 7815b0c2d521SEmilio G. Cota ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7816efe843d8SDavid Gibson if ((env->flags & POWERPC_FLAG_SE) && msr_se) { 7817b0c2d521SEmilio G. Cota ctx->singlestep_enabled = CPU_SINGLE_STEP; 7818efe843d8SDavid Gibson } else { 7819b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 7820efe843d8SDavid Gibson } 7821efe843d8SDavid Gibson if ((env->flags & POWERPC_FLAG_BE) && msr_be) { 7822b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7823efe843d8SDavid Gibson } 78240e3bf489SRoman Kapl if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 78250e3bf489SRoman Kapl ctx->singlestep_enabled = 0; 78260e3bf489SRoman Kapl target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 78270e3bf489SRoman Kapl if (dbcr0 & DBCR0_ICMP) { 78280e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_SINGLE_STEP; 78290e3bf489SRoman Kapl } 78300e3bf489SRoman Kapl if (dbcr0 & DBCR0_BRT) { 78310e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_BRANCH_STEP; 78320e3bf489SRoman Kapl } 78330e3bf489SRoman Kapl 78340e3bf489SRoman Kapl } 7835b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7836b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7837fcf5ef2aSThomas Huth } 7838fcf5ef2aSThomas Huth #if defined(DO_SINGLE_STEP) && 0 7839fcf5ef2aSThomas Huth /* Single step trace mode */ 7840fcf5ef2aSThomas Huth msr_se = 1; 7841fcf5ef2aSThomas Huth #endif 7842b0c2d521SEmilio G. Cota 7843b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7844b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7845fcf5ef2aSThomas Huth } 7846fcf5ef2aSThomas Huth 7847b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7848b0c2d521SEmilio G. Cota { 7849b0c2d521SEmilio G. Cota } 7850fcf5ef2aSThomas Huth 7851b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7852b0c2d521SEmilio G. Cota { 7853b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7854b0c2d521SEmilio G. Cota } 7855b0c2d521SEmilio G. Cota 7856b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7857b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 7858b0c2d521SEmilio G. Cota { 7859b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7860b0c2d521SEmilio G. Cota 7861b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 78622a8ceefcSEmilio G. Cota dcbase->is_jmp = DISAS_NORETURN; 7863efe843d8SDavid Gibson /* 7864efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 7865efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 7866efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 7867efe843d8SDavid Gibson * setting tb->size below does the right thing. 7868efe843d8SDavid Gibson */ 7869b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7870b0c2d521SEmilio G. Cota return true; 7871fcf5ef2aSThomas Huth } 7872fcf5ef2aSThomas Huth 7873b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7874b0c2d521SEmilio G. Cota { 7875b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 787628876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7877b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 7878b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 7879b0c2d521SEmilio G. Cota 7880fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7881fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7882b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7883b0c2d521SEmilio G. Cota 788423f42b60SEmilio G. Cota ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, 788523f42b60SEmilio G. Cota need_byteswap(ctx)); 788623f42b60SEmilio G. Cota 7887fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7888b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7889b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7890b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 7891b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 789228876bf2SAlex Bennée table = cpu->opcodes; 7893b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 7894fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7895fcf5ef2aSThomas Huth table = ind_table(handler); 7896b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 7897fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7898fcf5ef2aSThomas Huth table = ind_table(handler); 7899b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 7900fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7901fcf5ef2aSThomas Huth table = ind_table(handler); 7902b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 7903fcf5ef2aSThomas Huth } 7904fcf5ef2aSThomas Huth } 7905fcf5ef2aSThomas Huth } 7906fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7907fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7908fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7909fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7910fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7911b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7912b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7913b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7914fcf5ef2aSThomas Huth } else { 7915fcf5ef2aSThomas Huth uint32_t inval; 7916fcf5ef2aSThomas Huth 7917b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7918b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 7919fcf5ef2aSThomas Huth inval = handler->inval2; 7920fcf5ef2aSThomas Huth } else { 7921fcf5ef2aSThomas Huth inval = handler->inval1; 7922fcf5ef2aSThomas Huth } 7923fcf5ef2aSThomas Huth 7924b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 7925fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7926fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7927b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 7928b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7929b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7930b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4); 7931b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7932b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 7933b0c2d521SEmilio G. Cota return; 7934fcf5ef2aSThomas Huth } 7935fcf5ef2aSThomas Huth } 7936b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 7937fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7938fcf5ef2aSThomas Huth handler->count++; 7939fcf5ef2aSThomas Huth #endif 7940fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7941b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7942b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7943b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 7944b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 7945b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 7946e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 79470e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 7948fcf5ef2aSThomas Huth } 7949b0c2d521SEmilio G. Cota 7950fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7951b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7952b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7953b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7954fcf5ef2aSThomas Huth } 7955b0c2d521SEmilio G. Cota 7956b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7957b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 7958fcf5ef2aSThomas Huth } 7959b0c2d521SEmilio G. Cota 7960b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7961b0c2d521SEmilio G. Cota { 7962b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7963b0c2d521SEmilio G. Cota 7964b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 7965b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 7966b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7967b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7968b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 7969fcf5ef2aSThomas Huth } 7970fcf5ef2aSThomas Huth /* Generate the return instruction */ 797107ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7972fcf5ef2aSThomas Huth } 7973fcf5ef2aSThomas Huth } 7974b0c2d521SEmilio G. Cota 7975b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7976b0c2d521SEmilio G. Cota { 7977b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7978b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7979b0c2d521SEmilio G. Cota } 7980b0c2d521SEmilio G. Cota 7981b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7982b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7983b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7984b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7985b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 7986b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7987b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7988b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7989b0c2d521SEmilio G. Cota }; 7990b0c2d521SEmilio G. Cota 79918b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 7992b0c2d521SEmilio G. Cota { 7993b0c2d521SEmilio G. Cota DisasContext ctx; 7994b0c2d521SEmilio G. Cota 79958b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 7996fcf5ef2aSThomas Huth } 7997fcf5ef2aSThomas Huth 7998fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7999fcf5ef2aSThomas Huth target_ulong *data) 8000fcf5ef2aSThomas Huth { 8001fcf5ef2aSThomas Huth env->nip = data[0]; 8002fcf5ef2aSThomas Huth } 8003