1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39fcf5ef2aSThomas Huth 403e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 413e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 44fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 47efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 1572c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 158fcf5ef2aSThomas Huth uint32_t opcode; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 1771db3632aSMatheus Ferst bool hr; 178f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 179f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 180*8b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 181*8b3d1c49SLeandro Lupori bool pmc_other; 18246d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 183fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 184fcf5ef2aSThomas Huth int singlestep_enabled; 1850e3bf489SRoman Kapl uint32_t flags; 186fcf5ef2aSThomas Huth uint64_t insns_flags; 187fcf5ef2aSThomas Huth uint64_t insns_flags2; 188fcf5ef2aSThomas Huth }; 189fcf5ef2aSThomas Huth 190a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 191a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 192a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 193a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 194a9b5b3d0SRichard Henderson 195fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 196fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 197fcf5ef2aSThomas Huth { 198ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 199fcf5ef2aSThomas Huth return ctx->le_mode; 200fcf5ef2aSThomas Huth #else 201fcf5ef2aSThomas Huth return !ctx->le_mode; 202fcf5ef2aSThomas Huth #endif 203fcf5ef2aSThomas Huth } 204fcf5ef2aSThomas Huth 205fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 206fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 207fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 208fcf5ef2aSThomas Huth #else 209fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 210fcf5ef2aSThomas Huth #endif 211fcf5ef2aSThomas Huth 212fcf5ef2aSThomas Huth struct opc_handler_t { 213fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 214fcf5ef2aSThomas Huth uint32_t inval1; 215fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 216fcf5ef2aSThomas Huth uint32_t inval2; 217fcf5ef2aSThomas Huth /* instruction type */ 218fcf5ef2aSThomas Huth uint64_t type; 219fcf5ef2aSThomas Huth /* extended instruction type */ 220fcf5ef2aSThomas Huth uint64_t type2; 221fcf5ef2aSThomas Huth /* handler */ 222fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 223fcf5ef2aSThomas Huth }; 224fcf5ef2aSThomas Huth 2250e3bf489SRoman Kapl /* SPR load/store helpers */ 2260e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2270e3bf489SRoman Kapl { 2280e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2290e3bf489SRoman Kapl } 2300e3bf489SRoman Kapl 2310e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2320e3bf489SRoman Kapl { 2330e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2340e3bf489SRoman Kapl } 2350e3bf489SRoman Kapl 236fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 237fcf5ef2aSThomas Huth { 238fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 239fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 240fcf5ef2aSThomas Huth ctx->access_type = access_type; 241fcf5ef2aSThomas Huth } 242fcf5ef2aSThomas Huth } 243fcf5ef2aSThomas Huth 244fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 245fcf5ef2aSThomas Huth { 246fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 247fcf5ef2aSThomas Huth nip = (uint32_t)nip; 248fcf5ef2aSThomas Huth } 249fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 250fcf5ef2aSThomas Huth } 251fcf5ef2aSThomas Huth 252fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 253fcf5ef2aSThomas Huth { 254fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 255fcf5ef2aSThomas Huth 256efe843d8SDavid Gibson /* 257efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 258efe843d8SDavid Gibson * faulting instruction 259fcf5ef2aSThomas Huth */ 2602c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 261fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 262fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 263fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 264fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 265fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2663d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 267fcf5ef2aSThomas Huth } 268fcf5ef2aSThomas Huth 269fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 270fcf5ef2aSThomas Huth { 271fcf5ef2aSThomas Huth TCGv_i32 t0; 272fcf5ef2aSThomas Huth 273efe843d8SDavid Gibson /* 274efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 275efe843d8SDavid Gibson * faulting instruction 276fcf5ef2aSThomas Huth */ 2772c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 278fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 279fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 280fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2813d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 282fcf5ef2aSThomas Huth } 283fcf5ef2aSThomas Huth 284fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 285fcf5ef2aSThomas Huth target_ulong nip) 286fcf5ef2aSThomas Huth { 287fcf5ef2aSThomas Huth TCGv_i32 t0; 288fcf5ef2aSThomas Huth 289fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 290fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 291fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 292fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2933d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 294fcf5ef2aSThomas Huth } 295fcf5ef2aSThomas Huth 296f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 297f5b6daacSRichard Henderson { 298f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 299f5b6daacSRichard Henderson gen_io_start(); 300f5b6daacSRichard Henderson /* 301f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 302f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 303f5b6daacSRichard Henderson * decide if we need to return to the main loop. 304f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 305f5b6daacSRichard Henderson */ 306f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 307f5b6daacSRichard Henderson } 308f5b6daacSRichard Henderson } 309f5b6daacSRichard Henderson 3102fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3112fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3122fdedcbcSMatheus Ferst { 3132fdedcbcSMatheus Ferst gen_icount_io_start(ctx); 3142fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3152fdedcbcSMatheus Ferst } 3162fdedcbcSMatheus Ferst #endif 3172fdedcbcSMatheus Ferst 318e150ac89SRoman Kapl /* 319e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 320e150ac89SRoman Kapl * SPR registers for this exception. 321e150ac89SRoman Kapl * 322e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 323e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3240e3bf489SRoman Kapl */ 325e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3260e3bf489SRoman Kapl { 3270e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3280e3bf489SRoman Kapl target_ulong dbsr = 0; 329e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3300e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 331e150ac89SRoman Kapl } else { 332e150ac89SRoman Kapl /* Must have been branch */ 3330e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3340e3bf489SRoman Kapl } 3350e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3360e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3370e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3380e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3390e3bf489SRoman Kapl tcg_temp_free(t0); 3400e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3410e3bf489SRoman Kapl } else { 342e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3430e3bf489SRoman Kapl } 3440e3bf489SRoman Kapl } 3450e3bf489SRoman Kapl 346fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 347fcf5ef2aSThomas Huth { 3489498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3493d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 350fcf5ef2aSThomas Huth } 351fcf5ef2aSThomas Huth 352fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 353fcf5ef2aSThomas Huth { 354fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 355fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 358fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 359fcf5ef2aSThomas Huth { 360fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 361fcf5ef2aSThomas Huth } 362fcf5ef2aSThomas Huth 363fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 364fcf5ef2aSThomas Huth { 365fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 366fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 367fcf5ef2aSThomas Huth } 368fcf5ef2aSThomas Huth 36937f219c8SBruno Larsen (billionai) /*****************************************************************************/ 37037f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 37137f219c8SBruno Larsen (billionai) 372a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 37337f219c8SBruno Larsen (billionai) { 37437f219c8SBruno Larsen (billionai) #if 0 37537f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 37637f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 37737f219c8SBruno Larsen (billionai) #endif 37837f219c8SBruno Larsen (billionai) } 37937f219c8SBruno Larsen (billionai) 38037f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 38137f219c8SBruno Larsen (billionai) 38237f219c8SBruno Larsen (billionai) /* 38337f219c8SBruno Larsen (billionai) * Generic callbacks: 38437f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 38537f219c8SBruno Larsen (billionai) */ 38637f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 38737f219c8SBruno Larsen (billionai) { 38837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 38937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39037f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 39137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39237f219c8SBruno Larsen (billionai) #endif 39337f219c8SBruno Larsen (billionai) } 39437f219c8SBruno Larsen (billionai) 395a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 39637f219c8SBruno Larsen (billionai) { 39737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 39837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 39937f219c8SBruno Larsen (billionai) } 40037f219c8SBruno Larsen (billionai) 40137f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 40237f219c8SBruno Larsen (billionai) { 40337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 40437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 40537f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 40637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 40737f219c8SBruno Larsen (billionai) #endif 40837f219c8SBruno Larsen (billionai) } 40937f219c8SBruno Larsen (billionai) 410a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 41137f219c8SBruno Larsen (billionai) { 41237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 41337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41437f219c8SBruno Larsen (billionai) } 41537f219c8SBruno Larsen (billionai) 4167aeac354SDaniel Henrique Barboza void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 4177aeac354SDaniel Henrique Barboza { 4187aeac354SDaniel Henrique Barboza spr_write_generic(ctx, sprn, gprn); 4197aeac354SDaniel Henrique Barboza 4207aeac354SDaniel Henrique Barboza /* 4217aeac354SDaniel Henrique Barboza * SPR_CTRL writes must force a new translation block, 4227aeac354SDaniel Henrique Barboza * allowing the PMU to calculate the run latch events with 4237aeac354SDaniel Henrique Barboza * more accuracy. 4247aeac354SDaniel Henrique Barboza */ 4257aeac354SDaniel Henrique Barboza ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4267aeac354SDaniel Henrique Barboza } 4277aeac354SDaniel Henrique Barboza 42837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 429a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43037f219c8SBruno Larsen (billionai) { 43137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 43637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43737f219c8SBruno Larsen (billionai) #else 43837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43937f219c8SBruno Larsen (billionai) #endif 44037f219c8SBruno Larsen (billionai) } 44137f219c8SBruno Larsen (billionai) 442a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 44337f219c8SBruno Larsen (billionai) { 44437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44637f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 44737f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 44837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 44937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 45037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45137f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 45237f219c8SBruno Larsen (billionai) } 45337f219c8SBruno Larsen (billionai) 454a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 45537f219c8SBruno Larsen (billionai) { 45637f219c8SBruno Larsen (billionai) } 45737f219c8SBruno Larsen (billionai) 45837f219c8SBruno Larsen (billionai) #endif 45937f219c8SBruno Larsen (billionai) 46037f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 46137f219c8SBruno Larsen (billionai) /* XER */ 462a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 46337f219c8SBruno Larsen (billionai) { 46437f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 46537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 46637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 46737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 46837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 46937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 47037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 47137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 47237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 47337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 47437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47537f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 47637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 47737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 47937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 48037f219c8SBruno Larsen (billionai) } 48137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 48237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 48337f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 48437f219c8SBruno Larsen (billionai) } 48537f219c8SBruno Larsen (billionai) 486a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 48737f219c8SBruno Larsen (billionai) { 48837f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 48937f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 49037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 49137f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 49237f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 49337f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 49437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 49537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 49637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 49737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 49837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 49937f219c8SBruno Larsen (billionai) } 50037f219c8SBruno Larsen (billionai) 50137f219c8SBruno Larsen (billionai) /* LR */ 502a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 50337f219c8SBruno Larsen (billionai) { 50437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 50537f219c8SBruno Larsen (billionai) } 50637f219c8SBruno Larsen (billionai) 507a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 50837f219c8SBruno Larsen (billionai) { 50937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 51037f219c8SBruno Larsen (billionai) } 51137f219c8SBruno Larsen (billionai) 51237f219c8SBruno Larsen (billionai) /* CFAR */ 51337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 514a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 51537f219c8SBruno Larsen (billionai) { 51637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 51737f219c8SBruno Larsen (billionai) } 51837f219c8SBruno Larsen (billionai) 519a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 52037f219c8SBruno Larsen (billionai) { 52137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 52237f219c8SBruno Larsen (billionai) } 52337f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 52437f219c8SBruno Larsen (billionai) 52537f219c8SBruno Larsen (billionai) /* CTR */ 526a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 52737f219c8SBruno Larsen (billionai) { 52837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 52937f219c8SBruno Larsen (billionai) } 53037f219c8SBruno Larsen (billionai) 531a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 53237f219c8SBruno Larsen (billionai) { 53337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 53437f219c8SBruno Larsen (billionai) } 53537f219c8SBruno Larsen (billionai) 53637f219c8SBruno Larsen (billionai) /* User read access to SPR */ 53737f219c8SBruno Larsen (billionai) /* USPRx */ 53837f219c8SBruno Larsen (billionai) /* UMMCRx */ 53937f219c8SBruno Larsen (billionai) /* UPMCx */ 54037f219c8SBruno Larsen (billionai) /* USIA */ 54137f219c8SBruno Larsen (billionai) /* UDECR */ 542a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 54337f219c8SBruno Larsen (billionai) { 54437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 54537f219c8SBruno Larsen (billionai) } 54637f219c8SBruno Larsen (billionai) 54737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 548a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 54937f219c8SBruno Larsen (billionai) { 55037f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 55137f219c8SBruno Larsen (billionai) } 55237f219c8SBruno Larsen (billionai) #endif 55337f219c8SBruno Larsen (billionai) 55437f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 55537f219c8SBruno Larsen (billionai) /* DECR */ 55637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 557a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 55837f219c8SBruno Larsen (billionai) { 559f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56037f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 56137f219c8SBruno Larsen (billionai) } 56237f219c8SBruno Larsen (billionai) 563a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 56437f219c8SBruno Larsen (billionai) { 565f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56637f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 56737f219c8SBruno Larsen (billionai) } 56837f219c8SBruno Larsen (billionai) #endif 56937f219c8SBruno Larsen (billionai) 57037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 57137f219c8SBruno Larsen (billionai) /* Time base */ 572a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 57337f219c8SBruno Larsen (billionai) { 574f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57537f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 57637f219c8SBruno Larsen (billionai) } 57737f219c8SBruno Larsen (billionai) 578a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 57937f219c8SBruno Larsen (billionai) { 580f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58137f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 58237f219c8SBruno Larsen (billionai) } 58337f219c8SBruno Larsen (billionai) 584a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 58537f219c8SBruno Larsen (billionai) { 58637f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 58737f219c8SBruno Larsen (billionai) } 58837f219c8SBruno Larsen (billionai) 589a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 59037f219c8SBruno Larsen (billionai) { 59137f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 59237f219c8SBruno Larsen (billionai) } 59337f219c8SBruno Larsen (billionai) 59437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 595a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 59637f219c8SBruno Larsen (billionai) { 597f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59837f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 59937f219c8SBruno Larsen (billionai) } 60037f219c8SBruno Larsen (billionai) 601a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 60237f219c8SBruno Larsen (billionai) { 603f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60437f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 60537f219c8SBruno Larsen (billionai) } 60637f219c8SBruno Larsen (billionai) 607a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 60837f219c8SBruno Larsen (billionai) { 60937f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 61037f219c8SBruno Larsen (billionai) } 61137f219c8SBruno Larsen (billionai) 612a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 61337f219c8SBruno Larsen (billionai) { 61437f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 61537f219c8SBruno Larsen (billionai) } 61637f219c8SBruno Larsen (billionai) 61737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 618a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 61937f219c8SBruno Larsen (billionai) { 620f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62137f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 62237f219c8SBruno Larsen (billionai) } 62337f219c8SBruno Larsen (billionai) 624a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 62537f219c8SBruno Larsen (billionai) { 626f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62737f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 62837f219c8SBruno Larsen (billionai) } 62937f219c8SBruno Larsen (billionai) 63037f219c8SBruno Larsen (billionai) /* HDECR */ 631a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 63237f219c8SBruno Larsen (billionai) { 633f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63437f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 63537f219c8SBruno Larsen (billionai) } 63637f219c8SBruno Larsen (billionai) 637a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 63837f219c8SBruno Larsen (billionai) { 639f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64037f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 64137f219c8SBruno Larsen (billionai) } 64237f219c8SBruno Larsen (billionai) 643a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 64437f219c8SBruno Larsen (billionai) { 645f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64637f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 64737f219c8SBruno Larsen (billionai) } 64837f219c8SBruno Larsen (billionai) 649a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 65037f219c8SBruno Larsen (billionai) { 651f5b6daacSRichard Henderson gen_icount_io_start(ctx); 65237f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 65337f219c8SBruno Larsen (billionai) } 65437f219c8SBruno Larsen (billionai) 655a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 65637f219c8SBruno Larsen (billionai) { 657f5b6daacSRichard Henderson gen_icount_io_start(ctx); 65837f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 65937f219c8SBruno Larsen (billionai) } 66037f219c8SBruno Larsen (billionai) 66137f219c8SBruno Larsen (billionai) #endif 66237f219c8SBruno Larsen (billionai) #endif 66337f219c8SBruno Larsen (billionai) 66437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 66537f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 66637f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 667a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 66837f219c8SBruno Larsen (billionai) { 66937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 67037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 67137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 67237f219c8SBruno Larsen (billionai) } 67337f219c8SBruno Larsen (billionai) 674a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 67537f219c8SBruno Larsen (billionai) { 67637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 67737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 67837f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 67937f219c8SBruno Larsen (billionai) } 68037f219c8SBruno Larsen (billionai) 681a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 68237f219c8SBruno Larsen (billionai) { 68337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 68437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 68537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68637f219c8SBruno Larsen (billionai) } 68737f219c8SBruno Larsen (billionai) 688a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 68937f219c8SBruno Larsen (billionai) { 69037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 69137f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 69237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69337f219c8SBruno Larsen (billionai) } 69437f219c8SBruno Larsen (billionai) 695a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 69637f219c8SBruno Larsen (billionai) { 69737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 69837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 69937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70037f219c8SBruno Larsen (billionai) } 70137f219c8SBruno Larsen (billionai) 702a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 70337f219c8SBruno Larsen (billionai) { 70437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 70537f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 70637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70737f219c8SBruno Larsen (billionai) } 70837f219c8SBruno Larsen (billionai) 70937f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 71037f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 711a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 71237f219c8SBruno Larsen (billionai) { 71337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 71437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 71537f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 71637f219c8SBruno Larsen (billionai) } 71737f219c8SBruno Larsen (billionai) 718a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 71937f219c8SBruno Larsen (billionai) { 72037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 72137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 72237f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 72337f219c8SBruno Larsen (billionai) } 72437f219c8SBruno Larsen (billionai) 725a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 72637f219c8SBruno Larsen (billionai) { 72737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 72837f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 72937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73037f219c8SBruno Larsen (billionai) } 73137f219c8SBruno Larsen (billionai) 732a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 73337f219c8SBruno Larsen (billionai) { 73437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 73537f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 73637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73737f219c8SBruno Larsen (billionai) } 73837f219c8SBruno Larsen (billionai) 739a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 74037f219c8SBruno Larsen (billionai) { 74137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 74237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 74337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74437f219c8SBruno Larsen (billionai) } 74537f219c8SBruno Larsen (billionai) 746a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 74737f219c8SBruno Larsen (billionai) { 74837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 74937f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 75037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75137f219c8SBruno Larsen (billionai) } 75237f219c8SBruno Larsen (billionai) 75337f219c8SBruno Larsen (billionai) /* SDR1 */ 754a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 75537f219c8SBruno Larsen (billionai) { 75637f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 75737f219c8SBruno Larsen (billionai) } 75837f219c8SBruno Larsen (billionai) 75937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 76037f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 76137f219c8SBruno Larsen (billionai) /* PIDR */ 762a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 76337f219c8SBruno Larsen (billionai) { 76437f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 76537f219c8SBruno Larsen (billionai) } 76637f219c8SBruno Larsen (billionai) 767a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 76837f219c8SBruno Larsen (billionai) { 76937f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 772a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 77337f219c8SBruno Larsen (billionai) { 77437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 77537f219c8SBruno Larsen (billionai) } 77637f219c8SBruno Larsen (billionai) 777a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 77837f219c8SBruno Larsen (billionai) { 77937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 78037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 78137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 78237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 78337f219c8SBruno Larsen (billionai) } 784a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 78537f219c8SBruno Larsen (billionai) { 78637f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 78737f219c8SBruno Larsen (billionai) } 78837f219c8SBruno Larsen (billionai) 789a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 79037f219c8SBruno Larsen (billionai) { 79137f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 79237f219c8SBruno Larsen (billionai) } 79337f219c8SBruno Larsen (billionai) 79437f219c8SBruno Larsen (billionai) /* DPDES */ 795a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 79637f219c8SBruno Larsen (billionai) { 79737f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 79837f219c8SBruno Larsen (billionai) } 79937f219c8SBruno Larsen (billionai) 800a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 80137f219c8SBruno Larsen (billionai) { 80237f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 80337f219c8SBruno Larsen (billionai) } 80437f219c8SBruno Larsen (billionai) #endif 80537f219c8SBruno Larsen (billionai) #endif 80637f219c8SBruno Larsen (billionai) 80737f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 80837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 809a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 81037f219c8SBruno Larsen (billionai) { 811f5b6daacSRichard Henderson gen_icount_io_start(ctx); 81237f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 81337f219c8SBruno Larsen (billionai) } 81437f219c8SBruno Larsen (billionai) 815a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 81637f219c8SBruno Larsen (billionai) { 817f5b6daacSRichard Henderson gen_icount_io_start(ctx); 81837f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 81937f219c8SBruno Larsen (billionai) } 82037f219c8SBruno Larsen (billionai) 821a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 82237f219c8SBruno Larsen (billionai) { 823f5b6daacSRichard Henderson gen_icount_io_start(ctx); 82437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 82537f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 82637f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 827d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 82837f219c8SBruno Larsen (billionai) } 82937f219c8SBruno Larsen (billionai) 830a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 83137f219c8SBruno Larsen (billionai) { 832f5b6daacSRichard Henderson gen_icount_io_start(ctx); 83337f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 83437f219c8SBruno Larsen (billionai) } 83537f219c8SBruno Larsen (billionai) 836cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 837cbd8f17dSCédric Le Goater { 838cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 839cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 840cbd8f17dSCédric Le Goater } 841cbd8f17dSCédric Le Goater 842cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 843cbd8f17dSCédric Le Goater { 844cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 845cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 846cbd8f17dSCédric Le Goater } 847cbd8f17dSCédric Le Goater 848dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 849dd69d140SCédric Le Goater { 850dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 851dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 85247822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 853dd69d140SCédric Le Goater tcg_temp_free(t0); 854dd69d140SCédric Le Goater } 855dd69d140SCédric Le Goater 856a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 85737f219c8SBruno Larsen (billionai) { 858f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85937f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 86037f219c8SBruno Larsen (billionai) } 86137f219c8SBruno Larsen (billionai) 862a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 86337f219c8SBruno Larsen (billionai) { 864f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86537f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 86637f219c8SBruno Larsen (billionai) } 86737f219c8SBruno Larsen (billionai) #endif 86837f219c8SBruno Larsen (billionai) 869328c95fcSCédric Le Goater /* PIR */ 87037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 871a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 87237f219c8SBruno Larsen (billionai) { 87337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 87437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 87537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 87637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 87737f219c8SBruno Larsen (billionai) } 87837f219c8SBruno Larsen (billionai) #endif 87937f219c8SBruno Larsen (billionai) 88037f219c8SBruno Larsen (billionai) /* SPE specific registers */ 881a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 88237f219c8SBruno Larsen (billionai) { 88337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 88437f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 88537f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 88637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 88737f219c8SBruno Larsen (billionai) } 88837f219c8SBruno Larsen (billionai) 889a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 89037f219c8SBruno Larsen (billionai) { 89137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 89237f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 89337f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 89437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89537f219c8SBruno Larsen (billionai) } 89637f219c8SBruno Larsen (billionai) 89737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 89837f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 899a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 90037f219c8SBruno Larsen (billionai) { 90137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 90337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 90437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 90537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 90637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90737f219c8SBruno Larsen (billionai) } 90837f219c8SBruno Larsen (billionai) 909a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 91037f219c8SBruno Larsen (billionai) { 91137f219c8SBruno Larsen (billionai) int sprn_offs; 91237f219c8SBruno Larsen (billionai) 91337f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 91437f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 91537f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 91637f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 91737f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 91837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 91937f219c8SBruno Larsen (billionai) } else { 9208e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9218e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9228e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 92337f219c8SBruno Larsen (billionai) return; 92437f219c8SBruno Larsen (billionai) } 92537f219c8SBruno Larsen (billionai) 92637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 92837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 92937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 93037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93237f219c8SBruno Larsen (billionai) } 93337f219c8SBruno Larsen (billionai) #endif 93437f219c8SBruno Larsen (billionai) 93537f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 93637f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 937a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 93837f219c8SBruno Larsen (billionai) { 93937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 94037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 94137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 94237f219c8SBruno Larsen (billionai) 94337f219c8SBruno Larsen (billionai) /* 94437f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 94537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 94637f219c8SBruno Larsen (billionai) */ 94737f219c8SBruno Larsen (billionai) 94837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 94937f219c8SBruno Larsen (billionai) if (ctx->pr) { 95037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 95137f219c8SBruno Larsen (billionai) } else { 95237f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 95337f219c8SBruno Larsen (billionai) } 95437f219c8SBruno Larsen (billionai) 95537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 95637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 95737f219c8SBruno Larsen (billionai) 95837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 95937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 96037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 96137f219c8SBruno Larsen (billionai) 96237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 96337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 96437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 96537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 96637f219c8SBruno Larsen (billionai) 96737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 96837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 96937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 97037f219c8SBruno Larsen (billionai) } 97137f219c8SBruno Larsen (billionai) 972a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 97337f219c8SBruno Larsen (billionai) { 97437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 97637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 97737f219c8SBruno Larsen (billionai) 97837f219c8SBruno Larsen (billionai) /* 97937f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 98037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 98137f219c8SBruno Larsen (billionai) */ 98237f219c8SBruno Larsen (billionai) 98337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 98437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 98537f219c8SBruno Larsen (billionai) 98637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98837f219c8SBruno Larsen (billionai) 98937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 99037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 99137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 99237f219c8SBruno Larsen (billionai) 99337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 99437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 99537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 99637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 99737f219c8SBruno Larsen (billionai) 99837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 99937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 100037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 100137f219c8SBruno Larsen (billionai) } 100237f219c8SBruno Larsen (billionai) 1003a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 100437f219c8SBruno Larsen (billionai) { 100537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100837f219c8SBruno Larsen (billionai) 100937f219c8SBruno Larsen (billionai) /* 101037f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 101137f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 101237f219c8SBruno Larsen (billionai) */ 101337f219c8SBruno Larsen (billionai) 101437f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 101537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101637f219c8SBruno Larsen (billionai) 101737f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101937f219c8SBruno Larsen (billionai) 102037f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 102137f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 102237f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 102337f219c8SBruno Larsen (billionai) 102437f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 102537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 102737f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 102837f219c8SBruno Larsen (billionai) 102937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 103037f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 103137f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 103237f219c8SBruno Larsen (billionai) } 103337f219c8SBruno Larsen (billionai) #endif 103437f219c8SBruno Larsen (billionai) #endif 103537f219c8SBruno Larsen (billionai) 103637f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1037a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 103837f219c8SBruno Larsen (billionai) { 103937f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 104037f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 104137f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 104237f219c8SBruno Larsen (billionai) } 104337f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 104437f219c8SBruno Larsen (billionai) 104537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1046a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 104737f219c8SBruno Larsen (billionai) { 104837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 104937f219c8SBruno Larsen (billionai) 105037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 105137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 105237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105337f219c8SBruno Larsen (billionai) } 105437f219c8SBruno Larsen (billionai) 1055a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 105637f219c8SBruno Larsen (billionai) { 105737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 105837f219c8SBruno Larsen (billionai) 105937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 106037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 106137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 106237f219c8SBruno Larsen (billionai) } 106337f219c8SBruno Larsen (billionai) 1064a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 106537f219c8SBruno Larsen (billionai) { 106637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106737f219c8SBruno Larsen (billionai) 106837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 106937f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 107037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107237f219c8SBruno Larsen (billionai) } 107337f219c8SBruno Larsen (billionai) 1074a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 107537f219c8SBruno Larsen (billionai) { 107637f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 107737f219c8SBruno Larsen (billionai) } 107837f219c8SBruno Larsen (billionai) 1079a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 108037f219c8SBruno Larsen (billionai) { 108137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 108237f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 108337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 108437f219c8SBruno Larsen (billionai) } 1085a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 108637f219c8SBruno Larsen (billionai) { 108737f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 108837f219c8SBruno Larsen (billionai) } 1089a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 109037f219c8SBruno Larsen (billionai) { 109137f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 109237f219c8SBruno Larsen (billionai) } 109337f219c8SBruno Larsen (billionai) 109437f219c8SBruno Larsen (billionai) #endif 109537f219c8SBruno Larsen (billionai) 109637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1097a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 109837f219c8SBruno Larsen (billionai) { 109937f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 110037f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 110137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 110237f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 110337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 110437f219c8SBruno Larsen (billionai) tcg_temp_free(val); 110537f219c8SBruno Larsen (billionai) } 110637f219c8SBruno Larsen (billionai) 1107a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 110837f219c8SBruno Larsen (billionai) { 110937f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 111037f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 111137f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 111237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 111337f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 111437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 111537f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 111637f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 111737f219c8SBruno Larsen (billionai) } 111837f219c8SBruno Larsen (billionai) 111937f219c8SBruno Larsen (billionai) #endif 112037f219c8SBruno Larsen (billionai) 112137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 112237f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 112337f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 112437f219c8SBruno Larsen (billionai) { 112537f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 112637f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 112737f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 112837f219c8SBruno Larsen (billionai) 112937f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 113037f219c8SBruno Larsen (billionai) 113137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 113237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 113337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 113437f219c8SBruno Larsen (billionai) } 113537f219c8SBruno Larsen (billionai) 113637f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 113737f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 113837f219c8SBruno Larsen (billionai) { 113937f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 114037f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 114137f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 114237f219c8SBruno Larsen (billionai) 114337f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 114437f219c8SBruno Larsen (billionai) 114537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 114637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 114737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 114837f219c8SBruno Larsen (billionai) } 114937f219c8SBruno Larsen (billionai) 1150a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 115137f219c8SBruno Larsen (billionai) { 115237f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 115337f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 115437f219c8SBruno Larsen (billionai) 115537f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 115637f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 115737f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 115837f219c8SBruno Larsen (billionai) 115937f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 116037f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 116137f219c8SBruno Larsen (billionai) } 116237f219c8SBruno Larsen (billionai) 1163a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 116437f219c8SBruno Larsen (billionai) { 116537f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 116637f219c8SBruno Larsen (billionai) 116737f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 116837f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 116937f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 117037f219c8SBruno Larsen (billionai) 117137f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 117237f219c8SBruno Larsen (billionai) } 117337f219c8SBruno Larsen (billionai) 117437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1175a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 117637f219c8SBruno Larsen (billionai) { 117737f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 117837f219c8SBruno Larsen (billionai) 117937f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 118037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 118137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 118237f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 118337f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 118437f219c8SBruno Larsen (billionai) } 118537f219c8SBruno Larsen (billionai) 1186a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 118737f219c8SBruno Larsen (billionai) { 118837f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 118937f219c8SBruno Larsen (billionai) } 119037f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 119137f219c8SBruno Larsen (billionai) 1192a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 119337f219c8SBruno Larsen (billionai) { 119437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 119537f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 119637f219c8SBruno Larsen (billionai) } 119737f219c8SBruno Larsen (billionai) 1198a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 119937f219c8SBruno Larsen (billionai) { 120037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 120137f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 120237f219c8SBruno Larsen (billionai) } 120337f219c8SBruno Larsen (billionai) 1204a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 120537f219c8SBruno Larsen (billionai) { 120637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 120737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 120837f219c8SBruno Larsen (billionai) } 120937f219c8SBruno Larsen (billionai) 1210a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 121137f219c8SBruno Larsen (billionai) { 121237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 121437f219c8SBruno Larsen (billionai) } 121537f219c8SBruno Larsen (billionai) 1216a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 121737f219c8SBruno Larsen (billionai) { 121837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121937f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 122037f219c8SBruno Larsen (billionai) } 122137f219c8SBruno Larsen (billionai) 1222a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 122337f219c8SBruno Larsen (billionai) { 122437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122537f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 122637f219c8SBruno Larsen (billionai) } 122737f219c8SBruno Larsen (billionai) 1228a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 122937f219c8SBruno Larsen (billionai) { 123037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123137f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123237f219c8SBruno Larsen (billionai) } 123337f219c8SBruno Larsen (billionai) 1234a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 123537f219c8SBruno Larsen (billionai) { 123637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123837f219c8SBruno Larsen (billionai) } 123937f219c8SBruno Larsen (billionai) 1240a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 124137f219c8SBruno Larsen (billionai) { 124237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124337f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124437f219c8SBruno Larsen (billionai) } 124537f219c8SBruno Larsen (billionai) 1246a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 124737f219c8SBruno Larsen (billionai) { 124837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124937f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125037f219c8SBruno Larsen (billionai) } 125137f219c8SBruno Larsen (billionai) #endif 125237f219c8SBruno Larsen (billionai) 1253fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1254fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1255fcf5ef2aSThomas Huth 1256fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1257fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1258fcf5ef2aSThomas Huth 1259fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1260fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1261fcf5ef2aSThomas Huth 1262fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1263fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1264fcf5ef2aSThomas Huth 1265fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1266fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1267fcf5ef2aSThomas Huth 1268fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1269fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1270fcf5ef2aSThomas Huth 1271fcf5ef2aSThomas Huth typedef struct opcode_t { 1272fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1273fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1274fcf5ef2aSThomas Huth unsigned char pad[4]; 1275fcf5ef2aSThomas Huth #endif 1276fcf5ef2aSThomas Huth opc_handler_t handler; 1277fcf5ef2aSThomas Huth const char *oname; 1278fcf5ef2aSThomas Huth } opcode_t; 1279fcf5ef2aSThomas Huth 12809f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 12819f0cf041SMatheus Ferst { 12829f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 12839f0cf041SMatheus Ferst } 12849f0cf041SMatheus Ferst 1285fcf5ef2aSThomas Huth /* Helpers for priv. check */ 12869f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1287fcf5ef2aSThomas Huth do { \ 12889f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1289fcf5ef2aSThomas Huth } while (0) 1290fcf5ef2aSThomas Huth 1291fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 12929f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 12939f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 12949f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1295fcf5ef2aSThomas Huth #else 12969f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1297fcf5ef2aSThomas Huth do { \ 1298fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 12999f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1300fcf5ef2aSThomas Huth } \ 1301fcf5ef2aSThomas Huth } while (0) 13029f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1303fcf5ef2aSThomas Huth do { \ 1304fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13059f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1306fcf5ef2aSThomas Huth } \ 1307fcf5ef2aSThomas Huth } while (0) 13089f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1309fcf5ef2aSThomas Huth do { \ 1310fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13119f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1312fcf5ef2aSThomas Huth } \ 1313fcf5ef2aSThomas Huth } while (0) 1314fcf5ef2aSThomas Huth #endif 1315fcf5ef2aSThomas Huth 13169f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1317fcf5ef2aSThomas Huth 1318fcf5ef2aSThomas Huth /*****************************************************************************/ 1319fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1320fcf5ef2aSThomas Huth 1321fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1322fcf5ef2aSThomas Huth { \ 1323fcf5ef2aSThomas Huth .opc1 = op1, \ 1324fcf5ef2aSThomas Huth .opc2 = op2, \ 1325fcf5ef2aSThomas Huth .opc3 = op3, \ 1326fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1327fcf5ef2aSThomas Huth .handler = { \ 1328fcf5ef2aSThomas Huth .inval1 = invl, \ 1329fcf5ef2aSThomas Huth .type = _typ, \ 1330fcf5ef2aSThomas Huth .type2 = _typ2, \ 1331fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1332fcf5ef2aSThomas Huth }, \ 1333fcf5ef2aSThomas Huth .oname = stringify(name), \ 1334fcf5ef2aSThomas Huth } 1335fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1336fcf5ef2aSThomas Huth { \ 1337fcf5ef2aSThomas Huth .opc1 = op1, \ 1338fcf5ef2aSThomas Huth .opc2 = op2, \ 1339fcf5ef2aSThomas Huth .opc3 = op3, \ 1340fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1341fcf5ef2aSThomas Huth .handler = { \ 1342fcf5ef2aSThomas Huth .inval1 = invl1, \ 1343fcf5ef2aSThomas Huth .inval2 = invl2, \ 1344fcf5ef2aSThomas Huth .type = _typ, \ 1345fcf5ef2aSThomas Huth .type2 = _typ2, \ 1346fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1347fcf5ef2aSThomas Huth }, \ 1348fcf5ef2aSThomas Huth .oname = stringify(name), \ 1349fcf5ef2aSThomas Huth } 1350fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1351fcf5ef2aSThomas Huth { \ 1352fcf5ef2aSThomas Huth .opc1 = op1, \ 1353fcf5ef2aSThomas Huth .opc2 = op2, \ 1354fcf5ef2aSThomas Huth .opc3 = op3, \ 1355fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1356fcf5ef2aSThomas Huth .handler = { \ 1357fcf5ef2aSThomas Huth .inval1 = invl, \ 1358fcf5ef2aSThomas Huth .type = _typ, \ 1359fcf5ef2aSThomas Huth .type2 = _typ2, \ 1360fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1361fcf5ef2aSThomas Huth }, \ 1362fcf5ef2aSThomas Huth .oname = onam, \ 1363fcf5ef2aSThomas Huth } 1364fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1365fcf5ef2aSThomas Huth { \ 1366fcf5ef2aSThomas Huth .opc1 = op1, \ 1367fcf5ef2aSThomas Huth .opc2 = op2, \ 1368fcf5ef2aSThomas Huth .opc3 = op3, \ 1369fcf5ef2aSThomas Huth .opc4 = op4, \ 1370fcf5ef2aSThomas Huth .handler = { \ 1371fcf5ef2aSThomas Huth .inval1 = invl, \ 1372fcf5ef2aSThomas Huth .type = _typ, \ 1373fcf5ef2aSThomas Huth .type2 = _typ2, \ 1374fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1375fcf5ef2aSThomas Huth }, \ 1376fcf5ef2aSThomas Huth .oname = stringify(name), \ 1377fcf5ef2aSThomas Huth } 1378fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1379fcf5ef2aSThomas Huth { \ 1380fcf5ef2aSThomas Huth .opc1 = op1, \ 1381fcf5ef2aSThomas Huth .opc2 = op2, \ 1382fcf5ef2aSThomas Huth .opc3 = op3, \ 1383fcf5ef2aSThomas Huth .opc4 = op4, \ 1384fcf5ef2aSThomas Huth .handler = { \ 1385fcf5ef2aSThomas Huth .inval1 = invl, \ 1386fcf5ef2aSThomas Huth .type = _typ, \ 1387fcf5ef2aSThomas Huth .type2 = _typ2, \ 1388fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1389fcf5ef2aSThomas Huth }, \ 1390fcf5ef2aSThomas Huth .oname = onam, \ 1391fcf5ef2aSThomas Huth } 1392fcf5ef2aSThomas Huth 1393fcf5ef2aSThomas Huth /* Invalid instruction */ 1394fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1395fcf5ef2aSThomas Huth { 1396fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1397fcf5ef2aSThomas Huth } 1398fcf5ef2aSThomas Huth 1399fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1400fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1401fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1402fcf5ef2aSThomas Huth .type = PPC_NONE, 1403fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1404fcf5ef2aSThomas Huth .handler = gen_invalid, 1405fcf5ef2aSThomas Huth }; 1406fcf5ef2aSThomas Huth 1407fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1408fcf5ef2aSThomas Huth 1409fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1410fcf5ef2aSThomas Huth { 1411fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1412b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1413b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1414fcf5ef2aSThomas Huth 1415b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1416b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1417efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1418efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1419b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1420efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1421efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1422b62b3686Spbonzini@redhat.com 1423b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1424fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1425b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1426fcf5ef2aSThomas Huth 1427fcf5ef2aSThomas Huth tcg_temp_free(t0); 1428b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1429b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1430fcf5ef2aSThomas Huth } 1431fcf5ef2aSThomas Huth 1432fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1433fcf5ef2aSThomas Huth { 1434fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1435fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1436fcf5ef2aSThomas Huth tcg_temp_free(t0); 1437fcf5ef2aSThomas Huth } 1438fcf5ef2aSThomas Huth 1439fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1440fcf5ef2aSThomas Huth { 1441fcf5ef2aSThomas Huth TCGv t0, t1; 1442fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1443fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1444fcf5ef2aSThomas Huth if (s) { 1445fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1446fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1447fcf5ef2aSThomas Huth } else { 1448fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1449fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1450fcf5ef2aSThomas Huth } 1451fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1452fcf5ef2aSThomas Huth tcg_temp_free(t1); 1453fcf5ef2aSThomas Huth tcg_temp_free(t0); 1454fcf5ef2aSThomas Huth } 1455fcf5ef2aSThomas Huth 1456fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1457fcf5ef2aSThomas Huth { 1458fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1459fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1460fcf5ef2aSThomas Huth tcg_temp_free(t0); 1461fcf5ef2aSThomas Huth } 1462fcf5ef2aSThomas Huth 1463fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1464fcf5ef2aSThomas Huth { 1465fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1466fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1467fcf5ef2aSThomas Huth } else { 1468fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1469fcf5ef2aSThomas Huth } 1470fcf5ef2aSThomas Huth } 1471fcf5ef2aSThomas Huth 1472fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1473fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1474fcf5ef2aSThomas Huth { 1475fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1476fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1477fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1478fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1479fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1480fcf5ef2aSThomas Huth 1481fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1482fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1483fcf5ef2aSThomas Huth 1484fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1485fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1486fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1487fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1488fcf5ef2aSThomas Huth 1489fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1490fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1491fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1492fcf5ef2aSThomas Huth 1493fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1494fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1495fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1496fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1497fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1498fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1499fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1500fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1501fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1502fcf5ef2aSThomas Huth } 1503efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1504fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1505fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1506fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1507fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1508fcf5ef2aSThomas Huth } 1509fcf5ef2aSThomas Huth 1510fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1511fcf5ef2aSThomas Huth /* cmpeqb */ 1512fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1513fcf5ef2aSThomas Huth { 1514fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1515fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1516fcf5ef2aSThomas Huth } 1517fcf5ef2aSThomas Huth #endif 1518fcf5ef2aSThomas Huth 1519fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1520fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1521fcf5ef2aSThomas Huth { 1522fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1523fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1524fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1525fcf5ef2aSThomas Huth TCGv zr; 1526fcf5ef2aSThomas Huth 1527fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1528fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1529fcf5ef2aSThomas Huth 1530fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1531fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1532fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1533fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1534fcf5ef2aSThomas Huth tcg_temp_free(zr); 1535fcf5ef2aSThomas Huth tcg_temp_free(t0); 1536fcf5ef2aSThomas Huth } 1537fcf5ef2aSThomas Huth 1538fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1539fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1540fcf5ef2aSThomas Huth { 1541fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1542fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1543fcf5ef2aSThomas Huth } 1544fcf5ef2aSThomas Huth 1545fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1546fcf5ef2aSThomas Huth 1547fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1548fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1549fcf5ef2aSThomas Huth { 1550fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1551fcf5ef2aSThomas Huth 1552fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1553fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1554fcf5ef2aSThomas Huth if (sub) { 1555fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1556fcf5ef2aSThomas Huth } else { 1557fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1558fcf5ef2aSThomas Huth } 1559fcf5ef2aSThomas Huth tcg_temp_free(t0); 1560fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1561dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1562dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1563dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1564fcf5ef2aSThomas Huth } 1565dc0ad844SNikunj A Dadhania } else { 1566dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1567dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1568dc0ad844SNikunj A Dadhania } 156938a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1570dc0ad844SNikunj A Dadhania } 1571fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1572fcf5ef2aSThomas Huth } 1573fcf5ef2aSThomas Huth 15746b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15756b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15764c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15776b10d008SNikunj A Dadhania { 15786b10d008SNikunj A Dadhania TCGv t0; 15796b10d008SNikunj A Dadhania 15806b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 15816b10d008SNikunj A Dadhania return; 15826b10d008SNikunj A Dadhania } 15836b10d008SNikunj A Dadhania 15846b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 158533903d0aSNikunj A Dadhania if (sub) { 158633903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 158733903d0aSNikunj A Dadhania } else { 15886b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 158933903d0aSNikunj A Dadhania } 15906b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 15914c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 15926b10d008SNikunj A Dadhania tcg_temp_free(t0); 15936b10d008SNikunj A Dadhania } 15946b10d008SNikunj A Dadhania 1595fcf5ef2aSThomas Huth /* Common add function */ 1596fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 15974c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 15984c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1599fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1600fcf5ef2aSThomas Huth { 1601fcf5ef2aSThomas Huth TCGv t0 = ret; 1602fcf5ef2aSThomas Huth 1603fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1604fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1605fcf5ef2aSThomas Huth } 1606fcf5ef2aSThomas Huth 1607fcf5ef2aSThomas Huth if (compute_ca) { 1608fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1609efe843d8SDavid Gibson /* 1610efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1611efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1612efe843d8SDavid Gibson * produce the carry into bit 32. 1613efe843d8SDavid Gibson */ 1614fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1615fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1616fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1617fcf5ef2aSThomas Huth if (add_ca) { 16184c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1619fcf5ef2aSThomas Huth } 16204c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1621fcf5ef2aSThomas Huth tcg_temp_free(t1); 16224c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16236b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16244c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16256b10d008SNikunj A Dadhania } 1626fcf5ef2aSThomas Huth } else { 1627fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1628fcf5ef2aSThomas Huth if (add_ca) { 16294c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16304c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1631fcf5ef2aSThomas Huth } else { 16324c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1633fcf5ef2aSThomas Huth } 16344c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1635fcf5ef2aSThomas Huth tcg_temp_free(zero); 1636fcf5ef2aSThomas Huth } 1637fcf5ef2aSThomas Huth } else { 1638fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1639fcf5ef2aSThomas Huth if (add_ca) { 16404c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1641fcf5ef2aSThomas Huth } 1642fcf5ef2aSThomas Huth } 1643fcf5ef2aSThomas Huth 1644fcf5ef2aSThomas Huth if (compute_ov) { 1645fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1646fcf5ef2aSThomas Huth } 1647fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1648fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1649fcf5ef2aSThomas Huth } 1650fcf5ef2aSThomas Huth 165111f4e8f8SRichard Henderson if (t0 != ret) { 1652fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1653fcf5ef2aSThomas Huth tcg_temp_free(t0); 1654fcf5ef2aSThomas Huth } 1655fcf5ef2aSThomas Huth } 1656fcf5ef2aSThomas Huth /* Add functions with two operands */ 16574c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1658fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1659fcf5ef2aSThomas Huth { \ 1660fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1661fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16624c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1663fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1664fcf5ef2aSThomas Huth } 1665fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16664c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1667fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1668fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1669fcf5ef2aSThomas Huth { \ 1670fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1671fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1672fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16734c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1674fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1675fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1676fcf5ef2aSThomas Huth } 1677fcf5ef2aSThomas Huth 1678fcf5ef2aSThomas Huth /* add add. addo addo. */ 16794c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16804c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1681fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16824c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16834c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1684fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 16854c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 16864c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1687fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 16884c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 16894c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 16904c5920afSSuraj Jitindar Singh /* addex */ 16914c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1692fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 16934c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 16944c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1695fcf5ef2aSThomas Huth /* addic addic.*/ 1696fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1697fcf5ef2aSThomas Huth { 1698fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1699fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17004c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1701fcf5ef2aSThomas Huth tcg_temp_free(c); 1702fcf5ef2aSThomas Huth } 1703fcf5ef2aSThomas Huth 1704fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1705fcf5ef2aSThomas Huth { 1706fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1707fcf5ef2aSThomas Huth } 1708fcf5ef2aSThomas Huth 1709fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1710fcf5ef2aSThomas Huth { 1711fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1712fcf5ef2aSThomas Huth } 1713fcf5ef2aSThomas Huth 1714fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1715fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1716fcf5ef2aSThomas Huth { 1717fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1718fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1719fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1720fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1721fcf5ef2aSThomas Huth 1722fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1723fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1724fcf5ef2aSThomas Huth if (sign) { 1725fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1726fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1727fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1728fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1729fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1730fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1731fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1732fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1733fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1734fcf5ef2aSThomas Huth } else { 1735fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1736fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1737fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1738fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1739fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1740fcf5ef2aSThomas Huth } 1741fcf5ef2aSThomas Huth if (compute_ov) { 1742fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1743c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1744c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1745c44027ffSNikunj A Dadhania } 1746fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1747fcf5ef2aSThomas Huth } 1748fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1749fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1750fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1751fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1752fcf5ef2aSThomas Huth 1753efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1754fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1755fcf5ef2aSThomas Huth } 1756efe843d8SDavid Gibson } 1757fcf5ef2aSThomas Huth /* Div functions */ 1758fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1759fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1760fcf5ef2aSThomas Huth { \ 1761fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1762fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1763fcf5ef2aSThomas Huth sign, compute_ov); \ 1764fcf5ef2aSThomas Huth } 1765fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1766fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1767fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1768fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1769fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1770fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1771fcf5ef2aSThomas Huth 1772fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1773fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1774fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1775fcf5ef2aSThomas Huth { \ 1776fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1777fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1778fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1779fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1780fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1781fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1782fcf5ef2aSThomas Huth } \ 1783fcf5ef2aSThomas Huth } 1784fcf5ef2aSThomas Huth 1785fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1786fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1787fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1788fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1789fcf5ef2aSThomas Huth 1790fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1791fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1792fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1793fcf5ef2aSThomas Huth { 1794fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1795fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1796fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1797fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1798fcf5ef2aSThomas Huth 1799fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1800fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1801fcf5ef2aSThomas Huth if (sign) { 1802fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1803fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1804fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1805fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1806fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1807fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1808fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1809fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1810fcf5ef2aSThomas Huth } else { 1811fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1812fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1813fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1814fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1815fcf5ef2aSThomas Huth } 1816fcf5ef2aSThomas Huth if (compute_ov) { 1817fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1818c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1819c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1820c44027ffSNikunj A Dadhania } 1821fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1822fcf5ef2aSThomas Huth } 1823fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1824fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1825fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1826fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1827fcf5ef2aSThomas Huth 1828efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1829fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1830fcf5ef2aSThomas Huth } 1831efe843d8SDavid Gibson } 1832fcf5ef2aSThomas Huth 1833fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1834fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1835fcf5ef2aSThomas Huth { \ 1836fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1837fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1838fcf5ef2aSThomas Huth sign, compute_ov); \ 1839fcf5ef2aSThomas Huth } 1840c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1841fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1842fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1843c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1844fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1845fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1846fcf5ef2aSThomas Huth 1847fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1848fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1849fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1850fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1851fcf5ef2aSThomas Huth #endif 1852fcf5ef2aSThomas Huth 1853fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1854fcf5ef2aSThomas Huth TCGv arg2, int sign) 1855fcf5ef2aSThomas Huth { 1856fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1857fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1858fcf5ef2aSThomas Huth 1859fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1860fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1861fcf5ef2aSThomas Huth if (sign) { 1862fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1863fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1864fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1865fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1866fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1867fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1868fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1869fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1870fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1871fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1872fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1873fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1874fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1875fcf5ef2aSThomas Huth } else { 1876fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1877fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1878fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1879fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1880fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1881fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1882fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1883fcf5ef2aSThomas Huth } 1884fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1885fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1886fcf5ef2aSThomas Huth } 1887fcf5ef2aSThomas Huth 1888fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1889fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1890fcf5ef2aSThomas Huth { \ 1891fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1892fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1893fcf5ef2aSThomas Huth sign); \ 1894fcf5ef2aSThomas Huth } 1895fcf5ef2aSThomas Huth 1896fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1897fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1898fcf5ef2aSThomas Huth 1899fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1900fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1901fcf5ef2aSThomas Huth TCGv arg2, int sign) 1902fcf5ef2aSThomas Huth { 1903fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1904fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1905fcf5ef2aSThomas Huth 1906fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1907fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1908fcf5ef2aSThomas Huth if (sign) { 1909fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1910fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1911fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1912fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1913fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1914fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1915fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1916fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1917fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1918fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1919fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1920fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1921fcf5ef2aSThomas Huth } else { 1922fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1923fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1924fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1925fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1926fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1927fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1928fcf5ef2aSThomas Huth } 1929fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1930fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1931fcf5ef2aSThomas Huth } 1932fcf5ef2aSThomas Huth 1933fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1934fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1935fcf5ef2aSThomas Huth { \ 1936fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1937fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1938fcf5ef2aSThomas Huth sign); \ 1939fcf5ef2aSThomas Huth } 1940fcf5ef2aSThomas Huth 1941fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1942fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1943fcf5ef2aSThomas Huth #endif 1944fcf5ef2aSThomas Huth 1945fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1946fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1947fcf5ef2aSThomas Huth { 1948fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1949fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1950fcf5ef2aSThomas Huth 1951fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1952fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1953fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1954fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1955fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1956fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1957efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1958fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1959fcf5ef2aSThomas Huth } 1960efe843d8SDavid Gibson } 1961fcf5ef2aSThomas Huth 1962fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1963fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1964fcf5ef2aSThomas Huth { 1965fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1966fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1967fcf5ef2aSThomas Huth 1968fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1969fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1970fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1971fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1972fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1973fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1974efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1975fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1976fcf5ef2aSThomas Huth } 1977efe843d8SDavid Gibson } 1978fcf5ef2aSThomas Huth 1979fcf5ef2aSThomas Huth /* mullw mullw. */ 1980fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1981fcf5ef2aSThomas Huth { 1982fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1983fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1984fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1985fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1986fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1987fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1988fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1989fcf5ef2aSThomas Huth tcg_temp_free(t0); 1990fcf5ef2aSThomas Huth tcg_temp_free(t1); 1991fcf5ef2aSThomas Huth #else 1992fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1993fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1994fcf5ef2aSThomas Huth #endif 1995efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1996fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1997fcf5ef2aSThomas Huth } 1998efe843d8SDavid Gibson } 1999fcf5ef2aSThomas Huth 2000fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2001fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2002fcf5ef2aSThomas Huth { 2003fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2004fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2005fcf5ef2aSThomas Huth 2006fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2007fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2008fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2009fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2010fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2011fcf5ef2aSThomas Huth #else 2012fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2013fcf5ef2aSThomas Huth #endif 2014fcf5ef2aSThomas Huth 2015fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2016fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2017fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 201861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 201961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 202061aa9a69SNikunj A Dadhania } 2021fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2022fcf5ef2aSThomas Huth 2023fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2024fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2025efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2026fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2027fcf5ef2aSThomas Huth } 2028efe843d8SDavid Gibson } 2029fcf5ef2aSThomas Huth 2030fcf5ef2aSThomas Huth /* mulli */ 2031fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2032fcf5ef2aSThomas Huth { 2033fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2034fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2035fcf5ef2aSThomas Huth } 2036fcf5ef2aSThomas Huth 2037fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2038fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2039fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2040fcf5ef2aSThomas Huth { 2041fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2042fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2043fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2044fcf5ef2aSThomas Huth tcg_temp_free(lo); 2045fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2046fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2047fcf5ef2aSThomas Huth } 2048fcf5ef2aSThomas Huth } 2049fcf5ef2aSThomas Huth 2050fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2051fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2052fcf5ef2aSThomas Huth { 2053fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2054fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2055fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2056fcf5ef2aSThomas Huth tcg_temp_free(lo); 2057fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2058fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2059fcf5ef2aSThomas Huth } 2060fcf5ef2aSThomas Huth } 2061fcf5ef2aSThomas Huth 2062fcf5ef2aSThomas Huth /* mulld mulld. */ 2063fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2064fcf5ef2aSThomas Huth { 2065fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2066fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2067efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2068fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2069fcf5ef2aSThomas Huth } 2070efe843d8SDavid Gibson } 2071fcf5ef2aSThomas Huth 2072fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2073fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2074fcf5ef2aSThomas Huth { 2075fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2076fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2077fcf5ef2aSThomas Huth 2078fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2079fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2080fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2083fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 208461aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 208561aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 208661aa9a69SNikunj A Dadhania } 2087fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2088fcf5ef2aSThomas Huth 2089fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2090fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2091fcf5ef2aSThomas Huth 2092fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2093fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2094fcf5ef2aSThomas Huth } 2095fcf5ef2aSThomas Huth } 2096fcf5ef2aSThomas Huth #endif 2097fcf5ef2aSThomas Huth 2098fcf5ef2aSThomas Huth /* Common subf function */ 2099fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2100fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2101fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2102fcf5ef2aSThomas Huth { 2103fcf5ef2aSThomas Huth TCGv t0 = ret; 2104fcf5ef2aSThomas Huth 2105fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2106fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2107fcf5ef2aSThomas Huth } 2108fcf5ef2aSThomas Huth 2109fcf5ef2aSThomas Huth if (compute_ca) { 2110fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2111fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2112efe843d8SDavid Gibson /* 2113efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2114efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2115efe843d8SDavid Gibson * produce the carry into bit 32. 2116efe843d8SDavid Gibson */ 2117fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2118fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2119fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2120fcf5ef2aSThomas Huth if (add_ca) { 2121fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2122fcf5ef2aSThomas Huth } else { 2123fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2124fcf5ef2aSThomas Huth } 2125fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2126fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2127fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2128fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2129fcf5ef2aSThomas Huth tcg_temp_free(t1); 2130e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 213133903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 213233903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 213333903d0aSNikunj A Dadhania } 2134fcf5ef2aSThomas Huth } else if (add_ca) { 2135fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2136fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2137fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2138fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2139fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21404c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2141fcf5ef2aSThomas Huth tcg_temp_free(zero); 2142fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2143fcf5ef2aSThomas Huth } else { 2144fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2145fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21464c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2147fcf5ef2aSThomas Huth } 2148fcf5ef2aSThomas Huth } else if (add_ca) { 2149efe843d8SDavid Gibson /* 2150efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2151efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2152efe843d8SDavid Gibson */ 2153fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2154fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2155fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2156fcf5ef2aSThomas Huth } else { 2157fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2158fcf5ef2aSThomas Huth } 2159fcf5ef2aSThomas Huth 2160fcf5ef2aSThomas Huth if (compute_ov) { 2161fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2162fcf5ef2aSThomas Huth } 2163fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2164fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2165fcf5ef2aSThomas Huth } 2166fcf5ef2aSThomas Huth 216711f4e8f8SRichard Henderson if (t0 != ret) { 2168fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2169fcf5ef2aSThomas Huth tcg_temp_free(t0); 2170fcf5ef2aSThomas Huth } 2171fcf5ef2aSThomas Huth } 2172fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2173fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2174fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2175fcf5ef2aSThomas Huth { \ 2176fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2177fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2178fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2179fcf5ef2aSThomas Huth } 2180fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2181fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2182fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2183fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2184fcf5ef2aSThomas Huth { \ 2185fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2186fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2187fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2188fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2189fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2190fcf5ef2aSThomas Huth } 2191fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2192fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2193fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2194fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2195fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2196fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2197fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2198fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2199fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2200fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2201fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2202fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2203fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2204fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2205fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2206fcf5ef2aSThomas Huth 2207fcf5ef2aSThomas Huth /* subfic */ 2208fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2209fcf5ef2aSThomas Huth { 2210fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2211fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2212fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2213fcf5ef2aSThomas Huth tcg_temp_free(c); 2214fcf5ef2aSThomas Huth } 2215fcf5ef2aSThomas Huth 2216fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2217fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2218fcf5ef2aSThomas Huth { 2219fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2220fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2221fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2222fcf5ef2aSThomas Huth tcg_temp_free(zero); 2223fcf5ef2aSThomas Huth } 2224fcf5ef2aSThomas Huth 2225fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2226fcf5ef2aSThomas Huth { 22271480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22281480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22291480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22301480d71cSNikunj A Dadhania } 2231fcf5ef2aSThomas Huth } 2232fcf5ef2aSThomas Huth 2233fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2234fcf5ef2aSThomas Huth { 2235fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2236fcf5ef2aSThomas Huth } 2237fcf5ef2aSThomas Huth 2238fcf5ef2aSThomas Huth /*** Integer logical ***/ 2239fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2240fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2241fcf5ef2aSThomas Huth { \ 2242fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2243fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2244fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2245fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2246fcf5ef2aSThomas Huth } 2247fcf5ef2aSThomas Huth 2248fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2249fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2250fcf5ef2aSThomas Huth { \ 2251fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2252fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2253fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2254fcf5ef2aSThomas Huth } 2255fcf5ef2aSThomas Huth 2256fcf5ef2aSThomas Huth /* and & and. */ 2257fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2258fcf5ef2aSThomas Huth /* andc & andc. */ 2259fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2260fcf5ef2aSThomas Huth 2261fcf5ef2aSThomas Huth /* andi. */ 2262fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2263fcf5ef2aSThomas Huth { 2264efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2265efe843d8SDavid Gibson UIMM(ctx->opcode)); 2266fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2267fcf5ef2aSThomas Huth } 2268fcf5ef2aSThomas Huth 2269fcf5ef2aSThomas Huth /* andis. */ 2270fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2271fcf5ef2aSThomas Huth { 2272efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2273efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2274fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2275fcf5ef2aSThomas Huth } 2276fcf5ef2aSThomas Huth 2277fcf5ef2aSThomas Huth /* cntlzw */ 2278fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2279fcf5ef2aSThomas Huth { 22809b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22819b8514e5SRichard Henderson 22829b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22839b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22849b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22859b8514e5SRichard Henderson tcg_temp_free_i32(t); 22869b8514e5SRichard Henderson 2287efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2288fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2289fcf5ef2aSThomas Huth } 2290efe843d8SDavid Gibson } 2291fcf5ef2aSThomas Huth 2292fcf5ef2aSThomas Huth /* cnttzw */ 2293fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2294fcf5ef2aSThomas Huth { 22959b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22969b8514e5SRichard Henderson 22979b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22989b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22999b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23009b8514e5SRichard Henderson tcg_temp_free_i32(t); 23019b8514e5SRichard Henderson 2302fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2303fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2304fcf5ef2aSThomas Huth } 2305fcf5ef2aSThomas Huth } 2306fcf5ef2aSThomas Huth 2307fcf5ef2aSThomas Huth /* eqv & eqv. */ 2308fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2309fcf5ef2aSThomas Huth /* extsb & extsb. */ 2310fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2311fcf5ef2aSThomas Huth /* extsh & extsh. */ 2312fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2313fcf5ef2aSThomas Huth /* nand & nand. */ 2314fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2315fcf5ef2aSThomas Huth /* nor & nor. */ 2316fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2317fcf5ef2aSThomas Huth 2318fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2319fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2320fcf5ef2aSThomas Huth { 2321fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2322fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2323fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2324fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2325fcf5ef2aSThomas Huth 2326fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2327b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2328fcf5ef2aSThomas Huth } 2329fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2330fcf5ef2aSThomas Huth 2331fcf5ef2aSThomas Huth /* or & or. */ 2332fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2333fcf5ef2aSThomas Huth { 2334fcf5ef2aSThomas Huth int rs, ra, rb; 2335fcf5ef2aSThomas Huth 2336fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2337fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2338fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2339fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2340fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2341efe843d8SDavid Gibson if (rs != rb) { 2342fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2343efe843d8SDavid Gibson } else { 2344fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2345efe843d8SDavid Gibson } 2346efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2347fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2348efe843d8SDavid Gibson } 2349fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2350fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2351fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2352fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2353fcf5ef2aSThomas Huth int prio = 0; 2354fcf5ef2aSThomas Huth 2355fcf5ef2aSThomas Huth switch (rs) { 2356fcf5ef2aSThomas Huth case 1: 2357fcf5ef2aSThomas Huth /* Set process priority to low */ 2358fcf5ef2aSThomas Huth prio = 2; 2359fcf5ef2aSThomas Huth break; 2360fcf5ef2aSThomas Huth case 6: 2361fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2362fcf5ef2aSThomas Huth prio = 3; 2363fcf5ef2aSThomas Huth break; 2364fcf5ef2aSThomas Huth case 2: 2365fcf5ef2aSThomas Huth /* Set process priority to normal */ 2366fcf5ef2aSThomas Huth prio = 4; 2367fcf5ef2aSThomas Huth break; 2368fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2369fcf5ef2aSThomas Huth case 31: 2370fcf5ef2aSThomas Huth if (!ctx->pr) { 2371fcf5ef2aSThomas Huth /* Set process priority to very low */ 2372fcf5ef2aSThomas Huth prio = 1; 2373fcf5ef2aSThomas Huth } 2374fcf5ef2aSThomas Huth break; 2375fcf5ef2aSThomas Huth case 5: 2376fcf5ef2aSThomas Huth if (!ctx->pr) { 2377fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2378fcf5ef2aSThomas Huth prio = 5; 2379fcf5ef2aSThomas Huth } 2380fcf5ef2aSThomas Huth break; 2381fcf5ef2aSThomas Huth case 3: 2382fcf5ef2aSThomas Huth if (!ctx->pr) { 2383fcf5ef2aSThomas Huth /* Set process priority to high */ 2384fcf5ef2aSThomas Huth prio = 6; 2385fcf5ef2aSThomas Huth } 2386fcf5ef2aSThomas Huth break; 2387fcf5ef2aSThomas Huth case 7: 2388fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2389fcf5ef2aSThomas Huth /* Set process priority to very high */ 2390fcf5ef2aSThomas Huth prio = 7; 2391fcf5ef2aSThomas Huth } 2392fcf5ef2aSThomas Huth break; 2393fcf5ef2aSThomas Huth #endif 2394fcf5ef2aSThomas Huth default: 2395fcf5ef2aSThomas Huth break; 2396fcf5ef2aSThomas Huth } 2397fcf5ef2aSThomas Huth if (prio) { 2398fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2399fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2400fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2401fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2402fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2403fcf5ef2aSThomas Huth tcg_temp_free(t0); 2404fcf5ef2aSThomas Huth } 2405fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2406efe843d8SDavid Gibson /* 2407efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2408efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2409efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2410efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2411fcf5ef2aSThomas Huth */ 2412fcf5ef2aSThomas Huth gen_pause(ctx); 2413fcf5ef2aSThomas Huth #endif 2414fcf5ef2aSThomas Huth #endif 2415fcf5ef2aSThomas Huth } 2416fcf5ef2aSThomas Huth } 2417fcf5ef2aSThomas Huth /* orc & orc. */ 2418fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2419fcf5ef2aSThomas Huth 2420fcf5ef2aSThomas Huth /* xor & xor. */ 2421fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2422fcf5ef2aSThomas Huth { 2423fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2424efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2425efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2426efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2427efe843d8SDavid Gibson } else { 2428fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2429efe843d8SDavid Gibson } 2430efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2431fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2432fcf5ef2aSThomas Huth } 2433efe843d8SDavid Gibson } 2434fcf5ef2aSThomas Huth 2435fcf5ef2aSThomas Huth /* ori */ 2436fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2437fcf5ef2aSThomas Huth { 2438fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2439fcf5ef2aSThomas Huth 2440fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2441fcf5ef2aSThomas Huth return; 2442fcf5ef2aSThomas Huth } 2443fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2444fcf5ef2aSThomas Huth } 2445fcf5ef2aSThomas Huth 2446fcf5ef2aSThomas Huth /* oris */ 2447fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2448fcf5ef2aSThomas Huth { 2449fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2450fcf5ef2aSThomas Huth 2451fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2452fcf5ef2aSThomas Huth /* NOP */ 2453fcf5ef2aSThomas Huth return; 2454fcf5ef2aSThomas Huth } 2455efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2456efe843d8SDavid Gibson uimm << 16); 2457fcf5ef2aSThomas Huth } 2458fcf5ef2aSThomas Huth 2459fcf5ef2aSThomas Huth /* xori */ 2460fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2461fcf5ef2aSThomas Huth { 2462fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2463fcf5ef2aSThomas Huth 2464fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2465fcf5ef2aSThomas Huth /* NOP */ 2466fcf5ef2aSThomas Huth return; 2467fcf5ef2aSThomas Huth } 2468fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2469fcf5ef2aSThomas Huth } 2470fcf5ef2aSThomas Huth 2471fcf5ef2aSThomas Huth /* xoris */ 2472fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2473fcf5ef2aSThomas Huth { 2474fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2475fcf5ef2aSThomas Huth 2476fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2477fcf5ef2aSThomas Huth /* NOP */ 2478fcf5ef2aSThomas Huth return; 2479fcf5ef2aSThomas Huth } 2480efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2481efe843d8SDavid Gibson uimm << 16); 2482fcf5ef2aSThomas Huth } 2483fcf5ef2aSThomas Huth 2484fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2485fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2486fcf5ef2aSThomas Huth { 2487fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2488fcf5ef2aSThomas Huth } 2489fcf5ef2aSThomas Huth 2490fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2491fcf5ef2aSThomas Huth { 249279770002SRichard Henderson #if defined(TARGET_PPC64) 2493fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 249479770002SRichard Henderson #else 249579770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 249679770002SRichard Henderson #endif 2497fcf5ef2aSThomas Huth } 2498fcf5ef2aSThomas Huth 2499fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2500fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2501fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2502fcf5ef2aSThomas Huth { 250379770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2504fcf5ef2aSThomas Huth } 2505fcf5ef2aSThomas Huth #endif 2506fcf5ef2aSThomas Huth 2507fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2508fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2509fcf5ef2aSThomas Huth { 2510fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2511fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2512fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2513fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2514fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2515fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2516fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2517fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2518fcf5ef2aSThomas Huth tcg_temp_free(t0); 2519fcf5ef2aSThomas Huth } 2520fcf5ef2aSThomas Huth 2521fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2522fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2523fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2524fcf5ef2aSThomas Huth { 2525fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2526fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2527fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2528fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2529fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2530fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2531fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2532fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2533fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2534fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2535fcf5ef2aSThomas Huth tcg_temp_free(t0); 2536fcf5ef2aSThomas Huth } 2537fcf5ef2aSThomas Huth #endif 2538fcf5ef2aSThomas Huth 2539fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2540fcf5ef2aSThomas Huth /* bpermd */ 2541fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2542fcf5ef2aSThomas Huth { 2543fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2544fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2545fcf5ef2aSThomas Huth } 2546fcf5ef2aSThomas Huth #endif 2547fcf5ef2aSThomas Huth 2548fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2549fcf5ef2aSThomas Huth /* extsw & extsw. */ 2550fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2551fcf5ef2aSThomas Huth 2552fcf5ef2aSThomas Huth /* cntlzd */ 2553fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2554fcf5ef2aSThomas Huth { 25559b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2556efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2557fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2558fcf5ef2aSThomas Huth } 2559efe843d8SDavid Gibson } 2560fcf5ef2aSThomas Huth 2561fcf5ef2aSThomas Huth /* cnttzd */ 2562fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2563fcf5ef2aSThomas Huth { 25649b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2565fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2566fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2567fcf5ef2aSThomas Huth } 2568fcf5ef2aSThomas Huth } 2569fcf5ef2aSThomas Huth 2570fcf5ef2aSThomas Huth /* darn */ 2571fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2572fcf5ef2aSThomas Huth { 2573fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2574fcf5ef2aSThomas Huth 25757e4357f6SRichard Henderson if (l > 2) { 25767e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25777e4357f6SRichard Henderson } else { 2578f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2579fcf5ef2aSThomas Huth if (l == 0) { 2580fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25817e4357f6SRichard Henderson } else { 2582fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2583fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25847e4357f6SRichard Henderson } 2585fcf5ef2aSThomas Huth } 2586fcf5ef2aSThomas Huth } 2587fcf5ef2aSThomas Huth #endif 2588fcf5ef2aSThomas Huth 2589fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2590fcf5ef2aSThomas Huth 2591fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2592fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2593fcf5ef2aSThomas Huth { 2594fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2595fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2596fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2597fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2598fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2599fcf5ef2aSThomas Huth 2600fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2601fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2602fcf5ef2aSThomas Huth } else { 2603fcf5ef2aSThomas Huth target_ulong mask; 2604c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2605fcf5ef2aSThomas Huth TCGv t1; 2606fcf5ef2aSThomas Huth 2607fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2608fcf5ef2aSThomas Huth mb += 32; 2609fcf5ef2aSThomas Huth me += 32; 2610fcf5ef2aSThomas Huth #endif 2611fcf5ef2aSThomas Huth mask = MASK(mb, me); 2612fcf5ef2aSThomas Huth 2613c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2614c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2615c4f6a4a3SDaniele Buono mask_in_32b = false; 2616c4f6a4a3SDaniele Buono } 2617c4f6a4a3SDaniele Buono #endif 2618fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2619c4f6a4a3SDaniele Buono if (mask_in_32b) { 2620fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2621fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2622fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2623fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2624fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2625fcf5ef2aSThomas Huth } else { 2626fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2627fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2628fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2629fcf5ef2aSThomas Huth #else 2630fcf5ef2aSThomas Huth g_assert_not_reached(); 2631fcf5ef2aSThomas Huth #endif 2632fcf5ef2aSThomas Huth } 2633fcf5ef2aSThomas Huth 2634fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2635fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2636fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2637fcf5ef2aSThomas Huth tcg_temp_free(t1); 2638fcf5ef2aSThomas Huth } 2639fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2640fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2641fcf5ef2aSThomas Huth } 2642fcf5ef2aSThomas Huth } 2643fcf5ef2aSThomas Huth 2644fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2645fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2646fcf5ef2aSThomas Huth { 2647fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2648fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26497b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26507b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26517b4d326fSRichard Henderson int me = ME(ctx->opcode); 26527b4d326fSRichard Henderson int len = me - mb + 1; 26537b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2654fcf5ef2aSThomas Huth 26557b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26567b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26577b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26587b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2659fcf5ef2aSThomas Huth } else { 2660fcf5ef2aSThomas Huth target_ulong mask; 2661c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2662fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2663fcf5ef2aSThomas Huth mb += 32; 2664fcf5ef2aSThomas Huth me += 32; 2665fcf5ef2aSThomas Huth #endif 2666fcf5ef2aSThomas Huth mask = MASK(mb, me); 2667c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2668c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2669c4f6a4a3SDaniele Buono mask_in_32b = false; 2670c4f6a4a3SDaniele Buono } 2671c4f6a4a3SDaniele Buono #endif 2672c4f6a4a3SDaniele Buono if (mask_in_32b) { 26737b4d326fSRichard Henderson if (sh == 0) { 26747b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 267594f040aaSVitaly Chikunov } else { 2676fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2677fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2678fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2679fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2680fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2681fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 268294f040aaSVitaly Chikunov } 2683fcf5ef2aSThomas Huth } else { 2684fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2685fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2686fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2687fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2688fcf5ef2aSThomas Huth #else 2689fcf5ef2aSThomas Huth g_assert_not_reached(); 2690fcf5ef2aSThomas Huth #endif 2691fcf5ef2aSThomas Huth } 2692fcf5ef2aSThomas Huth } 2693fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2694fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2695fcf5ef2aSThomas Huth } 2696fcf5ef2aSThomas Huth } 2697fcf5ef2aSThomas Huth 2698fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2699fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2700fcf5ef2aSThomas Huth { 2701fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2702fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2703fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2704fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2705fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2706fcf5ef2aSThomas Huth target_ulong mask; 2707c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2708fcf5ef2aSThomas Huth 2709fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2710fcf5ef2aSThomas Huth mb += 32; 2711fcf5ef2aSThomas Huth me += 32; 2712fcf5ef2aSThomas Huth #endif 2713fcf5ef2aSThomas Huth mask = MASK(mb, me); 2714fcf5ef2aSThomas Huth 2715c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2716c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2717c4f6a4a3SDaniele Buono mask_in_32b = false; 2718c4f6a4a3SDaniele Buono } 2719c4f6a4a3SDaniele Buono #endif 2720c4f6a4a3SDaniele Buono if (mask_in_32b) { 2721fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2722fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2723fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2724fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2725fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2726fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2727fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2728fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2729fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2730fcf5ef2aSThomas Huth } else { 2731fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2732fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2733fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2734fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2735fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2736fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2737fcf5ef2aSThomas Huth #else 2738fcf5ef2aSThomas Huth g_assert_not_reached(); 2739fcf5ef2aSThomas Huth #endif 2740fcf5ef2aSThomas Huth } 2741fcf5ef2aSThomas Huth 2742fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2743fcf5ef2aSThomas Huth 2744fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2745fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2746fcf5ef2aSThomas Huth } 2747fcf5ef2aSThomas Huth } 2748fcf5ef2aSThomas Huth 2749fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2750fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2751fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2752fcf5ef2aSThomas Huth { \ 2753fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2754fcf5ef2aSThomas Huth } \ 2755fcf5ef2aSThomas Huth \ 2756fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2757fcf5ef2aSThomas Huth { \ 2758fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2759fcf5ef2aSThomas Huth } 2760fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2761fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2762fcf5ef2aSThomas Huth { \ 2763fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2764fcf5ef2aSThomas Huth } \ 2765fcf5ef2aSThomas Huth \ 2766fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2767fcf5ef2aSThomas Huth { \ 2768fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2769fcf5ef2aSThomas Huth } \ 2770fcf5ef2aSThomas Huth \ 2771fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2772fcf5ef2aSThomas Huth { \ 2773fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2774fcf5ef2aSThomas Huth } \ 2775fcf5ef2aSThomas Huth \ 2776fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2777fcf5ef2aSThomas Huth { \ 2778fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2779fcf5ef2aSThomas Huth } 2780fcf5ef2aSThomas Huth 2781fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2782fcf5ef2aSThomas Huth { 2783fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2784fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27857b4d326fSRichard Henderson int len = me - mb + 1; 27867b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2787fcf5ef2aSThomas Huth 27887b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27897b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27907b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27917b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2792fcf5ef2aSThomas Huth } else { 2793fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2794fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2795fcf5ef2aSThomas Huth } 2796fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2797fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2798fcf5ef2aSThomas Huth } 2799fcf5ef2aSThomas Huth } 2800fcf5ef2aSThomas Huth 2801fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2802fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2803fcf5ef2aSThomas Huth { 2804fcf5ef2aSThomas Huth uint32_t sh, mb; 2805fcf5ef2aSThomas Huth 2806fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2807fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2808fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2809fcf5ef2aSThomas Huth } 2810fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2811fcf5ef2aSThomas Huth 2812fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2813fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2814fcf5ef2aSThomas Huth { 2815fcf5ef2aSThomas Huth uint32_t sh, me; 2816fcf5ef2aSThomas Huth 2817fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2818fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2819fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2820fcf5ef2aSThomas Huth } 2821fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2822fcf5ef2aSThomas Huth 2823fcf5ef2aSThomas Huth /* rldic - rldic. */ 2824fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2825fcf5ef2aSThomas Huth { 2826fcf5ef2aSThomas Huth uint32_t sh, mb; 2827fcf5ef2aSThomas Huth 2828fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2829fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2830fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2831fcf5ef2aSThomas Huth } 2832fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2833fcf5ef2aSThomas Huth 2834fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2835fcf5ef2aSThomas Huth { 2836fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2837fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2838fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2839fcf5ef2aSThomas Huth TCGv t0; 2840fcf5ef2aSThomas Huth 2841fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2842fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2843fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2844fcf5ef2aSThomas Huth tcg_temp_free(t0); 2845fcf5ef2aSThomas Huth 2846fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2847fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2848fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth } 2851fcf5ef2aSThomas Huth 2852fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2853fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2854fcf5ef2aSThomas Huth { 2855fcf5ef2aSThomas Huth uint32_t mb; 2856fcf5ef2aSThomas Huth 2857fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2858fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2859fcf5ef2aSThomas Huth } 2860fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2861fcf5ef2aSThomas Huth 2862fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2863fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2864fcf5ef2aSThomas Huth { 2865fcf5ef2aSThomas Huth uint32_t me; 2866fcf5ef2aSThomas Huth 2867fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2868fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2869fcf5ef2aSThomas Huth } 2870fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2871fcf5ef2aSThomas Huth 2872fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2873fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2874fcf5ef2aSThomas Huth { 2875fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2876fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2877fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2878fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2879fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2880fcf5ef2aSThomas Huth 2881fcf5ef2aSThomas Huth if (mb <= me) { 2882fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2883fcf5ef2aSThomas Huth } else { 2884fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2885fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2886fcf5ef2aSThomas Huth 2887fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2888fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2889fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2890fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2891fcf5ef2aSThomas Huth tcg_temp_free(t1); 2892fcf5ef2aSThomas Huth } 2893fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2894fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2895fcf5ef2aSThomas Huth } 2896fcf5ef2aSThomas Huth } 2897fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2898fcf5ef2aSThomas Huth #endif 2899fcf5ef2aSThomas Huth 2900fcf5ef2aSThomas Huth /*** Integer shift ***/ 2901fcf5ef2aSThomas Huth 2902fcf5ef2aSThomas Huth /* slw & slw. */ 2903fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2904fcf5ef2aSThomas Huth { 2905fcf5ef2aSThomas Huth TCGv t0, t1; 2906fcf5ef2aSThomas Huth 2907fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2908fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2909fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2910fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2911fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2912fcf5ef2aSThomas Huth #else 2913fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2914fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2915fcf5ef2aSThomas Huth #endif 2916fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2917fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2918fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2919fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2920fcf5ef2aSThomas Huth tcg_temp_free(t1); 2921fcf5ef2aSThomas Huth tcg_temp_free(t0); 2922fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2923efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2924fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2925fcf5ef2aSThomas Huth } 2926efe843d8SDavid Gibson } 2927fcf5ef2aSThomas Huth 2928fcf5ef2aSThomas Huth /* sraw & sraw. */ 2929fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2930fcf5ef2aSThomas Huth { 2931fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2932fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2933efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2934fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2935fcf5ef2aSThomas Huth } 2936efe843d8SDavid Gibson } 2937fcf5ef2aSThomas Huth 2938fcf5ef2aSThomas Huth /* srawi & srawi. */ 2939fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2940fcf5ef2aSThomas Huth { 2941fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2942fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2943fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2944fcf5ef2aSThomas Huth if (sh == 0) { 2945fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2946fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2947af1c259fSSandipan Das if (is_isa300(ctx)) { 2948af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2949af1c259fSSandipan Das } 2950fcf5ef2aSThomas Huth } else { 2951fcf5ef2aSThomas Huth TCGv t0; 2952fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2953fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2954fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2955fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2956fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2957fcf5ef2aSThomas Huth tcg_temp_free(t0); 2958fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2959af1c259fSSandipan Das if (is_isa300(ctx)) { 2960af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2961af1c259fSSandipan Das } 2962fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2963fcf5ef2aSThomas Huth } 2964fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2965fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2966fcf5ef2aSThomas Huth } 2967fcf5ef2aSThomas Huth } 2968fcf5ef2aSThomas Huth 2969fcf5ef2aSThomas Huth /* srw & srw. */ 2970fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2971fcf5ef2aSThomas Huth { 2972fcf5ef2aSThomas Huth TCGv t0, t1; 2973fcf5ef2aSThomas Huth 2974fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2975fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2976fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2977fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2978fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2979fcf5ef2aSThomas Huth #else 2980fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2981fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2982fcf5ef2aSThomas Huth #endif 2983fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2984fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2985fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2986fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2987fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2988fcf5ef2aSThomas Huth tcg_temp_free(t1); 2989fcf5ef2aSThomas Huth tcg_temp_free(t0); 2990efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2991fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2992fcf5ef2aSThomas Huth } 2993efe843d8SDavid Gibson } 2994fcf5ef2aSThomas Huth 2995fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2996fcf5ef2aSThomas Huth /* sld & sld. */ 2997fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2998fcf5ef2aSThomas Huth { 2999fcf5ef2aSThomas Huth TCGv t0, t1; 3000fcf5ef2aSThomas Huth 3001fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3002fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3003fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3004fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3005fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3006fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3007fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3008fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3009fcf5ef2aSThomas Huth tcg_temp_free(t1); 3010fcf5ef2aSThomas Huth tcg_temp_free(t0); 3011efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3012fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3013fcf5ef2aSThomas Huth } 3014efe843d8SDavid Gibson } 3015fcf5ef2aSThomas Huth 3016fcf5ef2aSThomas Huth /* srad & srad. */ 3017fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3018fcf5ef2aSThomas Huth { 3019fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3020fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3021efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3022fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3023fcf5ef2aSThomas Huth } 3024efe843d8SDavid Gibson } 3025fcf5ef2aSThomas Huth /* sradi & sradi. */ 3026fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3027fcf5ef2aSThomas Huth { 3028fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3029fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3030fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3031fcf5ef2aSThomas Huth if (sh == 0) { 3032fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3033fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3034af1c259fSSandipan Das if (is_isa300(ctx)) { 3035af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3036af1c259fSSandipan Das } 3037fcf5ef2aSThomas Huth } else { 3038fcf5ef2aSThomas Huth TCGv t0; 3039fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3040fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3041fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3042fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3043fcf5ef2aSThomas Huth tcg_temp_free(t0); 3044fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3045af1c259fSSandipan Das if (is_isa300(ctx)) { 3046af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3047af1c259fSSandipan Das } 3048fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3049fcf5ef2aSThomas Huth } 3050fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3051fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3052fcf5ef2aSThomas Huth } 3053fcf5ef2aSThomas Huth } 3054fcf5ef2aSThomas Huth 3055fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3056fcf5ef2aSThomas Huth { 3057fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3058fcf5ef2aSThomas Huth } 3059fcf5ef2aSThomas Huth 3060fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3061fcf5ef2aSThomas Huth { 3062fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3063fcf5ef2aSThomas Huth } 3064fcf5ef2aSThomas Huth 3065fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3066fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3067fcf5ef2aSThomas Huth { 3068fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3069fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3070fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3071fcf5ef2aSThomas Huth 3072fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3073fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3074fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3075fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3076fcf5ef2aSThomas Huth } 3077fcf5ef2aSThomas Huth } 3078fcf5ef2aSThomas Huth 3079fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3080fcf5ef2aSThomas Huth { 3081fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3082fcf5ef2aSThomas Huth } 3083fcf5ef2aSThomas Huth 3084fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3085fcf5ef2aSThomas Huth { 3086fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3087fcf5ef2aSThomas Huth } 3088fcf5ef2aSThomas Huth 3089fcf5ef2aSThomas Huth /* srd & srd. */ 3090fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3091fcf5ef2aSThomas Huth { 3092fcf5ef2aSThomas Huth TCGv t0, t1; 3093fcf5ef2aSThomas Huth 3094fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3095fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3096fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3097fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3098fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3099fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3100fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3101fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3102fcf5ef2aSThomas Huth tcg_temp_free(t1); 3103fcf5ef2aSThomas Huth tcg_temp_free(t0); 3104efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3105fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3106fcf5ef2aSThomas Huth } 3107efe843d8SDavid Gibson } 3108fcf5ef2aSThomas Huth #endif 3109fcf5ef2aSThomas Huth 3110fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3111fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3112fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3113fcf5ef2aSThomas Huth target_long maskl) 3114fcf5ef2aSThomas Huth { 3115fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3116fcf5ef2aSThomas Huth 3117fcf5ef2aSThomas Huth simm &= ~maskl; 3118fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3119fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3120fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3121fcf5ef2aSThomas Huth } 3122fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3123fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3124fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3125fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3126fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3127fcf5ef2aSThomas Huth } 3128fcf5ef2aSThomas Huth } else { 3129fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3130fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3131fcf5ef2aSThomas Huth } else { 3132fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3133fcf5ef2aSThomas Huth } 3134fcf5ef2aSThomas Huth } 3135fcf5ef2aSThomas Huth } 3136fcf5ef2aSThomas Huth 3137fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3138fcf5ef2aSThomas Huth { 3139fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3140fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3141fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3142fcf5ef2aSThomas Huth } else { 3143fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3144fcf5ef2aSThomas Huth } 3145fcf5ef2aSThomas Huth } else { 3146fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3147fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3148fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3149fcf5ef2aSThomas Huth } 3150fcf5ef2aSThomas Huth } 3151fcf5ef2aSThomas Huth } 3152fcf5ef2aSThomas Huth 3153fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3154fcf5ef2aSThomas Huth { 3155fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3156fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3157fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3158fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3159fcf5ef2aSThomas Huth } else { 3160fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3161fcf5ef2aSThomas Huth } 3162fcf5ef2aSThomas Huth } 3163fcf5ef2aSThomas Huth 3164fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3165fcf5ef2aSThomas Huth target_long val) 3166fcf5ef2aSThomas Huth { 3167fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3168fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3169fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3170fcf5ef2aSThomas Huth } 3171fcf5ef2aSThomas Huth } 3172fcf5ef2aSThomas Huth 3173fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3174fcf5ef2aSThomas Huth { 3175fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3176fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3177fcf5ef2aSThomas Huth } 3178fcf5ef2aSThomas Huth 3179eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3180eb63efd9SFernando Eckhardt Valle { 3181eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3182eb63efd9SFernando Eckhardt Valle if (ra) { 3183eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3184eb63efd9SFernando Eckhardt Valle } else { 3185eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3186eb63efd9SFernando Eckhardt Valle } 3187eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3188eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3189eb63efd9SFernando Eckhardt Valle } 3190eb63efd9SFernando Eckhardt Valle return ea; 3191eb63efd9SFernando Eckhardt Valle } 3192eb63efd9SFernando Eckhardt Valle 3193fcf5ef2aSThomas Huth /*** Integer load ***/ 3194fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3195fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3196fcf5ef2aSThomas Huth 3197fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3198fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3199fcf5ef2aSThomas Huth TCGv val, \ 3200fcf5ef2aSThomas Huth TCGv addr) \ 3201fcf5ef2aSThomas Huth { \ 3202fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3203fcf5ef2aSThomas Huth } 3204fcf5ef2aSThomas Huth 3205fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3206fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3207fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3208fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3209fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3210fcf5ef2aSThomas Huth 3211fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3212fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3213fcf5ef2aSThomas Huth 3214fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3215fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3216fcf5ef2aSThomas Huth TCGv_i64 val, \ 3217fcf5ef2aSThomas Huth TCGv addr) \ 3218fcf5ef2aSThomas Huth { \ 3219fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3220fcf5ef2aSThomas Huth } 3221fcf5ef2aSThomas Huth 3222fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3223fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3224fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3225fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3226fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3227fcf5ef2aSThomas Huth 3228fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3229fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3230fcf5ef2aSThomas Huth #endif 3231fcf5ef2aSThomas Huth 3232fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3233fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3234fcf5ef2aSThomas Huth TCGv val, \ 3235fcf5ef2aSThomas Huth TCGv addr) \ 3236fcf5ef2aSThomas Huth { \ 3237fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3238fcf5ef2aSThomas Huth } 3239fcf5ef2aSThomas Huth 3240e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3241fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3242e8f4c8d6SRichard Henderson #endif 3243fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3244fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3245fcf5ef2aSThomas Huth 3246fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3247fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3248fcf5ef2aSThomas Huth 3249fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3250fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3251fcf5ef2aSThomas Huth TCGv_i64 val, \ 3252fcf5ef2aSThomas Huth TCGv addr) \ 3253fcf5ef2aSThomas Huth { \ 3254fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3255fcf5ef2aSThomas Huth } 3256fcf5ef2aSThomas Huth 3257fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3258fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3259fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3260fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3261fcf5ef2aSThomas Huth 3262fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3263fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3264fcf5ef2aSThomas Huth #endif 3265fcf5ef2aSThomas Huth 3266fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3267fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3268fcf5ef2aSThomas Huth { \ 3269fcf5ef2aSThomas Huth TCGv EA; \ 32709f0cf041SMatheus Ferst chk(ctx); \ 3271fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3272fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3273fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3274fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3275fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3276fcf5ef2aSThomas Huth } 3277fcf5ef2aSThomas Huth 3278fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3279fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3280fcf5ef2aSThomas Huth 3281fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3282fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3283fcf5ef2aSThomas Huth 328450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 328550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 328650728199SRoman Kapl { \ 328750728199SRoman Kapl TCGv EA; \ 32889f0cf041SMatheus Ferst CHK_SV(ctx); \ 328950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 329050728199SRoman Kapl EA = tcg_temp_new(); \ 329150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 329250728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 329350728199SRoman Kapl tcg_temp_free(EA); \ 329450728199SRoman Kapl } 329550728199SRoman Kapl 329650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 329750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 329850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 329950728199SRoman Kapl #if defined(TARGET_PPC64) 3300fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 330150728199SRoman Kapl #endif 330250728199SRoman Kapl 3303fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3304fcf5ef2aSThomas Huth /* CI load/store variants */ 3305fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3306fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3307fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3308fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3309fcf5ef2aSThomas Huth #endif 3310fcf5ef2aSThomas Huth 3311fcf5ef2aSThomas Huth /*** Integer store ***/ 3312fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3313fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3314fcf5ef2aSThomas Huth { \ 3315fcf5ef2aSThomas Huth TCGv EA; \ 33169f0cf041SMatheus Ferst chk(ctx); \ 3317fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3318fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3319fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3320fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3321fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3322fcf5ef2aSThomas Huth } 3323fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3324fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3325fcf5ef2aSThomas Huth 3326fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3327fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3328fcf5ef2aSThomas Huth 332950728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 333050728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 333150728199SRoman Kapl { \ 333250728199SRoman Kapl TCGv EA; \ 33339f0cf041SMatheus Ferst CHK_SV(ctx); \ 333450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 333550728199SRoman Kapl EA = tcg_temp_new(); \ 333650728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 333750728199SRoman Kapl tcg_gen_qemu_st_tl( \ 333850728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 333950728199SRoman Kapl tcg_temp_free(EA); \ 334050728199SRoman Kapl } 334150728199SRoman Kapl 334250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 334350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 334450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 334550728199SRoman Kapl #if defined(TARGET_PPC64) 3346fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 334750728199SRoman Kapl #endif 334850728199SRoman Kapl 3349fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3350fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3351fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3352fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3353fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3354fcf5ef2aSThomas Huth #endif 3355fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3356fcf5ef2aSThomas Huth 3357fcf5ef2aSThomas Huth /* lhbrx */ 3358fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3359fcf5ef2aSThomas Huth 3360fcf5ef2aSThomas Huth /* lwbrx */ 3361fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3362fcf5ef2aSThomas Huth 3363fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3364fcf5ef2aSThomas Huth /* ldbrx */ 3365fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3366fcf5ef2aSThomas Huth /* stdbrx */ 3367fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3368fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3369fcf5ef2aSThomas Huth 3370fcf5ef2aSThomas Huth /* sthbrx */ 3371fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3372fcf5ef2aSThomas Huth /* stwbrx */ 3373fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3374fcf5ef2aSThomas Huth 3375fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3376fcf5ef2aSThomas Huth 3377fcf5ef2aSThomas Huth /* lmw */ 3378fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3379fcf5ef2aSThomas Huth { 3380fcf5ef2aSThomas Huth TCGv t0; 3381fcf5ef2aSThomas Huth TCGv_i32 t1; 3382fcf5ef2aSThomas Huth 3383fcf5ef2aSThomas Huth if (ctx->le_mode) { 3384fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3385fcf5ef2aSThomas Huth return; 3386fcf5ef2aSThomas Huth } 3387fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3388fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3389fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3390fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3391fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3392fcf5ef2aSThomas Huth tcg_temp_free(t0); 3393fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3394fcf5ef2aSThomas Huth } 3395fcf5ef2aSThomas Huth 3396fcf5ef2aSThomas Huth /* stmw */ 3397fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3398fcf5ef2aSThomas Huth { 3399fcf5ef2aSThomas Huth TCGv t0; 3400fcf5ef2aSThomas Huth TCGv_i32 t1; 3401fcf5ef2aSThomas Huth 3402fcf5ef2aSThomas Huth if (ctx->le_mode) { 3403fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3404fcf5ef2aSThomas Huth return; 3405fcf5ef2aSThomas Huth } 3406fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3407fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3408fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3409fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3410fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3411fcf5ef2aSThomas Huth tcg_temp_free(t0); 3412fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3413fcf5ef2aSThomas Huth } 3414fcf5ef2aSThomas Huth 3415fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3416fcf5ef2aSThomas Huth 3417fcf5ef2aSThomas Huth /* lswi */ 3418efe843d8SDavid Gibson /* 3419efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3420efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3421efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3422efe843d8SDavid Gibson * spec... 3423fcf5ef2aSThomas Huth */ 3424fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3425fcf5ef2aSThomas Huth { 3426fcf5ef2aSThomas Huth TCGv t0; 3427fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3428fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3429fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3430fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3431fcf5ef2aSThomas Huth int nr; 3432fcf5ef2aSThomas Huth 3433fcf5ef2aSThomas Huth if (ctx->le_mode) { 3434fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3435fcf5ef2aSThomas Huth return; 3436fcf5ef2aSThomas Huth } 3437efe843d8SDavid Gibson if (nb == 0) { 3438fcf5ef2aSThomas Huth nb = 32; 3439efe843d8SDavid Gibson } 3440f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3441fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3442fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3443fcf5ef2aSThomas Huth return; 3444fcf5ef2aSThomas Huth } 3445fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3446fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3447fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3448fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3449fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3450fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3451fcf5ef2aSThomas Huth tcg_temp_free(t0); 3452fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3453fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3454fcf5ef2aSThomas Huth } 3455fcf5ef2aSThomas Huth 3456fcf5ef2aSThomas Huth /* lswx */ 3457fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3458fcf5ef2aSThomas Huth { 3459fcf5ef2aSThomas Huth TCGv t0; 3460fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3461fcf5ef2aSThomas Huth 3462fcf5ef2aSThomas Huth if (ctx->le_mode) { 3463fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3464fcf5ef2aSThomas Huth return; 3465fcf5ef2aSThomas Huth } 3466fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3467fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3468fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3469fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3470fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3471fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3472fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3473fcf5ef2aSThomas Huth tcg_temp_free(t0); 3474fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3475fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3476fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3477fcf5ef2aSThomas Huth } 3478fcf5ef2aSThomas Huth 3479fcf5ef2aSThomas Huth /* stswi */ 3480fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3481fcf5ef2aSThomas Huth { 3482fcf5ef2aSThomas Huth TCGv t0; 3483fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3484fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3485fcf5ef2aSThomas Huth 3486fcf5ef2aSThomas Huth if (ctx->le_mode) { 3487fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3488fcf5ef2aSThomas Huth return; 3489fcf5ef2aSThomas Huth } 3490fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3491fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3492fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3493efe843d8SDavid Gibson if (nb == 0) { 3494fcf5ef2aSThomas Huth nb = 32; 3495efe843d8SDavid Gibson } 3496fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3497fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3498fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3499fcf5ef2aSThomas Huth tcg_temp_free(t0); 3500fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3501fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3502fcf5ef2aSThomas Huth } 3503fcf5ef2aSThomas Huth 3504fcf5ef2aSThomas Huth /* stswx */ 3505fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3506fcf5ef2aSThomas Huth { 3507fcf5ef2aSThomas Huth TCGv t0; 3508fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3509fcf5ef2aSThomas Huth 3510fcf5ef2aSThomas Huth if (ctx->le_mode) { 3511fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3512fcf5ef2aSThomas Huth return; 3513fcf5ef2aSThomas Huth } 3514fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3515fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3516fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3517fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3518fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3519fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3520fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3521fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3522fcf5ef2aSThomas Huth tcg_temp_free(t0); 3523fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3524fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3525fcf5ef2aSThomas Huth } 3526fcf5ef2aSThomas Huth 3527fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3528fcf5ef2aSThomas Huth /* eieio */ 3529fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3530fcf5ef2aSThomas Huth { 3531fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3532fcb830afSNicholas Piggin 3533fcb830afSNicholas Piggin /* 3534fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3535fcb830afSNicholas Piggin * operations in the set: 3536fcb830afSNicholas Piggin * - loads from CI memory. 3537fcb830afSNicholas Piggin * - stores to CI memory. 3538fcb830afSNicholas Piggin * - stores to WT memory. 3539fcb830afSNicholas Piggin * 3540fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3541fcb830afSNicholas Piggin * - stores to cacheble memory. 3542fcb830afSNicholas Piggin * 3543fcb830afSNicholas Piggin * It also serializes instructions: 3544fcb830afSNicholas Piggin * - dcbt and dcbst. 3545fcb830afSNicholas Piggin * 3546fcb830afSNicholas Piggin * It separately serializes: 3547fcb830afSNicholas Piggin * - tlbie and tlbsync. 3548fcb830afSNicholas Piggin * 3549fcb830afSNicholas Piggin * And separately serializes: 3550fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3551fcb830afSNicholas Piggin * 3552fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3553fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3554fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3555fcb830afSNicholas Piggin * serialization. 3556fcb830afSNicholas Piggin */ 3557c8fd8373SCédric Le Goater 3558c8fd8373SCédric Le Goater /* 3559c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3560c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3561c8fd8373SCédric Le Goater */ 3562c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3563c8fd8373SCédric Le Goater /* 3564c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3565c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3566c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3567c8fd8373SCédric Le Goater * complain to the user. 3568c8fd8373SCédric Le Goater */ 3569c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3570c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 35712c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3572c8fd8373SCédric Le Goater } else { 3573c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3574c8fd8373SCédric Le Goater } 3575c8fd8373SCédric Le Goater } 3576c8fd8373SCédric Le Goater 3577c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3578fcf5ef2aSThomas Huth } 3579fcf5ef2aSThomas Huth 3580fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3581fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3582fcf5ef2aSThomas Huth { 3583fcf5ef2aSThomas Huth TCGv_i32 t; 3584fcf5ef2aSThomas Huth TCGLabel *l; 3585fcf5ef2aSThomas Huth 3586fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3587fcf5ef2aSThomas Huth return; 3588fcf5ef2aSThomas Huth } 3589fcf5ef2aSThomas Huth l = gen_new_label(); 3590fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3591fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3592fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3593fcf5ef2aSThomas Huth if (global) { 3594fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3595fcf5ef2aSThomas Huth } else { 3596fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3597fcf5ef2aSThomas Huth } 3598fcf5ef2aSThomas Huth gen_set_label(l); 3599fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3600fcf5ef2aSThomas Huth } 3601fcf5ef2aSThomas Huth #else 3602fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3603fcf5ef2aSThomas Huth #endif 3604fcf5ef2aSThomas Huth 3605fcf5ef2aSThomas Huth /* isync */ 3606fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3607fcf5ef2aSThomas Huth { 3608fcf5ef2aSThomas Huth /* 3609fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3610fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3611fcf5ef2aSThomas Huth */ 3612fcf5ef2aSThomas Huth if (!ctx->pr) { 3613fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3614fcf5ef2aSThomas Huth } 36154771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3616d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3617fcf5ef2aSThomas Huth } 3618fcf5ef2aSThomas Huth 3619fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3620fcf5ef2aSThomas Huth 362114776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 36222a4e6c1bSRichard Henderson { 36232a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 36242a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 36252a4e6c1bSRichard Henderson 36262a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 36272a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 36282a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 36292a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 36302a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 36312a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 36322a4e6c1bSRichard Henderson tcg_temp_free(t0); 36332a4e6c1bSRichard Henderson } 36342a4e6c1bSRichard Henderson 3635fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3636fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3637fcf5ef2aSThomas Huth { \ 36382a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3639fcf5ef2aSThomas Huth } 3640fcf5ef2aSThomas Huth 3641fcf5ef2aSThomas Huth /* lwarx */ 3642fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3643fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3644fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3645fcf5ef2aSThomas Huth 364614776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 364720923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 364820923c1dSRichard Henderson { 364920923c1dSRichard Henderson TCGv t = tcg_temp_new(); 365020923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 365120923c1dSRichard Henderson TCGv u = tcg_temp_new(); 365220923c1dSRichard Henderson 365320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 365420923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 365520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 365620923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 365720923c1dSRichard Henderson 365820923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 365920923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 366020923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 366120923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 366220923c1dSRichard Henderson 366320923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 366420923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 366520923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 366620923c1dSRichard Henderson 366720923c1dSRichard Henderson tcg_temp_free(t); 366820923c1dSRichard Henderson tcg_temp_free(t2); 366920923c1dSRichard Henderson tcg_temp_free(u); 367020923c1dSRichard Henderson } 367120923c1dSRichard Henderson 367214776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 367320ba8504SRichard Henderson { 367420ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 367520ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 367620923c1dSRichard Henderson int rt = rD(ctx->opcode); 367720923c1dSRichard Henderson bool need_serial; 367820ba8504SRichard Henderson TCGv src, dst; 367920ba8504SRichard Henderson 368020ba8504SRichard Henderson gen_addr_register(ctx, EA); 368120923c1dSRichard Henderson dst = cpu_gpr[rt]; 368220923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 368320ba8504SRichard Henderson 368420923c1dSRichard Henderson need_serial = false; 368520ba8504SRichard Henderson memop |= MO_ALIGN; 368620ba8504SRichard Henderson switch (gpr_FC) { 368720ba8504SRichard Henderson case 0: /* Fetch and add */ 368820ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 368920ba8504SRichard Henderson break; 369020ba8504SRichard Henderson case 1: /* Fetch and xor */ 369120ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 369220ba8504SRichard Henderson break; 369320ba8504SRichard Henderson case 2: /* Fetch and or */ 369420ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 369520ba8504SRichard Henderson break; 369620ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 369720ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 369820ba8504SRichard Henderson break; 3699b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3700b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3701b8ce0f86SRichard Henderson break; 3702b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3703b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3704b8ce0f86SRichard Henderson break; 3705b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3706b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3707b8ce0f86SRichard Henderson break; 3708b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3709b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3710b8ce0f86SRichard Henderson break; 371120ba8504SRichard Henderson case 8: /* Swap */ 371220ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 371320ba8504SRichard Henderson break; 371420923c1dSRichard Henderson 371520923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 371620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 371720923c1dSRichard Henderson need_serial = true; 371820923c1dSRichard Henderson } else { 371920923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 372020923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 372120923c1dSRichard Henderson 372220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 372320923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 372420923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 372520923c1dSRichard Henderson } else { 372620923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 372720923c1dSRichard Henderson } 372820923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 372920923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 373020923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 373120923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 373220923c1dSRichard Henderson 373320923c1dSRichard Henderson tcg_temp_free(t0); 373420923c1dSRichard Henderson tcg_temp_free(t1); 373520923c1dSRichard Henderson } 373620ba8504SRichard Henderson break; 373720923c1dSRichard Henderson 373820923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 373920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374020923c1dSRichard Henderson need_serial = true; 374120923c1dSRichard Henderson } else { 374220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 374320923c1dSRichard Henderson } 374420923c1dSRichard Henderson break; 374520923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 374620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374720923c1dSRichard Henderson need_serial = true; 374820923c1dSRichard Henderson } else { 374920923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 375020923c1dSRichard Henderson } 375120923c1dSRichard Henderson break; 375220923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 375320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 375420923c1dSRichard Henderson need_serial = true; 375520923c1dSRichard Henderson } else { 375620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 375720923c1dSRichard Henderson } 375820923c1dSRichard Henderson break; 375920923c1dSRichard Henderson 376020ba8504SRichard Henderson default: 376120ba8504SRichard Henderson /* invoke data storage error handler */ 376220ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 376320ba8504SRichard Henderson } 376420ba8504SRichard Henderson tcg_temp_free(EA); 376520923c1dSRichard Henderson 376620923c1dSRichard Henderson if (need_serial) { 376720923c1dSRichard Henderson /* Restart with exclusive lock. */ 376820923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 376920923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 377020923c1dSRichard Henderson } 3771a68a6146SBalamuruhan S } 3772a68a6146SBalamuruhan S 377320ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 377420ba8504SRichard Henderson { 377520ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 377620ba8504SRichard Henderson } 377720ba8504SRichard Henderson 377820ba8504SRichard Henderson #ifdef TARGET_PPC64 377920ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 378020ba8504SRichard Henderson { 3781fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 378220ba8504SRichard Henderson } 3783a68a6146SBalamuruhan S #endif 3784a68a6146SBalamuruhan S 378514776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 37869deb041cSRichard Henderson { 37879deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 37889deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 37899deb041cSRichard Henderson TCGv src, discard; 37909deb041cSRichard Henderson 37919deb041cSRichard Henderson gen_addr_register(ctx, EA); 37929deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 37939deb041cSRichard Henderson discard = tcg_temp_new(); 37949deb041cSRichard Henderson 37959deb041cSRichard Henderson memop |= MO_ALIGN; 37969deb041cSRichard Henderson switch (gpr_FC) { 37979deb041cSRichard Henderson case 0: /* add and Store */ 37989deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37999deb041cSRichard Henderson break; 38009deb041cSRichard Henderson case 1: /* xor and Store */ 38019deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38029deb041cSRichard Henderson break; 38039deb041cSRichard Henderson case 2: /* Or and Store */ 38049deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38059deb041cSRichard Henderson break; 38069deb041cSRichard Henderson case 3: /* 'and' and Store */ 38079deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38089deb041cSRichard Henderson break; 38099deb041cSRichard Henderson case 4: /* Store max unsigned */ 3810b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3811b8ce0f86SRichard Henderson break; 38129deb041cSRichard Henderson case 5: /* Store max signed */ 3813b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3814b8ce0f86SRichard Henderson break; 38159deb041cSRichard Henderson case 6: /* Store min unsigned */ 3816b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3817b8ce0f86SRichard Henderson break; 38189deb041cSRichard Henderson case 7: /* Store min signed */ 3819b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3820b8ce0f86SRichard Henderson break; 38219deb041cSRichard Henderson case 24: /* Store twin */ 38227fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 38237fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 38247fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 38257fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 38267fbc2b20SRichard Henderson } else { 38277fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 38287fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 38297fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 38307fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 38317fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 38327fbc2b20SRichard Henderson 38337fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 38347fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 38357fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 38367fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 38377fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 38387fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 38397fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 38407fbc2b20SRichard Henderson 38417fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 38427fbc2b20SRichard Henderson tcg_temp_free(s2); 38437fbc2b20SRichard Henderson tcg_temp_free(s); 38447fbc2b20SRichard Henderson tcg_temp_free(t2); 38457fbc2b20SRichard Henderson tcg_temp_free(t); 38467fbc2b20SRichard Henderson } 38479deb041cSRichard Henderson break; 38489deb041cSRichard Henderson default: 38499deb041cSRichard Henderson /* invoke data storage error handler */ 38509deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 38519deb041cSRichard Henderson } 38529deb041cSRichard Henderson tcg_temp_free(discard); 38539deb041cSRichard Henderson tcg_temp_free(EA); 3854a3401188SBalamuruhan S } 3855a3401188SBalamuruhan S 38569deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 38579deb041cSRichard Henderson { 38589deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 38599deb041cSRichard Henderson } 38609deb041cSRichard Henderson 38619deb041cSRichard Henderson #ifdef TARGET_PPC64 38629deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 38639deb041cSRichard Henderson { 3864fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 38659deb041cSRichard Henderson } 3866a3401188SBalamuruhan S #endif 3867a3401188SBalamuruhan S 386814776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3869fcf5ef2aSThomas Huth { 3870253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3871253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3872d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3873d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3874fcf5ef2aSThomas Huth 3875d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3876d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3877d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3878d8b86898SRichard Henderson tcg_temp_free(t0); 3879253ce7b2SNikunj A Dadhania 3880253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3881253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3882253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3883253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3884253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3885253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3886253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3887253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3888253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3889253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3890253ce7b2SNikunj A Dadhania 3891fcf5ef2aSThomas Huth gen_set_label(l1); 38924771df23SNikunj A Dadhania 3893efe843d8SDavid Gibson /* 3894efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3895efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3896efe843d8SDavid Gibson */ 38974771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3898253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3899253ce7b2SNikunj A Dadhania 3900253ce7b2SNikunj A Dadhania gen_set_label(l2); 3901fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3902fcf5ef2aSThomas Huth } 3903fcf5ef2aSThomas Huth 3904fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3905fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3906fcf5ef2aSThomas Huth { \ 3907d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3908fcf5ef2aSThomas Huth } 3909fcf5ef2aSThomas Huth 3910fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3911fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3912fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3913fcf5ef2aSThomas Huth 3914fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3915fcf5ef2aSThomas Huth /* ldarx */ 3916fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3917fcf5ef2aSThomas Huth /* stdcx. */ 3918fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3919fcf5ef2aSThomas Huth 3920fcf5ef2aSThomas Huth /* lqarx */ 3921fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3922fcf5ef2aSThomas Huth { 3923fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 392494bf2658SRichard Henderson TCGv EA, hi, lo; 3925fcf5ef2aSThomas Huth 3926fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3927fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3928fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3929fcf5ef2aSThomas Huth return; 3930fcf5ef2aSThomas Huth } 3931fcf5ef2aSThomas Huth 3932fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 393394bf2658SRichard Henderson EA = tcg_temp_new(); 3934fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 393594bf2658SRichard Henderson 393694bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 393794bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 393894bf2658SRichard Henderson hi = cpu_gpr[rd]; 393994bf2658SRichard Henderson 394094bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3941f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 394294bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 394394bf2658SRichard Henderson if (ctx->le_mode) { 394468e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 394594bf2658SRichard Henderson ctx->mem_idx)); 394694bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3947fcf5ef2aSThomas Huth } else { 394868e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 394994bf2658SRichard Henderson ctx->mem_idx)); 395094bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3951fcf5ef2aSThomas Huth } 395294bf2658SRichard Henderson tcg_temp_free_i32(oi); 395394bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3954f34ec0f6SRichard Henderson } else { 395594bf2658SRichard Henderson /* Restart with exclusive lock. */ 395694bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 395794bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 395894bf2658SRichard Henderson tcg_temp_free(EA); 395994bf2658SRichard Henderson return; 3960f34ec0f6SRichard Henderson } 396194bf2658SRichard Henderson } else if (ctx->le_mode) { 3962fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEUQ | MO_ALIGN_16); 3963fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3964fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3965fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEUQ); 396694bf2658SRichard Henderson } else { 3967fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEUQ | MO_ALIGN_16); 396894bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 396994bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3970fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ); 397194bf2658SRichard Henderson } 3972fcf5ef2aSThomas Huth tcg_temp_free(EA); 397394bf2658SRichard Henderson 397494bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 397594bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3976fcf5ef2aSThomas Huth } 3977fcf5ef2aSThomas Huth 3978fcf5ef2aSThomas Huth /* stqcx. */ 3979fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3980fcf5ef2aSThomas Huth { 39814a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 39824a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3983fcf5ef2aSThomas Huth 39844a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3985fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3986fcf5ef2aSThomas Huth return; 3987fcf5ef2aSThomas Huth } 39884a9b3c5dSRichard Henderson 3989fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 39904a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3991fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3992fcf5ef2aSThomas Huth 39934a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 39944a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 39954a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3996fcf5ef2aSThomas Huth 39974a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3998f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 399968e33d86SRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 40004a9b3c5dSRichard Henderson if (ctx->le_mode) { 4001f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4002f34ec0f6SRichard Henderson EA, lo, hi, oi); 4003fcf5ef2aSThomas Huth } else { 4004f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4005f34ec0f6SRichard Henderson EA, lo, hi, oi); 4006fcf5ef2aSThomas Huth } 4007f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4008f34ec0f6SRichard Henderson } else { 40094a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 40104a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 40114a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4012f34ec0f6SRichard Henderson } 4013fcf5ef2aSThomas Huth tcg_temp_free(EA); 40144a9b3c5dSRichard Henderson } else { 40154a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 40164a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 40174a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 40184a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4019fcf5ef2aSThomas Huth 40204a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 40214a9b3c5dSRichard Henderson tcg_temp_free(EA); 40224a9b3c5dSRichard Henderson 40234a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 40244a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40254a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 40264a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 40274a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40284a9b3c5dSRichard Henderson 40294a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40304a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 40314a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40324a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 40334a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 40344a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40354a9b3c5dSRichard Henderson 40364a9b3c5dSRichard Henderson /* Success */ 40374a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 40384a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40394a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 40404a9b3c5dSRichard Henderson 40414a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40424a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 40434a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 40444a9b3c5dSRichard Henderson 40454a9b3c5dSRichard Henderson gen_set_label(lab_fail); 40464a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40474a9b3c5dSRichard Henderson 40484a9b3c5dSRichard Henderson gen_set_label(lab_over); 40494a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 40504a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 40514a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 40524a9b3c5dSRichard Henderson } 40534a9b3c5dSRichard Henderson } 4054fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4055fcf5ef2aSThomas Huth 4056fcf5ef2aSThomas Huth /* sync */ 4057fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4058fcf5ef2aSThomas Huth { 405903abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 4060fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4061fcf5ef2aSThomas Huth 406203abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 406303abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 406403abfd90SNicholas Piggin } 406503abfd90SNicholas Piggin 4066fcf5ef2aSThomas Huth /* 4067fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4068fcf5ef2aSThomas Huth * 4069fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4070fcf5ef2aSThomas Huth * 4071fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4072fcf5ef2aSThomas Huth * check MSR_PR as well. 4073fcf5ef2aSThomas Huth */ 4074fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4075fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4076fcf5ef2aSThomas Huth } 407703abfd90SNicholas Piggin 407803abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 4079fcf5ef2aSThomas Huth } 4080fcf5ef2aSThomas Huth 4081fcf5ef2aSThomas Huth /* wait */ 4082fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4083fcf5ef2aSThomas Huth { 40840c9717ffSNicholas Piggin uint32_t wc; 40850c9717ffSNicholas Piggin 40860c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 40870c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 40880c9717ffSNicholas Piggin 40890c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 40900c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 40910c9717ffSNicholas Piggin wc = WC(ctx->opcode); 40920c9717ffSNicholas Piggin } else { 40930c9717ffSNicholas Piggin wc = 0; 40940c9717ffSNicholas Piggin } 40950c9717ffSNicholas Piggin 40960c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 40970c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 40980c9717ffSNicholas Piggin wc = WC(ctx->opcode); 40990c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 41000c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 41010c9717ffSNicholas Piggin 41020c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 41030c9717ffSNicholas Piggin if (wc == 3) { 41040c9717ffSNicholas Piggin gen_invalid(ctx); 41050c9717ffSNicholas Piggin return; 41060c9717ffSNicholas Piggin } 41070c9717ffSNicholas Piggin 41080c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 41090c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 41100c9717ffSNicholas Piggin gen_invalid(ctx); 41110c9717ffSNicholas Piggin return; 41120c9717ffSNicholas Piggin } 41130c9717ffSNicholas Piggin 41140c9717ffSNicholas Piggin } else { /* ISA300 */ 41150c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 41160c9717ffSNicholas Piggin if (wc > 0) { 41170c9717ffSNicholas Piggin gen_invalid(ctx); 41180c9717ffSNicholas Piggin return; 41190c9717ffSNicholas Piggin } 41200c9717ffSNicholas Piggin } 41210c9717ffSNicholas Piggin 41220c9717ffSNicholas Piggin } else { 41230c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 41240c9717ffSNicholas Piggin gen_invalid(ctx); 41250c9717ffSNicholas Piggin return; 41260c9717ffSNicholas Piggin } 41270c9717ffSNicholas Piggin 41280c9717ffSNicholas Piggin /* 41290c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 41300c9717ffSNicholas Piggin * to occur. 41310c9717ffSNicholas Piggin */ 41320c9717ffSNicholas Piggin if (wc == 0) { 4133fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4134fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4135fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4136fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4137fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4138b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4139fcf5ef2aSThomas Huth } 4140fcf5ef2aSThomas Huth 41410c9717ffSNicholas Piggin /* 41420c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 41430c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 41440c9717ffSNicholas Piggin * 41450c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 41460c9717ffSNicholas Piggin * no-ops. 41470c9717ffSNicholas Piggin * 41480c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 41490c9717ffSNicholas Piggin * 41500c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 41510c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 41520c9717ffSNicholas Piggin * 41530c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 41540c9717ffSNicholas Piggin * 41550c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 41560c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 41570c9717ffSNicholas Piggin * can be implemented as a no-op. 41580c9717ffSNicholas Piggin * 41590c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 41600c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 41610c9717ffSNicholas Piggin * no-op. 41620c9717ffSNicholas Piggin * 41630c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 41640c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 41650c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 41660c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 41670c9717ffSNicholas Piggin * (if suboptimal). 41680c9717ffSNicholas Piggin */ 41690c9717ffSNicholas Piggin } 41700c9717ffSNicholas Piggin 4171fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4172fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4173fcf5ef2aSThomas Huth { 4174fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41759f0cf041SMatheus Ferst GEN_PRIV(ctx); 4176fcf5ef2aSThomas Huth #else 4177fcf5ef2aSThomas Huth TCGv_i32 t; 4178fcf5ef2aSThomas Huth 41799f0cf041SMatheus Ferst CHK_HV(ctx); 4180fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4181fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4182fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4183154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4184154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4185fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4186fcf5ef2aSThomas Huth } 4187fcf5ef2aSThomas Huth 4188fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4189fcf5ef2aSThomas Huth { 4190fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41919f0cf041SMatheus Ferst GEN_PRIV(ctx); 4192fcf5ef2aSThomas Huth #else 4193fcf5ef2aSThomas Huth TCGv_i32 t; 4194fcf5ef2aSThomas Huth 41959f0cf041SMatheus Ferst CHK_HV(ctx); 4196fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4197fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4198fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4199154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4200154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4201fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4202fcf5ef2aSThomas Huth } 4203fcf5ef2aSThomas Huth 4204cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4205cdee0e72SNikunj A Dadhania { 420621c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 42079f0cf041SMatheus Ferst GEN_PRIV(ctx); 420821c0d66aSBenjamin Herrenschmidt #else 420921c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 421021c0d66aSBenjamin Herrenschmidt 42119f0cf041SMatheus Ferst CHK_HV(ctx); 421221c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 421321c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 421421c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 421521c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 421621c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 421721c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4218cdee0e72SNikunj A Dadhania } 4219cdee0e72SNikunj A Dadhania 4220fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4221fcf5ef2aSThomas Huth { 4222fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42239f0cf041SMatheus Ferst GEN_PRIV(ctx); 4224fcf5ef2aSThomas Huth #else 4225fcf5ef2aSThomas Huth TCGv_i32 t; 4226fcf5ef2aSThomas Huth 42279f0cf041SMatheus Ferst CHK_HV(ctx); 4228fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4229fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4230fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4231154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4232154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4233fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4234fcf5ef2aSThomas Huth } 4235fcf5ef2aSThomas Huth 4236fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4237fcf5ef2aSThomas Huth { 4238fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42399f0cf041SMatheus Ferst GEN_PRIV(ctx); 4240fcf5ef2aSThomas Huth #else 4241fcf5ef2aSThomas Huth TCGv_i32 t; 4242fcf5ef2aSThomas Huth 42439f0cf041SMatheus Ferst CHK_HV(ctx); 4244fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4245fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4246fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4247154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4248154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4249fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4250fcf5ef2aSThomas Huth } 4251fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4252fcf5ef2aSThomas Huth 4253fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4254fcf5ef2aSThomas Huth { 4255fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4256efe843d8SDavid Gibson if (ctx->has_cfar) { 4257fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4258efe843d8SDavid Gibson } 4259fcf5ef2aSThomas Huth #endif 4260fcf5ef2aSThomas Huth } 4261fcf5ef2aSThomas Huth 426246d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 426346d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 426446d396bdSDaniel Henrique Barboza { 426546d396bdSDaniel Henrique Barboza /* 426646d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 426746d396bdSDaniel Henrique Barboza * instructions. 426846d396bdSDaniel Henrique Barboza */ 426946d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 427046d396bdSDaniel Henrique Barboza return; 427146d396bdSDaniel Henrique Barboza } 427246d396bdSDaniel Henrique Barboza 427346d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 427446d396bdSDaniel Henrique Barboza /* 427546d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 427646d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 427746d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 427846d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 427946d396bdSDaniel Henrique Barboza */ 428046d396bdSDaniel Henrique Barboza gen_icount_io_start(ctx); 428146d396bdSDaniel Henrique Barboza 428246d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 428346d396bdSDaniel Henrique Barboza #else 428446d396bdSDaniel Henrique Barboza /* 428546d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 428646d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 428746d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 428846d396bdSDaniel Henrique Barboza */ 428946d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 429046d396bdSDaniel Henrique Barboza 429146d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 429246d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 429346d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 429446d396bdSDaniel Henrique Barboza 429546d396bdSDaniel Henrique Barboza tcg_temp_free(t0); 429646d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 429746d396bdSDaniel Henrique Barboza } 429846d396bdSDaniel Henrique Barboza #else 429946d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 430046d396bdSDaniel Henrique Barboza { 430146d396bdSDaniel Henrique Barboza return; 430246d396bdSDaniel Henrique Barboza } 430346d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 430446d396bdSDaniel Henrique Barboza 4305fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4306fcf5ef2aSThomas Huth { 43076e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4308fcf5ef2aSThomas Huth } 4309fcf5ef2aSThomas Huth 43100e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 43110e3bf489SRoman Kapl { 43129498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 43130e3bf489SRoman Kapl gen_debug_exception(ctx); 43140e3bf489SRoman Kapl } else { 431546d396bdSDaniel Henrique Barboza /* 431646d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 431746d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 431846d396bdSDaniel Henrique Barboza */ 431946d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 432046d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 432146d396bdSDaniel Henrique Barboza } 432246d396bdSDaniel Henrique Barboza 43230e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 43240e3bf489SRoman Kapl } 43250e3bf489SRoman Kapl } 43260e3bf489SRoman Kapl 4327fcf5ef2aSThomas Huth /*** Branch ***/ 4328c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4329fcf5ef2aSThomas Huth { 4330fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4331fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4332fcf5ef2aSThomas Huth } 4333fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 433446d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4335fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4336fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 433707ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4338fcf5ef2aSThomas Huth } else { 4339fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 43400e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4341fcf5ef2aSThomas Huth } 4342fcf5ef2aSThomas Huth } 4343fcf5ef2aSThomas Huth 4344fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4345fcf5ef2aSThomas Huth { 4346fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4347fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4348fcf5ef2aSThomas Huth } 4349fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4350fcf5ef2aSThomas Huth } 4351fcf5ef2aSThomas Huth 4352fcf5ef2aSThomas Huth /* b ba bl bla */ 4353fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4354fcf5ef2aSThomas Huth { 4355fcf5ef2aSThomas Huth target_ulong li, target; 4356fcf5ef2aSThomas Huth 4357fcf5ef2aSThomas Huth /* sign extend LI */ 4358fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4359fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4360fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43612c2bcb1bSRichard Henderson target = ctx->cia + li; 4362fcf5ef2aSThomas Huth } else { 4363fcf5ef2aSThomas Huth target = li; 4364fcf5ef2aSThomas Huth } 4365fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4366b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4367fcf5ef2aSThomas Huth } 43682c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4369fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 43706086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4371fcf5ef2aSThomas Huth } 4372fcf5ef2aSThomas Huth 4373fcf5ef2aSThomas Huth #define BCOND_IM 0 4374fcf5ef2aSThomas Huth #define BCOND_LR 1 4375fcf5ef2aSThomas Huth #define BCOND_CTR 2 4376fcf5ef2aSThomas Huth #define BCOND_TAR 3 4377fcf5ef2aSThomas Huth 4378c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4379fcf5ef2aSThomas Huth { 4380fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4381fcf5ef2aSThomas Huth TCGLabel *l1; 4382fcf5ef2aSThomas Huth TCGv target; 43830e3bf489SRoman Kapl 4384fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4385fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4386efe843d8SDavid Gibson if (type == BCOND_CTR) { 4387fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4388efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4389fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4390efe843d8SDavid Gibson } else { 4391fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4392efe843d8SDavid Gibson } 4393fcf5ef2aSThomas Huth } else { 4394f764718dSRichard Henderson target = NULL; 4395fcf5ef2aSThomas Huth } 4396efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4397b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4398efe843d8SDavid Gibson } 4399fcf5ef2aSThomas Huth l1 = gen_new_label(); 4400fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4401fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4402fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4403fa200c95SGreg Kurz 4404fa200c95SGreg Kurz if (type == BCOND_CTR) { 4405fa200c95SGreg Kurz /* 4406fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4407fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4408fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 440915d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 441015d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 441115d68c5eSGreg Kurz * it basically useless and thus never used in real code. 441215d68c5eSGreg Kurz * 441315d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 441415d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 441515d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 441615d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 441715d68c5eSGreg Kurz * doing anything else harmful. 4418fa200c95SGreg Kurz */ 4419d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4420fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 44219acc95cdSGreg Kurz tcg_temp_free(temp); 44229acc95cdSGreg Kurz tcg_temp_free(target); 4423fcf5ef2aSThomas Huth return; 4424fcf5ef2aSThomas Huth } 4425fa200c95SGreg Kurz 4426fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4427fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4428fa200c95SGreg Kurz } else { 4429fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4430fa200c95SGreg Kurz } 4431fa200c95SGreg Kurz if (bo & 0x2) { 4432fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4433fa200c95SGreg Kurz } else { 4434fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4435fa200c95SGreg Kurz } 4436fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4437fa200c95SGreg Kurz } else { 4438fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4439fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4440fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4441fcf5ef2aSThomas Huth } else { 4442fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4443fcf5ef2aSThomas Huth } 4444fcf5ef2aSThomas Huth if (bo & 0x2) { 4445fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4446fcf5ef2aSThomas Huth } else { 4447fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4448fcf5ef2aSThomas Huth } 4449fa200c95SGreg Kurz } 4450fcf5ef2aSThomas Huth tcg_temp_free(temp); 4451fcf5ef2aSThomas Huth } 4452fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4453fcf5ef2aSThomas Huth /* Test CR */ 4454fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4455fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4456fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4457fcf5ef2aSThomas Huth 4458fcf5ef2aSThomas Huth if (bo & 0x8) { 4459fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4460fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4461fcf5ef2aSThomas Huth } else { 4462fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4463fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4464fcf5ef2aSThomas Huth } 4465fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4466fcf5ef2aSThomas Huth } 44672c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4468fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4469fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4470fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 44712c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4472fcf5ef2aSThomas Huth } else { 4473fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4474fcf5ef2aSThomas Huth } 4475fcf5ef2aSThomas Huth } else { 4476fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4477fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4478fcf5ef2aSThomas Huth } else { 4479fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4480fcf5ef2aSThomas Huth } 44810e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4482c4a2e3a9SRichard Henderson tcg_temp_free(target); 4483c4a2e3a9SRichard Henderson } 4484fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 44850e3bf489SRoman Kapl /* fallthrough case */ 4486fcf5ef2aSThomas Huth gen_set_label(l1); 4487b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4488fcf5ef2aSThomas Huth } 44896086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4490fcf5ef2aSThomas Huth } 4491fcf5ef2aSThomas Huth 4492fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4493fcf5ef2aSThomas Huth { 4494fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4495fcf5ef2aSThomas Huth } 4496fcf5ef2aSThomas Huth 4497fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4498fcf5ef2aSThomas Huth { 4499fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4500fcf5ef2aSThomas Huth } 4501fcf5ef2aSThomas Huth 4502fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4503fcf5ef2aSThomas Huth { 4504fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4505fcf5ef2aSThomas Huth } 4506fcf5ef2aSThomas Huth 4507fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4508fcf5ef2aSThomas Huth { 4509fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4510fcf5ef2aSThomas Huth } 4511fcf5ef2aSThomas Huth 4512fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4513fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4514fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4515fcf5ef2aSThomas Huth { \ 4516fcf5ef2aSThomas Huth uint8_t bitmask; \ 4517fcf5ef2aSThomas Huth int sh; \ 4518fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4519fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4520fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4521fcf5ef2aSThomas Huth if (sh > 0) \ 4522fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4523fcf5ef2aSThomas Huth else if (sh < 0) \ 4524fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4525fcf5ef2aSThomas Huth else \ 4526fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4527fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4528fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4529fcf5ef2aSThomas Huth if (sh > 0) \ 4530fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4531fcf5ef2aSThomas Huth else if (sh < 0) \ 4532fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4533fcf5ef2aSThomas Huth else \ 4534fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4535fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4536fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4537fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4538fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4539fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4540fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4541fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4542fcf5ef2aSThomas Huth } 4543fcf5ef2aSThomas Huth 4544fcf5ef2aSThomas Huth /* crand */ 4545fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4546fcf5ef2aSThomas Huth /* crandc */ 4547fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4548fcf5ef2aSThomas Huth /* creqv */ 4549fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4550fcf5ef2aSThomas Huth /* crnand */ 4551fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4552fcf5ef2aSThomas Huth /* crnor */ 4553fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4554fcf5ef2aSThomas Huth /* cror */ 4555fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4556fcf5ef2aSThomas Huth /* crorc */ 4557fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4558fcf5ef2aSThomas Huth /* crxor */ 4559fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4560fcf5ef2aSThomas Huth 4561fcf5ef2aSThomas Huth /* mcrf */ 4562fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4563fcf5ef2aSThomas Huth { 4564fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4565fcf5ef2aSThomas Huth } 4566fcf5ef2aSThomas Huth 4567fcf5ef2aSThomas Huth /*** System linkage ***/ 4568fcf5ef2aSThomas Huth 4569fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4570fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4571fcf5ef2aSThomas Huth { 4572fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 45739f0cf041SMatheus Ferst GEN_PRIV(ctx); 4574fcf5ef2aSThomas Huth #else 4575efe843d8SDavid Gibson /* 4576efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4577fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4578fcf5ef2aSThomas Huth */ 4579d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4580fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4581fcf5ef2aSThomas Huth return; 4582fcf5ef2aSThomas Huth } 4583fcf5ef2aSThomas Huth /* Restore CPU state */ 45849f0cf041SMatheus Ferst CHK_SV(ctx); 4585f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45862c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4587fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 458859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4589fcf5ef2aSThomas Huth #endif 4590fcf5ef2aSThomas Huth } 4591fcf5ef2aSThomas Huth 4592fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4593fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4594fcf5ef2aSThomas Huth { 4595fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 45969f0cf041SMatheus Ferst GEN_PRIV(ctx); 4597fcf5ef2aSThomas Huth #else 4598fcf5ef2aSThomas Huth /* Restore CPU state */ 45999f0cf041SMatheus Ferst CHK_SV(ctx); 4600f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46012c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4602fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 460359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4604fcf5ef2aSThomas Huth #endif 4605fcf5ef2aSThomas Huth } 4606fcf5ef2aSThomas Huth 46073c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46083c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 46093c89b8d6SNicholas Piggin { 46103c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 46119f0cf041SMatheus Ferst GEN_PRIV(ctx); 46123c89b8d6SNicholas Piggin #else 46133c89b8d6SNicholas Piggin /* Restore CPU state */ 46149f0cf041SMatheus Ferst CHK_SV(ctx); 4615f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46162c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 46173c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 461859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 46193c89b8d6SNicholas Piggin #endif 46203c89b8d6SNicholas Piggin } 46213c89b8d6SNicholas Piggin #endif 46223c89b8d6SNicholas Piggin 4623fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4624fcf5ef2aSThomas Huth { 4625fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 46269f0cf041SMatheus Ferst GEN_PRIV(ctx); 4627fcf5ef2aSThomas Huth #else 4628fcf5ef2aSThomas Huth /* Restore CPU state */ 46299f0cf041SMatheus Ferst CHK_HV(ctx); 4630fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 463159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4632fcf5ef2aSThomas Huth #endif 4633fcf5ef2aSThomas Huth } 4634fcf5ef2aSThomas Huth #endif 4635fcf5ef2aSThomas Huth 4636fcf5ef2aSThomas Huth /* sc */ 4637fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4638fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4639fcf5ef2aSThomas Huth #else 4640fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 46413c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4642fcf5ef2aSThomas Huth #endif 4643fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4644fcf5ef2aSThomas Huth { 4645fcf5ef2aSThomas Huth uint32_t lev; 4646fcf5ef2aSThomas Huth 4647fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4648fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4649fcf5ef2aSThomas Huth } 4650fcf5ef2aSThomas Huth 46513c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 46523c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46533c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 46543c89b8d6SNicholas Piggin { 4655f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 46563c89b8d6SNicholas Piggin 4657f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 46582c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4659f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 46603c89b8d6SNicholas Piggin 46617a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 46623c89b8d6SNicholas Piggin } 46633c89b8d6SNicholas Piggin #endif 46643c89b8d6SNicholas Piggin #endif 46653c89b8d6SNicholas Piggin 4666fcf5ef2aSThomas Huth /*** Trap ***/ 4667fcf5ef2aSThomas Huth 4668fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4669fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4670fcf5ef2aSThomas Huth { 4671fcf5ef2aSThomas Huth /* Trap never */ 4672fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4673fcf5ef2aSThomas Huth return true; 4674fcf5ef2aSThomas Huth } 4675fcf5ef2aSThomas Huth /* Trap always */ 4676fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4677fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4678fcf5ef2aSThomas Huth return true; 4679fcf5ef2aSThomas Huth } 4680fcf5ef2aSThomas Huth return false; 4681fcf5ef2aSThomas Huth } 4682fcf5ef2aSThomas Huth 4683fcf5ef2aSThomas Huth /* tw */ 4684fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4685fcf5ef2aSThomas Huth { 4686fcf5ef2aSThomas Huth TCGv_i32 t0; 4687fcf5ef2aSThomas Huth 4688fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4689fcf5ef2aSThomas Huth return; 4690fcf5ef2aSThomas Huth } 4691fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4692fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4693fcf5ef2aSThomas Huth t0); 4694fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4695fcf5ef2aSThomas Huth } 4696fcf5ef2aSThomas Huth 4697fcf5ef2aSThomas Huth /* twi */ 4698fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4699fcf5ef2aSThomas Huth { 4700fcf5ef2aSThomas Huth TCGv t0; 4701fcf5ef2aSThomas Huth TCGv_i32 t1; 4702fcf5ef2aSThomas Huth 4703fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4704fcf5ef2aSThomas Huth return; 4705fcf5ef2aSThomas Huth } 4706fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4707fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4708fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4709fcf5ef2aSThomas Huth tcg_temp_free(t0); 4710fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4711fcf5ef2aSThomas Huth } 4712fcf5ef2aSThomas Huth 4713fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4714fcf5ef2aSThomas Huth /* td */ 4715fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4716fcf5ef2aSThomas Huth { 4717fcf5ef2aSThomas Huth TCGv_i32 t0; 4718fcf5ef2aSThomas Huth 4719fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4720fcf5ef2aSThomas Huth return; 4721fcf5ef2aSThomas Huth } 4722fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4723fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4724fcf5ef2aSThomas Huth t0); 4725fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4726fcf5ef2aSThomas Huth } 4727fcf5ef2aSThomas Huth 4728fcf5ef2aSThomas Huth /* tdi */ 4729fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4730fcf5ef2aSThomas Huth { 4731fcf5ef2aSThomas Huth TCGv t0; 4732fcf5ef2aSThomas Huth TCGv_i32 t1; 4733fcf5ef2aSThomas Huth 4734fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4735fcf5ef2aSThomas Huth return; 4736fcf5ef2aSThomas Huth } 4737fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4738fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4739fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4740fcf5ef2aSThomas Huth tcg_temp_free(t0); 4741fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4742fcf5ef2aSThomas Huth } 4743fcf5ef2aSThomas Huth #endif 4744fcf5ef2aSThomas Huth 4745fcf5ef2aSThomas Huth /*** Processor control ***/ 4746fcf5ef2aSThomas Huth 4747fcf5ef2aSThomas Huth /* mcrxr */ 4748fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4749fcf5ef2aSThomas Huth { 4750fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4751fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4752fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4753fcf5ef2aSThomas Huth 4754fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4755fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4756fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4757fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4758fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4759fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4760fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4761fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4762fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4763fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4764fcf5ef2aSThomas Huth 4765fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4766fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4767fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4768fcf5ef2aSThomas Huth } 4769fcf5ef2aSThomas Huth 4770b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4771b63d0434SNikunj A Dadhania /* mcrxrx */ 4772b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4773b63d0434SNikunj A Dadhania { 4774b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4775b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4776b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4777b63d0434SNikunj A Dadhania 4778b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4779b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4780b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4781b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4782b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4783b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4784b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4785b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4786b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4787b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4788b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4789b63d0434SNikunj A Dadhania } 4790b63d0434SNikunj A Dadhania #endif 4791b63d0434SNikunj A Dadhania 4792fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4793fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4794fcf5ef2aSThomas Huth { 4795fcf5ef2aSThomas Huth uint32_t crm, crn; 4796fcf5ef2aSThomas Huth 4797fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4798fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4799fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4800fcf5ef2aSThomas Huth crn = ctz32(crm); 4801fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4802fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4803fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4804fcf5ef2aSThomas Huth } 4805fcf5ef2aSThomas Huth } else { 4806fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4807fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4808fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4809fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4810fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4811fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4812fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4813fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4814fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4815fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4816fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4817fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4818fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4819fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4820fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4821fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4822fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4823fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4824fcf5ef2aSThomas Huth } 4825fcf5ef2aSThomas Huth } 4826fcf5ef2aSThomas Huth 4827fcf5ef2aSThomas Huth /* mfmsr */ 4828fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4829fcf5ef2aSThomas Huth { 48309f0cf041SMatheus Ferst CHK_SV(ctx); 4831fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4832fcf5ef2aSThomas Huth } 4833fcf5ef2aSThomas Huth 4834fcf5ef2aSThomas Huth /* mfspr */ 4835fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4836fcf5ef2aSThomas Huth { 4837fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4838fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4839fcf5ef2aSThomas Huth 4840fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4841fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4842fcf5ef2aSThomas Huth #else 4843fcf5ef2aSThomas Huth if (ctx->pr) { 4844fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4845fcf5ef2aSThomas Huth } else if (ctx->hv) { 4846fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4847fcf5ef2aSThomas Huth } else { 4848fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4849fcf5ef2aSThomas Huth } 4850fcf5ef2aSThomas Huth #endif 4851fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4852fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4853fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4854fcf5ef2aSThomas Huth } else { 4855fcf5ef2aSThomas Huth /* Privilege exception */ 4856efe843d8SDavid Gibson /* 4857efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4858fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4859fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4860fcf5ef2aSThomas Huth */ 4861fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 486231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 486331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48642c2bcb1bSRichard Henderson ctx->cia); 4865fcf5ef2aSThomas Huth } 4866fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4867fcf5ef2aSThomas Huth } 4868fcf5ef2aSThomas Huth } else { 4869fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4870fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4871fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4872fcf5ef2aSThomas Huth /* This is a nop */ 4873fcf5ef2aSThomas Huth return; 4874fcf5ef2aSThomas Huth } 4875fcf5ef2aSThomas Huth /* Not defined */ 487631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 487731085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 48782c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4879fcf5ef2aSThomas Huth 4880efe843d8SDavid Gibson /* 4881efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4882efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4883fcf5ef2aSThomas Huth */ 4884fcf5ef2aSThomas Huth if (sprn & 0x10) { 4885fcf5ef2aSThomas Huth if (ctx->pr) { 48861315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4887fcf5ef2aSThomas Huth } 4888fcf5ef2aSThomas Huth } else { 4889fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 48901315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4891fcf5ef2aSThomas Huth } 4892fcf5ef2aSThomas Huth } 4893fcf5ef2aSThomas Huth } 4894fcf5ef2aSThomas Huth } 4895fcf5ef2aSThomas Huth 4896fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4897fcf5ef2aSThomas Huth { 4898fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4899fcf5ef2aSThomas Huth } 4900fcf5ef2aSThomas Huth 4901fcf5ef2aSThomas Huth /* mftb */ 4902fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4903fcf5ef2aSThomas Huth { 4904fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4905fcf5ef2aSThomas Huth } 4906fcf5ef2aSThomas Huth 4907fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4908fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4909fcf5ef2aSThomas Huth { 4910fcf5ef2aSThomas Huth uint32_t crm, crn; 4911fcf5ef2aSThomas Huth 4912fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4913fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4914fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4915fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4916fcf5ef2aSThomas Huth crn = ctz32(crm); 4917fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4918fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4919fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4920fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4921fcf5ef2aSThomas Huth } 4922fcf5ef2aSThomas Huth } else { 4923fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4924fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4925fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4926fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4927fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4928fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4929fcf5ef2aSThomas Huth } 4930fcf5ef2aSThomas Huth } 4931fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4932fcf5ef2aSThomas Huth } 4933fcf5ef2aSThomas Huth } 4934fcf5ef2aSThomas Huth 4935fcf5ef2aSThomas Huth /* mtmsr */ 4936fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4937fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4938fcf5ef2aSThomas Huth { 4939caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4940caf590ddSNicholas Piggin gen_invalid(ctx); 4941caf590ddSNicholas Piggin return; 4942caf590ddSNicholas Piggin } 4943caf590ddSNicholas Piggin 49449f0cf041SMatheus Ferst CHK_SV(ctx); 4945fcf5ef2aSThomas Huth 4946fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49476fa5726bSMatheus Ferst TCGv t0, t1; 49486fa5726bSMatheus Ferst target_ulong mask; 49496fa5726bSMatheus Ferst 49506fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49516fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49526fa5726bSMatheus Ferst 4953f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49546fa5726bSMatheus Ferst 4955fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49565ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49576fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4958fcf5ef2aSThomas Huth } else { 49596fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 49606fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 49616fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4962efe843d8SDavid Gibson /* 4963efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4964efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4965efe843d8SDavid Gibson * ppc_store_msr 4966fcf5ef2aSThomas Huth */ 4967b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4968fcf5ef2aSThomas Huth } 49696fa5726bSMatheus Ferst 49706fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 49716fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 49726fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 49736fa5726bSMatheus Ferst 49746fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 49756fa5726bSMatheus Ferst 49765ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4977d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 49786fa5726bSMatheus Ferst 49796fa5726bSMatheus Ferst tcg_temp_free(t0); 49806fa5726bSMatheus Ferst tcg_temp_free(t1); 4981fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4982fcf5ef2aSThomas Huth } 4983fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4984fcf5ef2aSThomas Huth 4985fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4986fcf5ef2aSThomas Huth { 49879f0cf041SMatheus Ferst CHK_SV(ctx); 4988fcf5ef2aSThomas Huth 4989fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49906fa5726bSMatheus Ferst TCGv t0, t1; 49916fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 49926fa5726bSMatheus Ferst 49936fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49946fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49956fa5726bSMatheus Ferst 4996f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4997fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49985ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49996fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 5000fcf5ef2aSThomas Huth } else { 50016fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 50026fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 5003fcf5ef2aSThomas Huth 5004efe843d8SDavid Gibson /* 5005efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5006efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5007efe843d8SDavid Gibson * ppc_store_msr 5008fcf5ef2aSThomas Huth */ 5009b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5010fcf5ef2aSThomas Huth } 50116fa5726bSMatheus Ferst 50126fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 50136fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 50146fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 50156fa5726bSMatheus Ferst 50166fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 50176fa5726bSMatheus Ferst 50185ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5019d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 50206fa5726bSMatheus Ferst 50216fa5726bSMatheus Ferst tcg_temp_free(t0); 50226fa5726bSMatheus Ferst tcg_temp_free(t1); 5023fcf5ef2aSThomas Huth #endif 5024fcf5ef2aSThomas Huth } 5025fcf5ef2aSThomas Huth 5026fcf5ef2aSThomas Huth /* mtspr */ 5027fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5028fcf5ef2aSThomas Huth { 5029fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5030fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5031fcf5ef2aSThomas Huth 5032fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5033fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5034fcf5ef2aSThomas Huth #else 5035fcf5ef2aSThomas Huth if (ctx->pr) { 5036fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5037fcf5ef2aSThomas Huth } else if (ctx->hv) { 5038fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5039fcf5ef2aSThomas Huth } else { 5040fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5041fcf5ef2aSThomas Huth } 5042fcf5ef2aSThomas Huth #endif 5043fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5044fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5045fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5046fcf5ef2aSThomas Huth } else { 5047fcf5ef2aSThomas Huth /* Privilege exception */ 504831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 504931085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 50502c2bcb1bSRichard Henderson ctx->cia); 5051fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5052fcf5ef2aSThomas Huth } 5053fcf5ef2aSThomas Huth } else { 5054fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5055fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5056fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5057fcf5ef2aSThomas Huth /* This is a nop */ 5058fcf5ef2aSThomas Huth return; 5059fcf5ef2aSThomas Huth } 5060fcf5ef2aSThomas Huth 5061fcf5ef2aSThomas Huth /* Not defined */ 506231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 506331085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 50642c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5065fcf5ef2aSThomas Huth 5066fcf5ef2aSThomas Huth 5067efe843d8SDavid Gibson /* 5068efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5069efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5070fcf5ef2aSThomas Huth */ 5071fcf5ef2aSThomas Huth if (sprn & 0x10) { 5072fcf5ef2aSThomas Huth if (ctx->pr) { 50731315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5074fcf5ef2aSThomas Huth } 5075fcf5ef2aSThomas Huth } else { 5076fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 50771315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5078fcf5ef2aSThomas Huth } 5079fcf5ef2aSThomas Huth } 5080fcf5ef2aSThomas Huth } 5081fcf5ef2aSThomas Huth } 5082fcf5ef2aSThomas Huth 5083fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5084fcf5ef2aSThomas Huth /* setb */ 5085fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5086fcf5ef2aSThomas Huth { 5087fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 50886f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 50896f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5090fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5093fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5094fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5095fcf5ef2aSThomas Huth 5096fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5097fcf5ef2aSThomas Huth } 5098fcf5ef2aSThomas Huth #endif 5099fcf5ef2aSThomas Huth 5100fcf5ef2aSThomas Huth /*** Cache management ***/ 5101fcf5ef2aSThomas Huth 5102fcf5ef2aSThomas Huth /* dcbf */ 5103fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5104fcf5ef2aSThomas Huth { 5105fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5106fcf5ef2aSThomas Huth TCGv t0; 5107fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5108fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5109fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5110fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5111fcf5ef2aSThomas Huth tcg_temp_free(t0); 5112fcf5ef2aSThomas Huth } 5113fcf5ef2aSThomas Huth 511450728199SRoman Kapl /* dcbfep (external PID dcbf) */ 511550728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 511650728199SRoman Kapl { 511750728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 511850728199SRoman Kapl TCGv t0; 51199f0cf041SMatheus Ferst CHK_SV(ctx); 512050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 512150728199SRoman Kapl t0 = tcg_temp_new(); 512250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 512350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 512450728199SRoman Kapl tcg_temp_free(t0); 512550728199SRoman Kapl } 512650728199SRoman Kapl 5127fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5128fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5129fcf5ef2aSThomas Huth { 5130fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51319f0cf041SMatheus Ferst GEN_PRIV(ctx); 5132fcf5ef2aSThomas Huth #else 5133fcf5ef2aSThomas Huth TCGv EA, val; 5134fcf5ef2aSThomas Huth 51359f0cf041SMatheus Ferst CHK_SV(ctx); 5136fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5137fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5138fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5139fcf5ef2aSThomas Huth val = tcg_temp_new(); 5140fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5141fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5142fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5143fcf5ef2aSThomas Huth tcg_temp_free(val); 5144fcf5ef2aSThomas Huth tcg_temp_free(EA); 5145fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5146fcf5ef2aSThomas Huth } 5147fcf5ef2aSThomas Huth 5148fcf5ef2aSThomas Huth /* dcdst */ 5149fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5150fcf5ef2aSThomas Huth { 5151fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5152fcf5ef2aSThomas Huth TCGv t0; 5153fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5154fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5155fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5156fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5157fcf5ef2aSThomas Huth tcg_temp_free(t0); 5158fcf5ef2aSThomas Huth } 5159fcf5ef2aSThomas Huth 516050728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 516150728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 516250728199SRoman Kapl { 516350728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 516450728199SRoman Kapl TCGv t0; 516550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 516650728199SRoman Kapl t0 = tcg_temp_new(); 516750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 516850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 516950728199SRoman Kapl tcg_temp_free(t0); 517050728199SRoman Kapl } 517150728199SRoman Kapl 5172fcf5ef2aSThomas Huth /* dcbt */ 5173fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5174fcf5ef2aSThomas Huth { 5175efe843d8SDavid Gibson /* 5176efe843d8SDavid Gibson * interpreted as no-op 5177efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5178efe843d8SDavid Gibson * does not generate any exception 5179fcf5ef2aSThomas Huth */ 5180fcf5ef2aSThomas Huth } 5181fcf5ef2aSThomas Huth 518250728199SRoman Kapl /* dcbtep */ 518350728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 518450728199SRoman Kapl { 5185efe843d8SDavid Gibson /* 5186efe843d8SDavid Gibson * interpreted as no-op 5187efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5188efe843d8SDavid Gibson * does not generate any exception 518950728199SRoman Kapl */ 519050728199SRoman Kapl } 519150728199SRoman Kapl 5192fcf5ef2aSThomas Huth /* dcbtst */ 5193fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5194fcf5ef2aSThomas Huth { 5195efe843d8SDavid Gibson /* 5196efe843d8SDavid Gibson * interpreted as no-op 5197efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5198efe843d8SDavid Gibson * does not generate any exception 5199fcf5ef2aSThomas Huth */ 5200fcf5ef2aSThomas Huth } 5201fcf5ef2aSThomas Huth 520250728199SRoman Kapl /* dcbtstep */ 520350728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 520450728199SRoman Kapl { 5205efe843d8SDavid Gibson /* 5206efe843d8SDavid Gibson * interpreted as no-op 5207efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5208efe843d8SDavid Gibson * does not generate any exception 520950728199SRoman Kapl */ 521050728199SRoman Kapl } 521150728199SRoman Kapl 5212fcf5ef2aSThomas Huth /* dcbtls */ 5213fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5214fcf5ef2aSThomas Huth { 5215fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5216fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5217fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5218fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5219fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5220fcf5ef2aSThomas Huth tcg_temp_free(t0); 5221fcf5ef2aSThomas Huth } 5222fcf5ef2aSThomas Huth 5223fcf5ef2aSThomas Huth /* dcbz */ 5224fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5225fcf5ef2aSThomas Huth { 5226fcf5ef2aSThomas Huth TCGv tcgv_addr; 5227fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5228fcf5ef2aSThomas Huth 5229fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5230fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5231fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5232fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5233fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5234fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5235fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5236fcf5ef2aSThomas Huth } 5237fcf5ef2aSThomas Huth 523850728199SRoman Kapl /* dcbzep */ 523950728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 524050728199SRoman Kapl { 524150728199SRoman Kapl TCGv tcgv_addr; 524250728199SRoman Kapl TCGv_i32 tcgv_op; 524350728199SRoman Kapl 524450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 524550728199SRoman Kapl tcgv_addr = tcg_temp_new(); 524650728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 524750728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 524850728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 524950728199SRoman Kapl tcg_temp_free(tcgv_addr); 525050728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 525150728199SRoman Kapl } 525250728199SRoman Kapl 5253fcf5ef2aSThomas Huth /* dst / dstt */ 5254fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5255fcf5ef2aSThomas Huth { 5256fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5257fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5258fcf5ef2aSThomas Huth } else { 5259fcf5ef2aSThomas Huth /* interpreted as no-op */ 5260fcf5ef2aSThomas Huth } 5261fcf5ef2aSThomas Huth } 5262fcf5ef2aSThomas Huth 5263fcf5ef2aSThomas Huth /* dstst /dststt */ 5264fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5265fcf5ef2aSThomas Huth { 5266fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5267fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5268fcf5ef2aSThomas Huth } else { 5269fcf5ef2aSThomas Huth /* interpreted as no-op */ 5270fcf5ef2aSThomas Huth } 5271fcf5ef2aSThomas Huth 5272fcf5ef2aSThomas Huth } 5273fcf5ef2aSThomas Huth 5274fcf5ef2aSThomas Huth /* dss / dssall */ 5275fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5276fcf5ef2aSThomas Huth { 5277fcf5ef2aSThomas Huth /* interpreted as no-op */ 5278fcf5ef2aSThomas Huth } 5279fcf5ef2aSThomas Huth 5280fcf5ef2aSThomas Huth /* icbi */ 5281fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5282fcf5ef2aSThomas Huth { 5283fcf5ef2aSThomas Huth TCGv t0; 5284fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5285fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5286fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5287fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5288fcf5ef2aSThomas Huth tcg_temp_free(t0); 5289fcf5ef2aSThomas Huth } 5290fcf5ef2aSThomas Huth 529150728199SRoman Kapl /* icbiep */ 529250728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 529350728199SRoman Kapl { 529450728199SRoman Kapl TCGv t0; 529550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 529650728199SRoman Kapl t0 = tcg_temp_new(); 529750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 529850728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 529950728199SRoman Kapl tcg_temp_free(t0); 530050728199SRoman Kapl } 530150728199SRoman Kapl 5302fcf5ef2aSThomas Huth /* Optional: */ 5303fcf5ef2aSThomas Huth /* dcba */ 5304fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5305fcf5ef2aSThomas Huth { 5306efe843d8SDavid Gibson /* 5307efe843d8SDavid Gibson * interpreted as no-op 5308efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5309fcf5ef2aSThomas Huth * but does not generate any exception 5310fcf5ef2aSThomas Huth */ 5311fcf5ef2aSThomas Huth } 5312fcf5ef2aSThomas Huth 5313fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5314fcf5ef2aSThomas Huth /* Supervisor only: */ 5315fcf5ef2aSThomas Huth 5316fcf5ef2aSThomas Huth /* mfsr */ 5317fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5318fcf5ef2aSThomas Huth { 5319fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53209f0cf041SMatheus Ferst GEN_PRIV(ctx); 5321fcf5ef2aSThomas Huth #else 5322fcf5ef2aSThomas Huth TCGv t0; 5323fcf5ef2aSThomas Huth 53249f0cf041SMatheus Ferst CHK_SV(ctx); 5325fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5326fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5327fcf5ef2aSThomas Huth tcg_temp_free(t0); 5328fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5329fcf5ef2aSThomas Huth } 5330fcf5ef2aSThomas Huth 5331fcf5ef2aSThomas Huth /* mfsrin */ 5332fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5333fcf5ef2aSThomas Huth { 5334fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53359f0cf041SMatheus Ferst GEN_PRIV(ctx); 5336fcf5ef2aSThomas Huth #else 5337fcf5ef2aSThomas Huth TCGv t0; 5338fcf5ef2aSThomas Huth 53399f0cf041SMatheus Ferst CHK_SV(ctx); 5340fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5341e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5342fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5343fcf5ef2aSThomas Huth tcg_temp_free(t0); 5344fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5345fcf5ef2aSThomas Huth } 5346fcf5ef2aSThomas Huth 5347fcf5ef2aSThomas Huth /* mtsr */ 5348fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5349fcf5ef2aSThomas Huth { 5350fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53519f0cf041SMatheus Ferst GEN_PRIV(ctx); 5352fcf5ef2aSThomas Huth #else 5353fcf5ef2aSThomas Huth TCGv t0; 5354fcf5ef2aSThomas Huth 53559f0cf041SMatheus Ferst CHK_SV(ctx); 5356fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5357fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5358fcf5ef2aSThomas Huth tcg_temp_free(t0); 5359fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5360fcf5ef2aSThomas Huth } 5361fcf5ef2aSThomas Huth 5362fcf5ef2aSThomas Huth /* mtsrin */ 5363fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5364fcf5ef2aSThomas Huth { 5365fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53669f0cf041SMatheus Ferst GEN_PRIV(ctx); 5367fcf5ef2aSThomas Huth #else 5368fcf5ef2aSThomas Huth TCGv t0; 53699f0cf041SMatheus Ferst CHK_SV(ctx); 5370fcf5ef2aSThomas Huth 5371fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5372e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5373fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5374fcf5ef2aSThomas Huth tcg_temp_free(t0); 5375fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5376fcf5ef2aSThomas Huth } 5377fcf5ef2aSThomas Huth 5378fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5379fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5380fcf5ef2aSThomas Huth 5381fcf5ef2aSThomas Huth /* mfsr */ 5382fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5383fcf5ef2aSThomas Huth { 5384fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53859f0cf041SMatheus Ferst GEN_PRIV(ctx); 5386fcf5ef2aSThomas Huth #else 5387fcf5ef2aSThomas Huth TCGv t0; 5388fcf5ef2aSThomas Huth 53899f0cf041SMatheus Ferst CHK_SV(ctx); 5390fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5391fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5392fcf5ef2aSThomas Huth tcg_temp_free(t0); 5393fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5394fcf5ef2aSThomas Huth } 5395fcf5ef2aSThomas Huth 5396fcf5ef2aSThomas Huth /* mfsrin */ 5397fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5398fcf5ef2aSThomas Huth { 5399fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54009f0cf041SMatheus Ferst GEN_PRIV(ctx); 5401fcf5ef2aSThomas Huth #else 5402fcf5ef2aSThomas Huth TCGv t0; 5403fcf5ef2aSThomas Huth 54049f0cf041SMatheus Ferst CHK_SV(ctx); 5405fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5406e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5407fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5408fcf5ef2aSThomas Huth tcg_temp_free(t0); 5409fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5410fcf5ef2aSThomas Huth } 5411fcf5ef2aSThomas Huth 5412fcf5ef2aSThomas Huth /* mtsr */ 5413fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5414fcf5ef2aSThomas Huth { 5415fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54169f0cf041SMatheus Ferst GEN_PRIV(ctx); 5417fcf5ef2aSThomas Huth #else 5418fcf5ef2aSThomas Huth TCGv t0; 5419fcf5ef2aSThomas Huth 54209f0cf041SMatheus Ferst CHK_SV(ctx); 5421fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5422fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5423fcf5ef2aSThomas Huth tcg_temp_free(t0); 5424fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5425fcf5ef2aSThomas Huth } 5426fcf5ef2aSThomas Huth 5427fcf5ef2aSThomas Huth /* mtsrin */ 5428fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5429fcf5ef2aSThomas Huth { 5430fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54319f0cf041SMatheus Ferst GEN_PRIV(ctx); 5432fcf5ef2aSThomas Huth #else 5433fcf5ef2aSThomas Huth TCGv t0; 5434fcf5ef2aSThomas Huth 54359f0cf041SMatheus Ferst CHK_SV(ctx); 5436fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5437e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5438fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5439fcf5ef2aSThomas Huth tcg_temp_free(t0); 5440fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5441fcf5ef2aSThomas Huth } 5442fcf5ef2aSThomas Huth 5443fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5444fcf5ef2aSThomas Huth 5445fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5446fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5447fcf5ef2aSThomas Huth 5448fcf5ef2aSThomas Huth /* tlbia */ 5449fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5450fcf5ef2aSThomas Huth { 5451fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54529f0cf041SMatheus Ferst GEN_PRIV(ctx); 5453fcf5ef2aSThomas Huth #else 54549f0cf041SMatheus Ferst CHK_HV(ctx); 5455fcf5ef2aSThomas Huth 5456fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5457fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5458fcf5ef2aSThomas Huth } 5459fcf5ef2aSThomas Huth 5460fcf5ef2aSThomas Huth /* tlbsync */ 5461fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5462fcf5ef2aSThomas Huth { 5463fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5465fcf5ef2aSThomas Huth #else 546691c60f12SCédric Le Goater 546791c60f12SCédric Le Goater if (ctx->gtse) { 54689f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 546991c60f12SCédric Le Goater } else { 54709f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 547191c60f12SCédric Le Goater } 5472fcf5ef2aSThomas Huth 5473fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5474fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5475fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5476fcf5ef2aSThomas Huth } 5477fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5478fcf5ef2aSThomas Huth } 5479fcf5ef2aSThomas Huth 5480fcf5ef2aSThomas Huth /*** External control ***/ 5481fcf5ef2aSThomas Huth /* Optional: */ 5482fcf5ef2aSThomas Huth 5483fcf5ef2aSThomas Huth /* eciwx */ 5484fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5485fcf5ef2aSThomas Huth { 5486fcf5ef2aSThomas Huth TCGv t0; 5487fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5488fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5489fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5490fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5491c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5492c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5493fcf5ef2aSThomas Huth tcg_temp_free(t0); 5494fcf5ef2aSThomas Huth } 5495fcf5ef2aSThomas Huth 5496fcf5ef2aSThomas Huth /* ecowx */ 5497fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5498fcf5ef2aSThomas Huth { 5499fcf5ef2aSThomas Huth TCGv t0; 5500fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5501fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5502fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5503fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5504c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5505c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5506fcf5ef2aSThomas Huth tcg_temp_free(t0); 5507fcf5ef2aSThomas Huth } 5508fcf5ef2aSThomas Huth 5509fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5510fcf5ef2aSThomas Huth 5511fcf5ef2aSThomas Huth /* tlbld */ 5512fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5513fcf5ef2aSThomas Huth { 5514fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55159f0cf041SMatheus Ferst GEN_PRIV(ctx); 5516fcf5ef2aSThomas Huth #else 55179f0cf041SMatheus Ferst CHK_SV(ctx); 5518fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5519fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5520fcf5ef2aSThomas Huth } 5521fcf5ef2aSThomas Huth 5522fcf5ef2aSThomas Huth /* tlbli */ 5523fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5524fcf5ef2aSThomas Huth { 5525fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55269f0cf041SMatheus Ferst GEN_PRIV(ctx); 5527fcf5ef2aSThomas Huth #else 55289f0cf041SMatheus Ferst CHK_SV(ctx); 5529fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5530fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5531fcf5ef2aSThomas Huth } 5532fcf5ef2aSThomas Huth 5533fcf5ef2aSThomas Huth /* BookE specific instructions */ 5534fcf5ef2aSThomas Huth 5535fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5536fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5537fcf5ef2aSThomas Huth { 5538fcf5ef2aSThomas Huth /* XXX: TODO */ 5539fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5540fcf5ef2aSThomas Huth } 5541fcf5ef2aSThomas Huth 5542fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5543fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5544fcf5ef2aSThomas Huth { 5545fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55469f0cf041SMatheus Ferst GEN_PRIV(ctx); 5547fcf5ef2aSThomas Huth #else 5548fcf5ef2aSThomas Huth TCGv t0; 5549fcf5ef2aSThomas Huth 55509f0cf041SMatheus Ferst CHK_SV(ctx); 5551fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5552fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5553fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5554fcf5ef2aSThomas Huth tcg_temp_free(t0); 5555fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5556fcf5ef2aSThomas Huth } 5557fcf5ef2aSThomas Huth 5558fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5559fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5560fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5561fcf5ef2aSThomas Huth { 5562fcf5ef2aSThomas Huth TCGv t0, t1; 5563fcf5ef2aSThomas Huth 5564fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5565fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5566fcf5ef2aSThomas Huth 5567fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5568fcf5ef2aSThomas Huth case 0x05: 5569fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5570fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5571fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5572fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5573fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5574fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5575fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5576fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5577fcf5ef2aSThomas Huth break; 5578fcf5ef2aSThomas Huth case 0x04: 5579fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5580fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5581fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5582fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5583fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5584fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5585fcf5ef2aSThomas Huth break; 5586fcf5ef2aSThomas Huth case 0x01: 5587fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5588fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5589fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5590fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5591fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5592fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5593fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5594fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5595fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5596fcf5ef2aSThomas Huth break; 5597fcf5ef2aSThomas Huth case 0x00: 5598fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5599fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5600fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5601fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5602fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5603fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5604fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5605fcf5ef2aSThomas Huth break; 5606fcf5ef2aSThomas Huth case 0x0D: 5607fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5608fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5609fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5610fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5611fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5612fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5613fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5614fcf5ef2aSThomas Huth break; 5615fcf5ef2aSThomas Huth case 0x0C: 5616fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5617fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5618fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5619fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5620fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5621fcf5ef2aSThomas Huth break; 5622fcf5ef2aSThomas Huth } 5623fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5624fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5625fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5626fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5627fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5628fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5629fcf5ef2aSThomas Huth } else { 5630fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5631fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5632fcf5ef2aSThomas Huth } 5633fcf5ef2aSThomas Huth 5634fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5635fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5636fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5637fcf5ef2aSThomas Huth 5638fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5639fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5640fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5641fcf5ef2aSThomas Huth } 5642fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5643fcf5ef2aSThomas Huth /* Signed */ 5644fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5645fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5646fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5647fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5648fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5649fcf5ef2aSThomas Huth /* Saturate */ 5650fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5651fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5652fcf5ef2aSThomas Huth } 5653fcf5ef2aSThomas Huth } else { 5654fcf5ef2aSThomas Huth /* Unsigned */ 5655fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5656fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5657fcf5ef2aSThomas Huth /* Saturate */ 5658fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5659fcf5ef2aSThomas Huth } 5660fcf5ef2aSThomas Huth } 5661fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5662fcf5ef2aSThomas Huth /* Check overflow */ 5663fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5664fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5665fcf5ef2aSThomas Huth } 5666fcf5ef2aSThomas Huth gen_set_label(l1); 5667fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5668fcf5ef2aSThomas Huth } 5669fcf5ef2aSThomas Huth } else { 5670fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5671fcf5ef2aSThomas Huth } 5672fcf5ef2aSThomas Huth tcg_temp_free(t0); 5673fcf5ef2aSThomas Huth tcg_temp_free(t1); 5674fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5675fcf5ef2aSThomas Huth /* Update Rc0 */ 5676fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5677fcf5ef2aSThomas Huth } 5678fcf5ef2aSThomas Huth } 5679fcf5ef2aSThomas Huth 5680fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5681fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5682fcf5ef2aSThomas Huth { \ 5683fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5684fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5685fcf5ef2aSThomas Huth } 5686fcf5ef2aSThomas Huth 5687fcf5ef2aSThomas Huth /* macchw - macchw. */ 5688fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5689fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5690fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5691fcf5ef2aSThomas Huth /* macchws - macchws. */ 5692fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5693fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5694fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5695fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5696fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5697fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5698fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5699fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5700fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5701fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5702fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5703fcf5ef2aSThomas Huth /* machhw - machhw. */ 5704fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5705fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5706fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5707fcf5ef2aSThomas Huth /* machhws - machhws. */ 5708fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5709fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5710fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5711fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5712fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5713fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5714fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5715fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5716fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5717fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5718fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5719fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5720fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5721fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5722fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5723fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5724fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5725fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5726fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5727fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5728fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5729fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5730fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5731fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5732fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5733fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5734fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5735fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5736fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5737fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5738fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5739fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5740fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5741fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5742fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5743fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5744fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5745fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5746fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5747fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5748fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5749fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5750fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5751fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5752fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5753fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5754fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5755fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5756fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5757fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5758fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5759fcf5ef2aSThomas Huth 5760fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5761fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5762fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5763fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5764fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5765fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5766fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5767fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5768fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5769fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5770fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5771fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5772fcf5ef2aSThomas Huth 5773fcf5ef2aSThomas Huth /* mfdcr */ 5774fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5775fcf5ef2aSThomas Huth { 5776fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57779f0cf041SMatheus Ferst GEN_PRIV(ctx); 5778fcf5ef2aSThomas Huth #else 5779fcf5ef2aSThomas Huth TCGv dcrn; 5780fcf5ef2aSThomas Huth 57819f0cf041SMatheus Ferst CHK_SV(ctx); 5782fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5783fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5784fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5785fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5786fcf5ef2aSThomas Huth } 5787fcf5ef2aSThomas Huth 5788fcf5ef2aSThomas Huth /* mtdcr */ 5789fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5790fcf5ef2aSThomas Huth { 5791fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57929f0cf041SMatheus Ferst GEN_PRIV(ctx); 5793fcf5ef2aSThomas Huth #else 5794fcf5ef2aSThomas Huth TCGv dcrn; 5795fcf5ef2aSThomas Huth 57969f0cf041SMatheus Ferst CHK_SV(ctx); 5797fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5798fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5799fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5800fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5801fcf5ef2aSThomas Huth } 5802fcf5ef2aSThomas Huth 5803fcf5ef2aSThomas Huth /* mfdcrx */ 5804fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5805fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5806fcf5ef2aSThomas Huth { 5807fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58089f0cf041SMatheus Ferst GEN_PRIV(ctx); 5809fcf5ef2aSThomas Huth #else 58109f0cf041SMatheus Ferst CHK_SV(ctx); 5811fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5812fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5813fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5814fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5815fcf5ef2aSThomas Huth } 5816fcf5ef2aSThomas Huth 5817fcf5ef2aSThomas Huth /* mtdcrx */ 5818fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5819fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5820fcf5ef2aSThomas Huth { 5821fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58229f0cf041SMatheus Ferst GEN_PRIV(ctx); 5823fcf5ef2aSThomas Huth #else 58249f0cf041SMatheus Ferst CHK_SV(ctx); 5825fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5826fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5827fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5828fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5829fcf5ef2aSThomas Huth } 5830fcf5ef2aSThomas Huth 5831fcf5ef2aSThomas Huth /* dccci */ 5832fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5833fcf5ef2aSThomas Huth { 58349f0cf041SMatheus Ferst CHK_SV(ctx); 5835fcf5ef2aSThomas Huth /* interpreted as no-op */ 5836fcf5ef2aSThomas Huth } 5837fcf5ef2aSThomas Huth 5838fcf5ef2aSThomas Huth /* dcread */ 5839fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5840fcf5ef2aSThomas Huth { 5841fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58429f0cf041SMatheus Ferst GEN_PRIV(ctx); 5843fcf5ef2aSThomas Huth #else 5844fcf5ef2aSThomas Huth TCGv EA, val; 5845fcf5ef2aSThomas Huth 58469f0cf041SMatheus Ferst CHK_SV(ctx); 5847fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5848fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5849fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5850fcf5ef2aSThomas Huth val = tcg_temp_new(); 5851fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5852fcf5ef2aSThomas Huth tcg_temp_free(val); 5853fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5854fcf5ef2aSThomas Huth tcg_temp_free(EA); 5855fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5856fcf5ef2aSThomas Huth } 5857fcf5ef2aSThomas Huth 5858fcf5ef2aSThomas Huth /* icbt */ 5859fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5860fcf5ef2aSThomas Huth { 5861efe843d8SDavid Gibson /* 5862efe843d8SDavid Gibson * interpreted as no-op 5863efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5864efe843d8SDavid Gibson * does not generate any exception 5865fcf5ef2aSThomas Huth */ 5866fcf5ef2aSThomas Huth } 5867fcf5ef2aSThomas Huth 5868fcf5ef2aSThomas Huth /* iccci */ 5869fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5870fcf5ef2aSThomas Huth { 58719f0cf041SMatheus Ferst CHK_SV(ctx); 5872fcf5ef2aSThomas Huth /* interpreted as no-op */ 5873fcf5ef2aSThomas Huth } 5874fcf5ef2aSThomas Huth 5875fcf5ef2aSThomas Huth /* icread */ 5876fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5877fcf5ef2aSThomas Huth { 58789f0cf041SMatheus Ferst CHK_SV(ctx); 5879fcf5ef2aSThomas Huth /* interpreted as no-op */ 5880fcf5ef2aSThomas Huth } 5881fcf5ef2aSThomas Huth 5882fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5883fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5884fcf5ef2aSThomas Huth { 5885fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58869f0cf041SMatheus Ferst GEN_PRIV(ctx); 5887fcf5ef2aSThomas Huth #else 58889f0cf041SMatheus Ferst CHK_SV(ctx); 5889fcf5ef2aSThomas Huth /* Restore CPU state */ 5890fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 589159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5892fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5893fcf5ef2aSThomas Huth } 5894fcf5ef2aSThomas Huth 5895fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5896fcf5ef2aSThomas Huth { 5897fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58989f0cf041SMatheus Ferst GEN_PRIV(ctx); 5899fcf5ef2aSThomas Huth #else 59009f0cf041SMatheus Ferst CHK_SV(ctx); 5901fcf5ef2aSThomas Huth /* Restore CPU state */ 5902fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 590359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5904fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5905fcf5ef2aSThomas Huth } 5906fcf5ef2aSThomas Huth 5907fcf5ef2aSThomas Huth /* BookE specific */ 5908fcf5ef2aSThomas Huth 5909fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5910fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5911fcf5ef2aSThomas Huth { 5912fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59139f0cf041SMatheus Ferst GEN_PRIV(ctx); 5914fcf5ef2aSThomas Huth #else 59159f0cf041SMatheus Ferst CHK_SV(ctx); 5916fcf5ef2aSThomas Huth /* Restore CPU state */ 5917fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 591859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5919fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5920fcf5ef2aSThomas Huth } 5921fcf5ef2aSThomas Huth 5922fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5923fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5924fcf5ef2aSThomas Huth { 5925fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59269f0cf041SMatheus Ferst GEN_PRIV(ctx); 5927fcf5ef2aSThomas Huth #else 59289f0cf041SMatheus Ferst CHK_SV(ctx); 5929fcf5ef2aSThomas Huth /* Restore CPU state */ 5930fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 593159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5932fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5933fcf5ef2aSThomas Huth } 5934fcf5ef2aSThomas Huth 5935fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5936fcf5ef2aSThomas Huth 5937fcf5ef2aSThomas Huth /* tlbre */ 5938fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5939fcf5ef2aSThomas Huth { 5940fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59419f0cf041SMatheus Ferst GEN_PRIV(ctx); 5942fcf5ef2aSThomas Huth #else 59439f0cf041SMatheus Ferst CHK_SV(ctx); 5944fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5945fcf5ef2aSThomas Huth case 0: 5946fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5947fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5948fcf5ef2aSThomas Huth break; 5949fcf5ef2aSThomas Huth case 1: 5950fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5951fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5952fcf5ef2aSThomas Huth break; 5953fcf5ef2aSThomas Huth default: 5954fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5955fcf5ef2aSThomas Huth break; 5956fcf5ef2aSThomas Huth } 5957fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5958fcf5ef2aSThomas Huth } 5959fcf5ef2aSThomas Huth 5960fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5961fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5962fcf5ef2aSThomas Huth { 5963fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5965fcf5ef2aSThomas Huth #else 5966fcf5ef2aSThomas Huth TCGv t0; 5967fcf5ef2aSThomas Huth 59689f0cf041SMatheus Ferst CHK_SV(ctx); 5969fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5970fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5971fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5972fcf5ef2aSThomas Huth tcg_temp_free(t0); 5973fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5974fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5975fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5976fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5977fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5978fcf5ef2aSThomas Huth gen_set_label(l1); 5979fcf5ef2aSThomas Huth } 5980fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5981fcf5ef2aSThomas Huth } 5982fcf5ef2aSThomas Huth 5983fcf5ef2aSThomas Huth /* tlbwe */ 5984fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5985fcf5ef2aSThomas Huth { 5986fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59879f0cf041SMatheus Ferst GEN_PRIV(ctx); 5988fcf5ef2aSThomas Huth #else 59899f0cf041SMatheus Ferst CHK_SV(ctx); 5990fcf5ef2aSThomas Huth 5991fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5992fcf5ef2aSThomas Huth case 0: 5993fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5994fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5995fcf5ef2aSThomas Huth break; 5996fcf5ef2aSThomas Huth case 1: 5997fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5998fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5999fcf5ef2aSThomas Huth break; 6000fcf5ef2aSThomas Huth default: 6001fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6002fcf5ef2aSThomas Huth break; 6003fcf5ef2aSThomas Huth } 6004fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6005fcf5ef2aSThomas Huth } 6006fcf5ef2aSThomas Huth 6007fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6008fcf5ef2aSThomas Huth 6009fcf5ef2aSThomas Huth /* tlbre */ 6010fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6011fcf5ef2aSThomas Huth { 6012fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60139f0cf041SMatheus Ferst GEN_PRIV(ctx); 6014fcf5ef2aSThomas Huth #else 60159f0cf041SMatheus Ferst CHK_SV(ctx); 6016fcf5ef2aSThomas Huth 6017fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6018fcf5ef2aSThomas Huth case 0: 6019fcf5ef2aSThomas Huth case 1: 6020fcf5ef2aSThomas Huth case 2: 6021fcf5ef2aSThomas Huth { 6022fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6023fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6024fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6025fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6026fcf5ef2aSThomas Huth } 6027fcf5ef2aSThomas Huth break; 6028fcf5ef2aSThomas Huth default: 6029fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6030fcf5ef2aSThomas Huth break; 6031fcf5ef2aSThomas Huth } 6032fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6033fcf5ef2aSThomas Huth } 6034fcf5ef2aSThomas Huth 6035fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6036fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6037fcf5ef2aSThomas Huth { 6038fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60399f0cf041SMatheus Ferst GEN_PRIV(ctx); 6040fcf5ef2aSThomas Huth #else 6041fcf5ef2aSThomas Huth TCGv t0; 6042fcf5ef2aSThomas Huth 60439f0cf041SMatheus Ferst CHK_SV(ctx); 6044fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6045fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6046fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6047fcf5ef2aSThomas Huth tcg_temp_free(t0); 6048fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6049fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6050fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6051fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6052fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6053fcf5ef2aSThomas Huth gen_set_label(l1); 6054fcf5ef2aSThomas Huth } 6055fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6056fcf5ef2aSThomas Huth } 6057fcf5ef2aSThomas Huth 6058fcf5ef2aSThomas Huth /* tlbwe */ 6059fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6060fcf5ef2aSThomas Huth { 6061fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60629f0cf041SMatheus Ferst GEN_PRIV(ctx); 6063fcf5ef2aSThomas Huth #else 60649f0cf041SMatheus Ferst CHK_SV(ctx); 6065fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6066fcf5ef2aSThomas Huth case 0: 6067fcf5ef2aSThomas Huth case 1: 6068fcf5ef2aSThomas Huth case 2: 6069fcf5ef2aSThomas Huth { 6070fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6071fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6072fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6073fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6074fcf5ef2aSThomas Huth } 6075fcf5ef2aSThomas Huth break; 6076fcf5ef2aSThomas Huth default: 6077fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6078fcf5ef2aSThomas Huth break; 6079fcf5ef2aSThomas Huth } 6080fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6081fcf5ef2aSThomas Huth } 6082fcf5ef2aSThomas Huth 6083fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6084fcf5ef2aSThomas Huth 6085fcf5ef2aSThomas Huth /* tlbre */ 6086fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6087fcf5ef2aSThomas Huth { 6088fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60899f0cf041SMatheus Ferst GEN_PRIV(ctx); 6090fcf5ef2aSThomas Huth #else 60919f0cf041SMatheus Ferst CHK_SV(ctx); 6092fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6093fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6094fcf5ef2aSThomas Huth } 6095fcf5ef2aSThomas Huth 6096fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6097fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6098fcf5ef2aSThomas Huth { 6099fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61009f0cf041SMatheus Ferst GEN_PRIV(ctx); 6101fcf5ef2aSThomas Huth #else 6102fcf5ef2aSThomas Huth TCGv t0; 6103fcf5ef2aSThomas Huth 61049f0cf041SMatheus Ferst CHK_SV(ctx); 6105fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6106fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6107fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6108fcf5ef2aSThomas Huth } else { 6109fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6110fcf5ef2aSThomas Huth } 6111fcf5ef2aSThomas Huth 6112fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6113fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6114fcf5ef2aSThomas Huth tcg_temp_free(t0); 6115fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6116fcf5ef2aSThomas Huth } 6117fcf5ef2aSThomas Huth 6118fcf5ef2aSThomas Huth /* tlbwe */ 6119fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6120fcf5ef2aSThomas Huth { 6121fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61229f0cf041SMatheus Ferst GEN_PRIV(ctx); 6123fcf5ef2aSThomas Huth #else 61249f0cf041SMatheus Ferst CHK_SV(ctx); 6125fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6126fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6127fcf5ef2aSThomas Huth } 6128fcf5ef2aSThomas Huth 6129fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6130fcf5ef2aSThomas Huth { 6131fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61329f0cf041SMatheus Ferst GEN_PRIV(ctx); 6133fcf5ef2aSThomas Huth #else 6134fcf5ef2aSThomas Huth TCGv t0; 6135fcf5ef2aSThomas Huth 61369f0cf041SMatheus Ferst CHK_SV(ctx); 6137fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6138fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6139fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6140fcf5ef2aSThomas Huth tcg_temp_free(t0); 6141fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6142fcf5ef2aSThomas Huth } 6143fcf5ef2aSThomas Huth 6144fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6145fcf5ef2aSThomas Huth { 6146fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61479f0cf041SMatheus Ferst GEN_PRIV(ctx); 6148fcf5ef2aSThomas Huth #else 6149fcf5ef2aSThomas Huth TCGv t0; 6150fcf5ef2aSThomas Huth 61519f0cf041SMatheus Ferst CHK_SV(ctx); 6152fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6153fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6154fcf5ef2aSThomas Huth 6155fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 6156fcf5ef2aSThomas Huth case 0: 6157fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6158fcf5ef2aSThomas Huth break; 6159fcf5ef2aSThomas Huth case 1: 6160fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6161fcf5ef2aSThomas Huth break; 6162fcf5ef2aSThomas Huth case 3: 6163fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6164fcf5ef2aSThomas Huth break; 6165fcf5ef2aSThomas Huth default: 6166fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6167fcf5ef2aSThomas Huth break; 6168fcf5ef2aSThomas Huth } 6169fcf5ef2aSThomas Huth 6170fcf5ef2aSThomas Huth tcg_temp_free(t0); 6171fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6172fcf5ef2aSThomas Huth } 6173fcf5ef2aSThomas Huth 6174fcf5ef2aSThomas Huth /* wrtee */ 6175fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6176fcf5ef2aSThomas Huth { 6177fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61789f0cf041SMatheus Ferst GEN_PRIV(ctx); 6179fcf5ef2aSThomas Huth #else 6180fcf5ef2aSThomas Huth TCGv t0; 6181fcf5ef2aSThomas Huth 61829f0cf041SMatheus Ferst CHK_SV(ctx); 6183fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6184fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6185fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6186fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 61872fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6188fcf5ef2aSThomas Huth tcg_temp_free(t0); 6189efe843d8SDavid Gibson /* 6190efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6191efe843d8SDavid Gibson * just set msr_ee to 1 6192fcf5ef2aSThomas Huth */ 6193d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6194fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6195fcf5ef2aSThomas Huth } 6196fcf5ef2aSThomas Huth 6197fcf5ef2aSThomas Huth /* wrteei */ 6198fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6199fcf5ef2aSThomas Huth { 6200fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 62019f0cf041SMatheus Ferst GEN_PRIV(ctx); 6202fcf5ef2aSThomas Huth #else 62039f0cf041SMatheus Ferst CHK_SV(ctx); 6204fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6205fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 62062fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6207fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6208d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6209fcf5ef2aSThomas Huth } else { 6210fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6211fcf5ef2aSThomas Huth } 6212fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6213fcf5ef2aSThomas Huth } 6214fcf5ef2aSThomas Huth 6215fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6216fcf5ef2aSThomas Huth 6217fcf5ef2aSThomas Huth /* dlmzb */ 6218fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6219fcf5ef2aSThomas Huth { 6220fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6221fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6222fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6223fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6224fcf5ef2aSThomas Huth } 6225fcf5ef2aSThomas Huth 6226fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6227fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6228fcf5ef2aSThomas Huth { 6229fcf5ef2aSThomas Huth /* interpreted as no-op */ 6230fcf5ef2aSThomas Huth } 6231fcf5ef2aSThomas Huth 6232fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6233fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6234fcf5ef2aSThomas Huth { 623527a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 623627a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 623727a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 623827a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 623927a3ea7eSBALATON Zoltan } 624027a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6241fcf5ef2aSThomas Huth } 6242fcf5ef2aSThomas Huth 6243fcf5ef2aSThomas Huth /* icbt */ 6244fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6245fcf5ef2aSThomas Huth { 6246efe843d8SDavid Gibson /* 6247efe843d8SDavid Gibson * interpreted as no-op 6248efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6249efe843d8SDavid Gibson * does not generate any exception 6250fcf5ef2aSThomas Huth */ 6251fcf5ef2aSThomas Huth } 6252fcf5ef2aSThomas Huth 6253fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6254fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6255fcf5ef2aSThomas Huth { 6256fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6257fcf5ef2aSThomas Huth 6258fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6259fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6260fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6261fcf5ef2aSThomas Huth } 6262fcf5ef2aSThomas Huth 6263fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6264fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6265fcf5ef2aSThomas Huth { 6266fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6267fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6268fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6269fcf5ef2aSThomas Huth 6270fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6271fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6272fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6273fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6274fcf5ef2aSThomas Huth } else { 6275fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6276fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6277fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6278fcf5ef2aSThomas Huth } 6279fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6280fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6281fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6282fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6283fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6284fcf5ef2aSThomas Huth } 6285fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6286fcf5ef2aSThomas Huth 6287fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6288fcf5ef2aSThomas Huth { 6289fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6290fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6291fcf5ef2aSThomas Huth return; 6292fcf5ef2aSThomas Huth } 6293fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6294fcf5ef2aSThomas Huth } 6295fcf5ef2aSThomas Huth 6296fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6297fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6298fcf5ef2aSThomas Huth { \ 6299fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6300fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6301fcf5ef2aSThomas Huth return; \ 6302fcf5ef2aSThomas Huth } \ 6303efe843d8SDavid Gibson /* \ 6304efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6305fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6306fcf5ef2aSThomas Huth * \ 6307fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6308fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6309fcf5ef2aSThomas Huth */ \ 6310fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6311fcf5ef2aSThomas Huth } 6312fcf5ef2aSThomas Huth 6313fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6314fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6315fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6316fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6317fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6318fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6319fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6320efe843d8SDavid Gibson 6321b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6322b8b4576eSSuraj Jitindar Singh { 6323efe843d8SDavid Gibson /* Do Nothing */ 6324b8b4576eSSuraj Jitindar Singh } 6325fcf5ef2aSThomas Huth 632680b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 632780b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 632880b8c1eeSNikunj A Dadhania { \ 6329efe843d8SDavid Gibson /* \ 6330efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6331efe843d8SDavid Gibson * implementation of the copy paste facility \ 633280b8c1eeSNikunj A Dadhania */ \ 633380b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 633480b8c1eeSNikunj A Dadhania } 633580b8c1eeSNikunj A Dadhania 633680b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 633780b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 633880b8c1eeSNikunj A Dadhania 6339fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6340fcf5ef2aSThomas Huth { 6341fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6342fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6343fcf5ef2aSThomas Huth return; 6344fcf5ef2aSThomas Huth } 6345efe843d8SDavid Gibson /* 6346efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6347efe843d8SDavid Gibson * simple: 6348fcf5ef2aSThomas Huth * 6349fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6350fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6351fcf5ef2aSThomas Huth */ 6352fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6353fcf5ef2aSThomas Huth } 6354fcf5ef2aSThomas Huth 6355fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6356fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6357fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6358fcf5ef2aSThomas Huth { \ 63599f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6360fcf5ef2aSThomas Huth } 6361fcf5ef2aSThomas Huth 6362fcf5ef2aSThomas Huth #else 6363fcf5ef2aSThomas Huth 6364fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6365fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6366fcf5ef2aSThomas Huth { \ 63679f0cf041SMatheus Ferst CHK_SV(ctx); \ 6368fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6369fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6370fcf5ef2aSThomas Huth return; \ 6371fcf5ef2aSThomas Huth } \ 6372efe843d8SDavid Gibson /* \ 6373efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6374fcf5ef2aSThomas Huth * simple: \ 6375fcf5ef2aSThomas Huth * \ 6376fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6377fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6378fcf5ef2aSThomas Huth */ \ 6379fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6380fcf5ef2aSThomas Huth } 6381fcf5ef2aSThomas Huth 6382fcf5ef2aSThomas Huth #endif 6383fcf5ef2aSThomas Huth 6384fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6385fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6386fcf5ef2aSThomas Huth 63871a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 63881a404c91SMark Cave-Ayland { 6389e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 63901a404c91SMark Cave-Ayland } 63911a404c91SMark Cave-Ayland 63921a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 63931a404c91SMark Cave-Ayland { 6394e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 63954b65b6e7SVíctor Colombo /* 63964b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 63974b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 63984b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 63994b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 64004b65b6e7SVíctor Colombo * to be 0. 64014b65b6e7SVíctor Colombo */ 64024b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 64031a404c91SMark Cave-Ayland } 64041a404c91SMark Cave-Ayland 6405c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6406c4a18dbfSMark Cave-Ayland { 640737da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6408c4a18dbfSMark Cave-Ayland } 6409c4a18dbfSMark Cave-Ayland 6410c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6411c4a18dbfSMark Cave-Ayland { 641237da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6413c4a18dbfSMark Cave-Ayland } 6414c4a18dbfSMark Cave-Ayland 6415c9826ae9SRichard Henderson /* 6416f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6417f2aabda8SRichard Henderson */ 6418d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6419d39b2cc7SLuis Pires { 6420d39b2cc7SLuis Pires return x * 2; 6421d39b2cc7SLuis Pires } 6422d39b2cc7SLuis Pires 6423f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6424f2aabda8SRichard Henderson { 6425f2aabda8SRichard Henderson return x * 4; 6426f2aabda8SRichard Henderson } 6427f2aabda8SRichard Henderson 6428e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6429e10271e1SMatheus Ferst { 6430e10271e1SMatheus Ferst return x * 16; 6431e10271e1SMatheus Ferst } 6432e10271e1SMatheus Ferst 6433670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6434670f1da3SVíctor Colombo { 6435670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6436670f1da3SVíctor Colombo } 6437670f1da3SVíctor Colombo 6438f2aabda8SRichard Henderson /* 6439c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6440c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6441c9826ae9SRichard Henderson * proper variable. 6442c9826ae9SRichard Henderson */ 6443c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6444c9826ae9SRichard Henderson do { \ 6445c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6446c9826ae9SRichard Henderson return false; \ 6447c9826ae9SRichard Henderson } \ 6448c9826ae9SRichard Henderson } while (0) 6449c9826ae9SRichard Henderson 6450c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6451c9826ae9SRichard Henderson do { \ 6452c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6453c9826ae9SRichard Henderson return false; \ 6454c9826ae9SRichard Henderson } \ 6455c9826ae9SRichard Henderson } while (0) 6456c9826ae9SRichard Henderson 6457c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6458c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6459c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6460c9826ae9SRichard Henderson #else 6461c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6462c9826ae9SRichard Henderson #endif 6463c9826ae9SRichard Henderson 6464e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6465e2205a46SBruno Larsen do { \ 6466e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6467e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6468e2205a46SBruno Larsen return true; \ 6469e2205a46SBruno Larsen } \ 6470e2205a46SBruno Larsen } while (0) 6471e2205a46SBruno Larsen 64728226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 64738226cb2dSBruno Larsen (billionai) do { \ 64748226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 64758226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 64768226cb2dSBruno Larsen (billionai) return true; \ 64778226cb2dSBruno Larsen (billionai) } \ 64788226cb2dSBruno Larsen (billionai) } while (0) 64798226cb2dSBruno Larsen (billionai) 648086057426SFernando Valle #define REQUIRE_FPU(ctx) \ 648186057426SFernando Valle do { \ 648286057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 648386057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 648486057426SFernando Valle return true; \ 648586057426SFernando Valle } \ 648686057426SFernando Valle } while (0) 648786057426SFernando Valle 6488fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6489fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6490fc34e81aSMatheus Ferst do { \ 6491fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6492fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6493fc34e81aSMatheus Ferst return true; \ 6494fc34e81aSMatheus Ferst } \ 6495fc34e81aSMatheus Ferst } while (0) 6496fc34e81aSMatheus Ferst 6497fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6498fc34e81aSMatheus Ferst do { \ 6499e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6500fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6501fc34e81aSMatheus Ferst return true; \ 6502fc34e81aSMatheus Ferst } \ 6503fc34e81aSMatheus Ferst } while (0) 6504fc34e81aSMatheus Ferst #else 6505fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6506fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6507fc34e81aSMatheus Ferst #endif 6508fc34e81aSMatheus Ferst 6509f2aabda8SRichard Henderson /* 6510f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6511f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6512f2aabda8SRichard Henderson */ 6513f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6514f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6515f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 651619f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 651719f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 651819f0862dSLuis Pires { \ 651919f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 652019f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 652119f0862dSLuis Pires } 652219f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 652319f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 652419f0862dSLuis Pires { \ 652519f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 652619f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 652719f0862dSLuis Pires } 6528f2aabda8SRichard Henderson 6529f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6530f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6531f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 653219f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 653319f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 653419f0862dSLuis Pires { \ 653519f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 653619f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 653719f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 653819f0862dSLuis Pires } 6539f2aabda8SRichard Henderson 6540f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6541f2aabda8SRichard Henderson 6542f2aabda8SRichard Henderson 654399082815SRichard Henderson #include "decode-insn32.c.inc" 654499082815SRichard Henderson #include "decode-insn64.c.inc" 6545565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6546565cb109SGustavo Romero 6547725b2d4dSFernando Eckhardt Valle /* 6548725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6549725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6550725b2d4dSFernando Eckhardt Valle */ 6551725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6552725b2d4dSFernando Eckhardt Valle { 6553725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6554725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6555725b2d4dSFernando Eckhardt Valle d->si = a->si; 6556725b2d4dSFernando Eckhardt Valle if (a->r) { 6557725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6558725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6559725b2d4dSFernando Eckhardt Valle return false; 6560725b2d4dSFernando Eckhardt Valle } 6561725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6562725b2d4dSFernando Eckhardt Valle } 6563725b2d4dSFernando Eckhardt Valle return true; 6564725b2d4dSFernando Eckhardt Valle } 6565725b2d4dSFernando Eckhardt Valle 656699082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 656799082815SRichard Henderson 6568139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6569fcf5ef2aSThomas Huth 6570139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6571fcf5ef2aSThomas Huth 6572139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6573fcf5ef2aSThomas Huth 6574139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6575fcf5ef2aSThomas Huth 6576139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6577fcf5ef2aSThomas Huth 65781f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 65791f26c751SDaniel Henrique Barboza 658098f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 658198f43417SMatheus Ferst 6582016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6583016b6e1dSLeandro Lupori 658420e2d04eSLeandro Lupori /* Handles lfdp */ 65855cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 65865cb091a4SNikunj A Dadhania { 658720e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 65885cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 65895cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 65905cb091a4SNikunj A Dadhania } 65915cb091a4SNikunj A Dadhania } 65925cb091a4SNikunj A Dadhania return gen_invalid(ctx); 65935cb091a4SNikunj A Dadhania } 65945cb091a4SNikunj A Dadhania 659520e2d04eSLeandro Lupori /* Handles stfdp */ 6596e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6597e3001664SNikunj A Dadhania { 659820e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 659920e2d04eSLeandro Lupori /* stfdp */ 6600e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6601e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6602e3001664SNikunj A Dadhania } 6603e3001664SNikunj A Dadhania } 6604e3001664SNikunj A Dadhania return gen_invalid(ctx); 6605e3001664SNikunj A Dadhania } 6606e3001664SNikunj A Dadhania 66079d69cfa2SLijun Pan #if defined(TARGET_PPC64) 66089d69cfa2SLijun Pan /* brd */ 66099d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 66109d69cfa2SLijun Pan { 66119d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 66129d69cfa2SLijun Pan } 66139d69cfa2SLijun Pan 66149d69cfa2SLijun Pan /* brw */ 66159d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 66169d69cfa2SLijun Pan { 66179d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 66189d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 66199d69cfa2SLijun Pan 66209d69cfa2SLijun Pan } 66219d69cfa2SLijun Pan 66229d69cfa2SLijun Pan /* brh */ 66239d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 66249d69cfa2SLijun Pan { 6625491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 66269d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 66279d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 66289d69cfa2SLijun Pan 66299d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6630491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6631491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 66329d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 66339d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 66349d69cfa2SLijun Pan 66359d69cfa2SLijun Pan tcg_temp_free_i64(t1); 66369d69cfa2SLijun Pan tcg_temp_free_i64(t2); 66379d69cfa2SLijun Pan } 66389d69cfa2SLijun Pan #endif 66399d69cfa2SLijun Pan 6640fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 66419d69cfa2SLijun Pan #if defined(TARGET_PPC64) 66429d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 66439d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 66449d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 66459d69cfa2SLijun Pan #endif 6646fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6647fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6648fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6649fcf5ef2aSThomas Huth #endif 6650fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6651fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6652fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6653fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6654fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6655fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6656fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6657fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6658fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6659fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6660fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6661fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6662fcf5ef2aSThomas Huth #endif 6663fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6664fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6665fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6666fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6667fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6668fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6669fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 667080b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6671b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 667280b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6673fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6674fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6675fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6676fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6677fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6678fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6679fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6680fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6681fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6682fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6683fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6684fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6685fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6686fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6687fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6688fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6689fcf5ef2aSThomas Huth #endif 6690fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6691fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6692fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6693fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6694fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6695fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6696fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6697fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6698fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6699fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6700fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6701fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6702fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6703fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6704fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6705fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6706fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6707fcf5ef2aSThomas Huth #endif 67085cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 67095cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 671072b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6711e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6712fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6713fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6714fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6715fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6716fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6717fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6718c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6719fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6720fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6721fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6722fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6723a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6724a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6725fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6726fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6727fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6728fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6729a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6730a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6731fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6732fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6733fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6734fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6735fcf5ef2aSThomas Huth #endif 6736fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 67370c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 67380c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 67390c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6740fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6741fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6742fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6743fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6744fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6745fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6746fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6747fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6748fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 67493c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 67503c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 67513c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 67523c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 67533c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 67543c89b8d6SNicholas Piggin #endif 6755cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6756fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6757fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6758fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6759fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6760fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6761fcf5ef2aSThomas Huth #endif 67623c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 67633c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 67643c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6765fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6766fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6767fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6768fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6769fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6770fcf5ef2aSThomas Huth #endif 6771fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6772fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6773fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6774fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6775fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6776fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6777fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6778fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6779fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6780b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6781fcf5ef2aSThomas Huth #endif 6782fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6783fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6784fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 678550728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6786fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6787fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 678850728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6789fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 679050728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6791fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 679250728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6793fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6794fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 679550728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6796fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 679799d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6798fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6799fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 680050728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6801fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6802fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6803fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6804fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6805fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6806fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6807fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6808fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6809fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6810fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6811fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6812fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6813fcf5ef2aSThomas Huth #endif 6814fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6815efe843d8SDavid Gibson /* 6816efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6817efe843d8SDavid Gibson * different ISA versions 6818efe843d8SDavid Gibson */ 6819fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6820fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6821fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6822fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6823fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6824fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6825fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6826fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6827fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6828fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6829fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6830fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6831fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6832fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6833fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6834fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6835fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6836fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6837fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6838fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6839fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6840fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6841fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6842fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6843fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6844fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6845fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6846fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6847fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6848fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6849fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6850fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6851fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6852fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6853fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6854fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6855fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6856fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6857fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6858fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6859fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 686027a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6861fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6862fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 68630c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 68640c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6865fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6866fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6867fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6868fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6869fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6870fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6871fcf5ef2aSThomas Huth PPC2_ISA300), 6872fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6873fcf5ef2aSThomas Huth #endif 6874fcf5ef2aSThomas Huth 6875fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6876fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6877fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6878fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6879fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6880fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6881fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6882fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6883fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6884fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6885fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6886fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6887fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6888fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6889fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 68904c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6891fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6892fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6893fcf5ef2aSThomas Huth 6894fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6895fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6896fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6897fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6898fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6899fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6900fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6901fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6902fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6903fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6904fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6905fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6906fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6907fcf5ef2aSThomas Huth 6908fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6909fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6910fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6911fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6912fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6913fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6914fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6915fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6916fcf5ef2aSThomas Huth 6917fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6918fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6919fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6920fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6921fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6922fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6923fcf5ef2aSThomas Huth 6924fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6925fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6926fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6927fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6928fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6929fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6930fcf5ef2aSThomas Huth #endif 6931fcf5ef2aSThomas Huth 6932fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6933fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6934fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6935fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6936fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6937fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6938fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6939fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6940fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6941fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6942fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6943fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6944fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6945fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6946fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6947fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6948fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6949fcf5ef2aSThomas Huth 6950fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6951fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6952fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6953fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6954fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6955fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6956fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6957fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6958fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6959fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6960fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6961fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6962fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6963fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6964fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6965fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6966fcf5ef2aSThomas Huth #endif 6967fcf5ef2aSThomas Huth 6968fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6969fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6970fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6971fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6972fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6973fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6974fcf5ef2aSThomas Huth PPC_64B) 6975fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6976fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6977fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6978fcf5ef2aSThomas Huth PPC_64B), \ 6979fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6980fcf5ef2aSThomas Huth PPC_64B), \ 6981fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6982fcf5ef2aSThomas Huth PPC_64B) 6983fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6984fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6985fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6986fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6987fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6988fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6989fcf5ef2aSThomas Huth #endif 6990fcf5ef2aSThomas Huth 6991fcf5ef2aSThomas Huth #undef GEN_LDX_E 6992fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6993fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6994fcf5ef2aSThomas Huth 6995fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6996fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6997fcf5ef2aSThomas Huth 6998fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6999fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7000fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7001fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7002fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7003fcf5ef2aSThomas Huth #endif 7004fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7005fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7006fcf5ef2aSThomas Huth 700750728199SRoman Kapl /* External PID based load */ 700850728199SRoman Kapl #undef GEN_LDEPX 700950728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 701050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 701150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 701250728199SRoman Kapl 701350728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 701450728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 701550728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 701650728199SRoman Kapl #if defined(TARGET_PPC64) 7017fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 701850728199SRoman Kapl #endif 701950728199SRoman Kapl 7020fcf5ef2aSThomas Huth #undef GEN_STX_E 7021fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 70220123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7023fcf5ef2aSThomas Huth 7024fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7025fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7026fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7027fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7028fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7029fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7030fcf5ef2aSThomas Huth #endif 7031fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7032fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7033fcf5ef2aSThomas Huth 703450728199SRoman Kapl #undef GEN_STEPX 703550728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 703650728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 703750728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 703850728199SRoman Kapl 703950728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 704050728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 704150728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 704250728199SRoman Kapl #if defined(TARGET_PPC64) 7043fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 704450728199SRoman Kapl #endif 704550728199SRoman Kapl 7046fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7047fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7048fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7049fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7050fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7051fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7052fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7053fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7054fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7055fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7056fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7057fcf5ef2aSThomas Huth 7058fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7059fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7060fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7061fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7062fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7063fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7064fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7065fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7066fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7067fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7068fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7069fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7070fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7071fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7072fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7073fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7074fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7075fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7076fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7077fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7078fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7079fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7080fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7081fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7082fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7083fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7084fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7085fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7086fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7087fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7088fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7089fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7090fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7091fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7092fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7093fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7094fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7096fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7103fcf5ef2aSThomas Huth 7104fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7105fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7106fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7107fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7108fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7109fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7110fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7111fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7112fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7113fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7114fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7115fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7116fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7117fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7118fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7119fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7120fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7121fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7122fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7123fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7124fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7125fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7126fcf5ef2aSThomas Huth 7127139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 7128fcf5ef2aSThomas Huth 7129139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 7130fcf5ef2aSThomas Huth 7131139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 7132fcf5ef2aSThomas Huth 7133139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 7134fcf5ef2aSThomas Huth }; 7135fcf5ef2aSThomas Huth 71367468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71377468e2c8SBruno Larsen (billionai) /* Opcode types */ 71387468e2c8SBruno Larsen (billionai) enum { 71397468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 71407468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 71417468e2c8SBruno Larsen (billionai) }; 71427468e2c8SBruno Larsen (billionai) 71437468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 71447468e2c8SBruno Larsen (billionai) 71457468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 71467468e2c8SBruno Larsen (billionai) { 71477468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 71487468e2c8SBruno Larsen (billionai) } 71497468e2c8SBruno Larsen (billionai) 71507468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 71517468e2c8SBruno Larsen (billionai) { 71527468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 71537468e2c8SBruno Larsen (billionai) } 71547468e2c8SBruno Larsen (billionai) 71557468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 71567468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 71577468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 71587468e2c8SBruno Larsen (billionai) { 71597468e2c8SBruno Larsen (billionai) int i; 71607468e2c8SBruno Larsen (billionai) 71617468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 71627468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71637468e2c8SBruno Larsen (billionai) } 71647468e2c8SBruno Larsen (billionai) } 71657468e2c8SBruno Larsen (billionai) 71667468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 71677468e2c8SBruno Larsen (billionai) { 71687468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 71697468e2c8SBruno Larsen (billionai) 71707468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 71717468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 71727468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 71737468e2c8SBruno Larsen (billionai) 71747468e2c8SBruno Larsen (billionai) return 0; 71757468e2c8SBruno Larsen (billionai) } 71767468e2c8SBruno Larsen (billionai) 71777468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 71787468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 71797468e2c8SBruno Larsen (billionai) { 71807468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 71817468e2c8SBruno Larsen (billionai) return -1; 71827468e2c8SBruno Larsen (billionai) } 71837468e2c8SBruno Larsen (billionai) table[idx] = handler; 71847468e2c8SBruno Larsen (billionai) 71857468e2c8SBruno Larsen (billionai) return 0; 71867468e2c8SBruno Larsen (billionai) } 71877468e2c8SBruno Larsen (billionai) 71887468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 71897468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 71907468e2c8SBruno Larsen (billionai) { 71917468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 71927468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 71937468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 71947468e2c8SBruno Larsen (billionai) return -1; 71957468e2c8SBruno Larsen (billionai) } 71967468e2c8SBruno Larsen (billionai) 71977468e2c8SBruno Larsen (billionai) return 0; 71987468e2c8SBruno Larsen (billionai) } 71997468e2c8SBruno Larsen (billionai) 72007468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 72017468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72027468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72037468e2c8SBruno Larsen (billionai) { 72047468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 72057468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 72067468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 72077468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 72087468e2c8SBruno Larsen (billionai) return -1; 72097468e2c8SBruno Larsen (billionai) } 72107468e2c8SBruno Larsen (billionai) } else { 72117468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 72127468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 72137468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 72147468e2c8SBruno Larsen (billionai) return -1; 72157468e2c8SBruno Larsen (billionai) } 72167468e2c8SBruno Larsen (billionai) } 72177468e2c8SBruno Larsen (billionai) if (handler != NULL && 72187468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 72197468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 72207468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 72217468e2c8SBruno Larsen (billionai) return -1; 72227468e2c8SBruno Larsen (billionai) } 72237468e2c8SBruno Larsen (billionai) 72247468e2c8SBruno Larsen (billionai) return 0; 72257468e2c8SBruno Larsen (billionai) } 72267468e2c8SBruno Larsen (billionai) 72277468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 72287468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72297468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72307468e2c8SBruno Larsen (billionai) { 72317468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 72327468e2c8SBruno Larsen (billionai) } 72337468e2c8SBruno Larsen (billionai) 72347468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 72357468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72367468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 72377468e2c8SBruno Larsen (billionai) { 72387468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 72397468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 72407468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 72417468e2c8SBruno Larsen (billionai) return -1; 72427468e2c8SBruno Larsen (billionai) } 72437468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 72447468e2c8SBruno Larsen (billionai) handler) < 0) { 72457468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 72467468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 72477468e2c8SBruno Larsen (billionai) return -1; 72487468e2c8SBruno Larsen (billionai) } 72497468e2c8SBruno Larsen (billionai) 72507468e2c8SBruno Larsen (billionai) return 0; 72517468e2c8SBruno Larsen (billionai) } 72527468e2c8SBruno Larsen (billionai) 72537468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 72547468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72557468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 72567468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72577468e2c8SBruno Larsen (billionai) { 72587468e2c8SBruno Larsen (billionai) opc_handler_t **table; 72597468e2c8SBruno Larsen (billionai) 72607468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 72617468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 72627468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 72637468e2c8SBruno Larsen (billionai) return -1; 72647468e2c8SBruno Larsen (billionai) } 72657468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 72667468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 72677468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 72687468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 72697468e2c8SBruno Larsen (billionai) return -1; 72707468e2c8SBruno Larsen (billionai) } 72717468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 72727468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 72737468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 72747468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 72757468e2c8SBruno Larsen (billionai) return -1; 72767468e2c8SBruno Larsen (billionai) } 72777468e2c8SBruno Larsen (billionai) return 0; 72787468e2c8SBruno Larsen (billionai) } 72797468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 72807468e2c8SBruno Larsen (billionai) { 72817468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 72827468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 72837468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 72847468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 72857468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 72867468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 72877468e2c8SBruno Larsen (billionai) return -1; 72887468e2c8SBruno Larsen (billionai) } 72897468e2c8SBruno Larsen (billionai) } else { 72907468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 72917468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 72927468e2c8SBruno Larsen (billionai) return -1; 72937468e2c8SBruno Larsen (billionai) } 72947468e2c8SBruno Larsen (billionai) } 72957468e2c8SBruno Larsen (billionai) } else { 72967468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 72977468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 72987468e2c8SBruno Larsen (billionai) return -1; 72997468e2c8SBruno Larsen (billionai) } 73007468e2c8SBruno Larsen (billionai) } 73017468e2c8SBruno Larsen (billionai) } else { 73027468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 73037468e2c8SBruno Larsen (billionai) return -1; 73047468e2c8SBruno Larsen (billionai) } 73057468e2c8SBruno Larsen (billionai) } 73067468e2c8SBruno Larsen (billionai) 73077468e2c8SBruno Larsen (billionai) return 0; 73087468e2c8SBruno Larsen (billionai) } 73097468e2c8SBruno Larsen (billionai) 73107468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 73117468e2c8SBruno Larsen (billionai) { 73127468e2c8SBruno Larsen (billionai) int i, count, tmp; 73137468e2c8SBruno Larsen (billionai) 73147468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 73157468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 73167468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 73177468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 73187468e2c8SBruno Larsen (billionai) } 73197468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 73207468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 73217468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 73227468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 73237468e2c8SBruno Larsen (billionai) if (tmp == 0) { 73247468e2c8SBruno Larsen (billionai) free(table[i]); 73257468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 73267468e2c8SBruno Larsen (billionai) } else { 73277468e2c8SBruno Larsen (billionai) count++; 73287468e2c8SBruno Larsen (billionai) } 73297468e2c8SBruno Larsen (billionai) } else { 73307468e2c8SBruno Larsen (billionai) count++; 73317468e2c8SBruno Larsen (billionai) } 73327468e2c8SBruno Larsen (billionai) } 73337468e2c8SBruno Larsen (billionai) } 73347468e2c8SBruno Larsen (billionai) 73357468e2c8SBruno Larsen (billionai) return count; 73367468e2c8SBruno Larsen (billionai) } 73377468e2c8SBruno Larsen (billionai) 73387468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 73397468e2c8SBruno Larsen (billionai) { 73407468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 73417468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 73427468e2c8SBruno Larsen (billionai) } 73437468e2c8SBruno Larsen (billionai) } 73447468e2c8SBruno Larsen (billionai) 73457468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 73467468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 73477468e2c8SBruno Larsen (billionai) { 73487468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 73497468e2c8SBruno Larsen (billionai) opcode_t *opc; 73507468e2c8SBruno Larsen (billionai) 73517468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 73527468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 73537468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 73547468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 73557468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 73567468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 73577468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 73587468e2c8SBruno Larsen (billionai) opc->opc3); 73597468e2c8SBruno Larsen (billionai) return; 73607468e2c8SBruno Larsen (billionai) } 73617468e2c8SBruno Larsen (billionai) } 73627468e2c8SBruno Larsen (billionai) } 73637468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 73647468e2c8SBruno Larsen (billionai) fflush(stdout); 73657468e2c8SBruno Larsen (billionai) fflush(stderr); 73667468e2c8SBruno Larsen (billionai) } 73677468e2c8SBruno Larsen (billionai) 73687468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 73697468e2c8SBruno Larsen (billionai) { 73707468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 73717468e2c8SBruno Larsen (billionai) int i, j, k; 73727468e2c8SBruno Larsen (billionai) 73737468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 73747468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 73757468e2c8SBruno Larsen (billionai) continue; 73767468e2c8SBruno Larsen (billionai) } 73777468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 73787468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 73797468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 73807468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 73817468e2c8SBruno Larsen (billionai) continue; 73827468e2c8SBruno Larsen (billionai) } 73837468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 73847468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 73857468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 73867468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 73877468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 73887468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 73897468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 73907468e2c8SBruno Larsen (billionai) } 73917468e2c8SBruno Larsen (billionai) } 73927468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 73937468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 73947468e2c8SBruno Larsen (billionai) } 73957468e2c8SBruno Larsen (billionai) } 73967468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 73977468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 73987468e2c8SBruno Larsen (billionai) } 73997468e2c8SBruno Larsen (billionai) } 74007468e2c8SBruno Larsen (billionai) } 74017468e2c8SBruno Larsen (billionai) 74027468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 74037468e2c8SBruno Larsen (billionai) { 74047468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 74057468e2c8SBruno Larsen (billionai) 74067468e2c8SBruno Larsen (billionai) /* 74077468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 74087468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 74097468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 74107468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 74117468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 74127468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 74137468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 74147468e2c8SBruno Larsen (billionai) */ 74157468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 74167468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 74177468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 74187468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 74197468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 74207468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 74217468e2c8SBruno Larsen (billionai) } 74227468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 74237468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 74247468e2c8SBruno Larsen (billionai) return 0; 74257468e2c8SBruno Larsen (billionai) } 74267468e2c8SBruno Larsen (billionai) 7427624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7428624cb07fSRichard Henderson { 7429624cb07fSRichard Henderson opc_handler_t **table, *handler; 7430624cb07fSRichard Henderson uint32_t inval; 7431624cb07fSRichard Henderson 7432624cb07fSRichard Henderson ctx->opcode = insn; 7433624cb07fSRichard Henderson 7434624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7435624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7436624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7437624cb07fSRichard Henderson 7438624cb07fSRichard Henderson table = cpu->opcodes; 7439624cb07fSRichard Henderson handler = table[opc1(insn)]; 7440624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7441624cb07fSRichard Henderson table = ind_table(handler); 7442624cb07fSRichard Henderson handler = table[opc2(insn)]; 7443624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7444624cb07fSRichard Henderson table = ind_table(handler); 7445624cb07fSRichard Henderson handler = table[opc3(insn)]; 7446624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7447624cb07fSRichard Henderson table = ind_table(handler); 7448624cb07fSRichard Henderson handler = table[opc4(insn)]; 7449624cb07fSRichard Henderson } 7450624cb07fSRichard Henderson } 7451624cb07fSRichard Henderson } 7452624cb07fSRichard Henderson 7453624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7454624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7455624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7456624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7457624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7458624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7459624cb07fSRichard Henderson insn, ctx->cia); 7460624cb07fSRichard Henderson return false; 7461624cb07fSRichard Henderson } 7462624cb07fSRichard Henderson 7463624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7464624cb07fSRichard Henderson && Rc(insn))) { 7465624cb07fSRichard Henderson inval = handler->inval2; 7466624cb07fSRichard Henderson } else { 7467624cb07fSRichard Henderson inval = handler->inval1; 7468624cb07fSRichard Henderson } 7469624cb07fSRichard Henderson 7470624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7471624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7472624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7473624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7474624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7475624cb07fSRichard Henderson insn, ctx->cia); 7476624cb07fSRichard Henderson return false; 7477624cb07fSRichard Henderson } 7478624cb07fSRichard Henderson 7479624cb07fSRichard Henderson handler->handler(ctx); 7480624cb07fSRichard Henderson return true; 7481624cb07fSRichard Henderson } 7482624cb07fSRichard Henderson 7483b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7484fcf5ef2aSThomas Huth { 7485b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 74869c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 74872df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7488fcf5ef2aSThomas Huth 7489b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 74902df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7491d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 74922df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 74932df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7494b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7495b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7496b0c2d521SEmilio G. Cota ctx->access_type = -1; 7497d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 74982df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7499b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 75000e3bf489SRoman Kapl ctx->flags = env->flags; 7501fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 75022df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7503b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7504fcf5ef2aSThomas Huth #endif 7505e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7506d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7507fcf5ef2aSThomas Huth 75082df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 75092df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 75102df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 75112df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 75122df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7513f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 75141db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7515f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7516f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7517*8b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7518*8b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 751946d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 75202df4fe7aSRichard Henderson 7521b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 75222df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 75232df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 75249498d103SRichard Henderson ctx->base.max_insns = 1; 7525efe843d8SDavid Gibson } 75262df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7527b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7528efe843d8SDavid Gibson } 752913b45575SRichard Henderson } 7530fcf5ef2aSThomas Huth 7531b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7532b0c2d521SEmilio G. Cota { 7533b0c2d521SEmilio G. Cota } 7534fcf5ef2aSThomas Huth 7535b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7536b0c2d521SEmilio G. Cota { 7537b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7538b0c2d521SEmilio G. Cota } 7539b0c2d521SEmilio G. Cota 754099082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 754199082815SRichard Henderson { 754299082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 754399082815SRichard Henderson return opc1(insn) == 1; 754499082815SRichard Henderson } 754599082815SRichard Henderson 7546b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7547b0c2d521SEmilio G. Cota { 7548b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 754928876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7550b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 755199082815SRichard Henderson target_ulong pc; 7552624cb07fSRichard Henderson uint32_t insn; 7553624cb07fSRichard Henderson bool ok; 7554b0c2d521SEmilio G. Cota 7555fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7556fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7557b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7558b0c2d521SEmilio G. Cota 755999082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 75604e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 756199082815SRichard Henderson ctx->base.pc_next = pc += 4; 7562fcf5ef2aSThomas Huth 756399082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 756499082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 756599082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 756699082815SRichard Henderson } else if ((pc & 63) == 0) { 756799082815SRichard Henderson /* 756899082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 756999082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 757099082815SRichard Henderson * 64-byte address boundary (system alignment error). 757199082815SRichard Henderson */ 757299082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 757399082815SRichard Henderson ok = true; 757499082815SRichard Henderson } else { 75754e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 75764e116893SIlya Leoshkevich need_byteswap(ctx)); 757799082815SRichard Henderson ctx->base.pc_next = pc += 4; 757899082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 757999082815SRichard Henderson } 7580624cb07fSRichard Henderson if (!ok) { 7581624cb07fSRichard Henderson gen_invalid(ctx); 7582fcf5ef2aSThomas Huth } 7583624cb07fSRichard Henderson 758464a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 758599082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 758664a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 758764a0f644SRichard Henderson } 758864a0f644SRichard Henderson 758951eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 7590fcf5ef2aSThomas Huth } 7591b0c2d521SEmilio G. Cota 7592b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7593b0c2d521SEmilio G. Cota { 7594b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7595a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7596a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7597b0c2d521SEmilio G. Cota 7598a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7599a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 76003d8a5b69SRichard Henderson return; 76013d8a5b69SRichard Henderson } 76023d8a5b69SRichard Henderson 7603a9b5b3d0SRichard Henderson /* Honor single stepping. */ 76049498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 76059498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7606a9b5b3d0SRichard Henderson switch (is_jmp) { 7607a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7608a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7609a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7610a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7611a9b5b3d0SRichard Henderson break; 7612a9b5b3d0SRichard Henderson case DISAS_EXIT: 7613a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7614a9b5b3d0SRichard Henderson break; 7615a9b5b3d0SRichard Henderson default: 7616a9b5b3d0SRichard Henderson g_assert_not_reached(); 7617fcf5ef2aSThomas Huth } 761813b45575SRichard Henderson 7619a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7620a9b5b3d0SRichard Henderson return; 7621a9b5b3d0SRichard Henderson } 7622a9b5b3d0SRichard Henderson 7623a9b5b3d0SRichard Henderson switch (is_jmp) { 7624a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7625a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 762646d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7627a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7628a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7629a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7630a9b5b3d0SRichard Henderson break; 7631a9b5b3d0SRichard Henderson } 7632a9b5b3d0SRichard Henderson /* fall through */ 7633a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7634a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7635a9b5b3d0SRichard Henderson /* fall through */ 7636a9b5b3d0SRichard Henderson case DISAS_CHAIN: 763746d396bdSDaniel Henrique Barboza /* 763846d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 763946d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 764046d396bdSDaniel Henrique Barboza */ 764146d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 764246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 764346d396bdSDaniel Henrique Barboza } 764446d396bdSDaniel Henrique Barboza 7645a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7646a9b5b3d0SRichard Henderson break; 7647a9b5b3d0SRichard Henderson 7648a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7649a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7650a9b5b3d0SRichard Henderson /* fall through */ 7651a9b5b3d0SRichard Henderson case DISAS_EXIT: 765246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 765307ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7654a9b5b3d0SRichard Henderson break; 7655a9b5b3d0SRichard Henderson 7656a9b5b3d0SRichard Henderson default: 7657a9b5b3d0SRichard Henderson g_assert_not_reached(); 7658fcf5ef2aSThomas Huth } 7659fcf5ef2aSThomas Huth } 7660b0c2d521SEmilio G. Cota 76618eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 76628eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7663b0c2d521SEmilio G. Cota { 76648eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 76658eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7666b0c2d521SEmilio G. Cota } 7667b0c2d521SEmilio G. Cota 7668b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7669b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7670b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7671b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7672b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7673b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7674b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7675b0c2d521SEmilio G. Cota }; 7676b0c2d521SEmilio G. Cota 7677306c8721SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 7678306c8721SRichard Henderson target_ulong pc, void *host_pc) 7679b0c2d521SEmilio G. Cota { 7680b0c2d521SEmilio G. Cota DisasContext ctx; 7681b0c2d521SEmilio G. Cota 7682306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7683fcf5ef2aSThomas Huth } 7684