1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39eeaaefe9SLeandro Lupori #include "power8-pmu.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 48efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 49fcf5ef2aSThomas Huth 50fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 51fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 52fcf5ef2aSThomas Huth #else 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 54fcf5ef2aSThomas Huth #endif 55fcf5ef2aSThomas Huth /*****************************************************************************/ 56fcf5ef2aSThomas Huth /* Code translation helpers */ 57fcf5ef2aSThomas Huth 58fcf5ef2aSThomas Huth /* global register indexes */ 59fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 60fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 61fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 62fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 63fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 64fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 65fcf5ef2aSThomas Huth static TCGv cpu_nip; 66fcf5ef2aSThomas Huth static TCGv cpu_msr; 67fcf5ef2aSThomas Huth static TCGv cpu_ctr; 68fcf5ef2aSThomas Huth static TCGv cpu_lr; 69fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 70fcf5ef2aSThomas Huth static TCGv cpu_cfar; 71fcf5ef2aSThomas Huth #endif 72dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 73fcf5ef2aSThomas Huth static TCGv cpu_reserve; 74253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 75*894448aeSRichard Henderson static TCGv cpu_reserve_val2; 76fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 77fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth void ppc_translate_init(void) 82fcf5ef2aSThomas Huth { 83fcf5ef2aSThomas Huth int i; 84fcf5ef2aSThomas Huth char *p; 85fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 86fcf5ef2aSThomas Huth 87fcf5ef2aSThomas Huth p = cpu_reg_names; 88fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 91fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 92fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 93fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 94fcf5ef2aSThomas Huth p += 5; 95fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 96fcf5ef2aSThomas Huth } 97fcf5ef2aSThomas Huth 98fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 99fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 100fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 101fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 102fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 103fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 105fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 106fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 107fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 108fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth } 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 112fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 124fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 125fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 126fcf5ef2aSThomas Huth #endif 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 130fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 132fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 134fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 135fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 136dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 138dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 139dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 142fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 143fcf5ef2aSThomas Huth "reserve_addr"); 144253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 145253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 146253ce7b2SNikunj A Dadhania "reserve_val"); 147*894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 148*894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 149*894448aeSRichard Henderson "reserve_val2"); 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 152fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 155efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 156efe843d8SDavid Gibson "access_type"); 157fcf5ef2aSThomas Huth } 158fcf5ef2aSThomas Huth 159fcf5ef2aSThomas Huth /* internal defines */ 160fcf5ef2aSThomas Huth struct DisasContext { 161b6bac4bcSEmilio G. Cota DisasContextBase base; 1622c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 163fcf5ef2aSThomas Huth uint32_t opcode; 164fcf5ef2aSThomas Huth /* Routine used to access memory */ 165fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 166fcf5ef2aSThomas Huth bool lazy_tlb_flush; 167fcf5ef2aSThomas Huth bool need_access_type; 168fcf5ef2aSThomas Huth int mem_idx; 169fcf5ef2aSThomas Huth int access_type; 170fcf5ef2aSThomas Huth /* Translation flags */ 17114776ab5STony Nguyen MemOp default_tcg_memop_mask; 172fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 173fcf5ef2aSThomas Huth bool sf_mode; 174fcf5ef2aSThomas Huth bool has_cfar; 175fcf5ef2aSThomas Huth #endif 176fcf5ef2aSThomas Huth bool fpu_enabled; 177fcf5ef2aSThomas Huth bool altivec_enabled; 178fcf5ef2aSThomas Huth bool vsx_enabled; 179fcf5ef2aSThomas Huth bool spe_enabled; 180fcf5ef2aSThomas Huth bool tm_enabled; 181c6fd28fdSSuraj Jitindar Singh bool gtse; 1821db3632aSMatheus Ferst bool hr; 183f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 184f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1858b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1868b3d1c49SLeandro Lupori bool pmc_other; 18746d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 188fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 189fcf5ef2aSThomas Huth int singlestep_enabled; 1900e3bf489SRoman Kapl uint32_t flags; 191fcf5ef2aSThomas Huth uint64_t insns_flags; 192fcf5ef2aSThomas Huth uint64_t insns_flags2; 193fcf5ef2aSThomas Huth }; 194fcf5ef2aSThomas Huth 195a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 196a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 197a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 198a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 199a9b5b3d0SRichard Henderson 200fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 201fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 202fcf5ef2aSThomas Huth { 203ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 204fcf5ef2aSThomas Huth return ctx->le_mode; 205fcf5ef2aSThomas Huth #else 206fcf5ef2aSThomas Huth return !ctx->le_mode; 207fcf5ef2aSThomas Huth #endif 208fcf5ef2aSThomas Huth } 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 211fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 212fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 213fcf5ef2aSThomas Huth #else 214fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 215fcf5ef2aSThomas Huth #endif 216fcf5ef2aSThomas Huth 217fcf5ef2aSThomas Huth struct opc_handler_t { 218fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 219fcf5ef2aSThomas Huth uint32_t inval1; 220fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 221fcf5ef2aSThomas Huth uint32_t inval2; 222fcf5ef2aSThomas Huth /* instruction type */ 223fcf5ef2aSThomas Huth uint64_t type; 224fcf5ef2aSThomas Huth /* extended instruction type */ 225fcf5ef2aSThomas Huth uint64_t type2; 226fcf5ef2aSThomas Huth /* handler */ 227fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 228fcf5ef2aSThomas Huth }; 229fcf5ef2aSThomas Huth 2300e3bf489SRoman Kapl /* SPR load/store helpers */ 2310e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2320e3bf489SRoman Kapl { 2330e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2340e3bf489SRoman Kapl } 2350e3bf489SRoman Kapl 2360e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2370e3bf489SRoman Kapl { 2380e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2390e3bf489SRoman Kapl } 2400e3bf489SRoman Kapl 241fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 242fcf5ef2aSThomas Huth { 243fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 244fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 245fcf5ef2aSThomas Huth ctx->access_type = access_type; 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth } 248fcf5ef2aSThomas Huth 249fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 250fcf5ef2aSThomas Huth { 251fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 252fcf5ef2aSThomas Huth nip = (uint32_t)nip; 253fcf5ef2aSThomas Huth } 254fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 255fcf5ef2aSThomas Huth } 256fcf5ef2aSThomas Huth 257fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 258fcf5ef2aSThomas Huth { 259fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 260fcf5ef2aSThomas Huth 261efe843d8SDavid Gibson /* 262efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 263efe843d8SDavid Gibson * faulting instruction 264fcf5ef2aSThomas Huth */ 2652c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 266fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 267fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 268fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 269fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 270fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2713d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 272fcf5ef2aSThomas Huth } 273fcf5ef2aSThomas Huth 274fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 275fcf5ef2aSThomas Huth { 276fcf5ef2aSThomas Huth TCGv_i32 t0; 277fcf5ef2aSThomas Huth 278efe843d8SDavid Gibson /* 279efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 280efe843d8SDavid Gibson * faulting instruction 281fcf5ef2aSThomas Huth */ 2822c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 283fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 284fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 285fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2863d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 287fcf5ef2aSThomas Huth } 288fcf5ef2aSThomas Huth 289fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 290fcf5ef2aSThomas Huth target_ulong nip) 291fcf5ef2aSThomas Huth { 292fcf5ef2aSThomas Huth TCGv_i32 t0; 293fcf5ef2aSThomas Huth 294fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 295fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 296fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 297fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2983d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 299fcf5ef2aSThomas Huth } 300fcf5ef2aSThomas Huth 301f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 302f5b6daacSRichard Henderson { 303f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 304f5b6daacSRichard Henderson gen_io_start(); 305f5b6daacSRichard Henderson /* 306f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 307f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 308f5b6daacSRichard Henderson * decide if we need to return to the main loop. 309f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 310f5b6daacSRichard Henderson */ 311f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 312f5b6daacSRichard Henderson } 313f5b6daacSRichard Henderson } 314f5b6daacSRichard Henderson 3152fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3162fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3172fdedcbcSMatheus Ferst { 3182fdedcbcSMatheus Ferst gen_icount_io_start(ctx); 3192fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3202fdedcbcSMatheus Ferst } 3212fdedcbcSMatheus Ferst #endif 3222fdedcbcSMatheus Ferst 323e150ac89SRoman Kapl /* 324e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 325e150ac89SRoman Kapl * SPR registers for this exception. 326e150ac89SRoman Kapl * 327e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 328e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3290e3bf489SRoman Kapl */ 330e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3310e3bf489SRoman Kapl { 3320e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3330e3bf489SRoman Kapl target_ulong dbsr = 0; 334e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3350e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 336e150ac89SRoman Kapl } else { 337e150ac89SRoman Kapl /* Must have been branch */ 3380e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3390e3bf489SRoman Kapl } 3400e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3410e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3420e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3430e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3440e3bf489SRoman Kapl tcg_temp_free(t0); 3450e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3460e3bf489SRoman Kapl } else { 347e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3480e3bf489SRoman Kapl } 3490e3bf489SRoman Kapl } 3500e3bf489SRoman Kapl 351fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 352fcf5ef2aSThomas Huth { 3539498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3543d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 357fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 358fcf5ef2aSThomas Huth { 359fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 360fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 361fcf5ef2aSThomas Huth } 362fcf5ef2aSThomas Huth 363fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 364fcf5ef2aSThomas Huth { 365fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 366fcf5ef2aSThomas Huth } 367fcf5ef2aSThomas Huth 368fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 369fcf5ef2aSThomas Huth { 370fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 371fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 372fcf5ef2aSThomas Huth } 373fcf5ef2aSThomas Huth 37437f219c8SBruno Larsen (billionai) /*****************************************************************************/ 37537f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 37637f219c8SBruno Larsen (billionai) 377a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 37837f219c8SBruno Larsen (billionai) { 37937f219c8SBruno Larsen (billionai) #if 0 38037f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 38137f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 38237f219c8SBruno Larsen (billionai) #endif 38337f219c8SBruno Larsen (billionai) } 38437f219c8SBruno Larsen (billionai) 38537f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 38637f219c8SBruno Larsen (billionai) 38737f219c8SBruno Larsen (billionai) /* 38837f219c8SBruno Larsen (billionai) * Generic callbacks: 38937f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 39037f219c8SBruno Larsen (billionai) */ 39137f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 39237f219c8SBruno Larsen (billionai) { 39337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39537f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 39637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39737f219c8SBruno Larsen (billionai) #endif 39837f219c8SBruno Larsen (billionai) } 39937f219c8SBruno Larsen (billionai) 400a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 40137f219c8SBruno Larsen (billionai) { 40237f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 40337f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 40437f219c8SBruno Larsen (billionai) } 40537f219c8SBruno Larsen (billionai) 40637f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 40737f219c8SBruno Larsen (billionai) { 40837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 40937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 41037f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 41137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 41237f219c8SBruno Larsen (billionai) #endif 41337f219c8SBruno Larsen (billionai) } 41437f219c8SBruno Larsen (billionai) 415a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 41637f219c8SBruno Larsen (billionai) { 41737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 41837f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41937f219c8SBruno Larsen (billionai) } 42037f219c8SBruno Larsen (billionai) 4217aeac354SDaniel Henrique Barboza void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 4227aeac354SDaniel Henrique Barboza { 4237aeac354SDaniel Henrique Barboza spr_write_generic(ctx, sprn, gprn); 4247aeac354SDaniel Henrique Barboza 4257aeac354SDaniel Henrique Barboza /* 4267aeac354SDaniel Henrique Barboza * SPR_CTRL writes must force a new translation block, 4277aeac354SDaniel Henrique Barboza * allowing the PMU to calculate the run latch events with 4287aeac354SDaniel Henrique Barboza * more accuracy. 4297aeac354SDaniel Henrique Barboza */ 4307aeac354SDaniel Henrique Barboza ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4317aeac354SDaniel Henrique Barboza } 4327aeac354SDaniel Henrique Barboza 43337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 434a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43537f219c8SBruno Larsen (billionai) { 43637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43837f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 44137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 44237f219c8SBruno Larsen (billionai) #else 44337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 44437f219c8SBruno Larsen (billionai) #endif 44537f219c8SBruno Larsen (billionai) } 44637f219c8SBruno Larsen (billionai) 447a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 44837f219c8SBruno Larsen (billionai) { 44937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 45037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 45137f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 45237f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 45337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 45437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 45537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45637f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 45737f219c8SBruno Larsen (billionai) } 45837f219c8SBruno Larsen (billionai) 459a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 46037f219c8SBruno Larsen (billionai) { 46137f219c8SBruno Larsen (billionai) } 46237f219c8SBruno Larsen (billionai) 46337f219c8SBruno Larsen (billionai) #endif 46437f219c8SBruno Larsen (billionai) 46537f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 46637f219c8SBruno Larsen (billionai) /* XER */ 467a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 46837f219c8SBruno Larsen (billionai) { 46937f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 47037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 47137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 47237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 47337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 47437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 47537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 47637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 47737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 47837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 47937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 48037f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 48137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 48237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 48337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 48437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 48537f219c8SBruno Larsen (billionai) } 48637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 48737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 48837f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 48937f219c8SBruno Larsen (billionai) } 49037f219c8SBruno Larsen (billionai) 491a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 49237f219c8SBruno Larsen (billionai) { 49337f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 49437f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 49537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 49637f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 49737f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 49837f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 49937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 50037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 50137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 50237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 50337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 50437f219c8SBruno Larsen (billionai) } 50537f219c8SBruno Larsen (billionai) 50637f219c8SBruno Larsen (billionai) /* LR */ 507a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 50837f219c8SBruno Larsen (billionai) { 50937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 51037f219c8SBruno Larsen (billionai) } 51137f219c8SBruno Larsen (billionai) 512a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 51337f219c8SBruno Larsen (billionai) { 51437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 51537f219c8SBruno Larsen (billionai) } 51637f219c8SBruno Larsen (billionai) 51737f219c8SBruno Larsen (billionai) /* CFAR */ 51837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 519a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 52037f219c8SBruno Larsen (billionai) { 52137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 52237f219c8SBruno Larsen (billionai) } 52337f219c8SBruno Larsen (billionai) 524a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 52537f219c8SBruno Larsen (billionai) { 52637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 52737f219c8SBruno Larsen (billionai) } 52837f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 52937f219c8SBruno Larsen (billionai) 53037f219c8SBruno Larsen (billionai) /* CTR */ 531a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 53237f219c8SBruno Larsen (billionai) { 53337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 53437f219c8SBruno Larsen (billionai) } 53537f219c8SBruno Larsen (billionai) 536a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 53737f219c8SBruno Larsen (billionai) { 53837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 53937f219c8SBruno Larsen (billionai) } 54037f219c8SBruno Larsen (billionai) 54137f219c8SBruno Larsen (billionai) /* User read access to SPR */ 54237f219c8SBruno Larsen (billionai) /* USPRx */ 54337f219c8SBruno Larsen (billionai) /* UMMCRx */ 54437f219c8SBruno Larsen (billionai) /* UPMCx */ 54537f219c8SBruno Larsen (billionai) /* USIA */ 54637f219c8SBruno Larsen (billionai) /* UDECR */ 547a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 54837f219c8SBruno Larsen (billionai) { 54937f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 55037f219c8SBruno Larsen (billionai) } 55137f219c8SBruno Larsen (billionai) 55237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 553a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 55437f219c8SBruno Larsen (billionai) { 55537f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 55637f219c8SBruno Larsen (billionai) } 55737f219c8SBruno Larsen (billionai) #endif 55837f219c8SBruno Larsen (billionai) 55937f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 56037f219c8SBruno Larsen (billionai) /* DECR */ 56137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 562a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 56337f219c8SBruno Larsen (billionai) { 564f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56537f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 56637f219c8SBruno Larsen (billionai) } 56737f219c8SBruno Larsen (billionai) 568a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 56937f219c8SBruno Larsen (billionai) { 570f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57137f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 57237f219c8SBruno Larsen (billionai) } 57337f219c8SBruno Larsen (billionai) #endif 57437f219c8SBruno Larsen (billionai) 57537f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 57637f219c8SBruno Larsen (billionai) /* Time base */ 577a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 57837f219c8SBruno Larsen (billionai) { 579f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58037f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 58137f219c8SBruno Larsen (billionai) } 58237f219c8SBruno Larsen (billionai) 583a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 58437f219c8SBruno Larsen (billionai) { 585f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58637f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 58737f219c8SBruno Larsen (billionai) } 58837f219c8SBruno Larsen (billionai) 589a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 59037f219c8SBruno Larsen (billionai) { 59137f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 59237f219c8SBruno Larsen (billionai) } 59337f219c8SBruno Larsen (billionai) 594a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 59537f219c8SBruno Larsen (billionai) { 59637f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 59737f219c8SBruno Larsen (billionai) } 59837f219c8SBruno Larsen (billionai) 59937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 600a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 60137f219c8SBruno Larsen (billionai) { 602f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60337f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 60437f219c8SBruno Larsen (billionai) } 60537f219c8SBruno Larsen (billionai) 606a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 60737f219c8SBruno Larsen (billionai) { 608f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60937f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 61037f219c8SBruno Larsen (billionai) } 61137f219c8SBruno Larsen (billionai) 612a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 61337f219c8SBruno Larsen (billionai) { 61437f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 61537f219c8SBruno Larsen (billionai) } 61637f219c8SBruno Larsen (billionai) 617a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 61837f219c8SBruno Larsen (billionai) { 61937f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 62037f219c8SBruno Larsen (billionai) } 62137f219c8SBruno Larsen (billionai) 62237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 623a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 62437f219c8SBruno Larsen (billionai) { 625f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62637f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 62737f219c8SBruno Larsen (billionai) } 62837f219c8SBruno Larsen (billionai) 629a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 63037f219c8SBruno Larsen (billionai) { 631f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63237f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 63337f219c8SBruno Larsen (billionai) } 63437f219c8SBruno Larsen (billionai) 63537f219c8SBruno Larsen (billionai) /* HDECR */ 636a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 63737f219c8SBruno Larsen (billionai) { 638f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63937f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 64037f219c8SBruno Larsen (billionai) } 64137f219c8SBruno Larsen (billionai) 642a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 64337f219c8SBruno Larsen (billionai) { 644f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64537f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 64637f219c8SBruno Larsen (billionai) } 64737f219c8SBruno Larsen (billionai) 648a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 64937f219c8SBruno Larsen (billionai) { 650f5b6daacSRichard Henderson gen_icount_io_start(ctx); 65137f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 65237f219c8SBruno Larsen (billionai) } 65337f219c8SBruno Larsen (billionai) 654a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 65537f219c8SBruno Larsen (billionai) { 656f5b6daacSRichard Henderson gen_icount_io_start(ctx); 65737f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 65837f219c8SBruno Larsen (billionai) } 65937f219c8SBruno Larsen (billionai) 660a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 66137f219c8SBruno Larsen (billionai) { 662f5b6daacSRichard Henderson gen_icount_io_start(ctx); 66337f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 66437f219c8SBruno Larsen (billionai) } 66537f219c8SBruno Larsen (billionai) 66637f219c8SBruno Larsen (billionai) #endif 66737f219c8SBruno Larsen (billionai) #endif 66837f219c8SBruno Larsen (billionai) 66937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 67037f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 67137f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 672a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 67337f219c8SBruno Larsen (billionai) { 67437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 67537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 67637f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 67737f219c8SBruno Larsen (billionai) } 67837f219c8SBruno Larsen (billionai) 679a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 68037f219c8SBruno Larsen (billionai) { 68137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 68237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 68337f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 68437f219c8SBruno Larsen (billionai) } 68537f219c8SBruno Larsen (billionai) 686a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 68737f219c8SBruno Larsen (billionai) { 68837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 68937f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 69037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69137f219c8SBruno Larsen (billionai) } 69237f219c8SBruno Larsen (billionai) 693a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 69437f219c8SBruno Larsen (billionai) { 69537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 69637f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 69737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69837f219c8SBruno Larsen (billionai) } 69937f219c8SBruno Larsen (billionai) 700a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 70137f219c8SBruno Larsen (billionai) { 70237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 70337f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 70437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70537f219c8SBruno Larsen (billionai) } 70637f219c8SBruno Larsen (billionai) 707a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 70837f219c8SBruno Larsen (billionai) { 70937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 71037f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 71137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71237f219c8SBruno Larsen (billionai) } 71337f219c8SBruno Larsen (billionai) 71437f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 71537f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 716a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 71737f219c8SBruno Larsen (billionai) { 71837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 71937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 72037f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 72137f219c8SBruno Larsen (billionai) } 72237f219c8SBruno Larsen (billionai) 723a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 72437f219c8SBruno Larsen (billionai) { 72537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 72637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 72737f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 72837f219c8SBruno Larsen (billionai) } 72937f219c8SBruno Larsen (billionai) 730a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 73137f219c8SBruno Larsen (billionai) { 73237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 73337f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 73437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73537f219c8SBruno Larsen (billionai) } 73637f219c8SBruno Larsen (billionai) 737a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 73837f219c8SBruno Larsen (billionai) { 73937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 74037f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 74137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74237f219c8SBruno Larsen (billionai) } 74337f219c8SBruno Larsen (billionai) 744a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 74737f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 74837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74937f219c8SBruno Larsen (billionai) } 75037f219c8SBruno Larsen (billionai) 751a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 75237f219c8SBruno Larsen (billionai) { 75337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 75437f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 75537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75637f219c8SBruno Larsen (billionai) } 75737f219c8SBruno Larsen (billionai) 75837f219c8SBruno Larsen (billionai) /* SDR1 */ 759a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 76037f219c8SBruno Larsen (billionai) { 76137f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 76237f219c8SBruno Larsen (billionai) } 76337f219c8SBruno Larsen (billionai) 76437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 76537f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 76637f219c8SBruno Larsen (billionai) /* PIDR */ 767a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 76837f219c8SBruno Larsen (billionai) { 76937f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 772a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 77337f219c8SBruno Larsen (billionai) { 77437f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 77537f219c8SBruno Larsen (billionai) } 77637f219c8SBruno Larsen (billionai) 777a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 77837f219c8SBruno Larsen (billionai) { 77937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 78037f219c8SBruno Larsen (billionai) } 78137f219c8SBruno Larsen (billionai) 782a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 78337f219c8SBruno Larsen (billionai) { 78437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 78537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 78637f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 78737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 78837f219c8SBruno Larsen (billionai) } 789a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 79037f219c8SBruno Larsen (billionai) { 79137f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 79237f219c8SBruno Larsen (billionai) } 79337f219c8SBruno Larsen (billionai) 794a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 79537f219c8SBruno Larsen (billionai) { 79637f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 79737f219c8SBruno Larsen (billionai) } 79837f219c8SBruno Larsen (billionai) 79937f219c8SBruno Larsen (billionai) /* DPDES */ 800a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 80137f219c8SBruno Larsen (billionai) { 80237f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 80337f219c8SBruno Larsen (billionai) } 80437f219c8SBruno Larsen (billionai) 805a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 80637f219c8SBruno Larsen (billionai) { 80737f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 80837f219c8SBruno Larsen (billionai) } 80937f219c8SBruno Larsen (billionai) #endif 81037f219c8SBruno Larsen (billionai) #endif 81137f219c8SBruno Larsen (billionai) 81237f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 81337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 814a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 81537f219c8SBruno Larsen (billionai) { 816f5b6daacSRichard Henderson gen_icount_io_start(ctx); 81737f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 81837f219c8SBruno Larsen (billionai) } 81937f219c8SBruno Larsen (billionai) 820a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 82137f219c8SBruno Larsen (billionai) { 822f5b6daacSRichard Henderson gen_icount_io_start(ctx); 82337f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 82437f219c8SBruno Larsen (billionai) } 82537f219c8SBruno Larsen (billionai) 826a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 82737f219c8SBruno Larsen (billionai) { 828f5b6daacSRichard Henderson gen_icount_io_start(ctx); 82937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 83037f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 83137f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 832d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 83337f219c8SBruno Larsen (billionai) } 83437f219c8SBruno Larsen (billionai) 835a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 83637f219c8SBruno Larsen (billionai) { 837f5b6daacSRichard Henderson gen_icount_io_start(ctx); 83837f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 83937f219c8SBruno Larsen (billionai) } 84037f219c8SBruno Larsen (billionai) 841cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 842cbd8f17dSCédric Le Goater { 843cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 844cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 845cbd8f17dSCédric Le Goater } 846cbd8f17dSCédric Le Goater 847cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 848cbd8f17dSCédric Le Goater { 849cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 850cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 851cbd8f17dSCédric Le Goater } 852cbd8f17dSCédric Le Goater 853dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 854dd69d140SCédric Le Goater { 855dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 856dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 85747822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 858dd69d140SCédric Le Goater tcg_temp_free(t0); 859dd69d140SCédric Le Goater } 860dd69d140SCédric Le Goater 861a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 86237f219c8SBruno Larsen (billionai) { 863f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86437f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 86537f219c8SBruno Larsen (billionai) } 86637f219c8SBruno Larsen (billionai) 867a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 86837f219c8SBruno Larsen (billionai) { 869f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 87137f219c8SBruno Larsen (billionai) } 87237f219c8SBruno Larsen (billionai) #endif 87337f219c8SBruno Larsen (billionai) 874328c95fcSCédric Le Goater /* PIR */ 87537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 876a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 87737f219c8SBruno Larsen (billionai) { 87837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 87937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 88037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 88137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 88237f219c8SBruno Larsen (billionai) } 88337f219c8SBruno Larsen (billionai) #endif 88437f219c8SBruno Larsen (billionai) 88537f219c8SBruno Larsen (billionai) /* SPE specific registers */ 886a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 88737f219c8SBruno Larsen (billionai) { 88837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 88937f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 89037f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 89137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89237f219c8SBruno Larsen (billionai) } 89337f219c8SBruno Larsen (billionai) 894a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 89537f219c8SBruno Larsen (billionai) { 89637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 89737f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 89837f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 89937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 90037f219c8SBruno Larsen (billionai) } 90137f219c8SBruno Larsen (billionai) 90237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 90337f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 904a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 90537f219c8SBruno Larsen (billionai) { 90637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 90837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 90937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 91037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 91137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 91237f219c8SBruno Larsen (billionai) } 91337f219c8SBruno Larsen (billionai) 914a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 91537f219c8SBruno Larsen (billionai) { 91637f219c8SBruno Larsen (billionai) int sprn_offs; 91737f219c8SBruno Larsen (billionai) 91837f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 91937f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 92037f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 92137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 92237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 92337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 92437f219c8SBruno Larsen (billionai) } else { 9258e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9268e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9278e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 92837f219c8SBruno Larsen (billionai) return; 92937f219c8SBruno Larsen (billionai) } 93037f219c8SBruno Larsen (billionai) 93137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 93237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 93337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 93437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 93537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93737f219c8SBruno Larsen (billionai) } 93837f219c8SBruno Larsen (billionai) #endif 93937f219c8SBruno Larsen (billionai) 94037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 94137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 942a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 94337f219c8SBruno Larsen (billionai) { 94437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 94537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 94637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 94737f219c8SBruno Larsen (billionai) 94837f219c8SBruno Larsen (billionai) /* 94937f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 95037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 95137f219c8SBruno Larsen (billionai) */ 95237f219c8SBruno Larsen (billionai) 95337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 95437f219c8SBruno Larsen (billionai) if (ctx->pr) { 95537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 95637f219c8SBruno Larsen (billionai) } else { 95737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 95837f219c8SBruno Larsen (billionai) } 95937f219c8SBruno Larsen (billionai) 96037f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 96137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 96237f219c8SBruno Larsen (billionai) 96337f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 96437f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 96537f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 96637f219c8SBruno Larsen (billionai) 96737f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 96837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 96937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 97037f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 97137f219c8SBruno Larsen (billionai) 97237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 97337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 97437f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 97537f219c8SBruno Larsen (billionai) } 97637f219c8SBruno Larsen (billionai) 977a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 97837f219c8SBruno Larsen (billionai) { 97937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 98037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 98137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 98237f219c8SBruno Larsen (billionai) 98337f219c8SBruno Larsen (billionai) /* 98437f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 98537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 98637f219c8SBruno Larsen (billionai) */ 98737f219c8SBruno Larsen (billionai) 98837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 98937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 99037f219c8SBruno Larsen (billionai) 99137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 99237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 99337f219c8SBruno Larsen (billionai) 99437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 99537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 99637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 99737f219c8SBruno Larsen (billionai) 99837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 99937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 100037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 100137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 100237f219c8SBruno Larsen (billionai) 100337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 100437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 100537f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 100637f219c8SBruno Larsen (billionai) } 100737f219c8SBruno Larsen (billionai) 1008a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 100937f219c8SBruno Larsen (billionai) { 101037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 101137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 101237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 101337f219c8SBruno Larsen (billionai) 101437f219c8SBruno Larsen (billionai) /* 101537f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 101637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 101737f219c8SBruno Larsen (billionai) */ 101837f219c8SBruno Larsen (billionai) 101937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 102037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 102137f219c8SBruno Larsen (billionai) 102237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 102337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 102437f219c8SBruno Larsen (billionai) 102537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 102637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 102737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 102837f219c8SBruno Larsen (billionai) 102937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 103037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 103137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 103237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 103337f219c8SBruno Larsen (billionai) 103437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 103537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 103637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 103737f219c8SBruno Larsen (billionai) } 103837f219c8SBruno Larsen (billionai) #endif 103937f219c8SBruno Larsen (billionai) #endif 104037f219c8SBruno Larsen (billionai) 104137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1042a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 104337f219c8SBruno Larsen (billionai) { 104437f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 104537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 104637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 104737f219c8SBruno Larsen (billionai) } 104837f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 104937f219c8SBruno Larsen (billionai) 105037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1051a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 105237f219c8SBruno Larsen (billionai) { 105337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 105437f219c8SBruno Larsen (billionai) 105537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 105637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 105737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105837f219c8SBruno Larsen (billionai) } 105937f219c8SBruno Larsen (billionai) 1060a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 106137f219c8SBruno Larsen (billionai) { 106237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106337f219c8SBruno Larsen (billionai) 106437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 106537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 106637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 106737f219c8SBruno Larsen (billionai) } 106837f219c8SBruno Larsen (billionai) 1069a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 107037f219c8SBruno Larsen (billionai) { 107137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107237f219c8SBruno Larsen (billionai) 107337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 107437f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 107537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107737f219c8SBruno Larsen (billionai) } 107837f219c8SBruno Larsen (billionai) 1079a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 108037f219c8SBruno Larsen (billionai) { 108137f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 108237f219c8SBruno Larsen (billionai) } 108337f219c8SBruno Larsen (billionai) 1084a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 108537f219c8SBruno Larsen (billionai) { 108637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 108737f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 108837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 108937f219c8SBruno Larsen (billionai) } 1090a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 109137f219c8SBruno Larsen (billionai) { 109237f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 109337f219c8SBruno Larsen (billionai) } 1094a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 109537f219c8SBruno Larsen (billionai) { 109637f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 109737f219c8SBruno Larsen (billionai) } 109837f219c8SBruno Larsen (billionai) 109937f219c8SBruno Larsen (billionai) #endif 110037f219c8SBruno Larsen (billionai) 110137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1102a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 110337f219c8SBruno Larsen (billionai) { 110437f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 110537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 110637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 110737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 110837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 110937f219c8SBruno Larsen (billionai) tcg_temp_free(val); 111037f219c8SBruno Larsen (billionai) } 111137f219c8SBruno Larsen (billionai) 1112a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 111337f219c8SBruno Larsen (billionai) { 111437f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 111537f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 111637f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 111737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 111837f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 111937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 112037f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 112137f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 112237f219c8SBruno Larsen (billionai) } 112337f219c8SBruno Larsen (billionai) 112437f219c8SBruno Larsen (billionai) #endif 112537f219c8SBruno Larsen (billionai) 112637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 112737f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 112837f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 112937f219c8SBruno Larsen (billionai) { 113037f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 113137f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 113237f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 113337f219c8SBruno Larsen (billionai) 113437f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 113537f219c8SBruno Larsen (billionai) 113637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 113737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 113837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 113937f219c8SBruno Larsen (billionai) } 114037f219c8SBruno Larsen (billionai) 114137f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 114237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114337f219c8SBruno Larsen (billionai) { 114437f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 114537f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 114637f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 114737f219c8SBruno Larsen (billionai) 114837f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 114937f219c8SBruno Larsen (billionai) 115037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 115137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 115237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 115337f219c8SBruno Larsen (billionai) } 115437f219c8SBruno Larsen (billionai) 1155a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 115637f219c8SBruno Larsen (billionai) { 115737f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 115837f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 115937f219c8SBruno Larsen (billionai) 116037f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 116137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 116237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 116337f219c8SBruno Larsen (billionai) 116437f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 116537f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 116637f219c8SBruno Larsen (billionai) } 116737f219c8SBruno Larsen (billionai) 1168a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 116937f219c8SBruno Larsen (billionai) { 117037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 117137f219c8SBruno Larsen (billionai) 117237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 117337f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 117437f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 117537f219c8SBruno Larsen (billionai) 117637f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 117737f219c8SBruno Larsen (billionai) } 117837f219c8SBruno Larsen (billionai) 117937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1180a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 118137f219c8SBruno Larsen (billionai) { 118237f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 118337f219c8SBruno Larsen (billionai) 118437f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 118537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 118637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 118737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 118837f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 118937f219c8SBruno Larsen (billionai) } 119037f219c8SBruno Larsen (billionai) 1191a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 119237f219c8SBruno Larsen (billionai) { 119337f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 119437f219c8SBruno Larsen (billionai) } 119537f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 119637f219c8SBruno Larsen (billionai) 1197a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 119837f219c8SBruno Larsen (billionai) { 119937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 120037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 120137f219c8SBruno Larsen (billionai) } 120237f219c8SBruno Larsen (billionai) 1203a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 120437f219c8SBruno Larsen (billionai) { 120537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 120637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 120737f219c8SBruno Larsen (billionai) } 120837f219c8SBruno Larsen (billionai) 1209a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 121037f219c8SBruno Larsen (billionai) { 121137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121237f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 121337f219c8SBruno Larsen (billionai) } 121437f219c8SBruno Larsen (billionai) 1215a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 121637f219c8SBruno Larsen (billionai) { 121737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 121937f219c8SBruno Larsen (billionai) } 122037f219c8SBruno Larsen (billionai) 1221a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 122237f219c8SBruno Larsen (billionai) { 122337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122437f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 122537f219c8SBruno Larsen (billionai) } 122637f219c8SBruno Larsen (billionai) 1227a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 122837f219c8SBruno Larsen (billionai) { 122937f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123037f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 123137f219c8SBruno Larsen (billionai) } 123237f219c8SBruno Larsen (billionai) 1233a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 123437f219c8SBruno Larsen (billionai) { 123537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123737f219c8SBruno Larsen (billionai) } 123837f219c8SBruno Larsen (billionai) 1239a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 124037f219c8SBruno Larsen (billionai) { 124137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124337f219c8SBruno Larsen (billionai) } 124437f219c8SBruno Larsen (billionai) 1245a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 124637f219c8SBruno Larsen (billionai) { 124737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124937f219c8SBruno Larsen (billionai) } 125037f219c8SBruno Larsen (billionai) 1251a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 125237f219c8SBruno Larsen (billionai) { 125337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125537f219c8SBruno Larsen (billionai) } 1256395b5d5bSNicholas Miehlbradt 1257395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1258395b5d5bSNicholas Miehlbradt { 1259395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1260395b5d5bSNicholas Miehlbradt 1261395b5d5bSNicholas Miehlbradt /* 1262395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1263395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1264395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1265395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1266395b5d5bSNicholas Miehlbradt * 1267395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1268395b5d5bSNicholas Miehlbradt */ 1269395b5d5bSNicholas Miehlbradt 1270395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1271395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1272395b5d5bSNicholas Miehlbradt 1273395b5d5bSNicholas Miehlbradt tcg_temp_free(t0); 1274395b5d5bSNicholas Miehlbradt } 127537f219c8SBruno Larsen (billionai) #endif 127637f219c8SBruno Larsen (billionai) 1277fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1278fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1279fcf5ef2aSThomas Huth 1280fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1281fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1282fcf5ef2aSThomas Huth 1283fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1284fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1285fcf5ef2aSThomas Huth 1286fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1287fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1288fcf5ef2aSThomas Huth 1289fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1290fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1291fcf5ef2aSThomas Huth 1292fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1293fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1294fcf5ef2aSThomas Huth 1295fcf5ef2aSThomas Huth typedef struct opcode_t { 1296fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1297fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1298fcf5ef2aSThomas Huth unsigned char pad[4]; 1299fcf5ef2aSThomas Huth #endif 1300fcf5ef2aSThomas Huth opc_handler_t handler; 1301fcf5ef2aSThomas Huth const char *oname; 1302fcf5ef2aSThomas Huth } opcode_t; 1303fcf5ef2aSThomas Huth 13049f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 13059f0cf041SMatheus Ferst { 13069f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 13079f0cf041SMatheus Ferst } 13089f0cf041SMatheus Ferst 1309fcf5ef2aSThomas Huth /* Helpers for priv. check */ 13109f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1311fcf5ef2aSThomas Huth do { \ 13129f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1313fcf5ef2aSThomas Huth } while (0) 1314fcf5ef2aSThomas Huth 1315fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 13169f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 13179f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 13189f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1319fcf5ef2aSThomas Huth #else 13209f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1321fcf5ef2aSThomas Huth do { \ 1322fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 13239f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1324fcf5ef2aSThomas Huth } \ 1325fcf5ef2aSThomas Huth } while (0) 13269f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1327fcf5ef2aSThomas Huth do { \ 1328fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13299f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1330fcf5ef2aSThomas Huth } \ 1331fcf5ef2aSThomas Huth } while (0) 13329f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1333fcf5ef2aSThomas Huth do { \ 1334fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13359f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1336fcf5ef2aSThomas Huth } \ 1337fcf5ef2aSThomas Huth } while (0) 1338fcf5ef2aSThomas Huth #endif 1339fcf5ef2aSThomas Huth 13409f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1341fcf5ef2aSThomas Huth 1342fcf5ef2aSThomas Huth /*****************************************************************************/ 1343fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1344fcf5ef2aSThomas Huth 1345fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1346fcf5ef2aSThomas Huth { \ 1347fcf5ef2aSThomas Huth .opc1 = op1, \ 1348fcf5ef2aSThomas Huth .opc2 = op2, \ 1349fcf5ef2aSThomas Huth .opc3 = op3, \ 1350fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1351fcf5ef2aSThomas Huth .handler = { \ 1352fcf5ef2aSThomas Huth .inval1 = invl, \ 1353fcf5ef2aSThomas Huth .type = _typ, \ 1354fcf5ef2aSThomas Huth .type2 = _typ2, \ 1355fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1356fcf5ef2aSThomas Huth }, \ 1357fcf5ef2aSThomas Huth .oname = stringify(name), \ 1358fcf5ef2aSThomas Huth } 1359fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1360fcf5ef2aSThomas Huth { \ 1361fcf5ef2aSThomas Huth .opc1 = op1, \ 1362fcf5ef2aSThomas Huth .opc2 = op2, \ 1363fcf5ef2aSThomas Huth .opc3 = op3, \ 1364fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1365fcf5ef2aSThomas Huth .handler = { \ 1366fcf5ef2aSThomas Huth .inval1 = invl1, \ 1367fcf5ef2aSThomas Huth .inval2 = invl2, \ 1368fcf5ef2aSThomas Huth .type = _typ, \ 1369fcf5ef2aSThomas Huth .type2 = _typ2, \ 1370fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1371fcf5ef2aSThomas Huth }, \ 1372fcf5ef2aSThomas Huth .oname = stringify(name), \ 1373fcf5ef2aSThomas Huth } 1374fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1375fcf5ef2aSThomas Huth { \ 1376fcf5ef2aSThomas Huth .opc1 = op1, \ 1377fcf5ef2aSThomas Huth .opc2 = op2, \ 1378fcf5ef2aSThomas Huth .opc3 = op3, \ 1379fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1380fcf5ef2aSThomas Huth .handler = { \ 1381fcf5ef2aSThomas Huth .inval1 = invl, \ 1382fcf5ef2aSThomas Huth .type = _typ, \ 1383fcf5ef2aSThomas Huth .type2 = _typ2, \ 1384fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1385fcf5ef2aSThomas Huth }, \ 1386fcf5ef2aSThomas Huth .oname = onam, \ 1387fcf5ef2aSThomas Huth } 1388fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1389fcf5ef2aSThomas Huth { \ 1390fcf5ef2aSThomas Huth .opc1 = op1, \ 1391fcf5ef2aSThomas Huth .opc2 = op2, \ 1392fcf5ef2aSThomas Huth .opc3 = op3, \ 1393fcf5ef2aSThomas Huth .opc4 = op4, \ 1394fcf5ef2aSThomas Huth .handler = { \ 1395fcf5ef2aSThomas Huth .inval1 = invl, \ 1396fcf5ef2aSThomas Huth .type = _typ, \ 1397fcf5ef2aSThomas Huth .type2 = _typ2, \ 1398fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1399fcf5ef2aSThomas Huth }, \ 1400fcf5ef2aSThomas Huth .oname = stringify(name), \ 1401fcf5ef2aSThomas Huth } 1402fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1403fcf5ef2aSThomas Huth { \ 1404fcf5ef2aSThomas Huth .opc1 = op1, \ 1405fcf5ef2aSThomas Huth .opc2 = op2, \ 1406fcf5ef2aSThomas Huth .opc3 = op3, \ 1407fcf5ef2aSThomas Huth .opc4 = op4, \ 1408fcf5ef2aSThomas Huth .handler = { \ 1409fcf5ef2aSThomas Huth .inval1 = invl, \ 1410fcf5ef2aSThomas Huth .type = _typ, \ 1411fcf5ef2aSThomas Huth .type2 = _typ2, \ 1412fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1413fcf5ef2aSThomas Huth }, \ 1414fcf5ef2aSThomas Huth .oname = onam, \ 1415fcf5ef2aSThomas Huth } 1416fcf5ef2aSThomas Huth 1417fcf5ef2aSThomas Huth /* Invalid instruction */ 1418fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1419fcf5ef2aSThomas Huth { 1420fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1421fcf5ef2aSThomas Huth } 1422fcf5ef2aSThomas Huth 1423fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1424fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1425fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1426fcf5ef2aSThomas Huth .type = PPC_NONE, 1427fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1428fcf5ef2aSThomas Huth .handler = gen_invalid, 1429fcf5ef2aSThomas Huth }; 1430fcf5ef2aSThomas Huth 1431fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1432fcf5ef2aSThomas Huth 1433fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1434fcf5ef2aSThomas Huth { 1435fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1436b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1437b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1438fcf5ef2aSThomas Huth 1439b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1440b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1441efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1442efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1443b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1444efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1445efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1446b62b3686Spbonzini@redhat.com 1447b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1448fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1449b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1450fcf5ef2aSThomas Huth 1451fcf5ef2aSThomas Huth tcg_temp_free(t0); 1452b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1453b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1454fcf5ef2aSThomas Huth } 1455fcf5ef2aSThomas Huth 1456fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1457fcf5ef2aSThomas Huth { 1458fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1459fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1460fcf5ef2aSThomas Huth tcg_temp_free(t0); 1461fcf5ef2aSThomas Huth } 1462fcf5ef2aSThomas Huth 1463fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1464fcf5ef2aSThomas Huth { 1465fcf5ef2aSThomas Huth TCGv t0, t1; 1466fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1467fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1468fcf5ef2aSThomas Huth if (s) { 1469fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1470fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1471fcf5ef2aSThomas Huth } else { 1472fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1473fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1474fcf5ef2aSThomas Huth } 1475fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1476fcf5ef2aSThomas Huth tcg_temp_free(t1); 1477fcf5ef2aSThomas Huth tcg_temp_free(t0); 1478fcf5ef2aSThomas Huth } 1479fcf5ef2aSThomas Huth 1480fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1481fcf5ef2aSThomas Huth { 1482fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1483fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1484fcf5ef2aSThomas Huth tcg_temp_free(t0); 1485fcf5ef2aSThomas Huth } 1486fcf5ef2aSThomas Huth 1487fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1488fcf5ef2aSThomas Huth { 1489fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1490fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1491fcf5ef2aSThomas Huth } else { 1492fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1493fcf5ef2aSThomas Huth } 1494fcf5ef2aSThomas Huth } 1495fcf5ef2aSThomas Huth 1496fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1497fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1498fcf5ef2aSThomas Huth { 1499fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1500fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1501fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1502fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1503fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1504fcf5ef2aSThomas Huth 1505fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1506fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1507fcf5ef2aSThomas Huth 1508fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1509fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1510fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1511fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1512fcf5ef2aSThomas Huth 1513fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1514fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1515fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1516fcf5ef2aSThomas Huth 1517fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1518fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1519fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1520fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1521fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1522fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1523fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1524fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1525fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1526fcf5ef2aSThomas Huth } 1527efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1528fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1529fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1530fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1531fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1532fcf5ef2aSThomas Huth } 1533fcf5ef2aSThomas Huth 1534fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1535fcf5ef2aSThomas Huth /* cmpeqb */ 1536fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1537fcf5ef2aSThomas Huth { 1538fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1539fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1540fcf5ef2aSThomas Huth } 1541fcf5ef2aSThomas Huth #endif 1542fcf5ef2aSThomas Huth 1543fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1544fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1545fcf5ef2aSThomas Huth { 1546fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1547fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1548fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1549fcf5ef2aSThomas Huth TCGv zr; 1550fcf5ef2aSThomas Huth 1551fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1552fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1553fcf5ef2aSThomas Huth 1554fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1555fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1556fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1557fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1558fcf5ef2aSThomas Huth tcg_temp_free(zr); 1559fcf5ef2aSThomas Huth tcg_temp_free(t0); 1560fcf5ef2aSThomas Huth } 1561fcf5ef2aSThomas Huth 1562fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1563fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1564fcf5ef2aSThomas Huth { 1565fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1566fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1567fcf5ef2aSThomas Huth } 1568fcf5ef2aSThomas Huth 1569fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1570fcf5ef2aSThomas Huth 1571fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1572fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1573fcf5ef2aSThomas Huth { 1574fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1575fcf5ef2aSThomas Huth 1576fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1577fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1578fcf5ef2aSThomas Huth if (sub) { 1579fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1580fcf5ef2aSThomas Huth } else { 1581fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1582fcf5ef2aSThomas Huth } 1583fcf5ef2aSThomas Huth tcg_temp_free(t0); 1584fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1585dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1586dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1587dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1588fcf5ef2aSThomas Huth } 1589dc0ad844SNikunj A Dadhania } else { 1590dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1591dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1592dc0ad844SNikunj A Dadhania } 159338a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1594dc0ad844SNikunj A Dadhania } 1595fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1596fcf5ef2aSThomas Huth } 1597fcf5ef2aSThomas Huth 15986b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15996b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 16004c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 16016b10d008SNikunj A Dadhania { 16026b10d008SNikunj A Dadhania TCGv t0; 16036b10d008SNikunj A Dadhania 16046b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16056b10d008SNikunj A Dadhania return; 16066b10d008SNikunj A Dadhania } 16076b10d008SNikunj A Dadhania 16086b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 160933903d0aSNikunj A Dadhania if (sub) { 161033903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 161133903d0aSNikunj A Dadhania } else { 16126b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 161333903d0aSNikunj A Dadhania } 16146b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16154c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16166b10d008SNikunj A Dadhania tcg_temp_free(t0); 16176b10d008SNikunj A Dadhania } 16186b10d008SNikunj A Dadhania 1619fcf5ef2aSThomas Huth /* Common add function */ 1620fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16214c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16224c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1623fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1624fcf5ef2aSThomas Huth { 1625fcf5ef2aSThomas Huth TCGv t0 = ret; 1626fcf5ef2aSThomas Huth 1627fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1628fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1629fcf5ef2aSThomas Huth } 1630fcf5ef2aSThomas Huth 1631fcf5ef2aSThomas Huth if (compute_ca) { 1632fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1633efe843d8SDavid Gibson /* 1634efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1635efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1636efe843d8SDavid Gibson * produce the carry into bit 32. 1637efe843d8SDavid Gibson */ 1638fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1639fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1640fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1641fcf5ef2aSThomas Huth if (add_ca) { 16424c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1643fcf5ef2aSThomas Huth } 16444c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1645fcf5ef2aSThomas Huth tcg_temp_free(t1); 16464c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16476b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16484c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16496b10d008SNikunj A Dadhania } 1650fcf5ef2aSThomas Huth } else { 1651fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1652fcf5ef2aSThomas Huth if (add_ca) { 16534c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16544c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1655fcf5ef2aSThomas Huth } else { 16564c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1657fcf5ef2aSThomas Huth } 16584c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1659fcf5ef2aSThomas Huth tcg_temp_free(zero); 1660fcf5ef2aSThomas Huth } 1661fcf5ef2aSThomas Huth } else { 1662fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1663fcf5ef2aSThomas Huth if (add_ca) { 16644c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1665fcf5ef2aSThomas Huth } 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth 1668fcf5ef2aSThomas Huth if (compute_ov) { 1669fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1672fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1673fcf5ef2aSThomas Huth } 1674fcf5ef2aSThomas Huth 167511f4e8f8SRichard Henderson if (t0 != ret) { 1676fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1677fcf5ef2aSThomas Huth tcg_temp_free(t0); 1678fcf5ef2aSThomas Huth } 1679fcf5ef2aSThomas Huth } 1680fcf5ef2aSThomas Huth /* Add functions with two operands */ 16814c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1682fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1683fcf5ef2aSThomas Huth { \ 1684fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1685fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16864c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1687fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1688fcf5ef2aSThomas Huth } 1689fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16904c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1691fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1692fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1693fcf5ef2aSThomas Huth { \ 1694fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1695fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1696fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16974c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1698fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1699fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1700fcf5ef2aSThomas Huth } 1701fcf5ef2aSThomas Huth 1702fcf5ef2aSThomas Huth /* add add. addo addo. */ 17034c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17044c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1705fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17064c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17074c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1708fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17094c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17104c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1711fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17124c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17134c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17144c5920afSSuraj Jitindar Singh /* addex */ 17154c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1716fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17174c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17184c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1719fcf5ef2aSThomas Huth /* addic addic.*/ 1720fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1721fcf5ef2aSThomas Huth { 1722fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1723fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17244c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1725fcf5ef2aSThomas Huth tcg_temp_free(c); 1726fcf5ef2aSThomas Huth } 1727fcf5ef2aSThomas Huth 1728fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1729fcf5ef2aSThomas Huth { 1730fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1731fcf5ef2aSThomas Huth } 1732fcf5ef2aSThomas Huth 1733fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1734fcf5ef2aSThomas Huth { 1735fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1736fcf5ef2aSThomas Huth } 1737fcf5ef2aSThomas Huth 1738fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1739fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1740fcf5ef2aSThomas Huth { 1741fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1742fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1743fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1744fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1745fcf5ef2aSThomas Huth 1746fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1747fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1748fcf5ef2aSThomas Huth if (sign) { 1749fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1750fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1751fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1752fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1753fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1754fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1755fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1756fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1757fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1758fcf5ef2aSThomas Huth } else { 1759fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1760fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1761fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1762fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1763fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1764fcf5ef2aSThomas Huth } 1765fcf5ef2aSThomas Huth if (compute_ov) { 1766fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1767c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1768c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1769c44027ffSNikunj A Dadhania } 1770fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1771fcf5ef2aSThomas Huth } 1772fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1773fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1774fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1775fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1776fcf5ef2aSThomas Huth 1777efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1778fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1779fcf5ef2aSThomas Huth } 1780efe843d8SDavid Gibson } 1781fcf5ef2aSThomas Huth /* Div functions */ 1782fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1783fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1784fcf5ef2aSThomas Huth { \ 1785fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1786fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1787fcf5ef2aSThomas Huth sign, compute_ov); \ 1788fcf5ef2aSThomas Huth } 1789fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1790fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1791fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1792fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1793fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1794fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1795fcf5ef2aSThomas Huth 1796fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1797fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1798fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1799fcf5ef2aSThomas Huth { \ 1800fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1801fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1802fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1803fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1804fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1805fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1806fcf5ef2aSThomas Huth } \ 1807fcf5ef2aSThomas Huth } 1808fcf5ef2aSThomas Huth 1809fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1810fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1811fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1812fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1813fcf5ef2aSThomas Huth 1814fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1815fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1816fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1817fcf5ef2aSThomas Huth { 1818fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1819fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1820fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1821fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1822fcf5ef2aSThomas Huth 1823fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1824fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1825fcf5ef2aSThomas Huth if (sign) { 1826fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1827fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1828fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1829fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1830fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1831fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1832fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1833fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1834fcf5ef2aSThomas Huth } else { 1835fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1836fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1837fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1838fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1839fcf5ef2aSThomas Huth } 1840fcf5ef2aSThomas Huth if (compute_ov) { 1841fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1842c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1843c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1844c44027ffSNikunj A Dadhania } 1845fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1846fcf5ef2aSThomas Huth } 1847fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1848fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1849fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1850fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1851fcf5ef2aSThomas Huth 1852efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1853fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1854fcf5ef2aSThomas Huth } 1855efe843d8SDavid Gibson } 1856fcf5ef2aSThomas Huth 1857fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1858fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1859fcf5ef2aSThomas Huth { \ 1860fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1861fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1862fcf5ef2aSThomas Huth sign, compute_ov); \ 1863fcf5ef2aSThomas Huth } 1864c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1865fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1866fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1867c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1868fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1869fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1870fcf5ef2aSThomas Huth 1871fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1872fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1873fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1874fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1875fcf5ef2aSThomas Huth #endif 1876fcf5ef2aSThomas Huth 1877fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1878fcf5ef2aSThomas Huth TCGv arg2, int sign) 1879fcf5ef2aSThomas Huth { 1880fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1881fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1882fcf5ef2aSThomas Huth 1883fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1884fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1885fcf5ef2aSThomas Huth if (sign) { 1886fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1887fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1888fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1889fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1890fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1891fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1892fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1893fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1894fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1895fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1896fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1897fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1898fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1899fcf5ef2aSThomas Huth } else { 1900fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1901fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1902fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1903fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1904fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1905fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1906fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1907fcf5ef2aSThomas Huth } 1908fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1909fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1910fcf5ef2aSThomas Huth } 1911fcf5ef2aSThomas Huth 1912fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1913fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1914fcf5ef2aSThomas Huth { \ 1915fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1916fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1917fcf5ef2aSThomas Huth sign); \ 1918fcf5ef2aSThomas Huth } 1919fcf5ef2aSThomas Huth 1920fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1921fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1922fcf5ef2aSThomas Huth 1923fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1924fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1925fcf5ef2aSThomas Huth TCGv arg2, int sign) 1926fcf5ef2aSThomas Huth { 1927fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1928fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1929fcf5ef2aSThomas Huth 1930fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1931fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1932fcf5ef2aSThomas Huth if (sign) { 1933fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1934fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1935fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1936fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1937fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1938fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1939fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1940fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1941fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1942fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1943fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1944fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1945fcf5ef2aSThomas Huth } else { 1946fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1947fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1948fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1949fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1950fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1951fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1952fcf5ef2aSThomas Huth } 1953fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1954fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1955fcf5ef2aSThomas Huth } 1956fcf5ef2aSThomas Huth 1957fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1958fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1959fcf5ef2aSThomas Huth { \ 1960fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1961fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1962fcf5ef2aSThomas Huth sign); \ 1963fcf5ef2aSThomas Huth } 1964fcf5ef2aSThomas Huth 1965fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1966fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1967fcf5ef2aSThomas Huth #endif 1968fcf5ef2aSThomas Huth 1969fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1970fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1971fcf5ef2aSThomas Huth { 1972fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1973fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1974fcf5ef2aSThomas Huth 1975fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1976fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1977fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1978fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1979fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1980fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1981efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1982fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1983fcf5ef2aSThomas Huth } 1984efe843d8SDavid Gibson } 1985fcf5ef2aSThomas Huth 1986fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1987fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1988fcf5ef2aSThomas Huth { 1989fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1990fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1991fcf5ef2aSThomas Huth 1992fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1993fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1994fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1995fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1996fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1997fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1998efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1999fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2000fcf5ef2aSThomas Huth } 2001efe843d8SDavid Gibson } 2002fcf5ef2aSThomas Huth 2003fcf5ef2aSThomas Huth /* mullw mullw. */ 2004fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2005fcf5ef2aSThomas Huth { 2006fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2007fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2008fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2009fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2010fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2011fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2012fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2013fcf5ef2aSThomas Huth tcg_temp_free(t0); 2014fcf5ef2aSThomas Huth tcg_temp_free(t1); 2015fcf5ef2aSThomas Huth #else 2016fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2017fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2018fcf5ef2aSThomas Huth #endif 2019efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2020fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2021fcf5ef2aSThomas Huth } 2022efe843d8SDavid Gibson } 2023fcf5ef2aSThomas Huth 2024fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2025fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2026fcf5ef2aSThomas Huth { 2027fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2028fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2029fcf5ef2aSThomas Huth 2030fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2031fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2032fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2033fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2034fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2035fcf5ef2aSThomas Huth #else 2036fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2037fcf5ef2aSThomas Huth #endif 2038fcf5ef2aSThomas Huth 2039fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2040fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2041fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 204261aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 204361aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 204461aa9a69SNikunj A Dadhania } 2045fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2046fcf5ef2aSThomas Huth 2047fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2048fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2049efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2050fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2051fcf5ef2aSThomas Huth } 2052efe843d8SDavid Gibson } 2053fcf5ef2aSThomas Huth 2054fcf5ef2aSThomas Huth /* mulli */ 2055fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2056fcf5ef2aSThomas Huth { 2057fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2058fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2059fcf5ef2aSThomas Huth } 2060fcf5ef2aSThomas Huth 2061fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2062fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2063fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2064fcf5ef2aSThomas Huth { 2065fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2066fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2067fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2068fcf5ef2aSThomas Huth tcg_temp_free(lo); 2069fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2070fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2071fcf5ef2aSThomas Huth } 2072fcf5ef2aSThomas Huth } 2073fcf5ef2aSThomas Huth 2074fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2075fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2076fcf5ef2aSThomas Huth { 2077fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2078fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2079fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2080fcf5ef2aSThomas Huth tcg_temp_free(lo); 2081fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2082fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2083fcf5ef2aSThomas Huth } 2084fcf5ef2aSThomas Huth } 2085fcf5ef2aSThomas Huth 2086fcf5ef2aSThomas Huth /* mulld mulld. */ 2087fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2088fcf5ef2aSThomas Huth { 2089fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2090fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2091efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2092fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2093fcf5ef2aSThomas Huth } 2094efe843d8SDavid Gibson } 2095fcf5ef2aSThomas Huth 2096fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2097fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2098fcf5ef2aSThomas Huth { 2099fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2100fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2101fcf5ef2aSThomas Huth 2102fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2103fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2104fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2105fcf5ef2aSThomas Huth 2106fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2107fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 210861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 210961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 211061aa9a69SNikunj A Dadhania } 2111fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2112fcf5ef2aSThomas Huth 2113fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2114fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2115fcf5ef2aSThomas Huth 2116fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2117fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2118fcf5ef2aSThomas Huth } 2119fcf5ef2aSThomas Huth } 2120fcf5ef2aSThomas Huth #endif 2121fcf5ef2aSThomas Huth 2122fcf5ef2aSThomas Huth /* Common subf function */ 2123fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2124fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2125fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2126fcf5ef2aSThomas Huth { 2127fcf5ef2aSThomas Huth TCGv t0 = ret; 2128fcf5ef2aSThomas Huth 2129fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2130fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2131fcf5ef2aSThomas Huth } 2132fcf5ef2aSThomas Huth 2133fcf5ef2aSThomas Huth if (compute_ca) { 2134fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2135fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2136efe843d8SDavid Gibson /* 2137efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2138efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2139efe843d8SDavid Gibson * produce the carry into bit 32. 2140efe843d8SDavid Gibson */ 2141fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2142fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2143fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2144fcf5ef2aSThomas Huth if (add_ca) { 2145fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2146fcf5ef2aSThomas Huth } else { 2147fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2148fcf5ef2aSThomas Huth } 2149fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2150fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2151fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2152fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2153fcf5ef2aSThomas Huth tcg_temp_free(t1); 2154e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 215533903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 215633903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 215733903d0aSNikunj A Dadhania } 2158fcf5ef2aSThomas Huth } else if (add_ca) { 2159fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2160fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2161fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2162fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2163fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21644c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2165fcf5ef2aSThomas Huth tcg_temp_free(zero); 2166fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2167fcf5ef2aSThomas Huth } else { 2168fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2169fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21704c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2171fcf5ef2aSThomas Huth } 2172fcf5ef2aSThomas Huth } else if (add_ca) { 2173efe843d8SDavid Gibson /* 2174efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2175efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2176efe843d8SDavid Gibson */ 2177fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2178fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2179fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2180fcf5ef2aSThomas Huth } else { 2181fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2182fcf5ef2aSThomas Huth } 2183fcf5ef2aSThomas Huth 2184fcf5ef2aSThomas Huth if (compute_ov) { 2185fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2186fcf5ef2aSThomas Huth } 2187fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2188fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2189fcf5ef2aSThomas Huth } 2190fcf5ef2aSThomas Huth 219111f4e8f8SRichard Henderson if (t0 != ret) { 2192fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2193fcf5ef2aSThomas Huth tcg_temp_free(t0); 2194fcf5ef2aSThomas Huth } 2195fcf5ef2aSThomas Huth } 2196fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2197fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2198fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2199fcf5ef2aSThomas Huth { \ 2200fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2201fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2202fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2203fcf5ef2aSThomas Huth } 2204fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2205fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2206fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2207fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2208fcf5ef2aSThomas Huth { \ 2209fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2210fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2211fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2212fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2213fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2214fcf5ef2aSThomas Huth } 2215fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2216fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2217fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2218fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2219fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2220fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2221fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2222fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2223fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2224fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2225fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2226fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2227fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2228fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2229fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2230fcf5ef2aSThomas Huth 2231fcf5ef2aSThomas Huth /* subfic */ 2232fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2233fcf5ef2aSThomas Huth { 2234fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2235fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2236fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2237fcf5ef2aSThomas Huth tcg_temp_free(c); 2238fcf5ef2aSThomas Huth } 2239fcf5ef2aSThomas Huth 2240fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2241fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2242fcf5ef2aSThomas Huth { 2243fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2244fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2245fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2246fcf5ef2aSThomas Huth tcg_temp_free(zero); 2247fcf5ef2aSThomas Huth } 2248fcf5ef2aSThomas Huth 2249fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2250fcf5ef2aSThomas Huth { 22511480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22521480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22531480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22541480d71cSNikunj A Dadhania } 2255fcf5ef2aSThomas Huth } 2256fcf5ef2aSThomas Huth 2257fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2258fcf5ef2aSThomas Huth { 2259fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2260fcf5ef2aSThomas Huth } 2261fcf5ef2aSThomas Huth 2262fcf5ef2aSThomas Huth /*** Integer logical ***/ 2263fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2264fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2265fcf5ef2aSThomas Huth { \ 2266fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2267fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2268fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2269fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2270fcf5ef2aSThomas Huth } 2271fcf5ef2aSThomas Huth 2272fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2273fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2274fcf5ef2aSThomas Huth { \ 2275fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2276fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2277fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2278fcf5ef2aSThomas Huth } 2279fcf5ef2aSThomas Huth 2280fcf5ef2aSThomas Huth /* and & and. */ 2281fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2282fcf5ef2aSThomas Huth /* andc & andc. */ 2283fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2284fcf5ef2aSThomas Huth 2285fcf5ef2aSThomas Huth /* andi. */ 2286fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2287fcf5ef2aSThomas Huth { 2288efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2289efe843d8SDavid Gibson UIMM(ctx->opcode)); 2290fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2291fcf5ef2aSThomas Huth } 2292fcf5ef2aSThomas Huth 2293fcf5ef2aSThomas Huth /* andis. */ 2294fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2295fcf5ef2aSThomas Huth { 2296efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2297efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2298fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2299fcf5ef2aSThomas Huth } 2300fcf5ef2aSThomas Huth 2301fcf5ef2aSThomas Huth /* cntlzw */ 2302fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2303fcf5ef2aSThomas Huth { 23049b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23059b8514e5SRichard Henderson 23069b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23079b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23089b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23099b8514e5SRichard Henderson tcg_temp_free_i32(t); 23109b8514e5SRichard Henderson 2311efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2312fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2313fcf5ef2aSThomas Huth } 2314efe843d8SDavid Gibson } 2315fcf5ef2aSThomas Huth 2316fcf5ef2aSThomas Huth /* cnttzw */ 2317fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2318fcf5ef2aSThomas Huth { 23199b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23209b8514e5SRichard Henderson 23219b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23229b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23239b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23249b8514e5SRichard Henderson tcg_temp_free_i32(t); 23259b8514e5SRichard Henderson 2326fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2327fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2328fcf5ef2aSThomas Huth } 2329fcf5ef2aSThomas Huth } 2330fcf5ef2aSThomas Huth 2331fcf5ef2aSThomas Huth /* eqv & eqv. */ 2332fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2333fcf5ef2aSThomas Huth /* extsb & extsb. */ 2334fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2335fcf5ef2aSThomas Huth /* extsh & extsh. */ 2336fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2337fcf5ef2aSThomas Huth /* nand & nand. */ 2338fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2339fcf5ef2aSThomas Huth /* nor & nor. */ 2340fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2341fcf5ef2aSThomas Huth 2342fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2343fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2344fcf5ef2aSThomas Huth { 2345fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2346fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2347fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2348fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2349fcf5ef2aSThomas Huth 2350fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2351b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2352fcf5ef2aSThomas Huth } 2353fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2354fcf5ef2aSThomas Huth 2355fcf5ef2aSThomas Huth /* or & or. */ 2356fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2357fcf5ef2aSThomas Huth { 2358fcf5ef2aSThomas Huth int rs, ra, rb; 2359fcf5ef2aSThomas Huth 2360fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2361fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2362fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2363fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2364fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2365efe843d8SDavid Gibson if (rs != rb) { 2366fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2367efe843d8SDavid Gibson } else { 2368fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2369efe843d8SDavid Gibson } 2370efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2371fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2372efe843d8SDavid Gibson } 2373fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2374fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2375fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2376fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2377fcf5ef2aSThomas Huth int prio = 0; 2378fcf5ef2aSThomas Huth 2379fcf5ef2aSThomas Huth switch (rs) { 2380fcf5ef2aSThomas Huth case 1: 2381fcf5ef2aSThomas Huth /* Set process priority to low */ 2382fcf5ef2aSThomas Huth prio = 2; 2383fcf5ef2aSThomas Huth break; 2384fcf5ef2aSThomas Huth case 6: 2385fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2386fcf5ef2aSThomas Huth prio = 3; 2387fcf5ef2aSThomas Huth break; 2388fcf5ef2aSThomas Huth case 2: 2389fcf5ef2aSThomas Huth /* Set process priority to normal */ 2390fcf5ef2aSThomas Huth prio = 4; 2391fcf5ef2aSThomas Huth break; 2392fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2393fcf5ef2aSThomas Huth case 31: 2394fcf5ef2aSThomas Huth if (!ctx->pr) { 2395fcf5ef2aSThomas Huth /* Set process priority to very low */ 2396fcf5ef2aSThomas Huth prio = 1; 2397fcf5ef2aSThomas Huth } 2398fcf5ef2aSThomas Huth break; 2399fcf5ef2aSThomas Huth case 5: 2400fcf5ef2aSThomas Huth if (!ctx->pr) { 2401fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2402fcf5ef2aSThomas Huth prio = 5; 2403fcf5ef2aSThomas Huth } 2404fcf5ef2aSThomas Huth break; 2405fcf5ef2aSThomas Huth case 3: 2406fcf5ef2aSThomas Huth if (!ctx->pr) { 2407fcf5ef2aSThomas Huth /* Set process priority to high */ 2408fcf5ef2aSThomas Huth prio = 6; 2409fcf5ef2aSThomas Huth } 2410fcf5ef2aSThomas Huth break; 2411fcf5ef2aSThomas Huth case 7: 2412fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2413fcf5ef2aSThomas Huth /* Set process priority to very high */ 2414fcf5ef2aSThomas Huth prio = 7; 2415fcf5ef2aSThomas Huth } 2416fcf5ef2aSThomas Huth break; 2417fcf5ef2aSThomas Huth #endif 2418fcf5ef2aSThomas Huth default: 2419fcf5ef2aSThomas Huth break; 2420fcf5ef2aSThomas Huth } 2421fcf5ef2aSThomas Huth if (prio) { 2422fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2423fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2424fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2425fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2426fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2427fcf5ef2aSThomas Huth tcg_temp_free(t0); 2428fcf5ef2aSThomas Huth } 2429fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2430efe843d8SDavid Gibson /* 2431efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2432efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2433efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2434efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2435fcf5ef2aSThomas Huth */ 2436fcf5ef2aSThomas Huth gen_pause(ctx); 2437fcf5ef2aSThomas Huth #endif 2438fcf5ef2aSThomas Huth #endif 2439fcf5ef2aSThomas Huth } 2440fcf5ef2aSThomas Huth } 2441fcf5ef2aSThomas Huth /* orc & orc. */ 2442fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2443fcf5ef2aSThomas Huth 2444fcf5ef2aSThomas Huth /* xor & xor. */ 2445fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2446fcf5ef2aSThomas Huth { 2447fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2448efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2449efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2450efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2451efe843d8SDavid Gibson } else { 2452fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2453efe843d8SDavid Gibson } 2454efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2455fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2456fcf5ef2aSThomas Huth } 2457efe843d8SDavid Gibson } 2458fcf5ef2aSThomas Huth 2459fcf5ef2aSThomas Huth /* ori */ 2460fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2461fcf5ef2aSThomas Huth { 2462fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2463fcf5ef2aSThomas Huth 2464fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2465fcf5ef2aSThomas Huth return; 2466fcf5ef2aSThomas Huth } 2467fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2468fcf5ef2aSThomas Huth } 2469fcf5ef2aSThomas Huth 2470fcf5ef2aSThomas Huth /* oris */ 2471fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2472fcf5ef2aSThomas Huth { 2473fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2474fcf5ef2aSThomas Huth 2475fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2476fcf5ef2aSThomas Huth /* NOP */ 2477fcf5ef2aSThomas Huth return; 2478fcf5ef2aSThomas Huth } 2479efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2480efe843d8SDavid Gibson uimm << 16); 2481fcf5ef2aSThomas Huth } 2482fcf5ef2aSThomas Huth 2483fcf5ef2aSThomas Huth /* xori */ 2484fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2485fcf5ef2aSThomas Huth { 2486fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2487fcf5ef2aSThomas Huth 2488fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2489fcf5ef2aSThomas Huth /* NOP */ 2490fcf5ef2aSThomas Huth return; 2491fcf5ef2aSThomas Huth } 2492fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2493fcf5ef2aSThomas Huth } 2494fcf5ef2aSThomas Huth 2495fcf5ef2aSThomas Huth /* xoris */ 2496fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2497fcf5ef2aSThomas Huth { 2498fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2499fcf5ef2aSThomas Huth 2500fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2501fcf5ef2aSThomas Huth /* NOP */ 2502fcf5ef2aSThomas Huth return; 2503fcf5ef2aSThomas Huth } 2504efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2505efe843d8SDavid Gibson uimm << 16); 2506fcf5ef2aSThomas Huth } 2507fcf5ef2aSThomas Huth 2508fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2509fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2510fcf5ef2aSThomas Huth { 2511fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2512fcf5ef2aSThomas Huth } 2513fcf5ef2aSThomas Huth 2514fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2515fcf5ef2aSThomas Huth { 251679770002SRichard Henderson #if defined(TARGET_PPC64) 2517fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251879770002SRichard Henderson #else 251979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 252079770002SRichard Henderson #endif 2521fcf5ef2aSThomas Huth } 2522fcf5ef2aSThomas Huth 2523fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2524fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2525fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2526fcf5ef2aSThomas Huth { 252779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2528fcf5ef2aSThomas Huth } 2529fcf5ef2aSThomas Huth #endif 2530fcf5ef2aSThomas Huth 2531fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2532fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2533fcf5ef2aSThomas Huth { 2534fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2535fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2536fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2537fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2538fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2539fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2540fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2541fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2542fcf5ef2aSThomas Huth tcg_temp_free(t0); 2543fcf5ef2aSThomas Huth } 2544fcf5ef2aSThomas Huth 2545fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2546fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2547fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2548fcf5ef2aSThomas Huth { 2549fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2550fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2551fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2552fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2553fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2554fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2555fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2556fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2557fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2558fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2559fcf5ef2aSThomas Huth tcg_temp_free(t0); 2560fcf5ef2aSThomas Huth } 2561fcf5ef2aSThomas Huth #endif 2562fcf5ef2aSThomas Huth 2563fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2564fcf5ef2aSThomas Huth /* bpermd */ 2565fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2566fcf5ef2aSThomas Huth { 2567fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2568fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2569fcf5ef2aSThomas Huth } 2570fcf5ef2aSThomas Huth #endif 2571fcf5ef2aSThomas Huth 2572fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2573fcf5ef2aSThomas Huth /* extsw & extsw. */ 2574fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2575fcf5ef2aSThomas Huth 2576fcf5ef2aSThomas Huth /* cntlzd */ 2577fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2578fcf5ef2aSThomas Huth { 25799b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2580efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2581fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2582fcf5ef2aSThomas Huth } 2583efe843d8SDavid Gibson } 2584fcf5ef2aSThomas Huth 2585fcf5ef2aSThomas Huth /* cnttzd */ 2586fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2587fcf5ef2aSThomas Huth { 25889b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2589fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2590fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2591fcf5ef2aSThomas Huth } 2592fcf5ef2aSThomas Huth } 2593fcf5ef2aSThomas Huth 2594fcf5ef2aSThomas Huth /* darn */ 2595fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2596fcf5ef2aSThomas Huth { 2597fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2598fcf5ef2aSThomas Huth 25997e4357f6SRichard Henderson if (l > 2) { 26007e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 26017e4357f6SRichard Henderson } else { 2602f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2603fcf5ef2aSThomas Huth if (l == 0) { 2604fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26057e4357f6SRichard Henderson } else { 2606fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2607fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26087e4357f6SRichard Henderson } 2609fcf5ef2aSThomas Huth } 2610fcf5ef2aSThomas Huth } 2611fcf5ef2aSThomas Huth #endif 2612fcf5ef2aSThomas Huth 2613fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2614fcf5ef2aSThomas Huth 2615fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2616fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2617fcf5ef2aSThomas Huth { 2618fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2619fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2620fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2621fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2622fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2623fcf5ef2aSThomas Huth 2624fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2625fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2626fcf5ef2aSThomas Huth } else { 2627fcf5ef2aSThomas Huth target_ulong mask; 2628c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2629fcf5ef2aSThomas Huth TCGv t1; 2630fcf5ef2aSThomas Huth 2631fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2632fcf5ef2aSThomas Huth mb += 32; 2633fcf5ef2aSThomas Huth me += 32; 2634fcf5ef2aSThomas Huth #endif 2635fcf5ef2aSThomas Huth mask = MASK(mb, me); 2636fcf5ef2aSThomas Huth 2637c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2638c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2639c4f6a4a3SDaniele Buono mask_in_32b = false; 2640c4f6a4a3SDaniele Buono } 2641c4f6a4a3SDaniele Buono #endif 2642fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2643c4f6a4a3SDaniele Buono if (mask_in_32b) { 2644fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2645fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2646fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2647fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2648fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2649fcf5ef2aSThomas Huth } else { 2650fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2651fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2652fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2653fcf5ef2aSThomas Huth #else 2654fcf5ef2aSThomas Huth g_assert_not_reached(); 2655fcf5ef2aSThomas Huth #endif 2656fcf5ef2aSThomas Huth } 2657fcf5ef2aSThomas Huth 2658fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2659fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2660fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2661fcf5ef2aSThomas Huth tcg_temp_free(t1); 2662fcf5ef2aSThomas Huth } 2663fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2664fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2665fcf5ef2aSThomas Huth } 2666fcf5ef2aSThomas Huth } 2667fcf5ef2aSThomas Huth 2668fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2669fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2670fcf5ef2aSThomas Huth { 2671fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2672fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26737b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26747b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26757b4d326fSRichard Henderson int me = ME(ctx->opcode); 26767b4d326fSRichard Henderson int len = me - mb + 1; 26777b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2678fcf5ef2aSThomas Huth 26797b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26807b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26817b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26827b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2683fcf5ef2aSThomas Huth } else { 2684fcf5ef2aSThomas Huth target_ulong mask; 2685c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2686fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2687fcf5ef2aSThomas Huth mb += 32; 2688fcf5ef2aSThomas Huth me += 32; 2689fcf5ef2aSThomas Huth #endif 2690fcf5ef2aSThomas Huth mask = MASK(mb, me); 2691c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2692c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2693c4f6a4a3SDaniele Buono mask_in_32b = false; 2694c4f6a4a3SDaniele Buono } 2695c4f6a4a3SDaniele Buono #endif 2696c4f6a4a3SDaniele Buono if (mask_in_32b) { 26977b4d326fSRichard Henderson if (sh == 0) { 26987b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 269994f040aaSVitaly Chikunov } else { 2700fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2701fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2702fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2703fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2704fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2705fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 270694f040aaSVitaly Chikunov } 2707fcf5ef2aSThomas Huth } else { 2708fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2709fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2710fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2711fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2712fcf5ef2aSThomas Huth #else 2713fcf5ef2aSThomas Huth g_assert_not_reached(); 2714fcf5ef2aSThomas Huth #endif 2715fcf5ef2aSThomas Huth } 2716fcf5ef2aSThomas Huth } 2717fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2718fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2719fcf5ef2aSThomas Huth } 2720fcf5ef2aSThomas Huth } 2721fcf5ef2aSThomas Huth 2722fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2723fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2724fcf5ef2aSThomas Huth { 2725fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2726fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2727fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2728fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2729fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2730fcf5ef2aSThomas Huth target_ulong mask; 2731c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2732fcf5ef2aSThomas Huth 2733fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2734fcf5ef2aSThomas Huth mb += 32; 2735fcf5ef2aSThomas Huth me += 32; 2736fcf5ef2aSThomas Huth #endif 2737fcf5ef2aSThomas Huth mask = MASK(mb, me); 2738fcf5ef2aSThomas Huth 2739c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2740c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2741c4f6a4a3SDaniele Buono mask_in_32b = false; 2742c4f6a4a3SDaniele Buono } 2743c4f6a4a3SDaniele Buono #endif 2744c4f6a4a3SDaniele Buono if (mask_in_32b) { 2745fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2746fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2747fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2748fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2749fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2750fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2751fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2752fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2753fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2754fcf5ef2aSThomas Huth } else { 2755fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2756fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2757fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2758fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2759fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2760fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2761fcf5ef2aSThomas Huth #else 2762fcf5ef2aSThomas Huth g_assert_not_reached(); 2763fcf5ef2aSThomas Huth #endif 2764fcf5ef2aSThomas Huth } 2765fcf5ef2aSThomas Huth 2766fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2767fcf5ef2aSThomas Huth 2768fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2769fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2770fcf5ef2aSThomas Huth } 2771fcf5ef2aSThomas Huth } 2772fcf5ef2aSThomas Huth 2773fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2774fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2775fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2776fcf5ef2aSThomas Huth { \ 2777fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2778fcf5ef2aSThomas Huth } \ 2779fcf5ef2aSThomas Huth \ 2780fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2781fcf5ef2aSThomas Huth { \ 2782fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2783fcf5ef2aSThomas Huth } 2784fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2785fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2786fcf5ef2aSThomas Huth { \ 2787fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2788fcf5ef2aSThomas Huth } \ 2789fcf5ef2aSThomas Huth \ 2790fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2791fcf5ef2aSThomas Huth { \ 2792fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2793fcf5ef2aSThomas Huth } \ 2794fcf5ef2aSThomas Huth \ 2795fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2796fcf5ef2aSThomas Huth { \ 2797fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2798fcf5ef2aSThomas Huth } \ 2799fcf5ef2aSThomas Huth \ 2800fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2801fcf5ef2aSThomas Huth { \ 2802fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2803fcf5ef2aSThomas Huth } 2804fcf5ef2aSThomas Huth 2805fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2806fcf5ef2aSThomas Huth { 2807fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2808fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28097b4d326fSRichard Henderson int len = me - mb + 1; 28107b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2811fcf5ef2aSThomas Huth 28127b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28137b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28147b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28157b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2816fcf5ef2aSThomas Huth } else { 2817fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2818fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2819fcf5ef2aSThomas Huth } 2820fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2821fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2822fcf5ef2aSThomas Huth } 2823fcf5ef2aSThomas Huth } 2824fcf5ef2aSThomas Huth 2825fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2826fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2827fcf5ef2aSThomas Huth { 2828fcf5ef2aSThomas Huth uint32_t sh, mb; 2829fcf5ef2aSThomas Huth 2830fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2831fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2832fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2833fcf5ef2aSThomas Huth } 2834fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2835fcf5ef2aSThomas Huth 2836fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2837fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2838fcf5ef2aSThomas Huth { 2839fcf5ef2aSThomas Huth uint32_t sh, me; 2840fcf5ef2aSThomas Huth 2841fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2842fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2843fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2844fcf5ef2aSThomas Huth } 2845fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2846fcf5ef2aSThomas Huth 2847fcf5ef2aSThomas Huth /* rldic - rldic. */ 2848fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2849fcf5ef2aSThomas Huth { 2850fcf5ef2aSThomas Huth uint32_t sh, mb; 2851fcf5ef2aSThomas Huth 2852fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2853fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2854fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2855fcf5ef2aSThomas Huth } 2856fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2857fcf5ef2aSThomas Huth 2858fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2859fcf5ef2aSThomas Huth { 2860fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2861fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2862fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2863fcf5ef2aSThomas Huth TCGv t0; 2864fcf5ef2aSThomas Huth 2865fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2866fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2867fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2868fcf5ef2aSThomas Huth tcg_temp_free(t0); 2869fcf5ef2aSThomas Huth 2870fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2871fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2872fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2873fcf5ef2aSThomas Huth } 2874fcf5ef2aSThomas Huth } 2875fcf5ef2aSThomas Huth 2876fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2877fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2878fcf5ef2aSThomas Huth { 2879fcf5ef2aSThomas Huth uint32_t mb; 2880fcf5ef2aSThomas Huth 2881fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2882fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2883fcf5ef2aSThomas Huth } 2884fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2885fcf5ef2aSThomas Huth 2886fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2887fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2888fcf5ef2aSThomas Huth { 2889fcf5ef2aSThomas Huth uint32_t me; 2890fcf5ef2aSThomas Huth 2891fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2892fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2893fcf5ef2aSThomas Huth } 2894fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2895fcf5ef2aSThomas Huth 2896fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2897fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2898fcf5ef2aSThomas Huth { 2899fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2900fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2901fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2902fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2903fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2904fcf5ef2aSThomas Huth 2905fcf5ef2aSThomas Huth if (mb <= me) { 2906fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2907fcf5ef2aSThomas Huth } else { 2908fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2909fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2910fcf5ef2aSThomas Huth 2911fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2912fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2913fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2914fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2915fcf5ef2aSThomas Huth tcg_temp_free(t1); 2916fcf5ef2aSThomas Huth } 2917fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2918fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2919fcf5ef2aSThomas Huth } 2920fcf5ef2aSThomas Huth } 2921fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2922fcf5ef2aSThomas Huth #endif 2923fcf5ef2aSThomas Huth 2924fcf5ef2aSThomas Huth /*** Integer shift ***/ 2925fcf5ef2aSThomas Huth 2926fcf5ef2aSThomas Huth /* slw & slw. */ 2927fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2928fcf5ef2aSThomas Huth { 2929fcf5ef2aSThomas Huth TCGv t0, t1; 2930fcf5ef2aSThomas Huth 2931fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2932fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2933fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2934fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2935fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2936fcf5ef2aSThomas Huth #else 2937fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2938fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2939fcf5ef2aSThomas Huth #endif 2940fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2941fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2942fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2943fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2944fcf5ef2aSThomas Huth tcg_temp_free(t1); 2945fcf5ef2aSThomas Huth tcg_temp_free(t0); 2946fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2947efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2948fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2949fcf5ef2aSThomas Huth } 2950efe843d8SDavid Gibson } 2951fcf5ef2aSThomas Huth 2952fcf5ef2aSThomas Huth /* sraw & sraw. */ 2953fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2954fcf5ef2aSThomas Huth { 2955fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2956fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2957efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2958fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2959fcf5ef2aSThomas Huth } 2960efe843d8SDavid Gibson } 2961fcf5ef2aSThomas Huth 2962fcf5ef2aSThomas Huth /* srawi & srawi. */ 2963fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2964fcf5ef2aSThomas Huth { 2965fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2966fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2967fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2968fcf5ef2aSThomas Huth if (sh == 0) { 2969fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2970fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2971af1c259fSSandipan Das if (is_isa300(ctx)) { 2972af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2973af1c259fSSandipan Das } 2974fcf5ef2aSThomas Huth } else { 2975fcf5ef2aSThomas Huth TCGv t0; 2976fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2977fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2978fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2979fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2980fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2981fcf5ef2aSThomas Huth tcg_temp_free(t0); 2982fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2983af1c259fSSandipan Das if (is_isa300(ctx)) { 2984af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2985af1c259fSSandipan Das } 2986fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2987fcf5ef2aSThomas Huth } 2988fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2989fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2990fcf5ef2aSThomas Huth } 2991fcf5ef2aSThomas Huth } 2992fcf5ef2aSThomas Huth 2993fcf5ef2aSThomas Huth /* srw & srw. */ 2994fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2995fcf5ef2aSThomas Huth { 2996fcf5ef2aSThomas Huth TCGv t0, t1; 2997fcf5ef2aSThomas Huth 2998fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2999fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3000fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3001fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3002fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3003fcf5ef2aSThomas Huth #else 3004fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3005fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3006fcf5ef2aSThomas Huth #endif 3007fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3008fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3009fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3010fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3011fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3012fcf5ef2aSThomas Huth tcg_temp_free(t1); 3013fcf5ef2aSThomas Huth tcg_temp_free(t0); 3014efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3015fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3016fcf5ef2aSThomas Huth } 3017efe843d8SDavid Gibson } 3018fcf5ef2aSThomas Huth 3019fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3020fcf5ef2aSThomas Huth /* sld & sld. */ 3021fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3022fcf5ef2aSThomas Huth { 3023fcf5ef2aSThomas Huth TCGv t0, t1; 3024fcf5ef2aSThomas Huth 3025fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3026fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3027fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3028fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3029fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3030fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3031fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3032fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3033fcf5ef2aSThomas Huth tcg_temp_free(t1); 3034fcf5ef2aSThomas Huth tcg_temp_free(t0); 3035efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3036fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3037fcf5ef2aSThomas Huth } 3038efe843d8SDavid Gibson } 3039fcf5ef2aSThomas Huth 3040fcf5ef2aSThomas Huth /* srad & srad. */ 3041fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3042fcf5ef2aSThomas Huth { 3043fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3044fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3045efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3046fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3047fcf5ef2aSThomas Huth } 3048efe843d8SDavid Gibson } 3049fcf5ef2aSThomas Huth /* sradi & sradi. */ 3050fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3051fcf5ef2aSThomas Huth { 3052fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3053fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3054fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3055fcf5ef2aSThomas Huth if (sh == 0) { 3056fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3057fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3058af1c259fSSandipan Das if (is_isa300(ctx)) { 3059af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3060af1c259fSSandipan Das } 3061fcf5ef2aSThomas Huth } else { 3062fcf5ef2aSThomas Huth TCGv t0; 3063fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3064fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3065fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3066fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3067fcf5ef2aSThomas Huth tcg_temp_free(t0); 3068fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3069af1c259fSSandipan Das if (is_isa300(ctx)) { 3070af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3071af1c259fSSandipan Das } 3072fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3073fcf5ef2aSThomas Huth } 3074fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3075fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3076fcf5ef2aSThomas Huth } 3077fcf5ef2aSThomas Huth } 3078fcf5ef2aSThomas Huth 3079fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3080fcf5ef2aSThomas Huth { 3081fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3082fcf5ef2aSThomas Huth } 3083fcf5ef2aSThomas Huth 3084fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3085fcf5ef2aSThomas Huth { 3086fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3087fcf5ef2aSThomas Huth } 3088fcf5ef2aSThomas Huth 3089fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3090fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3091fcf5ef2aSThomas Huth { 3092fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3093fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3094fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3095fcf5ef2aSThomas Huth 3096fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3097fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3098fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3099fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3100fcf5ef2aSThomas Huth } 3101fcf5ef2aSThomas Huth } 3102fcf5ef2aSThomas Huth 3103fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3104fcf5ef2aSThomas Huth { 3105fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3106fcf5ef2aSThomas Huth } 3107fcf5ef2aSThomas Huth 3108fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3109fcf5ef2aSThomas Huth { 3110fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3111fcf5ef2aSThomas Huth } 3112fcf5ef2aSThomas Huth 3113fcf5ef2aSThomas Huth /* srd & srd. */ 3114fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3115fcf5ef2aSThomas Huth { 3116fcf5ef2aSThomas Huth TCGv t0, t1; 3117fcf5ef2aSThomas Huth 3118fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3119fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3120fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3121fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3122fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3123fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3124fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3125fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3126fcf5ef2aSThomas Huth tcg_temp_free(t1); 3127fcf5ef2aSThomas Huth tcg_temp_free(t0); 3128efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3129fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3130fcf5ef2aSThomas Huth } 3131efe843d8SDavid Gibson } 3132fcf5ef2aSThomas Huth #endif 3133fcf5ef2aSThomas Huth 3134fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3135fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3136fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3137fcf5ef2aSThomas Huth target_long maskl) 3138fcf5ef2aSThomas Huth { 3139fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3140fcf5ef2aSThomas Huth 3141fcf5ef2aSThomas Huth simm &= ~maskl; 3142fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3143fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3144fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3145fcf5ef2aSThomas Huth } 3146fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3147fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3148fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3149fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3150fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3151fcf5ef2aSThomas Huth } 3152fcf5ef2aSThomas Huth } else { 3153fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3154fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3155fcf5ef2aSThomas Huth } else { 3156fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3157fcf5ef2aSThomas Huth } 3158fcf5ef2aSThomas Huth } 3159fcf5ef2aSThomas Huth } 3160fcf5ef2aSThomas Huth 3161fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3162fcf5ef2aSThomas Huth { 3163fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3164fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3165fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3166fcf5ef2aSThomas Huth } else { 3167fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3168fcf5ef2aSThomas Huth } 3169fcf5ef2aSThomas Huth } else { 3170fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3171fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3172fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3173fcf5ef2aSThomas Huth } 3174fcf5ef2aSThomas Huth } 3175fcf5ef2aSThomas Huth } 3176fcf5ef2aSThomas Huth 3177fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3178fcf5ef2aSThomas Huth { 3179fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3180fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3181fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3182fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3183fcf5ef2aSThomas Huth } else { 3184fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3185fcf5ef2aSThomas Huth } 3186fcf5ef2aSThomas Huth } 3187fcf5ef2aSThomas Huth 3188fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3189fcf5ef2aSThomas Huth target_long val) 3190fcf5ef2aSThomas Huth { 3191fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3192fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3193fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3194fcf5ef2aSThomas Huth } 3195fcf5ef2aSThomas Huth } 3196fcf5ef2aSThomas Huth 3197fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3198fcf5ef2aSThomas Huth { 3199fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3200fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3201fcf5ef2aSThomas Huth } 3202fcf5ef2aSThomas Huth 3203eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3204eb63efd9SFernando Eckhardt Valle { 3205eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3206eb63efd9SFernando Eckhardt Valle if (ra) { 3207eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3208eb63efd9SFernando Eckhardt Valle } else { 3209eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3210eb63efd9SFernando Eckhardt Valle } 3211eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3212eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3213eb63efd9SFernando Eckhardt Valle } 3214eb63efd9SFernando Eckhardt Valle return ea; 3215eb63efd9SFernando Eckhardt Valle } 3216eb63efd9SFernando Eckhardt Valle 3217fcf5ef2aSThomas Huth /*** Integer load ***/ 3218fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3219fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3220fcf5ef2aSThomas Huth 3221fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3222fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3223fcf5ef2aSThomas Huth TCGv val, \ 3224fcf5ef2aSThomas Huth TCGv addr) \ 3225fcf5ef2aSThomas Huth { \ 3226fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3227fcf5ef2aSThomas Huth } 3228fcf5ef2aSThomas Huth 3229fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3230fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3231fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3232fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3233fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3234fcf5ef2aSThomas Huth 3235fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3236fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3237fcf5ef2aSThomas Huth 3238fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3239fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3240fcf5ef2aSThomas Huth TCGv_i64 val, \ 3241fcf5ef2aSThomas Huth TCGv addr) \ 3242fcf5ef2aSThomas Huth { \ 3243fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3244fcf5ef2aSThomas Huth } 3245fcf5ef2aSThomas Huth 3246fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3247fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3248fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3249fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3250fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3251fcf5ef2aSThomas Huth 3252fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3253fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3254fcf5ef2aSThomas Huth #endif 3255fcf5ef2aSThomas Huth 3256fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3257fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3258fcf5ef2aSThomas Huth TCGv val, \ 3259fcf5ef2aSThomas Huth TCGv addr) \ 3260fcf5ef2aSThomas Huth { \ 3261fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3262fcf5ef2aSThomas Huth } 3263fcf5ef2aSThomas Huth 3264e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3265fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3266e8f4c8d6SRichard Henderson #endif 3267fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3268fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3269fcf5ef2aSThomas Huth 3270fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3271fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3272fcf5ef2aSThomas Huth 3273fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3274fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3275fcf5ef2aSThomas Huth TCGv_i64 val, \ 3276fcf5ef2aSThomas Huth TCGv addr) \ 3277fcf5ef2aSThomas Huth { \ 3278fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3279fcf5ef2aSThomas Huth } 3280fcf5ef2aSThomas Huth 3281fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3282fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3283fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3284fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3285fcf5ef2aSThomas Huth 3286fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3287fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3288fcf5ef2aSThomas Huth #endif 3289fcf5ef2aSThomas Huth 3290fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3291fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3292fcf5ef2aSThomas Huth { \ 3293fcf5ef2aSThomas Huth TCGv EA; \ 32949f0cf041SMatheus Ferst chk(ctx); \ 3295fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3296fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3297fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3298fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3299fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3300fcf5ef2aSThomas Huth } 3301fcf5ef2aSThomas Huth 3302fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3303fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3304fcf5ef2aSThomas Huth 3305fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3306fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3307fcf5ef2aSThomas Huth 330850728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 330950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 331050728199SRoman Kapl { \ 331150728199SRoman Kapl TCGv EA; \ 33129f0cf041SMatheus Ferst CHK_SV(ctx); \ 331350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 331450728199SRoman Kapl EA = tcg_temp_new(); \ 331550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 331650728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 331750728199SRoman Kapl tcg_temp_free(EA); \ 331850728199SRoman Kapl } 331950728199SRoman Kapl 332050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 332150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 332250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 332350728199SRoman Kapl #if defined(TARGET_PPC64) 3324fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 332550728199SRoman Kapl #endif 332650728199SRoman Kapl 3327fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3328fcf5ef2aSThomas Huth /* CI load/store variants */ 3329fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3330fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3331fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3332fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3333fcf5ef2aSThomas Huth #endif 3334fcf5ef2aSThomas Huth 3335fcf5ef2aSThomas Huth /*** Integer store ***/ 3336fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3337fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3338fcf5ef2aSThomas Huth { \ 3339fcf5ef2aSThomas Huth TCGv EA; \ 33409f0cf041SMatheus Ferst chk(ctx); \ 3341fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3342fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3343fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3344fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3345fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3346fcf5ef2aSThomas Huth } 3347fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3348fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3349fcf5ef2aSThomas Huth 3350fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3351fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3352fcf5ef2aSThomas Huth 335350728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 335450728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 335550728199SRoman Kapl { \ 335650728199SRoman Kapl TCGv EA; \ 33579f0cf041SMatheus Ferst CHK_SV(ctx); \ 335850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 335950728199SRoman Kapl EA = tcg_temp_new(); \ 336050728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 336150728199SRoman Kapl tcg_gen_qemu_st_tl( \ 336250728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 336350728199SRoman Kapl tcg_temp_free(EA); \ 336450728199SRoman Kapl } 336550728199SRoman Kapl 336650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 336750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 336850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 336950728199SRoman Kapl #if defined(TARGET_PPC64) 3370fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 337150728199SRoman Kapl #endif 337250728199SRoman Kapl 3373fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3374fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3375fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3376fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3377fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3378fcf5ef2aSThomas Huth #endif 3379fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3380fcf5ef2aSThomas Huth 3381fcf5ef2aSThomas Huth /* lhbrx */ 3382fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3383fcf5ef2aSThomas Huth 3384fcf5ef2aSThomas Huth /* lwbrx */ 3385fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3386fcf5ef2aSThomas Huth 3387fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3388fcf5ef2aSThomas Huth /* ldbrx */ 3389fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3390fcf5ef2aSThomas Huth /* stdbrx */ 3391fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3392fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3393fcf5ef2aSThomas Huth 3394fcf5ef2aSThomas Huth /* sthbrx */ 3395fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3396fcf5ef2aSThomas Huth /* stwbrx */ 3397fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3398fcf5ef2aSThomas Huth 3399fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3400fcf5ef2aSThomas Huth 3401fcf5ef2aSThomas Huth /* lmw */ 3402fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3403fcf5ef2aSThomas Huth { 3404fcf5ef2aSThomas Huth TCGv t0; 3405fcf5ef2aSThomas Huth TCGv_i32 t1; 3406fcf5ef2aSThomas Huth 3407fcf5ef2aSThomas Huth if (ctx->le_mode) { 3408fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3409fcf5ef2aSThomas Huth return; 3410fcf5ef2aSThomas Huth } 3411fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3412fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3413fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3414fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3415fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3416fcf5ef2aSThomas Huth tcg_temp_free(t0); 3417fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3418fcf5ef2aSThomas Huth } 3419fcf5ef2aSThomas Huth 3420fcf5ef2aSThomas Huth /* stmw */ 3421fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3422fcf5ef2aSThomas Huth { 3423fcf5ef2aSThomas Huth TCGv t0; 3424fcf5ef2aSThomas Huth TCGv_i32 t1; 3425fcf5ef2aSThomas Huth 3426fcf5ef2aSThomas Huth if (ctx->le_mode) { 3427fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3428fcf5ef2aSThomas Huth return; 3429fcf5ef2aSThomas Huth } 3430fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3431fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3432fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3433fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3434fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3435fcf5ef2aSThomas Huth tcg_temp_free(t0); 3436fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3437fcf5ef2aSThomas Huth } 3438fcf5ef2aSThomas Huth 3439fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3440fcf5ef2aSThomas Huth 3441fcf5ef2aSThomas Huth /* lswi */ 3442efe843d8SDavid Gibson /* 3443efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3444efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3445efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3446efe843d8SDavid Gibson * spec... 3447fcf5ef2aSThomas Huth */ 3448fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3449fcf5ef2aSThomas Huth { 3450fcf5ef2aSThomas Huth TCGv t0; 3451fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3452fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3453fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3454fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3455fcf5ef2aSThomas Huth int nr; 3456fcf5ef2aSThomas Huth 3457fcf5ef2aSThomas Huth if (ctx->le_mode) { 3458fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3459fcf5ef2aSThomas Huth return; 3460fcf5ef2aSThomas Huth } 3461efe843d8SDavid Gibson if (nb == 0) { 3462fcf5ef2aSThomas Huth nb = 32; 3463efe843d8SDavid Gibson } 3464f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3465fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3466fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3467fcf5ef2aSThomas Huth return; 3468fcf5ef2aSThomas Huth } 3469fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3470fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3471fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3472fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3473fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3474fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3475fcf5ef2aSThomas Huth tcg_temp_free(t0); 3476fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3477fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3478fcf5ef2aSThomas Huth } 3479fcf5ef2aSThomas Huth 3480fcf5ef2aSThomas Huth /* lswx */ 3481fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3482fcf5ef2aSThomas Huth { 3483fcf5ef2aSThomas Huth TCGv t0; 3484fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3485fcf5ef2aSThomas Huth 3486fcf5ef2aSThomas Huth if (ctx->le_mode) { 3487fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3488fcf5ef2aSThomas Huth return; 3489fcf5ef2aSThomas Huth } 3490fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3491fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3492fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3493fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3494fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3495fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3496fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3497fcf5ef2aSThomas Huth tcg_temp_free(t0); 3498fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3499fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3500fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3501fcf5ef2aSThomas Huth } 3502fcf5ef2aSThomas Huth 3503fcf5ef2aSThomas Huth /* stswi */ 3504fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3505fcf5ef2aSThomas Huth { 3506fcf5ef2aSThomas Huth TCGv t0; 3507fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3508fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3509fcf5ef2aSThomas Huth 3510fcf5ef2aSThomas Huth if (ctx->le_mode) { 3511fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3512fcf5ef2aSThomas Huth return; 3513fcf5ef2aSThomas Huth } 3514fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3515fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3516fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3517efe843d8SDavid Gibson if (nb == 0) { 3518fcf5ef2aSThomas Huth nb = 32; 3519efe843d8SDavid Gibson } 3520fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3521fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3522fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3523fcf5ef2aSThomas Huth tcg_temp_free(t0); 3524fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3525fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3526fcf5ef2aSThomas Huth } 3527fcf5ef2aSThomas Huth 3528fcf5ef2aSThomas Huth /* stswx */ 3529fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3530fcf5ef2aSThomas Huth { 3531fcf5ef2aSThomas Huth TCGv t0; 3532fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3533fcf5ef2aSThomas Huth 3534fcf5ef2aSThomas Huth if (ctx->le_mode) { 3535fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3536fcf5ef2aSThomas Huth return; 3537fcf5ef2aSThomas Huth } 3538fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3539fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3540fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3541fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3542fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3543fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3544fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3545fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3546fcf5ef2aSThomas Huth tcg_temp_free(t0); 3547fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3548fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3549fcf5ef2aSThomas Huth } 3550fcf5ef2aSThomas Huth 3551fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3552fcf5ef2aSThomas Huth /* eieio */ 3553fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3554fcf5ef2aSThomas Huth { 3555fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3556fcb830afSNicholas Piggin 3557fcb830afSNicholas Piggin /* 3558fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3559fcb830afSNicholas Piggin * operations in the set: 3560fcb830afSNicholas Piggin * - loads from CI memory. 3561fcb830afSNicholas Piggin * - stores to CI memory. 3562fcb830afSNicholas Piggin * - stores to WT memory. 3563fcb830afSNicholas Piggin * 3564fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3565fcb830afSNicholas Piggin * - stores to cacheble memory. 3566fcb830afSNicholas Piggin * 3567fcb830afSNicholas Piggin * It also serializes instructions: 3568fcb830afSNicholas Piggin * - dcbt and dcbst. 3569fcb830afSNicholas Piggin * 3570fcb830afSNicholas Piggin * It separately serializes: 3571fcb830afSNicholas Piggin * - tlbie and tlbsync. 3572fcb830afSNicholas Piggin * 3573fcb830afSNicholas Piggin * And separately serializes: 3574fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3575fcb830afSNicholas Piggin * 3576fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3577fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3578fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3579fcb830afSNicholas Piggin * serialization. 3580fcb830afSNicholas Piggin */ 3581c8fd8373SCédric Le Goater 3582c8fd8373SCédric Le Goater /* 3583c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3584c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3585c8fd8373SCédric Le Goater */ 3586c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3587c8fd8373SCédric Le Goater /* 3588c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3589c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3590c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3591c8fd8373SCédric Le Goater * complain to the user. 3592c8fd8373SCédric Le Goater */ 3593c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3594c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 35952c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3596c8fd8373SCédric Le Goater } else { 3597c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3598c8fd8373SCédric Le Goater } 3599c8fd8373SCédric Le Goater } 3600c8fd8373SCédric Le Goater 3601c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3602fcf5ef2aSThomas Huth } 3603fcf5ef2aSThomas Huth 3604fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3605fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3606fcf5ef2aSThomas Huth { 3607fcf5ef2aSThomas Huth TCGv_i32 t; 3608fcf5ef2aSThomas Huth TCGLabel *l; 3609fcf5ef2aSThomas Huth 3610fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3611fcf5ef2aSThomas Huth return; 3612fcf5ef2aSThomas Huth } 3613fcf5ef2aSThomas Huth l = gen_new_label(); 3614fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3615fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3616fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3617fcf5ef2aSThomas Huth if (global) { 3618fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3619fcf5ef2aSThomas Huth } else { 3620fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3621fcf5ef2aSThomas Huth } 3622fcf5ef2aSThomas Huth gen_set_label(l); 3623fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3624fcf5ef2aSThomas Huth } 3625fcf5ef2aSThomas Huth #else 3626fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3627fcf5ef2aSThomas Huth #endif 3628fcf5ef2aSThomas Huth 3629fcf5ef2aSThomas Huth /* isync */ 3630fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3631fcf5ef2aSThomas Huth { 3632fcf5ef2aSThomas Huth /* 3633fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3634fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3635fcf5ef2aSThomas Huth */ 3636fcf5ef2aSThomas Huth if (!ctx->pr) { 3637fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3638fcf5ef2aSThomas Huth } 36394771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3640d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3641fcf5ef2aSThomas Huth } 3642fcf5ef2aSThomas Huth 3643fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3644fcf5ef2aSThomas Huth 364514776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 36462a4e6c1bSRichard Henderson { 36472a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 36482a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 36492a4e6c1bSRichard Henderson 36502a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 36512a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 36522a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 36532a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 36542a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 36552a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 36562a4e6c1bSRichard Henderson tcg_temp_free(t0); 36572a4e6c1bSRichard Henderson } 36582a4e6c1bSRichard Henderson 3659fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3660fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3661fcf5ef2aSThomas Huth { \ 36622a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3663fcf5ef2aSThomas Huth } 3664fcf5ef2aSThomas Huth 3665fcf5ef2aSThomas Huth /* lwarx */ 3666fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3667fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3668fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3669fcf5ef2aSThomas Huth 367014776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 367120923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 367220923c1dSRichard Henderson { 367320923c1dSRichard Henderson TCGv t = tcg_temp_new(); 367420923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 367520923c1dSRichard Henderson TCGv u = tcg_temp_new(); 367620923c1dSRichard Henderson 367720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 367820923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 367920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 368020923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 368120923c1dSRichard Henderson 368220923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 368320923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 368420923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 368520923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 368620923c1dSRichard Henderson 368720923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 368820923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 368920923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 369020923c1dSRichard Henderson 369120923c1dSRichard Henderson tcg_temp_free(t); 369220923c1dSRichard Henderson tcg_temp_free(t2); 369320923c1dSRichard Henderson tcg_temp_free(u); 369420923c1dSRichard Henderson } 369520923c1dSRichard Henderson 369614776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 369720ba8504SRichard Henderson { 369820ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 369920ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 370020923c1dSRichard Henderson int rt = rD(ctx->opcode); 370120923c1dSRichard Henderson bool need_serial; 370220ba8504SRichard Henderson TCGv src, dst; 370320ba8504SRichard Henderson 370420ba8504SRichard Henderson gen_addr_register(ctx, EA); 370520923c1dSRichard Henderson dst = cpu_gpr[rt]; 370620923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 370720ba8504SRichard Henderson 370820923c1dSRichard Henderson need_serial = false; 370920ba8504SRichard Henderson memop |= MO_ALIGN; 371020ba8504SRichard Henderson switch (gpr_FC) { 371120ba8504SRichard Henderson case 0: /* Fetch and add */ 371220ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 371320ba8504SRichard Henderson break; 371420ba8504SRichard Henderson case 1: /* Fetch and xor */ 371520ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 371620ba8504SRichard Henderson break; 371720ba8504SRichard Henderson case 2: /* Fetch and or */ 371820ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 371920ba8504SRichard Henderson break; 372020ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 372120ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 372220ba8504SRichard Henderson break; 3723b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3724b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3725b8ce0f86SRichard Henderson break; 3726b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3727b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3728b8ce0f86SRichard Henderson break; 3729b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3730b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3731b8ce0f86SRichard Henderson break; 3732b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3733b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3734b8ce0f86SRichard Henderson break; 373520ba8504SRichard Henderson case 8: /* Swap */ 373620ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 373720ba8504SRichard Henderson break; 373820923c1dSRichard Henderson 373920923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 374020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374120923c1dSRichard Henderson need_serial = true; 374220923c1dSRichard Henderson } else { 374320923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 374420923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 374520923c1dSRichard Henderson 374620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 374720923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 374820923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 374920923c1dSRichard Henderson } else { 375020923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 375120923c1dSRichard Henderson } 375220923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 375320923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 375420923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 375520923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 375620923c1dSRichard Henderson 375720923c1dSRichard Henderson tcg_temp_free(t0); 375820923c1dSRichard Henderson tcg_temp_free(t1); 375920923c1dSRichard Henderson } 376020ba8504SRichard Henderson break; 376120923c1dSRichard Henderson 376220923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 376320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 376420923c1dSRichard Henderson need_serial = true; 376520923c1dSRichard Henderson } else { 376620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 376720923c1dSRichard Henderson } 376820923c1dSRichard Henderson break; 376920923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 377020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 377120923c1dSRichard Henderson need_serial = true; 377220923c1dSRichard Henderson } else { 377320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 377420923c1dSRichard Henderson } 377520923c1dSRichard Henderson break; 377620923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 377720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 377820923c1dSRichard Henderson need_serial = true; 377920923c1dSRichard Henderson } else { 378020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 378120923c1dSRichard Henderson } 378220923c1dSRichard Henderson break; 378320923c1dSRichard Henderson 378420ba8504SRichard Henderson default: 378520ba8504SRichard Henderson /* invoke data storage error handler */ 378620ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 378720ba8504SRichard Henderson } 378820ba8504SRichard Henderson tcg_temp_free(EA); 378920923c1dSRichard Henderson 379020923c1dSRichard Henderson if (need_serial) { 379120923c1dSRichard Henderson /* Restart with exclusive lock. */ 379220923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 379320923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 379420923c1dSRichard Henderson } 3795a68a6146SBalamuruhan S } 3796a68a6146SBalamuruhan S 379720ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 379820ba8504SRichard Henderson { 379920ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 380020ba8504SRichard Henderson } 380120ba8504SRichard Henderson 380220ba8504SRichard Henderson #ifdef TARGET_PPC64 380320ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 380420ba8504SRichard Henderson { 3805fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 380620ba8504SRichard Henderson } 3807a68a6146SBalamuruhan S #endif 3808a68a6146SBalamuruhan S 380914776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 38109deb041cSRichard Henderson { 38119deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 38129deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 38139deb041cSRichard Henderson TCGv src, discard; 38149deb041cSRichard Henderson 38159deb041cSRichard Henderson gen_addr_register(ctx, EA); 38169deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 38179deb041cSRichard Henderson discard = tcg_temp_new(); 38189deb041cSRichard Henderson 38199deb041cSRichard Henderson memop |= MO_ALIGN; 38209deb041cSRichard Henderson switch (gpr_FC) { 38219deb041cSRichard Henderson case 0: /* add and Store */ 38229deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38239deb041cSRichard Henderson break; 38249deb041cSRichard Henderson case 1: /* xor and Store */ 38259deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38269deb041cSRichard Henderson break; 38279deb041cSRichard Henderson case 2: /* Or and Store */ 38289deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38299deb041cSRichard Henderson break; 38309deb041cSRichard Henderson case 3: /* 'and' and Store */ 38319deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38329deb041cSRichard Henderson break; 38339deb041cSRichard Henderson case 4: /* Store max unsigned */ 3834b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3835b8ce0f86SRichard Henderson break; 38369deb041cSRichard Henderson case 5: /* Store max signed */ 3837b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3838b8ce0f86SRichard Henderson break; 38399deb041cSRichard Henderson case 6: /* Store min unsigned */ 3840b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3841b8ce0f86SRichard Henderson break; 38429deb041cSRichard Henderson case 7: /* Store min signed */ 3843b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3844b8ce0f86SRichard Henderson break; 38459deb041cSRichard Henderson case 24: /* Store twin */ 38467fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 38477fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 38487fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 38497fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 38507fbc2b20SRichard Henderson } else { 38517fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 38527fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 38537fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 38547fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 38557fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 38567fbc2b20SRichard Henderson 38577fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 38587fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 38597fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 38607fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 38617fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 38627fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 38637fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 38647fbc2b20SRichard Henderson 38657fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 38667fbc2b20SRichard Henderson tcg_temp_free(s2); 38677fbc2b20SRichard Henderson tcg_temp_free(s); 38687fbc2b20SRichard Henderson tcg_temp_free(t2); 38697fbc2b20SRichard Henderson tcg_temp_free(t); 38707fbc2b20SRichard Henderson } 38719deb041cSRichard Henderson break; 38729deb041cSRichard Henderson default: 38739deb041cSRichard Henderson /* invoke data storage error handler */ 38749deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 38759deb041cSRichard Henderson } 38769deb041cSRichard Henderson tcg_temp_free(discard); 38779deb041cSRichard Henderson tcg_temp_free(EA); 3878a3401188SBalamuruhan S } 3879a3401188SBalamuruhan S 38809deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 38819deb041cSRichard Henderson { 38829deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 38839deb041cSRichard Henderson } 38849deb041cSRichard Henderson 38859deb041cSRichard Henderson #ifdef TARGET_PPC64 38869deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 38879deb041cSRichard Henderson { 3888fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 38899deb041cSRichard Henderson } 3890a3401188SBalamuruhan S #endif 3891a3401188SBalamuruhan S 389214776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3893fcf5ef2aSThomas Huth { 3894253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3895253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3896d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3897d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3898fcf5ef2aSThomas Huth 3899d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3900d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3901d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3902d8b86898SRichard Henderson tcg_temp_free(t0); 3903253ce7b2SNikunj A Dadhania 3904253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3905253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3906253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3907253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3908253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3909253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3910253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3911253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3912253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3913253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3914253ce7b2SNikunj A Dadhania 3915fcf5ef2aSThomas Huth gen_set_label(l1); 39164771df23SNikunj A Dadhania 3917efe843d8SDavid Gibson /* 3918efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3919efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3920efe843d8SDavid Gibson */ 39214771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3922253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3923253ce7b2SNikunj A Dadhania 3924253ce7b2SNikunj A Dadhania gen_set_label(l2); 3925fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3926fcf5ef2aSThomas Huth } 3927fcf5ef2aSThomas Huth 3928fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3929fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3930fcf5ef2aSThomas Huth { \ 3931d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3932fcf5ef2aSThomas Huth } 3933fcf5ef2aSThomas Huth 3934fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3935fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3936fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3937fcf5ef2aSThomas Huth 3938fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3939fcf5ef2aSThomas Huth /* ldarx */ 3940fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3941fcf5ef2aSThomas Huth /* stdcx. */ 3942fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3943fcf5ef2aSThomas Huth 3944fcf5ef2aSThomas Huth /* lqarx */ 3945fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3946fcf5ef2aSThomas Huth { 3947fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 394894bf2658SRichard Henderson TCGv EA, hi, lo; 3949fcf5ef2aSThomas Huth 3950fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3951fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3952fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3953fcf5ef2aSThomas Huth return; 3954fcf5ef2aSThomas Huth } 3955fcf5ef2aSThomas Huth 3956fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 395794bf2658SRichard Henderson EA = tcg_temp_new(); 3958fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 395994bf2658SRichard Henderson 396094bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 396194bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 396294bf2658SRichard Henderson hi = cpu_gpr[rd]; 396394bf2658SRichard Henderson 396494bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3965f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 396694bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 396794bf2658SRichard Henderson if (ctx->le_mode) { 396868e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 396994bf2658SRichard Henderson ctx->mem_idx)); 397094bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3971fcf5ef2aSThomas Huth } else { 397268e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 397394bf2658SRichard Henderson ctx->mem_idx)); 397494bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3975fcf5ef2aSThomas Huth } 397694bf2658SRichard Henderson tcg_temp_free_i32(oi); 397794bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3978f34ec0f6SRichard Henderson } else { 397994bf2658SRichard Henderson /* Restart with exclusive lock. */ 398094bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 398194bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 398294bf2658SRichard Henderson tcg_temp_free(EA); 398394bf2658SRichard Henderson return; 3984f34ec0f6SRichard Henderson } 398594bf2658SRichard Henderson } else if (ctx->le_mode) { 3986fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEUQ | MO_ALIGN_16); 3987fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3988fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3989fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEUQ); 399094bf2658SRichard Henderson } else { 3991fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEUQ | MO_ALIGN_16); 399294bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 399394bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3994fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ); 399594bf2658SRichard Henderson } 3996fcf5ef2aSThomas Huth tcg_temp_free(EA); 399794bf2658SRichard Henderson 399894bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 399994bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4000fcf5ef2aSThomas Huth } 4001fcf5ef2aSThomas Huth 4002fcf5ef2aSThomas Huth /* stqcx. */ 4003fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4004fcf5ef2aSThomas Huth { 4005*894448aeSRichard Henderson TCGLabel *lab_fail, *lab_over; 40064a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 4007*894448aeSRichard Henderson TCGv EA, t0, t1; 4008*894448aeSRichard Henderson TCGv_i128 cmp, val; 4009fcf5ef2aSThomas Huth 40104a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4011fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4012fcf5ef2aSThomas Huth return; 4013fcf5ef2aSThomas Huth } 40144a9b3c5dSRichard Henderson 4015*894448aeSRichard Henderson lab_fail = gen_new_label(); 4016*894448aeSRichard Henderson lab_over = gen_new_label(); 4017*894448aeSRichard Henderson 4018fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 40194a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4020fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4021fcf5ef2aSThomas Huth 40224a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 40234a9b3c5dSRichard Henderson tcg_temp_free(EA); 40244a9b3c5dSRichard Henderson 4025*894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 4026*894448aeSRichard Henderson val = tcg_temp_new_i128(); 40274a9b3c5dSRichard Henderson 4028*894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 40294a9b3c5dSRichard Henderson 4030*894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 4031*894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 40324a9b3c5dSRichard Henderson 4033*894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 4034*894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 4035*894448aeSRichard Henderson tcg_temp_free_i128(cmp); 4036*894448aeSRichard Henderson 4037*894448aeSRichard Henderson t0 = tcg_temp_new(); 4038*894448aeSRichard Henderson t1 = tcg_temp_new(); 4039*894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 4040*894448aeSRichard Henderson tcg_temp_free_i128(val); 4041*894448aeSRichard Henderson 4042*894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 4043*894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 4044*894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 4045*894448aeSRichard Henderson tcg_temp_free(t1); 4046*894448aeSRichard Henderson 4047*894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 4048*894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4049*894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, cpu_so); 4050*894448aeSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4051*894448aeSRichard Henderson tcg_temp_free(t0); 4052*894448aeSRichard Henderson 40534a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 40544a9b3c5dSRichard Henderson gen_set_label(lab_fail); 4055*894448aeSRichard Henderson 4056*894448aeSRichard Henderson /* 4057*894448aeSRichard Henderson * Address mismatch implies failure. But we still need to provide 4058*894448aeSRichard Henderson * the memory barrier semantics of the instruction. 4059*894448aeSRichard Henderson */ 4060*894448aeSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 40614a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40624a9b3c5dSRichard Henderson 40634a9b3c5dSRichard Henderson gen_set_label(lab_over); 40644a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 40654a9b3c5dSRichard Henderson } 4066fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4067fcf5ef2aSThomas Huth 4068fcf5ef2aSThomas Huth /* sync */ 4069fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4070fcf5ef2aSThomas Huth { 407103abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 4072fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4073fcf5ef2aSThomas Huth 407403abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 407503abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 407603abfd90SNicholas Piggin } 407703abfd90SNicholas Piggin 4078fcf5ef2aSThomas Huth /* 4079fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4080fcf5ef2aSThomas Huth * 4081fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4082fcf5ef2aSThomas Huth * 4083fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4084fcf5ef2aSThomas Huth * check MSR_PR as well. 4085fcf5ef2aSThomas Huth */ 4086fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4087fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4088fcf5ef2aSThomas Huth } 408903abfd90SNicholas Piggin 409003abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 4091fcf5ef2aSThomas Huth } 4092fcf5ef2aSThomas Huth 4093fcf5ef2aSThomas Huth /* wait */ 4094fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4095fcf5ef2aSThomas Huth { 40960c9717ffSNicholas Piggin uint32_t wc; 40970c9717ffSNicholas Piggin 40980c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 40990c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 41000c9717ffSNicholas Piggin 41010c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 41020c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 41030c9717ffSNicholas Piggin wc = WC(ctx->opcode); 41040c9717ffSNicholas Piggin } else { 41050c9717ffSNicholas Piggin wc = 0; 41060c9717ffSNicholas Piggin } 41070c9717ffSNicholas Piggin 41080c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 41090c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 41100c9717ffSNicholas Piggin wc = WC(ctx->opcode); 41110c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 41120c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 41130c9717ffSNicholas Piggin 41140c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 41150c9717ffSNicholas Piggin if (wc == 3) { 41160c9717ffSNicholas Piggin gen_invalid(ctx); 41170c9717ffSNicholas Piggin return; 41180c9717ffSNicholas Piggin } 41190c9717ffSNicholas Piggin 41200c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 41210c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 41220c9717ffSNicholas Piggin gen_invalid(ctx); 41230c9717ffSNicholas Piggin return; 41240c9717ffSNicholas Piggin } 41250c9717ffSNicholas Piggin 41260c9717ffSNicholas Piggin } else { /* ISA300 */ 41270c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 41280c9717ffSNicholas Piggin if (wc > 0) { 41290c9717ffSNicholas Piggin gen_invalid(ctx); 41300c9717ffSNicholas Piggin return; 41310c9717ffSNicholas Piggin } 41320c9717ffSNicholas Piggin } 41330c9717ffSNicholas Piggin 41340c9717ffSNicholas Piggin } else { 41350c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 41360c9717ffSNicholas Piggin gen_invalid(ctx); 41370c9717ffSNicholas Piggin return; 41380c9717ffSNicholas Piggin } 41390c9717ffSNicholas Piggin 41400c9717ffSNicholas Piggin /* 41410c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 41420c9717ffSNicholas Piggin * to occur. 41430c9717ffSNicholas Piggin */ 41440c9717ffSNicholas Piggin if (wc == 0) { 4145fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4146fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4147fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4148fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4149fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4150b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4151fcf5ef2aSThomas Huth } 4152fcf5ef2aSThomas Huth 41530c9717ffSNicholas Piggin /* 41540c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 41550c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 41560c9717ffSNicholas Piggin * 41570c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 41580c9717ffSNicholas Piggin * no-ops. 41590c9717ffSNicholas Piggin * 41600c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 41610c9717ffSNicholas Piggin * 41620c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 41630c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 41640c9717ffSNicholas Piggin * 41650c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 41660c9717ffSNicholas Piggin * 41670c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 41680c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 41690c9717ffSNicholas Piggin * can be implemented as a no-op. 41700c9717ffSNicholas Piggin * 41710c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 41720c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 41730c9717ffSNicholas Piggin * no-op. 41740c9717ffSNicholas Piggin * 41750c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 41760c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 41770c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 41780c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 41790c9717ffSNicholas Piggin * (if suboptimal). 41800c9717ffSNicholas Piggin */ 41810c9717ffSNicholas Piggin } 41820c9717ffSNicholas Piggin 4183fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4184fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4185fcf5ef2aSThomas Huth { 4186fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41879f0cf041SMatheus Ferst GEN_PRIV(ctx); 4188fcf5ef2aSThomas Huth #else 4189fcf5ef2aSThomas Huth TCGv_i32 t; 4190fcf5ef2aSThomas Huth 41919f0cf041SMatheus Ferst CHK_HV(ctx); 4192fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4193fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4194fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4195154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4196154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4197fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4198fcf5ef2aSThomas Huth } 4199fcf5ef2aSThomas Huth 4200fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4201fcf5ef2aSThomas Huth { 4202fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42039f0cf041SMatheus Ferst GEN_PRIV(ctx); 4204fcf5ef2aSThomas Huth #else 4205fcf5ef2aSThomas Huth TCGv_i32 t; 4206fcf5ef2aSThomas Huth 42079f0cf041SMatheus Ferst CHK_HV(ctx); 4208fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4209fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4210fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4211154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4212154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4213fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4214fcf5ef2aSThomas Huth } 4215fcf5ef2aSThomas Huth 4216cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4217cdee0e72SNikunj A Dadhania { 421821c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 42199f0cf041SMatheus Ferst GEN_PRIV(ctx); 422021c0d66aSBenjamin Herrenschmidt #else 422121c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 422221c0d66aSBenjamin Herrenschmidt 42239f0cf041SMatheus Ferst CHK_HV(ctx); 422421c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 422521c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 422621c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 422721c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 422821c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 422921c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4230cdee0e72SNikunj A Dadhania } 4231cdee0e72SNikunj A Dadhania 4232fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4233fcf5ef2aSThomas Huth { 4234fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42359f0cf041SMatheus Ferst GEN_PRIV(ctx); 4236fcf5ef2aSThomas Huth #else 4237fcf5ef2aSThomas Huth TCGv_i32 t; 4238fcf5ef2aSThomas Huth 42399f0cf041SMatheus Ferst CHK_HV(ctx); 4240fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4241fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4242fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4243154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4244154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4245fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4246fcf5ef2aSThomas Huth } 4247fcf5ef2aSThomas Huth 4248fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4249fcf5ef2aSThomas Huth { 4250fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42519f0cf041SMatheus Ferst GEN_PRIV(ctx); 4252fcf5ef2aSThomas Huth #else 4253fcf5ef2aSThomas Huth TCGv_i32 t; 4254fcf5ef2aSThomas Huth 42559f0cf041SMatheus Ferst CHK_HV(ctx); 4256fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4257fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4258fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4259154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4260154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4261fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4262fcf5ef2aSThomas Huth } 4263fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4264fcf5ef2aSThomas Huth 4265fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4266fcf5ef2aSThomas Huth { 4267fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4268efe843d8SDavid Gibson if (ctx->has_cfar) { 4269fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4270efe843d8SDavid Gibson } 4271fcf5ef2aSThomas Huth #endif 4272fcf5ef2aSThomas Huth } 4273fcf5ef2aSThomas Huth 427446d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 427546d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 427646d396bdSDaniel Henrique Barboza { 427746d396bdSDaniel Henrique Barboza /* 427846d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 427946d396bdSDaniel Henrique Barboza * instructions. 428046d396bdSDaniel Henrique Barboza */ 428146d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 428246d396bdSDaniel Henrique Barboza return; 428346d396bdSDaniel Henrique Barboza } 428446d396bdSDaniel Henrique Barboza 428546d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4286eeaaefe9SLeandro Lupori TCGLabel *l; 4287eeaaefe9SLeandro Lupori TCGv t0; 4288eeaaefe9SLeandro Lupori 428946d396bdSDaniel Henrique Barboza /* 429046d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 429146d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 429246d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 429346d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 429446d396bdSDaniel Henrique Barboza */ 429546d396bdSDaniel Henrique Barboza gen_icount_io_start(ctx); 429646d396bdSDaniel Henrique Barboza 4297eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4298eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4299eeaaefe9SLeandro Lupori l = gen_new_label(); 4300eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4301eeaaefe9SLeandro Lupori 4302eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4303eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4304eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4305eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4306eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4307eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4308eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4309eeaaefe9SLeandro Lupori } 4310eeaaefe9SLeandro Lupori 4311eeaaefe9SLeandro Lupori gen_set_label(l); 4312eeaaefe9SLeandro Lupori tcg_temp_free(t0); 4313eeaaefe9SLeandro Lupori } else { 431446d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4315eeaaefe9SLeandro Lupori } 431646d396bdSDaniel Henrique Barboza #else 431746d396bdSDaniel Henrique Barboza /* 431846d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 431946d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 432046d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 432146d396bdSDaniel Henrique Barboza */ 432246d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 432346d396bdSDaniel Henrique Barboza 432446d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 432546d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 432646d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 432746d396bdSDaniel Henrique Barboza 432846d396bdSDaniel Henrique Barboza tcg_temp_free(t0); 432946d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 433046d396bdSDaniel Henrique Barboza } 433146d396bdSDaniel Henrique Barboza #else 433246d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 433346d396bdSDaniel Henrique Barboza { 433446d396bdSDaniel Henrique Barboza return; 433546d396bdSDaniel Henrique Barboza } 433646d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 433746d396bdSDaniel Henrique Barboza 4338fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4339fcf5ef2aSThomas Huth { 43406e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4341fcf5ef2aSThomas Huth } 4342fcf5ef2aSThomas Huth 43430e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 43440e3bf489SRoman Kapl { 43459498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 43460e3bf489SRoman Kapl gen_debug_exception(ctx); 43470e3bf489SRoman Kapl } else { 434846d396bdSDaniel Henrique Barboza /* 434946d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 435046d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 435146d396bdSDaniel Henrique Barboza */ 435246d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 435346d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 435446d396bdSDaniel Henrique Barboza } 435546d396bdSDaniel Henrique Barboza 43560e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 43570e3bf489SRoman Kapl } 43580e3bf489SRoman Kapl } 43590e3bf489SRoman Kapl 4360fcf5ef2aSThomas Huth /*** Branch ***/ 4361c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4362fcf5ef2aSThomas Huth { 4363fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4364fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4365fcf5ef2aSThomas Huth } 4366fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 436746d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4368fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4369fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 437007ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4371fcf5ef2aSThomas Huth } else { 4372fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 43730e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4374fcf5ef2aSThomas Huth } 4375fcf5ef2aSThomas Huth } 4376fcf5ef2aSThomas Huth 4377fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4378fcf5ef2aSThomas Huth { 4379fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4380fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4381fcf5ef2aSThomas Huth } 4382fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4383fcf5ef2aSThomas Huth } 4384fcf5ef2aSThomas Huth 4385fcf5ef2aSThomas Huth /* b ba bl bla */ 4386fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4387fcf5ef2aSThomas Huth { 4388fcf5ef2aSThomas Huth target_ulong li, target; 4389fcf5ef2aSThomas Huth 4390fcf5ef2aSThomas Huth /* sign extend LI */ 4391fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4392fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4393fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43942c2bcb1bSRichard Henderson target = ctx->cia + li; 4395fcf5ef2aSThomas Huth } else { 4396fcf5ef2aSThomas Huth target = li; 4397fcf5ef2aSThomas Huth } 4398fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4399b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4400fcf5ef2aSThomas Huth } 44012c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4402fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 44036086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4404fcf5ef2aSThomas Huth } 4405fcf5ef2aSThomas Huth 4406fcf5ef2aSThomas Huth #define BCOND_IM 0 4407fcf5ef2aSThomas Huth #define BCOND_LR 1 4408fcf5ef2aSThomas Huth #define BCOND_CTR 2 4409fcf5ef2aSThomas Huth #define BCOND_TAR 3 4410fcf5ef2aSThomas Huth 4411c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4412fcf5ef2aSThomas Huth { 4413fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4414fcf5ef2aSThomas Huth TCGLabel *l1; 4415fcf5ef2aSThomas Huth TCGv target; 44160e3bf489SRoman Kapl 4417fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4418fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4419efe843d8SDavid Gibson if (type == BCOND_CTR) { 4420fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4421efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4422fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4423efe843d8SDavid Gibson } else { 4424fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4425efe843d8SDavid Gibson } 4426fcf5ef2aSThomas Huth } else { 4427f764718dSRichard Henderson target = NULL; 4428fcf5ef2aSThomas Huth } 4429efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4430b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4431efe843d8SDavid Gibson } 4432fcf5ef2aSThomas Huth l1 = gen_new_label(); 4433fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4434fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4435fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4436fa200c95SGreg Kurz 4437fa200c95SGreg Kurz if (type == BCOND_CTR) { 4438fa200c95SGreg Kurz /* 4439fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4440fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4441fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 444215d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 444315d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 444415d68c5eSGreg Kurz * it basically useless and thus never used in real code. 444515d68c5eSGreg Kurz * 444615d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 444715d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 444815d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 444915d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 445015d68c5eSGreg Kurz * doing anything else harmful. 4451fa200c95SGreg Kurz */ 4452d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4453fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 44549acc95cdSGreg Kurz tcg_temp_free(temp); 44559acc95cdSGreg Kurz tcg_temp_free(target); 4456fcf5ef2aSThomas Huth return; 4457fcf5ef2aSThomas Huth } 4458fa200c95SGreg Kurz 4459fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4460fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4461fa200c95SGreg Kurz } else { 4462fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4463fa200c95SGreg Kurz } 4464fa200c95SGreg Kurz if (bo & 0x2) { 4465fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4466fa200c95SGreg Kurz } else { 4467fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4468fa200c95SGreg Kurz } 4469fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4470fa200c95SGreg Kurz } else { 4471fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4472fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4473fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4474fcf5ef2aSThomas Huth } else { 4475fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4476fcf5ef2aSThomas Huth } 4477fcf5ef2aSThomas Huth if (bo & 0x2) { 4478fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4479fcf5ef2aSThomas Huth } else { 4480fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4481fcf5ef2aSThomas Huth } 4482fa200c95SGreg Kurz } 4483fcf5ef2aSThomas Huth tcg_temp_free(temp); 4484fcf5ef2aSThomas Huth } 4485fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4486fcf5ef2aSThomas Huth /* Test CR */ 4487fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4488fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4489fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4490fcf5ef2aSThomas Huth 4491fcf5ef2aSThomas Huth if (bo & 0x8) { 4492fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4493fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4494fcf5ef2aSThomas Huth } else { 4495fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4496fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4497fcf5ef2aSThomas Huth } 4498fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4499fcf5ef2aSThomas Huth } 45002c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4501fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4502fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4503fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 45042c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4505fcf5ef2aSThomas Huth } else { 4506fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4507fcf5ef2aSThomas Huth } 4508fcf5ef2aSThomas Huth } else { 4509fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4510fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4511fcf5ef2aSThomas Huth } else { 4512fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4513fcf5ef2aSThomas Huth } 45140e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4515c4a2e3a9SRichard Henderson tcg_temp_free(target); 4516c4a2e3a9SRichard Henderson } 4517fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 45180e3bf489SRoman Kapl /* fallthrough case */ 4519fcf5ef2aSThomas Huth gen_set_label(l1); 4520b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4521fcf5ef2aSThomas Huth } 45226086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4523fcf5ef2aSThomas Huth } 4524fcf5ef2aSThomas Huth 4525fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4526fcf5ef2aSThomas Huth { 4527fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4528fcf5ef2aSThomas Huth } 4529fcf5ef2aSThomas Huth 4530fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4531fcf5ef2aSThomas Huth { 4532fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4533fcf5ef2aSThomas Huth } 4534fcf5ef2aSThomas Huth 4535fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4536fcf5ef2aSThomas Huth { 4537fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4538fcf5ef2aSThomas Huth } 4539fcf5ef2aSThomas Huth 4540fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4541fcf5ef2aSThomas Huth { 4542fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4543fcf5ef2aSThomas Huth } 4544fcf5ef2aSThomas Huth 4545fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4546fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4547fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4548fcf5ef2aSThomas Huth { \ 4549fcf5ef2aSThomas Huth uint8_t bitmask; \ 4550fcf5ef2aSThomas Huth int sh; \ 4551fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4552fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4553fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4554fcf5ef2aSThomas Huth if (sh > 0) \ 4555fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4556fcf5ef2aSThomas Huth else if (sh < 0) \ 4557fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4558fcf5ef2aSThomas Huth else \ 4559fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4560fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4561fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4562fcf5ef2aSThomas Huth if (sh > 0) \ 4563fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4564fcf5ef2aSThomas Huth else if (sh < 0) \ 4565fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4566fcf5ef2aSThomas Huth else \ 4567fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4568fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4569fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4570fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4571fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4572fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4573fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4574fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4575fcf5ef2aSThomas Huth } 4576fcf5ef2aSThomas Huth 4577fcf5ef2aSThomas Huth /* crand */ 4578fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4579fcf5ef2aSThomas Huth /* crandc */ 4580fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4581fcf5ef2aSThomas Huth /* creqv */ 4582fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4583fcf5ef2aSThomas Huth /* crnand */ 4584fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4585fcf5ef2aSThomas Huth /* crnor */ 4586fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4587fcf5ef2aSThomas Huth /* cror */ 4588fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4589fcf5ef2aSThomas Huth /* crorc */ 4590fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4591fcf5ef2aSThomas Huth /* crxor */ 4592fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4593fcf5ef2aSThomas Huth 4594fcf5ef2aSThomas Huth /* mcrf */ 4595fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4596fcf5ef2aSThomas Huth { 4597fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4598fcf5ef2aSThomas Huth } 4599fcf5ef2aSThomas Huth 4600fcf5ef2aSThomas Huth /*** System linkage ***/ 4601fcf5ef2aSThomas Huth 4602fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4603fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4604fcf5ef2aSThomas Huth { 4605fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 46069f0cf041SMatheus Ferst GEN_PRIV(ctx); 4607fcf5ef2aSThomas Huth #else 4608efe843d8SDavid Gibson /* 4609efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4610fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4611fcf5ef2aSThomas Huth */ 4612d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4613fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4614fcf5ef2aSThomas Huth return; 4615fcf5ef2aSThomas Huth } 4616fcf5ef2aSThomas Huth /* Restore CPU state */ 46179f0cf041SMatheus Ferst CHK_SV(ctx); 4618f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46192c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4620fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 462159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4622fcf5ef2aSThomas Huth #endif 4623fcf5ef2aSThomas Huth } 4624fcf5ef2aSThomas Huth 4625fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4626fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4627fcf5ef2aSThomas Huth { 4628fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 46299f0cf041SMatheus Ferst GEN_PRIV(ctx); 4630fcf5ef2aSThomas Huth #else 4631fcf5ef2aSThomas Huth /* Restore CPU state */ 46329f0cf041SMatheus Ferst CHK_SV(ctx); 4633f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46342c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4635fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 463659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4637fcf5ef2aSThomas Huth #endif 4638fcf5ef2aSThomas Huth } 4639fcf5ef2aSThomas Huth 46403c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46413c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 46423c89b8d6SNicholas Piggin { 46433c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 46449f0cf041SMatheus Ferst GEN_PRIV(ctx); 46453c89b8d6SNicholas Piggin #else 46463c89b8d6SNicholas Piggin /* Restore CPU state */ 46479f0cf041SMatheus Ferst CHK_SV(ctx); 4648f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46492c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 46503c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 465159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 46523c89b8d6SNicholas Piggin #endif 46533c89b8d6SNicholas Piggin } 46543c89b8d6SNicholas Piggin #endif 46553c89b8d6SNicholas Piggin 4656fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4657fcf5ef2aSThomas Huth { 4658fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 46599f0cf041SMatheus Ferst GEN_PRIV(ctx); 4660fcf5ef2aSThomas Huth #else 4661fcf5ef2aSThomas Huth /* Restore CPU state */ 46629f0cf041SMatheus Ferst CHK_HV(ctx); 4663fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 466459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4665fcf5ef2aSThomas Huth #endif 4666fcf5ef2aSThomas Huth } 4667fcf5ef2aSThomas Huth #endif 4668fcf5ef2aSThomas Huth 4669fcf5ef2aSThomas Huth /* sc */ 4670fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4671fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4672fcf5ef2aSThomas Huth #else 4673fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 46743c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4675fcf5ef2aSThomas Huth #endif 4676fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4677fcf5ef2aSThomas Huth { 4678fcf5ef2aSThomas Huth uint32_t lev; 4679fcf5ef2aSThomas Huth 4680fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4681fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4682fcf5ef2aSThomas Huth } 4683fcf5ef2aSThomas Huth 46843c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 46853c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46863c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 46873c89b8d6SNicholas Piggin { 4688f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 46893c89b8d6SNicholas Piggin 4690f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 46912c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4692f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 46933c89b8d6SNicholas Piggin 46947a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 46953c89b8d6SNicholas Piggin } 46963c89b8d6SNicholas Piggin #endif 46973c89b8d6SNicholas Piggin #endif 46983c89b8d6SNicholas Piggin 4699fcf5ef2aSThomas Huth /*** Trap ***/ 4700fcf5ef2aSThomas Huth 4701fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4702fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4703fcf5ef2aSThomas Huth { 4704fcf5ef2aSThomas Huth /* Trap never */ 4705fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4706fcf5ef2aSThomas Huth return true; 4707fcf5ef2aSThomas Huth } 4708fcf5ef2aSThomas Huth /* Trap always */ 4709fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4710fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4711fcf5ef2aSThomas Huth return true; 4712fcf5ef2aSThomas Huth } 4713fcf5ef2aSThomas Huth return false; 4714fcf5ef2aSThomas Huth } 4715fcf5ef2aSThomas Huth 4716fcf5ef2aSThomas Huth /* tw */ 4717fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4718fcf5ef2aSThomas Huth { 4719fcf5ef2aSThomas Huth TCGv_i32 t0; 4720fcf5ef2aSThomas Huth 4721fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4722fcf5ef2aSThomas Huth return; 4723fcf5ef2aSThomas Huth } 4724fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4725fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4726fcf5ef2aSThomas Huth t0); 4727fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4728fcf5ef2aSThomas Huth } 4729fcf5ef2aSThomas Huth 4730fcf5ef2aSThomas Huth /* twi */ 4731fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4732fcf5ef2aSThomas Huth { 4733fcf5ef2aSThomas Huth TCGv t0; 4734fcf5ef2aSThomas Huth TCGv_i32 t1; 4735fcf5ef2aSThomas Huth 4736fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4737fcf5ef2aSThomas Huth return; 4738fcf5ef2aSThomas Huth } 4739fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4740fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4741fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4742fcf5ef2aSThomas Huth tcg_temp_free(t0); 4743fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4744fcf5ef2aSThomas Huth } 4745fcf5ef2aSThomas Huth 4746fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4747fcf5ef2aSThomas Huth /* td */ 4748fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4749fcf5ef2aSThomas Huth { 4750fcf5ef2aSThomas Huth TCGv_i32 t0; 4751fcf5ef2aSThomas Huth 4752fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4753fcf5ef2aSThomas Huth return; 4754fcf5ef2aSThomas Huth } 4755fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4756fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4757fcf5ef2aSThomas Huth t0); 4758fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4759fcf5ef2aSThomas Huth } 4760fcf5ef2aSThomas Huth 4761fcf5ef2aSThomas Huth /* tdi */ 4762fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4763fcf5ef2aSThomas Huth { 4764fcf5ef2aSThomas Huth TCGv t0; 4765fcf5ef2aSThomas Huth TCGv_i32 t1; 4766fcf5ef2aSThomas Huth 4767fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4768fcf5ef2aSThomas Huth return; 4769fcf5ef2aSThomas Huth } 4770fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4771fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4772fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4773fcf5ef2aSThomas Huth tcg_temp_free(t0); 4774fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4775fcf5ef2aSThomas Huth } 4776fcf5ef2aSThomas Huth #endif 4777fcf5ef2aSThomas Huth 4778fcf5ef2aSThomas Huth /*** Processor control ***/ 4779fcf5ef2aSThomas Huth 4780fcf5ef2aSThomas Huth /* mcrxr */ 4781fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4782fcf5ef2aSThomas Huth { 4783fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4784fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4785fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4786fcf5ef2aSThomas Huth 4787fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4788fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4789fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4790fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4791fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4792fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4793fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4794fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4795fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4796fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4797fcf5ef2aSThomas Huth 4798fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4799fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4800fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4801fcf5ef2aSThomas Huth } 4802fcf5ef2aSThomas Huth 4803b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4804b63d0434SNikunj A Dadhania /* mcrxrx */ 4805b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4806b63d0434SNikunj A Dadhania { 4807b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4808b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4809b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4810b63d0434SNikunj A Dadhania 4811b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4812b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4813b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4814b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4815b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4816b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4817b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4818b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4819b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4820b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4821b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4822b63d0434SNikunj A Dadhania } 4823b63d0434SNikunj A Dadhania #endif 4824b63d0434SNikunj A Dadhania 4825fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4826fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4827fcf5ef2aSThomas Huth { 4828fcf5ef2aSThomas Huth uint32_t crm, crn; 4829fcf5ef2aSThomas Huth 4830fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4831fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4832fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4833fcf5ef2aSThomas Huth crn = ctz32(crm); 4834fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4835fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4836fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4837fcf5ef2aSThomas Huth } 4838fcf5ef2aSThomas Huth } else { 4839fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4840fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4841fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4842fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4843fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4844fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4845fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4846fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4847fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4848fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4849fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4850fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4851fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4852fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4853fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4854fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4855fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4856fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4857fcf5ef2aSThomas Huth } 4858fcf5ef2aSThomas Huth } 4859fcf5ef2aSThomas Huth 4860fcf5ef2aSThomas Huth /* mfmsr */ 4861fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4862fcf5ef2aSThomas Huth { 48639f0cf041SMatheus Ferst CHK_SV(ctx); 4864fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4865fcf5ef2aSThomas Huth } 4866fcf5ef2aSThomas Huth 4867fcf5ef2aSThomas Huth /* mfspr */ 4868fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4869fcf5ef2aSThomas Huth { 4870fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4871fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4872fcf5ef2aSThomas Huth 4873fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4874fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4875fcf5ef2aSThomas Huth #else 4876fcf5ef2aSThomas Huth if (ctx->pr) { 4877fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4878fcf5ef2aSThomas Huth } else if (ctx->hv) { 4879fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4880fcf5ef2aSThomas Huth } else { 4881fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4882fcf5ef2aSThomas Huth } 4883fcf5ef2aSThomas Huth #endif 4884fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4885fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4886fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4887fcf5ef2aSThomas Huth } else { 4888fcf5ef2aSThomas Huth /* Privilege exception */ 4889efe843d8SDavid Gibson /* 4890efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4891fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4892fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4893fcf5ef2aSThomas Huth */ 4894fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 489531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 489631085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48972c2bcb1bSRichard Henderson ctx->cia); 4898fcf5ef2aSThomas Huth } 4899fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4900fcf5ef2aSThomas Huth } 4901fcf5ef2aSThomas Huth } else { 4902fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4903fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4904fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4905fcf5ef2aSThomas Huth /* This is a nop */ 4906fcf5ef2aSThomas Huth return; 4907fcf5ef2aSThomas Huth } 4908fcf5ef2aSThomas Huth /* Not defined */ 490931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 491031085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 49112c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4912fcf5ef2aSThomas Huth 4913efe843d8SDavid Gibson /* 4914efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4915efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4916fcf5ef2aSThomas Huth */ 4917fcf5ef2aSThomas Huth if (sprn & 0x10) { 4918fcf5ef2aSThomas Huth if (ctx->pr) { 49191315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4920fcf5ef2aSThomas Huth } 4921fcf5ef2aSThomas Huth } else { 4922fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 49231315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4924fcf5ef2aSThomas Huth } 4925fcf5ef2aSThomas Huth } 4926fcf5ef2aSThomas Huth } 4927fcf5ef2aSThomas Huth } 4928fcf5ef2aSThomas Huth 4929fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4930fcf5ef2aSThomas Huth { 4931fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4932fcf5ef2aSThomas Huth } 4933fcf5ef2aSThomas Huth 4934fcf5ef2aSThomas Huth /* mftb */ 4935fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4936fcf5ef2aSThomas Huth { 4937fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4938fcf5ef2aSThomas Huth } 4939fcf5ef2aSThomas Huth 4940fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4941fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4942fcf5ef2aSThomas Huth { 4943fcf5ef2aSThomas Huth uint32_t crm, crn; 4944fcf5ef2aSThomas Huth 4945fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4946fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4947fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4948fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4949fcf5ef2aSThomas Huth crn = ctz32(crm); 4950fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4951fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4952fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4953fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4954fcf5ef2aSThomas Huth } 4955fcf5ef2aSThomas Huth } else { 4956fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4957fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4958fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4959fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4960fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4961fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4962fcf5ef2aSThomas Huth } 4963fcf5ef2aSThomas Huth } 4964fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4965fcf5ef2aSThomas Huth } 4966fcf5ef2aSThomas Huth } 4967fcf5ef2aSThomas Huth 4968fcf5ef2aSThomas Huth /* mtmsr */ 4969fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4970fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4971fcf5ef2aSThomas Huth { 4972caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4973caf590ddSNicholas Piggin gen_invalid(ctx); 4974caf590ddSNicholas Piggin return; 4975caf590ddSNicholas Piggin } 4976caf590ddSNicholas Piggin 49779f0cf041SMatheus Ferst CHK_SV(ctx); 4978fcf5ef2aSThomas Huth 4979fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49806fa5726bSMatheus Ferst TCGv t0, t1; 49816fa5726bSMatheus Ferst target_ulong mask; 49826fa5726bSMatheus Ferst 49836fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49846fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49856fa5726bSMatheus Ferst 4986f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49876fa5726bSMatheus Ferst 4988fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49895ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49906fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4991fcf5ef2aSThomas Huth } else { 49926fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 49936fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 49946fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4995efe843d8SDavid Gibson /* 4996efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4997efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4998efe843d8SDavid Gibson * ppc_store_msr 4999fcf5ef2aSThomas Huth */ 5000b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5001fcf5ef2aSThomas Huth } 50026fa5726bSMatheus Ferst 50036fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 50046fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 50056fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 50066fa5726bSMatheus Ferst 50076fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 50086fa5726bSMatheus Ferst 50095ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5010d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 50116fa5726bSMatheus Ferst 50126fa5726bSMatheus Ferst tcg_temp_free(t0); 50136fa5726bSMatheus Ferst tcg_temp_free(t1); 5014fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5015fcf5ef2aSThomas Huth } 5016fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5017fcf5ef2aSThomas Huth 5018fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5019fcf5ef2aSThomas Huth { 50209f0cf041SMatheus Ferst CHK_SV(ctx); 5021fcf5ef2aSThomas Huth 5022fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 50236fa5726bSMatheus Ferst TCGv t0, t1; 50246fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 50256fa5726bSMatheus Ferst 50266fa5726bSMatheus Ferst t0 = tcg_temp_new(); 50276fa5726bSMatheus Ferst t1 = tcg_temp_new(); 50286fa5726bSMatheus Ferst 5029f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5030fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 50315ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 50326fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 5033fcf5ef2aSThomas Huth } else { 50346fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 50356fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 5036fcf5ef2aSThomas Huth 5037efe843d8SDavid Gibson /* 5038efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5039efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5040efe843d8SDavid Gibson * ppc_store_msr 5041fcf5ef2aSThomas Huth */ 5042b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5043fcf5ef2aSThomas Huth } 50446fa5726bSMatheus Ferst 50456fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 50466fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 50476fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 50486fa5726bSMatheus Ferst 50496fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 50506fa5726bSMatheus Ferst 50515ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5052d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 50536fa5726bSMatheus Ferst 50546fa5726bSMatheus Ferst tcg_temp_free(t0); 50556fa5726bSMatheus Ferst tcg_temp_free(t1); 5056fcf5ef2aSThomas Huth #endif 5057fcf5ef2aSThomas Huth } 5058fcf5ef2aSThomas Huth 5059fcf5ef2aSThomas Huth /* mtspr */ 5060fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5061fcf5ef2aSThomas Huth { 5062fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5063fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5064fcf5ef2aSThomas Huth 5065fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5066fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5067fcf5ef2aSThomas Huth #else 5068fcf5ef2aSThomas Huth if (ctx->pr) { 5069fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5070fcf5ef2aSThomas Huth } else if (ctx->hv) { 5071fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5072fcf5ef2aSThomas Huth } else { 5073fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5074fcf5ef2aSThomas Huth } 5075fcf5ef2aSThomas Huth #endif 5076fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5077fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5078fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5079fcf5ef2aSThomas Huth } else { 5080fcf5ef2aSThomas Huth /* Privilege exception */ 508131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 508231085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 50832c2bcb1bSRichard Henderson ctx->cia); 5084fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5085fcf5ef2aSThomas Huth } 5086fcf5ef2aSThomas Huth } else { 5087fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5088fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5089fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5090fcf5ef2aSThomas Huth /* This is a nop */ 5091fcf5ef2aSThomas Huth return; 5092fcf5ef2aSThomas Huth } 5093fcf5ef2aSThomas Huth 5094fcf5ef2aSThomas Huth /* Not defined */ 509531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 509631085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 50972c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5098fcf5ef2aSThomas Huth 5099fcf5ef2aSThomas Huth 5100efe843d8SDavid Gibson /* 5101efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5102efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5103fcf5ef2aSThomas Huth */ 5104fcf5ef2aSThomas Huth if (sprn & 0x10) { 5105fcf5ef2aSThomas Huth if (ctx->pr) { 51061315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5107fcf5ef2aSThomas Huth } 5108fcf5ef2aSThomas Huth } else { 5109fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 51101315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5111fcf5ef2aSThomas Huth } 5112fcf5ef2aSThomas Huth } 5113fcf5ef2aSThomas Huth } 5114fcf5ef2aSThomas Huth } 5115fcf5ef2aSThomas Huth 5116fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5117fcf5ef2aSThomas Huth /* setb */ 5118fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5119fcf5ef2aSThomas Huth { 5120fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 51216f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 51226f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5123fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5124fcf5ef2aSThomas Huth 5125fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5126fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5127fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5128fcf5ef2aSThomas Huth 5129fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5130fcf5ef2aSThomas Huth } 5131fcf5ef2aSThomas Huth #endif 5132fcf5ef2aSThomas Huth 5133fcf5ef2aSThomas Huth /*** Cache management ***/ 5134fcf5ef2aSThomas Huth 5135fcf5ef2aSThomas Huth /* dcbf */ 5136fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5137fcf5ef2aSThomas Huth { 5138fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5139fcf5ef2aSThomas Huth TCGv t0; 5140fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5141fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5142fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5143fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5144fcf5ef2aSThomas Huth tcg_temp_free(t0); 5145fcf5ef2aSThomas Huth } 5146fcf5ef2aSThomas Huth 514750728199SRoman Kapl /* dcbfep (external PID dcbf) */ 514850728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 514950728199SRoman Kapl { 515050728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 515150728199SRoman Kapl TCGv t0; 51529f0cf041SMatheus Ferst CHK_SV(ctx); 515350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 515450728199SRoman Kapl t0 = tcg_temp_new(); 515550728199SRoman Kapl gen_addr_reg_index(ctx, t0); 515650728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 515750728199SRoman Kapl tcg_temp_free(t0); 515850728199SRoman Kapl } 515950728199SRoman Kapl 5160fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5161fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5162fcf5ef2aSThomas Huth { 5163fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5165fcf5ef2aSThomas Huth #else 5166fcf5ef2aSThomas Huth TCGv EA, val; 5167fcf5ef2aSThomas Huth 51689f0cf041SMatheus Ferst CHK_SV(ctx); 5169fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5170fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5171fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5172fcf5ef2aSThomas Huth val = tcg_temp_new(); 5173fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5174fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5175fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5176fcf5ef2aSThomas Huth tcg_temp_free(val); 5177fcf5ef2aSThomas Huth tcg_temp_free(EA); 5178fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5179fcf5ef2aSThomas Huth } 5180fcf5ef2aSThomas Huth 5181fcf5ef2aSThomas Huth /* dcdst */ 5182fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5183fcf5ef2aSThomas Huth { 5184fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5185fcf5ef2aSThomas Huth TCGv t0; 5186fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5187fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5188fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5189fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5190fcf5ef2aSThomas Huth tcg_temp_free(t0); 5191fcf5ef2aSThomas Huth } 5192fcf5ef2aSThomas Huth 519350728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 519450728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 519550728199SRoman Kapl { 519650728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 519750728199SRoman Kapl TCGv t0; 519850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 519950728199SRoman Kapl t0 = tcg_temp_new(); 520050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 520150728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 520250728199SRoman Kapl tcg_temp_free(t0); 520350728199SRoman Kapl } 520450728199SRoman Kapl 5205fcf5ef2aSThomas Huth /* dcbt */ 5206fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5207fcf5ef2aSThomas Huth { 5208efe843d8SDavid Gibson /* 5209efe843d8SDavid Gibson * interpreted as no-op 5210efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5211efe843d8SDavid Gibson * does not generate any exception 5212fcf5ef2aSThomas Huth */ 5213fcf5ef2aSThomas Huth } 5214fcf5ef2aSThomas Huth 521550728199SRoman Kapl /* dcbtep */ 521650728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 521750728199SRoman Kapl { 5218efe843d8SDavid Gibson /* 5219efe843d8SDavid Gibson * interpreted as no-op 5220efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5221efe843d8SDavid Gibson * does not generate any exception 522250728199SRoman Kapl */ 522350728199SRoman Kapl } 522450728199SRoman Kapl 5225fcf5ef2aSThomas Huth /* dcbtst */ 5226fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5227fcf5ef2aSThomas Huth { 5228efe843d8SDavid Gibson /* 5229efe843d8SDavid Gibson * interpreted as no-op 5230efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5231efe843d8SDavid Gibson * does not generate any exception 5232fcf5ef2aSThomas Huth */ 5233fcf5ef2aSThomas Huth } 5234fcf5ef2aSThomas Huth 523550728199SRoman Kapl /* dcbtstep */ 523650728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 523750728199SRoman Kapl { 5238efe843d8SDavid Gibson /* 5239efe843d8SDavid Gibson * interpreted as no-op 5240efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5241efe843d8SDavid Gibson * does not generate any exception 524250728199SRoman Kapl */ 524350728199SRoman Kapl } 524450728199SRoman Kapl 5245fcf5ef2aSThomas Huth /* dcbtls */ 5246fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5247fcf5ef2aSThomas Huth { 5248fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5249fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5250fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5251fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5252fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5253fcf5ef2aSThomas Huth tcg_temp_free(t0); 5254fcf5ef2aSThomas Huth } 5255fcf5ef2aSThomas Huth 5256fcf5ef2aSThomas Huth /* dcbz */ 5257fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5258fcf5ef2aSThomas Huth { 5259fcf5ef2aSThomas Huth TCGv tcgv_addr; 5260fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5261fcf5ef2aSThomas Huth 5262fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5263fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5264fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5265fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5266fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5267fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5268fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5269fcf5ef2aSThomas Huth } 5270fcf5ef2aSThomas Huth 527150728199SRoman Kapl /* dcbzep */ 527250728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 527350728199SRoman Kapl { 527450728199SRoman Kapl TCGv tcgv_addr; 527550728199SRoman Kapl TCGv_i32 tcgv_op; 527650728199SRoman Kapl 527750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 527850728199SRoman Kapl tcgv_addr = tcg_temp_new(); 527950728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 528050728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 528150728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 528250728199SRoman Kapl tcg_temp_free(tcgv_addr); 528350728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 528450728199SRoman Kapl } 528550728199SRoman Kapl 5286fcf5ef2aSThomas Huth /* dst / dstt */ 5287fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5288fcf5ef2aSThomas Huth { 5289fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5290fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5291fcf5ef2aSThomas Huth } else { 5292fcf5ef2aSThomas Huth /* interpreted as no-op */ 5293fcf5ef2aSThomas Huth } 5294fcf5ef2aSThomas Huth } 5295fcf5ef2aSThomas Huth 5296fcf5ef2aSThomas Huth /* dstst /dststt */ 5297fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5298fcf5ef2aSThomas Huth { 5299fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5300fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5301fcf5ef2aSThomas Huth } else { 5302fcf5ef2aSThomas Huth /* interpreted as no-op */ 5303fcf5ef2aSThomas Huth } 5304fcf5ef2aSThomas Huth 5305fcf5ef2aSThomas Huth } 5306fcf5ef2aSThomas Huth 5307fcf5ef2aSThomas Huth /* dss / dssall */ 5308fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5309fcf5ef2aSThomas Huth { 5310fcf5ef2aSThomas Huth /* interpreted as no-op */ 5311fcf5ef2aSThomas Huth } 5312fcf5ef2aSThomas Huth 5313fcf5ef2aSThomas Huth /* icbi */ 5314fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5315fcf5ef2aSThomas Huth { 5316fcf5ef2aSThomas Huth TCGv t0; 5317fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5318fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5319fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5320fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5321fcf5ef2aSThomas Huth tcg_temp_free(t0); 5322fcf5ef2aSThomas Huth } 5323fcf5ef2aSThomas Huth 532450728199SRoman Kapl /* icbiep */ 532550728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 532650728199SRoman Kapl { 532750728199SRoman Kapl TCGv t0; 532850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 532950728199SRoman Kapl t0 = tcg_temp_new(); 533050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 533150728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 533250728199SRoman Kapl tcg_temp_free(t0); 533350728199SRoman Kapl } 533450728199SRoman Kapl 5335fcf5ef2aSThomas Huth /* Optional: */ 5336fcf5ef2aSThomas Huth /* dcba */ 5337fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5338fcf5ef2aSThomas Huth { 5339efe843d8SDavid Gibson /* 5340efe843d8SDavid Gibson * interpreted as no-op 5341efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5342fcf5ef2aSThomas Huth * but does not generate any exception 5343fcf5ef2aSThomas Huth */ 5344fcf5ef2aSThomas Huth } 5345fcf5ef2aSThomas Huth 5346fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5347fcf5ef2aSThomas Huth /* Supervisor only: */ 5348fcf5ef2aSThomas Huth 5349fcf5ef2aSThomas Huth /* mfsr */ 5350fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5351fcf5ef2aSThomas Huth { 5352fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53539f0cf041SMatheus Ferst GEN_PRIV(ctx); 5354fcf5ef2aSThomas Huth #else 5355fcf5ef2aSThomas Huth TCGv t0; 5356fcf5ef2aSThomas Huth 53579f0cf041SMatheus Ferst CHK_SV(ctx); 5358fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5359fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5360fcf5ef2aSThomas Huth tcg_temp_free(t0); 5361fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5362fcf5ef2aSThomas Huth } 5363fcf5ef2aSThomas Huth 5364fcf5ef2aSThomas Huth /* mfsrin */ 5365fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5366fcf5ef2aSThomas Huth { 5367fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53689f0cf041SMatheus Ferst GEN_PRIV(ctx); 5369fcf5ef2aSThomas Huth #else 5370fcf5ef2aSThomas Huth TCGv t0; 5371fcf5ef2aSThomas Huth 53729f0cf041SMatheus Ferst CHK_SV(ctx); 5373fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5374e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5375fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5376fcf5ef2aSThomas Huth tcg_temp_free(t0); 5377fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5378fcf5ef2aSThomas Huth } 5379fcf5ef2aSThomas Huth 5380fcf5ef2aSThomas Huth /* mtsr */ 5381fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5382fcf5ef2aSThomas Huth { 5383fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53849f0cf041SMatheus Ferst GEN_PRIV(ctx); 5385fcf5ef2aSThomas Huth #else 5386fcf5ef2aSThomas Huth TCGv t0; 5387fcf5ef2aSThomas Huth 53889f0cf041SMatheus Ferst CHK_SV(ctx); 5389fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5390fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5391fcf5ef2aSThomas Huth tcg_temp_free(t0); 5392fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5393fcf5ef2aSThomas Huth } 5394fcf5ef2aSThomas Huth 5395fcf5ef2aSThomas Huth /* mtsrin */ 5396fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5397fcf5ef2aSThomas Huth { 5398fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53999f0cf041SMatheus Ferst GEN_PRIV(ctx); 5400fcf5ef2aSThomas Huth #else 5401fcf5ef2aSThomas Huth TCGv t0; 54029f0cf041SMatheus Ferst CHK_SV(ctx); 5403fcf5ef2aSThomas Huth 5404fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5405e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5406fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5407fcf5ef2aSThomas Huth tcg_temp_free(t0); 5408fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5409fcf5ef2aSThomas Huth } 5410fcf5ef2aSThomas Huth 5411fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5412fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5413fcf5ef2aSThomas Huth 5414fcf5ef2aSThomas Huth /* mfsr */ 5415fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5416fcf5ef2aSThomas Huth { 5417fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54189f0cf041SMatheus Ferst GEN_PRIV(ctx); 5419fcf5ef2aSThomas Huth #else 5420fcf5ef2aSThomas Huth TCGv t0; 5421fcf5ef2aSThomas Huth 54229f0cf041SMatheus Ferst CHK_SV(ctx); 5423fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5424fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5425fcf5ef2aSThomas Huth tcg_temp_free(t0); 5426fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5427fcf5ef2aSThomas Huth } 5428fcf5ef2aSThomas Huth 5429fcf5ef2aSThomas Huth /* mfsrin */ 5430fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5431fcf5ef2aSThomas Huth { 5432fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54339f0cf041SMatheus Ferst GEN_PRIV(ctx); 5434fcf5ef2aSThomas Huth #else 5435fcf5ef2aSThomas Huth TCGv t0; 5436fcf5ef2aSThomas Huth 54379f0cf041SMatheus Ferst CHK_SV(ctx); 5438fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5439e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5440fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5441fcf5ef2aSThomas Huth tcg_temp_free(t0); 5442fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5443fcf5ef2aSThomas Huth } 5444fcf5ef2aSThomas Huth 5445fcf5ef2aSThomas Huth /* mtsr */ 5446fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5447fcf5ef2aSThomas Huth { 5448fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54499f0cf041SMatheus Ferst GEN_PRIV(ctx); 5450fcf5ef2aSThomas Huth #else 5451fcf5ef2aSThomas Huth TCGv t0; 5452fcf5ef2aSThomas Huth 54539f0cf041SMatheus Ferst CHK_SV(ctx); 5454fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5455fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5456fcf5ef2aSThomas Huth tcg_temp_free(t0); 5457fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5458fcf5ef2aSThomas Huth } 5459fcf5ef2aSThomas Huth 5460fcf5ef2aSThomas Huth /* mtsrin */ 5461fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5462fcf5ef2aSThomas Huth { 5463fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5465fcf5ef2aSThomas Huth #else 5466fcf5ef2aSThomas Huth TCGv t0; 5467fcf5ef2aSThomas Huth 54689f0cf041SMatheus Ferst CHK_SV(ctx); 5469fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5470e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5471fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5472fcf5ef2aSThomas Huth tcg_temp_free(t0); 5473fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5474fcf5ef2aSThomas Huth } 5475fcf5ef2aSThomas Huth 5476fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5477fcf5ef2aSThomas Huth 5478fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5479fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5480fcf5ef2aSThomas Huth 5481fcf5ef2aSThomas Huth /* tlbia */ 5482fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5483fcf5ef2aSThomas Huth { 5484fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54859f0cf041SMatheus Ferst GEN_PRIV(ctx); 5486fcf5ef2aSThomas Huth #else 54879f0cf041SMatheus Ferst CHK_HV(ctx); 5488fcf5ef2aSThomas Huth 5489fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5490fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5491fcf5ef2aSThomas Huth } 5492fcf5ef2aSThomas Huth 5493fcf5ef2aSThomas Huth /* tlbsync */ 5494fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5495fcf5ef2aSThomas Huth { 5496fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54979f0cf041SMatheus Ferst GEN_PRIV(ctx); 5498fcf5ef2aSThomas Huth #else 549991c60f12SCédric Le Goater 550091c60f12SCédric Le Goater if (ctx->gtse) { 55019f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 550291c60f12SCédric Le Goater } else { 55039f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 550491c60f12SCédric Le Goater } 5505fcf5ef2aSThomas Huth 5506fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5507fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5508fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5509fcf5ef2aSThomas Huth } 5510fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5511fcf5ef2aSThomas Huth } 5512fcf5ef2aSThomas Huth 5513fcf5ef2aSThomas Huth /*** External control ***/ 5514fcf5ef2aSThomas Huth /* Optional: */ 5515fcf5ef2aSThomas Huth 5516fcf5ef2aSThomas Huth /* eciwx */ 5517fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5518fcf5ef2aSThomas Huth { 5519fcf5ef2aSThomas Huth TCGv t0; 5520fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5521fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5522fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5523fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5524c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5525c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5526fcf5ef2aSThomas Huth tcg_temp_free(t0); 5527fcf5ef2aSThomas Huth } 5528fcf5ef2aSThomas Huth 5529fcf5ef2aSThomas Huth /* ecowx */ 5530fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5531fcf5ef2aSThomas Huth { 5532fcf5ef2aSThomas Huth TCGv t0; 5533fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5534fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5535fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5536fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5537c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5538c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5539fcf5ef2aSThomas Huth tcg_temp_free(t0); 5540fcf5ef2aSThomas Huth } 5541fcf5ef2aSThomas Huth 5542fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5543fcf5ef2aSThomas Huth 5544fcf5ef2aSThomas Huth /* tlbld */ 5545fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5546fcf5ef2aSThomas Huth { 5547fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55489f0cf041SMatheus Ferst GEN_PRIV(ctx); 5549fcf5ef2aSThomas Huth #else 55509f0cf041SMatheus Ferst CHK_SV(ctx); 5551fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5552fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5553fcf5ef2aSThomas Huth } 5554fcf5ef2aSThomas Huth 5555fcf5ef2aSThomas Huth /* tlbli */ 5556fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5557fcf5ef2aSThomas Huth { 5558fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55599f0cf041SMatheus Ferst GEN_PRIV(ctx); 5560fcf5ef2aSThomas Huth #else 55619f0cf041SMatheus Ferst CHK_SV(ctx); 5562fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5563fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5564fcf5ef2aSThomas Huth } 5565fcf5ef2aSThomas Huth 5566fcf5ef2aSThomas Huth /* BookE specific instructions */ 5567fcf5ef2aSThomas Huth 5568fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5569fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5570fcf5ef2aSThomas Huth { 5571fcf5ef2aSThomas Huth /* XXX: TODO */ 5572fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5573fcf5ef2aSThomas Huth } 5574fcf5ef2aSThomas Huth 5575fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5576fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5577fcf5ef2aSThomas Huth { 5578fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55799f0cf041SMatheus Ferst GEN_PRIV(ctx); 5580fcf5ef2aSThomas Huth #else 5581fcf5ef2aSThomas Huth TCGv t0; 5582fcf5ef2aSThomas Huth 55839f0cf041SMatheus Ferst CHK_SV(ctx); 5584fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5585fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5586fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5587fcf5ef2aSThomas Huth tcg_temp_free(t0); 5588fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5589fcf5ef2aSThomas Huth } 5590fcf5ef2aSThomas Huth 5591fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5592fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5593fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5594fcf5ef2aSThomas Huth { 5595fcf5ef2aSThomas Huth TCGv t0, t1; 5596fcf5ef2aSThomas Huth 5597fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5598fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5599fcf5ef2aSThomas Huth 5600fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5601fcf5ef2aSThomas Huth case 0x05: 5602fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5603fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5604fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5605fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5606fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5607fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5608fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5609fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5610fcf5ef2aSThomas Huth break; 5611fcf5ef2aSThomas Huth case 0x04: 5612fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5613fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5614fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5615fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5616fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5617fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5618fcf5ef2aSThomas Huth break; 5619fcf5ef2aSThomas Huth case 0x01: 5620fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5621fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5622fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5623fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5624fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5625fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5626fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5627fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5628fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5629fcf5ef2aSThomas Huth break; 5630fcf5ef2aSThomas Huth case 0x00: 5631fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5632fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5633fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5634fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5635fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5636fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5637fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5638fcf5ef2aSThomas Huth break; 5639fcf5ef2aSThomas Huth case 0x0D: 5640fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5641fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5642fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5643fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5644fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5645fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5646fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5647fcf5ef2aSThomas Huth break; 5648fcf5ef2aSThomas Huth case 0x0C: 5649fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5650fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5651fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5652fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5653fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5654fcf5ef2aSThomas Huth break; 5655fcf5ef2aSThomas Huth } 5656fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5657fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5658fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5659fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5660fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5661fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5662fcf5ef2aSThomas Huth } else { 5663fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5664fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5665fcf5ef2aSThomas Huth } 5666fcf5ef2aSThomas Huth 5667fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5668fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5669fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5670fcf5ef2aSThomas Huth 5671fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5672fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5673fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5674fcf5ef2aSThomas Huth } 5675fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5676fcf5ef2aSThomas Huth /* Signed */ 5677fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5678fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5679fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5680fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5681fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5682fcf5ef2aSThomas Huth /* Saturate */ 5683fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5684fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5685fcf5ef2aSThomas Huth } 5686fcf5ef2aSThomas Huth } else { 5687fcf5ef2aSThomas Huth /* Unsigned */ 5688fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5689fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5690fcf5ef2aSThomas Huth /* Saturate */ 5691fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5692fcf5ef2aSThomas Huth } 5693fcf5ef2aSThomas Huth } 5694fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5695fcf5ef2aSThomas Huth /* Check overflow */ 5696fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5697fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5698fcf5ef2aSThomas Huth } 5699fcf5ef2aSThomas Huth gen_set_label(l1); 5700fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5701fcf5ef2aSThomas Huth } 5702fcf5ef2aSThomas Huth } else { 5703fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5704fcf5ef2aSThomas Huth } 5705fcf5ef2aSThomas Huth tcg_temp_free(t0); 5706fcf5ef2aSThomas Huth tcg_temp_free(t1); 5707fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5708fcf5ef2aSThomas Huth /* Update Rc0 */ 5709fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5710fcf5ef2aSThomas Huth } 5711fcf5ef2aSThomas Huth } 5712fcf5ef2aSThomas Huth 5713fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5714fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5715fcf5ef2aSThomas Huth { \ 5716fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5717fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5718fcf5ef2aSThomas Huth } 5719fcf5ef2aSThomas Huth 5720fcf5ef2aSThomas Huth /* macchw - macchw. */ 5721fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5722fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5723fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5724fcf5ef2aSThomas Huth /* macchws - macchws. */ 5725fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5726fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5727fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5728fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5729fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5730fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5731fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5732fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5733fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5734fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5735fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5736fcf5ef2aSThomas Huth /* machhw - machhw. */ 5737fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5738fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5739fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5740fcf5ef2aSThomas Huth /* machhws - machhws. */ 5741fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5742fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5743fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5744fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5745fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5746fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5747fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5748fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5749fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5750fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5751fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5752fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5753fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5754fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5755fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5756fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5757fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5758fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5759fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5760fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5761fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5762fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5763fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5764fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5765fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5766fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5767fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5768fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5769fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5770fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5771fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5772fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5773fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5774fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5775fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5776fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5777fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5778fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5779fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5780fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5781fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5782fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5783fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5784fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5785fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5786fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5787fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5788fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5789fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5790fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5791fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5792fcf5ef2aSThomas Huth 5793fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5794fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5795fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5796fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5797fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5798fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5799fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5800fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5801fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5802fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5803fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5804fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5805fcf5ef2aSThomas Huth 5806fcf5ef2aSThomas Huth /* mfdcr */ 5807fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5808fcf5ef2aSThomas Huth { 5809fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58109f0cf041SMatheus Ferst GEN_PRIV(ctx); 5811fcf5ef2aSThomas Huth #else 5812fcf5ef2aSThomas Huth TCGv dcrn; 5813fcf5ef2aSThomas Huth 58149f0cf041SMatheus Ferst CHK_SV(ctx); 5815fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5816fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5817fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5818fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5819fcf5ef2aSThomas Huth } 5820fcf5ef2aSThomas Huth 5821fcf5ef2aSThomas Huth /* mtdcr */ 5822fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5823fcf5ef2aSThomas Huth { 5824fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58259f0cf041SMatheus Ferst GEN_PRIV(ctx); 5826fcf5ef2aSThomas Huth #else 5827fcf5ef2aSThomas Huth TCGv dcrn; 5828fcf5ef2aSThomas Huth 58299f0cf041SMatheus Ferst CHK_SV(ctx); 5830fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5831fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5832fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5833fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5834fcf5ef2aSThomas Huth } 5835fcf5ef2aSThomas Huth 5836fcf5ef2aSThomas Huth /* mfdcrx */ 5837fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5838fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5839fcf5ef2aSThomas Huth { 5840fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58419f0cf041SMatheus Ferst GEN_PRIV(ctx); 5842fcf5ef2aSThomas Huth #else 58439f0cf041SMatheus Ferst CHK_SV(ctx); 5844fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5845fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5846fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5847fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5848fcf5ef2aSThomas Huth } 5849fcf5ef2aSThomas Huth 5850fcf5ef2aSThomas Huth /* mtdcrx */ 5851fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5852fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5853fcf5ef2aSThomas Huth { 5854fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58559f0cf041SMatheus Ferst GEN_PRIV(ctx); 5856fcf5ef2aSThomas Huth #else 58579f0cf041SMatheus Ferst CHK_SV(ctx); 5858fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5859fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5860fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5861fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5862fcf5ef2aSThomas Huth } 5863fcf5ef2aSThomas Huth 5864fcf5ef2aSThomas Huth /* dccci */ 5865fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5866fcf5ef2aSThomas Huth { 58679f0cf041SMatheus Ferst CHK_SV(ctx); 5868fcf5ef2aSThomas Huth /* interpreted as no-op */ 5869fcf5ef2aSThomas Huth } 5870fcf5ef2aSThomas Huth 5871fcf5ef2aSThomas Huth /* dcread */ 5872fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5873fcf5ef2aSThomas Huth { 5874fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58759f0cf041SMatheus Ferst GEN_PRIV(ctx); 5876fcf5ef2aSThomas Huth #else 5877fcf5ef2aSThomas Huth TCGv EA, val; 5878fcf5ef2aSThomas Huth 58799f0cf041SMatheus Ferst CHK_SV(ctx); 5880fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5881fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5882fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5883fcf5ef2aSThomas Huth val = tcg_temp_new(); 5884fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5885fcf5ef2aSThomas Huth tcg_temp_free(val); 5886fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5887fcf5ef2aSThomas Huth tcg_temp_free(EA); 5888fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5889fcf5ef2aSThomas Huth } 5890fcf5ef2aSThomas Huth 5891fcf5ef2aSThomas Huth /* icbt */ 5892fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5893fcf5ef2aSThomas Huth { 5894efe843d8SDavid Gibson /* 5895efe843d8SDavid Gibson * interpreted as no-op 5896efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5897efe843d8SDavid Gibson * does not generate any exception 5898fcf5ef2aSThomas Huth */ 5899fcf5ef2aSThomas Huth } 5900fcf5ef2aSThomas Huth 5901fcf5ef2aSThomas Huth /* iccci */ 5902fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5903fcf5ef2aSThomas Huth { 59049f0cf041SMatheus Ferst CHK_SV(ctx); 5905fcf5ef2aSThomas Huth /* interpreted as no-op */ 5906fcf5ef2aSThomas Huth } 5907fcf5ef2aSThomas Huth 5908fcf5ef2aSThomas Huth /* icread */ 5909fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5910fcf5ef2aSThomas Huth { 59119f0cf041SMatheus Ferst CHK_SV(ctx); 5912fcf5ef2aSThomas Huth /* interpreted as no-op */ 5913fcf5ef2aSThomas Huth } 5914fcf5ef2aSThomas Huth 5915fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5916fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5917fcf5ef2aSThomas Huth { 5918fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59199f0cf041SMatheus Ferst GEN_PRIV(ctx); 5920fcf5ef2aSThomas Huth #else 59219f0cf041SMatheus Ferst CHK_SV(ctx); 5922fcf5ef2aSThomas Huth /* Restore CPU state */ 5923fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 592459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5925fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5926fcf5ef2aSThomas Huth } 5927fcf5ef2aSThomas Huth 5928fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5929fcf5ef2aSThomas Huth { 5930fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59319f0cf041SMatheus Ferst GEN_PRIV(ctx); 5932fcf5ef2aSThomas Huth #else 59339f0cf041SMatheus Ferst CHK_SV(ctx); 5934fcf5ef2aSThomas Huth /* Restore CPU state */ 5935fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 593659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5937fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5938fcf5ef2aSThomas Huth } 5939fcf5ef2aSThomas Huth 5940fcf5ef2aSThomas Huth /* BookE specific */ 5941fcf5ef2aSThomas Huth 5942fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5943fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5944fcf5ef2aSThomas Huth { 5945fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59469f0cf041SMatheus Ferst GEN_PRIV(ctx); 5947fcf5ef2aSThomas Huth #else 59489f0cf041SMatheus Ferst CHK_SV(ctx); 5949fcf5ef2aSThomas Huth /* Restore CPU state */ 5950fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 595159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5952fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5953fcf5ef2aSThomas Huth } 5954fcf5ef2aSThomas Huth 5955fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5956fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5957fcf5ef2aSThomas Huth { 5958fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59599f0cf041SMatheus Ferst GEN_PRIV(ctx); 5960fcf5ef2aSThomas Huth #else 59619f0cf041SMatheus Ferst CHK_SV(ctx); 5962fcf5ef2aSThomas Huth /* Restore CPU state */ 5963fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 596459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5965fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5966fcf5ef2aSThomas Huth } 5967fcf5ef2aSThomas Huth 5968fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5969fcf5ef2aSThomas Huth 5970fcf5ef2aSThomas Huth /* tlbre */ 5971fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5972fcf5ef2aSThomas Huth { 5973fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59749f0cf041SMatheus Ferst GEN_PRIV(ctx); 5975fcf5ef2aSThomas Huth #else 59769f0cf041SMatheus Ferst CHK_SV(ctx); 5977fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5978fcf5ef2aSThomas Huth case 0: 5979fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5980fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5981fcf5ef2aSThomas Huth break; 5982fcf5ef2aSThomas Huth case 1: 5983fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5984fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5985fcf5ef2aSThomas Huth break; 5986fcf5ef2aSThomas Huth default: 5987fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5988fcf5ef2aSThomas Huth break; 5989fcf5ef2aSThomas Huth } 5990fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5991fcf5ef2aSThomas Huth } 5992fcf5ef2aSThomas Huth 5993fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5994fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5995fcf5ef2aSThomas Huth { 5996fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59979f0cf041SMatheus Ferst GEN_PRIV(ctx); 5998fcf5ef2aSThomas Huth #else 5999fcf5ef2aSThomas Huth TCGv t0; 6000fcf5ef2aSThomas Huth 60019f0cf041SMatheus Ferst CHK_SV(ctx); 6002fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6003fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6004fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6005fcf5ef2aSThomas Huth tcg_temp_free(t0); 6006fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6007fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6008fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6009fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6010fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6011fcf5ef2aSThomas Huth gen_set_label(l1); 6012fcf5ef2aSThomas Huth } 6013fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6014fcf5ef2aSThomas Huth } 6015fcf5ef2aSThomas Huth 6016fcf5ef2aSThomas Huth /* tlbwe */ 6017fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6018fcf5ef2aSThomas Huth { 6019fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60209f0cf041SMatheus Ferst GEN_PRIV(ctx); 6021fcf5ef2aSThomas Huth #else 60229f0cf041SMatheus Ferst CHK_SV(ctx); 6023fcf5ef2aSThomas Huth 6024fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6025fcf5ef2aSThomas Huth case 0: 6026fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6027fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6028fcf5ef2aSThomas Huth break; 6029fcf5ef2aSThomas Huth case 1: 6030fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6031fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6032fcf5ef2aSThomas Huth break; 6033fcf5ef2aSThomas Huth default: 6034fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6035fcf5ef2aSThomas Huth break; 6036fcf5ef2aSThomas Huth } 6037fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6038fcf5ef2aSThomas Huth } 6039fcf5ef2aSThomas Huth 6040fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6041fcf5ef2aSThomas Huth 6042fcf5ef2aSThomas Huth /* tlbre */ 6043fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6044fcf5ef2aSThomas Huth { 6045fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60469f0cf041SMatheus Ferst GEN_PRIV(ctx); 6047fcf5ef2aSThomas Huth #else 60489f0cf041SMatheus Ferst CHK_SV(ctx); 6049fcf5ef2aSThomas Huth 6050fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6051fcf5ef2aSThomas Huth case 0: 6052fcf5ef2aSThomas Huth case 1: 6053fcf5ef2aSThomas Huth case 2: 6054fcf5ef2aSThomas Huth { 6055fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6056fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6057fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6058fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6059fcf5ef2aSThomas Huth } 6060fcf5ef2aSThomas Huth break; 6061fcf5ef2aSThomas Huth default: 6062fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6063fcf5ef2aSThomas Huth break; 6064fcf5ef2aSThomas Huth } 6065fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6066fcf5ef2aSThomas Huth } 6067fcf5ef2aSThomas Huth 6068fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6069fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6070fcf5ef2aSThomas Huth { 6071fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60729f0cf041SMatheus Ferst GEN_PRIV(ctx); 6073fcf5ef2aSThomas Huth #else 6074fcf5ef2aSThomas Huth TCGv t0; 6075fcf5ef2aSThomas Huth 60769f0cf041SMatheus Ferst CHK_SV(ctx); 6077fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6078fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6079fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6080fcf5ef2aSThomas Huth tcg_temp_free(t0); 6081fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6082fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6083fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6084fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6085fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6086fcf5ef2aSThomas Huth gen_set_label(l1); 6087fcf5ef2aSThomas Huth } 6088fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6089fcf5ef2aSThomas Huth } 6090fcf5ef2aSThomas Huth 6091fcf5ef2aSThomas Huth /* tlbwe */ 6092fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6093fcf5ef2aSThomas Huth { 6094fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60959f0cf041SMatheus Ferst GEN_PRIV(ctx); 6096fcf5ef2aSThomas Huth #else 60979f0cf041SMatheus Ferst CHK_SV(ctx); 6098fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6099fcf5ef2aSThomas Huth case 0: 6100fcf5ef2aSThomas Huth case 1: 6101fcf5ef2aSThomas Huth case 2: 6102fcf5ef2aSThomas Huth { 6103fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6104fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6105fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6106fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6107fcf5ef2aSThomas Huth } 6108fcf5ef2aSThomas Huth break; 6109fcf5ef2aSThomas Huth default: 6110fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6111fcf5ef2aSThomas Huth break; 6112fcf5ef2aSThomas Huth } 6113fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6114fcf5ef2aSThomas Huth } 6115fcf5ef2aSThomas Huth 6116fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6117fcf5ef2aSThomas Huth 6118fcf5ef2aSThomas Huth /* tlbre */ 6119fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6120fcf5ef2aSThomas Huth { 6121fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61229f0cf041SMatheus Ferst GEN_PRIV(ctx); 6123fcf5ef2aSThomas Huth #else 61249f0cf041SMatheus Ferst CHK_SV(ctx); 6125fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6126fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6127fcf5ef2aSThomas Huth } 6128fcf5ef2aSThomas Huth 6129fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6130fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6131fcf5ef2aSThomas Huth { 6132fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61339f0cf041SMatheus Ferst GEN_PRIV(ctx); 6134fcf5ef2aSThomas Huth #else 6135fcf5ef2aSThomas Huth TCGv t0; 6136fcf5ef2aSThomas Huth 61379f0cf041SMatheus Ferst CHK_SV(ctx); 6138fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6139fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6140fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6141fcf5ef2aSThomas Huth } else { 6142fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6143fcf5ef2aSThomas Huth } 6144fcf5ef2aSThomas Huth 6145fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6146fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6147fcf5ef2aSThomas Huth tcg_temp_free(t0); 6148fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6149fcf5ef2aSThomas Huth } 6150fcf5ef2aSThomas Huth 6151fcf5ef2aSThomas Huth /* tlbwe */ 6152fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6153fcf5ef2aSThomas Huth { 6154fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61559f0cf041SMatheus Ferst GEN_PRIV(ctx); 6156fcf5ef2aSThomas Huth #else 61579f0cf041SMatheus Ferst CHK_SV(ctx); 6158fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6159fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6160fcf5ef2aSThomas Huth } 6161fcf5ef2aSThomas Huth 6162fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6163fcf5ef2aSThomas Huth { 6164fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61659f0cf041SMatheus Ferst GEN_PRIV(ctx); 6166fcf5ef2aSThomas Huth #else 6167fcf5ef2aSThomas Huth TCGv t0; 6168fcf5ef2aSThomas Huth 61699f0cf041SMatheus Ferst CHK_SV(ctx); 6170fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6171fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6172fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6173fcf5ef2aSThomas Huth tcg_temp_free(t0); 6174fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6175fcf5ef2aSThomas Huth } 6176fcf5ef2aSThomas Huth 6177fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6178fcf5ef2aSThomas Huth { 6179fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61809f0cf041SMatheus Ferst GEN_PRIV(ctx); 6181fcf5ef2aSThomas Huth #else 6182fcf5ef2aSThomas Huth TCGv t0; 6183fcf5ef2aSThomas Huth 61849f0cf041SMatheus Ferst CHK_SV(ctx); 6185fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6186fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6187fcf5ef2aSThomas Huth 6188fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 6189fcf5ef2aSThomas Huth case 0: 6190fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6191fcf5ef2aSThomas Huth break; 6192fcf5ef2aSThomas Huth case 1: 6193fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6194fcf5ef2aSThomas Huth break; 6195fcf5ef2aSThomas Huth case 3: 6196fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6197fcf5ef2aSThomas Huth break; 6198fcf5ef2aSThomas Huth default: 6199fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6200fcf5ef2aSThomas Huth break; 6201fcf5ef2aSThomas Huth } 6202fcf5ef2aSThomas Huth 6203fcf5ef2aSThomas Huth tcg_temp_free(t0); 6204fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6205fcf5ef2aSThomas Huth } 6206fcf5ef2aSThomas Huth 6207fcf5ef2aSThomas Huth /* wrtee */ 6208fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6209fcf5ef2aSThomas Huth { 6210fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 62119f0cf041SMatheus Ferst GEN_PRIV(ctx); 6212fcf5ef2aSThomas Huth #else 6213fcf5ef2aSThomas Huth TCGv t0; 6214fcf5ef2aSThomas Huth 62159f0cf041SMatheus Ferst CHK_SV(ctx); 6216fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6217fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6218fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6219fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 62202fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6221fcf5ef2aSThomas Huth tcg_temp_free(t0); 6222efe843d8SDavid Gibson /* 6223efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6224efe843d8SDavid Gibson * just set msr_ee to 1 6225fcf5ef2aSThomas Huth */ 6226d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6227fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6228fcf5ef2aSThomas Huth } 6229fcf5ef2aSThomas Huth 6230fcf5ef2aSThomas Huth /* wrteei */ 6231fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6232fcf5ef2aSThomas Huth { 6233fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 62349f0cf041SMatheus Ferst GEN_PRIV(ctx); 6235fcf5ef2aSThomas Huth #else 62369f0cf041SMatheus Ferst CHK_SV(ctx); 6237fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6238fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 62392fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6240fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6241d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6242fcf5ef2aSThomas Huth } else { 6243fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6244fcf5ef2aSThomas Huth } 6245fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6246fcf5ef2aSThomas Huth } 6247fcf5ef2aSThomas Huth 6248fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6249fcf5ef2aSThomas Huth 6250fcf5ef2aSThomas Huth /* dlmzb */ 6251fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6252fcf5ef2aSThomas Huth { 6253fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6254fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6255fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6256fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6257fcf5ef2aSThomas Huth } 6258fcf5ef2aSThomas Huth 6259fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6260fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6261fcf5ef2aSThomas Huth { 6262fcf5ef2aSThomas Huth /* interpreted as no-op */ 6263fcf5ef2aSThomas Huth } 6264fcf5ef2aSThomas Huth 6265fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6266fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6267fcf5ef2aSThomas Huth { 626827a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 626927a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 627027a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 627127a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 627227a3ea7eSBALATON Zoltan } 627327a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6274fcf5ef2aSThomas Huth } 6275fcf5ef2aSThomas Huth 6276fcf5ef2aSThomas Huth /* icbt */ 6277fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6278fcf5ef2aSThomas Huth { 6279efe843d8SDavid Gibson /* 6280efe843d8SDavid Gibson * interpreted as no-op 6281efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6282efe843d8SDavid Gibson * does not generate any exception 6283fcf5ef2aSThomas Huth */ 6284fcf5ef2aSThomas Huth } 6285fcf5ef2aSThomas Huth 6286fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6287fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6288fcf5ef2aSThomas Huth { 6289fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6290fcf5ef2aSThomas Huth 6291fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6292fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6293fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6294fcf5ef2aSThomas Huth } 6295fcf5ef2aSThomas Huth 6296fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6297fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6298fcf5ef2aSThomas Huth { 6299fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6300fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6301fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6302fcf5ef2aSThomas Huth 6303fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6304fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6305fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6306fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6307fcf5ef2aSThomas Huth } else { 6308fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6309fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6310fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6311fcf5ef2aSThomas Huth } 6312fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6313fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6314fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6315fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6316fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6317fcf5ef2aSThomas Huth } 6318fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6319fcf5ef2aSThomas Huth 6320fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6321fcf5ef2aSThomas Huth { 6322fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6323fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6324fcf5ef2aSThomas Huth return; 6325fcf5ef2aSThomas Huth } 6326fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6327fcf5ef2aSThomas Huth } 6328fcf5ef2aSThomas Huth 6329fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6330fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6331fcf5ef2aSThomas Huth { \ 6332fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6333fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6334fcf5ef2aSThomas Huth return; \ 6335fcf5ef2aSThomas Huth } \ 6336efe843d8SDavid Gibson /* \ 6337efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6338fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6339fcf5ef2aSThomas Huth * \ 6340fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6341fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6342fcf5ef2aSThomas Huth */ \ 6343fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6344fcf5ef2aSThomas Huth } 6345fcf5ef2aSThomas Huth 6346fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6347fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6348fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6349fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6350fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6351fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6352fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6353efe843d8SDavid Gibson 6354b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6355b8b4576eSSuraj Jitindar Singh { 6356efe843d8SDavid Gibson /* Do Nothing */ 6357b8b4576eSSuraj Jitindar Singh } 6358fcf5ef2aSThomas Huth 635980b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 636080b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 636180b8c1eeSNikunj A Dadhania { \ 6362efe843d8SDavid Gibson /* \ 6363efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6364efe843d8SDavid Gibson * implementation of the copy paste facility \ 636580b8c1eeSNikunj A Dadhania */ \ 636680b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 636780b8c1eeSNikunj A Dadhania } 636880b8c1eeSNikunj A Dadhania 636980b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 637080b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 637180b8c1eeSNikunj A Dadhania 6372fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6373fcf5ef2aSThomas Huth { 6374fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6375fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6376fcf5ef2aSThomas Huth return; 6377fcf5ef2aSThomas Huth } 6378efe843d8SDavid Gibson /* 6379efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6380efe843d8SDavid Gibson * simple: 6381fcf5ef2aSThomas Huth * 6382fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6383fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6384fcf5ef2aSThomas Huth */ 6385fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6386fcf5ef2aSThomas Huth } 6387fcf5ef2aSThomas Huth 6388fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6389fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6390fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6391fcf5ef2aSThomas Huth { \ 63929f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6393fcf5ef2aSThomas Huth } 6394fcf5ef2aSThomas Huth 6395fcf5ef2aSThomas Huth #else 6396fcf5ef2aSThomas Huth 6397fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6398fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6399fcf5ef2aSThomas Huth { \ 64009f0cf041SMatheus Ferst CHK_SV(ctx); \ 6401fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6402fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6403fcf5ef2aSThomas Huth return; \ 6404fcf5ef2aSThomas Huth } \ 6405efe843d8SDavid Gibson /* \ 6406efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6407fcf5ef2aSThomas Huth * simple: \ 6408fcf5ef2aSThomas Huth * \ 6409fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6410fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6411fcf5ef2aSThomas Huth */ \ 6412fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6413fcf5ef2aSThomas Huth } 6414fcf5ef2aSThomas Huth 6415fcf5ef2aSThomas Huth #endif 6416fcf5ef2aSThomas Huth 6417fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6418fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6419fcf5ef2aSThomas Huth 64201a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 64211a404c91SMark Cave-Ayland { 6422e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 64231a404c91SMark Cave-Ayland } 64241a404c91SMark Cave-Ayland 64251a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 64261a404c91SMark Cave-Ayland { 6427e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 64284b65b6e7SVíctor Colombo /* 64294b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 64304b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 64314b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 64324b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 64334b65b6e7SVíctor Colombo * to be 0. 64344b65b6e7SVíctor Colombo */ 64354b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 64361a404c91SMark Cave-Ayland } 64371a404c91SMark Cave-Ayland 6438c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6439c4a18dbfSMark Cave-Ayland { 644037da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6441c4a18dbfSMark Cave-Ayland } 6442c4a18dbfSMark Cave-Ayland 6443c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6444c4a18dbfSMark Cave-Ayland { 644537da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6446c4a18dbfSMark Cave-Ayland } 6447c4a18dbfSMark Cave-Ayland 6448c9826ae9SRichard Henderson /* 6449f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6450f2aabda8SRichard Henderson */ 6451d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6452d39b2cc7SLuis Pires { 6453d39b2cc7SLuis Pires return x * 2; 6454d39b2cc7SLuis Pires } 6455d39b2cc7SLuis Pires 6456f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6457f2aabda8SRichard Henderson { 6458f2aabda8SRichard Henderson return x * 4; 6459f2aabda8SRichard Henderson } 6460f2aabda8SRichard Henderson 6461e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6462e10271e1SMatheus Ferst { 6463e10271e1SMatheus Ferst return x * 16; 6464e10271e1SMatheus Ferst } 6465e10271e1SMatheus Ferst 6466670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6467670f1da3SVíctor Colombo { 6468670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6469670f1da3SVíctor Colombo } 6470670f1da3SVíctor Colombo 6471f2aabda8SRichard Henderson /* 6472c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6473c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6474c9826ae9SRichard Henderson * proper variable. 6475c9826ae9SRichard Henderson */ 6476c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6477c9826ae9SRichard Henderson do { \ 6478c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6479c9826ae9SRichard Henderson return false; \ 6480c9826ae9SRichard Henderson } \ 6481c9826ae9SRichard Henderson } while (0) 6482c9826ae9SRichard Henderson 6483c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6484c9826ae9SRichard Henderson do { \ 6485c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6486c9826ae9SRichard Henderson return false; \ 6487c9826ae9SRichard Henderson } \ 6488c9826ae9SRichard Henderson } while (0) 6489c9826ae9SRichard Henderson 6490c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6491c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6492c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6493c9826ae9SRichard Henderson #else 6494c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6495c9826ae9SRichard Henderson #endif 6496c9826ae9SRichard Henderson 6497e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6498e2205a46SBruno Larsen do { \ 6499e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6500e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6501e2205a46SBruno Larsen return true; \ 6502e2205a46SBruno Larsen } \ 6503e2205a46SBruno Larsen } while (0) 6504e2205a46SBruno Larsen 65058226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 65068226cb2dSBruno Larsen (billionai) do { \ 65078226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 65088226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 65098226cb2dSBruno Larsen (billionai) return true; \ 65108226cb2dSBruno Larsen (billionai) } \ 65118226cb2dSBruno Larsen (billionai) } while (0) 65128226cb2dSBruno Larsen (billionai) 651386057426SFernando Valle #define REQUIRE_FPU(ctx) \ 651486057426SFernando Valle do { \ 651586057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 651686057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 651786057426SFernando Valle return true; \ 651886057426SFernando Valle } \ 651986057426SFernando Valle } while (0) 652086057426SFernando Valle 6521fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6522fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6523fc34e81aSMatheus Ferst do { \ 6524fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6525fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6526fc34e81aSMatheus Ferst return true; \ 6527fc34e81aSMatheus Ferst } \ 6528fc34e81aSMatheus Ferst } while (0) 6529fc34e81aSMatheus Ferst 6530fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6531fc34e81aSMatheus Ferst do { \ 6532e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6533fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6534fc34e81aSMatheus Ferst return true; \ 6535fc34e81aSMatheus Ferst } \ 6536fc34e81aSMatheus Ferst } while (0) 6537fc34e81aSMatheus Ferst #else 6538fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6539fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6540fc34e81aSMatheus Ferst #endif 6541fc34e81aSMatheus Ferst 6542f2aabda8SRichard Henderson /* 6543f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6544f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6545f2aabda8SRichard Henderson */ 6546f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6547f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6548f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 654919f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 655019f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 655119f0862dSLuis Pires { \ 655219f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 655319f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 655419f0862dSLuis Pires } 655519f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 655619f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 655719f0862dSLuis Pires { \ 655819f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 655919f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 656019f0862dSLuis Pires } 6561f2aabda8SRichard Henderson 6562f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6563f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6564f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 656519f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 656619f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 656719f0862dSLuis Pires { \ 656819f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 656919f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 657019f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 657119f0862dSLuis Pires } 6572f2aabda8SRichard Henderson 6573f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6574f2aabda8SRichard Henderson 6575f2aabda8SRichard Henderson 657699082815SRichard Henderson #include "decode-insn32.c.inc" 657799082815SRichard Henderson #include "decode-insn64.c.inc" 6578565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6579565cb109SGustavo Romero 6580725b2d4dSFernando Eckhardt Valle /* 6581725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6582725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6583725b2d4dSFernando Eckhardt Valle */ 6584725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6585725b2d4dSFernando Eckhardt Valle { 6586725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6587725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6588725b2d4dSFernando Eckhardt Valle d->si = a->si; 6589725b2d4dSFernando Eckhardt Valle if (a->r) { 6590725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6591725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6592725b2d4dSFernando Eckhardt Valle return false; 6593725b2d4dSFernando Eckhardt Valle } 6594725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6595725b2d4dSFernando Eckhardt Valle } 6596725b2d4dSFernando Eckhardt Valle return true; 6597725b2d4dSFernando Eckhardt Valle } 6598725b2d4dSFernando Eckhardt Valle 659999082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 660099082815SRichard Henderson 6601139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6602fcf5ef2aSThomas Huth 6603139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6604fcf5ef2aSThomas Huth 6605139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6606fcf5ef2aSThomas Huth 6607139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6608fcf5ef2aSThomas Huth 6609139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6610fcf5ef2aSThomas Huth 66111f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 66121f26c751SDaniel Henrique Barboza 661398f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 661498f43417SMatheus Ferst 6615016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6616016b6e1dSLeandro Lupori 661720e2d04eSLeandro Lupori /* Handles lfdp */ 66185cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 66195cb091a4SNikunj A Dadhania { 662020e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 66215cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 66225cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 66235cb091a4SNikunj A Dadhania } 66245cb091a4SNikunj A Dadhania } 66255cb091a4SNikunj A Dadhania return gen_invalid(ctx); 66265cb091a4SNikunj A Dadhania } 66275cb091a4SNikunj A Dadhania 662820e2d04eSLeandro Lupori /* Handles stfdp */ 6629e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6630e3001664SNikunj A Dadhania { 663120e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 663220e2d04eSLeandro Lupori /* stfdp */ 6633e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6634e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6635e3001664SNikunj A Dadhania } 6636e3001664SNikunj A Dadhania } 6637e3001664SNikunj A Dadhania return gen_invalid(ctx); 6638e3001664SNikunj A Dadhania } 6639e3001664SNikunj A Dadhania 66409d69cfa2SLijun Pan #if defined(TARGET_PPC64) 66419d69cfa2SLijun Pan /* brd */ 66429d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 66439d69cfa2SLijun Pan { 66449d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 66459d69cfa2SLijun Pan } 66469d69cfa2SLijun Pan 66479d69cfa2SLijun Pan /* brw */ 66489d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 66499d69cfa2SLijun Pan { 66509d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 66519d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 66529d69cfa2SLijun Pan 66539d69cfa2SLijun Pan } 66549d69cfa2SLijun Pan 66559d69cfa2SLijun Pan /* brh */ 66569d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 66579d69cfa2SLijun Pan { 6658491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 66599d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 66609d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 66619d69cfa2SLijun Pan 66629d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6663491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6664491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 66659d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 66669d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 66679d69cfa2SLijun Pan 66689d69cfa2SLijun Pan tcg_temp_free_i64(t1); 66699d69cfa2SLijun Pan tcg_temp_free_i64(t2); 66709d69cfa2SLijun Pan } 66719d69cfa2SLijun Pan #endif 66729d69cfa2SLijun Pan 6673fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 66749d69cfa2SLijun Pan #if defined(TARGET_PPC64) 66759d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 66769d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 66779d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 66789d69cfa2SLijun Pan #endif 6679fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6680fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6681fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6682fcf5ef2aSThomas Huth #endif 6683fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6684fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6685fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6686fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6687fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6688fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6689fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6690fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6691fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6692fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6693fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6694fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6695fcf5ef2aSThomas Huth #endif 6696fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6697fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6698fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6699fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6700fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6701fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6702fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 670380b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6704b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 670580b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6706fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6707fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6708fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6709fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6710fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6711fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6712fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6713fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6714fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6715fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6716fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6717fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6718fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6719fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6720fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6721fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6722fcf5ef2aSThomas Huth #endif 6723fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6724fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6725fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6726fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6727fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6728fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6729fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6730fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6731fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6732fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6733fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6734fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6735fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6736fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6737fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6738fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6739fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6740fcf5ef2aSThomas Huth #endif 67415cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 67425cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 674372b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6744e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6745fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6746fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6747fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6748fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6749fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6750fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6751c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6752fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6753fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6754fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6755fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6756a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6757a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6758fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6759fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6760fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6761fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6762a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6763a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6764fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6765fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6766fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6767fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6768fcf5ef2aSThomas Huth #endif 6769fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 67700c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 67710c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 67720c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6773fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6774fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6775fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6776fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6777fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6778fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6779fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6780fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6781fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 67823c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 67833c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 67843c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 67853c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 67863c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 67873c89b8d6SNicholas Piggin #endif 6788cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6789fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6790fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6791fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6792fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6793fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6794fcf5ef2aSThomas Huth #endif 67953c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 67963c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 67973c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6798fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6799fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6800fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6801fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6802fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6803fcf5ef2aSThomas Huth #endif 6804fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6805fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6806fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6807fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6808fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6809fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6810fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6811fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6812fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6813b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6814fcf5ef2aSThomas Huth #endif 6815fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6816fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6817fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 681850728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6819fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6820fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 682150728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6822fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 682350728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6824fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 682550728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6826fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6827fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 682850728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6829fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 683099d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6831fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6832fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 683350728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6834fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6835fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6836fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6837fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6838fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6839fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6840fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6841fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6842fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6843fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6844fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6845fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6846fcf5ef2aSThomas Huth #endif 6847fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6848efe843d8SDavid Gibson /* 6849efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6850efe843d8SDavid Gibson * different ISA versions 6851efe843d8SDavid Gibson */ 6852fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6853fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6854fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6855fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6856fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6857fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6858fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6859fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6860fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6861fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6862fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6863fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6864fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6865fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6866fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6867fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6868fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6869fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6870fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6871fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6872fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6873fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6874fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6875fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6876fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6877fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6878fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6879fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6880fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6881fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6882fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6883fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6884fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6885fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6886fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6887fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6888fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6889fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6890fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6891fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6892fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 689327a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6894fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6895fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 68960c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 68970c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6898fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6899fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6900fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6901fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6902fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6903fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6904fcf5ef2aSThomas Huth PPC2_ISA300), 6905fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6906fcf5ef2aSThomas Huth #endif 6907fcf5ef2aSThomas Huth 6908fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6909fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6910fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6911fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6912fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6913fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6914fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6915fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6916fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6917fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6918fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6919fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6920fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6921fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6922fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 69234c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6924fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6925fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6926fcf5ef2aSThomas Huth 6927fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6928fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6929fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6930fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6931fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6932fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6933fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6934fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6935fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6936fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6937fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6938fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6939fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6940fcf5ef2aSThomas Huth 6941fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6942fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6943fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6944fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6945fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6946fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6947fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6948fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6949fcf5ef2aSThomas Huth 6950fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6951fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6952fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6953fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6954fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6955fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6956fcf5ef2aSThomas Huth 6957fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6958fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6959fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6960fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6961fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6962fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6963fcf5ef2aSThomas Huth #endif 6964fcf5ef2aSThomas Huth 6965fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6966fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6967fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6968fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6969fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6970fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6971fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6972fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6973fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6974fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6975fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6976fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6977fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6978fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6979fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6980fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6981fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6982fcf5ef2aSThomas Huth 6983fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6984fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6985fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6986fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6987fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6988fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6989fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6990fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6991fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6992fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6993fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6994fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6995fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6996fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6997fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6998fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6999fcf5ef2aSThomas Huth #endif 7000fcf5ef2aSThomas Huth 7001fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7002fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7003fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7004fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7005fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7006fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7007fcf5ef2aSThomas Huth PPC_64B) 7008fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7009fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7010fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7011fcf5ef2aSThomas Huth PPC_64B), \ 7012fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7013fcf5ef2aSThomas Huth PPC_64B), \ 7014fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7015fcf5ef2aSThomas Huth PPC_64B) 7016fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7017fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7018fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7019fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7020fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7021fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7022fcf5ef2aSThomas Huth #endif 7023fcf5ef2aSThomas Huth 7024fcf5ef2aSThomas Huth #undef GEN_LDX_E 7025fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7026fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7027fcf5ef2aSThomas Huth 7028fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7029fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7030fcf5ef2aSThomas Huth 7031fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7032fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7033fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7034fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7035fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7036fcf5ef2aSThomas Huth #endif 7037fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7038fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7039fcf5ef2aSThomas Huth 704050728199SRoman Kapl /* External PID based load */ 704150728199SRoman Kapl #undef GEN_LDEPX 704250728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 704350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 704450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 704550728199SRoman Kapl 704650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 704750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 704850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 704950728199SRoman Kapl #if defined(TARGET_PPC64) 7050fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 705150728199SRoman Kapl #endif 705250728199SRoman Kapl 7053fcf5ef2aSThomas Huth #undef GEN_STX_E 7054fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 70550123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7056fcf5ef2aSThomas Huth 7057fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7058fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7059fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7060fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7061fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7062fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7063fcf5ef2aSThomas Huth #endif 7064fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7065fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7066fcf5ef2aSThomas Huth 706750728199SRoman Kapl #undef GEN_STEPX 706850728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 706950728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 707050728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 707150728199SRoman Kapl 707250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 707350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 707450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 707550728199SRoman Kapl #if defined(TARGET_PPC64) 7076fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 707750728199SRoman Kapl #endif 707850728199SRoman Kapl 7079fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7080fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7081fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7082fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7083fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7084fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7085fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7086fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7087fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7088fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7089fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7090fcf5ef2aSThomas Huth 7091fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7092fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7093fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7094fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7096fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7104fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7106fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7108fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7110fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7112fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7114fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7116fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7118fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7120fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7122fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7124fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7126fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7128fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7130fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7132fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7134fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7136fcf5ef2aSThomas Huth 7137fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7138fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7139fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7140fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7141fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7142fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7143fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7144fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7145fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7146fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7147fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7148fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7149fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7150fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7151fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7152fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7153fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7154fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7155fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7156fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7157fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7158fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7159fcf5ef2aSThomas Huth 7160139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 7161fcf5ef2aSThomas Huth 7162139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 7163fcf5ef2aSThomas Huth 7164139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 7165fcf5ef2aSThomas Huth 7166139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 7167fcf5ef2aSThomas Huth }; 7168fcf5ef2aSThomas Huth 71697468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71707468e2c8SBruno Larsen (billionai) /* Opcode types */ 71717468e2c8SBruno Larsen (billionai) enum { 71727468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 71737468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 71747468e2c8SBruno Larsen (billionai) }; 71757468e2c8SBruno Larsen (billionai) 71767468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 71777468e2c8SBruno Larsen (billionai) 71787468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 71797468e2c8SBruno Larsen (billionai) { 71807468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 71817468e2c8SBruno Larsen (billionai) } 71827468e2c8SBruno Larsen (billionai) 71837468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 71847468e2c8SBruno Larsen (billionai) { 71857468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 71867468e2c8SBruno Larsen (billionai) } 71877468e2c8SBruno Larsen (billionai) 71887468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 71897468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 71907468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 71917468e2c8SBruno Larsen (billionai) { 71927468e2c8SBruno Larsen (billionai) int i; 71937468e2c8SBruno Larsen (billionai) 71947468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 71957468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71967468e2c8SBruno Larsen (billionai) } 71977468e2c8SBruno Larsen (billionai) } 71987468e2c8SBruno Larsen (billionai) 71997468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 72007468e2c8SBruno Larsen (billionai) { 72017468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 72027468e2c8SBruno Larsen (billionai) 72037468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 72047468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 72057468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 72067468e2c8SBruno Larsen (billionai) 72077468e2c8SBruno Larsen (billionai) return 0; 72087468e2c8SBruno Larsen (billionai) } 72097468e2c8SBruno Larsen (billionai) 72107468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 72117468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72127468e2c8SBruno Larsen (billionai) { 72137468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 72147468e2c8SBruno Larsen (billionai) return -1; 72157468e2c8SBruno Larsen (billionai) } 72167468e2c8SBruno Larsen (billionai) table[idx] = handler; 72177468e2c8SBruno Larsen (billionai) 72187468e2c8SBruno Larsen (billionai) return 0; 72197468e2c8SBruno Larsen (billionai) } 72207468e2c8SBruno Larsen (billionai) 72217468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 72227468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 72237468e2c8SBruno Larsen (billionai) { 72247468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 72257468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 72267468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 72277468e2c8SBruno Larsen (billionai) return -1; 72287468e2c8SBruno Larsen (billionai) } 72297468e2c8SBruno Larsen (billionai) 72307468e2c8SBruno Larsen (billionai) return 0; 72317468e2c8SBruno Larsen (billionai) } 72327468e2c8SBruno Larsen (billionai) 72337468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 72347468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72357468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72367468e2c8SBruno Larsen (billionai) { 72377468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 72387468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 72397468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 72407468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 72417468e2c8SBruno Larsen (billionai) return -1; 72427468e2c8SBruno Larsen (billionai) } 72437468e2c8SBruno Larsen (billionai) } else { 72447468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 72457468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 72467468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 72477468e2c8SBruno Larsen (billionai) return -1; 72487468e2c8SBruno Larsen (billionai) } 72497468e2c8SBruno Larsen (billionai) } 72507468e2c8SBruno Larsen (billionai) if (handler != NULL && 72517468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 72527468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 72537468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 72547468e2c8SBruno Larsen (billionai) return -1; 72557468e2c8SBruno Larsen (billionai) } 72567468e2c8SBruno Larsen (billionai) 72577468e2c8SBruno Larsen (billionai) return 0; 72587468e2c8SBruno Larsen (billionai) } 72597468e2c8SBruno Larsen (billionai) 72607468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 72617468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72627468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72637468e2c8SBruno Larsen (billionai) { 72647468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 72657468e2c8SBruno Larsen (billionai) } 72667468e2c8SBruno Larsen (billionai) 72677468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 72687468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72697468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 72707468e2c8SBruno Larsen (billionai) { 72717468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 72727468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 72737468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 72747468e2c8SBruno Larsen (billionai) return -1; 72757468e2c8SBruno Larsen (billionai) } 72767468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 72777468e2c8SBruno Larsen (billionai) handler) < 0) { 72787468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 72797468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 72807468e2c8SBruno Larsen (billionai) return -1; 72817468e2c8SBruno Larsen (billionai) } 72827468e2c8SBruno Larsen (billionai) 72837468e2c8SBruno Larsen (billionai) return 0; 72847468e2c8SBruno Larsen (billionai) } 72857468e2c8SBruno Larsen (billionai) 72867468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 72877468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72887468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 72897468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72907468e2c8SBruno Larsen (billionai) { 72917468e2c8SBruno Larsen (billionai) opc_handler_t **table; 72927468e2c8SBruno Larsen (billionai) 72937468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 72947468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 72957468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 72967468e2c8SBruno Larsen (billionai) return -1; 72977468e2c8SBruno Larsen (billionai) } 72987468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 72997468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 73007468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 73017468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 73027468e2c8SBruno Larsen (billionai) return -1; 73037468e2c8SBruno Larsen (billionai) } 73047468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 73057468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 73067468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 73077468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 73087468e2c8SBruno Larsen (billionai) return -1; 73097468e2c8SBruno Larsen (billionai) } 73107468e2c8SBruno Larsen (billionai) return 0; 73117468e2c8SBruno Larsen (billionai) } 73127468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 73137468e2c8SBruno Larsen (billionai) { 73147468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 73157468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 73167468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 73177468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 73187468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 73197468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 73207468e2c8SBruno Larsen (billionai) return -1; 73217468e2c8SBruno Larsen (billionai) } 73227468e2c8SBruno Larsen (billionai) } else { 73237468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 73247468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 73257468e2c8SBruno Larsen (billionai) return -1; 73267468e2c8SBruno Larsen (billionai) } 73277468e2c8SBruno Larsen (billionai) } 73287468e2c8SBruno Larsen (billionai) } else { 73297468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 73307468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 73317468e2c8SBruno Larsen (billionai) return -1; 73327468e2c8SBruno Larsen (billionai) } 73337468e2c8SBruno Larsen (billionai) } 73347468e2c8SBruno Larsen (billionai) } else { 73357468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 73367468e2c8SBruno Larsen (billionai) return -1; 73377468e2c8SBruno Larsen (billionai) } 73387468e2c8SBruno Larsen (billionai) } 73397468e2c8SBruno Larsen (billionai) 73407468e2c8SBruno Larsen (billionai) return 0; 73417468e2c8SBruno Larsen (billionai) } 73427468e2c8SBruno Larsen (billionai) 73437468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 73447468e2c8SBruno Larsen (billionai) { 73457468e2c8SBruno Larsen (billionai) int i, count, tmp; 73467468e2c8SBruno Larsen (billionai) 73477468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 73487468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 73497468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 73507468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 73517468e2c8SBruno Larsen (billionai) } 73527468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 73537468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 73547468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 73557468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 73567468e2c8SBruno Larsen (billionai) if (tmp == 0) { 73577468e2c8SBruno Larsen (billionai) free(table[i]); 73587468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 73597468e2c8SBruno Larsen (billionai) } else { 73607468e2c8SBruno Larsen (billionai) count++; 73617468e2c8SBruno Larsen (billionai) } 73627468e2c8SBruno Larsen (billionai) } else { 73637468e2c8SBruno Larsen (billionai) count++; 73647468e2c8SBruno Larsen (billionai) } 73657468e2c8SBruno Larsen (billionai) } 73667468e2c8SBruno Larsen (billionai) } 73677468e2c8SBruno Larsen (billionai) 73687468e2c8SBruno Larsen (billionai) return count; 73697468e2c8SBruno Larsen (billionai) } 73707468e2c8SBruno Larsen (billionai) 73717468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 73727468e2c8SBruno Larsen (billionai) { 73737468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 73747468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 73757468e2c8SBruno Larsen (billionai) } 73767468e2c8SBruno Larsen (billionai) } 73777468e2c8SBruno Larsen (billionai) 73787468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 73797468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 73807468e2c8SBruno Larsen (billionai) { 73817468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 73827468e2c8SBruno Larsen (billionai) opcode_t *opc; 73837468e2c8SBruno Larsen (billionai) 73847468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 73857468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 73867468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 73877468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 73887468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 73897468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 73907468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 73917468e2c8SBruno Larsen (billionai) opc->opc3); 73927468e2c8SBruno Larsen (billionai) return; 73937468e2c8SBruno Larsen (billionai) } 73947468e2c8SBruno Larsen (billionai) } 73957468e2c8SBruno Larsen (billionai) } 73967468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 73977468e2c8SBruno Larsen (billionai) fflush(stdout); 73987468e2c8SBruno Larsen (billionai) fflush(stderr); 73997468e2c8SBruno Larsen (billionai) } 74007468e2c8SBruno Larsen (billionai) 74017468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 74027468e2c8SBruno Larsen (billionai) { 74037468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 74047468e2c8SBruno Larsen (billionai) int i, j, k; 74057468e2c8SBruno Larsen (billionai) 74067468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 74077468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 74087468e2c8SBruno Larsen (billionai) continue; 74097468e2c8SBruno Larsen (billionai) } 74107468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 74117468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 74127468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 74137468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 74147468e2c8SBruno Larsen (billionai) continue; 74157468e2c8SBruno Larsen (billionai) } 74167468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 74177468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 74187468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 74197468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 74207468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 74217468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 74227468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74237468e2c8SBruno Larsen (billionai) } 74247468e2c8SBruno Larsen (billionai) } 74257468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 74267468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74277468e2c8SBruno Larsen (billionai) } 74287468e2c8SBruno Larsen (billionai) } 74297468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 74307468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74317468e2c8SBruno Larsen (billionai) } 74327468e2c8SBruno Larsen (billionai) } 74337468e2c8SBruno Larsen (billionai) } 74347468e2c8SBruno Larsen (billionai) 74357468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 74367468e2c8SBruno Larsen (billionai) { 74377468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 74387468e2c8SBruno Larsen (billionai) 74397468e2c8SBruno Larsen (billionai) /* 74407468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 74417468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 74427468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 74437468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 74447468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 74457468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 74467468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 74477468e2c8SBruno Larsen (billionai) */ 74487468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 74497468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 74507468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 74517468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 74527468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 74537468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 74547468e2c8SBruno Larsen (billionai) } 74557468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 74567468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 74577468e2c8SBruno Larsen (billionai) return 0; 74587468e2c8SBruno Larsen (billionai) } 74597468e2c8SBruno Larsen (billionai) 7460624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7461624cb07fSRichard Henderson { 7462624cb07fSRichard Henderson opc_handler_t **table, *handler; 7463624cb07fSRichard Henderson uint32_t inval; 7464624cb07fSRichard Henderson 7465624cb07fSRichard Henderson ctx->opcode = insn; 7466624cb07fSRichard Henderson 7467624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7468624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7469624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7470624cb07fSRichard Henderson 7471624cb07fSRichard Henderson table = cpu->opcodes; 7472624cb07fSRichard Henderson handler = table[opc1(insn)]; 7473624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7474624cb07fSRichard Henderson table = ind_table(handler); 7475624cb07fSRichard Henderson handler = table[opc2(insn)]; 7476624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7477624cb07fSRichard Henderson table = ind_table(handler); 7478624cb07fSRichard Henderson handler = table[opc3(insn)]; 7479624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7480624cb07fSRichard Henderson table = ind_table(handler); 7481624cb07fSRichard Henderson handler = table[opc4(insn)]; 7482624cb07fSRichard Henderson } 7483624cb07fSRichard Henderson } 7484624cb07fSRichard Henderson } 7485624cb07fSRichard Henderson 7486624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7487624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7488624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7489624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7490624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7491624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7492624cb07fSRichard Henderson insn, ctx->cia); 7493624cb07fSRichard Henderson return false; 7494624cb07fSRichard Henderson } 7495624cb07fSRichard Henderson 7496624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7497624cb07fSRichard Henderson && Rc(insn))) { 7498624cb07fSRichard Henderson inval = handler->inval2; 7499624cb07fSRichard Henderson } else { 7500624cb07fSRichard Henderson inval = handler->inval1; 7501624cb07fSRichard Henderson } 7502624cb07fSRichard Henderson 7503624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7504624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7505624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7506624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7507624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7508624cb07fSRichard Henderson insn, ctx->cia); 7509624cb07fSRichard Henderson return false; 7510624cb07fSRichard Henderson } 7511624cb07fSRichard Henderson 7512624cb07fSRichard Henderson handler->handler(ctx); 7513624cb07fSRichard Henderson return true; 7514624cb07fSRichard Henderson } 7515624cb07fSRichard Henderson 7516b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7517fcf5ef2aSThomas Huth { 7518b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 75199c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 75202df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7521fcf5ef2aSThomas Huth 7522b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 75232df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7524d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 75252df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 75262df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7527b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7528b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7529b0c2d521SEmilio G. Cota ctx->access_type = -1; 7530d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 75312df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7532b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 75330e3bf489SRoman Kapl ctx->flags = env->flags; 7534fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 75352df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7536b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7537fcf5ef2aSThomas Huth #endif 7538e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7539d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7540fcf5ef2aSThomas Huth 75412df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 75422df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 75432df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 75442df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 75452df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7546f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 75471db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7548f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7549f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 75508b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 75518b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 755246d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 75532df4fe7aSRichard Henderson 7554b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 75552df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 75562df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 75579498d103SRichard Henderson ctx->base.max_insns = 1; 7558efe843d8SDavid Gibson } 75592df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7560b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7561efe843d8SDavid Gibson } 756213b45575SRichard Henderson } 7563fcf5ef2aSThomas Huth 7564b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7565b0c2d521SEmilio G. Cota { 7566b0c2d521SEmilio G. Cota } 7567fcf5ef2aSThomas Huth 7568b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7569b0c2d521SEmilio G. Cota { 7570b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7571b0c2d521SEmilio G. Cota } 7572b0c2d521SEmilio G. Cota 757399082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 757499082815SRichard Henderson { 757599082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 757699082815SRichard Henderson return opc1(insn) == 1; 757799082815SRichard Henderson } 757899082815SRichard Henderson 7579b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7580b0c2d521SEmilio G. Cota { 7581b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 758228876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7583b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 758499082815SRichard Henderson target_ulong pc; 7585624cb07fSRichard Henderson uint32_t insn; 7586624cb07fSRichard Henderson bool ok; 7587b0c2d521SEmilio G. Cota 7588fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7589fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7590b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7591b0c2d521SEmilio G. Cota 759299082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 75934e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 759499082815SRichard Henderson ctx->base.pc_next = pc += 4; 7595fcf5ef2aSThomas Huth 759699082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 759799082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 759899082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 759999082815SRichard Henderson } else if ((pc & 63) == 0) { 760099082815SRichard Henderson /* 760199082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 760299082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 760399082815SRichard Henderson * 64-byte address boundary (system alignment error). 760499082815SRichard Henderson */ 760599082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 760699082815SRichard Henderson ok = true; 760799082815SRichard Henderson } else { 76084e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 76094e116893SIlya Leoshkevich need_byteswap(ctx)); 761099082815SRichard Henderson ctx->base.pc_next = pc += 4; 761199082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 761299082815SRichard Henderson } 7613624cb07fSRichard Henderson if (!ok) { 7614624cb07fSRichard Henderson gen_invalid(ctx); 7615fcf5ef2aSThomas Huth } 7616624cb07fSRichard Henderson 761764a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 761899082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 761964a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 762064a0f644SRichard Henderson } 762164a0f644SRichard Henderson 762251eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 7623fcf5ef2aSThomas Huth } 7624b0c2d521SEmilio G. Cota 7625b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7626b0c2d521SEmilio G. Cota { 7627b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7628a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7629a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7630b0c2d521SEmilio G. Cota 7631a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7632a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 76333d8a5b69SRichard Henderson return; 76343d8a5b69SRichard Henderson } 76353d8a5b69SRichard Henderson 7636a9b5b3d0SRichard Henderson /* Honor single stepping. */ 76379498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 76389498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7639a9b5b3d0SRichard Henderson switch (is_jmp) { 7640a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7641a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7642a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7643a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7644a9b5b3d0SRichard Henderson break; 7645a9b5b3d0SRichard Henderson case DISAS_EXIT: 7646a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7647a9b5b3d0SRichard Henderson break; 7648a9b5b3d0SRichard Henderson default: 7649a9b5b3d0SRichard Henderson g_assert_not_reached(); 7650fcf5ef2aSThomas Huth } 765113b45575SRichard Henderson 7652a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7653a9b5b3d0SRichard Henderson return; 7654a9b5b3d0SRichard Henderson } 7655a9b5b3d0SRichard Henderson 7656a9b5b3d0SRichard Henderson switch (is_jmp) { 7657a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7658a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 765946d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7660a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7661a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7662a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7663a9b5b3d0SRichard Henderson break; 7664a9b5b3d0SRichard Henderson } 7665a9b5b3d0SRichard Henderson /* fall through */ 7666a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7667a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7668a9b5b3d0SRichard Henderson /* fall through */ 7669a9b5b3d0SRichard Henderson case DISAS_CHAIN: 767046d396bdSDaniel Henrique Barboza /* 767146d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 767246d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 767346d396bdSDaniel Henrique Barboza */ 767446d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 767546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 767646d396bdSDaniel Henrique Barboza } 767746d396bdSDaniel Henrique Barboza 7678a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7679a9b5b3d0SRichard Henderson break; 7680a9b5b3d0SRichard Henderson 7681a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7682a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7683a9b5b3d0SRichard Henderson /* fall through */ 7684a9b5b3d0SRichard Henderson case DISAS_EXIT: 768546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 768607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7687a9b5b3d0SRichard Henderson break; 7688a9b5b3d0SRichard Henderson 7689a9b5b3d0SRichard Henderson default: 7690a9b5b3d0SRichard Henderson g_assert_not_reached(); 7691fcf5ef2aSThomas Huth } 7692fcf5ef2aSThomas Huth } 7693b0c2d521SEmilio G. Cota 76948eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 76958eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7696b0c2d521SEmilio G. Cota { 76978eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 76988eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7699b0c2d521SEmilio G. Cota } 7700b0c2d521SEmilio G. Cota 7701b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7702b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7703b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7704b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7705b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7706b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7707b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7708b0c2d521SEmilio G. Cota }; 7709b0c2d521SEmilio G. Cota 7710306c8721SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 7711306c8721SRichard Henderson target_ulong pc, void *host_pc) 7712b0c2d521SEmilio G. Cota { 7713b0c2d521SEmilio G. Cota DisasContext ctx; 7714b0c2d521SEmilio G. Cota 7715306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7716fcf5ef2aSThomas Huth } 7717