1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26fcf5ef2aSThomas Huth #include "tcg-op.h" 27fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #include "trace-tcg.h" 34fcf5ef2aSThomas Huth #include "exec/log.h" 35fcf5ef2aSThomas Huth 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 38fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 39fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 40fcf5ef2aSThomas Huth 41fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 42fcf5ef2aSThomas Huth //#define PPC_DEBUG_DISAS 43fcf5ef2aSThomas Huth //#define DO_PPC_STATISTICS 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 46fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 47fcf5ef2aSThomas Huth #else 48fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 49fcf5ef2aSThomas Huth #endif 50fcf5ef2aSThomas Huth /*****************************************************************************/ 51fcf5ef2aSThomas Huth /* Code translation helpers */ 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth /* global register indexes */ 54fcf5ef2aSThomas Huth static TCGv_env cpu_env; 55fcf5ef2aSThomas Huth static char cpu_reg_names[10*3 + 22*4 /* GPR */ 56fcf5ef2aSThomas Huth + 10*4 + 22*5 /* SPE GPRh */ 57fcf5ef2aSThomas Huth + 10*4 + 22*5 /* FPR */ 58fcf5ef2aSThomas Huth + 2*(10*6 + 22*7) /* AVRh, AVRl */ 59fcf5ef2aSThomas Huth + 10*5 + 22*6 /* VSR */ 60fcf5ef2aSThomas Huth + 8*5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[32]; 64fcf5ef2aSThomas Huth static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 65fcf5ef2aSThomas Huth static TCGv_i64 cpu_vsr[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74fcf5ef2aSThomas Huth static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 77fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth void ppc_translate_init(void) 82fcf5ef2aSThomas Huth { 83fcf5ef2aSThomas Huth int i; 84fcf5ef2aSThomas Huth char* p; 85fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 86fcf5ef2aSThomas Huth static int done_init = 0; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth if (done_init) 89fcf5ef2aSThomas Huth return; 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 92fcf5ef2aSThomas Huth tcg_ctx.tcg_env = cpu_env; 93fcf5ef2aSThomas Huth 94fcf5ef2aSThomas Huth p = cpu_reg_names; 95fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 96fcf5ef2aSThomas Huth 97fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 98fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 99fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 100fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 101fcf5ef2aSThomas Huth p += 5; 102fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 103fcf5ef2aSThomas Huth } 104fcf5ef2aSThomas Huth 105fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 106fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 107fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 108fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 109fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 110fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 111fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 112fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 114fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 115fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "fp%d", i); 118fcf5ef2aSThomas Huth cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpr[i]), p); 120fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 121fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dH", i); 124fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 125fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 127fcf5ef2aSThomas Huth #else 128fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 130fcf5ef2aSThomas Huth #endif 131fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 132fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 133fcf5ef2aSThomas Huth 134fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dL", i); 135fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 136fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 137fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 138fcf5ef2aSThomas Huth #else 139fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 141fcf5ef2aSThomas Huth #endif 142fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 143fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 144fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "vsr%d", i); 145fcf5ef2aSThomas Huth cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 146fcf5ef2aSThomas Huth offsetof(CPUPPCState, vsr[i]), p); 147fcf5ef2aSThomas Huth p += (i < 10) ? 5 : 6; 148fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 5 : 6; 149fcf5ef2aSThomas Huth } 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 152fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 155fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 158fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 159fcf5ef2aSThomas Huth 160fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 161fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 162fcf5ef2aSThomas Huth 163fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 164fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 165fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 166fcf5ef2aSThomas Huth #endif 167fcf5ef2aSThomas Huth 168fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 169fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 170fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 171fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 172fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 173fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 174fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 175fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 176fcf5ef2aSThomas Huth 177fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 178fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 179fcf5ef2aSThomas Huth "reserve_addr"); 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 182fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 183fcf5ef2aSThomas Huth 184fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 185fcf5ef2aSThomas Huth offsetof(CPUPPCState, access_type), "access_type"); 186fcf5ef2aSThomas Huth 187fcf5ef2aSThomas Huth done_init = 1; 188fcf5ef2aSThomas Huth } 189fcf5ef2aSThomas Huth 190fcf5ef2aSThomas Huth /* internal defines */ 191fcf5ef2aSThomas Huth struct DisasContext { 192fcf5ef2aSThomas Huth struct TranslationBlock *tb; 193fcf5ef2aSThomas Huth target_ulong nip; 194fcf5ef2aSThomas Huth uint32_t opcode; 195fcf5ef2aSThomas Huth uint32_t exception; 196fcf5ef2aSThomas Huth /* Routine used to access memory */ 197fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 198fcf5ef2aSThomas Huth bool lazy_tlb_flush; 199fcf5ef2aSThomas Huth bool need_access_type; 200fcf5ef2aSThomas Huth int mem_idx; 201fcf5ef2aSThomas Huth int access_type; 202fcf5ef2aSThomas Huth /* Translation flags */ 203fcf5ef2aSThomas Huth TCGMemOp default_tcg_memop_mask; 204fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 205fcf5ef2aSThomas Huth bool sf_mode; 206fcf5ef2aSThomas Huth bool has_cfar; 207fcf5ef2aSThomas Huth #endif 208fcf5ef2aSThomas Huth bool fpu_enabled; 209fcf5ef2aSThomas Huth bool altivec_enabled; 210fcf5ef2aSThomas Huth bool vsx_enabled; 211fcf5ef2aSThomas Huth bool spe_enabled; 212fcf5ef2aSThomas Huth bool tm_enabled; 213fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 214fcf5ef2aSThomas Huth int singlestep_enabled; 215fcf5ef2aSThomas Huth uint64_t insns_flags; 216fcf5ef2aSThomas Huth uint64_t insns_flags2; 217fcf5ef2aSThomas Huth }; 218fcf5ef2aSThomas Huth 219fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 220fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 221fcf5ef2aSThomas Huth { 222fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 223fcf5ef2aSThomas Huth return ctx->le_mode; 224fcf5ef2aSThomas Huth #else 225fcf5ef2aSThomas Huth return !ctx->le_mode; 226fcf5ef2aSThomas Huth #endif 227fcf5ef2aSThomas Huth } 228fcf5ef2aSThomas Huth 229fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 230fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 231fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 232fcf5ef2aSThomas Huth #else 233fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 234fcf5ef2aSThomas Huth #endif 235fcf5ef2aSThomas Huth 236fcf5ef2aSThomas Huth struct opc_handler_t { 237fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 238fcf5ef2aSThomas Huth uint32_t inval1; 239fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 240fcf5ef2aSThomas Huth uint32_t inval2; 241fcf5ef2aSThomas Huth /* instruction type */ 242fcf5ef2aSThomas Huth uint64_t type; 243fcf5ef2aSThomas Huth /* extended instruction type */ 244fcf5ef2aSThomas Huth uint64_t type2; 245fcf5ef2aSThomas Huth /* handler */ 246fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 247fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 248fcf5ef2aSThomas Huth const char *oname; 249fcf5ef2aSThomas Huth #endif 250fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 251fcf5ef2aSThomas Huth uint64_t count; 252fcf5ef2aSThomas Huth #endif 253fcf5ef2aSThomas Huth }; 254fcf5ef2aSThomas Huth 255fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 256fcf5ef2aSThomas Huth { 257fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 258fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 259fcf5ef2aSThomas Huth ctx->access_type = access_type; 260fcf5ef2aSThomas Huth } 261fcf5ef2aSThomas Huth } 262fcf5ef2aSThomas Huth 263fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 264fcf5ef2aSThomas Huth { 265fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 266fcf5ef2aSThomas Huth nip = (uint32_t)nip; 267fcf5ef2aSThomas Huth } 268fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 269fcf5ef2aSThomas Huth } 270fcf5ef2aSThomas Huth 271fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 272fcf5ef2aSThomas Huth { 273fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 274fcf5ef2aSThomas Huth 275fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 276fcf5ef2aSThomas Huth * the faulting instruction 277fcf5ef2aSThomas Huth */ 278fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 279fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 282fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 283fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 284fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 285fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 286fcf5ef2aSThomas Huth ctx->exception = (excp); 287fcf5ef2aSThomas Huth } 288fcf5ef2aSThomas Huth 289fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 290fcf5ef2aSThomas Huth { 291fcf5ef2aSThomas Huth TCGv_i32 t0; 292fcf5ef2aSThomas Huth 293fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 294fcf5ef2aSThomas Huth * the faulting instruction 295fcf5ef2aSThomas Huth */ 296fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 297fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 298fcf5ef2aSThomas Huth } 299fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 300fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 301fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 302fcf5ef2aSThomas Huth ctx->exception = (excp); 303fcf5ef2aSThomas Huth } 304fcf5ef2aSThomas Huth 305fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 306fcf5ef2aSThomas Huth target_ulong nip) 307fcf5ef2aSThomas Huth { 308fcf5ef2aSThomas Huth TCGv_i32 t0; 309fcf5ef2aSThomas Huth 310fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 311fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 312fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 313fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 314fcf5ef2aSThomas Huth ctx->exception = (excp); 315fcf5ef2aSThomas Huth } 316fcf5ef2aSThomas Huth 317fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 318fcf5ef2aSThomas Huth { 319fcf5ef2aSThomas Huth TCGv_i32 t0; 320fcf5ef2aSThomas Huth 321fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 322fcf5ef2aSThomas Huth * the faulting instruction 323fcf5ef2aSThomas Huth */ 324fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 325fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 326fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 327fcf5ef2aSThomas Huth } 328fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 329fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 330fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 331fcf5ef2aSThomas Huth } 332fcf5ef2aSThomas Huth 333fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 334fcf5ef2aSThomas Huth { 335fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 336fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 337fcf5ef2aSThomas Huth } 338fcf5ef2aSThomas Huth 339fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 340fcf5ef2aSThomas Huth { 341fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 342fcf5ef2aSThomas Huth } 343fcf5ef2aSThomas Huth 344fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 345fcf5ef2aSThomas Huth { 346fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 347fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 348fcf5ef2aSThomas Huth } 349fcf5ef2aSThomas Huth 350fcf5ef2aSThomas Huth /* Stop translation */ 351fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 352fcf5ef2aSThomas Huth { 353fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 354fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 357fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 358fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 359fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 360fcf5ef2aSThomas Huth { 361fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 362fcf5ef2aSThomas Huth } 363fcf5ef2aSThomas Huth #endif 364fcf5ef2aSThomas Huth 365fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 366fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 367fcf5ef2aSThomas Huth 368fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 369fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 370fcf5ef2aSThomas Huth 371fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 372fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 373fcf5ef2aSThomas Huth 374fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 375fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 376fcf5ef2aSThomas Huth 377fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 378fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 379fcf5ef2aSThomas Huth 380fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 381fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 382fcf5ef2aSThomas Huth 383fcf5ef2aSThomas Huth typedef struct opcode_t { 384fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 385fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 386fcf5ef2aSThomas Huth unsigned char pad[4]; 387fcf5ef2aSThomas Huth #endif 388fcf5ef2aSThomas Huth opc_handler_t handler; 389fcf5ef2aSThomas Huth const char *oname; 390fcf5ef2aSThomas Huth } opcode_t; 391fcf5ef2aSThomas Huth 392fcf5ef2aSThomas Huth /* Helpers for priv. check */ 393fcf5ef2aSThomas Huth #define GEN_PRIV \ 394fcf5ef2aSThomas Huth do { \ 395fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 396fcf5ef2aSThomas Huth } while (0) 397fcf5ef2aSThomas Huth 398fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 399fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 400fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 401fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 402fcf5ef2aSThomas Huth #else 403fcf5ef2aSThomas Huth #define CHK_HV \ 404fcf5ef2aSThomas Huth do { \ 405fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 406fcf5ef2aSThomas Huth GEN_PRIV; \ 407fcf5ef2aSThomas Huth } \ 408fcf5ef2aSThomas Huth } while (0) 409fcf5ef2aSThomas Huth #define CHK_SV \ 410fcf5ef2aSThomas Huth do { \ 411fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 412fcf5ef2aSThomas Huth GEN_PRIV; \ 413fcf5ef2aSThomas Huth } \ 414fcf5ef2aSThomas Huth } while (0) 415fcf5ef2aSThomas Huth #define CHK_HVRM \ 416fcf5ef2aSThomas Huth do { \ 417fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 418fcf5ef2aSThomas Huth GEN_PRIV; \ 419fcf5ef2aSThomas Huth } \ 420fcf5ef2aSThomas Huth } while (0) 421fcf5ef2aSThomas Huth #endif 422fcf5ef2aSThomas Huth 423fcf5ef2aSThomas Huth #define CHK_NONE 424fcf5ef2aSThomas Huth 425fcf5ef2aSThomas Huth /*****************************************************************************/ 426fcf5ef2aSThomas Huth /* PowerPC instructions table */ 427fcf5ef2aSThomas Huth 428fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 429fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 430fcf5ef2aSThomas Huth { \ 431fcf5ef2aSThomas Huth .opc1 = op1, \ 432fcf5ef2aSThomas Huth .opc2 = op2, \ 433fcf5ef2aSThomas Huth .opc3 = op3, \ 434fcf5ef2aSThomas Huth .opc4 = 0xff, \ 435fcf5ef2aSThomas Huth .handler = { \ 436fcf5ef2aSThomas Huth .inval1 = invl, \ 437fcf5ef2aSThomas Huth .type = _typ, \ 438fcf5ef2aSThomas Huth .type2 = _typ2, \ 439fcf5ef2aSThomas Huth .handler = &gen_##name, \ 440fcf5ef2aSThomas Huth .oname = stringify(name), \ 441fcf5ef2aSThomas Huth }, \ 442fcf5ef2aSThomas Huth .oname = stringify(name), \ 443fcf5ef2aSThomas Huth } 444fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 445fcf5ef2aSThomas Huth { \ 446fcf5ef2aSThomas Huth .opc1 = op1, \ 447fcf5ef2aSThomas Huth .opc2 = op2, \ 448fcf5ef2aSThomas Huth .opc3 = op3, \ 449fcf5ef2aSThomas Huth .opc4 = 0xff, \ 450fcf5ef2aSThomas Huth .handler = { \ 451fcf5ef2aSThomas Huth .inval1 = invl1, \ 452fcf5ef2aSThomas Huth .inval2 = invl2, \ 453fcf5ef2aSThomas Huth .type = _typ, \ 454fcf5ef2aSThomas Huth .type2 = _typ2, \ 455fcf5ef2aSThomas Huth .handler = &gen_##name, \ 456fcf5ef2aSThomas Huth .oname = stringify(name), \ 457fcf5ef2aSThomas Huth }, \ 458fcf5ef2aSThomas Huth .oname = stringify(name), \ 459fcf5ef2aSThomas Huth } 460fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 461fcf5ef2aSThomas Huth { \ 462fcf5ef2aSThomas Huth .opc1 = op1, \ 463fcf5ef2aSThomas Huth .opc2 = op2, \ 464fcf5ef2aSThomas Huth .opc3 = op3, \ 465fcf5ef2aSThomas Huth .opc4 = 0xff, \ 466fcf5ef2aSThomas Huth .handler = { \ 467fcf5ef2aSThomas Huth .inval1 = invl, \ 468fcf5ef2aSThomas Huth .type = _typ, \ 469fcf5ef2aSThomas Huth .type2 = _typ2, \ 470fcf5ef2aSThomas Huth .handler = &gen_##name, \ 471fcf5ef2aSThomas Huth .oname = onam, \ 472fcf5ef2aSThomas Huth }, \ 473fcf5ef2aSThomas Huth .oname = onam, \ 474fcf5ef2aSThomas Huth } 475fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 476fcf5ef2aSThomas Huth { \ 477fcf5ef2aSThomas Huth .opc1 = op1, \ 478fcf5ef2aSThomas Huth .opc2 = op2, \ 479fcf5ef2aSThomas Huth .opc3 = op3, \ 480fcf5ef2aSThomas Huth .opc4 = op4, \ 481fcf5ef2aSThomas Huth .handler = { \ 482fcf5ef2aSThomas Huth .inval1 = invl, \ 483fcf5ef2aSThomas Huth .type = _typ, \ 484fcf5ef2aSThomas Huth .type2 = _typ2, \ 485fcf5ef2aSThomas Huth .handler = &gen_##name, \ 486fcf5ef2aSThomas Huth .oname = stringify(name), \ 487fcf5ef2aSThomas Huth }, \ 488fcf5ef2aSThomas Huth .oname = stringify(name), \ 489fcf5ef2aSThomas Huth } 490fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 491fcf5ef2aSThomas Huth { \ 492fcf5ef2aSThomas Huth .opc1 = op1, \ 493fcf5ef2aSThomas Huth .opc2 = op2, \ 494fcf5ef2aSThomas Huth .opc3 = op3, \ 495fcf5ef2aSThomas Huth .opc4 = op4, \ 496fcf5ef2aSThomas Huth .handler = { \ 497fcf5ef2aSThomas Huth .inval1 = invl, \ 498fcf5ef2aSThomas Huth .type = _typ, \ 499fcf5ef2aSThomas Huth .type2 = _typ2, \ 500fcf5ef2aSThomas Huth .handler = &gen_##name, \ 501fcf5ef2aSThomas Huth .oname = onam, \ 502fcf5ef2aSThomas Huth }, \ 503fcf5ef2aSThomas Huth .oname = onam, \ 504fcf5ef2aSThomas Huth } 505fcf5ef2aSThomas Huth #else 506fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 507fcf5ef2aSThomas Huth { \ 508fcf5ef2aSThomas Huth .opc1 = op1, \ 509fcf5ef2aSThomas Huth .opc2 = op2, \ 510fcf5ef2aSThomas Huth .opc3 = op3, \ 511fcf5ef2aSThomas Huth .opc4 = 0xff, \ 512fcf5ef2aSThomas Huth .handler = { \ 513fcf5ef2aSThomas Huth .inval1 = invl, \ 514fcf5ef2aSThomas Huth .type = _typ, \ 515fcf5ef2aSThomas Huth .type2 = _typ2, \ 516fcf5ef2aSThomas Huth .handler = &gen_##name, \ 517fcf5ef2aSThomas Huth }, \ 518fcf5ef2aSThomas Huth .oname = stringify(name), \ 519fcf5ef2aSThomas Huth } 520fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 521fcf5ef2aSThomas Huth { \ 522fcf5ef2aSThomas Huth .opc1 = op1, \ 523fcf5ef2aSThomas Huth .opc2 = op2, \ 524fcf5ef2aSThomas Huth .opc3 = op3, \ 525fcf5ef2aSThomas Huth .opc4 = 0xff, \ 526fcf5ef2aSThomas Huth .handler = { \ 527fcf5ef2aSThomas Huth .inval1 = invl1, \ 528fcf5ef2aSThomas Huth .inval2 = invl2, \ 529fcf5ef2aSThomas Huth .type = _typ, \ 530fcf5ef2aSThomas Huth .type2 = _typ2, \ 531fcf5ef2aSThomas Huth .handler = &gen_##name, \ 532fcf5ef2aSThomas Huth }, \ 533fcf5ef2aSThomas Huth .oname = stringify(name), \ 534fcf5ef2aSThomas Huth } 535fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 536fcf5ef2aSThomas Huth { \ 537fcf5ef2aSThomas Huth .opc1 = op1, \ 538fcf5ef2aSThomas Huth .opc2 = op2, \ 539fcf5ef2aSThomas Huth .opc3 = op3, \ 540fcf5ef2aSThomas Huth .opc4 = 0xff, \ 541fcf5ef2aSThomas Huth .handler = { \ 542fcf5ef2aSThomas Huth .inval1 = invl, \ 543fcf5ef2aSThomas Huth .type = _typ, \ 544fcf5ef2aSThomas Huth .type2 = _typ2, \ 545fcf5ef2aSThomas Huth .handler = &gen_##name, \ 546fcf5ef2aSThomas Huth }, \ 547fcf5ef2aSThomas Huth .oname = onam, \ 548fcf5ef2aSThomas Huth } 549fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 550fcf5ef2aSThomas Huth { \ 551fcf5ef2aSThomas Huth .opc1 = op1, \ 552fcf5ef2aSThomas Huth .opc2 = op2, \ 553fcf5ef2aSThomas Huth .opc3 = op3, \ 554fcf5ef2aSThomas Huth .opc4 = op4, \ 555fcf5ef2aSThomas Huth .handler = { \ 556fcf5ef2aSThomas Huth .inval1 = invl, \ 557fcf5ef2aSThomas Huth .type = _typ, \ 558fcf5ef2aSThomas Huth .type2 = _typ2, \ 559fcf5ef2aSThomas Huth .handler = &gen_##name, \ 560fcf5ef2aSThomas Huth }, \ 561fcf5ef2aSThomas Huth .oname = stringify(name), \ 562fcf5ef2aSThomas Huth } 563fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 564fcf5ef2aSThomas Huth { \ 565fcf5ef2aSThomas Huth .opc1 = op1, \ 566fcf5ef2aSThomas Huth .opc2 = op2, \ 567fcf5ef2aSThomas Huth .opc3 = op3, \ 568fcf5ef2aSThomas Huth .opc4 = op4, \ 569fcf5ef2aSThomas Huth .handler = { \ 570fcf5ef2aSThomas Huth .inval1 = invl, \ 571fcf5ef2aSThomas Huth .type = _typ, \ 572fcf5ef2aSThomas Huth .type2 = _typ2, \ 573fcf5ef2aSThomas Huth .handler = &gen_##name, \ 574fcf5ef2aSThomas Huth }, \ 575fcf5ef2aSThomas Huth .oname = onam, \ 576fcf5ef2aSThomas Huth } 577fcf5ef2aSThomas Huth #endif 578fcf5ef2aSThomas Huth 579fcf5ef2aSThomas Huth /* SPR load/store helpers */ 580fcf5ef2aSThomas Huth static inline void gen_load_spr(TCGv t, int reg) 581fcf5ef2aSThomas Huth { 582fcf5ef2aSThomas Huth tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 583fcf5ef2aSThomas Huth } 584fcf5ef2aSThomas Huth 585fcf5ef2aSThomas Huth static inline void gen_store_spr(int reg, TCGv t) 586fcf5ef2aSThomas Huth { 587fcf5ef2aSThomas Huth tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 588fcf5ef2aSThomas Huth } 589fcf5ef2aSThomas Huth 590fcf5ef2aSThomas Huth /* Invalid instruction */ 591fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 592fcf5ef2aSThomas Huth { 593fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 594fcf5ef2aSThomas Huth } 595fcf5ef2aSThomas Huth 596fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 597fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 598fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 599fcf5ef2aSThomas Huth .type = PPC_NONE, 600fcf5ef2aSThomas Huth .type2 = PPC_NONE, 601fcf5ef2aSThomas Huth .handler = gen_invalid, 602fcf5ef2aSThomas Huth }; 603fcf5ef2aSThomas Huth 604fcf5ef2aSThomas Huth /*** Integer comparison ***/ 605fcf5ef2aSThomas Huth 606fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 607fcf5ef2aSThomas Huth { 608fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 609fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 610fcf5ef2aSThomas Huth 611fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 612fcf5ef2aSThomas Huth 613fcf5ef2aSThomas Huth tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); 614fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 615efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_LT_BIT); 616fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 617fcf5ef2aSThomas Huth 618fcf5ef2aSThomas Huth tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); 619fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 620efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_GT_BIT); 621fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 622fcf5ef2aSThomas Huth 623fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); 624fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 625efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT); 626fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 627fcf5ef2aSThomas Huth 628fcf5ef2aSThomas Huth tcg_temp_free(t0); 629fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 630fcf5ef2aSThomas Huth } 631fcf5ef2aSThomas Huth 632fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 633fcf5ef2aSThomas Huth { 634fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 635fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 636fcf5ef2aSThomas Huth tcg_temp_free(t0); 637fcf5ef2aSThomas Huth } 638fcf5ef2aSThomas Huth 639fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 640fcf5ef2aSThomas Huth { 641fcf5ef2aSThomas Huth TCGv t0, t1; 642fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 643fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 644fcf5ef2aSThomas Huth if (s) { 645fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 646fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 647fcf5ef2aSThomas Huth } else { 648fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 649fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 650fcf5ef2aSThomas Huth } 651fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 652fcf5ef2aSThomas Huth tcg_temp_free(t1); 653fcf5ef2aSThomas Huth tcg_temp_free(t0); 654fcf5ef2aSThomas Huth } 655fcf5ef2aSThomas Huth 656fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 657fcf5ef2aSThomas Huth { 658fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 659fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 660fcf5ef2aSThomas Huth tcg_temp_free(t0); 661fcf5ef2aSThomas Huth } 662fcf5ef2aSThomas Huth 663fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 664fcf5ef2aSThomas Huth { 665fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 666fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 667fcf5ef2aSThomas Huth } else { 668fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 669fcf5ef2aSThomas Huth } 670fcf5ef2aSThomas Huth } 671fcf5ef2aSThomas Huth 672fcf5ef2aSThomas Huth /* cmp */ 673fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 674fcf5ef2aSThomas Huth { 675fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 676fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 677fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 678fcf5ef2aSThomas Huth } else { 679fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 680fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 681fcf5ef2aSThomas Huth } 682fcf5ef2aSThomas Huth } 683fcf5ef2aSThomas Huth 684fcf5ef2aSThomas Huth /* cmpi */ 685fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 686fcf5ef2aSThomas Huth { 687fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 688fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 689fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 690fcf5ef2aSThomas Huth } else { 691fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 692fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 693fcf5ef2aSThomas Huth } 694fcf5ef2aSThomas Huth } 695fcf5ef2aSThomas Huth 696fcf5ef2aSThomas Huth /* cmpl */ 697fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 698fcf5ef2aSThomas Huth { 699fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 700fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 701fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 702fcf5ef2aSThomas Huth } else { 703fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 704fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 705fcf5ef2aSThomas Huth } 706fcf5ef2aSThomas Huth } 707fcf5ef2aSThomas Huth 708fcf5ef2aSThomas Huth /* cmpli */ 709fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 710fcf5ef2aSThomas Huth { 711fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 712fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 713fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 714fcf5ef2aSThomas Huth } else { 715fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 716fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 717fcf5ef2aSThomas Huth } 718fcf5ef2aSThomas Huth } 719fcf5ef2aSThomas Huth 720fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 721fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 722fcf5ef2aSThomas Huth { 723fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 724fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 725fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 726fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 727fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 728fcf5ef2aSThomas Huth 729fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 730fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 731fcf5ef2aSThomas Huth 732fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 733fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 734fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 735fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 736fcf5ef2aSThomas Huth 737fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 738fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 739fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 740fcf5ef2aSThomas Huth 741fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 742fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 743fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 744fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 745fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 746fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 747fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 748fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 749fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 750fcf5ef2aSThomas Huth } 751efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 752fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 753fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 754fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 755fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 756fcf5ef2aSThomas Huth } 757fcf5ef2aSThomas Huth 758fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 759fcf5ef2aSThomas Huth /* cmpeqb */ 760fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 761fcf5ef2aSThomas Huth { 762fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 763fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 764fcf5ef2aSThomas Huth } 765fcf5ef2aSThomas Huth #endif 766fcf5ef2aSThomas Huth 767fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 768fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 769fcf5ef2aSThomas Huth { 770fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 771fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 772fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 773fcf5ef2aSThomas Huth TCGv zr; 774fcf5ef2aSThomas Huth 775fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 776fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 777fcf5ef2aSThomas Huth 778fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 779fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 780fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 781fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 782fcf5ef2aSThomas Huth tcg_temp_free(zr); 783fcf5ef2aSThomas Huth tcg_temp_free(t0); 784fcf5ef2aSThomas Huth } 785fcf5ef2aSThomas Huth 786fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 787fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 788fcf5ef2aSThomas Huth { 789fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 790fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 791fcf5ef2aSThomas Huth } 792fcf5ef2aSThomas Huth 793fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 794fcf5ef2aSThomas Huth 795fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 796fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 797fcf5ef2aSThomas Huth { 798fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 799fcf5ef2aSThomas Huth 800fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 801fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 802fcf5ef2aSThomas Huth if (sub) { 803fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 804fcf5ef2aSThomas Huth } else { 805fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 806fcf5ef2aSThomas Huth } 807fcf5ef2aSThomas Huth tcg_temp_free(t0); 808fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 809fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(cpu_ov, cpu_ov); 810fcf5ef2aSThomas Huth } 811fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); 812fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 813fcf5ef2aSThomas Huth } 814fcf5ef2aSThomas Huth 815fcf5ef2aSThomas Huth /* Common add function */ 816fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 817fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 818fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 819fcf5ef2aSThomas Huth { 820fcf5ef2aSThomas Huth TCGv t0 = ret; 821fcf5ef2aSThomas Huth 822fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 823fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 824fcf5ef2aSThomas Huth } 825fcf5ef2aSThomas Huth 826fcf5ef2aSThomas Huth if (compute_ca) { 827fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 828fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 829fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 830fcf5ef2aSThomas Huth carry into bit 32. */ 831fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 832fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 833fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 834fcf5ef2aSThomas Huth if (add_ca) { 835fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 836fcf5ef2aSThomas Huth } 837fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 838fcf5ef2aSThomas Huth tcg_temp_free(t1); 839fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ 840fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); 841fcf5ef2aSThomas Huth } else { 842fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 843fcf5ef2aSThomas Huth if (add_ca) { 844fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 845fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 846fcf5ef2aSThomas Huth } else { 847fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 848fcf5ef2aSThomas Huth } 849fcf5ef2aSThomas Huth tcg_temp_free(zero); 850fcf5ef2aSThomas Huth } 851fcf5ef2aSThomas Huth } else { 852fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 853fcf5ef2aSThomas Huth if (add_ca) { 854fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 855fcf5ef2aSThomas Huth } 856fcf5ef2aSThomas Huth } 857fcf5ef2aSThomas Huth 858fcf5ef2aSThomas Huth if (compute_ov) { 859fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 860fcf5ef2aSThomas Huth } 861fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 862fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 863fcf5ef2aSThomas Huth } 864fcf5ef2aSThomas Huth 865fcf5ef2aSThomas Huth if (!TCGV_EQUAL(t0, ret)) { 866fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 867fcf5ef2aSThomas Huth tcg_temp_free(t0); 868fcf5ef2aSThomas Huth } 869fcf5ef2aSThomas Huth } 870fcf5ef2aSThomas Huth /* Add functions with two operands */ 871fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 872fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 873fcf5ef2aSThomas Huth { \ 874fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 875fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 876fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 877fcf5ef2aSThomas Huth } 878fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 879fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 880fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 881fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 882fcf5ef2aSThomas Huth { \ 883fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 884fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 885fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 886fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 887fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 888fcf5ef2aSThomas Huth } 889fcf5ef2aSThomas Huth 890fcf5ef2aSThomas Huth /* add add. addo addo. */ 891fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 892fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 893fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 894fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 895fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 896fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 897fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 898fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 899fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 900fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 901fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 902fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 903fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 904fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 905fcf5ef2aSThomas Huth /* addi */ 906fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 907fcf5ef2aSThomas Huth { 908fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 909fcf5ef2aSThomas Huth 910fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 911fcf5ef2aSThomas Huth /* li case */ 912fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 913fcf5ef2aSThomas Huth } else { 914fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 915fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 916fcf5ef2aSThomas Huth } 917fcf5ef2aSThomas Huth } 918fcf5ef2aSThomas Huth /* addic addic.*/ 919fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 920fcf5ef2aSThomas Huth { 921fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 922fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 923fcf5ef2aSThomas Huth c, 0, 1, 0, compute_rc0); 924fcf5ef2aSThomas Huth tcg_temp_free(c); 925fcf5ef2aSThomas Huth } 926fcf5ef2aSThomas Huth 927fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 928fcf5ef2aSThomas Huth { 929fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 930fcf5ef2aSThomas Huth } 931fcf5ef2aSThomas Huth 932fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 933fcf5ef2aSThomas Huth { 934fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 935fcf5ef2aSThomas Huth } 936fcf5ef2aSThomas Huth 937fcf5ef2aSThomas Huth /* addis */ 938fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 939fcf5ef2aSThomas Huth { 940fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 941fcf5ef2aSThomas Huth 942fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 943fcf5ef2aSThomas Huth /* lis case */ 944fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 945fcf5ef2aSThomas Huth } else { 946fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 947fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 948fcf5ef2aSThomas Huth } 949fcf5ef2aSThomas Huth } 950fcf5ef2aSThomas Huth 951fcf5ef2aSThomas Huth /* addpcis */ 952fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 953fcf5ef2aSThomas Huth { 954fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 955fcf5ef2aSThomas Huth 956fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16)); 957fcf5ef2aSThomas Huth } 958fcf5ef2aSThomas Huth 959fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 960fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 961fcf5ef2aSThomas Huth { 962fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 963fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 964fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 965fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 966fcf5ef2aSThomas Huth 967fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 968fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 969fcf5ef2aSThomas Huth if (sign) { 970fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 971fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 972fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 973fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 974fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 975fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 976fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 977fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 978fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 979fcf5ef2aSThomas Huth } else { 980fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 981fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 982fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 983fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 984fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 985fcf5ef2aSThomas Huth } 986fcf5ef2aSThomas Huth if (compute_ov) { 987fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 988fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 989fcf5ef2aSThomas Huth } 990fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 991fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 992fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 993fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 994fcf5ef2aSThomas Huth 995fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 996fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 997fcf5ef2aSThomas Huth } 998fcf5ef2aSThomas Huth /* Div functions */ 999fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1000fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1001fcf5ef2aSThomas Huth { \ 1002fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1003fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1004fcf5ef2aSThomas Huth sign, compute_ov); \ 1005fcf5ef2aSThomas Huth } 1006fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1007fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1008fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1009fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1010fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1011fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1012fcf5ef2aSThomas Huth 1013fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1014fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1015fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1016fcf5ef2aSThomas Huth { \ 1017fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1018fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1019fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1020fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1021fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1022fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1023fcf5ef2aSThomas Huth } \ 1024fcf5ef2aSThomas Huth } 1025fcf5ef2aSThomas Huth 1026fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1027fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1028fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1029fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1030fcf5ef2aSThomas Huth 1031fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1032fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1033fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1034fcf5ef2aSThomas Huth { 1035fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1036fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1037fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1038fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1039fcf5ef2aSThomas Huth 1040fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1041fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1042fcf5ef2aSThomas Huth if (sign) { 1043fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1044fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1045fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1046fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1047fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1048fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1049fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1050fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1051fcf5ef2aSThomas Huth } else { 1052fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1053fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1054fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1055fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1056fcf5ef2aSThomas Huth } 1057fcf5ef2aSThomas Huth if (compute_ov) { 1058fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1059fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1060fcf5ef2aSThomas Huth } 1061fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1062fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1063fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1064fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1065fcf5ef2aSThomas Huth 1066fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1067fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1068fcf5ef2aSThomas Huth } 1069fcf5ef2aSThomas Huth 1070fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1071fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1072fcf5ef2aSThomas Huth { \ 1073fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1074fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1075fcf5ef2aSThomas Huth sign, compute_ov); \ 1076fcf5ef2aSThomas Huth } 1077fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1078fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1079fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1080fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1081fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1082fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1083fcf5ef2aSThomas Huth 1084fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1085fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1086fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1087fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1088fcf5ef2aSThomas Huth #endif 1089fcf5ef2aSThomas Huth 1090fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1091fcf5ef2aSThomas Huth TCGv arg2, int sign) 1092fcf5ef2aSThomas Huth { 1093fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1094fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1095fcf5ef2aSThomas Huth 1096fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1097fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1098fcf5ef2aSThomas Huth if (sign) { 1099fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1100fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1101fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1102fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1103fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1104fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1105fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1106fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1107fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1108fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1109fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1110fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1111fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1112fcf5ef2aSThomas Huth } else { 1113fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1114fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1115fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1116fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1117fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1118fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1119fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1120fcf5ef2aSThomas Huth } 1121fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1122fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1123fcf5ef2aSThomas Huth } 1124fcf5ef2aSThomas Huth 1125fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1126fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1127fcf5ef2aSThomas Huth { \ 1128fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1129fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1130fcf5ef2aSThomas Huth sign); \ 1131fcf5ef2aSThomas Huth } 1132fcf5ef2aSThomas Huth 1133fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1134fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1135fcf5ef2aSThomas Huth 1136fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1137fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1138fcf5ef2aSThomas Huth TCGv arg2, int sign) 1139fcf5ef2aSThomas Huth { 1140fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1141fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1142fcf5ef2aSThomas Huth 1143fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1144fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1145fcf5ef2aSThomas Huth if (sign) { 1146fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1147fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1148fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1149fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1150fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1151fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1152fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1153fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1154fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1155fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1156fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1157fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1158fcf5ef2aSThomas Huth } else { 1159fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1160fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1161fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1162fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1163fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1164fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1165fcf5ef2aSThomas Huth } 1166fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1167fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1168fcf5ef2aSThomas Huth } 1169fcf5ef2aSThomas Huth 1170fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1171fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1172fcf5ef2aSThomas Huth { \ 1173fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1174fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1175fcf5ef2aSThomas Huth sign); \ 1176fcf5ef2aSThomas Huth } 1177fcf5ef2aSThomas Huth 1178fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1179fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1180fcf5ef2aSThomas Huth #endif 1181fcf5ef2aSThomas Huth 1182fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1183fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1184fcf5ef2aSThomas Huth { 1185fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1186fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1187fcf5ef2aSThomas Huth 1188fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1189fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1190fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1191fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1192fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1193fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1194fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1195fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1196fcf5ef2aSThomas Huth } 1197fcf5ef2aSThomas Huth 1198fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1199fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1200fcf5ef2aSThomas Huth { 1201fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1202fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1203fcf5ef2aSThomas Huth 1204fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1205fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1206fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1207fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1208fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1209fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1210fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1211fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1212fcf5ef2aSThomas Huth } 1213fcf5ef2aSThomas Huth 1214fcf5ef2aSThomas Huth /* mullw mullw. */ 1215fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1216fcf5ef2aSThomas Huth { 1217fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1218fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1219fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1220fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1221fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1222fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1223fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1224fcf5ef2aSThomas Huth tcg_temp_free(t0); 1225fcf5ef2aSThomas Huth tcg_temp_free(t1); 1226fcf5ef2aSThomas Huth #else 1227fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1228fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1229fcf5ef2aSThomas Huth #endif 1230fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1231fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1232fcf5ef2aSThomas Huth } 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1235fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1236fcf5ef2aSThomas Huth { 1237fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1238fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1239fcf5ef2aSThomas Huth 1240fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1241fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1242fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1243fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1244fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1245fcf5ef2aSThomas Huth #else 1246fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1247fcf5ef2aSThomas Huth #endif 1248fcf5ef2aSThomas Huth 1249fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1250fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1251fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 1252fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1253fcf5ef2aSThomas Huth 1254fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1255fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1256fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1257fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1258fcf5ef2aSThomas Huth } 1259fcf5ef2aSThomas Huth 1260fcf5ef2aSThomas Huth /* mulli */ 1261fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1262fcf5ef2aSThomas Huth { 1263fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1264fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1265fcf5ef2aSThomas Huth } 1266fcf5ef2aSThomas Huth 1267fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1268fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1269fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1270fcf5ef2aSThomas Huth { 1271fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1272fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1273fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1274fcf5ef2aSThomas Huth tcg_temp_free(lo); 1275fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1276fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1277fcf5ef2aSThomas Huth } 1278fcf5ef2aSThomas Huth } 1279fcf5ef2aSThomas Huth 1280fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1281fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1282fcf5ef2aSThomas Huth { 1283fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1284fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1285fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1286fcf5ef2aSThomas Huth tcg_temp_free(lo); 1287fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1288fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1289fcf5ef2aSThomas Huth } 1290fcf5ef2aSThomas Huth } 1291fcf5ef2aSThomas Huth 1292fcf5ef2aSThomas Huth /* mulld mulld. */ 1293fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1294fcf5ef2aSThomas Huth { 1295fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1296fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1297fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1298fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1299fcf5ef2aSThomas Huth } 1300fcf5ef2aSThomas Huth 1301fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1302fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1303fcf5ef2aSThomas Huth { 1304fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1305fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1306fcf5ef2aSThomas Huth 1307fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1308fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1309fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1310fcf5ef2aSThomas Huth 1311fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1312fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1313fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1314fcf5ef2aSThomas Huth 1315fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1316fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1317fcf5ef2aSThomas Huth 1318fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1319fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1320fcf5ef2aSThomas Huth } 1321fcf5ef2aSThomas Huth } 1322fcf5ef2aSThomas Huth #endif 1323fcf5ef2aSThomas Huth 1324fcf5ef2aSThomas Huth /* Common subf function */ 1325fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1326fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1327fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1328fcf5ef2aSThomas Huth { 1329fcf5ef2aSThomas Huth TCGv t0 = ret; 1330fcf5ef2aSThomas Huth 1331fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1332fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1333fcf5ef2aSThomas Huth } 1334fcf5ef2aSThomas Huth 1335fcf5ef2aSThomas Huth if (compute_ca) { 1336fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1337fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1338fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 1339fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 1340fcf5ef2aSThomas Huth carry into bit 32. */ 1341fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1342fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1343fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1344fcf5ef2aSThomas Huth if (add_ca) { 1345fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1346fcf5ef2aSThomas Huth } else { 1347fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1348fcf5ef2aSThomas Huth } 1349fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1350fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1351fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1352fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1353fcf5ef2aSThomas Huth tcg_temp_free(t1); 1354fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ 1355fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); 1356fcf5ef2aSThomas Huth } else if (add_ca) { 1357fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1358fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1359fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1360fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1361fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1362fcf5ef2aSThomas Huth tcg_temp_free(zero); 1363fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1364fcf5ef2aSThomas Huth } else { 1365fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1366fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1367fcf5ef2aSThomas Huth } 1368fcf5ef2aSThomas Huth } else if (add_ca) { 1369fcf5ef2aSThomas Huth /* Since we're ignoring carry-out, we can simplify the 1370fcf5ef2aSThomas Huth standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1371fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1372fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1373fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1374fcf5ef2aSThomas Huth } else { 1375fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1376fcf5ef2aSThomas Huth } 1377fcf5ef2aSThomas Huth 1378fcf5ef2aSThomas Huth if (compute_ov) { 1379fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1380fcf5ef2aSThomas Huth } 1381fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1382fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1383fcf5ef2aSThomas Huth } 1384fcf5ef2aSThomas Huth 1385fcf5ef2aSThomas Huth if (!TCGV_EQUAL(t0, ret)) { 1386fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1387fcf5ef2aSThomas Huth tcg_temp_free(t0); 1388fcf5ef2aSThomas Huth } 1389fcf5ef2aSThomas Huth } 1390fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1391fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1392fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1393fcf5ef2aSThomas Huth { \ 1394fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1395fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1396fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1397fcf5ef2aSThomas Huth } 1398fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1399fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1400fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1401fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1402fcf5ef2aSThomas Huth { \ 1403fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1404fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1405fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1406fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1407fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1408fcf5ef2aSThomas Huth } 1409fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1410fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1411fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1412fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1413fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1414fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1415fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1416fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1417fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1418fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1419fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1420fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1421fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1422fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1423fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1424fcf5ef2aSThomas Huth 1425fcf5ef2aSThomas Huth /* subfic */ 1426fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1427fcf5ef2aSThomas Huth { 1428fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1429fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1430fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1431fcf5ef2aSThomas Huth tcg_temp_free(c); 1432fcf5ef2aSThomas Huth } 1433fcf5ef2aSThomas Huth 1434fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1435fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1436fcf5ef2aSThomas Huth { 1437fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1438fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1439fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1440fcf5ef2aSThomas Huth tcg_temp_free(zero); 1441fcf5ef2aSThomas Huth } 1442fcf5ef2aSThomas Huth 1443fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1444fcf5ef2aSThomas Huth { 1445fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 0); 1446fcf5ef2aSThomas Huth } 1447fcf5ef2aSThomas Huth 1448fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1449fcf5ef2aSThomas Huth { 1450fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1451fcf5ef2aSThomas Huth } 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth /*** Integer logical ***/ 1454fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1455fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1456fcf5ef2aSThomas Huth { \ 1457fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1458fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1459fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1460fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1461fcf5ef2aSThomas Huth } 1462fcf5ef2aSThomas Huth 1463fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1464fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1465fcf5ef2aSThomas Huth { \ 1466fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1467fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1468fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1469fcf5ef2aSThomas Huth } 1470fcf5ef2aSThomas Huth 1471fcf5ef2aSThomas Huth /* and & and. */ 1472fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1473fcf5ef2aSThomas Huth /* andc & andc. */ 1474fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1475fcf5ef2aSThomas Huth 1476fcf5ef2aSThomas Huth /* andi. */ 1477fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1478fcf5ef2aSThomas Huth { 1479fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1480fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1481fcf5ef2aSThomas Huth } 1482fcf5ef2aSThomas Huth 1483fcf5ef2aSThomas Huth /* andis. */ 1484fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1485fcf5ef2aSThomas Huth { 1486fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1487fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1488fcf5ef2aSThomas Huth } 1489fcf5ef2aSThomas Huth 1490fcf5ef2aSThomas Huth /* cntlzw */ 1491fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1492fcf5ef2aSThomas Huth { 14939b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 14949b8514e5SRichard Henderson 14959b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 14969b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 14979b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 14989b8514e5SRichard Henderson tcg_temp_free_i32(t); 14999b8514e5SRichard Henderson 1500fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1501fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1502fcf5ef2aSThomas Huth } 1503fcf5ef2aSThomas Huth 1504fcf5ef2aSThomas Huth /* cnttzw */ 1505fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1506fcf5ef2aSThomas Huth { 15079b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15089b8514e5SRichard Henderson 15099b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15109b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15119b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15129b8514e5SRichard Henderson tcg_temp_free_i32(t); 15139b8514e5SRichard Henderson 1514fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1515fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1516fcf5ef2aSThomas Huth } 1517fcf5ef2aSThomas Huth } 1518fcf5ef2aSThomas Huth 1519fcf5ef2aSThomas Huth /* eqv & eqv. */ 1520fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1521fcf5ef2aSThomas Huth /* extsb & extsb. */ 1522fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1523fcf5ef2aSThomas Huth /* extsh & extsh. */ 1524fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1525fcf5ef2aSThomas Huth /* nand & nand. */ 1526fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1527fcf5ef2aSThomas Huth /* nor & nor. */ 1528fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1529fcf5ef2aSThomas Huth 1530fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1531fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1532fcf5ef2aSThomas Huth { 1533fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1534fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1535fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1536fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1537fcf5ef2aSThomas Huth 1538fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1539fcf5ef2aSThomas Huth gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 1540fcf5ef2aSThomas Huth } 1541fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1542fcf5ef2aSThomas Huth 1543fcf5ef2aSThomas Huth /* or & or. */ 1544fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1545fcf5ef2aSThomas Huth { 1546fcf5ef2aSThomas Huth int rs, ra, rb; 1547fcf5ef2aSThomas Huth 1548fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1549fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1550fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1551fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1552fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1553fcf5ef2aSThomas Huth if (rs != rb) 1554fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1555fcf5ef2aSThomas Huth else 1556fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1557fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1558fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1559fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1560fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1561fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1562fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1563fcf5ef2aSThomas Huth int prio = 0; 1564fcf5ef2aSThomas Huth 1565fcf5ef2aSThomas Huth switch (rs) { 1566fcf5ef2aSThomas Huth case 1: 1567fcf5ef2aSThomas Huth /* Set process priority to low */ 1568fcf5ef2aSThomas Huth prio = 2; 1569fcf5ef2aSThomas Huth break; 1570fcf5ef2aSThomas Huth case 6: 1571fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1572fcf5ef2aSThomas Huth prio = 3; 1573fcf5ef2aSThomas Huth break; 1574fcf5ef2aSThomas Huth case 2: 1575fcf5ef2aSThomas Huth /* Set process priority to normal */ 1576fcf5ef2aSThomas Huth prio = 4; 1577fcf5ef2aSThomas Huth break; 1578fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1579fcf5ef2aSThomas Huth case 31: 1580fcf5ef2aSThomas Huth if (!ctx->pr) { 1581fcf5ef2aSThomas Huth /* Set process priority to very low */ 1582fcf5ef2aSThomas Huth prio = 1; 1583fcf5ef2aSThomas Huth } 1584fcf5ef2aSThomas Huth break; 1585fcf5ef2aSThomas Huth case 5: 1586fcf5ef2aSThomas Huth if (!ctx->pr) { 1587fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1588fcf5ef2aSThomas Huth prio = 5; 1589fcf5ef2aSThomas Huth } 1590fcf5ef2aSThomas Huth break; 1591fcf5ef2aSThomas Huth case 3: 1592fcf5ef2aSThomas Huth if (!ctx->pr) { 1593fcf5ef2aSThomas Huth /* Set process priority to high */ 1594fcf5ef2aSThomas Huth prio = 6; 1595fcf5ef2aSThomas Huth } 1596fcf5ef2aSThomas Huth break; 1597fcf5ef2aSThomas Huth case 7: 1598fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1599fcf5ef2aSThomas Huth /* Set process priority to very high */ 1600fcf5ef2aSThomas Huth prio = 7; 1601fcf5ef2aSThomas Huth } 1602fcf5ef2aSThomas Huth break; 1603fcf5ef2aSThomas Huth #endif 1604fcf5ef2aSThomas Huth default: 1605fcf5ef2aSThomas Huth break; 1606fcf5ef2aSThomas Huth } 1607fcf5ef2aSThomas Huth if (prio) { 1608fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1609fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1610fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1611fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1612fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1613fcf5ef2aSThomas Huth tcg_temp_free(t0); 1614fcf5ef2aSThomas Huth } 1615fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1616fcf5ef2aSThomas Huth /* Pause out of TCG otherwise spin loops with smt_low eat too much 1617fcf5ef2aSThomas Huth * CPU and the kernel hangs. This applies to all encodings other 1618fcf5ef2aSThomas Huth * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1619fcf5ef2aSThomas Huth * and all currently undefined. 1620fcf5ef2aSThomas Huth */ 1621fcf5ef2aSThomas Huth gen_pause(ctx); 1622fcf5ef2aSThomas Huth #endif 1623fcf5ef2aSThomas Huth #endif 1624fcf5ef2aSThomas Huth } 1625fcf5ef2aSThomas Huth } 1626fcf5ef2aSThomas Huth /* orc & orc. */ 1627fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1628fcf5ef2aSThomas Huth 1629fcf5ef2aSThomas Huth /* xor & xor. */ 1630fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1631fcf5ef2aSThomas Huth { 1632fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1633fcf5ef2aSThomas Huth if (rS(ctx->opcode) != rB(ctx->opcode)) 1634fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1635fcf5ef2aSThomas Huth else 1636fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1637fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1638fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1639fcf5ef2aSThomas Huth } 1640fcf5ef2aSThomas Huth 1641fcf5ef2aSThomas Huth /* ori */ 1642fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1643fcf5ef2aSThomas Huth { 1644fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1645fcf5ef2aSThomas Huth 1646fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1647fcf5ef2aSThomas Huth return; 1648fcf5ef2aSThomas Huth } 1649fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1650fcf5ef2aSThomas Huth } 1651fcf5ef2aSThomas Huth 1652fcf5ef2aSThomas Huth /* oris */ 1653fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1654fcf5ef2aSThomas Huth { 1655fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1656fcf5ef2aSThomas Huth 1657fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1658fcf5ef2aSThomas Huth /* NOP */ 1659fcf5ef2aSThomas Huth return; 1660fcf5ef2aSThomas Huth } 1661fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1662fcf5ef2aSThomas Huth } 1663fcf5ef2aSThomas Huth 1664fcf5ef2aSThomas Huth /* xori */ 1665fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1666fcf5ef2aSThomas Huth { 1667fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1668fcf5ef2aSThomas Huth 1669fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1670fcf5ef2aSThomas Huth /* NOP */ 1671fcf5ef2aSThomas Huth return; 1672fcf5ef2aSThomas Huth } 1673fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1674fcf5ef2aSThomas Huth } 1675fcf5ef2aSThomas Huth 1676fcf5ef2aSThomas Huth /* xoris */ 1677fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1678fcf5ef2aSThomas Huth { 1679fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1680fcf5ef2aSThomas Huth 1681fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1682fcf5ef2aSThomas Huth /* NOP */ 1683fcf5ef2aSThomas Huth return; 1684fcf5ef2aSThomas Huth } 1685fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1686fcf5ef2aSThomas Huth } 1687fcf5ef2aSThomas Huth 1688fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1689fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1690fcf5ef2aSThomas Huth { 1691fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1692fcf5ef2aSThomas Huth } 1693fcf5ef2aSThomas Huth 1694fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1695fcf5ef2aSThomas Huth { 169679770002SRichard Henderson #if defined(TARGET_PPC64) 1697fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 169879770002SRichard Henderson #else 169979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 170079770002SRichard Henderson #endif 1701fcf5ef2aSThomas Huth } 1702fcf5ef2aSThomas Huth 1703fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1704fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1705fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1706fcf5ef2aSThomas Huth { 170779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1708fcf5ef2aSThomas Huth } 1709fcf5ef2aSThomas Huth #endif 1710fcf5ef2aSThomas Huth 1711fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1712fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1713fcf5ef2aSThomas Huth { 1714fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1715fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1716fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1717fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1718fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1719fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1720fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1721fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1722fcf5ef2aSThomas Huth tcg_temp_free(t0); 1723fcf5ef2aSThomas Huth } 1724fcf5ef2aSThomas Huth 1725fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1726fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1727fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1728fcf5ef2aSThomas Huth { 1729fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1730fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1731fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1732fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1733fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1734fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1735fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1736fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1737fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1738fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1739fcf5ef2aSThomas Huth tcg_temp_free(t0); 1740fcf5ef2aSThomas Huth } 1741fcf5ef2aSThomas Huth #endif 1742fcf5ef2aSThomas Huth 1743fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1744fcf5ef2aSThomas Huth /* bpermd */ 1745fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1746fcf5ef2aSThomas Huth { 1747fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1748fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1749fcf5ef2aSThomas Huth } 1750fcf5ef2aSThomas Huth #endif 1751fcf5ef2aSThomas Huth 1752fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1753fcf5ef2aSThomas Huth /* extsw & extsw. */ 1754fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1755fcf5ef2aSThomas Huth 1756fcf5ef2aSThomas Huth /* cntlzd */ 1757fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1758fcf5ef2aSThomas Huth { 17599b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1760fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1761fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1762fcf5ef2aSThomas Huth } 1763fcf5ef2aSThomas Huth 1764fcf5ef2aSThomas Huth /* cnttzd */ 1765fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1766fcf5ef2aSThomas Huth { 17679b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1768fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1769fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1770fcf5ef2aSThomas Huth } 1771fcf5ef2aSThomas Huth } 1772fcf5ef2aSThomas Huth 1773fcf5ef2aSThomas Huth /* darn */ 1774fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1775fcf5ef2aSThomas Huth { 1776fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1777fcf5ef2aSThomas Huth 1778fcf5ef2aSThomas Huth if (l == 0) { 1779fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1780fcf5ef2aSThomas Huth } else if (l <= 2) { 1781fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1782fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1783fcf5ef2aSThomas Huth } else { 1784fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1785fcf5ef2aSThomas Huth } 1786fcf5ef2aSThomas Huth } 1787fcf5ef2aSThomas Huth #endif 1788fcf5ef2aSThomas Huth 1789fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1790fcf5ef2aSThomas Huth 1791fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1792fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1793fcf5ef2aSThomas Huth { 1794fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1795fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1796fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1797fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1798fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1799fcf5ef2aSThomas Huth 1800fcf5ef2aSThomas Huth if (sh == (31-me) && mb <= me) { 1801fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1802fcf5ef2aSThomas Huth } else { 1803fcf5ef2aSThomas Huth target_ulong mask; 1804fcf5ef2aSThomas Huth TCGv t1; 1805fcf5ef2aSThomas Huth 1806fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1807fcf5ef2aSThomas Huth mb += 32; 1808fcf5ef2aSThomas Huth me += 32; 1809fcf5ef2aSThomas Huth #endif 1810fcf5ef2aSThomas Huth mask = MASK(mb, me); 1811fcf5ef2aSThomas Huth 1812fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1813fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1814fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1815fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1816fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1817fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1818fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1819fcf5ef2aSThomas Huth } else { 1820fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1821fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1822fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1823fcf5ef2aSThomas Huth #else 1824fcf5ef2aSThomas Huth g_assert_not_reached(); 1825fcf5ef2aSThomas Huth #endif 1826fcf5ef2aSThomas Huth } 1827fcf5ef2aSThomas Huth 1828fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1829fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1830fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1831fcf5ef2aSThomas Huth tcg_temp_free(t1); 1832fcf5ef2aSThomas Huth } 1833fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1834fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1835fcf5ef2aSThomas Huth } 1836fcf5ef2aSThomas Huth } 1837fcf5ef2aSThomas Huth 1838fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1839fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1840fcf5ef2aSThomas Huth { 1841fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1842fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 18437b4d326fSRichard Henderson int sh = SH(ctx->opcode); 18447b4d326fSRichard Henderson int mb = MB(ctx->opcode); 18457b4d326fSRichard Henderson int me = ME(ctx->opcode); 18467b4d326fSRichard Henderson int len = me - mb + 1; 18477b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1848fcf5ef2aSThomas Huth 18497b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 18507b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 18517b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 18527b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1853fcf5ef2aSThomas Huth } else { 1854fcf5ef2aSThomas Huth target_ulong mask; 1855fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1856fcf5ef2aSThomas Huth mb += 32; 1857fcf5ef2aSThomas Huth me += 32; 1858fcf5ef2aSThomas Huth #endif 1859fcf5ef2aSThomas Huth mask = MASK(mb, me); 18607b4d326fSRichard Henderson if (sh == 0) { 18617b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 18627b4d326fSRichard Henderson } else if (mask <= 0xffffffffu) { 1863fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1864fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1865fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1866fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1867fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1868fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1869fcf5ef2aSThomas Huth } else { 1870fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1871fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1872fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1873fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1874fcf5ef2aSThomas Huth #else 1875fcf5ef2aSThomas Huth g_assert_not_reached(); 1876fcf5ef2aSThomas Huth #endif 1877fcf5ef2aSThomas Huth } 1878fcf5ef2aSThomas Huth } 1879fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1880fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1881fcf5ef2aSThomas Huth } 1882fcf5ef2aSThomas Huth } 1883fcf5ef2aSThomas Huth 1884fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1885fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1886fcf5ef2aSThomas Huth { 1887fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1888fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1889fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1890fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1891fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1892fcf5ef2aSThomas Huth target_ulong mask; 1893fcf5ef2aSThomas Huth 1894fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1895fcf5ef2aSThomas Huth mb += 32; 1896fcf5ef2aSThomas Huth me += 32; 1897fcf5ef2aSThomas Huth #endif 1898fcf5ef2aSThomas Huth mask = MASK(mb, me); 1899fcf5ef2aSThomas Huth 1900fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1901fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1902fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1903fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1904fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1905fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1906fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1907fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1908fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1909fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1910fcf5ef2aSThomas Huth } else { 1911fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1912fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1913fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1914fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1915fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1916fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1917fcf5ef2aSThomas Huth #else 1918fcf5ef2aSThomas Huth g_assert_not_reached(); 1919fcf5ef2aSThomas Huth #endif 1920fcf5ef2aSThomas Huth } 1921fcf5ef2aSThomas Huth 1922fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 1923fcf5ef2aSThomas Huth 1924fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1925fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1926fcf5ef2aSThomas Huth } 1927fcf5ef2aSThomas Huth } 1928fcf5ef2aSThomas Huth 1929fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1930fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 1931fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1932fcf5ef2aSThomas Huth { \ 1933fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 1934fcf5ef2aSThomas Huth } \ 1935fcf5ef2aSThomas Huth \ 1936fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1937fcf5ef2aSThomas Huth { \ 1938fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 1939fcf5ef2aSThomas Huth } 1940fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 1941fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1942fcf5ef2aSThomas Huth { \ 1943fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 1944fcf5ef2aSThomas Huth } \ 1945fcf5ef2aSThomas Huth \ 1946fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1947fcf5ef2aSThomas Huth { \ 1948fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 1949fcf5ef2aSThomas Huth } \ 1950fcf5ef2aSThomas Huth \ 1951fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 1952fcf5ef2aSThomas Huth { \ 1953fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 1954fcf5ef2aSThomas Huth } \ 1955fcf5ef2aSThomas Huth \ 1956fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 1957fcf5ef2aSThomas Huth { \ 1958fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 1959fcf5ef2aSThomas Huth } 1960fcf5ef2aSThomas Huth 1961fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 1962fcf5ef2aSThomas Huth { 1963fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1964fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 19657b4d326fSRichard Henderson int len = me - mb + 1; 19667b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 1967fcf5ef2aSThomas Huth 19687b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 19697b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 19707b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 19717b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1972fcf5ef2aSThomas Huth } else { 1973fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 1974fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 1975fcf5ef2aSThomas Huth } 1976fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1977fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1978fcf5ef2aSThomas Huth } 1979fcf5ef2aSThomas Huth } 1980fcf5ef2aSThomas Huth 1981fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 1982fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 1983fcf5ef2aSThomas Huth { 1984fcf5ef2aSThomas Huth uint32_t sh, mb; 1985fcf5ef2aSThomas Huth 1986fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 1987fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 1988fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 1989fcf5ef2aSThomas Huth } 1990fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 1991fcf5ef2aSThomas Huth 1992fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 1993fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 1994fcf5ef2aSThomas Huth { 1995fcf5ef2aSThomas Huth uint32_t sh, me; 1996fcf5ef2aSThomas Huth 1997fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 1998fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 1999fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2000fcf5ef2aSThomas Huth } 2001fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2002fcf5ef2aSThomas Huth 2003fcf5ef2aSThomas Huth /* rldic - rldic. */ 2004fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2005fcf5ef2aSThomas Huth { 2006fcf5ef2aSThomas Huth uint32_t sh, mb; 2007fcf5ef2aSThomas Huth 2008fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2009fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2010fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2011fcf5ef2aSThomas Huth } 2012fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2013fcf5ef2aSThomas Huth 2014fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2015fcf5ef2aSThomas Huth { 2016fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2017fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2018fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2019fcf5ef2aSThomas Huth TCGv t0; 2020fcf5ef2aSThomas Huth 2021fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2022fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2023fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2024fcf5ef2aSThomas Huth tcg_temp_free(t0); 2025fcf5ef2aSThomas Huth 2026fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2027fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2028fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2029fcf5ef2aSThomas Huth } 2030fcf5ef2aSThomas Huth } 2031fcf5ef2aSThomas Huth 2032fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2033fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2034fcf5ef2aSThomas Huth { 2035fcf5ef2aSThomas Huth uint32_t mb; 2036fcf5ef2aSThomas Huth 2037fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2038fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2039fcf5ef2aSThomas Huth } 2040fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2041fcf5ef2aSThomas Huth 2042fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2043fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2044fcf5ef2aSThomas Huth { 2045fcf5ef2aSThomas Huth uint32_t me; 2046fcf5ef2aSThomas Huth 2047fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2048fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2049fcf5ef2aSThomas Huth } 2050fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2051fcf5ef2aSThomas Huth 2052fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2053fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2054fcf5ef2aSThomas Huth { 2055fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2056fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2057fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2058fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2059fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2060fcf5ef2aSThomas Huth 2061fcf5ef2aSThomas Huth if (mb <= me) { 2062fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2063fcf5ef2aSThomas Huth } else { 2064fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2065fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2066fcf5ef2aSThomas Huth 2067fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2068fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2069fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2070fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2071fcf5ef2aSThomas Huth tcg_temp_free(t1); 2072fcf5ef2aSThomas Huth } 2073fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2074fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2075fcf5ef2aSThomas Huth } 2076fcf5ef2aSThomas Huth } 2077fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2078fcf5ef2aSThomas Huth #endif 2079fcf5ef2aSThomas Huth 2080fcf5ef2aSThomas Huth /*** Integer shift ***/ 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth /* slw & slw. */ 2083fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2084fcf5ef2aSThomas Huth { 2085fcf5ef2aSThomas Huth TCGv t0, t1; 2086fcf5ef2aSThomas Huth 2087fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2088fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2089fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2090fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2091fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2092fcf5ef2aSThomas Huth #else 2093fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2094fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2095fcf5ef2aSThomas Huth #endif 2096fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2097fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2098fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2099fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2100fcf5ef2aSThomas Huth tcg_temp_free(t1); 2101fcf5ef2aSThomas Huth tcg_temp_free(t0); 2102fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2103fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2104fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2105fcf5ef2aSThomas Huth } 2106fcf5ef2aSThomas Huth 2107fcf5ef2aSThomas Huth /* sraw & sraw. */ 2108fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2109fcf5ef2aSThomas Huth { 2110fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2111fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2112fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2113fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2114fcf5ef2aSThomas Huth } 2115fcf5ef2aSThomas Huth 2116fcf5ef2aSThomas Huth /* srawi & srawi. */ 2117fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2118fcf5ef2aSThomas Huth { 2119fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2120fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2121fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2122fcf5ef2aSThomas Huth if (sh == 0) { 2123fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2124fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2125fcf5ef2aSThomas Huth } else { 2126fcf5ef2aSThomas Huth TCGv t0; 2127fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2128fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2129fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2130fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2131fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2132fcf5ef2aSThomas Huth tcg_temp_free(t0); 2133fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2134fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2135fcf5ef2aSThomas Huth } 2136fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2137fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2138fcf5ef2aSThomas Huth } 2139fcf5ef2aSThomas Huth } 2140fcf5ef2aSThomas Huth 2141fcf5ef2aSThomas Huth /* srw & srw. */ 2142fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2143fcf5ef2aSThomas Huth { 2144fcf5ef2aSThomas Huth TCGv t0, t1; 2145fcf5ef2aSThomas Huth 2146fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2147fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2148fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2149fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2150fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2151fcf5ef2aSThomas Huth #else 2152fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2153fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2154fcf5ef2aSThomas Huth #endif 2155fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2156fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2157fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2158fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2159fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2160fcf5ef2aSThomas Huth tcg_temp_free(t1); 2161fcf5ef2aSThomas Huth tcg_temp_free(t0); 2162fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2163fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2164fcf5ef2aSThomas Huth } 2165fcf5ef2aSThomas Huth 2166fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2167fcf5ef2aSThomas Huth /* sld & sld. */ 2168fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2169fcf5ef2aSThomas Huth { 2170fcf5ef2aSThomas Huth TCGv t0, t1; 2171fcf5ef2aSThomas Huth 2172fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2173fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2174fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2175fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2176fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2177fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2178fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2179fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2180fcf5ef2aSThomas Huth tcg_temp_free(t1); 2181fcf5ef2aSThomas Huth tcg_temp_free(t0); 2182fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2183fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2184fcf5ef2aSThomas Huth } 2185fcf5ef2aSThomas Huth 2186fcf5ef2aSThomas Huth /* srad & srad. */ 2187fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2188fcf5ef2aSThomas Huth { 2189fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2190fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2191fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2192fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2193fcf5ef2aSThomas Huth } 2194fcf5ef2aSThomas Huth /* sradi & sradi. */ 2195fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2196fcf5ef2aSThomas Huth { 2197fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2198fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2199fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2200fcf5ef2aSThomas Huth if (sh == 0) { 2201fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2202fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2203fcf5ef2aSThomas Huth } else { 2204fcf5ef2aSThomas Huth TCGv t0; 2205fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2206fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2207fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2208fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2209fcf5ef2aSThomas Huth tcg_temp_free(t0); 2210fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2211fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2212fcf5ef2aSThomas Huth } 2213fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2214fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2215fcf5ef2aSThomas Huth } 2216fcf5ef2aSThomas Huth } 2217fcf5ef2aSThomas Huth 2218fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2219fcf5ef2aSThomas Huth { 2220fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2221fcf5ef2aSThomas Huth } 2222fcf5ef2aSThomas Huth 2223fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2224fcf5ef2aSThomas Huth { 2225fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2226fcf5ef2aSThomas Huth } 2227fcf5ef2aSThomas Huth 2228fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2229fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2230fcf5ef2aSThomas Huth { 2231fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2232fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2233fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2234fcf5ef2aSThomas Huth 2235fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2236fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2237fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2238fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2239fcf5ef2aSThomas Huth } 2240fcf5ef2aSThomas Huth } 2241fcf5ef2aSThomas Huth 2242fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2243fcf5ef2aSThomas Huth { 2244fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2245fcf5ef2aSThomas Huth } 2246fcf5ef2aSThomas Huth 2247fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2248fcf5ef2aSThomas Huth { 2249fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2250fcf5ef2aSThomas Huth } 2251fcf5ef2aSThomas Huth 2252fcf5ef2aSThomas Huth /* srd & srd. */ 2253fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2254fcf5ef2aSThomas Huth { 2255fcf5ef2aSThomas Huth TCGv t0, t1; 2256fcf5ef2aSThomas Huth 2257fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2258fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2259fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2260fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2261fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2262fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2263fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2264fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2265fcf5ef2aSThomas Huth tcg_temp_free(t1); 2266fcf5ef2aSThomas Huth tcg_temp_free(t0); 2267fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2268fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2269fcf5ef2aSThomas Huth } 2270fcf5ef2aSThomas Huth #endif 2271fcf5ef2aSThomas Huth 2272fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2273fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2274fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2275fcf5ef2aSThomas Huth target_long maskl) 2276fcf5ef2aSThomas Huth { 2277fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2278fcf5ef2aSThomas Huth 2279fcf5ef2aSThomas Huth simm &= ~maskl; 2280fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2281fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2282fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2283fcf5ef2aSThomas Huth } 2284fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2285fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2286fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2287fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2288fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2289fcf5ef2aSThomas Huth } 2290fcf5ef2aSThomas Huth } else { 2291fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2292fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2293fcf5ef2aSThomas Huth } else { 2294fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2295fcf5ef2aSThomas Huth } 2296fcf5ef2aSThomas Huth } 2297fcf5ef2aSThomas Huth } 2298fcf5ef2aSThomas Huth 2299fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2300fcf5ef2aSThomas Huth { 2301fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2302fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2303fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2304fcf5ef2aSThomas Huth } else { 2305fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2306fcf5ef2aSThomas Huth } 2307fcf5ef2aSThomas Huth } else { 2308fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2309fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2310fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2311fcf5ef2aSThomas Huth } 2312fcf5ef2aSThomas Huth } 2313fcf5ef2aSThomas Huth } 2314fcf5ef2aSThomas Huth 2315fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2316fcf5ef2aSThomas Huth { 2317fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2318fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2319fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2320fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2321fcf5ef2aSThomas Huth } else { 2322fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2323fcf5ef2aSThomas Huth } 2324fcf5ef2aSThomas Huth } 2325fcf5ef2aSThomas Huth 2326fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2327fcf5ef2aSThomas Huth target_long val) 2328fcf5ef2aSThomas Huth { 2329fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2330fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2331fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2332fcf5ef2aSThomas Huth } 2333fcf5ef2aSThomas Huth } 2334fcf5ef2aSThomas Huth 2335fcf5ef2aSThomas Huth static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) 2336fcf5ef2aSThomas Huth { 2337fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 2338fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2339fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2340fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, EA, mask); 2341fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 2342fcf5ef2aSThomas Huth t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); 2343fcf5ef2aSThomas Huth t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); 2344fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 2345fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t1, t2); 2346fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2347fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2348fcf5ef2aSThomas Huth gen_set_label(l1); 2349fcf5ef2aSThomas Huth tcg_temp_free(t0); 2350fcf5ef2aSThomas Huth } 2351fcf5ef2aSThomas Huth 2352fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2353fcf5ef2aSThomas Huth { 2354fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2355fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2356fcf5ef2aSThomas Huth } 2357fcf5ef2aSThomas Huth 2358fcf5ef2aSThomas Huth /*** Integer load ***/ 2359fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2360fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2361fcf5ef2aSThomas Huth 2362fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2363fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2364fcf5ef2aSThomas Huth TCGv val, \ 2365fcf5ef2aSThomas Huth TCGv addr) \ 2366fcf5ef2aSThomas Huth { \ 2367fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2368fcf5ef2aSThomas Huth } 2369fcf5ef2aSThomas Huth 2370fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2371fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2372fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2373fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2374fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2375fcf5ef2aSThomas Huth 2376fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2377fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2378fcf5ef2aSThomas Huth 2379fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2380fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2381fcf5ef2aSThomas Huth TCGv_i64 val, \ 2382fcf5ef2aSThomas Huth TCGv addr) \ 2383fcf5ef2aSThomas Huth { \ 2384fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2385fcf5ef2aSThomas Huth } 2386fcf5ef2aSThomas Huth 2387fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2388fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2389fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2390fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2391fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2392fcf5ef2aSThomas Huth 2393fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2394fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2395fcf5ef2aSThomas Huth #endif 2396fcf5ef2aSThomas Huth 2397fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2398fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2399fcf5ef2aSThomas Huth TCGv val, \ 2400fcf5ef2aSThomas Huth TCGv addr) \ 2401fcf5ef2aSThomas Huth { \ 2402fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2403fcf5ef2aSThomas Huth } 2404fcf5ef2aSThomas Huth 2405fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2406fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2407fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2408fcf5ef2aSThomas Huth 2409fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2410fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2411fcf5ef2aSThomas Huth 2412fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2413fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2414fcf5ef2aSThomas Huth TCGv_i64 val, \ 2415fcf5ef2aSThomas Huth TCGv addr) \ 2416fcf5ef2aSThomas Huth { \ 2417fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2418fcf5ef2aSThomas Huth } 2419fcf5ef2aSThomas Huth 2420fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2421fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2422fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2423fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2424fcf5ef2aSThomas Huth 2425fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2426fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2427fcf5ef2aSThomas Huth #endif 2428fcf5ef2aSThomas Huth 2429fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2430fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2431fcf5ef2aSThomas Huth { \ 2432fcf5ef2aSThomas Huth TCGv EA; \ 2433fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2434fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2435fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2436fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2437fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2438fcf5ef2aSThomas Huth } 2439fcf5ef2aSThomas Huth 2440fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2441fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2442fcf5ef2aSThomas Huth { \ 2443fcf5ef2aSThomas Huth TCGv EA; \ 2444fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2445fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2446fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2447fcf5ef2aSThomas Huth return; \ 2448fcf5ef2aSThomas Huth } \ 2449fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2450fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2451fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2452fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2453fcf5ef2aSThomas Huth else \ 2454fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2455fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2456fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2457fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2458fcf5ef2aSThomas Huth } 2459fcf5ef2aSThomas Huth 2460fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2461fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2462fcf5ef2aSThomas Huth { \ 2463fcf5ef2aSThomas Huth TCGv EA; \ 2464fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2465fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2466fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2467fcf5ef2aSThomas Huth return; \ 2468fcf5ef2aSThomas Huth } \ 2469fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2470fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2471fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2472fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2473fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2474fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2475fcf5ef2aSThomas Huth } 2476fcf5ef2aSThomas Huth 2477fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2478fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2479fcf5ef2aSThomas Huth { \ 2480fcf5ef2aSThomas Huth TCGv EA; \ 2481fcf5ef2aSThomas Huth chk; \ 2482fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2483fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2484fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2485fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2486fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2487fcf5ef2aSThomas Huth } 2488fcf5ef2aSThomas Huth 2489fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2490fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2491fcf5ef2aSThomas Huth 2492fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2493fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2494fcf5ef2aSThomas Huth 2495fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2496fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2497fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2498fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2499fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2500fcf5ef2aSThomas Huth 2501fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2502fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2503fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2504fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2505fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2506fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2507fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2508fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2509fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2510fcf5ef2aSThomas Huth /* lwaux */ 2511fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2512fcf5ef2aSThomas Huth /* lwax */ 2513fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2514fcf5ef2aSThomas Huth /* ldux */ 2515fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2516fcf5ef2aSThomas Huth /* ldx */ 2517fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2518fcf5ef2aSThomas Huth 2519fcf5ef2aSThomas Huth /* CI load/store variants */ 2520fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2521fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2522fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2523fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2524fcf5ef2aSThomas Huth 2525fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2526fcf5ef2aSThomas Huth { 2527fcf5ef2aSThomas Huth TCGv EA; 2528fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2529fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2530fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2531fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2532fcf5ef2aSThomas Huth return; 2533fcf5ef2aSThomas Huth } 2534fcf5ef2aSThomas Huth } 2535fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2536fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2537fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2538fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2539fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2540fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2541fcf5ef2aSThomas Huth } else { 2542fcf5ef2aSThomas Huth /* ld - ldu */ 2543fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2544fcf5ef2aSThomas Huth } 2545fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2546fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2547fcf5ef2aSThomas Huth tcg_temp_free(EA); 2548fcf5ef2aSThomas Huth } 2549fcf5ef2aSThomas Huth 2550fcf5ef2aSThomas Huth /* lq */ 2551fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2552fcf5ef2aSThomas Huth { 2553fcf5ef2aSThomas Huth int ra, rd; 2554fcf5ef2aSThomas Huth TCGv EA; 2555fcf5ef2aSThomas Huth 2556fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2557fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2558fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2559fcf5ef2aSThomas Huth 2560fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2561fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2562fcf5ef2aSThomas Huth return; 2563fcf5ef2aSThomas Huth } 2564fcf5ef2aSThomas Huth 2565fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2566fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2567fcf5ef2aSThomas Huth return; 2568fcf5ef2aSThomas Huth } 2569fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2570fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2571fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2572fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2573fcf5ef2aSThomas Huth return; 2574fcf5ef2aSThomas Huth } 2575fcf5ef2aSThomas Huth 2576fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2577fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2578fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2579fcf5ef2aSThomas Huth 2580fcf5ef2aSThomas Huth /* We only need to swap high and low halves. gen_qemu_ld64_i64 does 2581fcf5ef2aSThomas Huth necessary 64-bit byteswap already. */ 2582fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 2583fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2584fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2585fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2586fcf5ef2aSThomas Huth } else { 2587fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2588fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2589fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2590fcf5ef2aSThomas Huth } 2591fcf5ef2aSThomas Huth tcg_temp_free(EA); 2592fcf5ef2aSThomas Huth } 2593fcf5ef2aSThomas Huth #endif 2594fcf5ef2aSThomas Huth 2595fcf5ef2aSThomas Huth /*** Integer store ***/ 2596fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2597fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2598fcf5ef2aSThomas Huth { \ 2599fcf5ef2aSThomas Huth TCGv EA; \ 2600fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2601fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2602fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2603fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2604fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2605fcf5ef2aSThomas Huth } 2606fcf5ef2aSThomas Huth 2607fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2608fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2609fcf5ef2aSThomas Huth { \ 2610fcf5ef2aSThomas Huth TCGv EA; \ 2611fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2612fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2613fcf5ef2aSThomas Huth return; \ 2614fcf5ef2aSThomas Huth } \ 2615fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2616fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2617fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2618fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2619fcf5ef2aSThomas Huth else \ 2620fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2621fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2622fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2623fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2624fcf5ef2aSThomas Huth } 2625fcf5ef2aSThomas Huth 2626fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2627fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2628fcf5ef2aSThomas Huth { \ 2629fcf5ef2aSThomas Huth TCGv EA; \ 2630fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2631fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2632fcf5ef2aSThomas Huth return; \ 2633fcf5ef2aSThomas Huth } \ 2634fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2635fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2636fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2637fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2638fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2639fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2640fcf5ef2aSThomas Huth } 2641fcf5ef2aSThomas Huth 2642fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2643fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2644fcf5ef2aSThomas Huth { \ 2645fcf5ef2aSThomas Huth TCGv EA; \ 2646fcf5ef2aSThomas Huth chk; \ 2647fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2648fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2649fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2650fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2651fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2652fcf5ef2aSThomas Huth } 2653fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2654fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2655fcf5ef2aSThomas Huth 2656fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2657fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2658fcf5ef2aSThomas Huth 2659fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2660fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2661fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2662fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2663fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2664fcf5ef2aSThomas Huth 2665fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2666fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2667fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2668fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2669fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2670fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2671fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2672fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2673fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2674fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2675fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2676fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2677fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2678fcf5ef2aSThomas Huth 2679fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2680fcf5ef2aSThomas Huth { 2681fcf5ef2aSThomas Huth int rs; 2682fcf5ef2aSThomas Huth TCGv EA; 2683fcf5ef2aSThomas Huth 2684fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2685fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2686fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2687fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2688fcf5ef2aSThomas Huth 2689fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2690fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2691fcf5ef2aSThomas Huth } 2692fcf5ef2aSThomas Huth 2693fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2694fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2695fcf5ef2aSThomas Huth return; 2696fcf5ef2aSThomas Huth } 2697fcf5ef2aSThomas Huth 2698fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2699fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2700fcf5ef2aSThomas Huth return; 2701fcf5ef2aSThomas Huth } 2702fcf5ef2aSThomas Huth 2703fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2704fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2705fcf5ef2aSThomas Huth return; 2706fcf5ef2aSThomas Huth } 2707fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2708fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2709fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2710fcf5ef2aSThomas Huth 2711fcf5ef2aSThomas Huth /* We only need to swap high and low halves. gen_qemu_st64_i64 does 2712fcf5ef2aSThomas Huth necessary 64-bit byteswap already. */ 2713fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 2714fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2715fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2716fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2717fcf5ef2aSThomas Huth } else { 2718fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2719fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2720fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2721fcf5ef2aSThomas Huth } 2722fcf5ef2aSThomas Huth tcg_temp_free(EA); 2723fcf5ef2aSThomas Huth } else { 2724fcf5ef2aSThomas Huth /* std / stdu*/ 2725fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2726fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2727fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2728fcf5ef2aSThomas Huth return; 2729fcf5ef2aSThomas Huth } 2730fcf5ef2aSThomas Huth } 2731fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2732fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2733fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2734fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2735fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2736fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2737fcf5ef2aSThomas Huth tcg_temp_free(EA); 2738fcf5ef2aSThomas Huth } 2739fcf5ef2aSThomas Huth } 2740fcf5ef2aSThomas Huth #endif 2741fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2742fcf5ef2aSThomas Huth 2743fcf5ef2aSThomas Huth /* lhbrx */ 2744fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2745fcf5ef2aSThomas Huth 2746fcf5ef2aSThomas Huth /* lwbrx */ 2747fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2748fcf5ef2aSThomas Huth 2749fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2750fcf5ef2aSThomas Huth /* ldbrx */ 2751fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2752fcf5ef2aSThomas Huth /* stdbrx */ 2753fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2754fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2755fcf5ef2aSThomas Huth 2756fcf5ef2aSThomas Huth /* sthbrx */ 2757fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2758fcf5ef2aSThomas Huth /* stwbrx */ 2759fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2760fcf5ef2aSThomas Huth 2761fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2762fcf5ef2aSThomas Huth 2763fcf5ef2aSThomas Huth /* lmw */ 2764fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2765fcf5ef2aSThomas Huth { 2766fcf5ef2aSThomas Huth TCGv t0; 2767fcf5ef2aSThomas Huth TCGv_i32 t1; 2768fcf5ef2aSThomas Huth 2769fcf5ef2aSThomas Huth if (ctx->le_mode) { 2770fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2771fcf5ef2aSThomas Huth return; 2772fcf5ef2aSThomas Huth } 2773fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2774fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2775fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2776fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2777fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2778fcf5ef2aSThomas Huth tcg_temp_free(t0); 2779fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2780fcf5ef2aSThomas Huth } 2781fcf5ef2aSThomas Huth 2782fcf5ef2aSThomas Huth /* stmw */ 2783fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2784fcf5ef2aSThomas Huth { 2785fcf5ef2aSThomas Huth TCGv t0; 2786fcf5ef2aSThomas Huth TCGv_i32 t1; 2787fcf5ef2aSThomas Huth 2788fcf5ef2aSThomas Huth if (ctx->le_mode) { 2789fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2790fcf5ef2aSThomas Huth return; 2791fcf5ef2aSThomas Huth } 2792fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2793fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2794fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2795fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2796fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2797fcf5ef2aSThomas Huth tcg_temp_free(t0); 2798fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2799fcf5ef2aSThomas Huth } 2800fcf5ef2aSThomas Huth 2801fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2802fcf5ef2aSThomas Huth 2803fcf5ef2aSThomas Huth /* lswi */ 2804fcf5ef2aSThomas Huth /* PowerPC32 specification says we must generate an exception if 2805fcf5ef2aSThomas Huth * rA is in the range of registers to be loaded. 2806fcf5ef2aSThomas Huth * In an other hand, IBM says this is valid, but rA won't be loaded. 2807fcf5ef2aSThomas Huth * For now, I'll follow the spec... 2808fcf5ef2aSThomas Huth */ 2809fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2810fcf5ef2aSThomas Huth { 2811fcf5ef2aSThomas Huth TCGv t0; 2812fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2813fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2814fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2815fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2816fcf5ef2aSThomas Huth int nr; 2817fcf5ef2aSThomas Huth 2818fcf5ef2aSThomas Huth if (ctx->le_mode) { 2819fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2820fcf5ef2aSThomas Huth return; 2821fcf5ef2aSThomas Huth } 2822fcf5ef2aSThomas Huth if (nb == 0) 2823fcf5ef2aSThomas Huth nb = 32; 2824fcf5ef2aSThomas Huth nr = (nb + 3) / 4; 2825fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2826fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2827fcf5ef2aSThomas Huth return; 2828fcf5ef2aSThomas Huth } 2829fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2830fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2831fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2832fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2833fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 2834fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 2835fcf5ef2aSThomas Huth tcg_temp_free(t0); 2836fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2837fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2838fcf5ef2aSThomas Huth } 2839fcf5ef2aSThomas Huth 2840fcf5ef2aSThomas Huth /* lswx */ 2841fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 2842fcf5ef2aSThomas Huth { 2843fcf5ef2aSThomas Huth TCGv t0; 2844fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 2845fcf5ef2aSThomas Huth 2846fcf5ef2aSThomas Huth if (ctx->le_mode) { 2847fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2848fcf5ef2aSThomas Huth return; 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2851fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2852fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2853fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2854fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 2855fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 2856fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2857fcf5ef2aSThomas Huth tcg_temp_free(t0); 2858fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2859fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2860fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2861fcf5ef2aSThomas Huth } 2862fcf5ef2aSThomas Huth 2863fcf5ef2aSThomas Huth /* stswi */ 2864fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 2865fcf5ef2aSThomas Huth { 2866fcf5ef2aSThomas Huth TCGv t0; 2867fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2868fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2869fcf5ef2aSThomas Huth 2870fcf5ef2aSThomas Huth if (ctx->le_mode) { 2871fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2872fcf5ef2aSThomas Huth return; 2873fcf5ef2aSThomas Huth } 2874fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2875fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2876fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2877fcf5ef2aSThomas Huth if (nb == 0) 2878fcf5ef2aSThomas Huth nb = 32; 2879fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2880fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2881fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2882fcf5ef2aSThomas Huth tcg_temp_free(t0); 2883fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2884fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2885fcf5ef2aSThomas Huth } 2886fcf5ef2aSThomas Huth 2887fcf5ef2aSThomas Huth /* stswx */ 2888fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 2889fcf5ef2aSThomas Huth { 2890fcf5ef2aSThomas Huth TCGv t0; 2891fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2892fcf5ef2aSThomas Huth 2893fcf5ef2aSThomas Huth if (ctx->le_mode) { 2894fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2895fcf5ef2aSThomas Huth return; 2896fcf5ef2aSThomas Huth } 2897fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2898fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2899fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2900fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 2901fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 2902fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 2903fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2904fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2905fcf5ef2aSThomas Huth tcg_temp_free(t0); 2906fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2907fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2908fcf5ef2aSThomas Huth } 2909fcf5ef2aSThomas Huth 2910fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 2911fcf5ef2aSThomas Huth /* eieio */ 2912fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 2913fcf5ef2aSThomas Huth { 2914fcf5ef2aSThomas Huth } 2915fcf5ef2aSThomas Huth 2916fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2917fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2918fcf5ef2aSThomas Huth { 2919fcf5ef2aSThomas Huth TCGv_i32 t; 2920fcf5ef2aSThomas Huth TCGLabel *l; 2921fcf5ef2aSThomas Huth 2922fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 2923fcf5ef2aSThomas Huth return; 2924fcf5ef2aSThomas Huth } 2925fcf5ef2aSThomas Huth l = gen_new_label(); 2926fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 2927fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 2928fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 2929fcf5ef2aSThomas Huth if (global) { 2930fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 2931fcf5ef2aSThomas Huth } else { 2932fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 2933fcf5ef2aSThomas Huth } 2934fcf5ef2aSThomas Huth gen_set_label(l); 2935fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 2936fcf5ef2aSThomas Huth } 2937fcf5ef2aSThomas Huth #else 2938fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 2939fcf5ef2aSThomas Huth #endif 2940fcf5ef2aSThomas Huth 2941fcf5ef2aSThomas Huth /* isync */ 2942fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 2943fcf5ef2aSThomas Huth { 2944fcf5ef2aSThomas Huth /* 2945fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 2946fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 2947fcf5ef2aSThomas Huth */ 2948fcf5ef2aSThomas Huth if (!ctx->pr) { 2949fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 2950fcf5ef2aSThomas Huth } 2951fcf5ef2aSThomas Huth gen_stop_exception(ctx); 2952fcf5ef2aSThomas Huth } 2953fcf5ef2aSThomas Huth 2954fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 2955fcf5ef2aSThomas Huth 2956fcf5ef2aSThomas Huth #define LARX(name, memop) \ 2957fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 2958fcf5ef2aSThomas Huth { \ 2959fcf5ef2aSThomas Huth TCGv t0; \ 2960fcf5ef2aSThomas Huth TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ 2961fcf5ef2aSThomas Huth int len = MEMOP_GET_SIZE(memop); \ 2962fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); \ 2963fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); \ 2964fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); \ 2965fcf5ef2aSThomas Huth if ((len) > 1) { \ 2966fcf5ef2aSThomas Huth gen_check_align(ctx, t0, (len)-1); \ 2967fcf5ef2aSThomas Huth } \ 2968fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ 2969fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, t0); \ 2970fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ 2971fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2972fcf5ef2aSThomas Huth } 2973fcf5ef2aSThomas Huth 2974fcf5ef2aSThomas Huth /* lwarx */ 2975fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 2976fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 2977fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 2978fcf5ef2aSThomas Huth 2979a68a6146SBalamuruhan S #define LD_ATOMIC(name, memop, tp, op, eop) \ 2980a68a6146SBalamuruhan S static void gen_##name(DisasContext *ctx) \ 2981a68a6146SBalamuruhan S { \ 2982a68a6146SBalamuruhan S int len = MEMOP_GET_SIZE(memop); \ 2983a68a6146SBalamuruhan S uint32_t gpr_FC = FC(ctx->opcode); \ 2984a68a6146SBalamuruhan S TCGv EA = tcg_temp_local_new(); \ 2985a68a6146SBalamuruhan S TCGv_##tp t0, t1; \ 2986a68a6146SBalamuruhan S \ 2987a68a6146SBalamuruhan S gen_addr_register(ctx, EA); \ 2988a68a6146SBalamuruhan S if (len > 1) { \ 2989a68a6146SBalamuruhan S gen_check_align(ctx, EA, len - 1); \ 2990a68a6146SBalamuruhan S } \ 2991a68a6146SBalamuruhan S t0 = tcg_temp_new_##tp(); \ 2992a68a6146SBalamuruhan S t1 = tcg_temp_new_##tp(); \ 2993a68a6146SBalamuruhan S tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 2994a68a6146SBalamuruhan S \ 2995a68a6146SBalamuruhan S switch (gpr_FC) { \ 2996a68a6146SBalamuruhan S case 0: /* Fetch and add */ \ 2997a68a6146SBalamuruhan S tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 2998a68a6146SBalamuruhan S break; \ 2999a68a6146SBalamuruhan S case 1: /* Fetch and xor */ \ 3000a68a6146SBalamuruhan S tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3001a68a6146SBalamuruhan S break; \ 3002a68a6146SBalamuruhan S case 2: /* Fetch and or */ \ 3003a68a6146SBalamuruhan S tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3004a68a6146SBalamuruhan S break; \ 3005a68a6146SBalamuruhan S case 3: /* Fetch and 'and' */ \ 3006a68a6146SBalamuruhan S tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3007a68a6146SBalamuruhan S break; \ 3008a68a6146SBalamuruhan S case 8: /* Swap */ \ 3009a68a6146SBalamuruhan S tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3010a68a6146SBalamuruhan S break; \ 3011a68a6146SBalamuruhan S case 4: /* Fetch and max unsigned */ \ 3012a68a6146SBalamuruhan S case 5: /* Fetch and max signed */ \ 3013a68a6146SBalamuruhan S case 6: /* Fetch and min unsigned */ \ 3014a68a6146SBalamuruhan S case 7: /* Fetch and min signed */ \ 3015a68a6146SBalamuruhan S case 16: /* compare and swap not equal */ \ 3016a68a6146SBalamuruhan S case 24: /* Fetch and increment bounded */ \ 3017a68a6146SBalamuruhan S case 25: /* Fetch and increment equal */ \ 3018a68a6146SBalamuruhan S case 28: /* Fetch and decrement bounded */ \ 3019a68a6146SBalamuruhan S gen_invalid(ctx); \ 3020a68a6146SBalamuruhan S break; \ 3021a68a6146SBalamuruhan S default: \ 3022a68a6146SBalamuruhan S /* invoke data storage error handler */ \ 3023a68a6146SBalamuruhan S gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3024a68a6146SBalamuruhan S } \ 3025a68a6146SBalamuruhan S tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ 3026a68a6146SBalamuruhan S tcg_temp_free_##tp(t0); \ 3027a68a6146SBalamuruhan S tcg_temp_free_##tp(t1); \ 3028a68a6146SBalamuruhan S tcg_temp_free(EA); \ 3029a68a6146SBalamuruhan S } 3030a68a6146SBalamuruhan S 3031a68a6146SBalamuruhan S LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) 3032a68a6146SBalamuruhan S #if defined(TARGET_PPC64) 3033a68a6146SBalamuruhan S LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) 3034a68a6146SBalamuruhan S #endif 3035a68a6146SBalamuruhan S 3036a3401188SBalamuruhan S #define ST_ATOMIC(name, memop, tp, op) \ 3037a3401188SBalamuruhan S static void gen_##name(DisasContext *ctx) \ 3038a3401188SBalamuruhan S { \ 3039a3401188SBalamuruhan S int len = MEMOP_GET_SIZE(memop); \ 3040a3401188SBalamuruhan S uint32_t gpr_FC = FC(ctx->opcode); \ 3041a3401188SBalamuruhan S TCGv EA = tcg_temp_local_new(); \ 3042a3401188SBalamuruhan S TCGv_##tp t0, t1; \ 3043a3401188SBalamuruhan S \ 3044a3401188SBalamuruhan S gen_addr_register(ctx, EA); \ 3045a3401188SBalamuruhan S if (len > 1) { \ 3046a3401188SBalamuruhan S gen_check_align(ctx, EA, len - 1); \ 3047a3401188SBalamuruhan S } \ 3048a3401188SBalamuruhan S t0 = tcg_temp_new_##tp(); \ 3049a3401188SBalamuruhan S t1 = tcg_temp_new_##tp(); \ 3050a3401188SBalamuruhan S tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3051a3401188SBalamuruhan S \ 3052a3401188SBalamuruhan S switch (gpr_FC) { \ 3053a3401188SBalamuruhan S case 0: /* add and Store */ \ 3054a3401188SBalamuruhan S tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3055a3401188SBalamuruhan S break; \ 3056a3401188SBalamuruhan S case 1: /* xor and Store */ \ 3057a3401188SBalamuruhan S tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3058a3401188SBalamuruhan S break; \ 3059a3401188SBalamuruhan S case 2: /* Or and Store */ \ 3060a3401188SBalamuruhan S tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3061a3401188SBalamuruhan S break; \ 3062a3401188SBalamuruhan S case 3: /* 'and' and Store */ \ 3063a3401188SBalamuruhan S tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3064a3401188SBalamuruhan S break; \ 3065a3401188SBalamuruhan S case 4: /* Store max unsigned */ \ 3066a3401188SBalamuruhan S case 5: /* Store max signed */ \ 3067a3401188SBalamuruhan S case 6: /* Store min unsigned */ \ 3068a3401188SBalamuruhan S case 7: /* Store min signed */ \ 3069a3401188SBalamuruhan S case 24: /* Store twin */ \ 3070a3401188SBalamuruhan S gen_invalid(ctx); \ 3071a3401188SBalamuruhan S break; \ 3072a3401188SBalamuruhan S default: \ 3073a3401188SBalamuruhan S /* invoke data storage error handler */ \ 3074a3401188SBalamuruhan S gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3075a3401188SBalamuruhan S } \ 3076a3401188SBalamuruhan S tcg_temp_free_##tp(t0); \ 3077a3401188SBalamuruhan S tcg_temp_free_##tp(t1); \ 3078a3401188SBalamuruhan S tcg_temp_free(EA); \ 3079a3401188SBalamuruhan S } 3080a3401188SBalamuruhan S 3081a3401188SBalamuruhan S ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) 3082a3401188SBalamuruhan S #if defined(TARGET_PPC64) 3083a3401188SBalamuruhan S ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) 3084a3401188SBalamuruhan S #endif 3085a3401188SBalamuruhan S 3086fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3087fcf5ef2aSThomas Huth static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3088fcf5ef2aSThomas Huth int reg, int memop) 3089fcf5ef2aSThomas Huth { 3090fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3091fcf5ef2aSThomas Huth 3092fcf5ef2aSThomas Huth tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); 3093fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); 3094fcf5ef2aSThomas Huth tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); 3095fcf5ef2aSThomas Huth tcg_temp_free(t0); 3096fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); 3097fcf5ef2aSThomas Huth } 3098fcf5ef2aSThomas Huth #else 3099fcf5ef2aSThomas Huth static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3100fcf5ef2aSThomas Huth int reg, int memop) 3101fcf5ef2aSThomas Huth { 3102fcf5ef2aSThomas Huth TCGLabel *l1; 3103fcf5ef2aSThomas Huth 3104fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3105fcf5ef2aSThomas Huth l1 = gen_new_label(); 3106fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3107efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3108fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop); 3109fcf5ef2aSThomas Huth gen_set_label(l1); 3110fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3111fcf5ef2aSThomas Huth } 3112fcf5ef2aSThomas Huth #endif 3113fcf5ef2aSThomas Huth 3114fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3115fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3116fcf5ef2aSThomas Huth { \ 3117fcf5ef2aSThomas Huth TCGv t0; \ 3118fcf5ef2aSThomas Huth int len = MEMOP_GET_SIZE(memop); \ 3119fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); \ 3120fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); \ 3121fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); \ 3122fcf5ef2aSThomas Huth if (len > 1) { \ 3123fcf5ef2aSThomas Huth gen_check_align(ctx, t0, (len) - 1); \ 3124fcf5ef2aSThomas Huth } \ 3125fcf5ef2aSThomas Huth gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ 3126fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 3127fcf5ef2aSThomas Huth } 3128fcf5ef2aSThomas Huth 3129fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3130fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3131fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3132fcf5ef2aSThomas Huth 3133fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3134fcf5ef2aSThomas Huth /* ldarx */ 3135fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3136fcf5ef2aSThomas Huth /* stdcx. */ 3137fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3138fcf5ef2aSThomas Huth 3139fcf5ef2aSThomas Huth /* lqarx */ 3140fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3141fcf5ef2aSThomas Huth { 3142fcf5ef2aSThomas Huth TCGv EA; 3143fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 3144fcf5ef2aSThomas Huth TCGv gpr1, gpr2; 3145fcf5ef2aSThomas Huth 3146fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3147fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3148fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3149fcf5ef2aSThomas Huth return; 3150fcf5ef2aSThomas Huth } 3151fcf5ef2aSThomas Huth 3152fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 3153fcf5ef2aSThomas Huth EA = tcg_temp_local_new(); 3154fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3155fcf5ef2aSThomas Huth gen_check_align(ctx, EA, 15); 3156fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 3157fcf5ef2aSThomas Huth gpr1 = cpu_gpr[rd+1]; 3158fcf5ef2aSThomas Huth gpr2 = cpu_gpr[rd]; 3159fcf5ef2aSThomas Huth } else { 3160fcf5ef2aSThomas Huth gpr1 = cpu_gpr[rd]; 3161fcf5ef2aSThomas Huth gpr2 = cpu_gpr[rd+1]; 3162fcf5ef2aSThomas Huth } 3163fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3164fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3165fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3166fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3167fcf5ef2aSThomas Huth 3168fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); 3169fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3170fcf5ef2aSThomas Huth tcg_temp_free(EA); 3171fcf5ef2aSThomas Huth } 3172fcf5ef2aSThomas Huth 3173fcf5ef2aSThomas Huth /* stqcx. */ 3174fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3175fcf5ef2aSThomas Huth { 3176fcf5ef2aSThomas Huth TCGv EA; 3177fcf5ef2aSThomas Huth int reg = rS(ctx->opcode); 3178fcf5ef2aSThomas Huth int len = 16; 3179fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3180fcf5ef2aSThomas Huth TCGLabel *l1; 3181fcf5ef2aSThomas Huth TCGv gpr1, gpr2; 3182fcf5ef2aSThomas Huth #endif 3183fcf5ef2aSThomas Huth 3184fcf5ef2aSThomas Huth if (unlikely((rD(ctx->opcode) & 1))) { 3185fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3186fcf5ef2aSThomas Huth return; 3187fcf5ef2aSThomas Huth } 3188fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 3189fcf5ef2aSThomas Huth EA = tcg_temp_local_new(); 3190fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3191fcf5ef2aSThomas Huth if (len > 1) { 3192fcf5ef2aSThomas Huth gen_check_align(ctx, EA, (len) - 1); 3193fcf5ef2aSThomas Huth } 3194fcf5ef2aSThomas Huth 3195fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3196fcf5ef2aSThomas Huth gen_conditional_store(ctx, EA, reg, 16); 3197fcf5ef2aSThomas Huth #else 3198fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3199fcf5ef2aSThomas Huth l1 = gen_new_label(); 3200fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3201efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3202fcf5ef2aSThomas Huth 3203fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 3204fcf5ef2aSThomas Huth gpr1 = cpu_gpr[reg + 1]; 3205fcf5ef2aSThomas Huth gpr2 = cpu_gpr[reg]; 3206fcf5ef2aSThomas Huth } else { 3207fcf5ef2aSThomas Huth gpr1 = cpu_gpr[reg]; 3208fcf5ef2aSThomas Huth gpr2 = cpu_gpr[reg + 1]; 3209fcf5ef2aSThomas Huth } 3210fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3211fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3212fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3213fcf5ef2aSThomas Huth 3214fcf5ef2aSThomas Huth gen_set_label(l1); 3215fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3216fcf5ef2aSThomas Huth #endif 3217fcf5ef2aSThomas Huth tcg_temp_free(EA); 3218fcf5ef2aSThomas Huth } 3219fcf5ef2aSThomas Huth 3220fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3221fcf5ef2aSThomas Huth 3222fcf5ef2aSThomas Huth /* sync */ 3223fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3224fcf5ef2aSThomas Huth { 3225fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3226fcf5ef2aSThomas Huth 3227fcf5ef2aSThomas Huth /* 3228fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3229fcf5ef2aSThomas Huth * 3230fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3231fcf5ef2aSThomas Huth * 3232fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3233fcf5ef2aSThomas Huth * check MSR_PR as well. 3234fcf5ef2aSThomas Huth */ 3235fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3236fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3237fcf5ef2aSThomas Huth } 3238fcf5ef2aSThomas Huth } 3239fcf5ef2aSThomas Huth 3240fcf5ef2aSThomas Huth /* wait */ 3241fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3242fcf5ef2aSThomas Huth { 3243fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3244fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3245fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3246fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3247fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3248fcf5ef2aSThomas Huth gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 3249fcf5ef2aSThomas Huth } 3250fcf5ef2aSThomas Huth 3251fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3252fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3253fcf5ef2aSThomas Huth { 3254fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3255fcf5ef2aSThomas Huth GEN_PRIV; 3256fcf5ef2aSThomas Huth #else 3257fcf5ef2aSThomas Huth TCGv_i32 t; 3258fcf5ef2aSThomas Huth 3259fcf5ef2aSThomas Huth CHK_HV; 3260fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3261fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3262fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3263fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3264fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3265fcf5ef2aSThomas Huth } 3266fcf5ef2aSThomas Huth 3267fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3268fcf5ef2aSThomas Huth { 3269fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3270fcf5ef2aSThomas Huth GEN_PRIV; 3271fcf5ef2aSThomas Huth #else 3272fcf5ef2aSThomas Huth TCGv_i32 t; 3273fcf5ef2aSThomas Huth 3274fcf5ef2aSThomas Huth CHK_HV; 3275fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3276fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3277fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3278fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3279fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3280fcf5ef2aSThomas Huth } 3281fcf5ef2aSThomas Huth 3282cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3283cdee0e72SNikunj A Dadhania { 3284cdee0e72SNikunj A Dadhania gen_nap(ctx); 3285cdee0e72SNikunj A Dadhania } 3286cdee0e72SNikunj A Dadhania 3287fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3288fcf5ef2aSThomas Huth { 3289fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3290fcf5ef2aSThomas Huth GEN_PRIV; 3291fcf5ef2aSThomas Huth #else 3292fcf5ef2aSThomas Huth TCGv_i32 t; 3293fcf5ef2aSThomas Huth 3294fcf5ef2aSThomas Huth CHK_HV; 3295fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3296fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3297fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3298fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3299fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3300fcf5ef2aSThomas Huth } 3301fcf5ef2aSThomas Huth 3302fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3303fcf5ef2aSThomas Huth { 3304fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3305fcf5ef2aSThomas Huth GEN_PRIV; 3306fcf5ef2aSThomas Huth #else 3307fcf5ef2aSThomas Huth TCGv_i32 t; 3308fcf5ef2aSThomas Huth 3309fcf5ef2aSThomas Huth CHK_HV; 3310fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3311fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3312fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3313fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3314fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3315fcf5ef2aSThomas Huth } 3316fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3317fcf5ef2aSThomas Huth 3318fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3319fcf5ef2aSThomas Huth { 3320fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3321fcf5ef2aSThomas Huth if (ctx->has_cfar) 3322fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3323fcf5ef2aSThomas Huth #endif 3324fcf5ef2aSThomas Huth } 3325fcf5ef2aSThomas Huth 3326fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3327fcf5ef2aSThomas Huth { 3328fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3329fcf5ef2aSThomas Huth return false; 3330fcf5ef2aSThomas Huth } 3331fcf5ef2aSThomas Huth 3332fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3333fcf5ef2aSThomas Huth return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3334fcf5ef2aSThomas Huth #else 3335fcf5ef2aSThomas Huth return true; 3336fcf5ef2aSThomas Huth #endif 3337fcf5ef2aSThomas Huth } 3338fcf5ef2aSThomas Huth 3339fcf5ef2aSThomas Huth /*** Branch ***/ 3340fcf5ef2aSThomas Huth static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3341fcf5ef2aSThomas Huth { 3342fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3343fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3344fcf5ef2aSThomas Huth } 3345fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3346fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3347fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 3348fcf5ef2aSThomas Huth tcg_gen_exit_tb((uintptr_t)ctx->tb + n); 3349fcf5ef2aSThomas Huth } else { 3350fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 3351fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3352fcf5ef2aSThomas Huth if ((ctx->singlestep_enabled & 3353fcf5ef2aSThomas Huth (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && 3354fcf5ef2aSThomas Huth (ctx->exception == POWERPC_EXCP_BRANCH || 3355fcf5ef2aSThomas Huth ctx->exception == POWERPC_EXCP_TRACE)) { 3356fcf5ef2aSThomas Huth gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); 3357fcf5ef2aSThomas Huth } 3358fcf5ef2aSThomas Huth if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { 3359fcf5ef2aSThomas Huth gen_debug_exception(ctx); 3360fcf5ef2aSThomas Huth } 3361fcf5ef2aSThomas Huth } 3362fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3363fcf5ef2aSThomas Huth } 3364fcf5ef2aSThomas Huth } 3365fcf5ef2aSThomas Huth 3366fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3367fcf5ef2aSThomas Huth { 3368fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3369fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3370fcf5ef2aSThomas Huth } 3371fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3372fcf5ef2aSThomas Huth } 3373fcf5ef2aSThomas Huth 3374fcf5ef2aSThomas Huth /* b ba bl bla */ 3375fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3376fcf5ef2aSThomas Huth { 3377fcf5ef2aSThomas Huth target_ulong li, target; 3378fcf5ef2aSThomas Huth 3379fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3380fcf5ef2aSThomas Huth /* sign extend LI */ 3381fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3382fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3383fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3384fcf5ef2aSThomas Huth target = ctx->nip + li - 4; 3385fcf5ef2aSThomas Huth } else { 3386fcf5ef2aSThomas Huth target = li; 3387fcf5ef2aSThomas Huth } 3388fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3389fcf5ef2aSThomas Huth gen_setlr(ctx, ctx->nip); 3390fcf5ef2aSThomas Huth } 3391fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3392fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3393fcf5ef2aSThomas Huth } 3394fcf5ef2aSThomas Huth 3395fcf5ef2aSThomas Huth #define BCOND_IM 0 3396fcf5ef2aSThomas Huth #define BCOND_LR 1 3397fcf5ef2aSThomas Huth #define BCOND_CTR 2 3398fcf5ef2aSThomas Huth #define BCOND_TAR 3 3399fcf5ef2aSThomas Huth 3400fcf5ef2aSThomas Huth static inline void gen_bcond(DisasContext *ctx, int type) 3401fcf5ef2aSThomas Huth { 3402fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3403fcf5ef2aSThomas Huth TCGLabel *l1; 3404fcf5ef2aSThomas Huth TCGv target; 3405fcf5ef2aSThomas Huth 3406fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3407fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3408fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3409fcf5ef2aSThomas Huth if (type == BCOND_CTR) 3410fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3411fcf5ef2aSThomas Huth else if (type == BCOND_TAR) 3412fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3413fcf5ef2aSThomas Huth else 3414fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3415fcf5ef2aSThomas Huth } else { 3416fcf5ef2aSThomas Huth TCGV_UNUSED(target); 3417fcf5ef2aSThomas Huth } 3418fcf5ef2aSThomas Huth if (LK(ctx->opcode)) 3419fcf5ef2aSThomas Huth gen_setlr(ctx, ctx->nip); 3420fcf5ef2aSThomas Huth l1 = gen_new_label(); 3421fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3422fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3423fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3424fcf5ef2aSThomas Huth if (unlikely(type == BCOND_CTR)) { 3425fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3426fcf5ef2aSThomas Huth return; 3427fcf5ef2aSThomas Huth } 3428fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3429fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3430fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3431fcf5ef2aSThomas Huth } else { 3432fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3433fcf5ef2aSThomas Huth } 3434fcf5ef2aSThomas Huth if (bo & 0x2) { 3435fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3436fcf5ef2aSThomas Huth } else { 3437fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3438fcf5ef2aSThomas Huth } 3439fcf5ef2aSThomas Huth tcg_temp_free(temp); 3440fcf5ef2aSThomas Huth } 3441fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3442fcf5ef2aSThomas Huth /* Test CR */ 3443fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3444fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3445fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3446fcf5ef2aSThomas Huth 3447fcf5ef2aSThomas Huth if (bo & 0x8) { 3448fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3449fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3450fcf5ef2aSThomas Huth } else { 3451fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3452fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3453fcf5ef2aSThomas Huth } 3454fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3455fcf5ef2aSThomas Huth } 3456fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3457fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3458fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3459fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3460fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, ctx->nip + li - 4); 3461fcf5ef2aSThomas Huth } else { 3462fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3463fcf5ef2aSThomas Huth } 3464fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 3465fcf5ef2aSThomas Huth gen_set_label(l1); 3466fcf5ef2aSThomas Huth gen_goto_tb(ctx, 1, ctx->nip); 3467fcf5ef2aSThomas Huth } 3468fcf5ef2aSThomas Huth } else { 3469fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3470fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3471fcf5ef2aSThomas Huth } else { 3472fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3473fcf5ef2aSThomas Huth } 3474fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3475fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 3476fcf5ef2aSThomas Huth gen_set_label(l1); 3477fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 3478fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3479fcf5ef2aSThomas Huth } 3480fcf5ef2aSThomas Huth } 3481fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3482fcf5ef2aSThomas Huth tcg_temp_free(target); 3483fcf5ef2aSThomas Huth } 3484fcf5ef2aSThomas Huth } 3485fcf5ef2aSThomas Huth 3486fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3487fcf5ef2aSThomas Huth { 3488fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3489fcf5ef2aSThomas Huth } 3490fcf5ef2aSThomas Huth 3491fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3492fcf5ef2aSThomas Huth { 3493fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3494fcf5ef2aSThomas Huth } 3495fcf5ef2aSThomas Huth 3496fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3497fcf5ef2aSThomas Huth { 3498fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3499fcf5ef2aSThomas Huth } 3500fcf5ef2aSThomas Huth 3501fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3502fcf5ef2aSThomas Huth { 3503fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3504fcf5ef2aSThomas Huth } 3505fcf5ef2aSThomas Huth 3506fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3507fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3508fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3509fcf5ef2aSThomas Huth { \ 3510fcf5ef2aSThomas Huth uint8_t bitmask; \ 3511fcf5ef2aSThomas Huth int sh; \ 3512fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3513fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3514fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3515fcf5ef2aSThomas Huth if (sh > 0) \ 3516fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3517fcf5ef2aSThomas Huth else if (sh < 0) \ 3518fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3519fcf5ef2aSThomas Huth else \ 3520fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3521fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3522fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3523fcf5ef2aSThomas Huth if (sh > 0) \ 3524fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3525fcf5ef2aSThomas Huth else if (sh < 0) \ 3526fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3527fcf5ef2aSThomas Huth else \ 3528fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3529fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3530fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3531fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3532fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3533fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3534fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3535fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3536fcf5ef2aSThomas Huth } 3537fcf5ef2aSThomas Huth 3538fcf5ef2aSThomas Huth /* crand */ 3539fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3540fcf5ef2aSThomas Huth /* crandc */ 3541fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3542fcf5ef2aSThomas Huth /* creqv */ 3543fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3544fcf5ef2aSThomas Huth /* crnand */ 3545fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3546fcf5ef2aSThomas Huth /* crnor */ 3547fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3548fcf5ef2aSThomas Huth /* cror */ 3549fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3550fcf5ef2aSThomas Huth /* crorc */ 3551fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3552fcf5ef2aSThomas Huth /* crxor */ 3553fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3554fcf5ef2aSThomas Huth 3555fcf5ef2aSThomas Huth /* mcrf */ 3556fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3557fcf5ef2aSThomas Huth { 3558fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3559fcf5ef2aSThomas Huth } 3560fcf5ef2aSThomas Huth 3561fcf5ef2aSThomas Huth /*** System linkage ***/ 3562fcf5ef2aSThomas Huth 3563fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3564fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3565fcf5ef2aSThomas Huth { 3566fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3567fcf5ef2aSThomas Huth GEN_PRIV; 3568fcf5ef2aSThomas Huth #else 3569fcf5ef2aSThomas Huth /* This instruction doesn't exist anymore on 64-bit server 3570fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3571fcf5ef2aSThomas Huth */ 3572fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_SEGMENT_64B) { 3573fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3574fcf5ef2aSThomas Huth return; 3575fcf5ef2aSThomas Huth } 3576fcf5ef2aSThomas Huth /* Restore CPU state */ 3577fcf5ef2aSThomas Huth CHK_SV; 3578fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3579fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3580fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3581fcf5ef2aSThomas Huth #endif 3582fcf5ef2aSThomas Huth } 3583fcf5ef2aSThomas Huth 3584fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3585fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 3586fcf5ef2aSThomas Huth { 3587fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3588fcf5ef2aSThomas Huth GEN_PRIV; 3589fcf5ef2aSThomas Huth #else 3590fcf5ef2aSThomas Huth /* Restore CPU state */ 3591fcf5ef2aSThomas Huth CHK_SV; 3592fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3593fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 3594fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3595fcf5ef2aSThomas Huth #endif 3596fcf5ef2aSThomas Huth } 3597fcf5ef2aSThomas Huth 3598fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 3599fcf5ef2aSThomas Huth { 3600fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3601fcf5ef2aSThomas Huth GEN_PRIV; 3602fcf5ef2aSThomas Huth #else 3603fcf5ef2aSThomas Huth /* Restore CPU state */ 3604fcf5ef2aSThomas Huth CHK_HV; 3605fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 3606fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3607fcf5ef2aSThomas Huth #endif 3608fcf5ef2aSThomas Huth } 3609fcf5ef2aSThomas Huth #endif 3610fcf5ef2aSThomas Huth 3611fcf5ef2aSThomas Huth /* sc */ 3612fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3613fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3614fcf5ef2aSThomas Huth #else 3615fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3616fcf5ef2aSThomas Huth #endif 3617fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 3618fcf5ef2aSThomas Huth { 3619fcf5ef2aSThomas Huth uint32_t lev; 3620fcf5ef2aSThomas Huth 3621fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 3622fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3623fcf5ef2aSThomas Huth } 3624fcf5ef2aSThomas Huth 3625fcf5ef2aSThomas Huth /*** Trap ***/ 3626fcf5ef2aSThomas Huth 3627fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 3628fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 3629fcf5ef2aSThomas Huth { 3630fcf5ef2aSThomas Huth /* Trap never */ 3631fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 3632fcf5ef2aSThomas Huth return true; 3633fcf5ef2aSThomas Huth } 3634fcf5ef2aSThomas Huth /* Trap always */ 3635fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 3636fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3637fcf5ef2aSThomas Huth return true; 3638fcf5ef2aSThomas Huth } 3639fcf5ef2aSThomas Huth return false; 3640fcf5ef2aSThomas Huth } 3641fcf5ef2aSThomas Huth 3642fcf5ef2aSThomas Huth /* tw */ 3643fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 3644fcf5ef2aSThomas Huth { 3645fcf5ef2aSThomas Huth TCGv_i32 t0; 3646fcf5ef2aSThomas Huth 3647fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3648fcf5ef2aSThomas Huth return; 3649fcf5ef2aSThomas Huth } 3650fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3651fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3652fcf5ef2aSThomas Huth t0); 3653fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3654fcf5ef2aSThomas Huth } 3655fcf5ef2aSThomas Huth 3656fcf5ef2aSThomas Huth /* twi */ 3657fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 3658fcf5ef2aSThomas Huth { 3659fcf5ef2aSThomas Huth TCGv t0; 3660fcf5ef2aSThomas Huth TCGv_i32 t1; 3661fcf5ef2aSThomas Huth 3662fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3663fcf5ef2aSThomas Huth return; 3664fcf5ef2aSThomas Huth } 3665fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3666fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3667fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3668fcf5ef2aSThomas Huth tcg_temp_free(t0); 3669fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3670fcf5ef2aSThomas Huth } 3671fcf5ef2aSThomas Huth 3672fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3673fcf5ef2aSThomas Huth /* td */ 3674fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 3675fcf5ef2aSThomas Huth { 3676fcf5ef2aSThomas Huth TCGv_i32 t0; 3677fcf5ef2aSThomas Huth 3678fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3679fcf5ef2aSThomas Huth return; 3680fcf5ef2aSThomas Huth } 3681fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3682fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3683fcf5ef2aSThomas Huth t0); 3684fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3685fcf5ef2aSThomas Huth } 3686fcf5ef2aSThomas Huth 3687fcf5ef2aSThomas Huth /* tdi */ 3688fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 3689fcf5ef2aSThomas Huth { 3690fcf5ef2aSThomas Huth TCGv t0; 3691fcf5ef2aSThomas Huth TCGv_i32 t1; 3692fcf5ef2aSThomas Huth 3693fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3694fcf5ef2aSThomas Huth return; 3695fcf5ef2aSThomas Huth } 3696fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3697fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3698fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3699fcf5ef2aSThomas Huth tcg_temp_free(t0); 3700fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3701fcf5ef2aSThomas Huth } 3702fcf5ef2aSThomas Huth #endif 3703fcf5ef2aSThomas Huth 3704fcf5ef2aSThomas Huth /*** Processor control ***/ 3705fcf5ef2aSThomas Huth 3706fcf5ef2aSThomas Huth static void gen_read_xer(TCGv dst) 3707fcf5ef2aSThomas Huth { 3708fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3709fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3710fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 3711fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 3712fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 3713fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 3714fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 3715fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 3716fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 3717fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 3718fcf5ef2aSThomas Huth tcg_temp_free(t0); 3719fcf5ef2aSThomas Huth tcg_temp_free(t1); 3720fcf5ef2aSThomas Huth tcg_temp_free(t2); 3721fcf5ef2aSThomas Huth } 3722fcf5ef2aSThomas Huth 3723fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 3724fcf5ef2aSThomas Huth { 3725fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 3726fcf5ef2aSThomas Huth ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); 3727fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_so, src, XER_SO); 3728fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_ov, src, XER_OV); 3729fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_ca, src, XER_CA); 3730fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_so, cpu_so, 1); 3731fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); 3732fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); 3733fcf5ef2aSThomas Huth } 3734fcf5ef2aSThomas Huth 3735fcf5ef2aSThomas Huth /* mcrxr */ 3736fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 3737fcf5ef2aSThomas Huth { 3738fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3739fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3740fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3741fcf5ef2aSThomas Huth 3742fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 3743fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 3744fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 3745fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 3746fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 3747fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 3748fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 3749fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 3750fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3751fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3752fcf5ef2aSThomas Huth 3753fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 3754fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 3755fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3756fcf5ef2aSThomas Huth } 3757fcf5ef2aSThomas Huth 3758fcf5ef2aSThomas Huth /* mfcr mfocrf */ 3759fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 3760fcf5ef2aSThomas Huth { 3761fcf5ef2aSThomas Huth uint32_t crm, crn; 3762fcf5ef2aSThomas Huth 3763fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 3764fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 3765fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 3766fcf5ef2aSThomas Huth crn = ctz32 (crm); 3767fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3768fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 3769fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 3770fcf5ef2aSThomas Huth } 3771fcf5ef2aSThomas Huth } else { 3772fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3773fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 3774fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3775fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 3776fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3777fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 3778fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3779fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 3780fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3781fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 3782fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3783fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 3784fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3785fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 3786fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3787fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 3788fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 3789fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3790fcf5ef2aSThomas Huth } 3791fcf5ef2aSThomas Huth } 3792fcf5ef2aSThomas Huth 3793fcf5ef2aSThomas Huth /* mfmsr */ 3794fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 3795fcf5ef2aSThomas Huth { 3796fcf5ef2aSThomas Huth CHK_SV; 3797fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 3798fcf5ef2aSThomas Huth } 3799fcf5ef2aSThomas Huth 3800fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 3801fcf5ef2aSThomas Huth { 3802fcf5ef2aSThomas Huth #if 0 3803fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 3804fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 3805fcf5ef2aSThomas Huth #endif 3806fcf5ef2aSThomas Huth } 3807fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 3808fcf5ef2aSThomas Huth 3809fcf5ef2aSThomas Huth /* mfspr */ 3810fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 3811fcf5ef2aSThomas Huth { 3812fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 3813fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 3814fcf5ef2aSThomas Huth 3815fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3816fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 3817fcf5ef2aSThomas Huth #else 3818fcf5ef2aSThomas Huth if (ctx->pr) { 3819fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 3820fcf5ef2aSThomas Huth } else if (ctx->hv) { 3821fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 3822fcf5ef2aSThomas Huth } else { 3823fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 3824fcf5ef2aSThomas Huth } 3825fcf5ef2aSThomas Huth #endif 3826fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 3827fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 3828fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 3829fcf5ef2aSThomas Huth } else { 3830fcf5ef2aSThomas Huth /* Privilege exception */ 3831fcf5ef2aSThomas Huth /* This is a hack to avoid warnings when running Linux: 3832fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 3833fcf5ef2aSThomas Huth * allowing userland application to read the PVR 3834fcf5ef2aSThomas Huth */ 3835fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 3836fcf5ef2aSThomas Huth fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at " 3837fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3838fcf5ef2aSThomas Huth if (qemu_log_separate()) { 3839fcf5ef2aSThomas Huth qemu_log("Trying to read privileged spr %d (0x%03x) at " 3840fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3841fcf5ef2aSThomas Huth } 3842fcf5ef2aSThomas Huth } 3843fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 3844fcf5ef2aSThomas Huth } 3845fcf5ef2aSThomas Huth } else { 3846fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 3847fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 3848fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 3849fcf5ef2aSThomas Huth /* This is a nop */ 3850fcf5ef2aSThomas Huth return; 3851fcf5ef2aSThomas Huth } 3852fcf5ef2aSThomas Huth /* Not defined */ 3853fcf5ef2aSThomas Huth fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " 3854fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3855fcf5ef2aSThomas Huth if (qemu_log_separate()) { 3856fcf5ef2aSThomas Huth qemu_log("Trying to read invalid spr %d (0x%03x) at " 3857fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3858fcf5ef2aSThomas Huth } 3859fcf5ef2aSThomas Huth 3860fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 3861fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 3862fcf5ef2aSThomas Huth */ 3863fcf5ef2aSThomas Huth if (sprn & 0x10) { 3864fcf5ef2aSThomas Huth if (ctx->pr) { 3865fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3866fcf5ef2aSThomas Huth } 3867fcf5ef2aSThomas Huth } else { 3868fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 3869fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3870fcf5ef2aSThomas Huth } 3871fcf5ef2aSThomas Huth } 3872fcf5ef2aSThomas Huth } 3873fcf5ef2aSThomas Huth } 3874fcf5ef2aSThomas Huth 3875fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 3876fcf5ef2aSThomas Huth { 3877fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 3878fcf5ef2aSThomas Huth } 3879fcf5ef2aSThomas Huth 3880fcf5ef2aSThomas Huth /* mftb */ 3881fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 3882fcf5ef2aSThomas Huth { 3883fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 3884fcf5ef2aSThomas Huth } 3885fcf5ef2aSThomas Huth 3886fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 3887fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 3888fcf5ef2aSThomas Huth { 3889fcf5ef2aSThomas Huth uint32_t crm, crn; 3890fcf5ef2aSThomas Huth 3891fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 3892fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 3893fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 3894fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3895fcf5ef2aSThomas Huth crn = ctz32 (crm); 3896fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3897fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 3898fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 3899fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3900fcf5ef2aSThomas Huth } 3901fcf5ef2aSThomas Huth } else { 3902fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3903fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3904fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 3905fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 3906fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 3907fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 3908fcf5ef2aSThomas Huth } 3909fcf5ef2aSThomas Huth } 3910fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3911fcf5ef2aSThomas Huth } 3912fcf5ef2aSThomas Huth } 3913fcf5ef2aSThomas Huth 3914fcf5ef2aSThomas Huth /* mtmsr */ 3915fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3916fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 3917fcf5ef2aSThomas Huth { 3918fcf5ef2aSThomas Huth CHK_SV; 3919fcf5ef2aSThomas Huth 3920fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3921fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 3922fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 3923fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3924fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 3925fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 3926fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 3927fcf5ef2aSThomas Huth tcg_temp_free(t0); 3928fcf5ef2aSThomas Huth } else { 3929fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 3930fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 3931fcf5ef2aSThomas Huth * directly from ppc_store_msr 3932fcf5ef2aSThomas Huth */ 3933fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 3934fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 3935fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 3936fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 3937fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3938fcf5ef2aSThomas Huth } 3939fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 3940fcf5ef2aSThomas Huth } 3941fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3942fcf5ef2aSThomas Huth 3943fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 3944fcf5ef2aSThomas Huth { 3945fcf5ef2aSThomas Huth CHK_SV; 3946fcf5ef2aSThomas Huth 3947fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3948fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 3949fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 3950fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3951fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 3952fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 3953fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 3954fcf5ef2aSThomas Huth tcg_temp_free(t0); 3955fcf5ef2aSThomas Huth } else { 3956fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 3957fcf5ef2aSThomas Huth 3958fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 3959fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 3960fcf5ef2aSThomas Huth * directly from ppc_store_msr 3961fcf5ef2aSThomas Huth */ 3962fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 3963fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3964fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 3965fcf5ef2aSThomas Huth #else 3966fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 3967fcf5ef2aSThomas Huth #endif 3968fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 3969fcf5ef2aSThomas Huth tcg_temp_free(msr); 3970fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 3971fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 3972fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3973fcf5ef2aSThomas Huth } 3974fcf5ef2aSThomas Huth #endif 3975fcf5ef2aSThomas Huth } 3976fcf5ef2aSThomas Huth 3977fcf5ef2aSThomas Huth /* mtspr */ 3978fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 3979fcf5ef2aSThomas Huth { 3980fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 3981fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 3982fcf5ef2aSThomas Huth 3983fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3984fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 3985fcf5ef2aSThomas Huth #else 3986fcf5ef2aSThomas Huth if (ctx->pr) { 3987fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 3988fcf5ef2aSThomas Huth } else if (ctx->hv) { 3989fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 3990fcf5ef2aSThomas Huth } else { 3991fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 3992fcf5ef2aSThomas Huth } 3993fcf5ef2aSThomas Huth #endif 3994fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 3995fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 3996fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 3997fcf5ef2aSThomas Huth } else { 3998fcf5ef2aSThomas Huth /* Privilege exception */ 3999fcf5ef2aSThomas Huth fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at " 4000fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4001fcf5ef2aSThomas Huth if (qemu_log_separate()) { 4002fcf5ef2aSThomas Huth qemu_log("Trying to write privileged spr %d (0x%03x) at " 4003fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4004fcf5ef2aSThomas Huth } 4005fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4006fcf5ef2aSThomas Huth } 4007fcf5ef2aSThomas Huth } else { 4008fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4009fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4010fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4011fcf5ef2aSThomas Huth /* This is a nop */ 4012fcf5ef2aSThomas Huth return; 4013fcf5ef2aSThomas Huth } 4014fcf5ef2aSThomas Huth 4015fcf5ef2aSThomas Huth /* Not defined */ 4016fcf5ef2aSThomas Huth if (qemu_log_separate()) { 4017fcf5ef2aSThomas Huth qemu_log("Trying to write invalid spr %d (0x%03x) at " 4018fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4019fcf5ef2aSThomas Huth } 4020fcf5ef2aSThomas Huth fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " 4021fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4022fcf5ef2aSThomas Huth 4023fcf5ef2aSThomas Huth 4024fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4025fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4026fcf5ef2aSThomas Huth */ 4027fcf5ef2aSThomas Huth if (sprn & 0x10) { 4028fcf5ef2aSThomas Huth if (ctx->pr) { 4029fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4030fcf5ef2aSThomas Huth } 4031fcf5ef2aSThomas Huth } else { 4032fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4033fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4034fcf5ef2aSThomas Huth } 4035fcf5ef2aSThomas Huth } 4036fcf5ef2aSThomas Huth } 4037fcf5ef2aSThomas Huth } 4038fcf5ef2aSThomas Huth 4039fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4040fcf5ef2aSThomas Huth /* setb */ 4041fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4042fcf5ef2aSThomas Huth { 4043fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4044fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4045fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4046fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4047fcf5ef2aSThomas Huth 4048fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4049fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4050fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4051fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4052fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4053fcf5ef2aSThomas Huth 4054fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4055fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4056fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4057fcf5ef2aSThomas Huth } 4058fcf5ef2aSThomas Huth #endif 4059fcf5ef2aSThomas Huth 4060fcf5ef2aSThomas Huth /*** Cache management ***/ 4061fcf5ef2aSThomas Huth 4062fcf5ef2aSThomas Huth /* dcbf */ 4063fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4064fcf5ef2aSThomas Huth { 4065fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4066fcf5ef2aSThomas Huth TCGv t0; 4067fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4068fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4069fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4070fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4071fcf5ef2aSThomas Huth tcg_temp_free(t0); 4072fcf5ef2aSThomas Huth } 4073fcf5ef2aSThomas Huth 4074fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4075fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4076fcf5ef2aSThomas Huth { 4077fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4078fcf5ef2aSThomas Huth GEN_PRIV; 4079fcf5ef2aSThomas Huth #else 4080fcf5ef2aSThomas Huth TCGv EA, val; 4081fcf5ef2aSThomas Huth 4082fcf5ef2aSThomas Huth CHK_SV; 4083fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4084fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4085fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4086fcf5ef2aSThomas Huth val = tcg_temp_new(); 4087fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4088fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4089fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4090fcf5ef2aSThomas Huth tcg_temp_free(val); 4091fcf5ef2aSThomas Huth tcg_temp_free(EA); 4092fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4093fcf5ef2aSThomas Huth } 4094fcf5ef2aSThomas Huth 4095fcf5ef2aSThomas Huth /* dcdst */ 4096fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4097fcf5ef2aSThomas Huth { 4098fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4099fcf5ef2aSThomas Huth TCGv t0; 4100fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4101fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4102fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4103fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4104fcf5ef2aSThomas Huth tcg_temp_free(t0); 4105fcf5ef2aSThomas Huth } 4106fcf5ef2aSThomas Huth 4107fcf5ef2aSThomas Huth /* dcbt */ 4108fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4109fcf5ef2aSThomas Huth { 4110fcf5ef2aSThomas Huth /* interpreted as no-op */ 4111fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4112fcf5ef2aSThomas Huth * but does not generate any exception 4113fcf5ef2aSThomas Huth */ 4114fcf5ef2aSThomas Huth } 4115fcf5ef2aSThomas Huth 4116fcf5ef2aSThomas Huth /* dcbtst */ 4117fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4118fcf5ef2aSThomas Huth { 4119fcf5ef2aSThomas Huth /* interpreted as no-op */ 4120fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4121fcf5ef2aSThomas Huth * but does not generate any exception 4122fcf5ef2aSThomas Huth */ 4123fcf5ef2aSThomas Huth } 4124fcf5ef2aSThomas Huth 4125fcf5ef2aSThomas Huth /* dcbtls */ 4126fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4127fcf5ef2aSThomas Huth { 4128fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4129fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4130fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4131fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4132fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4133fcf5ef2aSThomas Huth tcg_temp_free(t0); 4134fcf5ef2aSThomas Huth } 4135fcf5ef2aSThomas Huth 4136fcf5ef2aSThomas Huth /* dcbz */ 4137fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4138fcf5ef2aSThomas Huth { 4139fcf5ef2aSThomas Huth TCGv tcgv_addr; 4140fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4141fcf5ef2aSThomas Huth 4142fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4143fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4144fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4145fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4146fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4147fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4148fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4149fcf5ef2aSThomas Huth } 4150fcf5ef2aSThomas Huth 4151fcf5ef2aSThomas Huth /* dst / dstt */ 4152fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4153fcf5ef2aSThomas Huth { 4154fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4155fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4156fcf5ef2aSThomas Huth } else { 4157fcf5ef2aSThomas Huth /* interpreted as no-op */ 4158fcf5ef2aSThomas Huth } 4159fcf5ef2aSThomas Huth } 4160fcf5ef2aSThomas Huth 4161fcf5ef2aSThomas Huth /* dstst /dststt */ 4162fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4163fcf5ef2aSThomas Huth { 4164fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4165fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4166fcf5ef2aSThomas Huth } else { 4167fcf5ef2aSThomas Huth /* interpreted as no-op */ 4168fcf5ef2aSThomas Huth } 4169fcf5ef2aSThomas Huth 4170fcf5ef2aSThomas Huth } 4171fcf5ef2aSThomas Huth 4172fcf5ef2aSThomas Huth /* dss / dssall */ 4173fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4174fcf5ef2aSThomas Huth { 4175fcf5ef2aSThomas Huth /* interpreted as no-op */ 4176fcf5ef2aSThomas Huth } 4177fcf5ef2aSThomas Huth 4178fcf5ef2aSThomas Huth /* icbi */ 4179fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4180fcf5ef2aSThomas Huth { 4181fcf5ef2aSThomas Huth TCGv t0; 4182fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4183fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4184fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4185fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4186fcf5ef2aSThomas Huth tcg_temp_free(t0); 4187fcf5ef2aSThomas Huth } 4188fcf5ef2aSThomas Huth 4189fcf5ef2aSThomas Huth /* Optional: */ 4190fcf5ef2aSThomas Huth /* dcba */ 4191fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4192fcf5ef2aSThomas Huth { 4193fcf5ef2aSThomas Huth /* interpreted as no-op */ 4194fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a store by the MMU 4195fcf5ef2aSThomas Huth * but does not generate any exception 4196fcf5ef2aSThomas Huth */ 4197fcf5ef2aSThomas Huth } 4198fcf5ef2aSThomas Huth 4199fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4200fcf5ef2aSThomas Huth /* Supervisor only: */ 4201fcf5ef2aSThomas Huth 4202fcf5ef2aSThomas Huth /* mfsr */ 4203fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4204fcf5ef2aSThomas Huth { 4205fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4206fcf5ef2aSThomas Huth GEN_PRIV; 4207fcf5ef2aSThomas Huth #else 4208fcf5ef2aSThomas Huth TCGv t0; 4209fcf5ef2aSThomas Huth 4210fcf5ef2aSThomas Huth CHK_SV; 4211fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4212fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4213fcf5ef2aSThomas Huth tcg_temp_free(t0); 4214fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4215fcf5ef2aSThomas Huth } 4216fcf5ef2aSThomas Huth 4217fcf5ef2aSThomas Huth /* mfsrin */ 4218fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4219fcf5ef2aSThomas Huth { 4220fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4221fcf5ef2aSThomas Huth GEN_PRIV; 4222fcf5ef2aSThomas Huth #else 4223fcf5ef2aSThomas Huth TCGv t0; 4224fcf5ef2aSThomas Huth 4225fcf5ef2aSThomas Huth CHK_SV; 4226fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4227fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4228fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 4229fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4230fcf5ef2aSThomas Huth tcg_temp_free(t0); 4231fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4232fcf5ef2aSThomas Huth } 4233fcf5ef2aSThomas Huth 4234fcf5ef2aSThomas Huth /* mtsr */ 4235fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4236fcf5ef2aSThomas Huth { 4237fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4238fcf5ef2aSThomas Huth GEN_PRIV; 4239fcf5ef2aSThomas Huth #else 4240fcf5ef2aSThomas Huth TCGv t0; 4241fcf5ef2aSThomas Huth 4242fcf5ef2aSThomas Huth CHK_SV; 4243fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4244fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4245fcf5ef2aSThomas Huth tcg_temp_free(t0); 4246fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4247fcf5ef2aSThomas Huth } 4248fcf5ef2aSThomas Huth 4249fcf5ef2aSThomas Huth /* mtsrin */ 4250fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4251fcf5ef2aSThomas Huth { 4252fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4253fcf5ef2aSThomas Huth GEN_PRIV; 4254fcf5ef2aSThomas Huth #else 4255fcf5ef2aSThomas Huth TCGv t0; 4256fcf5ef2aSThomas Huth CHK_SV; 4257fcf5ef2aSThomas Huth 4258fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4259fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4260fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 4261fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4262fcf5ef2aSThomas Huth tcg_temp_free(t0); 4263fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4264fcf5ef2aSThomas Huth } 4265fcf5ef2aSThomas Huth 4266fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4267fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4268fcf5ef2aSThomas Huth 4269fcf5ef2aSThomas Huth /* mfsr */ 4270fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4271fcf5ef2aSThomas Huth { 4272fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4273fcf5ef2aSThomas Huth GEN_PRIV; 4274fcf5ef2aSThomas Huth #else 4275fcf5ef2aSThomas Huth TCGv t0; 4276fcf5ef2aSThomas Huth 4277fcf5ef2aSThomas Huth CHK_SV; 4278fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4279fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4280fcf5ef2aSThomas Huth tcg_temp_free(t0); 4281fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4282fcf5ef2aSThomas Huth } 4283fcf5ef2aSThomas Huth 4284fcf5ef2aSThomas Huth /* mfsrin */ 4285fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4286fcf5ef2aSThomas Huth { 4287fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4288fcf5ef2aSThomas Huth GEN_PRIV; 4289fcf5ef2aSThomas Huth #else 4290fcf5ef2aSThomas Huth TCGv t0; 4291fcf5ef2aSThomas Huth 4292fcf5ef2aSThomas Huth CHK_SV; 4293fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4294fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4295fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 4296fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4297fcf5ef2aSThomas Huth tcg_temp_free(t0); 4298fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4299fcf5ef2aSThomas Huth } 4300fcf5ef2aSThomas Huth 4301fcf5ef2aSThomas Huth /* mtsr */ 4302fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4303fcf5ef2aSThomas Huth { 4304fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4305fcf5ef2aSThomas Huth GEN_PRIV; 4306fcf5ef2aSThomas Huth #else 4307fcf5ef2aSThomas Huth TCGv t0; 4308fcf5ef2aSThomas Huth 4309fcf5ef2aSThomas Huth CHK_SV; 4310fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4311fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4312fcf5ef2aSThomas Huth tcg_temp_free(t0); 4313fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4314fcf5ef2aSThomas Huth } 4315fcf5ef2aSThomas Huth 4316fcf5ef2aSThomas Huth /* mtsrin */ 4317fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4318fcf5ef2aSThomas Huth { 4319fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4320fcf5ef2aSThomas Huth GEN_PRIV; 4321fcf5ef2aSThomas Huth #else 4322fcf5ef2aSThomas Huth TCGv t0; 4323fcf5ef2aSThomas Huth 4324fcf5ef2aSThomas Huth CHK_SV; 4325fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4326fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4327fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 4328fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4329fcf5ef2aSThomas Huth tcg_temp_free(t0); 4330fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4331fcf5ef2aSThomas Huth } 4332fcf5ef2aSThomas Huth 4333fcf5ef2aSThomas Huth /* slbmte */ 4334fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4335fcf5ef2aSThomas Huth { 4336fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4337fcf5ef2aSThomas Huth GEN_PRIV; 4338fcf5ef2aSThomas Huth #else 4339fcf5ef2aSThomas Huth CHK_SV; 4340fcf5ef2aSThomas Huth 4341fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4342fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4343fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4344fcf5ef2aSThomas Huth } 4345fcf5ef2aSThomas Huth 4346fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4347fcf5ef2aSThomas Huth { 4348fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4349fcf5ef2aSThomas Huth GEN_PRIV; 4350fcf5ef2aSThomas Huth #else 4351fcf5ef2aSThomas Huth CHK_SV; 4352fcf5ef2aSThomas Huth 4353fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4354fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4355fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4356fcf5ef2aSThomas Huth } 4357fcf5ef2aSThomas Huth 4358fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4359fcf5ef2aSThomas Huth { 4360fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4361fcf5ef2aSThomas Huth GEN_PRIV; 4362fcf5ef2aSThomas Huth #else 4363fcf5ef2aSThomas Huth CHK_SV; 4364fcf5ef2aSThomas Huth 4365fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4366fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4367fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4368fcf5ef2aSThomas Huth } 4369fcf5ef2aSThomas Huth 4370fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4371fcf5ef2aSThomas Huth { 4372fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4373fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4374fcf5ef2aSThomas Huth #else 4375fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4376fcf5ef2aSThomas Huth 4377fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4378fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4379fcf5ef2aSThomas Huth return; 4380fcf5ef2aSThomas Huth } 4381fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4382fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4383fcf5ef2aSThomas Huth l1 = gen_new_label(); 4384fcf5ef2aSThomas Huth l2 = gen_new_label(); 4385fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4386fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4387efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4388fcf5ef2aSThomas Huth tcg_gen_br(l2); 4389fcf5ef2aSThomas Huth gen_set_label(l1); 4390fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4391fcf5ef2aSThomas Huth gen_set_label(l2); 4392fcf5ef2aSThomas Huth #endif 4393fcf5ef2aSThomas Huth } 4394fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4395fcf5ef2aSThomas Huth 4396fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4397fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4398fcf5ef2aSThomas Huth 4399fcf5ef2aSThomas Huth /* tlbia */ 4400fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4401fcf5ef2aSThomas Huth { 4402fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4403fcf5ef2aSThomas Huth GEN_PRIV; 4404fcf5ef2aSThomas Huth #else 4405fcf5ef2aSThomas Huth CHK_HV; 4406fcf5ef2aSThomas Huth 4407fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4408fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4409fcf5ef2aSThomas Huth } 4410fcf5ef2aSThomas Huth 4411fcf5ef2aSThomas Huth /* tlbiel */ 4412fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4413fcf5ef2aSThomas Huth { 4414fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4415fcf5ef2aSThomas Huth GEN_PRIV; 4416fcf5ef2aSThomas Huth #else 4417fcf5ef2aSThomas Huth CHK_SV; 4418fcf5ef2aSThomas Huth 4419fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4420fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4421fcf5ef2aSThomas Huth } 4422fcf5ef2aSThomas Huth 4423fcf5ef2aSThomas Huth /* tlbie */ 4424fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4425fcf5ef2aSThomas Huth { 4426fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4427fcf5ef2aSThomas Huth GEN_PRIV; 4428fcf5ef2aSThomas Huth #else 4429fcf5ef2aSThomas Huth TCGv_i32 t1; 4430fcf5ef2aSThomas Huth CHK_HV; 4431fcf5ef2aSThomas Huth 4432fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4433fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4434fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4435fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4436fcf5ef2aSThomas Huth tcg_temp_free(t0); 4437fcf5ef2aSThomas Huth } else { 4438fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4439fcf5ef2aSThomas Huth } 4440fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4441fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4442fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4443fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4444fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4445fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4446fcf5ef2aSThomas Huth } 4447fcf5ef2aSThomas Huth 4448fcf5ef2aSThomas Huth /* tlbsync */ 4449fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4450fcf5ef2aSThomas Huth { 4451fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4452fcf5ef2aSThomas Huth GEN_PRIV; 4453fcf5ef2aSThomas Huth #else 4454fcf5ef2aSThomas Huth CHK_HV; 4455fcf5ef2aSThomas Huth 4456fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4457fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4458fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4459fcf5ef2aSThomas Huth } 4460fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4461fcf5ef2aSThomas Huth } 4462fcf5ef2aSThomas Huth 4463fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4464fcf5ef2aSThomas Huth /* slbia */ 4465fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 4466fcf5ef2aSThomas Huth { 4467fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4468fcf5ef2aSThomas Huth GEN_PRIV; 4469fcf5ef2aSThomas Huth #else 4470fcf5ef2aSThomas Huth CHK_SV; 4471fcf5ef2aSThomas Huth 4472fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 4473fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4474fcf5ef2aSThomas Huth } 4475fcf5ef2aSThomas Huth 4476fcf5ef2aSThomas Huth /* slbie */ 4477fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 4478fcf5ef2aSThomas Huth { 4479fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4480fcf5ef2aSThomas Huth GEN_PRIV; 4481fcf5ef2aSThomas Huth #else 4482fcf5ef2aSThomas Huth CHK_SV; 4483fcf5ef2aSThomas Huth 4484fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4485fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4486fcf5ef2aSThomas Huth } 4487fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4488fcf5ef2aSThomas Huth 4489fcf5ef2aSThomas Huth /*** External control ***/ 4490fcf5ef2aSThomas Huth /* Optional: */ 4491fcf5ef2aSThomas Huth 4492fcf5ef2aSThomas Huth /* eciwx */ 4493fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 4494fcf5ef2aSThomas Huth { 4495fcf5ef2aSThomas Huth TCGv t0; 4496fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4497fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4498fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4499fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4500fcf5ef2aSThomas Huth gen_check_align(ctx, t0, 0x03); 4501fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4502fcf5ef2aSThomas Huth tcg_temp_free(t0); 4503fcf5ef2aSThomas Huth } 4504fcf5ef2aSThomas Huth 4505fcf5ef2aSThomas Huth /* ecowx */ 4506fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 4507fcf5ef2aSThomas Huth { 4508fcf5ef2aSThomas Huth TCGv t0; 4509fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4510fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4511fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4512fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4513fcf5ef2aSThomas Huth gen_check_align(ctx, t0, 0x03); 4514fcf5ef2aSThomas Huth gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4515fcf5ef2aSThomas Huth tcg_temp_free(t0); 4516fcf5ef2aSThomas Huth } 4517fcf5ef2aSThomas Huth 4518fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 4519fcf5ef2aSThomas Huth 4520fcf5ef2aSThomas Huth /* abs - abs. */ 4521fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 4522fcf5ef2aSThomas Huth { 4523fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4524fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4525fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4526fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4527fcf5ef2aSThomas Huth tcg_gen_br(l2); 4528fcf5ef2aSThomas Huth gen_set_label(l1); 4529fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4530fcf5ef2aSThomas Huth gen_set_label(l2); 4531fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4532fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4533fcf5ef2aSThomas Huth } 4534fcf5ef2aSThomas Huth 4535fcf5ef2aSThomas Huth /* abso - abso. */ 4536fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 4537fcf5ef2aSThomas Huth { 4538fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4539fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4540fcf5ef2aSThomas Huth TCGLabel *l3 = gen_new_label(); 4541fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4542fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4543fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4544fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4545fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4546fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4547fcf5ef2aSThomas Huth tcg_gen_br(l2); 4548fcf5ef2aSThomas Huth gen_set_label(l1); 4549fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4550fcf5ef2aSThomas Huth tcg_gen_br(l3); 4551fcf5ef2aSThomas Huth gen_set_label(l2); 4552fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4553fcf5ef2aSThomas Huth gen_set_label(l3); 4554fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4555fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4556fcf5ef2aSThomas Huth } 4557fcf5ef2aSThomas Huth 4558fcf5ef2aSThomas Huth /* clcs */ 4559fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 4560fcf5ef2aSThomas Huth { 4561fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4562fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4563fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4564fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 4565fcf5ef2aSThomas Huth } 4566fcf5ef2aSThomas Huth 4567fcf5ef2aSThomas Huth /* div - div. */ 4568fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 4569fcf5ef2aSThomas Huth { 4570fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4571fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4572fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4573fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4574fcf5ef2aSThomas Huth } 4575fcf5ef2aSThomas Huth 4576fcf5ef2aSThomas Huth /* divo - divo. */ 4577fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 4578fcf5ef2aSThomas Huth { 4579fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4580fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4581fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4582fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4583fcf5ef2aSThomas Huth } 4584fcf5ef2aSThomas Huth 4585fcf5ef2aSThomas Huth /* divs - divs. */ 4586fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 4587fcf5ef2aSThomas Huth { 4588fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4589fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4590fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4591fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4592fcf5ef2aSThomas Huth } 4593fcf5ef2aSThomas Huth 4594fcf5ef2aSThomas Huth /* divso - divso. */ 4595fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 4596fcf5ef2aSThomas Huth { 4597fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4598fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4599fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4600fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4601fcf5ef2aSThomas Huth } 4602fcf5ef2aSThomas Huth 4603fcf5ef2aSThomas Huth /* doz - doz. */ 4604fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 4605fcf5ef2aSThomas Huth { 4606fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4607fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4608fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4609fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4610fcf5ef2aSThomas Huth tcg_gen_br(l2); 4611fcf5ef2aSThomas Huth gen_set_label(l1); 4612fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4613fcf5ef2aSThomas Huth gen_set_label(l2); 4614fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4615fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4616fcf5ef2aSThomas Huth } 4617fcf5ef2aSThomas Huth 4618fcf5ef2aSThomas Huth /* dozo - dozo. */ 4619fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 4620fcf5ef2aSThomas Huth { 4621fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4622fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4623fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4624fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4625fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4626fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4627fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4628fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4629fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4630fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4631fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4632fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 4633fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4634fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4635fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4636fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4637fcf5ef2aSThomas Huth tcg_gen_br(l2); 4638fcf5ef2aSThomas Huth gen_set_label(l1); 4639fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4640fcf5ef2aSThomas Huth gen_set_label(l2); 4641fcf5ef2aSThomas Huth tcg_temp_free(t0); 4642fcf5ef2aSThomas Huth tcg_temp_free(t1); 4643fcf5ef2aSThomas Huth tcg_temp_free(t2); 4644fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4645fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4646fcf5ef2aSThomas Huth } 4647fcf5ef2aSThomas Huth 4648fcf5ef2aSThomas Huth /* dozi */ 4649fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 4650fcf5ef2aSThomas Huth { 4651fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 4652fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4653fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4654fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 4655fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 4656fcf5ef2aSThomas Huth tcg_gen_br(l2); 4657fcf5ef2aSThomas Huth gen_set_label(l1); 4658fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4659fcf5ef2aSThomas Huth gen_set_label(l2); 4660fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4661fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4662fcf5ef2aSThomas Huth } 4663fcf5ef2aSThomas Huth 4664fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 4665fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 4666fcf5ef2aSThomas Huth { 4667fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4668fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 4669fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 4670fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 4671fcf5ef2aSThomas Huth 4672fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4673fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 4674fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4675fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4676fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4677fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 4678fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 4679fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4680fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 4681fcf5ef2aSThomas Huth tcg_temp_free(t0); 4682fcf5ef2aSThomas Huth } 4683fcf5ef2aSThomas Huth 4684fcf5ef2aSThomas Huth /* maskg - maskg. */ 4685fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 4686fcf5ef2aSThomas Huth { 4687fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4688fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4689fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4690fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4691fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 4692fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 4693fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4694fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 4695fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 4696fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 4697fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 4698fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 4699fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4700fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4701fcf5ef2aSThomas Huth gen_set_label(l1); 4702fcf5ef2aSThomas Huth tcg_temp_free(t0); 4703fcf5ef2aSThomas Huth tcg_temp_free(t1); 4704fcf5ef2aSThomas Huth tcg_temp_free(t2); 4705fcf5ef2aSThomas Huth tcg_temp_free(t3); 4706fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4707fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4708fcf5ef2aSThomas Huth } 4709fcf5ef2aSThomas Huth 4710fcf5ef2aSThomas Huth /* maskir - maskir. */ 4711fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 4712fcf5ef2aSThomas Huth { 4713fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4714fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4715fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4716fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4717fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4718fcf5ef2aSThomas Huth tcg_temp_free(t0); 4719fcf5ef2aSThomas Huth tcg_temp_free(t1); 4720fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4721fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4722fcf5ef2aSThomas Huth } 4723fcf5ef2aSThomas Huth 4724fcf5ef2aSThomas Huth /* mul - mul. */ 4725fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 4726fcf5ef2aSThomas Huth { 4727fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 4728fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 4729fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4730fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4731fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4732fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 4733fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 4734fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 4735fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 4736fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4737fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 4738fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 4739fcf5ef2aSThomas Huth tcg_temp_free(t2); 4740fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4741fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4742fcf5ef2aSThomas Huth } 4743fcf5ef2aSThomas Huth 4744fcf5ef2aSThomas Huth /* mulo - mulo. */ 4745fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 4746fcf5ef2aSThomas Huth { 4747fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4748fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 4749fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 4750fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4751fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4752fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4753fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4754fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4755fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 4756fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 4757fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 4758fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 4759fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4760fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 4761fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 4762fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4763fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4764fcf5ef2aSThomas Huth gen_set_label(l1); 4765fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 4766fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 4767fcf5ef2aSThomas Huth tcg_temp_free(t2); 4768fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4769fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4770fcf5ef2aSThomas Huth } 4771fcf5ef2aSThomas Huth 4772fcf5ef2aSThomas Huth /* nabs - nabs. */ 4773fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 4774fcf5ef2aSThomas Huth { 4775fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4776fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4777fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4778fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4779fcf5ef2aSThomas Huth tcg_gen_br(l2); 4780fcf5ef2aSThomas Huth gen_set_label(l1); 4781fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4782fcf5ef2aSThomas Huth gen_set_label(l2); 4783fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4784fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4785fcf5ef2aSThomas Huth } 4786fcf5ef2aSThomas Huth 4787fcf5ef2aSThomas Huth /* nabso - nabso. */ 4788fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 4789fcf5ef2aSThomas Huth { 4790fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4791fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4792fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4793fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4794fcf5ef2aSThomas Huth tcg_gen_br(l2); 4795fcf5ef2aSThomas Huth gen_set_label(l1); 4796fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4797fcf5ef2aSThomas Huth gen_set_label(l2); 4798fcf5ef2aSThomas Huth /* nabs never overflows */ 4799fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4800fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4801fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4802fcf5ef2aSThomas Huth } 4803fcf5ef2aSThomas Huth 4804fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 4805fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 4806fcf5ef2aSThomas Huth { 4807fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 4808fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 4809fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4810fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4811fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4812fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 4813fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 4814fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 4815fcf5ef2aSThomas Huth tcg_temp_free(t0); 4816fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4817fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4818fcf5ef2aSThomas Huth } 4819fcf5ef2aSThomas Huth 4820fcf5ef2aSThomas Huth /* rrib - rrib. */ 4821fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 4822fcf5ef2aSThomas Huth { 4823fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4824fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4825fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4826fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 4827fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 4828fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4829fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 4830fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 4831fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4832fcf5ef2aSThomas Huth tcg_temp_free(t0); 4833fcf5ef2aSThomas Huth tcg_temp_free(t1); 4834fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4835fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4836fcf5ef2aSThomas Huth } 4837fcf5ef2aSThomas Huth 4838fcf5ef2aSThomas Huth /* sle - sle. */ 4839fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 4840fcf5ef2aSThomas Huth { 4841fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4842fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4843fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4844fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4845fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 4846fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4847fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 4848fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4849fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 4850fcf5ef2aSThomas Huth tcg_temp_free(t0); 4851fcf5ef2aSThomas Huth tcg_temp_free(t1); 4852fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4853fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4854fcf5ef2aSThomas Huth } 4855fcf5ef2aSThomas Huth 4856fcf5ef2aSThomas Huth /* sleq - sleq. */ 4857fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 4858fcf5ef2aSThomas Huth { 4859fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4860fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4861fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4862fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4863fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 4864fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 4865fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4866fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 4867fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 4868fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 4869fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 4870fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4871fcf5ef2aSThomas Huth tcg_temp_free(t0); 4872fcf5ef2aSThomas Huth tcg_temp_free(t1); 4873fcf5ef2aSThomas Huth tcg_temp_free(t2); 4874fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4875fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4876fcf5ef2aSThomas Huth } 4877fcf5ef2aSThomas Huth 4878fcf5ef2aSThomas Huth /* sliq - sliq. */ 4879fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 4880fcf5ef2aSThomas Huth { 4881fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 4882fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4883fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4884fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 4885fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 4886fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 4887fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4888fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 4889fcf5ef2aSThomas Huth tcg_temp_free(t0); 4890fcf5ef2aSThomas Huth tcg_temp_free(t1); 4891fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4892fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4893fcf5ef2aSThomas Huth } 4894fcf5ef2aSThomas Huth 4895fcf5ef2aSThomas Huth /* slliq - slliq. */ 4896fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 4897fcf5ef2aSThomas Huth { 4898fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 4899fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4900fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4901fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 4902fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 4903fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 4904fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 4905fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 4906fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4907fcf5ef2aSThomas Huth tcg_temp_free(t0); 4908fcf5ef2aSThomas Huth tcg_temp_free(t1); 4909fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4910fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4911fcf5ef2aSThomas Huth } 4912fcf5ef2aSThomas Huth 4913fcf5ef2aSThomas Huth /* sllq - sllq. */ 4914fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 4915fcf5ef2aSThomas Huth { 4916fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4917fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4918fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 4919fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 4920fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 4921fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 4922fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 4923fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 4924fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 4925fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 4926fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 4927fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4928fcf5ef2aSThomas Huth tcg_gen_br(l2); 4929fcf5ef2aSThomas Huth gen_set_label(l1); 4930fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 4931fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 4932fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 4933fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4934fcf5ef2aSThomas Huth gen_set_label(l2); 4935fcf5ef2aSThomas Huth tcg_temp_free(t0); 4936fcf5ef2aSThomas Huth tcg_temp_free(t1); 4937fcf5ef2aSThomas Huth tcg_temp_free(t2); 4938fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4939fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4940fcf5ef2aSThomas Huth } 4941fcf5ef2aSThomas Huth 4942fcf5ef2aSThomas Huth /* slq - slq. */ 4943fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 4944fcf5ef2aSThomas Huth { 4945fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4946fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4947fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4948fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4949fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4950fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 4951fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4952fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 4953fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 4954fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 4955fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4956fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 4957fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 4958fcf5ef2aSThomas Huth gen_set_label(l1); 4959fcf5ef2aSThomas Huth tcg_temp_free(t0); 4960fcf5ef2aSThomas Huth tcg_temp_free(t1); 4961fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4962fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4963fcf5ef2aSThomas Huth } 4964fcf5ef2aSThomas Huth 4965fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 4966fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 4967fcf5ef2aSThomas Huth { 4968fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 4969fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4970fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4971fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4972fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 4973fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 4974fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 4975fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 4976fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4977fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 4978fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 4979fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 4980fcf5ef2aSThomas Huth gen_set_label(l1); 4981fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 4982fcf5ef2aSThomas Huth tcg_temp_free(t0); 4983fcf5ef2aSThomas Huth tcg_temp_free(t1); 4984fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4985fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4986fcf5ef2aSThomas Huth } 4987fcf5ef2aSThomas Huth 4988fcf5ef2aSThomas Huth /* sraq - sraq. */ 4989fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 4990fcf5ef2aSThomas Huth { 4991fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4992fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4993fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4994fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 4995fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 4996fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 4997fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 4998fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 4999fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5000fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5001fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5002fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5003fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5004fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5005fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5006fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5007fcf5ef2aSThomas Huth gen_set_label(l1); 5008fcf5ef2aSThomas Huth tcg_temp_free(t0); 5009fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5010fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5011fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5012fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5013fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5014fcf5ef2aSThomas Huth gen_set_label(l2); 5015fcf5ef2aSThomas Huth tcg_temp_free(t1); 5016fcf5ef2aSThomas Huth tcg_temp_free(t2); 5017fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5018fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5019fcf5ef2aSThomas Huth } 5020fcf5ef2aSThomas Huth 5021fcf5ef2aSThomas Huth /* sre - sre. */ 5022fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5023fcf5ef2aSThomas Huth { 5024fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5025fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5026fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5027fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5028fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5029fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5030fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5031fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5032fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5033fcf5ef2aSThomas Huth tcg_temp_free(t0); 5034fcf5ef2aSThomas Huth tcg_temp_free(t1); 5035fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5036fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5037fcf5ef2aSThomas Huth } 5038fcf5ef2aSThomas Huth 5039fcf5ef2aSThomas Huth /* srea - srea. */ 5040fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5041fcf5ef2aSThomas Huth { 5042fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5043fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5044fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5045fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5046fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5047fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5048fcf5ef2aSThomas Huth tcg_temp_free(t0); 5049fcf5ef2aSThomas Huth tcg_temp_free(t1); 5050fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5051fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5052fcf5ef2aSThomas Huth } 5053fcf5ef2aSThomas Huth 5054fcf5ef2aSThomas Huth /* sreq */ 5055fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5056fcf5ef2aSThomas Huth { 5057fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5058fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5059fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5060fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5061fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5062fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5063fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5064fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5065fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5066fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5067fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5068fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5069fcf5ef2aSThomas Huth tcg_temp_free(t0); 5070fcf5ef2aSThomas Huth tcg_temp_free(t1); 5071fcf5ef2aSThomas Huth tcg_temp_free(t2); 5072fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5073fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5074fcf5ef2aSThomas Huth } 5075fcf5ef2aSThomas Huth 5076fcf5ef2aSThomas Huth /* sriq */ 5077fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5078fcf5ef2aSThomas Huth { 5079fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5080fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5081fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5082fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5083fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5084fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5085fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5086fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5087fcf5ef2aSThomas Huth tcg_temp_free(t0); 5088fcf5ef2aSThomas Huth tcg_temp_free(t1); 5089fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5090fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5091fcf5ef2aSThomas Huth } 5092fcf5ef2aSThomas Huth 5093fcf5ef2aSThomas Huth /* srliq */ 5094fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5095fcf5ef2aSThomas Huth { 5096fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5097fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5098fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5099fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5100fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5101fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5102fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5103fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5104fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5105fcf5ef2aSThomas Huth tcg_temp_free(t0); 5106fcf5ef2aSThomas Huth tcg_temp_free(t1); 5107fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5108fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5109fcf5ef2aSThomas Huth } 5110fcf5ef2aSThomas Huth 5111fcf5ef2aSThomas Huth /* srlq */ 5112fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5113fcf5ef2aSThomas Huth { 5114fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5115fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5116fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5117fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5118fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5119fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5120fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5121fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5122fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5123fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5124fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5125fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5126fcf5ef2aSThomas Huth tcg_gen_br(l2); 5127fcf5ef2aSThomas Huth gen_set_label(l1); 5128fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5129fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5130fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5131fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5132fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5133fcf5ef2aSThomas Huth gen_set_label(l2); 5134fcf5ef2aSThomas Huth tcg_temp_free(t0); 5135fcf5ef2aSThomas Huth tcg_temp_free(t1); 5136fcf5ef2aSThomas Huth tcg_temp_free(t2); 5137fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5138fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5139fcf5ef2aSThomas Huth } 5140fcf5ef2aSThomas Huth 5141fcf5ef2aSThomas Huth /* srq */ 5142fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5143fcf5ef2aSThomas Huth { 5144fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5145fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5146fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5147fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5148fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5149fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5150fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5151fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5152fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5153fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5154fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5155fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5156fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5157fcf5ef2aSThomas Huth gen_set_label(l1); 5158fcf5ef2aSThomas Huth tcg_temp_free(t0); 5159fcf5ef2aSThomas Huth tcg_temp_free(t1); 5160fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5161fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5162fcf5ef2aSThomas Huth } 5163fcf5ef2aSThomas Huth 5164fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5165fcf5ef2aSThomas Huth 5166fcf5ef2aSThomas Huth /* dsa */ 5167fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5168fcf5ef2aSThomas Huth { 5169fcf5ef2aSThomas Huth /* XXX: TODO */ 5170fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5171fcf5ef2aSThomas Huth } 5172fcf5ef2aSThomas Huth 5173fcf5ef2aSThomas Huth /* esa */ 5174fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5175fcf5ef2aSThomas Huth { 5176fcf5ef2aSThomas Huth /* XXX: TODO */ 5177fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5178fcf5ef2aSThomas Huth } 5179fcf5ef2aSThomas Huth 5180fcf5ef2aSThomas Huth /* mfrom */ 5181fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5182fcf5ef2aSThomas Huth { 5183fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5184fcf5ef2aSThomas Huth GEN_PRIV; 5185fcf5ef2aSThomas Huth #else 5186fcf5ef2aSThomas Huth CHK_SV; 5187fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5188fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5189fcf5ef2aSThomas Huth } 5190fcf5ef2aSThomas Huth 5191fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5192fcf5ef2aSThomas Huth 5193fcf5ef2aSThomas Huth /* tlbld */ 5194fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5195fcf5ef2aSThomas Huth { 5196fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5197fcf5ef2aSThomas Huth GEN_PRIV; 5198fcf5ef2aSThomas Huth #else 5199fcf5ef2aSThomas Huth CHK_SV; 5200fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5201fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5202fcf5ef2aSThomas Huth } 5203fcf5ef2aSThomas Huth 5204fcf5ef2aSThomas Huth /* tlbli */ 5205fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5206fcf5ef2aSThomas Huth { 5207fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5208fcf5ef2aSThomas Huth GEN_PRIV; 5209fcf5ef2aSThomas Huth #else 5210fcf5ef2aSThomas Huth CHK_SV; 5211fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5212fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5213fcf5ef2aSThomas Huth } 5214fcf5ef2aSThomas Huth 5215fcf5ef2aSThomas Huth /* 74xx TLB management */ 5216fcf5ef2aSThomas Huth 5217fcf5ef2aSThomas Huth /* tlbld */ 5218fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5219fcf5ef2aSThomas Huth { 5220fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5221fcf5ef2aSThomas Huth GEN_PRIV; 5222fcf5ef2aSThomas Huth #else 5223fcf5ef2aSThomas Huth CHK_SV; 5224fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5225fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5226fcf5ef2aSThomas Huth } 5227fcf5ef2aSThomas Huth 5228fcf5ef2aSThomas Huth /* tlbli */ 5229fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5230fcf5ef2aSThomas Huth { 5231fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5232fcf5ef2aSThomas Huth GEN_PRIV; 5233fcf5ef2aSThomas Huth #else 5234fcf5ef2aSThomas Huth CHK_SV; 5235fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5236fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5237fcf5ef2aSThomas Huth } 5238fcf5ef2aSThomas Huth 5239fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5240fcf5ef2aSThomas Huth 5241fcf5ef2aSThomas Huth /* clf */ 5242fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5243fcf5ef2aSThomas Huth { 5244fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5245fcf5ef2aSThomas Huth } 5246fcf5ef2aSThomas Huth 5247fcf5ef2aSThomas Huth /* cli */ 5248fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5249fcf5ef2aSThomas Huth { 5250fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5251fcf5ef2aSThomas Huth GEN_PRIV; 5252fcf5ef2aSThomas Huth #else 5253fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5254fcf5ef2aSThomas Huth CHK_SV; 5255fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5256fcf5ef2aSThomas Huth } 5257fcf5ef2aSThomas Huth 5258fcf5ef2aSThomas Huth /* dclst */ 5259fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5260fcf5ef2aSThomas Huth { 5261fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5262fcf5ef2aSThomas Huth } 5263fcf5ef2aSThomas Huth 5264fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5265fcf5ef2aSThomas Huth { 5266fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5267fcf5ef2aSThomas Huth GEN_PRIV; 5268fcf5ef2aSThomas Huth #else 5269fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5270fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5271fcf5ef2aSThomas Huth TCGv t0; 5272fcf5ef2aSThomas Huth 5273fcf5ef2aSThomas Huth CHK_SV; 5274fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5275fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5276fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, t0, 28); 5277fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 5278fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5279fcf5ef2aSThomas Huth tcg_temp_free(t0); 5280fcf5ef2aSThomas Huth if (ra != 0 && ra != rd) 5281fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5282fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5283fcf5ef2aSThomas Huth } 5284fcf5ef2aSThomas Huth 5285fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5286fcf5ef2aSThomas Huth { 5287fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5288fcf5ef2aSThomas Huth GEN_PRIV; 5289fcf5ef2aSThomas Huth #else 5290fcf5ef2aSThomas Huth TCGv t0; 5291fcf5ef2aSThomas Huth 5292fcf5ef2aSThomas Huth CHK_SV; 5293fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5294fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5295fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5296fcf5ef2aSThomas Huth tcg_temp_free(t0); 5297fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5298fcf5ef2aSThomas Huth } 5299fcf5ef2aSThomas Huth 5300fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5301fcf5ef2aSThomas Huth { 5302fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5303fcf5ef2aSThomas Huth GEN_PRIV; 5304fcf5ef2aSThomas Huth #else 5305fcf5ef2aSThomas Huth CHK_SV; 5306fcf5ef2aSThomas Huth 5307fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5308fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5309fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5310fcf5ef2aSThomas Huth } 5311fcf5ef2aSThomas Huth 5312fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5313fcf5ef2aSThomas Huth 5314fcf5ef2aSThomas Huth /* BookE specific instructions */ 5315fcf5ef2aSThomas Huth 5316fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5317fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5318fcf5ef2aSThomas Huth { 5319fcf5ef2aSThomas Huth /* XXX: TODO */ 5320fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5321fcf5ef2aSThomas Huth } 5322fcf5ef2aSThomas Huth 5323fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5324fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5325fcf5ef2aSThomas Huth { 5326fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5327fcf5ef2aSThomas Huth GEN_PRIV; 5328fcf5ef2aSThomas Huth #else 5329fcf5ef2aSThomas Huth TCGv t0; 5330fcf5ef2aSThomas Huth 5331fcf5ef2aSThomas Huth CHK_SV; 5332fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5333fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5334fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5335fcf5ef2aSThomas Huth tcg_temp_free(t0); 5336fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5337fcf5ef2aSThomas Huth } 5338fcf5ef2aSThomas Huth 5339fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5340fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5341fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5342fcf5ef2aSThomas Huth { 5343fcf5ef2aSThomas Huth TCGv t0, t1; 5344fcf5ef2aSThomas Huth 5345fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5346fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5347fcf5ef2aSThomas Huth 5348fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5349fcf5ef2aSThomas Huth case 0x05: 5350fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5351fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5352fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5353fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5354fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5355fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5356fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5357fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5358fcf5ef2aSThomas Huth break; 5359fcf5ef2aSThomas Huth case 0x04: 5360fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5361fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5362fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5363fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5364fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5365fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5366fcf5ef2aSThomas Huth break; 5367fcf5ef2aSThomas Huth case 0x01: 5368fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5369fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5370fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5371fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5372fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5373fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5374fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5375fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5376fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5377fcf5ef2aSThomas Huth break; 5378fcf5ef2aSThomas Huth case 0x00: 5379fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5380fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5381fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5382fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5383fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5384fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5385fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5386fcf5ef2aSThomas Huth break; 5387fcf5ef2aSThomas Huth case 0x0D: 5388fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5389fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5390fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5391fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5392fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5393fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5394fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5395fcf5ef2aSThomas Huth break; 5396fcf5ef2aSThomas Huth case 0x0C: 5397fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5398fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5399fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5400fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5401fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5402fcf5ef2aSThomas Huth break; 5403fcf5ef2aSThomas Huth } 5404fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5405fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5406fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5407fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5408fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5409fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5410fcf5ef2aSThomas Huth } else { 5411fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5412fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5413fcf5ef2aSThomas Huth } 5414fcf5ef2aSThomas Huth 5415fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5416fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5417fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5418fcf5ef2aSThomas Huth 5419fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5420fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5421fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5422fcf5ef2aSThomas Huth } 5423fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5424fcf5ef2aSThomas Huth /* Signed */ 5425fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5426fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5427fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5428fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5429fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5430fcf5ef2aSThomas Huth /* Saturate */ 5431fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5432fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5433fcf5ef2aSThomas Huth } 5434fcf5ef2aSThomas Huth } else { 5435fcf5ef2aSThomas Huth /* Unsigned */ 5436fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5437fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5438fcf5ef2aSThomas Huth /* Saturate */ 5439fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5440fcf5ef2aSThomas Huth } 5441fcf5ef2aSThomas Huth } 5442fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5443fcf5ef2aSThomas Huth /* Check overflow */ 5444fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5445fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5446fcf5ef2aSThomas Huth } 5447fcf5ef2aSThomas Huth gen_set_label(l1); 5448fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5449fcf5ef2aSThomas Huth } 5450fcf5ef2aSThomas Huth } else { 5451fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5452fcf5ef2aSThomas Huth } 5453fcf5ef2aSThomas Huth tcg_temp_free(t0); 5454fcf5ef2aSThomas Huth tcg_temp_free(t1); 5455fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5456fcf5ef2aSThomas Huth /* Update Rc0 */ 5457fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5458fcf5ef2aSThomas Huth } 5459fcf5ef2aSThomas Huth } 5460fcf5ef2aSThomas Huth 5461fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5462fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5463fcf5ef2aSThomas Huth { \ 5464fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5465fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5466fcf5ef2aSThomas Huth } 5467fcf5ef2aSThomas Huth 5468fcf5ef2aSThomas Huth /* macchw - macchw. */ 5469fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5470fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5471fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5472fcf5ef2aSThomas Huth /* macchws - macchws. */ 5473fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5474fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5475fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5476fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5477fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5478fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5479fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5480fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5481fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5482fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5483fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5484fcf5ef2aSThomas Huth /* machhw - machhw. */ 5485fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5486fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5487fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5488fcf5ef2aSThomas Huth /* machhws - machhws. */ 5489fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5490fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5491fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5492fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5493fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5494fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5495fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5496fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5497fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5498fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5499fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5500fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5501fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5502fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5503fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5504fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5505fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5506fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5507fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5508fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5509fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5510fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5511fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5512fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5513fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5514fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5515fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5516fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5517fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5518fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5519fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5520fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5521fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5522fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5523fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5524fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5525fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5526fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5527fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5528fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5529fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5530fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5531fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5532fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5533fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5534fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5535fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5536fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5537fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5538fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5539fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5540fcf5ef2aSThomas Huth 5541fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5542fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5543fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5544fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5545fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5546fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5547fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5549fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5551fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5553fcf5ef2aSThomas Huth 5554fcf5ef2aSThomas Huth /* mfdcr */ 5555fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5556fcf5ef2aSThomas Huth { 5557fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5558fcf5ef2aSThomas Huth GEN_PRIV; 5559fcf5ef2aSThomas Huth #else 5560fcf5ef2aSThomas Huth TCGv dcrn; 5561fcf5ef2aSThomas Huth 5562fcf5ef2aSThomas Huth CHK_SV; 5563fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5564fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5565fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5566fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5567fcf5ef2aSThomas Huth } 5568fcf5ef2aSThomas Huth 5569fcf5ef2aSThomas Huth /* mtdcr */ 5570fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5571fcf5ef2aSThomas Huth { 5572fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5573fcf5ef2aSThomas Huth GEN_PRIV; 5574fcf5ef2aSThomas Huth #else 5575fcf5ef2aSThomas Huth TCGv dcrn; 5576fcf5ef2aSThomas Huth 5577fcf5ef2aSThomas Huth CHK_SV; 5578fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5579fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5580fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5581fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5582fcf5ef2aSThomas Huth } 5583fcf5ef2aSThomas Huth 5584fcf5ef2aSThomas Huth /* mfdcrx */ 5585fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5586fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5587fcf5ef2aSThomas Huth { 5588fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5589fcf5ef2aSThomas Huth GEN_PRIV; 5590fcf5ef2aSThomas Huth #else 5591fcf5ef2aSThomas Huth CHK_SV; 5592fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5593fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5594fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5595fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5596fcf5ef2aSThomas Huth } 5597fcf5ef2aSThomas Huth 5598fcf5ef2aSThomas Huth /* mtdcrx */ 5599fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5600fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5601fcf5ef2aSThomas Huth { 5602fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5603fcf5ef2aSThomas Huth GEN_PRIV; 5604fcf5ef2aSThomas Huth #else 5605fcf5ef2aSThomas Huth CHK_SV; 5606fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5607fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5608fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5609fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5610fcf5ef2aSThomas Huth } 5611fcf5ef2aSThomas Huth 5612fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 5613fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 5614fcf5ef2aSThomas Huth { 5615fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5616fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5617fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5618fcf5ef2aSThomas Huth } 5619fcf5ef2aSThomas Huth 5620fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 5621fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 5622fcf5ef2aSThomas Huth { 5623fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5624fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5625fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5626fcf5ef2aSThomas Huth } 5627fcf5ef2aSThomas Huth 5628fcf5ef2aSThomas Huth /* dccci */ 5629fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5630fcf5ef2aSThomas Huth { 5631fcf5ef2aSThomas Huth CHK_SV; 5632fcf5ef2aSThomas Huth /* interpreted as no-op */ 5633fcf5ef2aSThomas Huth } 5634fcf5ef2aSThomas Huth 5635fcf5ef2aSThomas Huth /* dcread */ 5636fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5637fcf5ef2aSThomas Huth { 5638fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5639fcf5ef2aSThomas Huth GEN_PRIV; 5640fcf5ef2aSThomas Huth #else 5641fcf5ef2aSThomas Huth TCGv EA, val; 5642fcf5ef2aSThomas Huth 5643fcf5ef2aSThomas Huth CHK_SV; 5644fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5645fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5646fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5647fcf5ef2aSThomas Huth val = tcg_temp_new(); 5648fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5649fcf5ef2aSThomas Huth tcg_temp_free(val); 5650fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5651fcf5ef2aSThomas Huth tcg_temp_free(EA); 5652fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5653fcf5ef2aSThomas Huth } 5654fcf5ef2aSThomas Huth 5655fcf5ef2aSThomas Huth /* icbt */ 5656fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5657fcf5ef2aSThomas Huth { 5658fcf5ef2aSThomas Huth /* interpreted as no-op */ 5659fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 5660fcf5ef2aSThomas Huth * but does not generate any exception 5661fcf5ef2aSThomas Huth */ 5662fcf5ef2aSThomas Huth } 5663fcf5ef2aSThomas Huth 5664fcf5ef2aSThomas Huth /* iccci */ 5665fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5666fcf5ef2aSThomas Huth { 5667fcf5ef2aSThomas Huth CHK_SV; 5668fcf5ef2aSThomas Huth /* interpreted as no-op */ 5669fcf5ef2aSThomas Huth } 5670fcf5ef2aSThomas Huth 5671fcf5ef2aSThomas Huth /* icread */ 5672fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5673fcf5ef2aSThomas Huth { 5674fcf5ef2aSThomas Huth CHK_SV; 5675fcf5ef2aSThomas Huth /* interpreted as no-op */ 5676fcf5ef2aSThomas Huth } 5677fcf5ef2aSThomas Huth 5678fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5679fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5680fcf5ef2aSThomas Huth { 5681fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5682fcf5ef2aSThomas Huth GEN_PRIV; 5683fcf5ef2aSThomas Huth #else 5684fcf5ef2aSThomas Huth CHK_SV; 5685fcf5ef2aSThomas Huth /* Restore CPU state */ 5686fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 5687fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5688fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5689fcf5ef2aSThomas Huth } 5690fcf5ef2aSThomas Huth 5691fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5692fcf5ef2aSThomas Huth { 5693fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5694fcf5ef2aSThomas Huth GEN_PRIV; 5695fcf5ef2aSThomas Huth #else 5696fcf5ef2aSThomas Huth CHK_SV; 5697fcf5ef2aSThomas Huth /* Restore CPU state */ 5698fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 5699fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5700fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5701fcf5ef2aSThomas Huth } 5702fcf5ef2aSThomas Huth 5703fcf5ef2aSThomas Huth /* BookE specific */ 5704fcf5ef2aSThomas Huth 5705fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5706fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5707fcf5ef2aSThomas Huth { 5708fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5709fcf5ef2aSThomas Huth GEN_PRIV; 5710fcf5ef2aSThomas Huth #else 5711fcf5ef2aSThomas Huth CHK_SV; 5712fcf5ef2aSThomas Huth /* Restore CPU state */ 5713fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 5714fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5715fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5716fcf5ef2aSThomas Huth } 5717fcf5ef2aSThomas Huth 5718fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5719fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5720fcf5ef2aSThomas Huth { 5721fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5722fcf5ef2aSThomas Huth GEN_PRIV; 5723fcf5ef2aSThomas Huth #else 5724fcf5ef2aSThomas Huth CHK_SV; 5725fcf5ef2aSThomas Huth /* Restore CPU state */ 5726fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 5727fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5728fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5729fcf5ef2aSThomas Huth } 5730fcf5ef2aSThomas Huth 5731fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5732fcf5ef2aSThomas Huth 5733fcf5ef2aSThomas Huth /* tlbre */ 5734fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5735fcf5ef2aSThomas Huth { 5736fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5737fcf5ef2aSThomas Huth GEN_PRIV; 5738fcf5ef2aSThomas Huth #else 5739fcf5ef2aSThomas Huth CHK_SV; 5740fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5741fcf5ef2aSThomas Huth case 0: 5742fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5743fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5744fcf5ef2aSThomas Huth break; 5745fcf5ef2aSThomas Huth case 1: 5746fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5747fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5748fcf5ef2aSThomas Huth break; 5749fcf5ef2aSThomas Huth default: 5750fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5751fcf5ef2aSThomas Huth break; 5752fcf5ef2aSThomas Huth } 5753fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5754fcf5ef2aSThomas Huth } 5755fcf5ef2aSThomas Huth 5756fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5757fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5758fcf5ef2aSThomas Huth { 5759fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5760fcf5ef2aSThomas Huth GEN_PRIV; 5761fcf5ef2aSThomas Huth #else 5762fcf5ef2aSThomas Huth TCGv t0; 5763fcf5ef2aSThomas Huth 5764fcf5ef2aSThomas Huth CHK_SV; 5765fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5766fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5767fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5768fcf5ef2aSThomas Huth tcg_temp_free(t0); 5769fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5770fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5771fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5772fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5773fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5774fcf5ef2aSThomas Huth gen_set_label(l1); 5775fcf5ef2aSThomas Huth } 5776fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5777fcf5ef2aSThomas Huth } 5778fcf5ef2aSThomas Huth 5779fcf5ef2aSThomas Huth /* tlbwe */ 5780fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5781fcf5ef2aSThomas Huth { 5782fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5783fcf5ef2aSThomas Huth GEN_PRIV; 5784fcf5ef2aSThomas Huth #else 5785fcf5ef2aSThomas Huth CHK_SV; 5786fcf5ef2aSThomas Huth 5787fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5788fcf5ef2aSThomas Huth case 0: 5789fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5790fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5791fcf5ef2aSThomas Huth break; 5792fcf5ef2aSThomas Huth case 1: 5793fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5794fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5795fcf5ef2aSThomas Huth break; 5796fcf5ef2aSThomas Huth default: 5797fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5798fcf5ef2aSThomas Huth break; 5799fcf5ef2aSThomas Huth } 5800fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5801fcf5ef2aSThomas Huth } 5802fcf5ef2aSThomas Huth 5803fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5804fcf5ef2aSThomas Huth 5805fcf5ef2aSThomas Huth /* tlbre */ 5806fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5807fcf5ef2aSThomas Huth { 5808fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5809fcf5ef2aSThomas Huth GEN_PRIV; 5810fcf5ef2aSThomas Huth #else 5811fcf5ef2aSThomas Huth CHK_SV; 5812fcf5ef2aSThomas Huth 5813fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5814fcf5ef2aSThomas Huth case 0: 5815fcf5ef2aSThomas Huth case 1: 5816fcf5ef2aSThomas Huth case 2: 5817fcf5ef2aSThomas Huth { 5818fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5819fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5820fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5821fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5822fcf5ef2aSThomas Huth } 5823fcf5ef2aSThomas Huth break; 5824fcf5ef2aSThomas Huth default: 5825fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5826fcf5ef2aSThomas Huth break; 5827fcf5ef2aSThomas Huth } 5828fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5829fcf5ef2aSThomas Huth } 5830fcf5ef2aSThomas Huth 5831fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5832fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5833fcf5ef2aSThomas Huth { 5834fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5835fcf5ef2aSThomas Huth GEN_PRIV; 5836fcf5ef2aSThomas Huth #else 5837fcf5ef2aSThomas Huth TCGv t0; 5838fcf5ef2aSThomas Huth 5839fcf5ef2aSThomas Huth CHK_SV; 5840fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5841fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5842fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5843fcf5ef2aSThomas Huth tcg_temp_free(t0); 5844fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5845fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5846fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5847fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5848fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5849fcf5ef2aSThomas Huth gen_set_label(l1); 5850fcf5ef2aSThomas Huth } 5851fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5852fcf5ef2aSThomas Huth } 5853fcf5ef2aSThomas Huth 5854fcf5ef2aSThomas Huth /* tlbwe */ 5855fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5856fcf5ef2aSThomas Huth { 5857fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5858fcf5ef2aSThomas Huth GEN_PRIV; 5859fcf5ef2aSThomas Huth #else 5860fcf5ef2aSThomas Huth CHK_SV; 5861fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5862fcf5ef2aSThomas Huth case 0: 5863fcf5ef2aSThomas Huth case 1: 5864fcf5ef2aSThomas Huth case 2: 5865fcf5ef2aSThomas Huth { 5866fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5867fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5868fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5869fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5870fcf5ef2aSThomas Huth } 5871fcf5ef2aSThomas Huth break; 5872fcf5ef2aSThomas Huth default: 5873fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5874fcf5ef2aSThomas Huth break; 5875fcf5ef2aSThomas Huth } 5876fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5877fcf5ef2aSThomas Huth } 5878fcf5ef2aSThomas Huth 5879fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5880fcf5ef2aSThomas Huth 5881fcf5ef2aSThomas Huth /* tlbre */ 5882fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5883fcf5ef2aSThomas Huth { 5884fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5885fcf5ef2aSThomas Huth GEN_PRIV; 5886fcf5ef2aSThomas Huth #else 5887fcf5ef2aSThomas Huth CHK_SV; 5888fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5889fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5890fcf5ef2aSThomas Huth } 5891fcf5ef2aSThomas Huth 5892fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5893fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5894fcf5ef2aSThomas Huth { 5895fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5896fcf5ef2aSThomas Huth GEN_PRIV; 5897fcf5ef2aSThomas Huth #else 5898fcf5ef2aSThomas Huth TCGv t0; 5899fcf5ef2aSThomas Huth 5900fcf5ef2aSThomas Huth CHK_SV; 5901fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5902fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5903fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 5904fcf5ef2aSThomas Huth } else { 5905fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 5906fcf5ef2aSThomas Huth } 5907fcf5ef2aSThomas Huth 5908fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 5909fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5910fcf5ef2aSThomas Huth tcg_temp_free(t0); 5911fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5912fcf5ef2aSThomas Huth } 5913fcf5ef2aSThomas Huth 5914fcf5ef2aSThomas Huth /* tlbwe */ 5915fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5916fcf5ef2aSThomas Huth { 5917fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5918fcf5ef2aSThomas Huth GEN_PRIV; 5919fcf5ef2aSThomas Huth #else 5920fcf5ef2aSThomas Huth CHK_SV; 5921fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5922fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5923fcf5ef2aSThomas Huth } 5924fcf5ef2aSThomas Huth 5925fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5926fcf5ef2aSThomas Huth { 5927fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5928fcf5ef2aSThomas Huth GEN_PRIV; 5929fcf5ef2aSThomas Huth #else 5930fcf5ef2aSThomas Huth TCGv t0; 5931fcf5ef2aSThomas Huth 5932fcf5ef2aSThomas Huth CHK_SV; 5933fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5934fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5935fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5936fcf5ef2aSThomas Huth tcg_temp_free(t0); 5937fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5938fcf5ef2aSThomas Huth } 5939fcf5ef2aSThomas Huth 5940fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5941fcf5ef2aSThomas Huth { 5942fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5943fcf5ef2aSThomas Huth GEN_PRIV; 5944fcf5ef2aSThomas Huth #else 5945fcf5ef2aSThomas Huth TCGv t0; 5946fcf5ef2aSThomas Huth 5947fcf5ef2aSThomas Huth CHK_SV; 5948fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5949fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5950fcf5ef2aSThomas Huth 5951fcf5ef2aSThomas Huth switch((ctx->opcode >> 21) & 0x3) { 5952fcf5ef2aSThomas Huth case 0: 5953fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 5954fcf5ef2aSThomas Huth break; 5955fcf5ef2aSThomas Huth case 1: 5956fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 5957fcf5ef2aSThomas Huth break; 5958fcf5ef2aSThomas Huth case 3: 5959fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 5960fcf5ef2aSThomas Huth break; 5961fcf5ef2aSThomas Huth default: 5962fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5963fcf5ef2aSThomas Huth break; 5964fcf5ef2aSThomas Huth } 5965fcf5ef2aSThomas Huth 5966fcf5ef2aSThomas Huth tcg_temp_free(t0); 5967fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5968fcf5ef2aSThomas Huth } 5969fcf5ef2aSThomas Huth 5970fcf5ef2aSThomas Huth 5971fcf5ef2aSThomas Huth /* wrtee */ 5972fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 5973fcf5ef2aSThomas Huth { 5974fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5975fcf5ef2aSThomas Huth GEN_PRIV; 5976fcf5ef2aSThomas Huth #else 5977fcf5ef2aSThomas Huth TCGv t0; 5978fcf5ef2aSThomas Huth 5979fcf5ef2aSThomas Huth CHK_SV; 5980fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5981fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5982fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5983fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5984fcf5ef2aSThomas Huth tcg_temp_free(t0); 5985fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception 5986fcf5ef2aSThomas Huth * if we just set msr_ee to 1 5987fcf5ef2aSThomas Huth */ 5988fcf5ef2aSThomas Huth gen_stop_exception(ctx); 5989fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5990fcf5ef2aSThomas Huth } 5991fcf5ef2aSThomas Huth 5992fcf5ef2aSThomas Huth /* wrteei */ 5993fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 5994fcf5ef2aSThomas Huth { 5995fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5996fcf5ef2aSThomas Huth GEN_PRIV; 5997fcf5ef2aSThomas Huth #else 5998fcf5ef2aSThomas Huth CHK_SV; 5999fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6000fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6001fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6002fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6003fcf5ef2aSThomas Huth } else { 6004fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6005fcf5ef2aSThomas Huth } 6006fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6007fcf5ef2aSThomas Huth } 6008fcf5ef2aSThomas Huth 6009fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6010fcf5ef2aSThomas Huth 6011fcf5ef2aSThomas Huth /* dlmzb */ 6012fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6013fcf5ef2aSThomas Huth { 6014fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6015fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6016fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6017fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6018fcf5ef2aSThomas Huth } 6019fcf5ef2aSThomas Huth 6020fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6021fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6022fcf5ef2aSThomas Huth { 6023fcf5ef2aSThomas Huth /* interpreted as no-op */ 6024fcf5ef2aSThomas Huth } 6025fcf5ef2aSThomas Huth 6026fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6027fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6028fcf5ef2aSThomas Huth { 6029fcf5ef2aSThomas Huth /* interpreted as no-op */ 6030fcf5ef2aSThomas Huth } 6031fcf5ef2aSThomas Huth 6032fcf5ef2aSThomas Huth /* icbt */ 6033fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6034fcf5ef2aSThomas Huth { 6035fcf5ef2aSThomas Huth /* interpreted as no-op */ 6036fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6037fcf5ef2aSThomas Huth * but does not generate any exception 6038fcf5ef2aSThomas Huth */ 6039fcf5ef2aSThomas Huth } 6040fcf5ef2aSThomas Huth 6041fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6042fcf5ef2aSThomas Huth 6043fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6044fcf5ef2aSThomas Huth { 6045fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6046fcf5ef2aSThomas Huth GEN_PRIV; 6047fcf5ef2aSThomas Huth #else 6048fcf5ef2aSThomas Huth CHK_SV; 6049fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6050fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6051fcf5ef2aSThomas Huth } 6052fcf5ef2aSThomas Huth 6053fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6054fcf5ef2aSThomas Huth { 6055fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6056fcf5ef2aSThomas Huth GEN_PRIV; 6057fcf5ef2aSThomas Huth #else 6058fcf5ef2aSThomas Huth CHK_SV; 6059fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6060fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6061fcf5ef2aSThomas Huth } 6062fcf5ef2aSThomas Huth 6063fcf5ef2aSThomas Huth 6064fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6065fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6066fcf5ef2aSThomas Huth { 6067fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6068fcf5ef2aSThomas Huth 6069fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6070fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6071fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6072fcf5ef2aSThomas Huth } 6073fcf5ef2aSThomas Huth 6074fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6075fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6076fcf5ef2aSThomas Huth { 6077fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6078fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6079fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6080fcf5ef2aSThomas Huth 6081fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6082fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6083fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6084fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6085fcf5ef2aSThomas Huth } else { 6086fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6087fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6088fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6089fcf5ef2aSThomas Huth } 6090fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6091fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6092fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6093fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6094fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6095fcf5ef2aSThomas Huth } 6096fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6097fcf5ef2aSThomas Huth 6098fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6099fcf5ef2aSThomas Huth { 6100fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6101fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6102fcf5ef2aSThomas Huth return; 6103fcf5ef2aSThomas Huth } 6104fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6105fcf5ef2aSThomas Huth } 6106fcf5ef2aSThomas Huth 6107fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6108fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6109fcf5ef2aSThomas Huth { \ 6110fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6111fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6112fcf5ef2aSThomas Huth return; \ 6113fcf5ef2aSThomas Huth } \ 6114fcf5ef2aSThomas Huth /* Because tbegin always fails in QEMU, these user \ 6115fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6116fcf5ef2aSThomas Huth * \ 6117fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6118fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6119fcf5ef2aSThomas Huth */ \ 6120fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6121fcf5ef2aSThomas Huth } 6122fcf5ef2aSThomas Huth 6123fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6124fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6125fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6126fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6127fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6128fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6129fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6130b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6131b8b4576eSSuraj Jitindar Singh { 6132b8b4576eSSuraj Jitindar Singh // Do Nothing 6133b8b4576eSSuraj Jitindar Singh } 6134fcf5ef2aSThomas Huth 6135*80b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 6136*80b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 6137*80b8c1eeSNikunj A Dadhania { \ 6138*80b8c1eeSNikunj A Dadhania /* Generate invalid exception until \ 6139*80b8c1eeSNikunj A Dadhania * we have an implementation of the copy \ 6140*80b8c1eeSNikunj A Dadhania * paste facility \ 6141*80b8c1eeSNikunj A Dadhania */ \ 6142*80b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 6143*80b8c1eeSNikunj A Dadhania } 6144*80b8c1eeSNikunj A Dadhania 6145*80b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 6146*80b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 6147*80b8c1eeSNikunj A Dadhania 6148fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6149fcf5ef2aSThomas Huth { 6150fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6151fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6152fcf5ef2aSThomas Huth return; 6153fcf5ef2aSThomas Huth } 6154fcf5ef2aSThomas Huth /* Because tbegin always fails, the tcheck implementation 6155fcf5ef2aSThomas Huth * is simple: 6156fcf5ef2aSThomas Huth * 6157fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6158fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6159fcf5ef2aSThomas Huth */ 6160fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6161fcf5ef2aSThomas Huth } 6162fcf5ef2aSThomas Huth 6163fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6164fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6165fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6166fcf5ef2aSThomas Huth { \ 6167fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6168fcf5ef2aSThomas Huth } 6169fcf5ef2aSThomas Huth 6170fcf5ef2aSThomas Huth #else 6171fcf5ef2aSThomas Huth 6172fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6173fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6174fcf5ef2aSThomas Huth { \ 6175fcf5ef2aSThomas Huth CHK_SV; \ 6176fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6177fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6178fcf5ef2aSThomas Huth return; \ 6179fcf5ef2aSThomas Huth } \ 6180fcf5ef2aSThomas Huth /* Because tbegin always fails, the implementation is \ 6181fcf5ef2aSThomas Huth * simple: \ 6182fcf5ef2aSThomas Huth * \ 6183fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6184fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6185fcf5ef2aSThomas Huth */ \ 6186fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6187fcf5ef2aSThomas Huth } 6188fcf5ef2aSThomas Huth 6189fcf5ef2aSThomas Huth #endif 6190fcf5ef2aSThomas Huth 6191fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6192fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6193fcf5ef2aSThomas Huth 6194fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6195fcf5ef2aSThomas Huth 6196fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6197fcf5ef2aSThomas Huth 6198fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6199fcf5ef2aSThomas Huth 6200fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6201fcf5ef2aSThomas Huth 6202fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6203fcf5ef2aSThomas Huth 62045cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 62055cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 62065cb091a4SNikunj A Dadhania { 62075cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 62085cb091a4SNikunj A Dadhania case 0: /* lfdp */ 62095cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 62105cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 62115cb091a4SNikunj A Dadhania } 62125cb091a4SNikunj A Dadhania break; 62135cb091a4SNikunj A Dadhania case 2: /* lxsd */ 62145cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 62155cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 62165cb091a4SNikunj A Dadhania } 62175cb091a4SNikunj A Dadhania break; 62185cb091a4SNikunj A Dadhania case 3: /* lxssp */ 62195cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 62205cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 62215cb091a4SNikunj A Dadhania } 62225cb091a4SNikunj A Dadhania break; 62235cb091a4SNikunj A Dadhania } 62245cb091a4SNikunj A Dadhania return gen_invalid(ctx); 62255cb091a4SNikunj A Dadhania } 62265cb091a4SNikunj A Dadhania 6227d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6228e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6229e3001664SNikunj A Dadhania { 6230e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6231e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6232e3001664SNikunj A Dadhania case 1: /* lxv */ 6233d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6234d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6235d59ba583SNikunj A Dadhania } 6236e3001664SNikunj A Dadhania break; 6237e3001664SNikunj A Dadhania case 5: /* stxv */ 6238d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6239d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6240d59ba583SNikunj A Dadhania } 6241e3001664SNikunj A Dadhania break; 6242e3001664SNikunj A Dadhania } 6243e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6244e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6245e3001664SNikunj A Dadhania case 0: /* stfdp */ 6246e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6247e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6248e3001664SNikunj A Dadhania } 6249e3001664SNikunj A Dadhania break; 6250e3001664SNikunj A Dadhania case 2: /* stxsd */ 6251e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6252e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6253e3001664SNikunj A Dadhania } 6254e3001664SNikunj A Dadhania break; 6255e3001664SNikunj A Dadhania case 3: /* stxssp */ 6256e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6257e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6258e3001664SNikunj A Dadhania } 6259e3001664SNikunj A Dadhania break; 6260e3001664SNikunj A Dadhania } 6261e3001664SNikunj A Dadhania } 6262e3001664SNikunj A Dadhania return gen_invalid(ctx); 6263e3001664SNikunj A Dadhania } 6264e3001664SNikunj A Dadhania 6265fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6266fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6267fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6268fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6269fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6270fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6271fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6272fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6273fcf5ef2aSThomas Huth #endif 6274fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6275fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6276fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6277fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6278fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6279fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6280fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6281fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6282fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6283fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6284fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6285fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6286fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6287fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6288fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6289fcf5ef2aSThomas Huth #endif 6290fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6291fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6292fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6293fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6294fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6295fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6296fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6297*80b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6298b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6299*80b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6300fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6301fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6302fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6303fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6304fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6305fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6306fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6307fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6308fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6309fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6310fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6311fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6312fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6313fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6314fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6315fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6316fcf5ef2aSThomas Huth #endif 6317fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6318fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6319fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6320fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6321fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6322fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6323fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6324fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6325fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6326fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6327fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6328fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6329fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6330fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6331fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6332fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6333fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6334fcf5ef2aSThomas Huth #endif 6335fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6336fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6337fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6338fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6339fcf5ef2aSThomas Huth #endif 63405cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 63415cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6342d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6343e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6344fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6345fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6346fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6347fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6348fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6349fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6350fcf5ef2aSThomas Huth GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), 6351fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6352fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6353fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6354fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6355a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6356a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6357fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6358fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6359fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6360fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6361a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6362a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6363fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6364fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6365fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6366fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6367fcf5ef2aSThomas Huth #endif 6368fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6369fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6370fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6371fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6372fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6373fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6374fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6375fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6376fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6377fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6378fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6379cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6380fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6381fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6382fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6383fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6384fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6385fcf5ef2aSThomas Huth #endif 6386fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6387fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6388fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6389fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6390fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6391fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6392fcf5ef2aSThomas Huth #endif 6393fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6394fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6395fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6396fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6397fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6398fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6399fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6400fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6401fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6402fcf5ef2aSThomas Huth #endif 6403fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6404fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6405fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6406fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6407fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6408fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6409fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6410fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6411fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6412fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6413fcf5ef2aSThomas Huth GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), 6414fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6415fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6416fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6417fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6418fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6419fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6420fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6421fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6422fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6423fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6424fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6425fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6426fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6427fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6428fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6429fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6430fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6431fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6432fcf5ef2aSThomas Huth #endif 6433fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6434fcf5ef2aSThomas Huth /* XXX Those instructions will need to be handled differently for 6435fcf5ef2aSThomas Huth * different ISA versions */ 6436fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6437fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6438fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6439fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6440fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6441fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6442fcf5ef2aSThomas Huth #endif 6443fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6444fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6445fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6446fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6447fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6448fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6449fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6450fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6451fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6452fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6453fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6454fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6455fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6456fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6457fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6458fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6459fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6460fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6461fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6462fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6463fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6464fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6465fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6466fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6467fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6468fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6469fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6470fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6471fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6472fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6473fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6474fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6475fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6476fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6477fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6478fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6479fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6480fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6481fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6482fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6483fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6484fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6485fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6486fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6487fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6488fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6489fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6490fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6491fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6492fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6493fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6494fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6495fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6496fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6497fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6498fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6499fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6500fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6501fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6502fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6503fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6504fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6505fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6506fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6507fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6508fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6509fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6510fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6511fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6512fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6513fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6514fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6515fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6516fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6517fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6518fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6519fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6520fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6521fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6522fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6523fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6524fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6525fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6526fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6527fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6528fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6529fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6530fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6531fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6532fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6533fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6534fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6535fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6536fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6537fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6538fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6539fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6540fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6541fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6542fcf5ef2aSThomas Huth GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6543fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6544fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6545fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6546fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6547fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6548fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6549fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6550fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6551fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6552fcf5ef2aSThomas Huth PPC2_ISA300), 6553fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6554fcf5ef2aSThomas Huth #endif 6555fcf5ef2aSThomas Huth 6556fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6557fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6558fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6559fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6560fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6561fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6562fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6563fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6564fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6565fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6566fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6567fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6568fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6569fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6570fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6571fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6572fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6573fcf5ef2aSThomas Huth 6574fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6575fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6576fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6577fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6578fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6579fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6580fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6581fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6582fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6583fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6584fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6585fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6586fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6587fcf5ef2aSThomas Huth 6588fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6589fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6590fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6591fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6592fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6593fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6594fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6595fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6596fcf5ef2aSThomas Huth 6597fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6598fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6599fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6600fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6601fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6602fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6603fcf5ef2aSThomas Huth 6604fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6605fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6606fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6607fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6608fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6609fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6610fcf5ef2aSThomas Huth #endif 6611fcf5ef2aSThomas Huth 6612fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6613fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6614fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6615fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6616fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6617fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6618fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6619fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6620fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6621fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6622fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6623fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6624fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6625fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6626fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6627fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6628fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6629fcf5ef2aSThomas Huth 6630fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6631fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6632fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6633fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6634fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6635fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6636fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6637fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6638fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6639fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6640fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6641fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6642fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6643fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6644fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6645fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6646fcf5ef2aSThomas Huth #endif 6647fcf5ef2aSThomas Huth 6648fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6649fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6650fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6651fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6652fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6653fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6654fcf5ef2aSThomas Huth PPC_64B) 6655fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6656fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6657fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6658fcf5ef2aSThomas Huth PPC_64B), \ 6659fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6660fcf5ef2aSThomas Huth PPC_64B), \ 6661fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6662fcf5ef2aSThomas Huth PPC_64B) 6663fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6664fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6665fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6666fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6667fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6668fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6669fcf5ef2aSThomas Huth #endif 6670fcf5ef2aSThomas Huth 6671fcf5ef2aSThomas Huth #undef GEN_LD 6672fcf5ef2aSThomas Huth #undef GEN_LDU 6673fcf5ef2aSThomas Huth #undef GEN_LDUX 6674fcf5ef2aSThomas Huth #undef GEN_LDX_E 6675fcf5ef2aSThomas Huth #undef GEN_LDS 6676fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 6677fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6678fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 6679fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 6680fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 6681fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6682fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6683fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6684fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 6685fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 6686fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 6687fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 6688fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 6689fcf5ef2aSThomas Huth 6690fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 6691fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 6692fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 6693fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 6694fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6695fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 6696fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 6697fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 6698fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 6699fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6700fcf5ef2aSThomas Huth 6701fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6702fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6703fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6704fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6705fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6706fcf5ef2aSThomas Huth #endif 6707fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6708fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6709fcf5ef2aSThomas Huth 6710fcf5ef2aSThomas Huth #undef GEN_ST 6711fcf5ef2aSThomas Huth #undef GEN_STU 6712fcf5ef2aSThomas Huth #undef GEN_STUX 6713fcf5ef2aSThomas Huth #undef GEN_STX_E 6714fcf5ef2aSThomas Huth #undef GEN_STS 6715fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 6716fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6717fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 6718fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 6719fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 6720fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6721fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6722fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6723fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 6724fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 6725fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 6726fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 6727fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 6728fcf5ef2aSThomas Huth 6729fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 6730fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 6731fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 6732fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6733fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 6734fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 6735fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6736fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6737fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6738fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6739fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6740fcf5ef2aSThomas Huth #endif 6741fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6742fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6743fcf5ef2aSThomas Huth 6744fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6745fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6746fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6747fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6748fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6749fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6750fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6751fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6752fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6753fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6754fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6755fcf5ef2aSThomas Huth 6756fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6757fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6758fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6759fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6760fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6761fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6762fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6763fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6764fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6765fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6766fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6767fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6768fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6769fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6770fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6771fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6772fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6773fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6774fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6775fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6776fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6777fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6778fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6779fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6780fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6781fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6782fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6783fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6784fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6785fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6786fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6787fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6788fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6789fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6790fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6791fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6792fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6793fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6794fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6795fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6796fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6797fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6798fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6799fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6800fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6801fcf5ef2aSThomas Huth 6802fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6803fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6804fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6805fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6806fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6807fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6808fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6809fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6810fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6811fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6812fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6813fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6814fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6815fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6816fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6817fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6818fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6819fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6820fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6821fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6822fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6823fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6824fcf5ef2aSThomas Huth 6825fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 6826fcf5ef2aSThomas Huth 6827fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 6828fcf5ef2aSThomas Huth 6829fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 6830fcf5ef2aSThomas Huth 6831fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 6832fcf5ef2aSThomas Huth 6833fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 6834fcf5ef2aSThomas Huth }; 6835fcf5ef2aSThomas Huth 6836fcf5ef2aSThomas Huth #include "helper_regs.h" 6837fcf5ef2aSThomas Huth #include "translate_init.c" 6838fcf5ef2aSThomas Huth 6839fcf5ef2aSThomas Huth /*****************************************************************************/ 6840fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 6841fcf5ef2aSThomas Huth void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 6842fcf5ef2aSThomas Huth int flags) 6843fcf5ef2aSThomas Huth { 6844fcf5ef2aSThomas Huth #define RGPL 4 6845fcf5ef2aSThomas Huth #define RFPL 4 6846fcf5ef2aSThomas Huth 6847fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 6848fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 6849fcf5ef2aSThomas Huth int i; 6850fcf5ef2aSThomas Huth 6851fcf5ef2aSThomas Huth cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 6852fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 6853fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 6854fcf5ef2aSThomas Huth cs->cpu_index); 6855fcf5ef2aSThomas Huth cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 6856fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 6857fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 6858fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 6859fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 6860fcf5ef2aSThomas Huth cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 6861fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 6862fcf5ef2aSThomas Huth " DECR %08" PRIu32 6863fcf5ef2aSThomas Huth #endif 6864fcf5ef2aSThomas Huth "\n", 6865fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 6866fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 6867fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 6868fcf5ef2aSThomas Huth #endif 6869fcf5ef2aSThomas Huth ); 6870fcf5ef2aSThomas Huth #endif 6871fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 6872fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == 0) 6873fcf5ef2aSThomas Huth cpu_fprintf(f, "GPR%02d", i); 6874fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 6875fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == (RGPL - 1)) 6876fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 6877fcf5ef2aSThomas Huth } 6878fcf5ef2aSThomas Huth cpu_fprintf(f, "CR "); 6879fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 6880fcf5ef2aSThomas Huth cpu_fprintf(f, "%01x", env->crf[i]); 6881fcf5ef2aSThomas Huth cpu_fprintf(f, " ["); 6882fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 6883fcf5ef2aSThomas Huth char a = '-'; 6884fcf5ef2aSThomas Huth if (env->crf[i] & 0x08) 6885fcf5ef2aSThomas Huth a = 'L'; 6886fcf5ef2aSThomas Huth else if (env->crf[i] & 0x04) 6887fcf5ef2aSThomas Huth a = 'G'; 6888fcf5ef2aSThomas Huth else if (env->crf[i] & 0x02) 6889fcf5ef2aSThomas Huth a = 'E'; 6890fcf5ef2aSThomas Huth cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 6891fcf5ef2aSThomas Huth } 6892fcf5ef2aSThomas Huth cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 6893fcf5ef2aSThomas Huth env->reserve_addr); 6894fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 6895fcf5ef2aSThomas Huth if ((i & (RFPL - 1)) == 0) 6896fcf5ef2aSThomas Huth cpu_fprintf(f, "FPR%02d", i); 6897fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 6898fcf5ef2aSThomas Huth if ((i & (RFPL - 1)) == (RFPL - 1)) 6899fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 6900fcf5ef2aSThomas Huth } 6901fcf5ef2aSThomas Huth cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 6902fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 6903fcf5ef2aSThomas Huth cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 6904fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 6905fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 6906fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 6907fcf5ef2aSThomas Huth 6908fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 6909fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 6910fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 6911fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 6912fcf5ef2aSThomas Huth 6913fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 6914fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 6915fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 6916fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 6917fcf5ef2aSThomas Huth 6918fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6919fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 6920fcf5ef2aSThomas Huth env->excp_model == POWERPC_EXCP_POWER8) { 6921fcf5ef2aSThomas Huth cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 6922fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 6923fcf5ef2aSThomas Huth } 6924fcf5ef2aSThomas Huth #endif 6925fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 6926fcf5ef2aSThomas Huth cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 6927fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 6928fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 6929fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 6930fcf5ef2aSThomas Huth 6931fcf5ef2aSThomas Huth cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 6932fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 6933fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 6934fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 6935fcf5ef2aSThomas Huth 6936fcf5ef2aSThomas Huth cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 6937fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 6938fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 6939fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 6940fcf5ef2aSThomas Huth 6941fcf5ef2aSThomas Huth cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 6942fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 6943fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 6944fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 6945fcf5ef2aSThomas Huth 6946fcf5ef2aSThomas Huth /* FSL-specific */ 6947fcf5ef2aSThomas Huth cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 6948fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 6949fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 6950fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 6951fcf5ef2aSThomas Huth 6952fcf5ef2aSThomas Huth /* 6953fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 6954fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 6955fcf5ef2aSThomas Huth */ 6956fcf5ef2aSThomas Huth } 6957fcf5ef2aSThomas Huth 6958fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6959fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 6960fcf5ef2aSThomas Huth cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 6961fcf5ef2aSThomas Huth } 6962fcf5ef2aSThomas Huth #endif 6963fcf5ef2aSThomas Huth 6964d801a61eSSuraj Jitindar Singh if (env->spr_cb[SPR_LPCR].name) 6965d801a61eSSuraj Jitindar Singh cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 6966d801a61eSSuraj Jitindar Singh 6967fcf5ef2aSThomas Huth switch (env->mmu_model) { 6968fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 6969fcf5ef2aSThomas Huth case POWERPC_MMU_601: 6970fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 6971fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 6972fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6973fcf5ef2aSThomas Huth case POWERPC_MMU_64B: 6974fcf5ef2aSThomas Huth case POWERPC_MMU_2_03: 6975fcf5ef2aSThomas Huth case POWERPC_MMU_2_06: 6976fcf5ef2aSThomas Huth case POWERPC_MMU_2_06a: 6977fcf5ef2aSThomas Huth case POWERPC_MMU_2_07: 6978fcf5ef2aSThomas Huth case POWERPC_MMU_2_07a: 6979fcf5ef2aSThomas Huth #endif 6980fcf5ef2aSThomas Huth cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx 6981fcf5ef2aSThomas Huth " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], 6982fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 6983fcf5ef2aSThomas Huth break; 6984fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 6985fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 6986fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 6987fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 6988fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 6989fcf5ef2aSThomas Huth 6990fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 6991fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 6992fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 6993fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 6994fcf5ef2aSThomas Huth 6995fcf5ef2aSThomas Huth cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 6996fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 6997fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 6998fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 6999fcf5ef2aSThomas Huth break; 7000fcf5ef2aSThomas Huth default: 7001fcf5ef2aSThomas Huth break; 7002fcf5ef2aSThomas Huth } 7003fcf5ef2aSThomas Huth #endif 7004fcf5ef2aSThomas Huth 7005fcf5ef2aSThomas Huth #undef RGPL 7006fcf5ef2aSThomas Huth #undef RFPL 7007fcf5ef2aSThomas Huth } 7008fcf5ef2aSThomas Huth 7009fcf5ef2aSThomas Huth void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7010fcf5ef2aSThomas Huth fprintf_function cpu_fprintf, int flags) 7011fcf5ef2aSThomas Huth { 7012fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7013fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7014fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7015fcf5ef2aSThomas Huth int op1, op2, op3; 7016fcf5ef2aSThomas Huth 7017fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7018fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7019fcf5ef2aSThomas Huth handler = t1[op1]; 7020fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7021fcf5ef2aSThomas Huth t2 = ind_table(handler); 7022fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7023fcf5ef2aSThomas Huth handler = t2[op2]; 7024fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7025fcf5ef2aSThomas Huth t3 = ind_table(handler); 7026fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7027fcf5ef2aSThomas Huth handler = t3[op3]; 7028fcf5ef2aSThomas Huth if (handler->count == 0) 7029fcf5ef2aSThomas Huth continue; 7030fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7031fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7032fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7033fcf5ef2aSThomas Huth handler->oname, 7034fcf5ef2aSThomas Huth handler->count, handler->count); 7035fcf5ef2aSThomas Huth } 7036fcf5ef2aSThomas Huth } else { 7037fcf5ef2aSThomas Huth if (handler->count == 0) 7038fcf5ef2aSThomas Huth continue; 7039fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7040fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7041fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7042fcf5ef2aSThomas Huth handler->count, handler->count); 7043fcf5ef2aSThomas Huth } 7044fcf5ef2aSThomas Huth } 7045fcf5ef2aSThomas Huth } else { 7046fcf5ef2aSThomas Huth if (handler->count == 0) 7047fcf5ef2aSThomas Huth continue; 7048fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7049fcf5ef2aSThomas Huth " %" PRId64 "\n", 7050fcf5ef2aSThomas Huth op1, op1, handler->oname, 7051fcf5ef2aSThomas Huth handler->count, handler->count); 7052fcf5ef2aSThomas Huth } 7053fcf5ef2aSThomas Huth } 7054fcf5ef2aSThomas Huth #endif 7055fcf5ef2aSThomas Huth } 7056fcf5ef2aSThomas Huth 7057fcf5ef2aSThomas Huth /*****************************************************************************/ 7058fcf5ef2aSThomas Huth void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) 7059fcf5ef2aSThomas Huth { 7060fcf5ef2aSThomas Huth PowerPCCPU *cpu = ppc_env_get_cpu(env); 7061fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 7062fcf5ef2aSThomas Huth DisasContext ctx, *ctxp = &ctx; 7063fcf5ef2aSThomas Huth opc_handler_t **table, *handler; 7064fcf5ef2aSThomas Huth target_ulong pc_start; 7065fcf5ef2aSThomas Huth int num_insns; 7066fcf5ef2aSThomas Huth int max_insns; 7067fcf5ef2aSThomas Huth 7068fcf5ef2aSThomas Huth pc_start = tb->pc; 7069fcf5ef2aSThomas Huth ctx.nip = pc_start; 7070fcf5ef2aSThomas Huth ctx.tb = tb; 7071fcf5ef2aSThomas Huth ctx.exception = POWERPC_EXCP_NONE; 7072fcf5ef2aSThomas Huth ctx.spr_cb = env->spr_cb; 7073fcf5ef2aSThomas Huth ctx.pr = msr_pr; 7074fcf5ef2aSThomas Huth ctx.mem_idx = env->dmmu_idx; 7075fcf5ef2aSThomas Huth ctx.dr = msr_dr; 7076fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7077fcf5ef2aSThomas Huth ctx.hv = msr_hv || !env->has_hv_mode; 7078fcf5ef2aSThomas Huth #endif 7079fcf5ef2aSThomas Huth ctx.insns_flags = env->insns_flags; 7080fcf5ef2aSThomas Huth ctx.insns_flags2 = env->insns_flags2; 7081fcf5ef2aSThomas Huth ctx.access_type = -1; 7082fcf5ef2aSThomas Huth ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7083fcf5ef2aSThomas Huth ctx.le_mode = !!(env->hflags & (1 << MSR_LE)); 7084fcf5ef2aSThomas Huth ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; 7085fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7086fcf5ef2aSThomas Huth ctx.sf_mode = msr_is_64bit(env, env->msr); 7087fcf5ef2aSThomas Huth ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7088fcf5ef2aSThomas Huth #endif 7089fcf5ef2aSThomas Huth if (env->mmu_model == POWERPC_MMU_32B || 7090fcf5ef2aSThomas Huth env->mmu_model == POWERPC_MMU_601 || 7091fcf5ef2aSThomas Huth (env->mmu_model & POWERPC_MMU_64B)) 7092fcf5ef2aSThomas Huth ctx.lazy_tlb_flush = true; 7093fcf5ef2aSThomas Huth 7094fcf5ef2aSThomas Huth ctx.fpu_enabled = !!msr_fp; 7095fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7096fcf5ef2aSThomas Huth ctx.spe_enabled = !!msr_spe; 7097fcf5ef2aSThomas Huth else 7098fcf5ef2aSThomas Huth ctx.spe_enabled = false; 7099fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7100fcf5ef2aSThomas Huth ctx.altivec_enabled = !!msr_vr; 7101fcf5ef2aSThomas Huth else 7102fcf5ef2aSThomas Huth ctx.altivec_enabled = false; 7103fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7104fcf5ef2aSThomas Huth ctx.vsx_enabled = !!msr_vsx; 7105fcf5ef2aSThomas Huth } else { 7106fcf5ef2aSThomas Huth ctx.vsx_enabled = false; 7107fcf5ef2aSThomas Huth } 7108fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7109fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7110fcf5ef2aSThomas Huth ctx.tm_enabled = !!msr_tm; 7111fcf5ef2aSThomas Huth } else { 7112fcf5ef2aSThomas Huth ctx.tm_enabled = false; 7113fcf5ef2aSThomas Huth } 7114fcf5ef2aSThomas Huth #endif 7115fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7116fcf5ef2aSThomas Huth ctx.singlestep_enabled = CPU_SINGLE_STEP; 7117fcf5ef2aSThomas Huth else 7118fcf5ef2aSThomas Huth ctx.singlestep_enabled = 0; 7119fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7120fcf5ef2aSThomas Huth ctx.singlestep_enabled |= CPU_BRANCH_STEP; 7121fcf5ef2aSThomas Huth if (unlikely(cs->singlestep_enabled)) { 7122fcf5ef2aSThomas Huth ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7123fcf5ef2aSThomas Huth } 7124fcf5ef2aSThomas Huth #if defined (DO_SINGLE_STEP) && 0 7125fcf5ef2aSThomas Huth /* Single step trace mode */ 7126fcf5ef2aSThomas Huth msr_se = 1; 7127fcf5ef2aSThomas Huth #endif 7128fcf5ef2aSThomas Huth num_insns = 0; 7129fcf5ef2aSThomas Huth max_insns = tb->cflags & CF_COUNT_MASK; 7130fcf5ef2aSThomas Huth if (max_insns == 0) { 7131fcf5ef2aSThomas Huth max_insns = CF_COUNT_MASK; 7132fcf5ef2aSThomas Huth } 7133fcf5ef2aSThomas Huth if (max_insns > TCG_MAX_INSNS) { 7134fcf5ef2aSThomas Huth max_insns = TCG_MAX_INSNS; 7135fcf5ef2aSThomas Huth } 7136fcf5ef2aSThomas Huth 7137fcf5ef2aSThomas Huth gen_tb_start(tb); 7138fcf5ef2aSThomas Huth tcg_clear_temp_count(); 7139fcf5ef2aSThomas Huth /* Set env in case of segfault during code fetch */ 7140fcf5ef2aSThomas Huth while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) { 7141fcf5ef2aSThomas Huth tcg_gen_insn_start(ctx.nip); 7142fcf5ef2aSThomas Huth num_insns++; 7143fcf5ef2aSThomas Huth 7144fcf5ef2aSThomas Huth if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { 7145fcf5ef2aSThomas Huth gen_debug_exception(ctxp); 7146fcf5ef2aSThomas Huth /* The address covered by the breakpoint must be included in 7147fcf5ef2aSThomas Huth [tb->pc, tb->pc + tb->size) in order to for it to be 7148fcf5ef2aSThomas Huth properly cleared -- thus we increment the PC here so that 7149fcf5ef2aSThomas Huth the logic setting tb->size below does the right thing. */ 7150fcf5ef2aSThomas Huth ctx.nip += 4; 7151fcf5ef2aSThomas Huth break; 7152fcf5ef2aSThomas Huth } 7153fcf5ef2aSThomas Huth 7154fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7155fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7156fcf5ef2aSThomas Huth ctx.nip, ctx.mem_idx, (int)msr_ir); 7157fcf5ef2aSThomas Huth if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) 7158fcf5ef2aSThomas Huth gen_io_start(); 7159fcf5ef2aSThomas Huth if (unlikely(need_byteswap(&ctx))) { 7160fcf5ef2aSThomas Huth ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); 7161fcf5ef2aSThomas Huth } else { 7162fcf5ef2aSThomas Huth ctx.opcode = cpu_ldl_code(env, ctx.nip); 7163fcf5ef2aSThomas Huth } 7164fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7165fcf5ef2aSThomas Huth ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), 7166fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7167fcf5ef2aSThomas Huth ctx.le_mode ? "little" : "big"); 7168fcf5ef2aSThomas Huth ctx.nip += 4; 7169fcf5ef2aSThomas Huth table = env->opcodes; 7170fcf5ef2aSThomas Huth handler = table[opc1(ctx.opcode)]; 7171fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7172fcf5ef2aSThomas Huth table = ind_table(handler); 7173fcf5ef2aSThomas Huth handler = table[opc2(ctx.opcode)]; 7174fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7175fcf5ef2aSThomas Huth table = ind_table(handler); 7176fcf5ef2aSThomas Huth handler = table[opc3(ctx.opcode)]; 7177fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7178fcf5ef2aSThomas Huth table = ind_table(handler); 7179fcf5ef2aSThomas Huth handler = table[opc4(ctx.opcode)]; 7180fcf5ef2aSThomas Huth } 7181fcf5ef2aSThomas Huth } 7182fcf5ef2aSThomas Huth } 7183fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7184fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7185fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7186fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7187fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7188fcf5ef2aSThomas Huth opc1(ctx.opcode), opc2(ctx.opcode), 7189fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7190fcf5ef2aSThomas Huth ctx.opcode, ctx.nip - 4, (int)msr_ir); 7191fcf5ef2aSThomas Huth } else { 7192fcf5ef2aSThomas Huth uint32_t inval; 7193fcf5ef2aSThomas Huth 7194fcf5ef2aSThomas Huth if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { 7195fcf5ef2aSThomas Huth inval = handler->inval2; 7196fcf5ef2aSThomas Huth } else { 7197fcf5ef2aSThomas Huth inval = handler->inval1; 7198fcf5ef2aSThomas Huth } 7199fcf5ef2aSThomas Huth 7200fcf5ef2aSThomas Huth if (unlikely((ctx.opcode & inval) != 0)) { 7201fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7202fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7203fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", ctx.opcode & inval, 7204fcf5ef2aSThomas Huth opc1(ctx.opcode), opc2(ctx.opcode), 7205fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7206fcf5ef2aSThomas Huth ctx.opcode, ctx.nip - 4); 7207fcf5ef2aSThomas Huth gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); 7208fcf5ef2aSThomas Huth break; 7209fcf5ef2aSThomas Huth } 7210fcf5ef2aSThomas Huth } 7211fcf5ef2aSThomas Huth (*(handler->handler))(&ctx); 7212fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7213fcf5ef2aSThomas Huth handler->count++; 7214fcf5ef2aSThomas Huth #endif 7215fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7216fcf5ef2aSThomas Huth if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && 7217fcf5ef2aSThomas Huth (ctx.nip <= 0x100 || ctx.nip > 0xF00) && 7218fcf5ef2aSThomas Huth ctx.exception != POWERPC_SYSCALL && 7219fcf5ef2aSThomas Huth ctx.exception != POWERPC_EXCP_TRAP && 7220fcf5ef2aSThomas Huth ctx.exception != POWERPC_EXCP_BRANCH)) { 7221fcf5ef2aSThomas Huth gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); 7222fcf5ef2aSThomas Huth } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || 7223fcf5ef2aSThomas Huth (cs->singlestep_enabled) || 7224fcf5ef2aSThomas Huth singlestep || 7225fcf5ef2aSThomas Huth num_insns >= max_insns)) { 7226fcf5ef2aSThomas Huth /* if we reach a page boundary or are single stepping, stop 7227fcf5ef2aSThomas Huth * generation 7228fcf5ef2aSThomas Huth */ 7229fcf5ef2aSThomas Huth break; 7230fcf5ef2aSThomas Huth } 7231fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7232fcf5ef2aSThomas Huth fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " 7233fcf5ef2aSThomas Huth "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), 7234fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); 7235fcf5ef2aSThomas Huth exit(1); 7236fcf5ef2aSThomas Huth } 7237fcf5ef2aSThomas Huth } 7238fcf5ef2aSThomas Huth if (tb->cflags & CF_LAST_IO) 7239fcf5ef2aSThomas Huth gen_io_end(); 7240fcf5ef2aSThomas Huth if (ctx.exception == POWERPC_EXCP_NONE) { 7241fcf5ef2aSThomas Huth gen_goto_tb(&ctx, 0, ctx.nip); 7242fcf5ef2aSThomas Huth } else if (ctx.exception != POWERPC_EXCP_BRANCH) { 7243fcf5ef2aSThomas Huth if (unlikely(cs->singlestep_enabled)) { 7244fcf5ef2aSThomas Huth gen_debug_exception(ctxp); 7245fcf5ef2aSThomas Huth } 7246fcf5ef2aSThomas Huth /* Generate the return instruction */ 7247fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 7248fcf5ef2aSThomas Huth } 7249fcf5ef2aSThomas Huth gen_tb_end(tb, num_insns); 7250fcf5ef2aSThomas Huth 7251fcf5ef2aSThomas Huth tb->size = ctx.nip - pc_start; 7252fcf5ef2aSThomas Huth tb->icount = num_insns; 7253fcf5ef2aSThomas Huth 7254fcf5ef2aSThomas Huth #if defined(DEBUG_DISAS) 7255fcf5ef2aSThomas Huth if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 7256fcf5ef2aSThomas Huth && qemu_log_in_addr_range(pc_start)) { 7257fcf5ef2aSThomas Huth int flags; 7258fcf5ef2aSThomas Huth flags = env->bfd_mach; 7259fcf5ef2aSThomas Huth flags |= ctx.le_mode << 16; 7260fcf5ef2aSThomas Huth qemu_log_lock(); 7261fcf5ef2aSThomas Huth qemu_log("IN: %s\n", lookup_symbol(pc_start)); 7262fcf5ef2aSThomas Huth log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); 7263fcf5ef2aSThomas Huth qemu_log("\n"); 7264fcf5ef2aSThomas Huth qemu_log_unlock(); 7265fcf5ef2aSThomas Huth } 7266fcf5ef2aSThomas Huth #endif 7267fcf5ef2aSThomas Huth } 7268fcf5ef2aSThomas Huth 7269fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7270fcf5ef2aSThomas Huth target_ulong *data) 7271fcf5ef2aSThomas Huth { 7272fcf5ef2aSThomas Huth env->nip = data[0]; 7273fcf5ef2aSThomas Huth } 7274