1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26fcf5ef2aSThomas Huth #include "tcg-op.h" 2750d24aedSMark Cave-Ayland #include "tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 30fcf5ef2aSThomas Huth 31fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 32fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 33fcf5ef2aSThomas Huth 34fcf5ef2aSThomas Huth #include "trace-tcg.h" 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 38fcf5ef2aSThomas Huth 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 41fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 42fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 45efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 46efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 49fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 50fcf5ef2aSThomas Huth #else 51fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 52fcf5ef2aSThomas Huth #endif 53fcf5ef2aSThomas Huth /*****************************************************************************/ 54fcf5ef2aSThomas Huth /* Code translation helpers */ 55fcf5ef2aSThomas Huth 56fcf5ef2aSThomas Huth /* global register indexes */ 57fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 58fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 59fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 60fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 61fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 62fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 63fcf5ef2aSThomas Huth static TCGv cpu_nip; 64fcf5ef2aSThomas Huth static TCGv cpu_msr; 65fcf5ef2aSThomas Huth static TCGv cpu_ctr; 66fcf5ef2aSThomas Huth static TCGv cpu_lr; 67fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 68fcf5ef2aSThomas Huth static TCGv cpu_cfar; 69fcf5ef2aSThomas Huth #endif 70dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 71fcf5ef2aSThomas Huth static TCGv cpu_reserve; 72253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 73fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 74fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 75fcf5ef2aSThomas Huth 76fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 77fcf5ef2aSThomas Huth 78fcf5ef2aSThomas Huth void ppc_translate_init(void) 79fcf5ef2aSThomas Huth { 80fcf5ef2aSThomas Huth int i; 81fcf5ef2aSThomas Huth char *p; 82fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 83fcf5ef2aSThomas Huth 84fcf5ef2aSThomas Huth p = cpu_reg_names; 85fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 86fcf5ef2aSThomas Huth 87fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 88fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 89fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 90fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 91fcf5ef2aSThomas Huth p += 5; 92fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 93fcf5ef2aSThomas Huth } 94fcf5ef2aSThomas Huth 95fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 96fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 97fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 98fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 99fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 100fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 102fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 103fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 104fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 105fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth } 107fcf5ef2aSThomas Huth 108fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 109fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 112fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 121fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 123fcf5ef2aSThomas Huth #endif 124fcf5ef2aSThomas Huth 125fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 127fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 128fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 129fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 131fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 133dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 134dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 135dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 136dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 137fcf5ef2aSThomas Huth 138fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 139fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 140fcf5ef2aSThomas Huth "reserve_addr"); 141253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 142253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 143253ce7b2SNikunj A Dadhania "reserve_val"); 144fcf5ef2aSThomas Huth 145fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 146fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 147fcf5ef2aSThomas Huth 148fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 149efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 150efe843d8SDavid Gibson "access_type"); 151fcf5ef2aSThomas Huth } 152fcf5ef2aSThomas Huth 153fcf5ef2aSThomas Huth /* internal defines */ 154fcf5ef2aSThomas Huth struct DisasContext { 155b6bac4bcSEmilio G. Cota DisasContextBase base; 156fcf5ef2aSThomas Huth uint32_t opcode; 157fcf5ef2aSThomas Huth uint32_t exception; 158fcf5ef2aSThomas Huth /* Routine used to access memory */ 159fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 160fcf5ef2aSThomas Huth bool lazy_tlb_flush; 161fcf5ef2aSThomas Huth bool need_access_type; 162fcf5ef2aSThomas Huth int mem_idx; 163fcf5ef2aSThomas Huth int access_type; 164fcf5ef2aSThomas Huth /* Translation flags */ 165fcf5ef2aSThomas Huth TCGMemOp default_tcg_memop_mask; 166fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 167fcf5ef2aSThomas Huth bool sf_mode; 168fcf5ef2aSThomas Huth bool has_cfar; 169fcf5ef2aSThomas Huth #endif 170fcf5ef2aSThomas Huth bool fpu_enabled; 171fcf5ef2aSThomas Huth bool altivec_enabled; 172fcf5ef2aSThomas Huth bool vsx_enabled; 173fcf5ef2aSThomas Huth bool spe_enabled; 174fcf5ef2aSThomas Huth bool tm_enabled; 175c6fd28fdSSuraj Jitindar Singh bool gtse; 176fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 177fcf5ef2aSThomas Huth int singlestep_enabled; 1780e3bf489SRoman Kapl uint32_t flags; 179fcf5ef2aSThomas Huth uint64_t insns_flags; 180fcf5ef2aSThomas Huth uint64_t insns_flags2; 181fcf5ef2aSThomas Huth }; 182fcf5ef2aSThomas Huth 183fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 184fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 185fcf5ef2aSThomas Huth { 186fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 187fcf5ef2aSThomas Huth return ctx->le_mode; 188fcf5ef2aSThomas Huth #else 189fcf5ef2aSThomas Huth return !ctx->le_mode; 190fcf5ef2aSThomas Huth #endif 191fcf5ef2aSThomas Huth } 192fcf5ef2aSThomas Huth 193fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 194fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 195fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 196fcf5ef2aSThomas Huth #else 197fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 198fcf5ef2aSThomas Huth #endif 199fcf5ef2aSThomas Huth 200fcf5ef2aSThomas Huth struct opc_handler_t { 201fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 202fcf5ef2aSThomas Huth uint32_t inval1; 203fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 204fcf5ef2aSThomas Huth uint32_t inval2; 205fcf5ef2aSThomas Huth /* instruction type */ 206fcf5ef2aSThomas Huth uint64_t type; 207fcf5ef2aSThomas Huth /* extended instruction type */ 208fcf5ef2aSThomas Huth uint64_t type2; 209fcf5ef2aSThomas Huth /* handler */ 210fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 211fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 212fcf5ef2aSThomas Huth const char *oname; 213fcf5ef2aSThomas Huth #endif 214fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 215fcf5ef2aSThomas Huth uint64_t count; 216fcf5ef2aSThomas Huth #endif 217fcf5ef2aSThomas Huth }; 218fcf5ef2aSThomas Huth 2190e3bf489SRoman Kapl /* SPR load/store helpers */ 2200e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2210e3bf489SRoman Kapl { 2220e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2230e3bf489SRoman Kapl } 2240e3bf489SRoman Kapl 2250e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2260e3bf489SRoman Kapl { 2270e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2280e3bf489SRoman Kapl } 2290e3bf489SRoman Kapl 230fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 231fcf5ef2aSThomas Huth { 232fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 233fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 234fcf5ef2aSThomas Huth ctx->access_type = access_type; 235fcf5ef2aSThomas Huth } 236fcf5ef2aSThomas Huth } 237fcf5ef2aSThomas Huth 238fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 239fcf5ef2aSThomas Huth { 240fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 241fcf5ef2aSThomas Huth nip = (uint32_t)nip; 242fcf5ef2aSThomas Huth } 243fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 244fcf5ef2aSThomas Huth } 245fcf5ef2aSThomas Huth 246fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 247fcf5ef2aSThomas Huth { 248fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 249fcf5ef2aSThomas Huth 250efe843d8SDavid Gibson /* 251efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 252efe843d8SDavid Gibson * faulting instruction 253fcf5ef2aSThomas Huth */ 254fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 255b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 256fcf5ef2aSThomas Huth } 257fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 258fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 259fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 260fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 261fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 262fcf5ef2aSThomas Huth ctx->exception = (excp); 263fcf5ef2aSThomas Huth } 264fcf5ef2aSThomas Huth 265fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 266fcf5ef2aSThomas Huth { 267fcf5ef2aSThomas Huth TCGv_i32 t0; 268fcf5ef2aSThomas Huth 269efe843d8SDavid Gibson /* 270efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 271efe843d8SDavid Gibson * faulting instruction 272fcf5ef2aSThomas Huth */ 273fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 274b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 275fcf5ef2aSThomas Huth } 276fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 277fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 278fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 279fcf5ef2aSThomas Huth ctx->exception = (excp); 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth 282fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 283fcf5ef2aSThomas Huth target_ulong nip) 284fcf5ef2aSThomas Huth { 285fcf5ef2aSThomas Huth TCGv_i32 t0; 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 288fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 289fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 290fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 291fcf5ef2aSThomas Huth ctx->exception = (excp); 292fcf5ef2aSThomas Huth } 293fcf5ef2aSThomas Huth 294e150ac89SRoman Kapl /* 295e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 296e150ac89SRoman Kapl * SPR registers for this exception. 297e150ac89SRoman Kapl * 298e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 299e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3000e3bf489SRoman Kapl */ 301e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3020e3bf489SRoman Kapl { 3030e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3040e3bf489SRoman Kapl target_ulong dbsr = 0; 305e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3060e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 307e150ac89SRoman Kapl } else { 308e150ac89SRoman Kapl /* Must have been branch */ 3090e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3100e3bf489SRoman Kapl } 3110e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3120e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3130e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3140e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3150e3bf489SRoman Kapl tcg_temp_free(t0); 3160e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3170e3bf489SRoman Kapl } else { 318e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3190e3bf489SRoman Kapl } 3200e3bf489SRoman Kapl } 3210e3bf489SRoman Kapl 322fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 323fcf5ef2aSThomas Huth { 324fcf5ef2aSThomas Huth TCGv_i32 t0; 325fcf5ef2aSThomas Huth 326efe843d8SDavid Gibson /* 327efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 328efe843d8SDavid Gibson * faulting instruction 329fcf5ef2aSThomas Huth */ 330fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 331fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 332b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 333fcf5ef2aSThomas Huth } 334fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 335fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 336fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 337fcf5ef2aSThomas Huth } 338fcf5ef2aSThomas Huth 339fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 340fcf5ef2aSThomas Huth { 341fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 342fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 343fcf5ef2aSThomas Huth } 344fcf5ef2aSThomas Huth 345fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 346fcf5ef2aSThomas Huth { 347fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 348fcf5ef2aSThomas Huth } 349fcf5ef2aSThomas Huth 350fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 351fcf5ef2aSThomas Huth { 352fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 353fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 354fcf5ef2aSThomas Huth } 355fcf5ef2aSThomas Huth 356fcf5ef2aSThomas Huth /* Stop translation */ 357fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 358fcf5ef2aSThomas Huth { 359b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 360fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 361fcf5ef2aSThomas Huth } 362fcf5ef2aSThomas Huth 363fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 364fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 365fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 366fcf5ef2aSThomas Huth { 367fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 368fcf5ef2aSThomas Huth } 369fcf5ef2aSThomas Huth #endif 370fcf5ef2aSThomas Huth 371fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 372fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 373fcf5ef2aSThomas Huth 374fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 375fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 376fcf5ef2aSThomas Huth 377fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 378fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 379fcf5ef2aSThomas Huth 380fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 381fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 382fcf5ef2aSThomas Huth 383fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 384fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 385fcf5ef2aSThomas Huth 386fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 387fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 388fcf5ef2aSThomas Huth 389fcf5ef2aSThomas Huth typedef struct opcode_t { 390fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 391fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 392fcf5ef2aSThomas Huth unsigned char pad[4]; 393fcf5ef2aSThomas Huth #endif 394fcf5ef2aSThomas Huth opc_handler_t handler; 395fcf5ef2aSThomas Huth const char *oname; 396fcf5ef2aSThomas Huth } opcode_t; 397fcf5ef2aSThomas Huth 398fcf5ef2aSThomas Huth /* Helpers for priv. check */ 399fcf5ef2aSThomas Huth #define GEN_PRIV \ 400fcf5ef2aSThomas Huth do { \ 401fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 402fcf5ef2aSThomas Huth } while (0) 403fcf5ef2aSThomas Huth 404fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 405fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 406fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 407fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 408fcf5ef2aSThomas Huth #else 409fcf5ef2aSThomas Huth #define CHK_HV \ 410fcf5ef2aSThomas Huth do { \ 411fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 412fcf5ef2aSThomas Huth GEN_PRIV; \ 413fcf5ef2aSThomas Huth } \ 414fcf5ef2aSThomas Huth } while (0) 415fcf5ef2aSThomas Huth #define CHK_SV \ 416fcf5ef2aSThomas Huth do { \ 417fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 418fcf5ef2aSThomas Huth GEN_PRIV; \ 419fcf5ef2aSThomas Huth } \ 420fcf5ef2aSThomas Huth } while (0) 421fcf5ef2aSThomas Huth #define CHK_HVRM \ 422fcf5ef2aSThomas Huth do { \ 423fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 424fcf5ef2aSThomas Huth GEN_PRIV; \ 425fcf5ef2aSThomas Huth } \ 426fcf5ef2aSThomas Huth } while (0) 427fcf5ef2aSThomas Huth #endif 428fcf5ef2aSThomas Huth 429fcf5ef2aSThomas Huth #define CHK_NONE 430fcf5ef2aSThomas Huth 431fcf5ef2aSThomas Huth /*****************************************************************************/ 432fcf5ef2aSThomas Huth /* PowerPC instructions table */ 433fcf5ef2aSThomas Huth 434fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 435fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 436fcf5ef2aSThomas Huth { \ 437fcf5ef2aSThomas Huth .opc1 = op1, \ 438fcf5ef2aSThomas Huth .opc2 = op2, \ 439fcf5ef2aSThomas Huth .opc3 = op3, \ 440fcf5ef2aSThomas Huth .opc4 = 0xff, \ 441fcf5ef2aSThomas Huth .handler = { \ 442fcf5ef2aSThomas Huth .inval1 = invl, \ 443fcf5ef2aSThomas Huth .type = _typ, \ 444fcf5ef2aSThomas Huth .type2 = _typ2, \ 445fcf5ef2aSThomas Huth .handler = &gen_##name, \ 446fcf5ef2aSThomas Huth .oname = stringify(name), \ 447fcf5ef2aSThomas Huth }, \ 448fcf5ef2aSThomas Huth .oname = stringify(name), \ 449fcf5ef2aSThomas Huth } 450fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 451fcf5ef2aSThomas Huth { \ 452fcf5ef2aSThomas Huth .opc1 = op1, \ 453fcf5ef2aSThomas Huth .opc2 = op2, \ 454fcf5ef2aSThomas Huth .opc3 = op3, \ 455fcf5ef2aSThomas Huth .opc4 = 0xff, \ 456fcf5ef2aSThomas Huth .handler = { \ 457fcf5ef2aSThomas Huth .inval1 = invl1, \ 458fcf5ef2aSThomas Huth .inval2 = invl2, \ 459fcf5ef2aSThomas Huth .type = _typ, \ 460fcf5ef2aSThomas Huth .type2 = _typ2, \ 461fcf5ef2aSThomas Huth .handler = &gen_##name, \ 462fcf5ef2aSThomas Huth .oname = stringify(name), \ 463fcf5ef2aSThomas Huth }, \ 464fcf5ef2aSThomas Huth .oname = stringify(name), \ 465fcf5ef2aSThomas Huth } 466fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 467fcf5ef2aSThomas Huth { \ 468fcf5ef2aSThomas Huth .opc1 = op1, \ 469fcf5ef2aSThomas Huth .opc2 = op2, \ 470fcf5ef2aSThomas Huth .opc3 = op3, \ 471fcf5ef2aSThomas Huth .opc4 = 0xff, \ 472fcf5ef2aSThomas Huth .handler = { \ 473fcf5ef2aSThomas Huth .inval1 = invl, \ 474fcf5ef2aSThomas Huth .type = _typ, \ 475fcf5ef2aSThomas Huth .type2 = _typ2, \ 476fcf5ef2aSThomas Huth .handler = &gen_##name, \ 477fcf5ef2aSThomas Huth .oname = onam, \ 478fcf5ef2aSThomas Huth }, \ 479fcf5ef2aSThomas Huth .oname = onam, \ 480fcf5ef2aSThomas Huth } 481fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 482fcf5ef2aSThomas Huth { \ 483fcf5ef2aSThomas Huth .opc1 = op1, \ 484fcf5ef2aSThomas Huth .opc2 = op2, \ 485fcf5ef2aSThomas Huth .opc3 = op3, \ 486fcf5ef2aSThomas Huth .opc4 = op4, \ 487fcf5ef2aSThomas Huth .handler = { \ 488fcf5ef2aSThomas Huth .inval1 = invl, \ 489fcf5ef2aSThomas Huth .type = _typ, \ 490fcf5ef2aSThomas Huth .type2 = _typ2, \ 491fcf5ef2aSThomas Huth .handler = &gen_##name, \ 492fcf5ef2aSThomas Huth .oname = stringify(name), \ 493fcf5ef2aSThomas Huth }, \ 494fcf5ef2aSThomas Huth .oname = stringify(name), \ 495fcf5ef2aSThomas Huth } 496fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 497fcf5ef2aSThomas Huth { \ 498fcf5ef2aSThomas Huth .opc1 = op1, \ 499fcf5ef2aSThomas Huth .opc2 = op2, \ 500fcf5ef2aSThomas Huth .opc3 = op3, \ 501fcf5ef2aSThomas Huth .opc4 = op4, \ 502fcf5ef2aSThomas Huth .handler = { \ 503fcf5ef2aSThomas Huth .inval1 = invl, \ 504fcf5ef2aSThomas Huth .type = _typ, \ 505fcf5ef2aSThomas Huth .type2 = _typ2, \ 506fcf5ef2aSThomas Huth .handler = &gen_##name, \ 507fcf5ef2aSThomas Huth .oname = onam, \ 508fcf5ef2aSThomas Huth }, \ 509fcf5ef2aSThomas Huth .oname = onam, \ 510fcf5ef2aSThomas Huth } 511fcf5ef2aSThomas Huth #else 512fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 513fcf5ef2aSThomas Huth { \ 514fcf5ef2aSThomas Huth .opc1 = op1, \ 515fcf5ef2aSThomas Huth .opc2 = op2, \ 516fcf5ef2aSThomas Huth .opc3 = op3, \ 517fcf5ef2aSThomas Huth .opc4 = 0xff, \ 518fcf5ef2aSThomas Huth .handler = { \ 519fcf5ef2aSThomas Huth .inval1 = invl, \ 520fcf5ef2aSThomas Huth .type = _typ, \ 521fcf5ef2aSThomas Huth .type2 = _typ2, \ 522fcf5ef2aSThomas Huth .handler = &gen_##name, \ 523fcf5ef2aSThomas Huth }, \ 524fcf5ef2aSThomas Huth .oname = stringify(name), \ 525fcf5ef2aSThomas Huth } 526fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 527fcf5ef2aSThomas Huth { \ 528fcf5ef2aSThomas Huth .opc1 = op1, \ 529fcf5ef2aSThomas Huth .opc2 = op2, \ 530fcf5ef2aSThomas Huth .opc3 = op3, \ 531fcf5ef2aSThomas Huth .opc4 = 0xff, \ 532fcf5ef2aSThomas Huth .handler = { \ 533fcf5ef2aSThomas Huth .inval1 = invl1, \ 534fcf5ef2aSThomas Huth .inval2 = invl2, \ 535fcf5ef2aSThomas Huth .type = _typ, \ 536fcf5ef2aSThomas Huth .type2 = _typ2, \ 537fcf5ef2aSThomas Huth .handler = &gen_##name, \ 538fcf5ef2aSThomas Huth }, \ 539fcf5ef2aSThomas Huth .oname = stringify(name), \ 540fcf5ef2aSThomas Huth } 541fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 542fcf5ef2aSThomas Huth { \ 543fcf5ef2aSThomas Huth .opc1 = op1, \ 544fcf5ef2aSThomas Huth .opc2 = op2, \ 545fcf5ef2aSThomas Huth .opc3 = op3, \ 546fcf5ef2aSThomas Huth .opc4 = 0xff, \ 547fcf5ef2aSThomas Huth .handler = { \ 548fcf5ef2aSThomas Huth .inval1 = invl, \ 549fcf5ef2aSThomas Huth .type = _typ, \ 550fcf5ef2aSThomas Huth .type2 = _typ2, \ 551fcf5ef2aSThomas Huth .handler = &gen_##name, \ 552fcf5ef2aSThomas Huth }, \ 553fcf5ef2aSThomas Huth .oname = onam, \ 554fcf5ef2aSThomas Huth } 555fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 556fcf5ef2aSThomas Huth { \ 557fcf5ef2aSThomas Huth .opc1 = op1, \ 558fcf5ef2aSThomas Huth .opc2 = op2, \ 559fcf5ef2aSThomas Huth .opc3 = op3, \ 560fcf5ef2aSThomas Huth .opc4 = op4, \ 561fcf5ef2aSThomas Huth .handler = { \ 562fcf5ef2aSThomas Huth .inval1 = invl, \ 563fcf5ef2aSThomas Huth .type = _typ, \ 564fcf5ef2aSThomas Huth .type2 = _typ2, \ 565fcf5ef2aSThomas Huth .handler = &gen_##name, \ 566fcf5ef2aSThomas Huth }, \ 567fcf5ef2aSThomas Huth .oname = stringify(name), \ 568fcf5ef2aSThomas Huth } 569fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 570fcf5ef2aSThomas Huth { \ 571fcf5ef2aSThomas Huth .opc1 = op1, \ 572fcf5ef2aSThomas Huth .opc2 = op2, \ 573fcf5ef2aSThomas Huth .opc3 = op3, \ 574fcf5ef2aSThomas Huth .opc4 = op4, \ 575fcf5ef2aSThomas Huth .handler = { \ 576fcf5ef2aSThomas Huth .inval1 = invl, \ 577fcf5ef2aSThomas Huth .type = _typ, \ 578fcf5ef2aSThomas Huth .type2 = _typ2, \ 579fcf5ef2aSThomas Huth .handler = &gen_##name, \ 580fcf5ef2aSThomas Huth }, \ 581fcf5ef2aSThomas Huth .oname = onam, \ 582fcf5ef2aSThomas Huth } 583fcf5ef2aSThomas Huth #endif 584fcf5ef2aSThomas Huth 585fcf5ef2aSThomas Huth /* Invalid instruction */ 586fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 587fcf5ef2aSThomas Huth { 588fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 589fcf5ef2aSThomas Huth } 590fcf5ef2aSThomas Huth 591fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 592fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 593fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 594fcf5ef2aSThomas Huth .type = PPC_NONE, 595fcf5ef2aSThomas Huth .type2 = PPC_NONE, 596fcf5ef2aSThomas Huth .handler = gen_invalid, 597fcf5ef2aSThomas Huth }; 598fcf5ef2aSThomas Huth 599fcf5ef2aSThomas Huth /*** Integer comparison ***/ 600fcf5ef2aSThomas Huth 601fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 602fcf5ef2aSThomas Huth { 603fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 604b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 605b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 606fcf5ef2aSThomas Huth 607b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 608b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 609efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 610efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 611b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 612efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 613efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 614b62b3686Spbonzini@redhat.com 615b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 616fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 617b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 618fcf5ef2aSThomas Huth 619fcf5ef2aSThomas Huth tcg_temp_free(t0); 620b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 621b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 622fcf5ef2aSThomas Huth } 623fcf5ef2aSThomas Huth 624fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 625fcf5ef2aSThomas Huth { 626fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 627fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 628fcf5ef2aSThomas Huth tcg_temp_free(t0); 629fcf5ef2aSThomas Huth } 630fcf5ef2aSThomas Huth 631fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 632fcf5ef2aSThomas Huth { 633fcf5ef2aSThomas Huth TCGv t0, t1; 634fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 635fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 636fcf5ef2aSThomas Huth if (s) { 637fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 638fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 639fcf5ef2aSThomas Huth } else { 640fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 641fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 642fcf5ef2aSThomas Huth } 643fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 644fcf5ef2aSThomas Huth tcg_temp_free(t1); 645fcf5ef2aSThomas Huth tcg_temp_free(t0); 646fcf5ef2aSThomas Huth } 647fcf5ef2aSThomas Huth 648fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 649fcf5ef2aSThomas Huth { 650fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 651fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 652fcf5ef2aSThomas Huth tcg_temp_free(t0); 653fcf5ef2aSThomas Huth } 654fcf5ef2aSThomas Huth 655fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 656fcf5ef2aSThomas Huth { 657fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 658fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 659fcf5ef2aSThomas Huth } else { 660fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 661fcf5ef2aSThomas Huth } 662fcf5ef2aSThomas Huth } 663fcf5ef2aSThomas Huth 664fcf5ef2aSThomas Huth /* cmp */ 665fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 666fcf5ef2aSThomas Huth { 667fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 668fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 669fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 670fcf5ef2aSThomas Huth } else { 671fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 672fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 673fcf5ef2aSThomas Huth } 674fcf5ef2aSThomas Huth } 675fcf5ef2aSThomas Huth 676fcf5ef2aSThomas Huth /* cmpi */ 677fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 678fcf5ef2aSThomas Huth { 679fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 680fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 681fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 682fcf5ef2aSThomas Huth } else { 683fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 684fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 685fcf5ef2aSThomas Huth } 686fcf5ef2aSThomas Huth } 687fcf5ef2aSThomas Huth 688fcf5ef2aSThomas Huth /* cmpl */ 689fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 690fcf5ef2aSThomas Huth { 691fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 692fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 693fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 694fcf5ef2aSThomas Huth } else { 695fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 696fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 697fcf5ef2aSThomas Huth } 698fcf5ef2aSThomas Huth } 699fcf5ef2aSThomas Huth 700fcf5ef2aSThomas Huth /* cmpli */ 701fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 702fcf5ef2aSThomas Huth { 703fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 704fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 705fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 706fcf5ef2aSThomas Huth } else { 707fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 708fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 709fcf5ef2aSThomas Huth } 710fcf5ef2aSThomas Huth } 711fcf5ef2aSThomas Huth 712fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 713fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 714fcf5ef2aSThomas Huth { 715fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 716fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 717fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 718fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 719fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 720fcf5ef2aSThomas Huth 721fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 722fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 723fcf5ef2aSThomas Huth 724fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 725fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 726fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 727fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 728fcf5ef2aSThomas Huth 729fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 730fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 731fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 732fcf5ef2aSThomas Huth 733fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 734fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 735fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 736fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 737fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 738fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 739fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 740fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 741fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 742fcf5ef2aSThomas Huth } 743efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 744fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 745fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 746fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 747fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 748fcf5ef2aSThomas Huth } 749fcf5ef2aSThomas Huth 750fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 751fcf5ef2aSThomas Huth /* cmpeqb */ 752fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 753fcf5ef2aSThomas Huth { 754fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 755fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 756fcf5ef2aSThomas Huth } 757fcf5ef2aSThomas Huth #endif 758fcf5ef2aSThomas Huth 759fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 760fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 761fcf5ef2aSThomas Huth { 762fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 763fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 764fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 765fcf5ef2aSThomas Huth TCGv zr; 766fcf5ef2aSThomas Huth 767fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 768fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 769fcf5ef2aSThomas Huth 770fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 771fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 772fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 773fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 774fcf5ef2aSThomas Huth tcg_temp_free(zr); 775fcf5ef2aSThomas Huth tcg_temp_free(t0); 776fcf5ef2aSThomas Huth } 777fcf5ef2aSThomas Huth 778fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 779fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 780fcf5ef2aSThomas Huth { 781fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 782fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 783fcf5ef2aSThomas Huth } 784fcf5ef2aSThomas Huth 785fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 786fcf5ef2aSThomas Huth 787fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 788fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 789fcf5ef2aSThomas Huth { 790fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 791fcf5ef2aSThomas Huth 792fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 793fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 794fcf5ef2aSThomas Huth if (sub) { 795fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 796fcf5ef2aSThomas Huth } else { 797fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 798fcf5ef2aSThomas Huth } 799fcf5ef2aSThomas Huth tcg_temp_free(t0); 800fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 801dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 802dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 803dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 804fcf5ef2aSThomas Huth } 805dc0ad844SNikunj A Dadhania } else { 806dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 807dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 808dc0ad844SNikunj A Dadhania } 80938a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 810dc0ad844SNikunj A Dadhania } 811fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 812fcf5ef2aSThomas Huth } 813fcf5ef2aSThomas Huth 8146b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8156b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 8164c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 8176b10d008SNikunj A Dadhania { 8186b10d008SNikunj A Dadhania TCGv t0; 8196b10d008SNikunj A Dadhania 8206b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8216b10d008SNikunj A Dadhania return; 8226b10d008SNikunj A Dadhania } 8236b10d008SNikunj A Dadhania 8246b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 82533903d0aSNikunj A Dadhania if (sub) { 82633903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 82733903d0aSNikunj A Dadhania } else { 8286b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 82933903d0aSNikunj A Dadhania } 8306b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 8314c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 8326b10d008SNikunj A Dadhania tcg_temp_free(t0); 8336b10d008SNikunj A Dadhania } 8346b10d008SNikunj A Dadhania 835fcf5ef2aSThomas Huth /* Common add function */ 836fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 8374c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 8384c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 839fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 840fcf5ef2aSThomas Huth { 841fcf5ef2aSThomas Huth TCGv t0 = ret; 842fcf5ef2aSThomas Huth 843fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 844fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 845fcf5ef2aSThomas Huth } 846fcf5ef2aSThomas Huth 847fcf5ef2aSThomas Huth if (compute_ca) { 848fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 849efe843d8SDavid Gibson /* 850efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 851efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 852efe843d8SDavid Gibson * produce the carry into bit 32. 853efe843d8SDavid Gibson */ 854fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 855fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 856fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 857fcf5ef2aSThomas Huth if (add_ca) { 8584c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 859fcf5ef2aSThomas Huth } 8604c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 861fcf5ef2aSThomas Huth tcg_temp_free(t1); 8624c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 8636b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 8644c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 8656b10d008SNikunj A Dadhania } 866fcf5ef2aSThomas Huth } else { 867fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 868fcf5ef2aSThomas Huth if (add_ca) { 8694c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 8704c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 871fcf5ef2aSThomas Huth } else { 8724c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 873fcf5ef2aSThomas Huth } 8744c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 875fcf5ef2aSThomas Huth tcg_temp_free(zero); 876fcf5ef2aSThomas Huth } 877fcf5ef2aSThomas Huth } else { 878fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 879fcf5ef2aSThomas Huth if (add_ca) { 8804c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 881fcf5ef2aSThomas Huth } 882fcf5ef2aSThomas Huth } 883fcf5ef2aSThomas Huth 884fcf5ef2aSThomas Huth if (compute_ov) { 885fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 886fcf5ef2aSThomas Huth } 887fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 888fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 889fcf5ef2aSThomas Huth } 890fcf5ef2aSThomas Huth 89111f4e8f8SRichard Henderson if (t0 != ret) { 892fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 893fcf5ef2aSThomas Huth tcg_temp_free(t0); 894fcf5ef2aSThomas Huth } 895fcf5ef2aSThomas Huth } 896fcf5ef2aSThomas Huth /* Add functions with two operands */ 8974c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 898fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 899fcf5ef2aSThomas Huth { \ 900fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 901fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 9024c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 903fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 904fcf5ef2aSThomas Huth } 905fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 9064c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 907fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 908fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 909fcf5ef2aSThomas Huth { \ 910fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 911fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 912fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 9134c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 914fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 915fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 916fcf5ef2aSThomas Huth } 917fcf5ef2aSThomas Huth 918fcf5ef2aSThomas Huth /* add add. addo addo. */ 9194c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 9204c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 921fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 9224c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 9234c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 924fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 9254c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 9264c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 927fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 9284c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 9294c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 9304c5920afSSuraj Jitindar Singh /* addex */ 9314c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 932fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 9334c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 9344c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 935fcf5ef2aSThomas Huth /* addi */ 936fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 937fcf5ef2aSThomas Huth { 938fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 939fcf5ef2aSThomas Huth 940fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 941fcf5ef2aSThomas Huth /* li case */ 942fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 943fcf5ef2aSThomas Huth } else { 944fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 945fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 946fcf5ef2aSThomas Huth } 947fcf5ef2aSThomas Huth } 948fcf5ef2aSThomas Huth /* addic addic.*/ 949fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 950fcf5ef2aSThomas Huth { 951fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 952fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 9534c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 954fcf5ef2aSThomas Huth tcg_temp_free(c); 955fcf5ef2aSThomas Huth } 956fcf5ef2aSThomas Huth 957fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 958fcf5ef2aSThomas Huth { 959fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 960fcf5ef2aSThomas Huth } 961fcf5ef2aSThomas Huth 962fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 963fcf5ef2aSThomas Huth { 964fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 965fcf5ef2aSThomas Huth } 966fcf5ef2aSThomas Huth 967fcf5ef2aSThomas Huth /* addis */ 968fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 969fcf5ef2aSThomas Huth { 970fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 971fcf5ef2aSThomas Huth 972fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 973fcf5ef2aSThomas Huth /* lis case */ 974fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 975fcf5ef2aSThomas Huth } else { 976fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 977fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 978fcf5ef2aSThomas Huth } 979fcf5ef2aSThomas Huth } 980fcf5ef2aSThomas Huth 981fcf5ef2aSThomas Huth /* addpcis */ 982fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 983fcf5ef2aSThomas Huth { 984fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 985fcf5ef2aSThomas Huth 986b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 987fcf5ef2aSThomas Huth } 988fcf5ef2aSThomas Huth 989fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 990fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 991fcf5ef2aSThomas Huth { 992fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 993fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 994fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 995fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 996fcf5ef2aSThomas Huth 997fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 998fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 999fcf5ef2aSThomas Huth if (sign) { 1000fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1001fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1002fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1003fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1004fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1005fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1006fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1007fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1008fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1009fcf5ef2aSThomas Huth } else { 1010fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1011fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1012fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1013fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1014fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1015fcf5ef2aSThomas Huth } 1016fcf5ef2aSThomas Huth if (compute_ov) { 1017fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1018c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1019c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1020c44027ffSNikunj A Dadhania } 1021fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1022fcf5ef2aSThomas Huth } 1023fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1024fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1025fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1026fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1027fcf5ef2aSThomas Huth 1028efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1029fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1030fcf5ef2aSThomas Huth } 1031efe843d8SDavid Gibson } 1032fcf5ef2aSThomas Huth /* Div functions */ 1033fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1034fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1035fcf5ef2aSThomas Huth { \ 1036fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1037fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1038fcf5ef2aSThomas Huth sign, compute_ov); \ 1039fcf5ef2aSThomas Huth } 1040fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1041fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1042fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1043fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1044fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1045fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1046fcf5ef2aSThomas Huth 1047fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1048fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1049fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1050fcf5ef2aSThomas Huth { \ 1051fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1052fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1053fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1054fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1055fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1056fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1057fcf5ef2aSThomas Huth } \ 1058fcf5ef2aSThomas Huth } 1059fcf5ef2aSThomas Huth 1060fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1061fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1062fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1063fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1064fcf5ef2aSThomas Huth 1065fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1066fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1067fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1068fcf5ef2aSThomas Huth { 1069fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1070fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1071fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1072fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1073fcf5ef2aSThomas Huth 1074fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1075fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1076fcf5ef2aSThomas Huth if (sign) { 1077fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1078fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1079fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1080fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1081fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1082fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1083fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1084fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1085fcf5ef2aSThomas Huth } else { 1086fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1087fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1088fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1089fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1090fcf5ef2aSThomas Huth } 1091fcf5ef2aSThomas Huth if (compute_ov) { 1092fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1093c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1094c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1095c44027ffSNikunj A Dadhania } 1096fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1097fcf5ef2aSThomas Huth } 1098fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1099fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1100fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1101fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1102fcf5ef2aSThomas Huth 1103efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1104fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1105fcf5ef2aSThomas Huth } 1106efe843d8SDavid Gibson } 1107fcf5ef2aSThomas Huth 1108fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1109fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1110fcf5ef2aSThomas Huth { \ 1111fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1112fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1113fcf5ef2aSThomas Huth sign, compute_ov); \ 1114fcf5ef2aSThomas Huth } 1115c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1116fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1117fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1118c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1119fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1120fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1121fcf5ef2aSThomas Huth 1122fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1123fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1124fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1125fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1126fcf5ef2aSThomas Huth #endif 1127fcf5ef2aSThomas Huth 1128fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1129fcf5ef2aSThomas Huth TCGv arg2, int sign) 1130fcf5ef2aSThomas Huth { 1131fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1132fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1133fcf5ef2aSThomas Huth 1134fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1135fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1136fcf5ef2aSThomas Huth if (sign) { 1137fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1138fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1139fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1140fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1141fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1142fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1143fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1144fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1145fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1146fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1147fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1148fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1149fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1150fcf5ef2aSThomas Huth } else { 1151fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1152fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1153fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1154fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1155fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1156fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1157fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1158fcf5ef2aSThomas Huth } 1159fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1160fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1161fcf5ef2aSThomas Huth } 1162fcf5ef2aSThomas Huth 1163fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1164fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1165fcf5ef2aSThomas Huth { \ 1166fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1167fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1168fcf5ef2aSThomas Huth sign); \ 1169fcf5ef2aSThomas Huth } 1170fcf5ef2aSThomas Huth 1171fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1172fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1173fcf5ef2aSThomas Huth 1174fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1175fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1176fcf5ef2aSThomas Huth TCGv arg2, int sign) 1177fcf5ef2aSThomas Huth { 1178fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1179fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1180fcf5ef2aSThomas Huth 1181fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1182fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1183fcf5ef2aSThomas Huth if (sign) { 1184fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1185fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1186fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1187fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1188fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1189fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1190fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1191fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1192fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1193fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1194fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1195fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1196fcf5ef2aSThomas Huth } else { 1197fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1198fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1199fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1200fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1201fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1202fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1203fcf5ef2aSThomas Huth } 1204fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1205fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1206fcf5ef2aSThomas Huth } 1207fcf5ef2aSThomas Huth 1208fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1209fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1210fcf5ef2aSThomas Huth { \ 1211fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1212fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1213fcf5ef2aSThomas Huth sign); \ 1214fcf5ef2aSThomas Huth } 1215fcf5ef2aSThomas Huth 1216fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1217fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1218fcf5ef2aSThomas Huth #endif 1219fcf5ef2aSThomas Huth 1220fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1221fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1222fcf5ef2aSThomas Huth { 1223fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1224fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1225fcf5ef2aSThomas Huth 1226fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1227fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1228fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1229fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1230fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1231fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1232efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1233fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1234fcf5ef2aSThomas Huth } 1235efe843d8SDavid Gibson } 1236fcf5ef2aSThomas Huth 1237fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1238fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1239fcf5ef2aSThomas Huth { 1240fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1241fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1242fcf5ef2aSThomas Huth 1243fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1244fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1245fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1246fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1247fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1248fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1249efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1250fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1251fcf5ef2aSThomas Huth } 1252efe843d8SDavid Gibson } 1253fcf5ef2aSThomas Huth 1254fcf5ef2aSThomas Huth /* mullw mullw. */ 1255fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1256fcf5ef2aSThomas Huth { 1257fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1258fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1259fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1260fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1261fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1262fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1263fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1264fcf5ef2aSThomas Huth tcg_temp_free(t0); 1265fcf5ef2aSThomas Huth tcg_temp_free(t1); 1266fcf5ef2aSThomas Huth #else 1267fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1268fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1269fcf5ef2aSThomas Huth #endif 1270efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1271fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1272fcf5ef2aSThomas Huth } 1273efe843d8SDavid Gibson } 1274fcf5ef2aSThomas Huth 1275fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1276fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1277fcf5ef2aSThomas Huth { 1278fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1279fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1280fcf5ef2aSThomas Huth 1281fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1282fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1283fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1284fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1285fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1286fcf5ef2aSThomas Huth #else 1287fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1288fcf5ef2aSThomas Huth #endif 1289fcf5ef2aSThomas Huth 1290fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1291fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1292fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 129361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 129461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 129561aa9a69SNikunj A Dadhania } 1296fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1297fcf5ef2aSThomas Huth 1298fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1299fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1300efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1301fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1302fcf5ef2aSThomas Huth } 1303efe843d8SDavid Gibson } 1304fcf5ef2aSThomas Huth 1305fcf5ef2aSThomas Huth /* mulli */ 1306fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1307fcf5ef2aSThomas Huth { 1308fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1309fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1310fcf5ef2aSThomas Huth } 1311fcf5ef2aSThomas Huth 1312fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1313fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1314fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1315fcf5ef2aSThomas Huth { 1316fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1317fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1318fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1319fcf5ef2aSThomas Huth tcg_temp_free(lo); 1320fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1321fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1322fcf5ef2aSThomas Huth } 1323fcf5ef2aSThomas Huth } 1324fcf5ef2aSThomas Huth 1325fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1326fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1327fcf5ef2aSThomas Huth { 1328fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1329fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1330fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1331fcf5ef2aSThomas Huth tcg_temp_free(lo); 1332fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1333fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1334fcf5ef2aSThomas Huth } 1335fcf5ef2aSThomas Huth } 1336fcf5ef2aSThomas Huth 1337fcf5ef2aSThomas Huth /* mulld mulld. */ 1338fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1339fcf5ef2aSThomas Huth { 1340fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1341fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1342efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1343fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1344fcf5ef2aSThomas Huth } 1345efe843d8SDavid Gibson } 1346fcf5ef2aSThomas Huth 1347fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1348fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1349fcf5ef2aSThomas Huth { 1350fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1351fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1352fcf5ef2aSThomas Huth 1353fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1354fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1355fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1356fcf5ef2aSThomas Huth 1357fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1358fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 135961aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 136061aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 136161aa9a69SNikunj A Dadhania } 1362fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1363fcf5ef2aSThomas Huth 1364fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1365fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1366fcf5ef2aSThomas Huth 1367fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1368fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1369fcf5ef2aSThomas Huth } 1370fcf5ef2aSThomas Huth } 1371fcf5ef2aSThomas Huth #endif 1372fcf5ef2aSThomas Huth 1373fcf5ef2aSThomas Huth /* Common subf function */ 1374fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1375fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1376fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1377fcf5ef2aSThomas Huth { 1378fcf5ef2aSThomas Huth TCGv t0 = ret; 1379fcf5ef2aSThomas Huth 1380fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1381fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1382fcf5ef2aSThomas Huth } 1383fcf5ef2aSThomas Huth 1384fcf5ef2aSThomas Huth if (compute_ca) { 1385fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1386fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1387efe843d8SDavid Gibson /* 1388efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1389efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1390efe843d8SDavid Gibson * produce the carry into bit 32. 1391efe843d8SDavid Gibson */ 1392fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1393fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1394fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1395fcf5ef2aSThomas Huth if (add_ca) { 1396fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1397fcf5ef2aSThomas Huth } else { 1398fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1399fcf5ef2aSThomas Huth } 1400fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1401fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1402fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1403fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1404fcf5ef2aSThomas Huth tcg_temp_free(t1); 1405e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 140633903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 140733903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 140833903d0aSNikunj A Dadhania } 1409fcf5ef2aSThomas Huth } else if (add_ca) { 1410fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1411fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1412fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1413fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1414fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 14154c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1416fcf5ef2aSThomas Huth tcg_temp_free(zero); 1417fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1418fcf5ef2aSThomas Huth } else { 1419fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1420fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 14214c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1422fcf5ef2aSThomas Huth } 1423fcf5ef2aSThomas Huth } else if (add_ca) { 1424efe843d8SDavid Gibson /* 1425efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 1426efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1427efe843d8SDavid Gibson */ 1428fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1429fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1430fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1431fcf5ef2aSThomas Huth } else { 1432fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1433fcf5ef2aSThomas Huth } 1434fcf5ef2aSThomas Huth 1435fcf5ef2aSThomas Huth if (compute_ov) { 1436fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1437fcf5ef2aSThomas Huth } 1438fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1439fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1440fcf5ef2aSThomas Huth } 1441fcf5ef2aSThomas Huth 144211f4e8f8SRichard Henderson if (t0 != ret) { 1443fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1444fcf5ef2aSThomas Huth tcg_temp_free(t0); 1445fcf5ef2aSThomas Huth } 1446fcf5ef2aSThomas Huth } 1447fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1448fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1449fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1450fcf5ef2aSThomas Huth { \ 1451fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1452fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1453fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1454fcf5ef2aSThomas Huth } 1455fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1456fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1457fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1458fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1459fcf5ef2aSThomas Huth { \ 1460fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1461fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1462fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1463fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1464fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1465fcf5ef2aSThomas Huth } 1466fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1467fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1468fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1469fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1470fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1471fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1472fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1473fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1474fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1475fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1476fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1477fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1478fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1479fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1480fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1481fcf5ef2aSThomas Huth 1482fcf5ef2aSThomas Huth /* subfic */ 1483fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1484fcf5ef2aSThomas Huth { 1485fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1486fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1487fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1488fcf5ef2aSThomas Huth tcg_temp_free(c); 1489fcf5ef2aSThomas Huth } 1490fcf5ef2aSThomas Huth 1491fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1492fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1493fcf5ef2aSThomas Huth { 1494fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1495fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1496fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1497fcf5ef2aSThomas Huth tcg_temp_free(zero); 1498fcf5ef2aSThomas Huth } 1499fcf5ef2aSThomas Huth 1500fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1501fcf5ef2aSThomas Huth { 15021480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 15031480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 15041480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 15051480d71cSNikunj A Dadhania } 1506fcf5ef2aSThomas Huth } 1507fcf5ef2aSThomas Huth 1508fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1509fcf5ef2aSThomas Huth { 1510fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1511fcf5ef2aSThomas Huth } 1512fcf5ef2aSThomas Huth 1513fcf5ef2aSThomas Huth /*** Integer logical ***/ 1514fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1515fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1516fcf5ef2aSThomas Huth { \ 1517fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1518fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1519fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1520fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1521fcf5ef2aSThomas Huth } 1522fcf5ef2aSThomas Huth 1523fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1524fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1525fcf5ef2aSThomas Huth { \ 1526fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1527fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1528fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1529fcf5ef2aSThomas Huth } 1530fcf5ef2aSThomas Huth 1531fcf5ef2aSThomas Huth /* and & and. */ 1532fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1533fcf5ef2aSThomas Huth /* andc & andc. */ 1534fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1535fcf5ef2aSThomas Huth 1536fcf5ef2aSThomas Huth /* andi. */ 1537fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1538fcf5ef2aSThomas Huth { 1539efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1540efe843d8SDavid Gibson UIMM(ctx->opcode)); 1541fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1542fcf5ef2aSThomas Huth } 1543fcf5ef2aSThomas Huth 1544fcf5ef2aSThomas Huth /* andis. */ 1545fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1546fcf5ef2aSThomas Huth { 1547efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1548efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 1549fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1550fcf5ef2aSThomas Huth } 1551fcf5ef2aSThomas Huth 1552fcf5ef2aSThomas Huth /* cntlzw */ 1553fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1554fcf5ef2aSThomas Huth { 15559b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15569b8514e5SRichard Henderson 15579b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15589b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15599b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15609b8514e5SRichard Henderson tcg_temp_free_i32(t); 15619b8514e5SRichard Henderson 1562efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1563fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1564fcf5ef2aSThomas Huth } 1565efe843d8SDavid Gibson } 1566fcf5ef2aSThomas Huth 1567fcf5ef2aSThomas Huth /* cnttzw */ 1568fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1569fcf5ef2aSThomas Huth { 15709b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15719b8514e5SRichard Henderson 15729b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15739b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15749b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15759b8514e5SRichard Henderson tcg_temp_free_i32(t); 15769b8514e5SRichard Henderson 1577fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1578fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1579fcf5ef2aSThomas Huth } 1580fcf5ef2aSThomas Huth } 1581fcf5ef2aSThomas Huth 1582fcf5ef2aSThomas Huth /* eqv & eqv. */ 1583fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1584fcf5ef2aSThomas Huth /* extsb & extsb. */ 1585fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1586fcf5ef2aSThomas Huth /* extsh & extsh. */ 1587fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1588fcf5ef2aSThomas Huth /* nand & nand. */ 1589fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1590fcf5ef2aSThomas Huth /* nor & nor. */ 1591fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1592fcf5ef2aSThomas Huth 1593fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1594fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1595fcf5ef2aSThomas Huth { 1596fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1597fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1598fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1599fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1600fcf5ef2aSThomas Huth 1601fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1602b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1603fcf5ef2aSThomas Huth } 1604fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1605fcf5ef2aSThomas Huth 1606fcf5ef2aSThomas Huth /* or & or. */ 1607fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1608fcf5ef2aSThomas Huth { 1609fcf5ef2aSThomas Huth int rs, ra, rb; 1610fcf5ef2aSThomas Huth 1611fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1612fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1613fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1614fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1615fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1616efe843d8SDavid Gibson if (rs != rb) { 1617fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1618efe843d8SDavid Gibson } else { 1619fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1620efe843d8SDavid Gibson } 1621efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1622fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1623efe843d8SDavid Gibson } 1624fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1625fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1626fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1627fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1628fcf5ef2aSThomas Huth int prio = 0; 1629fcf5ef2aSThomas Huth 1630fcf5ef2aSThomas Huth switch (rs) { 1631fcf5ef2aSThomas Huth case 1: 1632fcf5ef2aSThomas Huth /* Set process priority to low */ 1633fcf5ef2aSThomas Huth prio = 2; 1634fcf5ef2aSThomas Huth break; 1635fcf5ef2aSThomas Huth case 6: 1636fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1637fcf5ef2aSThomas Huth prio = 3; 1638fcf5ef2aSThomas Huth break; 1639fcf5ef2aSThomas Huth case 2: 1640fcf5ef2aSThomas Huth /* Set process priority to normal */ 1641fcf5ef2aSThomas Huth prio = 4; 1642fcf5ef2aSThomas Huth break; 1643fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1644fcf5ef2aSThomas Huth case 31: 1645fcf5ef2aSThomas Huth if (!ctx->pr) { 1646fcf5ef2aSThomas Huth /* Set process priority to very low */ 1647fcf5ef2aSThomas Huth prio = 1; 1648fcf5ef2aSThomas Huth } 1649fcf5ef2aSThomas Huth break; 1650fcf5ef2aSThomas Huth case 5: 1651fcf5ef2aSThomas Huth if (!ctx->pr) { 1652fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1653fcf5ef2aSThomas Huth prio = 5; 1654fcf5ef2aSThomas Huth } 1655fcf5ef2aSThomas Huth break; 1656fcf5ef2aSThomas Huth case 3: 1657fcf5ef2aSThomas Huth if (!ctx->pr) { 1658fcf5ef2aSThomas Huth /* Set process priority to high */ 1659fcf5ef2aSThomas Huth prio = 6; 1660fcf5ef2aSThomas Huth } 1661fcf5ef2aSThomas Huth break; 1662fcf5ef2aSThomas Huth case 7: 1663fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1664fcf5ef2aSThomas Huth /* Set process priority to very high */ 1665fcf5ef2aSThomas Huth prio = 7; 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth break; 1668fcf5ef2aSThomas Huth #endif 1669fcf5ef2aSThomas Huth default: 1670fcf5ef2aSThomas Huth break; 1671fcf5ef2aSThomas Huth } 1672fcf5ef2aSThomas Huth if (prio) { 1673fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1674fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1675fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1676fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1677fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1678fcf5ef2aSThomas Huth tcg_temp_free(t0); 1679fcf5ef2aSThomas Huth } 1680fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1681efe843d8SDavid Gibson /* 1682efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 1683efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 1684efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 1685efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 1686fcf5ef2aSThomas Huth */ 1687fcf5ef2aSThomas Huth gen_pause(ctx); 1688fcf5ef2aSThomas Huth #endif 1689fcf5ef2aSThomas Huth #endif 1690fcf5ef2aSThomas Huth } 1691fcf5ef2aSThomas Huth } 1692fcf5ef2aSThomas Huth /* orc & orc. */ 1693fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1694fcf5ef2aSThomas Huth 1695fcf5ef2aSThomas Huth /* xor & xor. */ 1696fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1697fcf5ef2aSThomas Huth { 1698fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1699efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 1700efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1701efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 1702efe843d8SDavid Gibson } else { 1703fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1704efe843d8SDavid Gibson } 1705efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1706fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1707fcf5ef2aSThomas Huth } 1708efe843d8SDavid Gibson } 1709fcf5ef2aSThomas Huth 1710fcf5ef2aSThomas Huth /* ori */ 1711fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1712fcf5ef2aSThomas Huth { 1713fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1714fcf5ef2aSThomas Huth 1715fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1716fcf5ef2aSThomas Huth return; 1717fcf5ef2aSThomas Huth } 1718fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1719fcf5ef2aSThomas Huth } 1720fcf5ef2aSThomas Huth 1721fcf5ef2aSThomas Huth /* oris */ 1722fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1723fcf5ef2aSThomas Huth { 1724fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1725fcf5ef2aSThomas Huth 1726fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1727fcf5ef2aSThomas Huth /* NOP */ 1728fcf5ef2aSThomas Huth return; 1729fcf5ef2aSThomas Huth } 1730efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1731efe843d8SDavid Gibson uimm << 16); 1732fcf5ef2aSThomas Huth } 1733fcf5ef2aSThomas Huth 1734fcf5ef2aSThomas Huth /* xori */ 1735fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1736fcf5ef2aSThomas Huth { 1737fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1738fcf5ef2aSThomas Huth 1739fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1740fcf5ef2aSThomas Huth /* NOP */ 1741fcf5ef2aSThomas Huth return; 1742fcf5ef2aSThomas Huth } 1743fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1744fcf5ef2aSThomas Huth } 1745fcf5ef2aSThomas Huth 1746fcf5ef2aSThomas Huth /* xoris */ 1747fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1748fcf5ef2aSThomas Huth { 1749fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1750fcf5ef2aSThomas Huth 1751fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1752fcf5ef2aSThomas Huth /* NOP */ 1753fcf5ef2aSThomas Huth return; 1754fcf5ef2aSThomas Huth } 1755efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1756efe843d8SDavid Gibson uimm << 16); 1757fcf5ef2aSThomas Huth } 1758fcf5ef2aSThomas Huth 1759fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1760fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1761fcf5ef2aSThomas Huth { 1762fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1763fcf5ef2aSThomas Huth } 1764fcf5ef2aSThomas Huth 1765fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1766fcf5ef2aSThomas Huth { 176779770002SRichard Henderson #if defined(TARGET_PPC64) 1768fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 176979770002SRichard Henderson #else 177079770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 177179770002SRichard Henderson #endif 1772fcf5ef2aSThomas Huth } 1773fcf5ef2aSThomas Huth 1774fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1775fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1776fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1777fcf5ef2aSThomas Huth { 177879770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1779fcf5ef2aSThomas Huth } 1780fcf5ef2aSThomas Huth #endif 1781fcf5ef2aSThomas Huth 1782fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1783fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1784fcf5ef2aSThomas Huth { 1785fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1786fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1787fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1788fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1789fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1790fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1791fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1792fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1793fcf5ef2aSThomas Huth tcg_temp_free(t0); 1794fcf5ef2aSThomas Huth } 1795fcf5ef2aSThomas Huth 1796fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1797fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1798fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1799fcf5ef2aSThomas Huth { 1800fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1801fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1802fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1803fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1804fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1805fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1806fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1807fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1808fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1809fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1810fcf5ef2aSThomas Huth tcg_temp_free(t0); 1811fcf5ef2aSThomas Huth } 1812fcf5ef2aSThomas Huth #endif 1813fcf5ef2aSThomas Huth 1814fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1815fcf5ef2aSThomas Huth /* bpermd */ 1816fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1817fcf5ef2aSThomas Huth { 1818fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1819fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1820fcf5ef2aSThomas Huth } 1821fcf5ef2aSThomas Huth #endif 1822fcf5ef2aSThomas Huth 1823fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1824fcf5ef2aSThomas Huth /* extsw & extsw. */ 1825fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1826fcf5ef2aSThomas Huth 1827fcf5ef2aSThomas Huth /* cntlzd */ 1828fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1829fcf5ef2aSThomas Huth { 18309b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1831efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1832fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1833fcf5ef2aSThomas Huth } 1834efe843d8SDavid Gibson } 1835fcf5ef2aSThomas Huth 1836fcf5ef2aSThomas Huth /* cnttzd */ 1837fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1838fcf5ef2aSThomas Huth { 18399b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1840fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1841fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1842fcf5ef2aSThomas Huth } 1843fcf5ef2aSThomas Huth } 1844fcf5ef2aSThomas Huth 1845fcf5ef2aSThomas Huth /* darn */ 1846fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1847fcf5ef2aSThomas Huth { 1848fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1849fcf5ef2aSThomas Huth 1850*7e4357f6SRichard Henderson if (l > 2) { 1851*7e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1852*7e4357f6SRichard Henderson } else { 1853*7e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 1854*7e4357f6SRichard Henderson gen_io_start(); 1855*7e4357f6SRichard Henderson } 1856fcf5ef2aSThomas Huth if (l == 0) { 1857fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1858*7e4357f6SRichard Henderson } else { 1859fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1860fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1861*7e4357f6SRichard Henderson } 1862*7e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 1863*7e4357f6SRichard Henderson gen_io_end(); 1864*7e4357f6SRichard Henderson gen_stop_exception(ctx); 1865*7e4357f6SRichard Henderson } 1866fcf5ef2aSThomas Huth } 1867fcf5ef2aSThomas Huth } 1868fcf5ef2aSThomas Huth #endif 1869fcf5ef2aSThomas Huth 1870fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1871fcf5ef2aSThomas Huth 1872fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1873fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1874fcf5ef2aSThomas Huth { 1875fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1876fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1877fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1878fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1879fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1880fcf5ef2aSThomas Huth 1881fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 1882fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1883fcf5ef2aSThomas Huth } else { 1884fcf5ef2aSThomas Huth target_ulong mask; 1885fcf5ef2aSThomas Huth TCGv t1; 1886fcf5ef2aSThomas Huth 1887fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1888fcf5ef2aSThomas Huth mb += 32; 1889fcf5ef2aSThomas Huth me += 32; 1890fcf5ef2aSThomas Huth #endif 1891fcf5ef2aSThomas Huth mask = MASK(mb, me); 1892fcf5ef2aSThomas Huth 1893fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1894fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1895fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1896fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1897fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1898fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1899fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1900fcf5ef2aSThomas Huth } else { 1901fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1902fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1903fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1904fcf5ef2aSThomas Huth #else 1905fcf5ef2aSThomas Huth g_assert_not_reached(); 1906fcf5ef2aSThomas Huth #endif 1907fcf5ef2aSThomas Huth } 1908fcf5ef2aSThomas Huth 1909fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1910fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1911fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1912fcf5ef2aSThomas Huth tcg_temp_free(t1); 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1915fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1916fcf5ef2aSThomas Huth } 1917fcf5ef2aSThomas Huth } 1918fcf5ef2aSThomas Huth 1919fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1920fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1921fcf5ef2aSThomas Huth { 1922fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1923fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 19247b4d326fSRichard Henderson int sh = SH(ctx->opcode); 19257b4d326fSRichard Henderson int mb = MB(ctx->opcode); 19267b4d326fSRichard Henderson int me = ME(ctx->opcode); 19277b4d326fSRichard Henderson int len = me - mb + 1; 19287b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1929fcf5ef2aSThomas Huth 19307b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 19317b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 19327b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 19337b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1934fcf5ef2aSThomas Huth } else { 1935fcf5ef2aSThomas Huth target_ulong mask; 1936fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1937fcf5ef2aSThomas Huth mb += 32; 1938fcf5ef2aSThomas Huth me += 32; 1939fcf5ef2aSThomas Huth #endif 1940fcf5ef2aSThomas Huth mask = MASK(mb, me); 19417b4d326fSRichard Henderson if (sh == 0) { 19427b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 19437b4d326fSRichard Henderson } else if (mask <= 0xffffffffu) { 1944fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1945fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1946fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1947fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1948fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1949fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1950fcf5ef2aSThomas Huth } else { 1951fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1952fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1953fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1954fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1955fcf5ef2aSThomas Huth #else 1956fcf5ef2aSThomas Huth g_assert_not_reached(); 1957fcf5ef2aSThomas Huth #endif 1958fcf5ef2aSThomas Huth } 1959fcf5ef2aSThomas Huth } 1960fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1961fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1962fcf5ef2aSThomas Huth } 1963fcf5ef2aSThomas Huth } 1964fcf5ef2aSThomas Huth 1965fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1966fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1967fcf5ef2aSThomas Huth { 1968fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1969fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1970fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1971fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1972fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1973fcf5ef2aSThomas Huth target_ulong mask; 1974fcf5ef2aSThomas Huth 1975fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1976fcf5ef2aSThomas Huth mb += 32; 1977fcf5ef2aSThomas Huth me += 32; 1978fcf5ef2aSThomas Huth #endif 1979fcf5ef2aSThomas Huth mask = MASK(mb, me); 1980fcf5ef2aSThomas Huth 1981fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1982fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1983fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1984fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1985fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1986fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1987fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1988fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1989fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1990fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1991fcf5ef2aSThomas Huth } else { 1992fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1993fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1994fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1995fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1996fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1997fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1998fcf5ef2aSThomas Huth #else 1999fcf5ef2aSThomas Huth g_assert_not_reached(); 2000fcf5ef2aSThomas Huth #endif 2001fcf5ef2aSThomas Huth } 2002fcf5ef2aSThomas Huth 2003fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2004fcf5ef2aSThomas Huth 2005fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2006fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2007fcf5ef2aSThomas Huth } 2008fcf5ef2aSThomas Huth } 2009fcf5ef2aSThomas Huth 2010fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2011fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2012fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2013fcf5ef2aSThomas Huth { \ 2014fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2015fcf5ef2aSThomas Huth } \ 2016fcf5ef2aSThomas Huth \ 2017fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2018fcf5ef2aSThomas Huth { \ 2019fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2020fcf5ef2aSThomas Huth } 2021fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2022fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2023fcf5ef2aSThomas Huth { \ 2024fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2025fcf5ef2aSThomas Huth } \ 2026fcf5ef2aSThomas Huth \ 2027fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2028fcf5ef2aSThomas Huth { \ 2029fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2030fcf5ef2aSThomas Huth } \ 2031fcf5ef2aSThomas Huth \ 2032fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2033fcf5ef2aSThomas Huth { \ 2034fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2035fcf5ef2aSThomas Huth } \ 2036fcf5ef2aSThomas Huth \ 2037fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2038fcf5ef2aSThomas Huth { \ 2039fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2040fcf5ef2aSThomas Huth } 2041fcf5ef2aSThomas Huth 2042fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2043fcf5ef2aSThomas Huth { 2044fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2045fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20467b4d326fSRichard Henderson int len = me - mb + 1; 20477b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2048fcf5ef2aSThomas Huth 20497b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20507b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20517b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20527b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2053fcf5ef2aSThomas Huth } else { 2054fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2055fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2056fcf5ef2aSThomas Huth } 2057fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2058fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2059fcf5ef2aSThomas Huth } 2060fcf5ef2aSThomas Huth } 2061fcf5ef2aSThomas Huth 2062fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2063fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2064fcf5ef2aSThomas Huth { 2065fcf5ef2aSThomas Huth uint32_t sh, mb; 2066fcf5ef2aSThomas Huth 2067fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2068fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2069fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2070fcf5ef2aSThomas Huth } 2071fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2072fcf5ef2aSThomas Huth 2073fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2074fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2075fcf5ef2aSThomas Huth { 2076fcf5ef2aSThomas Huth uint32_t sh, me; 2077fcf5ef2aSThomas Huth 2078fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2079fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2080fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2081fcf5ef2aSThomas Huth } 2082fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2083fcf5ef2aSThomas Huth 2084fcf5ef2aSThomas Huth /* rldic - rldic. */ 2085fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2086fcf5ef2aSThomas Huth { 2087fcf5ef2aSThomas Huth uint32_t sh, mb; 2088fcf5ef2aSThomas Huth 2089fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2090fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2091fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2092fcf5ef2aSThomas Huth } 2093fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2094fcf5ef2aSThomas Huth 2095fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2096fcf5ef2aSThomas Huth { 2097fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2098fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2099fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2100fcf5ef2aSThomas Huth TCGv t0; 2101fcf5ef2aSThomas Huth 2102fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2103fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2104fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2105fcf5ef2aSThomas Huth tcg_temp_free(t0); 2106fcf5ef2aSThomas Huth 2107fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2108fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2109fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2110fcf5ef2aSThomas Huth } 2111fcf5ef2aSThomas Huth } 2112fcf5ef2aSThomas Huth 2113fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2114fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2115fcf5ef2aSThomas Huth { 2116fcf5ef2aSThomas Huth uint32_t mb; 2117fcf5ef2aSThomas Huth 2118fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2119fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2120fcf5ef2aSThomas Huth } 2121fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2122fcf5ef2aSThomas Huth 2123fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2124fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2125fcf5ef2aSThomas Huth { 2126fcf5ef2aSThomas Huth uint32_t me; 2127fcf5ef2aSThomas Huth 2128fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2129fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2130fcf5ef2aSThomas Huth } 2131fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2132fcf5ef2aSThomas Huth 2133fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2134fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2135fcf5ef2aSThomas Huth { 2136fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2137fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2138fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2139fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2140fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2141fcf5ef2aSThomas Huth 2142fcf5ef2aSThomas Huth if (mb <= me) { 2143fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2144fcf5ef2aSThomas Huth } else { 2145fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2146fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2147fcf5ef2aSThomas Huth 2148fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2149fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2150fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2151fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2152fcf5ef2aSThomas Huth tcg_temp_free(t1); 2153fcf5ef2aSThomas Huth } 2154fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2155fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2156fcf5ef2aSThomas Huth } 2157fcf5ef2aSThomas Huth } 2158fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2159fcf5ef2aSThomas Huth #endif 2160fcf5ef2aSThomas Huth 2161fcf5ef2aSThomas Huth /*** Integer shift ***/ 2162fcf5ef2aSThomas Huth 2163fcf5ef2aSThomas Huth /* slw & slw. */ 2164fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2165fcf5ef2aSThomas Huth { 2166fcf5ef2aSThomas Huth TCGv t0, t1; 2167fcf5ef2aSThomas Huth 2168fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2169fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2170fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2171fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2172fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2173fcf5ef2aSThomas Huth #else 2174fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2175fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2176fcf5ef2aSThomas Huth #endif 2177fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2178fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2179fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2180fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2181fcf5ef2aSThomas Huth tcg_temp_free(t1); 2182fcf5ef2aSThomas Huth tcg_temp_free(t0); 2183fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2184efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2185fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2186fcf5ef2aSThomas Huth } 2187efe843d8SDavid Gibson } 2188fcf5ef2aSThomas Huth 2189fcf5ef2aSThomas Huth /* sraw & sraw. */ 2190fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2191fcf5ef2aSThomas Huth { 2192fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2193fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2194efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2195fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2196fcf5ef2aSThomas Huth } 2197efe843d8SDavid Gibson } 2198fcf5ef2aSThomas Huth 2199fcf5ef2aSThomas Huth /* srawi & srawi. */ 2200fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2201fcf5ef2aSThomas Huth { 2202fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2203fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2204fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2205fcf5ef2aSThomas Huth if (sh == 0) { 2206fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2207fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2208af1c259fSSandipan Das if (is_isa300(ctx)) { 2209af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2210af1c259fSSandipan Das } 2211fcf5ef2aSThomas Huth } else { 2212fcf5ef2aSThomas Huth TCGv t0; 2213fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2214fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2215fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2216fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2217fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2218fcf5ef2aSThomas Huth tcg_temp_free(t0); 2219fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2220af1c259fSSandipan Das if (is_isa300(ctx)) { 2221af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2222af1c259fSSandipan Das } 2223fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2224fcf5ef2aSThomas Huth } 2225fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2226fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2227fcf5ef2aSThomas Huth } 2228fcf5ef2aSThomas Huth } 2229fcf5ef2aSThomas Huth 2230fcf5ef2aSThomas Huth /* srw & srw. */ 2231fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2232fcf5ef2aSThomas Huth { 2233fcf5ef2aSThomas Huth TCGv t0, t1; 2234fcf5ef2aSThomas Huth 2235fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2236fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2237fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2238fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2239fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2240fcf5ef2aSThomas Huth #else 2241fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2242fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2243fcf5ef2aSThomas Huth #endif 2244fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2245fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2246fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2247fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2248fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2249fcf5ef2aSThomas Huth tcg_temp_free(t1); 2250fcf5ef2aSThomas Huth tcg_temp_free(t0); 2251efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2252fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2253fcf5ef2aSThomas Huth } 2254efe843d8SDavid Gibson } 2255fcf5ef2aSThomas Huth 2256fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2257fcf5ef2aSThomas Huth /* sld & sld. */ 2258fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2259fcf5ef2aSThomas Huth { 2260fcf5ef2aSThomas Huth TCGv t0, t1; 2261fcf5ef2aSThomas Huth 2262fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2263fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2264fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2265fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2266fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2267fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2268fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2269fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2270fcf5ef2aSThomas Huth tcg_temp_free(t1); 2271fcf5ef2aSThomas Huth tcg_temp_free(t0); 2272efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2273fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2274fcf5ef2aSThomas Huth } 2275efe843d8SDavid Gibson } 2276fcf5ef2aSThomas Huth 2277fcf5ef2aSThomas Huth /* srad & srad. */ 2278fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2279fcf5ef2aSThomas Huth { 2280fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2281fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2282efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2283fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2284fcf5ef2aSThomas Huth } 2285efe843d8SDavid Gibson } 2286fcf5ef2aSThomas Huth /* sradi & sradi. */ 2287fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2288fcf5ef2aSThomas Huth { 2289fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2290fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2291fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2292fcf5ef2aSThomas Huth if (sh == 0) { 2293fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2294fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2295af1c259fSSandipan Das if (is_isa300(ctx)) { 2296af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2297af1c259fSSandipan Das } 2298fcf5ef2aSThomas Huth } else { 2299fcf5ef2aSThomas Huth TCGv t0; 2300fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2301fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2302fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2303fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2304fcf5ef2aSThomas Huth tcg_temp_free(t0); 2305fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2306af1c259fSSandipan Das if (is_isa300(ctx)) { 2307af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2308af1c259fSSandipan Das } 2309fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2310fcf5ef2aSThomas Huth } 2311fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2312fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2313fcf5ef2aSThomas Huth } 2314fcf5ef2aSThomas Huth } 2315fcf5ef2aSThomas Huth 2316fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2317fcf5ef2aSThomas Huth { 2318fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2319fcf5ef2aSThomas Huth } 2320fcf5ef2aSThomas Huth 2321fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2322fcf5ef2aSThomas Huth { 2323fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2324fcf5ef2aSThomas Huth } 2325fcf5ef2aSThomas Huth 2326fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2327fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2328fcf5ef2aSThomas Huth { 2329fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2330fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2331fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2332fcf5ef2aSThomas Huth 2333fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2334fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2335fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2336fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2337fcf5ef2aSThomas Huth } 2338fcf5ef2aSThomas Huth } 2339fcf5ef2aSThomas Huth 2340fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2341fcf5ef2aSThomas Huth { 2342fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2343fcf5ef2aSThomas Huth } 2344fcf5ef2aSThomas Huth 2345fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2346fcf5ef2aSThomas Huth { 2347fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2348fcf5ef2aSThomas Huth } 2349fcf5ef2aSThomas Huth 2350fcf5ef2aSThomas Huth /* srd & srd. */ 2351fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2352fcf5ef2aSThomas Huth { 2353fcf5ef2aSThomas Huth TCGv t0, t1; 2354fcf5ef2aSThomas Huth 2355fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2356fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2357fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2358fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2359fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2360fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2361fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2362fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2363fcf5ef2aSThomas Huth tcg_temp_free(t1); 2364fcf5ef2aSThomas Huth tcg_temp_free(t0); 2365efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2366fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2367fcf5ef2aSThomas Huth } 2368efe843d8SDavid Gibson } 2369fcf5ef2aSThomas Huth #endif 2370fcf5ef2aSThomas Huth 2371fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2372fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2373fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2374fcf5ef2aSThomas Huth target_long maskl) 2375fcf5ef2aSThomas Huth { 2376fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2377fcf5ef2aSThomas Huth 2378fcf5ef2aSThomas Huth simm &= ~maskl; 2379fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2380fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2381fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2382fcf5ef2aSThomas Huth } 2383fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2384fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2385fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2386fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2387fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2388fcf5ef2aSThomas Huth } 2389fcf5ef2aSThomas Huth } else { 2390fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2391fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2392fcf5ef2aSThomas Huth } else { 2393fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2394fcf5ef2aSThomas Huth } 2395fcf5ef2aSThomas Huth } 2396fcf5ef2aSThomas Huth } 2397fcf5ef2aSThomas Huth 2398fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2399fcf5ef2aSThomas Huth { 2400fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2401fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2402fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2403fcf5ef2aSThomas Huth } else { 2404fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2405fcf5ef2aSThomas Huth } 2406fcf5ef2aSThomas Huth } else { 2407fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2408fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2409fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2410fcf5ef2aSThomas Huth } 2411fcf5ef2aSThomas Huth } 2412fcf5ef2aSThomas Huth } 2413fcf5ef2aSThomas Huth 2414fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2415fcf5ef2aSThomas Huth { 2416fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2417fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2418fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2419fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2420fcf5ef2aSThomas Huth } else { 2421fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2422fcf5ef2aSThomas Huth } 2423fcf5ef2aSThomas Huth } 2424fcf5ef2aSThomas Huth 2425fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2426fcf5ef2aSThomas Huth target_long val) 2427fcf5ef2aSThomas Huth { 2428fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2429fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2430fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2431fcf5ef2aSThomas Huth } 2432fcf5ef2aSThomas Huth } 2433fcf5ef2aSThomas Huth 2434fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2435fcf5ef2aSThomas Huth { 2436fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2437fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2438fcf5ef2aSThomas Huth } 2439fcf5ef2aSThomas Huth 2440fcf5ef2aSThomas Huth /*** Integer load ***/ 2441fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2442fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2443fcf5ef2aSThomas Huth 2444fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2445fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2446fcf5ef2aSThomas Huth TCGv val, \ 2447fcf5ef2aSThomas Huth TCGv addr) \ 2448fcf5ef2aSThomas Huth { \ 2449fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2450fcf5ef2aSThomas Huth } 2451fcf5ef2aSThomas Huth 2452fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2453fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2454fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2455fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2456fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2457fcf5ef2aSThomas Huth 2458fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2459fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2460fcf5ef2aSThomas Huth 2461fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2462fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2463fcf5ef2aSThomas Huth TCGv_i64 val, \ 2464fcf5ef2aSThomas Huth TCGv addr) \ 2465fcf5ef2aSThomas Huth { \ 2466fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2467fcf5ef2aSThomas Huth } 2468fcf5ef2aSThomas Huth 2469fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2470fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2471fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2472fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2473fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2474fcf5ef2aSThomas Huth 2475fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2476fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2477fcf5ef2aSThomas Huth #endif 2478fcf5ef2aSThomas Huth 2479fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2480fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2481fcf5ef2aSThomas Huth TCGv val, \ 2482fcf5ef2aSThomas Huth TCGv addr) \ 2483fcf5ef2aSThomas Huth { \ 2484fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2485fcf5ef2aSThomas Huth } 2486fcf5ef2aSThomas Huth 2487fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2488fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2489fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2490fcf5ef2aSThomas Huth 2491fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2492fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2493fcf5ef2aSThomas Huth 2494fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2495fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2496fcf5ef2aSThomas Huth TCGv_i64 val, \ 2497fcf5ef2aSThomas Huth TCGv addr) \ 2498fcf5ef2aSThomas Huth { \ 2499fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2500fcf5ef2aSThomas Huth } 2501fcf5ef2aSThomas Huth 2502fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2503fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2504fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2505fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2506fcf5ef2aSThomas Huth 2507fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2508fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2509fcf5ef2aSThomas Huth #endif 2510fcf5ef2aSThomas Huth 2511fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2512fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2513fcf5ef2aSThomas Huth { \ 2514fcf5ef2aSThomas Huth TCGv EA; \ 2515fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2516fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2517fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2518fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2519fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2520fcf5ef2aSThomas Huth } 2521fcf5ef2aSThomas Huth 2522fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2523fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2524fcf5ef2aSThomas Huth { \ 2525fcf5ef2aSThomas Huth TCGv EA; \ 2526fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2527fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2528fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2529fcf5ef2aSThomas Huth return; \ 2530fcf5ef2aSThomas Huth } \ 2531fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2532fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2533fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2534fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2535fcf5ef2aSThomas Huth else \ 2536fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2537fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2538fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2539fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2540fcf5ef2aSThomas Huth } 2541fcf5ef2aSThomas Huth 2542fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2543fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2544fcf5ef2aSThomas Huth { \ 2545fcf5ef2aSThomas Huth TCGv EA; \ 2546fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2547fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2548fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2549fcf5ef2aSThomas Huth return; \ 2550fcf5ef2aSThomas Huth } \ 2551fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2552fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2553fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2554fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2555fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2556fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2557fcf5ef2aSThomas Huth } 2558fcf5ef2aSThomas Huth 2559fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2560fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2561fcf5ef2aSThomas Huth { \ 2562fcf5ef2aSThomas Huth TCGv EA; \ 2563fcf5ef2aSThomas Huth chk; \ 2564fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2565fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2566fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2567fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2568fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2569fcf5ef2aSThomas Huth } 2570fcf5ef2aSThomas Huth 2571fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2572fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2573fcf5ef2aSThomas Huth 2574fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2575fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2576fcf5ef2aSThomas Huth 2577fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2578fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2579fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2580fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2581fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2582fcf5ef2aSThomas Huth 2583fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2584fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2585fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2586fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2587fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2588fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2589fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2590fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 259150728199SRoman Kapl 259250728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 259350728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 259450728199SRoman Kapl { \ 259550728199SRoman Kapl TCGv EA; \ 259650728199SRoman Kapl CHK_SV; \ 259750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 259850728199SRoman Kapl EA = tcg_temp_new(); \ 259950728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 260050728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 260150728199SRoman Kapl tcg_temp_free(EA); \ 260250728199SRoman Kapl } 260350728199SRoman Kapl 260450728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 260550728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 260650728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 260750728199SRoman Kapl #if defined(TARGET_PPC64) 260850728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 260950728199SRoman Kapl #endif 261050728199SRoman Kapl 2611fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2612fcf5ef2aSThomas Huth /* lwaux */ 2613fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2614fcf5ef2aSThomas Huth /* lwax */ 2615fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2616fcf5ef2aSThomas Huth /* ldux */ 2617fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2618fcf5ef2aSThomas Huth /* ldx */ 2619fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2620fcf5ef2aSThomas Huth 2621fcf5ef2aSThomas Huth /* CI load/store variants */ 2622fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2623fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2624fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2625fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2626fcf5ef2aSThomas Huth 2627fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2628fcf5ef2aSThomas Huth { 2629fcf5ef2aSThomas Huth TCGv EA; 2630fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2631fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2632fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2633fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2634fcf5ef2aSThomas Huth return; 2635fcf5ef2aSThomas Huth } 2636fcf5ef2aSThomas Huth } 2637fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2638fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2639fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2640fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2641fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2642fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2643fcf5ef2aSThomas Huth } else { 2644fcf5ef2aSThomas Huth /* ld - ldu */ 2645fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2646fcf5ef2aSThomas Huth } 2647efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 2648fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2649efe843d8SDavid Gibson } 2650fcf5ef2aSThomas Huth tcg_temp_free(EA); 2651fcf5ef2aSThomas Huth } 2652fcf5ef2aSThomas Huth 2653fcf5ef2aSThomas Huth /* lq */ 2654fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2655fcf5ef2aSThomas Huth { 2656fcf5ef2aSThomas Huth int ra, rd; 265794bf2658SRichard Henderson TCGv EA, hi, lo; 2658fcf5ef2aSThomas Huth 2659fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2660fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2661fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2662fcf5ef2aSThomas Huth 2663fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2664fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2665fcf5ef2aSThomas Huth return; 2666fcf5ef2aSThomas Huth } 2667fcf5ef2aSThomas Huth 2668fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2669fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2670fcf5ef2aSThomas Huth return; 2671fcf5ef2aSThomas Huth } 2672fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2673fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2674fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2675fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2676fcf5ef2aSThomas Huth return; 2677fcf5ef2aSThomas Huth } 2678fcf5ef2aSThomas Huth 2679fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2680fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2681fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2682fcf5ef2aSThomas Huth 268394bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 268494bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 268594bf2658SRichard Henderson hi = cpu_gpr[rd]; 268694bf2658SRichard Henderson 268794bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2688f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 268994bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 269094bf2658SRichard Henderson if (ctx->le_mode) { 269194bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 269294bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2693fcf5ef2aSThomas Huth } else { 269494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 269594bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 269694bf2658SRichard Henderson } 269794bf2658SRichard Henderson tcg_temp_free_i32(oi); 269894bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2699f34ec0f6SRichard Henderson } else { 270094bf2658SRichard Henderson /* Restart with exclusive lock. */ 270194bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 270294bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2703f34ec0f6SRichard Henderson } 270494bf2658SRichard Henderson } else if (ctx->le_mode) { 270594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2706fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 270794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 270894bf2658SRichard Henderson } else { 270994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 271094bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 271194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2712fcf5ef2aSThomas Huth } 2713fcf5ef2aSThomas Huth tcg_temp_free(EA); 2714fcf5ef2aSThomas Huth } 2715fcf5ef2aSThomas Huth #endif 2716fcf5ef2aSThomas Huth 2717fcf5ef2aSThomas Huth /*** Integer store ***/ 2718fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2719fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2720fcf5ef2aSThomas Huth { \ 2721fcf5ef2aSThomas Huth TCGv EA; \ 2722fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2723fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2724fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2725fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2726fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2727fcf5ef2aSThomas Huth } 2728fcf5ef2aSThomas Huth 2729fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2730fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2731fcf5ef2aSThomas Huth { \ 2732fcf5ef2aSThomas Huth TCGv EA; \ 2733fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2734fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2735fcf5ef2aSThomas Huth return; \ 2736fcf5ef2aSThomas Huth } \ 2737fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2738fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2739fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2740fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2741fcf5ef2aSThomas Huth else \ 2742fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2743fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2744fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2745fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2746fcf5ef2aSThomas Huth } 2747fcf5ef2aSThomas Huth 2748fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2749fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2750fcf5ef2aSThomas Huth { \ 2751fcf5ef2aSThomas Huth TCGv EA; \ 2752fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2753fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2754fcf5ef2aSThomas Huth return; \ 2755fcf5ef2aSThomas Huth } \ 2756fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2757fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2758fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2759fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2760fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2761fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2762fcf5ef2aSThomas Huth } 2763fcf5ef2aSThomas Huth 2764fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2765fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2766fcf5ef2aSThomas Huth { \ 2767fcf5ef2aSThomas Huth TCGv EA; \ 2768fcf5ef2aSThomas Huth chk; \ 2769fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2770fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2771fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2772fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2773fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2774fcf5ef2aSThomas Huth } 2775fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2776fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2777fcf5ef2aSThomas Huth 2778fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2779fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2780fcf5ef2aSThomas Huth 2781fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2782fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2783fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2784fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2785fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2786fcf5ef2aSThomas Huth 2787fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2788fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2789fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2790fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2791fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2792fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 279350728199SRoman Kapl 279450728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 279550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 279650728199SRoman Kapl { \ 279750728199SRoman Kapl TCGv EA; \ 279850728199SRoman Kapl CHK_SV; \ 279950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 280050728199SRoman Kapl EA = tcg_temp_new(); \ 280150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 280250728199SRoman Kapl tcg_gen_qemu_st_tl( \ 280350728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 280450728199SRoman Kapl tcg_temp_free(EA); \ 280550728199SRoman Kapl } 280650728199SRoman Kapl 280750728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 280850728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 280950728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 281050728199SRoman Kapl #if defined(TARGET_PPC64) 281150728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 281250728199SRoman Kapl #endif 281350728199SRoman Kapl 2814fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2815fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2816fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2817fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2818fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2819fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2820fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2821fcf5ef2aSThomas Huth 2822fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2823fcf5ef2aSThomas Huth { 2824fcf5ef2aSThomas Huth int rs; 2825fcf5ef2aSThomas Huth TCGv EA; 2826fcf5ef2aSThomas Huth 2827fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2828fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2829fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2830fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2831f89ced5fSRichard Henderson TCGv hi, lo; 2832fcf5ef2aSThomas Huth 2833fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2834fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2835fcf5ef2aSThomas Huth } 2836fcf5ef2aSThomas Huth 2837fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2838fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2839fcf5ef2aSThomas Huth return; 2840fcf5ef2aSThomas Huth } 2841fcf5ef2aSThomas Huth 2842fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2843fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2844fcf5ef2aSThomas Huth return; 2845fcf5ef2aSThomas Huth } 2846fcf5ef2aSThomas Huth 2847fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2848fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2849fcf5ef2aSThomas Huth return; 2850fcf5ef2aSThomas Huth } 2851fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2852fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2853fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2854fcf5ef2aSThomas Huth 2855f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 2856f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 2857f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 2858f89ced5fSRichard Henderson 2859f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2860f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 2861f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 2862f89ced5fSRichard Henderson if (ctx->le_mode) { 2863f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2864f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2865fcf5ef2aSThomas Huth } else { 2866f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2867f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2868f89ced5fSRichard Henderson } 2869f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 2870f34ec0f6SRichard Henderson } else { 2871f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 2872f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 2873f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2874f34ec0f6SRichard Henderson } 2875f89ced5fSRichard Henderson } else if (ctx->le_mode) { 2876f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2877fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2878f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2879f89ced5fSRichard Henderson } else { 2880f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2881f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 2882f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2883fcf5ef2aSThomas Huth } 2884fcf5ef2aSThomas Huth tcg_temp_free(EA); 2885fcf5ef2aSThomas Huth } else { 2886fcf5ef2aSThomas Huth /* std / stdu */ 2887fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2888fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2889fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2890fcf5ef2aSThomas Huth return; 2891fcf5ef2aSThomas Huth } 2892fcf5ef2aSThomas Huth } 2893fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2894fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2895fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2896fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2897efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 2898fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2899efe843d8SDavid Gibson } 2900fcf5ef2aSThomas Huth tcg_temp_free(EA); 2901fcf5ef2aSThomas Huth } 2902fcf5ef2aSThomas Huth } 2903fcf5ef2aSThomas Huth #endif 2904fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2905fcf5ef2aSThomas Huth 2906fcf5ef2aSThomas Huth /* lhbrx */ 2907fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2908fcf5ef2aSThomas Huth 2909fcf5ef2aSThomas Huth /* lwbrx */ 2910fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2911fcf5ef2aSThomas Huth 2912fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2913fcf5ef2aSThomas Huth /* ldbrx */ 2914fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2915fcf5ef2aSThomas Huth /* stdbrx */ 2916fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2917fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2918fcf5ef2aSThomas Huth 2919fcf5ef2aSThomas Huth /* sthbrx */ 2920fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2921fcf5ef2aSThomas Huth /* stwbrx */ 2922fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2923fcf5ef2aSThomas Huth 2924fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2925fcf5ef2aSThomas Huth 2926fcf5ef2aSThomas Huth /* lmw */ 2927fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2928fcf5ef2aSThomas Huth { 2929fcf5ef2aSThomas Huth TCGv t0; 2930fcf5ef2aSThomas Huth TCGv_i32 t1; 2931fcf5ef2aSThomas Huth 2932fcf5ef2aSThomas Huth if (ctx->le_mode) { 2933fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2934fcf5ef2aSThomas Huth return; 2935fcf5ef2aSThomas Huth } 2936fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2937fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2938fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2939fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2940fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2941fcf5ef2aSThomas Huth tcg_temp_free(t0); 2942fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2943fcf5ef2aSThomas Huth } 2944fcf5ef2aSThomas Huth 2945fcf5ef2aSThomas Huth /* stmw */ 2946fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2947fcf5ef2aSThomas Huth { 2948fcf5ef2aSThomas Huth TCGv t0; 2949fcf5ef2aSThomas Huth TCGv_i32 t1; 2950fcf5ef2aSThomas Huth 2951fcf5ef2aSThomas Huth if (ctx->le_mode) { 2952fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2953fcf5ef2aSThomas Huth return; 2954fcf5ef2aSThomas Huth } 2955fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2956fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2957fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2958fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2959fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2960fcf5ef2aSThomas Huth tcg_temp_free(t0); 2961fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2962fcf5ef2aSThomas Huth } 2963fcf5ef2aSThomas Huth 2964fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2965fcf5ef2aSThomas Huth 2966fcf5ef2aSThomas Huth /* lswi */ 2967efe843d8SDavid Gibson /* 2968efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 2969efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 2970efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 2971efe843d8SDavid Gibson * spec... 2972fcf5ef2aSThomas Huth */ 2973fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2974fcf5ef2aSThomas Huth { 2975fcf5ef2aSThomas Huth TCGv t0; 2976fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2977fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2978fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2979fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2980fcf5ef2aSThomas Huth int nr; 2981fcf5ef2aSThomas Huth 2982fcf5ef2aSThomas Huth if (ctx->le_mode) { 2983fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2984fcf5ef2aSThomas Huth return; 2985fcf5ef2aSThomas Huth } 2986efe843d8SDavid Gibson if (nb == 0) { 2987fcf5ef2aSThomas Huth nb = 32; 2988efe843d8SDavid Gibson } 2989f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 2990fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2991fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2992fcf5ef2aSThomas Huth return; 2993fcf5ef2aSThomas Huth } 2994fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2995fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2996fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2997fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2998fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 2999fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3000fcf5ef2aSThomas Huth tcg_temp_free(t0); 3001fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3002fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3003fcf5ef2aSThomas Huth } 3004fcf5ef2aSThomas Huth 3005fcf5ef2aSThomas Huth /* lswx */ 3006fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3007fcf5ef2aSThomas Huth { 3008fcf5ef2aSThomas Huth TCGv t0; 3009fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3010fcf5ef2aSThomas Huth 3011fcf5ef2aSThomas Huth if (ctx->le_mode) { 3012fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3013fcf5ef2aSThomas Huth return; 3014fcf5ef2aSThomas Huth } 3015fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3016fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3017fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3018fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3019fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3020fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3021fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3022fcf5ef2aSThomas Huth tcg_temp_free(t0); 3023fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3024fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3025fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3026fcf5ef2aSThomas Huth } 3027fcf5ef2aSThomas Huth 3028fcf5ef2aSThomas Huth /* stswi */ 3029fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3030fcf5ef2aSThomas Huth { 3031fcf5ef2aSThomas Huth TCGv t0; 3032fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3033fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3034fcf5ef2aSThomas Huth 3035fcf5ef2aSThomas Huth if (ctx->le_mode) { 3036fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3037fcf5ef2aSThomas Huth return; 3038fcf5ef2aSThomas Huth } 3039fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3040fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3041fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3042efe843d8SDavid Gibson if (nb == 0) { 3043fcf5ef2aSThomas Huth nb = 32; 3044efe843d8SDavid Gibson } 3045fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3046fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3047fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3048fcf5ef2aSThomas Huth tcg_temp_free(t0); 3049fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3050fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3051fcf5ef2aSThomas Huth } 3052fcf5ef2aSThomas Huth 3053fcf5ef2aSThomas Huth /* stswx */ 3054fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3055fcf5ef2aSThomas Huth { 3056fcf5ef2aSThomas Huth TCGv t0; 3057fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3058fcf5ef2aSThomas Huth 3059fcf5ef2aSThomas Huth if (ctx->le_mode) { 3060fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3061fcf5ef2aSThomas Huth return; 3062fcf5ef2aSThomas Huth } 3063fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3064fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3065fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3066fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3067fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3068fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3069fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3070fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3071fcf5ef2aSThomas Huth tcg_temp_free(t0); 3072fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3073fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3074fcf5ef2aSThomas Huth } 3075fcf5ef2aSThomas Huth 3076fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3077fcf5ef2aSThomas Huth /* eieio */ 3078fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3079fcf5ef2aSThomas Huth { 3080c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3081c8fd8373SCédric Le Goater 3082c8fd8373SCédric Le Goater /* 3083c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3084c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3085c8fd8373SCédric Le Goater */ 3086c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3087c8fd8373SCédric Le Goater /* 3088c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3089c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3090c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3091c8fd8373SCédric Le Goater * complain to the user. 3092c8fd8373SCédric Le Goater */ 3093c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3094c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3095c8fd8373SCédric Le Goater TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3096c8fd8373SCédric Le Goater } else { 3097c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3098c8fd8373SCédric Le Goater } 3099c8fd8373SCédric Le Goater } 3100c8fd8373SCédric Le Goater 3101c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3102fcf5ef2aSThomas Huth } 3103fcf5ef2aSThomas Huth 3104fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3105fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3106fcf5ef2aSThomas Huth { 3107fcf5ef2aSThomas Huth TCGv_i32 t; 3108fcf5ef2aSThomas Huth TCGLabel *l; 3109fcf5ef2aSThomas Huth 3110fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3111fcf5ef2aSThomas Huth return; 3112fcf5ef2aSThomas Huth } 3113fcf5ef2aSThomas Huth l = gen_new_label(); 3114fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3115fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3116fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3117fcf5ef2aSThomas Huth if (global) { 3118fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3119fcf5ef2aSThomas Huth } else { 3120fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3121fcf5ef2aSThomas Huth } 3122fcf5ef2aSThomas Huth gen_set_label(l); 3123fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3124fcf5ef2aSThomas Huth } 3125fcf5ef2aSThomas Huth #else 3126fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3127fcf5ef2aSThomas Huth #endif 3128fcf5ef2aSThomas Huth 3129fcf5ef2aSThomas Huth /* isync */ 3130fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3131fcf5ef2aSThomas Huth { 3132fcf5ef2aSThomas Huth /* 3133fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3134fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3135fcf5ef2aSThomas Huth */ 3136fcf5ef2aSThomas Huth if (!ctx->pr) { 3137fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3138fcf5ef2aSThomas Huth } 31394771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3140fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3141fcf5ef2aSThomas Huth } 3142fcf5ef2aSThomas Huth 3143fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3144fcf5ef2aSThomas Huth 31452a4e6c1bSRichard Henderson static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) 31462a4e6c1bSRichard Henderson { 31472a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 31482a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 31492a4e6c1bSRichard Henderson 31502a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 31512a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 31522a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 31532a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 31542a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 31552a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 31562a4e6c1bSRichard Henderson tcg_temp_free(t0); 31572a4e6c1bSRichard Henderson } 31582a4e6c1bSRichard Henderson 3159fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3160fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3161fcf5ef2aSThomas Huth { \ 31622a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3163fcf5ef2aSThomas Huth } 3164fcf5ef2aSThomas Huth 3165fcf5ef2aSThomas Huth /* lwarx */ 3166fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3167fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3168fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3169fcf5ef2aSThomas Huth 317020923c1dSRichard Henderson static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, 317120923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 317220923c1dSRichard Henderson { 317320923c1dSRichard Henderson TCGv t = tcg_temp_new(); 317420923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 317520923c1dSRichard Henderson TCGv u = tcg_temp_new(); 317620923c1dSRichard Henderson 317720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 317820923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 317920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 318020923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 318120923c1dSRichard Henderson 318220923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 318320923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 318420923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 318520923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 318620923c1dSRichard Henderson 318720923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 318820923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 318920923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 319020923c1dSRichard Henderson 319120923c1dSRichard Henderson tcg_temp_free(t); 319220923c1dSRichard Henderson tcg_temp_free(t2); 319320923c1dSRichard Henderson tcg_temp_free(u); 319420923c1dSRichard Henderson } 319520923c1dSRichard Henderson 319620ba8504SRichard Henderson static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) 319720ba8504SRichard Henderson { 319820ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 319920ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 320020923c1dSRichard Henderson int rt = rD(ctx->opcode); 320120923c1dSRichard Henderson bool need_serial; 320220ba8504SRichard Henderson TCGv src, dst; 320320ba8504SRichard Henderson 320420ba8504SRichard Henderson gen_addr_register(ctx, EA); 320520923c1dSRichard Henderson dst = cpu_gpr[rt]; 320620923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 320720ba8504SRichard Henderson 320820923c1dSRichard Henderson need_serial = false; 320920ba8504SRichard Henderson memop |= MO_ALIGN; 321020ba8504SRichard Henderson switch (gpr_FC) { 321120ba8504SRichard Henderson case 0: /* Fetch and add */ 321220ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 321320ba8504SRichard Henderson break; 321420ba8504SRichard Henderson case 1: /* Fetch and xor */ 321520ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 321620ba8504SRichard Henderson break; 321720ba8504SRichard Henderson case 2: /* Fetch and or */ 321820ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 321920ba8504SRichard Henderson break; 322020ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 322120ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 322220ba8504SRichard Henderson break; 3223b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3224b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3225b8ce0f86SRichard Henderson break; 3226b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3227b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3228b8ce0f86SRichard Henderson break; 3229b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3230b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3231b8ce0f86SRichard Henderson break; 3232b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3233b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3234b8ce0f86SRichard Henderson break; 323520ba8504SRichard Henderson case 8: /* Swap */ 323620ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 323720ba8504SRichard Henderson break; 323820923c1dSRichard Henderson 323920923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 324020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 324120923c1dSRichard Henderson need_serial = true; 324220923c1dSRichard Henderson } else { 324320923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 324420923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 324520923c1dSRichard Henderson 324620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 324720923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 324820923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 324920923c1dSRichard Henderson } else { 325020923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 325120923c1dSRichard Henderson } 325220923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 325320923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 325420923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 325520923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 325620923c1dSRichard Henderson 325720923c1dSRichard Henderson tcg_temp_free(t0); 325820923c1dSRichard Henderson tcg_temp_free(t1); 325920923c1dSRichard Henderson } 326020ba8504SRichard Henderson break; 326120923c1dSRichard Henderson 326220923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 326320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 326420923c1dSRichard Henderson need_serial = true; 326520923c1dSRichard Henderson } else { 326620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 326720923c1dSRichard Henderson } 326820923c1dSRichard Henderson break; 326920923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 327020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 327120923c1dSRichard Henderson need_serial = true; 327220923c1dSRichard Henderson } else { 327320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 327420923c1dSRichard Henderson } 327520923c1dSRichard Henderson break; 327620923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 327720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 327820923c1dSRichard Henderson need_serial = true; 327920923c1dSRichard Henderson } else { 328020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 328120923c1dSRichard Henderson } 328220923c1dSRichard Henderson break; 328320923c1dSRichard Henderson 328420ba8504SRichard Henderson default: 328520ba8504SRichard Henderson /* invoke data storage error handler */ 328620ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 328720ba8504SRichard Henderson } 328820ba8504SRichard Henderson tcg_temp_free(EA); 328920923c1dSRichard Henderson 329020923c1dSRichard Henderson if (need_serial) { 329120923c1dSRichard Henderson /* Restart with exclusive lock. */ 329220923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 329320923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 329420923c1dSRichard Henderson } 3295a68a6146SBalamuruhan S } 3296a68a6146SBalamuruhan S 329720ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 329820ba8504SRichard Henderson { 329920ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 330020ba8504SRichard Henderson } 330120ba8504SRichard Henderson 330220ba8504SRichard Henderson #ifdef TARGET_PPC64 330320ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 330420ba8504SRichard Henderson { 330520ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 330620ba8504SRichard Henderson } 3307a68a6146SBalamuruhan S #endif 3308a68a6146SBalamuruhan S 33099deb041cSRichard Henderson static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) 33109deb041cSRichard Henderson { 33119deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 33129deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 33139deb041cSRichard Henderson TCGv src, discard; 33149deb041cSRichard Henderson 33159deb041cSRichard Henderson gen_addr_register(ctx, EA); 33169deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 33179deb041cSRichard Henderson discard = tcg_temp_new(); 33189deb041cSRichard Henderson 33199deb041cSRichard Henderson memop |= MO_ALIGN; 33209deb041cSRichard Henderson switch (gpr_FC) { 33219deb041cSRichard Henderson case 0: /* add and Store */ 33229deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33239deb041cSRichard Henderson break; 33249deb041cSRichard Henderson case 1: /* xor and Store */ 33259deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33269deb041cSRichard Henderson break; 33279deb041cSRichard Henderson case 2: /* Or and Store */ 33289deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33299deb041cSRichard Henderson break; 33309deb041cSRichard Henderson case 3: /* 'and' and Store */ 33319deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33329deb041cSRichard Henderson break; 33339deb041cSRichard Henderson case 4: /* Store max unsigned */ 3334b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3335b8ce0f86SRichard Henderson break; 33369deb041cSRichard Henderson case 5: /* Store max signed */ 3337b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3338b8ce0f86SRichard Henderson break; 33399deb041cSRichard Henderson case 6: /* Store min unsigned */ 3340b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3341b8ce0f86SRichard Henderson break; 33429deb041cSRichard Henderson case 7: /* Store min signed */ 3343b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3344b8ce0f86SRichard Henderson break; 33459deb041cSRichard Henderson case 24: /* Store twin */ 33467fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 33477fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 33487fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 33497fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 33507fbc2b20SRichard Henderson } else { 33517fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 33527fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 33537fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 33547fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 33557fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 33567fbc2b20SRichard Henderson 33577fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 33587fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 33597fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 33607fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 33617fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 33627fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 33637fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 33647fbc2b20SRichard Henderson 33657fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 33667fbc2b20SRichard Henderson tcg_temp_free(s2); 33677fbc2b20SRichard Henderson tcg_temp_free(s); 33687fbc2b20SRichard Henderson tcg_temp_free(t2); 33697fbc2b20SRichard Henderson tcg_temp_free(t); 33707fbc2b20SRichard Henderson } 33719deb041cSRichard Henderson break; 33729deb041cSRichard Henderson default: 33739deb041cSRichard Henderson /* invoke data storage error handler */ 33749deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 33759deb041cSRichard Henderson } 33769deb041cSRichard Henderson tcg_temp_free(discard); 33779deb041cSRichard Henderson tcg_temp_free(EA); 3378a3401188SBalamuruhan S } 3379a3401188SBalamuruhan S 33809deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 33819deb041cSRichard Henderson { 33829deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 33839deb041cSRichard Henderson } 33849deb041cSRichard Henderson 33859deb041cSRichard Henderson #ifdef TARGET_PPC64 33869deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 33879deb041cSRichard Henderson { 33889deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 33899deb041cSRichard Henderson } 3390a3401188SBalamuruhan S #endif 3391a3401188SBalamuruhan S 3392d8b86898SRichard Henderson static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) 3393fcf5ef2aSThomas Huth { 3394253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3395253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3396d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3397d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3398fcf5ef2aSThomas Huth 3399d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3400d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3401d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3402d8b86898SRichard Henderson tcg_temp_free(t0); 3403253ce7b2SNikunj A Dadhania 3404253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3405253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3406253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3407253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3408253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3409253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3410253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3411253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3412253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3413253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3414253ce7b2SNikunj A Dadhania 3415fcf5ef2aSThomas Huth gen_set_label(l1); 34164771df23SNikunj A Dadhania 3417efe843d8SDavid Gibson /* 3418efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3419efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3420efe843d8SDavid Gibson */ 34214771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3422253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3423253ce7b2SNikunj A Dadhania 3424253ce7b2SNikunj A Dadhania gen_set_label(l2); 3425fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3426fcf5ef2aSThomas Huth } 3427fcf5ef2aSThomas Huth 3428fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3429fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3430fcf5ef2aSThomas Huth { \ 3431d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3432fcf5ef2aSThomas Huth } 3433fcf5ef2aSThomas Huth 3434fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3435fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3436fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3437fcf5ef2aSThomas Huth 3438fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3439fcf5ef2aSThomas Huth /* ldarx */ 3440fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3441fcf5ef2aSThomas Huth /* stdcx. */ 3442fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3443fcf5ef2aSThomas Huth 3444fcf5ef2aSThomas Huth /* lqarx */ 3445fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3446fcf5ef2aSThomas Huth { 3447fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 344894bf2658SRichard Henderson TCGv EA, hi, lo; 3449fcf5ef2aSThomas Huth 3450fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3451fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3452fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3453fcf5ef2aSThomas Huth return; 3454fcf5ef2aSThomas Huth } 3455fcf5ef2aSThomas Huth 3456fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 345794bf2658SRichard Henderson EA = tcg_temp_new(); 3458fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 345994bf2658SRichard Henderson 346094bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 346194bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 346294bf2658SRichard Henderson hi = cpu_gpr[rd]; 346394bf2658SRichard Henderson 346494bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3465f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 346694bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 346794bf2658SRichard Henderson if (ctx->le_mode) { 346894bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 346994bf2658SRichard Henderson ctx->mem_idx)); 347094bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3471fcf5ef2aSThomas Huth } else { 347294bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 347394bf2658SRichard Henderson ctx->mem_idx)); 347494bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3475fcf5ef2aSThomas Huth } 347694bf2658SRichard Henderson tcg_temp_free_i32(oi); 347794bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3478f34ec0f6SRichard Henderson } else { 347994bf2658SRichard Henderson /* Restart with exclusive lock. */ 348094bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 348194bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 348294bf2658SRichard Henderson tcg_temp_free(EA); 348394bf2658SRichard Henderson return; 3484f34ec0f6SRichard Henderson } 348594bf2658SRichard Henderson } else if (ctx->le_mode) { 348694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3487fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3488fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 348994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 349094bf2658SRichard Henderson } else { 349194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 349294bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 349394bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 349494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 349594bf2658SRichard Henderson } 3496fcf5ef2aSThomas Huth tcg_temp_free(EA); 349794bf2658SRichard Henderson 349894bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 349994bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3500fcf5ef2aSThomas Huth } 3501fcf5ef2aSThomas Huth 3502fcf5ef2aSThomas Huth /* stqcx. */ 3503fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3504fcf5ef2aSThomas Huth { 35054a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 35064a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3507fcf5ef2aSThomas Huth 35084a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3509fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3510fcf5ef2aSThomas Huth return; 3511fcf5ef2aSThomas Huth } 35124a9b3c5dSRichard Henderson 3513fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 35144a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3515fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3516fcf5ef2aSThomas Huth 35174a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 35184a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 35194a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3520fcf5ef2aSThomas Huth 35214a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3522f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 35234a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 35244a9b3c5dSRichard Henderson if (ctx->le_mode) { 3525f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3526f34ec0f6SRichard Henderson EA, lo, hi, oi); 3527fcf5ef2aSThomas Huth } else { 3528f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3529f34ec0f6SRichard Henderson EA, lo, hi, oi); 3530fcf5ef2aSThomas Huth } 3531f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 3532f34ec0f6SRichard Henderson } else { 35334a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 35344a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 35354a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3536f34ec0f6SRichard Henderson } 3537fcf5ef2aSThomas Huth tcg_temp_free(EA); 35384a9b3c5dSRichard Henderson } else { 35394a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 35404a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 35414a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 35424a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 3543fcf5ef2aSThomas Huth 35444a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 35454a9b3c5dSRichard Henderson tcg_temp_free(EA); 35464a9b3c5dSRichard Henderson 35474a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 35484a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35494a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 35504a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 35514a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35524a9b3c5dSRichard Henderson 35534a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35544a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 35554a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35564a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 35574a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 35584a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35594a9b3c5dSRichard Henderson 35604a9b3c5dSRichard Henderson /* Success */ 35614a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 35624a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35634a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 35644a9b3c5dSRichard Henderson 35654a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35664a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 35674a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 35684a9b3c5dSRichard Henderson 35694a9b3c5dSRichard Henderson gen_set_label(lab_fail); 35704a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35714a9b3c5dSRichard Henderson 35724a9b3c5dSRichard Henderson gen_set_label(lab_over); 35734a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 35744a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 35754a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 35764a9b3c5dSRichard Henderson } 35774a9b3c5dSRichard Henderson } 3578fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3579fcf5ef2aSThomas Huth 3580fcf5ef2aSThomas Huth /* sync */ 3581fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3582fcf5ef2aSThomas Huth { 3583fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3584fcf5ef2aSThomas Huth 3585fcf5ef2aSThomas Huth /* 3586fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3587fcf5ef2aSThomas Huth * 3588fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3589fcf5ef2aSThomas Huth * 3590fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3591fcf5ef2aSThomas Huth * check MSR_PR as well. 3592fcf5ef2aSThomas Huth */ 3593fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3594fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3595fcf5ef2aSThomas Huth } 35964771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3597fcf5ef2aSThomas Huth } 3598fcf5ef2aSThomas Huth 3599fcf5ef2aSThomas Huth /* wait */ 3600fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3601fcf5ef2aSThomas Huth { 3602fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3603fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3604fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3605fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3606fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3607b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3608fcf5ef2aSThomas Huth } 3609fcf5ef2aSThomas Huth 3610fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3611fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3612fcf5ef2aSThomas Huth { 3613fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3614fcf5ef2aSThomas Huth GEN_PRIV; 3615fcf5ef2aSThomas Huth #else 3616fcf5ef2aSThomas Huth TCGv_i32 t; 3617fcf5ef2aSThomas Huth 3618fcf5ef2aSThomas Huth CHK_HV; 3619fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3620fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3621fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3622154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3623154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3624fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3625fcf5ef2aSThomas Huth } 3626fcf5ef2aSThomas Huth 3627fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3628fcf5ef2aSThomas Huth { 3629fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3630fcf5ef2aSThomas Huth GEN_PRIV; 3631fcf5ef2aSThomas Huth #else 3632fcf5ef2aSThomas Huth TCGv_i32 t; 3633fcf5ef2aSThomas Huth 3634fcf5ef2aSThomas Huth CHK_HV; 3635fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3636fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3637fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3638154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3639154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3640fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3641fcf5ef2aSThomas Huth } 3642fcf5ef2aSThomas Huth 3643cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3644cdee0e72SNikunj A Dadhania { 364521c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 364621c0d66aSBenjamin Herrenschmidt GEN_PRIV; 364721c0d66aSBenjamin Herrenschmidt #else 364821c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 364921c0d66aSBenjamin Herrenschmidt 365021c0d66aSBenjamin Herrenschmidt CHK_HV; 365121c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 365221c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 365321c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 365421c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 365521c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 365621c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 3657cdee0e72SNikunj A Dadhania } 3658cdee0e72SNikunj A Dadhania 3659fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3660fcf5ef2aSThomas Huth { 3661fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3662fcf5ef2aSThomas Huth GEN_PRIV; 3663fcf5ef2aSThomas Huth #else 3664fcf5ef2aSThomas Huth TCGv_i32 t; 3665fcf5ef2aSThomas Huth 3666fcf5ef2aSThomas Huth CHK_HV; 3667fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3668fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3669fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3670154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3671154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3672fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3673fcf5ef2aSThomas Huth } 3674fcf5ef2aSThomas Huth 3675fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3676fcf5ef2aSThomas Huth { 3677fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3678fcf5ef2aSThomas Huth GEN_PRIV; 3679fcf5ef2aSThomas Huth #else 3680fcf5ef2aSThomas Huth TCGv_i32 t; 3681fcf5ef2aSThomas Huth 3682fcf5ef2aSThomas Huth CHK_HV; 3683fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3684fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3685fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3686154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3687154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3688fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3689fcf5ef2aSThomas Huth } 3690fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3691fcf5ef2aSThomas Huth 3692fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3693fcf5ef2aSThomas Huth { 3694fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3695efe843d8SDavid Gibson if (ctx->has_cfar) { 3696fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3697efe843d8SDavid Gibson } 3698fcf5ef2aSThomas Huth #endif 3699fcf5ef2aSThomas Huth } 3700fcf5ef2aSThomas Huth 3701fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3702fcf5ef2aSThomas Huth { 3703fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3704fcf5ef2aSThomas Huth return false; 3705fcf5ef2aSThomas Huth } 3706fcf5ef2aSThomas Huth 3707fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3708b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3709fcf5ef2aSThomas Huth #else 3710fcf5ef2aSThomas Huth return true; 3711fcf5ef2aSThomas Huth #endif 3712fcf5ef2aSThomas Huth } 3713fcf5ef2aSThomas Huth 37140e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 37150e3bf489SRoman Kapl { 37160e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 37170e3bf489SRoman Kapl if (unlikely(sse)) { 37180e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 37190e3bf489SRoman Kapl gen_debug_exception(ctx); 37200e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3721e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 37220e3bf489SRoman Kapl gen_exception(ctx, excp); 37230e3bf489SRoman Kapl } 37240e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 37250e3bf489SRoman Kapl } else { 37260e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 37270e3bf489SRoman Kapl } 37280e3bf489SRoman Kapl } 37290e3bf489SRoman Kapl 3730fcf5ef2aSThomas Huth /*** Branch ***/ 3731c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3732fcf5ef2aSThomas Huth { 3733fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3734fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3735fcf5ef2aSThomas Huth } 3736fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3737fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3738fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 373907ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 3740fcf5ef2aSThomas Huth } else { 3741fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 37420e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3743fcf5ef2aSThomas Huth } 3744fcf5ef2aSThomas Huth } 3745fcf5ef2aSThomas Huth 3746fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3747fcf5ef2aSThomas Huth { 3748fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3749fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3750fcf5ef2aSThomas Huth } 3751fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3752fcf5ef2aSThomas Huth } 3753fcf5ef2aSThomas Huth 3754fcf5ef2aSThomas Huth /* b ba bl bla */ 3755fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3756fcf5ef2aSThomas Huth { 3757fcf5ef2aSThomas Huth target_ulong li, target; 3758fcf5ef2aSThomas Huth 3759fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3760fcf5ef2aSThomas Huth /* sign extend LI */ 3761fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3762fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3763fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3764b6bac4bcSEmilio G. Cota target = ctx->base.pc_next + li - 4; 3765fcf5ef2aSThomas Huth } else { 3766fcf5ef2aSThomas Huth target = li; 3767fcf5ef2aSThomas Huth } 3768fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3769b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3770fcf5ef2aSThomas Huth } 3771b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3772fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3773fcf5ef2aSThomas Huth } 3774fcf5ef2aSThomas Huth 3775fcf5ef2aSThomas Huth #define BCOND_IM 0 3776fcf5ef2aSThomas Huth #define BCOND_LR 1 3777fcf5ef2aSThomas Huth #define BCOND_CTR 2 3778fcf5ef2aSThomas Huth #define BCOND_TAR 3 3779fcf5ef2aSThomas Huth 3780c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 3781fcf5ef2aSThomas Huth { 3782fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3783fcf5ef2aSThomas Huth TCGLabel *l1; 3784fcf5ef2aSThomas Huth TCGv target; 3785fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 37860e3bf489SRoman Kapl 3787fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3788fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3789efe843d8SDavid Gibson if (type == BCOND_CTR) { 3790fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3791efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 3792fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3793efe843d8SDavid Gibson } else { 3794fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3795efe843d8SDavid Gibson } 3796fcf5ef2aSThomas Huth } else { 3797f764718dSRichard Henderson target = NULL; 3798fcf5ef2aSThomas Huth } 3799efe843d8SDavid Gibson if (LK(ctx->opcode)) { 3800b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3801efe843d8SDavid Gibson } 3802fcf5ef2aSThomas Huth l1 = gen_new_label(); 3803fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3804fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3805fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3806fa200c95SGreg Kurz 3807fa200c95SGreg Kurz if (type == BCOND_CTR) { 3808fa200c95SGreg Kurz /* 3809fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 3810fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 3811fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 381215d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 381315d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 381415d68c5eSGreg Kurz * it basically useless and thus never used in real code. 381515d68c5eSGreg Kurz * 381615d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 381715d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 381815d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 381915d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 382015d68c5eSGreg Kurz * doing anything else harmful. 3821fa200c95SGreg Kurz */ 3822d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 3823fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 38249acc95cdSGreg Kurz tcg_temp_free(temp); 38259acc95cdSGreg Kurz tcg_temp_free(target); 3826fcf5ef2aSThomas Huth return; 3827fcf5ef2aSThomas Huth } 3828fa200c95SGreg Kurz 3829fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 3830fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 3831fa200c95SGreg Kurz } else { 3832fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 3833fa200c95SGreg Kurz } 3834fa200c95SGreg Kurz if (bo & 0x2) { 3835fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3836fa200c95SGreg Kurz } else { 3837fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3838fa200c95SGreg Kurz } 3839fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3840fa200c95SGreg Kurz } else { 3841fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3842fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3843fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3844fcf5ef2aSThomas Huth } else { 3845fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3846fcf5ef2aSThomas Huth } 3847fcf5ef2aSThomas Huth if (bo & 0x2) { 3848fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3849fcf5ef2aSThomas Huth } else { 3850fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3851fcf5ef2aSThomas Huth } 3852fa200c95SGreg Kurz } 3853fcf5ef2aSThomas Huth tcg_temp_free(temp); 3854fcf5ef2aSThomas Huth } 3855fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3856fcf5ef2aSThomas Huth /* Test CR */ 3857fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3858fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3859fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3860fcf5ef2aSThomas Huth 3861fcf5ef2aSThomas Huth if (bo & 0x8) { 3862fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3863fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3864fcf5ef2aSThomas Huth } else { 3865fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3866fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3867fcf5ef2aSThomas Huth } 3868fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3869fcf5ef2aSThomas Huth } 3870b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3871fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3872fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3873fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3874b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3875fcf5ef2aSThomas Huth } else { 3876fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3877fcf5ef2aSThomas Huth } 3878fcf5ef2aSThomas Huth } else { 3879fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3880fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3881fcf5ef2aSThomas Huth } else { 3882fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3883fcf5ef2aSThomas Huth } 38840e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3885c4a2e3a9SRichard Henderson tcg_temp_free(target); 3886c4a2e3a9SRichard Henderson } 3887fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 38880e3bf489SRoman Kapl /* fallthrough case */ 3889fcf5ef2aSThomas Huth gen_set_label(l1); 3890b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 3891fcf5ef2aSThomas Huth } 3892fcf5ef2aSThomas Huth } 3893fcf5ef2aSThomas Huth 3894fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3895fcf5ef2aSThomas Huth { 3896fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3897fcf5ef2aSThomas Huth } 3898fcf5ef2aSThomas Huth 3899fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3900fcf5ef2aSThomas Huth { 3901fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3902fcf5ef2aSThomas Huth } 3903fcf5ef2aSThomas Huth 3904fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3905fcf5ef2aSThomas Huth { 3906fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3907fcf5ef2aSThomas Huth } 3908fcf5ef2aSThomas Huth 3909fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3910fcf5ef2aSThomas Huth { 3911fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3912fcf5ef2aSThomas Huth } 3913fcf5ef2aSThomas Huth 3914fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3915fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3916fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3917fcf5ef2aSThomas Huth { \ 3918fcf5ef2aSThomas Huth uint8_t bitmask; \ 3919fcf5ef2aSThomas Huth int sh; \ 3920fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3921fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3922fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3923fcf5ef2aSThomas Huth if (sh > 0) \ 3924fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3925fcf5ef2aSThomas Huth else if (sh < 0) \ 3926fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3927fcf5ef2aSThomas Huth else \ 3928fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3929fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3930fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3931fcf5ef2aSThomas Huth if (sh > 0) \ 3932fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3933fcf5ef2aSThomas Huth else if (sh < 0) \ 3934fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3935fcf5ef2aSThomas Huth else \ 3936fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3937fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3938fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3939fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3940fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3941fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3942fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3943fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3944fcf5ef2aSThomas Huth } 3945fcf5ef2aSThomas Huth 3946fcf5ef2aSThomas Huth /* crand */ 3947fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3948fcf5ef2aSThomas Huth /* crandc */ 3949fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3950fcf5ef2aSThomas Huth /* creqv */ 3951fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3952fcf5ef2aSThomas Huth /* crnand */ 3953fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3954fcf5ef2aSThomas Huth /* crnor */ 3955fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3956fcf5ef2aSThomas Huth /* cror */ 3957fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3958fcf5ef2aSThomas Huth /* crorc */ 3959fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3960fcf5ef2aSThomas Huth /* crxor */ 3961fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3962fcf5ef2aSThomas Huth 3963fcf5ef2aSThomas Huth /* mcrf */ 3964fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3965fcf5ef2aSThomas Huth { 3966fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3967fcf5ef2aSThomas Huth } 3968fcf5ef2aSThomas Huth 3969fcf5ef2aSThomas Huth /*** System linkage ***/ 3970fcf5ef2aSThomas Huth 3971fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3972fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3973fcf5ef2aSThomas Huth { 3974fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3975fcf5ef2aSThomas Huth GEN_PRIV; 3976fcf5ef2aSThomas Huth #else 3977efe843d8SDavid Gibson /* 3978efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 3979fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3980fcf5ef2aSThomas Huth */ 3981d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 3982fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3983fcf5ef2aSThomas Huth return; 3984fcf5ef2aSThomas Huth } 3985fcf5ef2aSThomas Huth /* Restore CPU state */ 3986fcf5ef2aSThomas Huth CHK_SV; 3987a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3988a59d628fSMaria Klimushenkova gen_io_start(); 3989a59d628fSMaria Klimushenkova } 3990b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3991fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3992fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3993a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3994a59d628fSMaria Klimushenkova gen_io_end(); 3995a59d628fSMaria Klimushenkova } 3996fcf5ef2aSThomas Huth #endif 3997fcf5ef2aSThomas Huth } 3998fcf5ef2aSThomas Huth 3999fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4000fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4001fcf5ef2aSThomas Huth { 4002fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4003fcf5ef2aSThomas Huth GEN_PRIV; 4004fcf5ef2aSThomas Huth #else 4005fcf5ef2aSThomas Huth /* Restore CPU state */ 4006fcf5ef2aSThomas Huth CHK_SV; 4007a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4008a59d628fSMaria Klimushenkova gen_io_start(); 4009a59d628fSMaria Klimushenkova } 4010b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 4011fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 4012fcf5ef2aSThomas Huth gen_sync_exception(ctx); 4013a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4014a59d628fSMaria Klimushenkova gen_io_end(); 4015a59d628fSMaria Klimushenkova } 4016fcf5ef2aSThomas Huth #endif 4017fcf5ef2aSThomas Huth } 4018fcf5ef2aSThomas Huth 4019fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4020fcf5ef2aSThomas Huth { 4021fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4022fcf5ef2aSThomas Huth GEN_PRIV; 4023fcf5ef2aSThomas Huth #else 4024fcf5ef2aSThomas Huth /* Restore CPU state */ 4025fcf5ef2aSThomas Huth CHK_HV; 4026fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 4027fcf5ef2aSThomas Huth gen_sync_exception(ctx); 4028fcf5ef2aSThomas Huth #endif 4029fcf5ef2aSThomas Huth } 4030fcf5ef2aSThomas Huth #endif 4031fcf5ef2aSThomas Huth 4032fcf5ef2aSThomas Huth /* sc */ 4033fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4034fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4035fcf5ef2aSThomas Huth #else 4036fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4037fcf5ef2aSThomas Huth #endif 4038fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4039fcf5ef2aSThomas Huth { 4040fcf5ef2aSThomas Huth uint32_t lev; 4041fcf5ef2aSThomas Huth 4042fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4043fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4044fcf5ef2aSThomas Huth } 4045fcf5ef2aSThomas Huth 4046fcf5ef2aSThomas Huth /*** Trap ***/ 4047fcf5ef2aSThomas Huth 4048fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4049fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4050fcf5ef2aSThomas Huth { 4051fcf5ef2aSThomas Huth /* Trap never */ 4052fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4053fcf5ef2aSThomas Huth return true; 4054fcf5ef2aSThomas Huth } 4055fcf5ef2aSThomas Huth /* Trap always */ 4056fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4057fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4058fcf5ef2aSThomas Huth return true; 4059fcf5ef2aSThomas Huth } 4060fcf5ef2aSThomas Huth return false; 4061fcf5ef2aSThomas Huth } 4062fcf5ef2aSThomas Huth 4063fcf5ef2aSThomas Huth /* tw */ 4064fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4065fcf5ef2aSThomas Huth { 4066fcf5ef2aSThomas Huth TCGv_i32 t0; 4067fcf5ef2aSThomas Huth 4068fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4069fcf5ef2aSThomas Huth return; 4070fcf5ef2aSThomas Huth } 4071fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4072fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4073fcf5ef2aSThomas Huth t0); 4074fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4075fcf5ef2aSThomas Huth } 4076fcf5ef2aSThomas Huth 4077fcf5ef2aSThomas Huth /* twi */ 4078fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4079fcf5ef2aSThomas Huth { 4080fcf5ef2aSThomas Huth TCGv t0; 4081fcf5ef2aSThomas Huth TCGv_i32 t1; 4082fcf5ef2aSThomas Huth 4083fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4084fcf5ef2aSThomas Huth return; 4085fcf5ef2aSThomas Huth } 4086fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4087fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4088fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4089fcf5ef2aSThomas Huth tcg_temp_free(t0); 4090fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4091fcf5ef2aSThomas Huth } 4092fcf5ef2aSThomas Huth 4093fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4094fcf5ef2aSThomas Huth /* td */ 4095fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4096fcf5ef2aSThomas Huth { 4097fcf5ef2aSThomas Huth TCGv_i32 t0; 4098fcf5ef2aSThomas Huth 4099fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4100fcf5ef2aSThomas Huth return; 4101fcf5ef2aSThomas Huth } 4102fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4103fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4104fcf5ef2aSThomas Huth t0); 4105fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4106fcf5ef2aSThomas Huth } 4107fcf5ef2aSThomas Huth 4108fcf5ef2aSThomas Huth /* tdi */ 4109fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4110fcf5ef2aSThomas Huth { 4111fcf5ef2aSThomas Huth TCGv t0; 4112fcf5ef2aSThomas Huth TCGv_i32 t1; 4113fcf5ef2aSThomas Huth 4114fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4115fcf5ef2aSThomas Huth return; 4116fcf5ef2aSThomas Huth } 4117fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4118fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4119fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4120fcf5ef2aSThomas Huth tcg_temp_free(t0); 4121fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4122fcf5ef2aSThomas Huth } 4123fcf5ef2aSThomas Huth #endif 4124fcf5ef2aSThomas Huth 4125fcf5ef2aSThomas Huth /*** Processor control ***/ 4126fcf5ef2aSThomas Huth 4127dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 4128fcf5ef2aSThomas Huth { 4129fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4130fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4131fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4132fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 4133fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4134fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4135fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4136fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 4137fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 4138fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 4139dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 4140dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4141dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4142dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4143dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4144dd09c361SNikunj A Dadhania } 4145fcf5ef2aSThomas Huth tcg_temp_free(t0); 4146fcf5ef2aSThomas Huth tcg_temp_free(t1); 4147fcf5ef2aSThomas Huth tcg_temp_free(t2); 4148fcf5ef2aSThomas Huth } 4149fcf5ef2aSThomas Huth 4150fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 4151fcf5ef2aSThomas Huth { 4152dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 4153fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 4154dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 4155dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 4156dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 4157dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4158dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 41591bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 41601bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 41611bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4162fcf5ef2aSThomas Huth } 4163fcf5ef2aSThomas Huth 4164fcf5ef2aSThomas Huth /* mcrxr */ 4165fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4166fcf5ef2aSThomas Huth { 4167fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4168fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4169fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4170fcf5ef2aSThomas Huth 4171fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4172fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4173fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4174fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4175fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4176fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4177fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4178fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4179fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4180fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4181fcf5ef2aSThomas Huth 4182fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4183fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4184fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4185fcf5ef2aSThomas Huth } 4186fcf5ef2aSThomas Huth 4187b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4188b63d0434SNikunj A Dadhania /* mcrxrx */ 4189b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4190b63d0434SNikunj A Dadhania { 4191b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4192b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4193b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4194b63d0434SNikunj A Dadhania 4195b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4196b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4197b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4198b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4199b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4200b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4201b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4202b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4203b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4204b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4205b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4206b63d0434SNikunj A Dadhania } 4207b63d0434SNikunj A Dadhania #endif 4208b63d0434SNikunj A Dadhania 4209fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4210fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4211fcf5ef2aSThomas Huth { 4212fcf5ef2aSThomas Huth uint32_t crm, crn; 4213fcf5ef2aSThomas Huth 4214fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4215fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4216fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4217fcf5ef2aSThomas Huth crn = ctz32(crm); 4218fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4219fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4220fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4221fcf5ef2aSThomas Huth } 4222fcf5ef2aSThomas Huth } else { 4223fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4224fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4225fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4226fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4227fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4228fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4229fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4230fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4231fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4232fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4233fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4234fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4235fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4236fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4237fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4238fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4239fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4240fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4241fcf5ef2aSThomas Huth } 4242fcf5ef2aSThomas Huth } 4243fcf5ef2aSThomas Huth 4244fcf5ef2aSThomas Huth /* mfmsr */ 4245fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4246fcf5ef2aSThomas Huth { 4247fcf5ef2aSThomas Huth CHK_SV; 4248fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4249fcf5ef2aSThomas Huth } 4250fcf5ef2aSThomas Huth 4251fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4252fcf5ef2aSThomas Huth { 4253fcf5ef2aSThomas Huth #if 0 4254fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4255fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 4256fcf5ef2aSThomas Huth #endif 4257fcf5ef2aSThomas Huth } 4258fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 4259fcf5ef2aSThomas Huth 4260fcf5ef2aSThomas Huth /* mfspr */ 4261fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4262fcf5ef2aSThomas Huth { 4263fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4264fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4265fcf5ef2aSThomas Huth 4266fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4267fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4268fcf5ef2aSThomas Huth #else 4269fcf5ef2aSThomas Huth if (ctx->pr) { 4270fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4271fcf5ef2aSThomas Huth } else if (ctx->hv) { 4272fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4273fcf5ef2aSThomas Huth } else { 4274fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4275fcf5ef2aSThomas Huth } 4276fcf5ef2aSThomas Huth #endif 4277fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4278fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4279fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4280fcf5ef2aSThomas Huth } else { 4281fcf5ef2aSThomas Huth /* Privilege exception */ 4282efe843d8SDavid Gibson /* 4283efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4284fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4285fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4286fcf5ef2aSThomas Huth */ 4287fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 428831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 428931085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4290b6bac4bcSEmilio G. Cota ctx->base.pc_next - 4); 4291fcf5ef2aSThomas Huth } 4292fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4293fcf5ef2aSThomas Huth } 4294fcf5ef2aSThomas Huth } else { 4295fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4296fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4297fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4298fcf5ef2aSThomas Huth /* This is a nop */ 4299fcf5ef2aSThomas Huth return; 4300fcf5ef2aSThomas Huth } 4301fcf5ef2aSThomas Huth /* Not defined */ 430231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 430331085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 4304b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4305fcf5ef2aSThomas Huth 4306efe843d8SDavid Gibson /* 4307efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4308efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4309fcf5ef2aSThomas Huth */ 4310fcf5ef2aSThomas Huth if (sprn & 0x10) { 4311fcf5ef2aSThomas Huth if (ctx->pr) { 4312fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4313fcf5ef2aSThomas Huth } 4314fcf5ef2aSThomas Huth } else { 4315fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4316fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4317fcf5ef2aSThomas Huth } 4318fcf5ef2aSThomas Huth } 4319fcf5ef2aSThomas Huth } 4320fcf5ef2aSThomas Huth } 4321fcf5ef2aSThomas Huth 4322fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4323fcf5ef2aSThomas Huth { 4324fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4325fcf5ef2aSThomas Huth } 4326fcf5ef2aSThomas Huth 4327fcf5ef2aSThomas Huth /* mftb */ 4328fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4329fcf5ef2aSThomas Huth { 4330fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4331fcf5ef2aSThomas Huth } 4332fcf5ef2aSThomas Huth 4333fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4334fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4335fcf5ef2aSThomas Huth { 4336fcf5ef2aSThomas Huth uint32_t crm, crn; 4337fcf5ef2aSThomas Huth 4338fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4339fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4340fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4341fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4342fcf5ef2aSThomas Huth crn = ctz32(crm); 4343fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4344fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4345fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4346fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4347fcf5ef2aSThomas Huth } 4348fcf5ef2aSThomas Huth } else { 4349fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4350fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4351fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4352fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4353fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4354fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4355fcf5ef2aSThomas Huth } 4356fcf5ef2aSThomas Huth } 4357fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4358fcf5ef2aSThomas Huth } 4359fcf5ef2aSThomas Huth } 4360fcf5ef2aSThomas Huth 4361fcf5ef2aSThomas Huth /* mtmsr */ 4362fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4363fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4364fcf5ef2aSThomas Huth { 4365fcf5ef2aSThomas Huth CHK_SV; 4366fcf5ef2aSThomas Huth 4367fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4368fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4369fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4370fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4371efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4372efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 4373efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_msr, cpu_msr, 4374efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4375fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4376fcf5ef2aSThomas Huth tcg_temp_free(t0); 4377fcf5ef2aSThomas Huth } else { 4378efe843d8SDavid Gibson /* 4379efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4380efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4381efe843d8SDavid Gibson * ppc_store_msr 4382fcf5ef2aSThomas Huth */ 4383b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4384b8edea50SPavel Dovgalyuk gen_io_start(); 4385b8edea50SPavel Dovgalyuk } 4386b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4387fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4388fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4389fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4390fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4391b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4392b8edea50SPavel Dovgalyuk gen_io_end(); 4393b8edea50SPavel Dovgalyuk } 4394fcf5ef2aSThomas Huth } 4395fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4396fcf5ef2aSThomas Huth } 4397fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4398fcf5ef2aSThomas Huth 4399fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4400fcf5ef2aSThomas Huth { 4401fcf5ef2aSThomas Huth CHK_SV; 4402fcf5ef2aSThomas Huth 4403fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4404fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4405fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4406fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4407efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4408efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 4409efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_msr, cpu_msr, 4410efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4411fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4412fcf5ef2aSThomas Huth tcg_temp_free(t0); 4413fcf5ef2aSThomas Huth } else { 4414fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4415fcf5ef2aSThomas Huth 4416efe843d8SDavid Gibson /* 4417efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4418efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4419efe843d8SDavid Gibson * ppc_store_msr 4420fcf5ef2aSThomas Huth */ 4421b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4422b8edea50SPavel Dovgalyuk gen_io_start(); 4423b8edea50SPavel Dovgalyuk } 4424b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4425fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4426fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4427fcf5ef2aSThomas Huth #else 4428fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4429fcf5ef2aSThomas Huth #endif 4430fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4431b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4432b8edea50SPavel Dovgalyuk gen_io_end(); 4433b8edea50SPavel Dovgalyuk } 4434fcf5ef2aSThomas Huth tcg_temp_free(msr); 4435fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4436fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4437fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4438fcf5ef2aSThomas Huth } 4439fcf5ef2aSThomas Huth #endif 4440fcf5ef2aSThomas Huth } 4441fcf5ef2aSThomas Huth 4442fcf5ef2aSThomas Huth /* mtspr */ 4443fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4444fcf5ef2aSThomas Huth { 4445fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4446fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4447fcf5ef2aSThomas Huth 4448fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4449fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4450fcf5ef2aSThomas Huth #else 4451fcf5ef2aSThomas Huth if (ctx->pr) { 4452fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4453fcf5ef2aSThomas Huth } else if (ctx->hv) { 4454fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4455fcf5ef2aSThomas Huth } else { 4456fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4457fcf5ef2aSThomas Huth } 4458fcf5ef2aSThomas Huth #endif 4459fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4460fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4461fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4462fcf5ef2aSThomas Huth } else { 4463fcf5ef2aSThomas Huth /* Privilege exception */ 446431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 446531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 446631085338SThomas Huth ctx->base.pc_next - 4); 4467fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4468fcf5ef2aSThomas Huth } 4469fcf5ef2aSThomas Huth } else { 4470fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4471fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4472fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4473fcf5ef2aSThomas Huth /* This is a nop */ 4474fcf5ef2aSThomas Huth return; 4475fcf5ef2aSThomas Huth } 4476fcf5ef2aSThomas Huth 4477fcf5ef2aSThomas Huth /* Not defined */ 447831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 447931085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 4480b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4481fcf5ef2aSThomas Huth 4482fcf5ef2aSThomas Huth 4483efe843d8SDavid Gibson /* 4484efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4485efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4486fcf5ef2aSThomas Huth */ 4487fcf5ef2aSThomas Huth if (sprn & 0x10) { 4488fcf5ef2aSThomas Huth if (ctx->pr) { 4489fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4490fcf5ef2aSThomas Huth } 4491fcf5ef2aSThomas Huth } else { 4492fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4493fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4494fcf5ef2aSThomas Huth } 4495fcf5ef2aSThomas Huth } 4496fcf5ef2aSThomas Huth } 4497fcf5ef2aSThomas Huth } 4498fcf5ef2aSThomas Huth 4499fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4500fcf5ef2aSThomas Huth /* setb */ 4501fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4502fcf5ef2aSThomas Huth { 4503fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4504fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4505fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4506fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4507fcf5ef2aSThomas Huth 4508fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4509fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4510fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4511fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4512fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4513fcf5ef2aSThomas Huth 4514fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4515fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4516fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4517fcf5ef2aSThomas Huth } 4518fcf5ef2aSThomas Huth #endif 4519fcf5ef2aSThomas Huth 4520fcf5ef2aSThomas Huth /*** Cache management ***/ 4521fcf5ef2aSThomas Huth 4522fcf5ef2aSThomas Huth /* dcbf */ 4523fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4524fcf5ef2aSThomas Huth { 4525fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4526fcf5ef2aSThomas Huth TCGv t0; 4527fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4528fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4529fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4530fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4531fcf5ef2aSThomas Huth tcg_temp_free(t0); 4532fcf5ef2aSThomas Huth } 4533fcf5ef2aSThomas Huth 453450728199SRoman Kapl /* dcbfep (external PID dcbf) */ 453550728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 453650728199SRoman Kapl { 453750728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 453850728199SRoman Kapl TCGv t0; 453950728199SRoman Kapl CHK_SV; 454050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 454150728199SRoman Kapl t0 = tcg_temp_new(); 454250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 454350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 454450728199SRoman Kapl tcg_temp_free(t0); 454550728199SRoman Kapl } 454650728199SRoman Kapl 4547fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4548fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4549fcf5ef2aSThomas Huth { 4550fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4551fcf5ef2aSThomas Huth GEN_PRIV; 4552fcf5ef2aSThomas Huth #else 4553fcf5ef2aSThomas Huth TCGv EA, val; 4554fcf5ef2aSThomas Huth 4555fcf5ef2aSThomas Huth CHK_SV; 4556fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4557fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4558fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4559fcf5ef2aSThomas Huth val = tcg_temp_new(); 4560fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4561fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4562fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4563fcf5ef2aSThomas Huth tcg_temp_free(val); 4564fcf5ef2aSThomas Huth tcg_temp_free(EA); 4565fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4566fcf5ef2aSThomas Huth } 4567fcf5ef2aSThomas Huth 4568fcf5ef2aSThomas Huth /* dcdst */ 4569fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4570fcf5ef2aSThomas Huth { 4571fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4572fcf5ef2aSThomas Huth TCGv t0; 4573fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4574fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4575fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4576fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4577fcf5ef2aSThomas Huth tcg_temp_free(t0); 4578fcf5ef2aSThomas Huth } 4579fcf5ef2aSThomas Huth 458050728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 458150728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 458250728199SRoman Kapl { 458350728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 458450728199SRoman Kapl TCGv t0; 458550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 458650728199SRoman Kapl t0 = tcg_temp_new(); 458750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 458850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 458950728199SRoman Kapl tcg_temp_free(t0); 459050728199SRoman Kapl } 459150728199SRoman Kapl 4592fcf5ef2aSThomas Huth /* dcbt */ 4593fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4594fcf5ef2aSThomas Huth { 4595efe843d8SDavid Gibson /* 4596efe843d8SDavid Gibson * interpreted as no-op 4597efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4598efe843d8SDavid Gibson * does not generate any exception 4599fcf5ef2aSThomas Huth */ 4600fcf5ef2aSThomas Huth } 4601fcf5ef2aSThomas Huth 460250728199SRoman Kapl /* dcbtep */ 460350728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 460450728199SRoman Kapl { 4605efe843d8SDavid Gibson /* 4606efe843d8SDavid Gibson * interpreted as no-op 4607efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4608efe843d8SDavid Gibson * does not generate any exception 460950728199SRoman Kapl */ 461050728199SRoman Kapl } 461150728199SRoman Kapl 4612fcf5ef2aSThomas Huth /* dcbtst */ 4613fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4614fcf5ef2aSThomas Huth { 4615efe843d8SDavid Gibson /* 4616efe843d8SDavid Gibson * interpreted as no-op 4617efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4618efe843d8SDavid Gibson * does not generate any exception 4619fcf5ef2aSThomas Huth */ 4620fcf5ef2aSThomas Huth } 4621fcf5ef2aSThomas Huth 462250728199SRoman Kapl /* dcbtstep */ 462350728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 462450728199SRoman Kapl { 4625efe843d8SDavid Gibson /* 4626efe843d8SDavid Gibson * interpreted as no-op 4627efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4628efe843d8SDavid Gibson * does not generate any exception 462950728199SRoman Kapl */ 463050728199SRoman Kapl } 463150728199SRoman Kapl 4632fcf5ef2aSThomas Huth /* dcbtls */ 4633fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4634fcf5ef2aSThomas Huth { 4635fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4636fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4637fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4638fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4639fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4640fcf5ef2aSThomas Huth tcg_temp_free(t0); 4641fcf5ef2aSThomas Huth } 4642fcf5ef2aSThomas Huth 4643fcf5ef2aSThomas Huth /* dcbz */ 4644fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4645fcf5ef2aSThomas Huth { 4646fcf5ef2aSThomas Huth TCGv tcgv_addr; 4647fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4648fcf5ef2aSThomas Huth 4649fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4650fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4651fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4652fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4653fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4654fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4655fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4656fcf5ef2aSThomas Huth } 4657fcf5ef2aSThomas Huth 465850728199SRoman Kapl /* dcbzep */ 465950728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 466050728199SRoman Kapl { 466150728199SRoman Kapl TCGv tcgv_addr; 466250728199SRoman Kapl TCGv_i32 tcgv_op; 466350728199SRoman Kapl 466450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 466550728199SRoman Kapl tcgv_addr = tcg_temp_new(); 466650728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 466750728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 466850728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 466950728199SRoman Kapl tcg_temp_free(tcgv_addr); 467050728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 467150728199SRoman Kapl } 467250728199SRoman Kapl 4673fcf5ef2aSThomas Huth /* dst / dstt */ 4674fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4675fcf5ef2aSThomas Huth { 4676fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4677fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4678fcf5ef2aSThomas Huth } else { 4679fcf5ef2aSThomas Huth /* interpreted as no-op */ 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth } 4682fcf5ef2aSThomas Huth 4683fcf5ef2aSThomas Huth /* dstst /dststt */ 4684fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4685fcf5ef2aSThomas Huth { 4686fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4687fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4688fcf5ef2aSThomas Huth } else { 4689fcf5ef2aSThomas Huth /* interpreted as no-op */ 4690fcf5ef2aSThomas Huth } 4691fcf5ef2aSThomas Huth 4692fcf5ef2aSThomas Huth } 4693fcf5ef2aSThomas Huth 4694fcf5ef2aSThomas Huth /* dss / dssall */ 4695fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4696fcf5ef2aSThomas Huth { 4697fcf5ef2aSThomas Huth /* interpreted as no-op */ 4698fcf5ef2aSThomas Huth } 4699fcf5ef2aSThomas Huth 4700fcf5ef2aSThomas Huth /* icbi */ 4701fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4702fcf5ef2aSThomas Huth { 4703fcf5ef2aSThomas Huth TCGv t0; 4704fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4705fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4706fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4707fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4708fcf5ef2aSThomas Huth tcg_temp_free(t0); 4709fcf5ef2aSThomas Huth } 4710fcf5ef2aSThomas Huth 471150728199SRoman Kapl /* icbiep */ 471250728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 471350728199SRoman Kapl { 471450728199SRoman Kapl TCGv t0; 471550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 471650728199SRoman Kapl t0 = tcg_temp_new(); 471750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 471850728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 471950728199SRoman Kapl tcg_temp_free(t0); 472050728199SRoman Kapl } 472150728199SRoman Kapl 4722fcf5ef2aSThomas Huth /* Optional: */ 4723fcf5ef2aSThomas Huth /* dcba */ 4724fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4725fcf5ef2aSThomas Huth { 4726efe843d8SDavid Gibson /* 4727efe843d8SDavid Gibson * interpreted as no-op 4728efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 4729fcf5ef2aSThomas Huth * but does not generate any exception 4730fcf5ef2aSThomas Huth */ 4731fcf5ef2aSThomas Huth } 4732fcf5ef2aSThomas Huth 4733fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4734fcf5ef2aSThomas Huth /* Supervisor only: */ 4735fcf5ef2aSThomas Huth 4736fcf5ef2aSThomas Huth /* mfsr */ 4737fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4738fcf5ef2aSThomas Huth { 4739fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4740fcf5ef2aSThomas Huth GEN_PRIV; 4741fcf5ef2aSThomas Huth #else 4742fcf5ef2aSThomas Huth TCGv t0; 4743fcf5ef2aSThomas Huth 4744fcf5ef2aSThomas Huth CHK_SV; 4745fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4746fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4747fcf5ef2aSThomas Huth tcg_temp_free(t0); 4748fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4749fcf5ef2aSThomas Huth } 4750fcf5ef2aSThomas Huth 4751fcf5ef2aSThomas Huth /* mfsrin */ 4752fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4753fcf5ef2aSThomas Huth { 4754fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4755fcf5ef2aSThomas Huth GEN_PRIV; 4756fcf5ef2aSThomas Huth #else 4757fcf5ef2aSThomas Huth TCGv t0; 4758fcf5ef2aSThomas Huth 4759fcf5ef2aSThomas Huth CHK_SV; 4760fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4761e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4762fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4763fcf5ef2aSThomas Huth tcg_temp_free(t0); 4764fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4765fcf5ef2aSThomas Huth } 4766fcf5ef2aSThomas Huth 4767fcf5ef2aSThomas Huth /* mtsr */ 4768fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4769fcf5ef2aSThomas Huth { 4770fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4771fcf5ef2aSThomas Huth GEN_PRIV; 4772fcf5ef2aSThomas Huth #else 4773fcf5ef2aSThomas Huth TCGv t0; 4774fcf5ef2aSThomas Huth 4775fcf5ef2aSThomas Huth CHK_SV; 4776fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4777fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4778fcf5ef2aSThomas Huth tcg_temp_free(t0); 4779fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4780fcf5ef2aSThomas Huth } 4781fcf5ef2aSThomas Huth 4782fcf5ef2aSThomas Huth /* mtsrin */ 4783fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4784fcf5ef2aSThomas Huth { 4785fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4786fcf5ef2aSThomas Huth GEN_PRIV; 4787fcf5ef2aSThomas Huth #else 4788fcf5ef2aSThomas Huth TCGv t0; 4789fcf5ef2aSThomas Huth CHK_SV; 4790fcf5ef2aSThomas Huth 4791fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4792e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4793fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4794fcf5ef2aSThomas Huth tcg_temp_free(t0); 4795fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4796fcf5ef2aSThomas Huth } 4797fcf5ef2aSThomas Huth 4798fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4799fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4800fcf5ef2aSThomas Huth 4801fcf5ef2aSThomas Huth /* mfsr */ 4802fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4803fcf5ef2aSThomas Huth { 4804fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4805fcf5ef2aSThomas Huth GEN_PRIV; 4806fcf5ef2aSThomas Huth #else 4807fcf5ef2aSThomas Huth TCGv t0; 4808fcf5ef2aSThomas Huth 4809fcf5ef2aSThomas Huth CHK_SV; 4810fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4811fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4812fcf5ef2aSThomas Huth tcg_temp_free(t0); 4813fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4814fcf5ef2aSThomas Huth } 4815fcf5ef2aSThomas Huth 4816fcf5ef2aSThomas Huth /* mfsrin */ 4817fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4818fcf5ef2aSThomas Huth { 4819fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4820fcf5ef2aSThomas Huth GEN_PRIV; 4821fcf5ef2aSThomas Huth #else 4822fcf5ef2aSThomas Huth TCGv t0; 4823fcf5ef2aSThomas Huth 4824fcf5ef2aSThomas Huth CHK_SV; 4825fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4826e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4827fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4828fcf5ef2aSThomas Huth tcg_temp_free(t0); 4829fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4830fcf5ef2aSThomas Huth } 4831fcf5ef2aSThomas Huth 4832fcf5ef2aSThomas Huth /* mtsr */ 4833fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4834fcf5ef2aSThomas Huth { 4835fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4836fcf5ef2aSThomas Huth GEN_PRIV; 4837fcf5ef2aSThomas Huth #else 4838fcf5ef2aSThomas Huth TCGv t0; 4839fcf5ef2aSThomas Huth 4840fcf5ef2aSThomas Huth CHK_SV; 4841fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4842fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4843fcf5ef2aSThomas Huth tcg_temp_free(t0); 4844fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4845fcf5ef2aSThomas Huth } 4846fcf5ef2aSThomas Huth 4847fcf5ef2aSThomas Huth /* mtsrin */ 4848fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4849fcf5ef2aSThomas Huth { 4850fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4851fcf5ef2aSThomas Huth GEN_PRIV; 4852fcf5ef2aSThomas Huth #else 4853fcf5ef2aSThomas Huth TCGv t0; 4854fcf5ef2aSThomas Huth 4855fcf5ef2aSThomas Huth CHK_SV; 4856fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4857e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4858fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4859fcf5ef2aSThomas Huth tcg_temp_free(t0); 4860fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4861fcf5ef2aSThomas Huth } 4862fcf5ef2aSThomas Huth 4863fcf5ef2aSThomas Huth /* slbmte */ 4864fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4865fcf5ef2aSThomas Huth { 4866fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4867fcf5ef2aSThomas Huth GEN_PRIV; 4868fcf5ef2aSThomas Huth #else 4869fcf5ef2aSThomas Huth CHK_SV; 4870fcf5ef2aSThomas Huth 4871fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4872fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4873fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4874fcf5ef2aSThomas Huth } 4875fcf5ef2aSThomas Huth 4876fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4877fcf5ef2aSThomas Huth { 4878fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4879fcf5ef2aSThomas Huth GEN_PRIV; 4880fcf5ef2aSThomas Huth #else 4881fcf5ef2aSThomas Huth CHK_SV; 4882fcf5ef2aSThomas Huth 4883fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4884fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4885fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4886fcf5ef2aSThomas Huth } 4887fcf5ef2aSThomas Huth 4888fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4889fcf5ef2aSThomas Huth { 4890fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4891fcf5ef2aSThomas Huth GEN_PRIV; 4892fcf5ef2aSThomas Huth #else 4893fcf5ef2aSThomas Huth CHK_SV; 4894fcf5ef2aSThomas Huth 4895fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4896fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4897fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4898fcf5ef2aSThomas Huth } 4899fcf5ef2aSThomas Huth 4900fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4901fcf5ef2aSThomas Huth { 4902fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4903fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4904fcf5ef2aSThomas Huth #else 4905fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4906fcf5ef2aSThomas Huth 4907fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4908fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4909fcf5ef2aSThomas Huth return; 4910fcf5ef2aSThomas Huth } 4911fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4912fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4913fcf5ef2aSThomas Huth l1 = gen_new_label(); 4914fcf5ef2aSThomas Huth l2 = gen_new_label(); 4915fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4916fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4917efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4918fcf5ef2aSThomas Huth tcg_gen_br(l2); 4919fcf5ef2aSThomas Huth gen_set_label(l1); 4920fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4921fcf5ef2aSThomas Huth gen_set_label(l2); 4922fcf5ef2aSThomas Huth #endif 4923fcf5ef2aSThomas Huth } 4924fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4925fcf5ef2aSThomas Huth 4926fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4927fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4928fcf5ef2aSThomas Huth 4929fcf5ef2aSThomas Huth /* tlbia */ 4930fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4931fcf5ef2aSThomas Huth { 4932fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4933fcf5ef2aSThomas Huth GEN_PRIV; 4934fcf5ef2aSThomas Huth #else 4935fcf5ef2aSThomas Huth CHK_HV; 4936fcf5ef2aSThomas Huth 4937fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4938fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4939fcf5ef2aSThomas Huth } 4940fcf5ef2aSThomas Huth 4941fcf5ef2aSThomas Huth /* tlbiel */ 4942fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4943fcf5ef2aSThomas Huth { 4944fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4945fcf5ef2aSThomas Huth GEN_PRIV; 4946fcf5ef2aSThomas Huth #else 4947fcf5ef2aSThomas Huth CHK_SV; 4948fcf5ef2aSThomas Huth 4949fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4950fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4951fcf5ef2aSThomas Huth } 4952fcf5ef2aSThomas Huth 4953fcf5ef2aSThomas Huth /* tlbie */ 4954fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4955fcf5ef2aSThomas Huth { 4956fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4957fcf5ef2aSThomas Huth GEN_PRIV; 4958fcf5ef2aSThomas Huth #else 4959fcf5ef2aSThomas Huth TCGv_i32 t1; 4960c6fd28fdSSuraj Jitindar Singh 4961c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 496291c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4963c6fd28fdSSuraj Jitindar Singh } else { 4964c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 4965c6fd28fdSSuraj Jitindar Singh } 4966fcf5ef2aSThomas Huth 4967fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4968fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4969fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4970fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4971fcf5ef2aSThomas Huth tcg_temp_free(t0); 4972fcf5ef2aSThomas Huth } else { 4973fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4974fcf5ef2aSThomas Huth } 4975fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4976fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4977fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4978fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4979fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4980fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4981fcf5ef2aSThomas Huth } 4982fcf5ef2aSThomas Huth 4983fcf5ef2aSThomas Huth /* tlbsync */ 4984fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4985fcf5ef2aSThomas Huth { 4986fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4987fcf5ef2aSThomas Huth GEN_PRIV; 4988fcf5ef2aSThomas Huth #else 498991c60f12SCédric Le Goater 499091c60f12SCédric Le Goater if (ctx->gtse) { 499191c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 499291c60f12SCédric Le Goater } else { 499391c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 499491c60f12SCédric Le Goater } 4995fcf5ef2aSThomas Huth 4996fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4997fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4998fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4999fcf5ef2aSThomas Huth } 5000fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5001fcf5ef2aSThomas Huth } 5002fcf5ef2aSThomas Huth 5003fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5004fcf5ef2aSThomas Huth /* slbia */ 5005fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5006fcf5ef2aSThomas Huth { 5007fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5008fcf5ef2aSThomas Huth GEN_PRIV; 5009fcf5ef2aSThomas Huth #else 5010fcf5ef2aSThomas Huth CHK_SV; 5011fcf5ef2aSThomas Huth 5012fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 5013fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5014fcf5ef2aSThomas Huth } 5015fcf5ef2aSThomas Huth 5016fcf5ef2aSThomas Huth /* slbie */ 5017fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5018fcf5ef2aSThomas Huth { 5019fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5020fcf5ef2aSThomas Huth GEN_PRIV; 5021fcf5ef2aSThomas Huth #else 5022fcf5ef2aSThomas Huth CHK_SV; 5023fcf5ef2aSThomas Huth 5024fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5025fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5026fcf5ef2aSThomas Huth } 5027a63f1dfcSNikunj A Dadhania 5028a63f1dfcSNikunj A Dadhania /* slbieg */ 5029a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5030a63f1dfcSNikunj A Dadhania { 5031a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5032a63f1dfcSNikunj A Dadhania GEN_PRIV; 5033a63f1dfcSNikunj A Dadhania #else 5034a63f1dfcSNikunj A Dadhania CHK_SV; 5035a63f1dfcSNikunj A Dadhania 5036a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5037a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5038a63f1dfcSNikunj A Dadhania } 5039a63f1dfcSNikunj A Dadhania 504062d897caSNikunj A Dadhania /* slbsync */ 504162d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 504262d897caSNikunj A Dadhania { 504362d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 504462d897caSNikunj A Dadhania GEN_PRIV; 504562d897caSNikunj A Dadhania #else 504662d897caSNikunj A Dadhania CHK_SV; 504762d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 504862d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 504962d897caSNikunj A Dadhania } 505062d897caSNikunj A Dadhania 5051fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5052fcf5ef2aSThomas Huth 5053fcf5ef2aSThomas Huth /*** External control ***/ 5054fcf5ef2aSThomas Huth /* Optional: */ 5055fcf5ef2aSThomas Huth 5056fcf5ef2aSThomas Huth /* eciwx */ 5057fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5058fcf5ef2aSThomas Huth { 5059fcf5ef2aSThomas Huth TCGv t0; 5060fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5061fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5062fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5063fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5064c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5065c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5066fcf5ef2aSThomas Huth tcg_temp_free(t0); 5067fcf5ef2aSThomas Huth } 5068fcf5ef2aSThomas Huth 5069fcf5ef2aSThomas Huth /* ecowx */ 5070fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5071fcf5ef2aSThomas Huth { 5072fcf5ef2aSThomas Huth TCGv t0; 5073fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5074fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5075fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5076fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5077c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5078c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5079fcf5ef2aSThomas Huth tcg_temp_free(t0); 5080fcf5ef2aSThomas Huth } 5081fcf5ef2aSThomas Huth 5082fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5083fcf5ef2aSThomas Huth 5084fcf5ef2aSThomas Huth /* abs - abs. */ 5085fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5086fcf5ef2aSThomas Huth { 5087fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5088fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5089fe21b785SRichard Henderson 5090fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5091efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5092fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5093fcf5ef2aSThomas Huth } 5094efe843d8SDavid Gibson } 5095fcf5ef2aSThomas Huth 5096fcf5ef2aSThomas Huth /* abso - abso. */ 5097fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5098fcf5ef2aSThomas Huth { 5099fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5100fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5101fe21b785SRichard Henderson 5102fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5103fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5104fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5105efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5106fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5107fcf5ef2aSThomas Huth } 5108efe843d8SDavid Gibson } 5109fcf5ef2aSThomas Huth 5110fcf5ef2aSThomas Huth /* clcs */ 5111fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5112fcf5ef2aSThomas Huth { 5113fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5114fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5115fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5116fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5117fcf5ef2aSThomas Huth } 5118fcf5ef2aSThomas Huth 5119fcf5ef2aSThomas Huth /* div - div. */ 5120fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5121fcf5ef2aSThomas Huth { 5122fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5123fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5124efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5125fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5126fcf5ef2aSThomas Huth } 5127efe843d8SDavid Gibson } 5128fcf5ef2aSThomas Huth 5129fcf5ef2aSThomas Huth /* divo - divo. */ 5130fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5131fcf5ef2aSThomas Huth { 5132fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5133fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5134efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5135fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5136fcf5ef2aSThomas Huth } 5137efe843d8SDavid Gibson } 5138fcf5ef2aSThomas Huth 5139fcf5ef2aSThomas Huth /* divs - divs. */ 5140fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5141fcf5ef2aSThomas Huth { 5142fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5143fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5144efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5145fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5146fcf5ef2aSThomas Huth } 5147efe843d8SDavid Gibson } 5148fcf5ef2aSThomas Huth 5149fcf5ef2aSThomas Huth /* divso - divso. */ 5150fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5151fcf5ef2aSThomas Huth { 5152fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5153fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5154efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5155fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5156fcf5ef2aSThomas Huth } 5157efe843d8SDavid Gibson } 5158fcf5ef2aSThomas Huth 5159fcf5ef2aSThomas Huth /* doz - doz. */ 5160fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5161fcf5ef2aSThomas Huth { 5162fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5163fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5164efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5165efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5166efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5167efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5168fcf5ef2aSThomas Huth tcg_gen_br(l2); 5169fcf5ef2aSThomas Huth gen_set_label(l1); 5170fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5171fcf5ef2aSThomas Huth gen_set_label(l2); 5172efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5173fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5174fcf5ef2aSThomas Huth } 5175efe843d8SDavid Gibson } 5176fcf5ef2aSThomas Huth 5177fcf5ef2aSThomas Huth /* dozo - dozo. */ 5178fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5179fcf5ef2aSThomas Huth { 5180fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5181fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5182fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5183fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5184fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5185fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5186fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5187efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5188efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5189fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5190fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5191fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5192fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5193fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5194fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5195fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5196fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5197fcf5ef2aSThomas Huth tcg_gen_br(l2); 5198fcf5ef2aSThomas Huth gen_set_label(l1); 5199fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5200fcf5ef2aSThomas Huth gen_set_label(l2); 5201fcf5ef2aSThomas Huth tcg_temp_free(t0); 5202fcf5ef2aSThomas Huth tcg_temp_free(t1); 5203fcf5ef2aSThomas Huth tcg_temp_free(t2); 5204efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5205fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5206fcf5ef2aSThomas Huth } 5207efe843d8SDavid Gibson } 5208fcf5ef2aSThomas Huth 5209fcf5ef2aSThomas Huth /* dozi */ 5210fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5211fcf5ef2aSThomas Huth { 5212fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5213fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5214fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5215fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5216fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5217fcf5ef2aSThomas Huth tcg_gen_br(l2); 5218fcf5ef2aSThomas Huth gen_set_label(l1); 5219fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5220fcf5ef2aSThomas Huth gen_set_label(l2); 5221efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5222fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5223fcf5ef2aSThomas Huth } 5224efe843d8SDavid Gibson } 5225fcf5ef2aSThomas Huth 5226fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5227fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5228fcf5ef2aSThomas Huth { 5229fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5230fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5231fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5232fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5233fcf5ef2aSThomas Huth 5234fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5235fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5236fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5237fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5238fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5239fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5240fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5241efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5242fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5243efe843d8SDavid Gibson } 5244fcf5ef2aSThomas Huth tcg_temp_free(t0); 5245fcf5ef2aSThomas Huth } 5246fcf5ef2aSThomas Huth 5247fcf5ef2aSThomas Huth /* maskg - maskg. */ 5248fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5249fcf5ef2aSThomas Huth { 5250fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5251fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5252fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5253fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5254fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5255fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5256fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5257fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5258fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5259fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5260fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5261fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5262fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5263fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5264fcf5ef2aSThomas Huth gen_set_label(l1); 5265fcf5ef2aSThomas Huth tcg_temp_free(t0); 5266fcf5ef2aSThomas Huth tcg_temp_free(t1); 5267fcf5ef2aSThomas Huth tcg_temp_free(t2); 5268fcf5ef2aSThomas Huth tcg_temp_free(t3); 5269efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5270fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5271fcf5ef2aSThomas Huth } 5272efe843d8SDavid Gibson } 5273fcf5ef2aSThomas Huth 5274fcf5ef2aSThomas Huth /* maskir - maskir. */ 5275fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5276fcf5ef2aSThomas Huth { 5277fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5278fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5279fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5280fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5281fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5282fcf5ef2aSThomas Huth tcg_temp_free(t0); 5283fcf5ef2aSThomas Huth tcg_temp_free(t1); 5284efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5285fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5286fcf5ef2aSThomas Huth } 5287efe843d8SDavid Gibson } 5288fcf5ef2aSThomas Huth 5289fcf5ef2aSThomas Huth /* mul - mul. */ 5290fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5291fcf5ef2aSThomas Huth { 5292fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5293fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5294fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5295fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5296fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5297fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5298fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5299fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5300fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5301fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5302fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5303fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5304fcf5ef2aSThomas Huth tcg_temp_free(t2); 5305efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5306fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5307fcf5ef2aSThomas Huth } 5308efe843d8SDavid Gibson } 5309fcf5ef2aSThomas Huth 5310fcf5ef2aSThomas Huth /* mulo - mulo. */ 5311fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5312fcf5ef2aSThomas Huth { 5313fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5314fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5315fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5316fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5317fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5318fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5319fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5320fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5321fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5322fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5323fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5324fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5325fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5326fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5327fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5328fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5329fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5330fcf5ef2aSThomas Huth gen_set_label(l1); 5331fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5332fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5333fcf5ef2aSThomas Huth tcg_temp_free(t2); 5334efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5335fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5336fcf5ef2aSThomas Huth } 5337efe843d8SDavid Gibson } 5338fcf5ef2aSThomas Huth 5339fcf5ef2aSThomas Huth /* nabs - nabs. */ 5340fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5341fcf5ef2aSThomas Huth { 5342fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5343fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5344fe21b785SRichard Henderson 5345fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5346fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5347efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5348fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5349fcf5ef2aSThomas Huth } 5350efe843d8SDavid Gibson } 5351fcf5ef2aSThomas Huth 5352fcf5ef2aSThomas Huth /* nabso - nabso. */ 5353fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5354fcf5ef2aSThomas Huth { 5355fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5356fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5357fe21b785SRichard Henderson 5358fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5359fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5360fcf5ef2aSThomas Huth /* nabs never overflows */ 5361fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5362efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5363fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5364fcf5ef2aSThomas Huth } 5365efe843d8SDavid Gibson } 5366fcf5ef2aSThomas Huth 5367fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5368fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5369fcf5ef2aSThomas Huth { 5370fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5371fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5372fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5373fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5374fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5375fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5376efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5377efe843d8SDavid Gibson ~MASK(mb, me)); 5378fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5379fcf5ef2aSThomas Huth tcg_temp_free(t0); 5380efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5381fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5382fcf5ef2aSThomas Huth } 5383efe843d8SDavid Gibson } 5384fcf5ef2aSThomas Huth 5385fcf5ef2aSThomas Huth /* rrib - rrib. */ 5386fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5387fcf5ef2aSThomas Huth { 5388fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5389fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5390fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5391fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5392fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5393fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5394fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5395fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5396fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5397fcf5ef2aSThomas Huth tcg_temp_free(t0); 5398fcf5ef2aSThomas Huth tcg_temp_free(t1); 5399efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5400fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5401fcf5ef2aSThomas Huth } 5402efe843d8SDavid Gibson } 5403fcf5ef2aSThomas Huth 5404fcf5ef2aSThomas Huth /* sle - sle. */ 5405fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5406fcf5ef2aSThomas Huth { 5407fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5408fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5409fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5410fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5411fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5412fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5413fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5414fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5415fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5416fcf5ef2aSThomas Huth tcg_temp_free(t0); 5417fcf5ef2aSThomas Huth tcg_temp_free(t1); 5418efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5419fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5420fcf5ef2aSThomas Huth } 5421efe843d8SDavid Gibson } 5422fcf5ef2aSThomas Huth 5423fcf5ef2aSThomas Huth /* sleq - sleq. */ 5424fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5425fcf5ef2aSThomas Huth { 5426fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5427fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5428fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5429fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5430fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5431fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5432fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5433fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5434fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5435fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5436fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5437fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5438fcf5ef2aSThomas Huth tcg_temp_free(t0); 5439fcf5ef2aSThomas Huth tcg_temp_free(t1); 5440fcf5ef2aSThomas Huth tcg_temp_free(t2); 5441efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5442fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5443fcf5ef2aSThomas Huth } 5444efe843d8SDavid Gibson } 5445fcf5ef2aSThomas Huth 5446fcf5ef2aSThomas Huth /* sliq - sliq. */ 5447fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5448fcf5ef2aSThomas Huth { 5449fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5450fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5451fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5452fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5453fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5454fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5455fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5456fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5457fcf5ef2aSThomas Huth tcg_temp_free(t0); 5458fcf5ef2aSThomas Huth tcg_temp_free(t1); 5459efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5460fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5461fcf5ef2aSThomas Huth } 5462efe843d8SDavid Gibson } 5463fcf5ef2aSThomas Huth 5464fcf5ef2aSThomas Huth /* slliq - slliq. */ 5465fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5466fcf5ef2aSThomas Huth { 5467fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5468fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5469fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5470fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5471fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5472fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5473fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5474fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5475fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5476fcf5ef2aSThomas Huth tcg_temp_free(t0); 5477fcf5ef2aSThomas Huth tcg_temp_free(t1); 5478efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5479fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5480fcf5ef2aSThomas Huth } 5481efe843d8SDavid Gibson } 5482fcf5ef2aSThomas Huth 5483fcf5ef2aSThomas Huth /* sllq - sllq. */ 5484fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5485fcf5ef2aSThomas Huth { 5486fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5487fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5488fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5489fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5490fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5491fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5492fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5493fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5494fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5495fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5496fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5497fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5498fcf5ef2aSThomas Huth tcg_gen_br(l2); 5499fcf5ef2aSThomas Huth gen_set_label(l1); 5500fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5501fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5502fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5503fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5504fcf5ef2aSThomas Huth gen_set_label(l2); 5505fcf5ef2aSThomas Huth tcg_temp_free(t0); 5506fcf5ef2aSThomas Huth tcg_temp_free(t1); 5507fcf5ef2aSThomas Huth tcg_temp_free(t2); 5508efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5509fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5510fcf5ef2aSThomas Huth } 5511efe843d8SDavid Gibson } 5512fcf5ef2aSThomas Huth 5513fcf5ef2aSThomas Huth /* slq - slq. */ 5514fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5515fcf5ef2aSThomas Huth { 5516fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5517fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5518fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5519fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5520fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5521fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5522fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5523fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5524fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5525fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5526fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5527fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5528fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5529fcf5ef2aSThomas Huth gen_set_label(l1); 5530fcf5ef2aSThomas Huth tcg_temp_free(t0); 5531fcf5ef2aSThomas Huth tcg_temp_free(t1); 5532efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5533fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5534fcf5ef2aSThomas Huth } 5535efe843d8SDavid Gibson } 5536fcf5ef2aSThomas Huth 5537fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5538fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5539fcf5ef2aSThomas Huth { 5540fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5541fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5542fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5543fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5544fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5545fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5546fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5547fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5548fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5549fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5550fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5551fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5552fcf5ef2aSThomas Huth gen_set_label(l1); 5553fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5554fcf5ef2aSThomas Huth tcg_temp_free(t0); 5555fcf5ef2aSThomas Huth tcg_temp_free(t1); 5556efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5557fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5558fcf5ef2aSThomas Huth } 5559efe843d8SDavid Gibson } 5560fcf5ef2aSThomas Huth 5561fcf5ef2aSThomas Huth /* sraq - sraq. */ 5562fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5563fcf5ef2aSThomas Huth { 5564fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5565fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5566fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5567fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5568fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5569fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5570fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5571fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5572fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5573fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5574fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5575fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5576fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5577fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5578fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5579fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5580fcf5ef2aSThomas Huth gen_set_label(l1); 5581fcf5ef2aSThomas Huth tcg_temp_free(t0); 5582fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5583fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5584fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5585fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5586fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5587fcf5ef2aSThomas Huth gen_set_label(l2); 5588fcf5ef2aSThomas Huth tcg_temp_free(t1); 5589fcf5ef2aSThomas Huth tcg_temp_free(t2); 5590efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5591fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5592fcf5ef2aSThomas Huth } 5593efe843d8SDavid Gibson } 5594fcf5ef2aSThomas Huth 5595fcf5ef2aSThomas Huth /* sre - sre. */ 5596fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5597fcf5ef2aSThomas Huth { 5598fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5599fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5600fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5601fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5602fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5603fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5604fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5605fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5606fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5607fcf5ef2aSThomas Huth tcg_temp_free(t0); 5608fcf5ef2aSThomas Huth tcg_temp_free(t1); 5609efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5610fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5611fcf5ef2aSThomas Huth } 5612efe843d8SDavid Gibson } 5613fcf5ef2aSThomas Huth 5614fcf5ef2aSThomas Huth /* srea - srea. */ 5615fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5616fcf5ef2aSThomas Huth { 5617fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5618fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5619fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5620fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5621fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5622fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5623fcf5ef2aSThomas Huth tcg_temp_free(t0); 5624fcf5ef2aSThomas Huth tcg_temp_free(t1); 5625efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5626fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5627fcf5ef2aSThomas Huth } 5628efe843d8SDavid Gibson } 5629fcf5ef2aSThomas Huth 5630fcf5ef2aSThomas Huth /* sreq */ 5631fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5632fcf5ef2aSThomas Huth { 5633fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5634fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5635fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5636fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5637fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5638fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5639fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5640fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5641fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5642fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5643fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5644fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5645fcf5ef2aSThomas Huth tcg_temp_free(t0); 5646fcf5ef2aSThomas Huth tcg_temp_free(t1); 5647fcf5ef2aSThomas Huth tcg_temp_free(t2); 5648efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5649fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5650fcf5ef2aSThomas Huth } 5651efe843d8SDavid Gibson } 5652fcf5ef2aSThomas Huth 5653fcf5ef2aSThomas Huth /* sriq */ 5654fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5655fcf5ef2aSThomas Huth { 5656fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5657fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5658fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5659fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5660fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5661fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5662fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5663fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5664fcf5ef2aSThomas Huth tcg_temp_free(t0); 5665fcf5ef2aSThomas Huth tcg_temp_free(t1); 5666efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5667fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5668fcf5ef2aSThomas Huth } 5669efe843d8SDavid Gibson } 5670fcf5ef2aSThomas Huth 5671fcf5ef2aSThomas Huth /* srliq */ 5672fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5673fcf5ef2aSThomas Huth { 5674fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5675fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5676fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5677fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5678fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5679fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5680fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5681fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5682fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5683fcf5ef2aSThomas Huth tcg_temp_free(t0); 5684fcf5ef2aSThomas Huth tcg_temp_free(t1); 5685efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5686fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5687fcf5ef2aSThomas Huth } 5688efe843d8SDavid Gibson } 5689fcf5ef2aSThomas Huth 5690fcf5ef2aSThomas Huth /* srlq */ 5691fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5692fcf5ef2aSThomas Huth { 5693fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5694fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5695fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5696fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5697fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5698fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5699fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5700fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5701fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5702fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5703fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5704fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5705fcf5ef2aSThomas Huth tcg_gen_br(l2); 5706fcf5ef2aSThomas Huth gen_set_label(l1); 5707fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5708fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5709fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5710fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5711fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5712fcf5ef2aSThomas Huth gen_set_label(l2); 5713fcf5ef2aSThomas Huth tcg_temp_free(t0); 5714fcf5ef2aSThomas Huth tcg_temp_free(t1); 5715fcf5ef2aSThomas Huth tcg_temp_free(t2); 5716efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5717fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5718fcf5ef2aSThomas Huth } 5719efe843d8SDavid Gibson } 5720fcf5ef2aSThomas Huth 5721fcf5ef2aSThomas Huth /* srq */ 5722fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5723fcf5ef2aSThomas Huth { 5724fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5725fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5726fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5727fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5728fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5729fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5730fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5731fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5732fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5733fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5734fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5735fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5736fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5737fcf5ef2aSThomas Huth gen_set_label(l1); 5738fcf5ef2aSThomas Huth tcg_temp_free(t0); 5739fcf5ef2aSThomas Huth tcg_temp_free(t1); 5740efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5741fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5742fcf5ef2aSThomas Huth } 5743efe843d8SDavid Gibson } 5744fcf5ef2aSThomas Huth 5745fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5746fcf5ef2aSThomas Huth 5747fcf5ef2aSThomas Huth /* dsa */ 5748fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5749fcf5ef2aSThomas Huth { 5750fcf5ef2aSThomas Huth /* XXX: TODO */ 5751fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5752fcf5ef2aSThomas Huth } 5753fcf5ef2aSThomas Huth 5754fcf5ef2aSThomas Huth /* esa */ 5755fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5756fcf5ef2aSThomas Huth { 5757fcf5ef2aSThomas Huth /* XXX: TODO */ 5758fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5759fcf5ef2aSThomas Huth } 5760fcf5ef2aSThomas Huth 5761fcf5ef2aSThomas Huth /* mfrom */ 5762fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5763fcf5ef2aSThomas Huth { 5764fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5765fcf5ef2aSThomas Huth GEN_PRIV; 5766fcf5ef2aSThomas Huth #else 5767fcf5ef2aSThomas Huth CHK_SV; 5768fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5769fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5770fcf5ef2aSThomas Huth } 5771fcf5ef2aSThomas Huth 5772fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5773fcf5ef2aSThomas Huth 5774fcf5ef2aSThomas Huth /* tlbld */ 5775fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5776fcf5ef2aSThomas Huth { 5777fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5778fcf5ef2aSThomas Huth GEN_PRIV; 5779fcf5ef2aSThomas Huth #else 5780fcf5ef2aSThomas Huth CHK_SV; 5781fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5782fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5783fcf5ef2aSThomas Huth } 5784fcf5ef2aSThomas Huth 5785fcf5ef2aSThomas Huth /* tlbli */ 5786fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5787fcf5ef2aSThomas Huth { 5788fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5789fcf5ef2aSThomas Huth GEN_PRIV; 5790fcf5ef2aSThomas Huth #else 5791fcf5ef2aSThomas Huth CHK_SV; 5792fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5793fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5794fcf5ef2aSThomas Huth } 5795fcf5ef2aSThomas Huth 5796fcf5ef2aSThomas Huth /* 74xx TLB management */ 5797fcf5ef2aSThomas Huth 5798fcf5ef2aSThomas Huth /* tlbld */ 5799fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5800fcf5ef2aSThomas Huth { 5801fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5802fcf5ef2aSThomas Huth GEN_PRIV; 5803fcf5ef2aSThomas Huth #else 5804fcf5ef2aSThomas Huth CHK_SV; 5805fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5806fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5807fcf5ef2aSThomas Huth } 5808fcf5ef2aSThomas Huth 5809fcf5ef2aSThomas Huth /* tlbli */ 5810fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5811fcf5ef2aSThomas Huth { 5812fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5813fcf5ef2aSThomas Huth GEN_PRIV; 5814fcf5ef2aSThomas Huth #else 5815fcf5ef2aSThomas Huth CHK_SV; 5816fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5817fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5818fcf5ef2aSThomas Huth } 5819fcf5ef2aSThomas Huth 5820fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5821fcf5ef2aSThomas Huth 5822fcf5ef2aSThomas Huth /* clf */ 5823fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5824fcf5ef2aSThomas Huth { 5825fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5826fcf5ef2aSThomas Huth } 5827fcf5ef2aSThomas Huth 5828fcf5ef2aSThomas Huth /* cli */ 5829fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5830fcf5ef2aSThomas Huth { 5831fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5832fcf5ef2aSThomas Huth GEN_PRIV; 5833fcf5ef2aSThomas Huth #else 5834fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5835fcf5ef2aSThomas Huth CHK_SV; 5836fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5837fcf5ef2aSThomas Huth } 5838fcf5ef2aSThomas Huth 5839fcf5ef2aSThomas Huth /* dclst */ 5840fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5841fcf5ef2aSThomas Huth { 5842fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5843fcf5ef2aSThomas Huth } 5844fcf5ef2aSThomas Huth 5845fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5846fcf5ef2aSThomas Huth { 5847fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5848fcf5ef2aSThomas Huth GEN_PRIV; 5849fcf5ef2aSThomas Huth #else 5850fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5851fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5852fcf5ef2aSThomas Huth TCGv t0; 5853fcf5ef2aSThomas Huth 5854fcf5ef2aSThomas Huth CHK_SV; 5855fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5856fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5857e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 5858fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5859fcf5ef2aSThomas Huth tcg_temp_free(t0); 5860efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 5861fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5862efe843d8SDavid Gibson } 5863fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5864fcf5ef2aSThomas Huth } 5865fcf5ef2aSThomas Huth 5866fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5867fcf5ef2aSThomas Huth { 5868fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5869fcf5ef2aSThomas Huth GEN_PRIV; 5870fcf5ef2aSThomas Huth #else 5871fcf5ef2aSThomas Huth TCGv t0; 5872fcf5ef2aSThomas Huth 5873fcf5ef2aSThomas Huth CHK_SV; 5874fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5875fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5876fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5877fcf5ef2aSThomas Huth tcg_temp_free(t0); 5878fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5879fcf5ef2aSThomas Huth } 5880fcf5ef2aSThomas Huth 5881fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5882fcf5ef2aSThomas Huth { 5883fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5884fcf5ef2aSThomas Huth GEN_PRIV; 5885fcf5ef2aSThomas Huth #else 5886fcf5ef2aSThomas Huth CHK_SV; 5887fcf5ef2aSThomas Huth 5888fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5889fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5890fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5891fcf5ef2aSThomas Huth } 5892fcf5ef2aSThomas Huth 5893fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5894fcf5ef2aSThomas Huth 5895fcf5ef2aSThomas Huth /* BookE specific instructions */ 5896fcf5ef2aSThomas Huth 5897fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5898fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5899fcf5ef2aSThomas Huth { 5900fcf5ef2aSThomas Huth /* XXX: TODO */ 5901fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5902fcf5ef2aSThomas Huth } 5903fcf5ef2aSThomas Huth 5904fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5905fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5906fcf5ef2aSThomas Huth { 5907fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5908fcf5ef2aSThomas Huth GEN_PRIV; 5909fcf5ef2aSThomas Huth #else 5910fcf5ef2aSThomas Huth TCGv t0; 5911fcf5ef2aSThomas Huth 5912fcf5ef2aSThomas Huth CHK_SV; 5913fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5914fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5915fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5916fcf5ef2aSThomas Huth tcg_temp_free(t0); 5917fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5918fcf5ef2aSThomas Huth } 5919fcf5ef2aSThomas Huth 5920fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5921fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5922fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5923fcf5ef2aSThomas Huth { 5924fcf5ef2aSThomas Huth TCGv t0, t1; 5925fcf5ef2aSThomas Huth 5926fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5927fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5928fcf5ef2aSThomas Huth 5929fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5930fcf5ef2aSThomas Huth case 0x05: 5931fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5932fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5933fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5934fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5935fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5936fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5937fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5938fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5939fcf5ef2aSThomas Huth break; 5940fcf5ef2aSThomas Huth case 0x04: 5941fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5942fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5943fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5944fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5945fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5946fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5947fcf5ef2aSThomas Huth break; 5948fcf5ef2aSThomas Huth case 0x01: 5949fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5950fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5951fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5952fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5953fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5954fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5955fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5956fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5957fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5958fcf5ef2aSThomas Huth break; 5959fcf5ef2aSThomas Huth case 0x00: 5960fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5961fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5962fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5963fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5964fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5965fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5966fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5967fcf5ef2aSThomas Huth break; 5968fcf5ef2aSThomas Huth case 0x0D: 5969fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5970fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5971fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5972fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5973fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5974fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5975fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5976fcf5ef2aSThomas Huth break; 5977fcf5ef2aSThomas Huth case 0x0C: 5978fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5979fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5980fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5981fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5982fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5983fcf5ef2aSThomas Huth break; 5984fcf5ef2aSThomas Huth } 5985fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5986fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5987fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5988fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5989fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5990fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5991fcf5ef2aSThomas Huth } else { 5992fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5993fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5994fcf5ef2aSThomas Huth } 5995fcf5ef2aSThomas Huth 5996fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5997fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5998fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5999fcf5ef2aSThomas Huth 6000fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6001fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6002fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6003fcf5ef2aSThomas Huth } 6004fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6005fcf5ef2aSThomas Huth /* Signed */ 6006fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6007fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6008fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6009fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6010fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6011fcf5ef2aSThomas Huth /* Saturate */ 6012fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6013fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6014fcf5ef2aSThomas Huth } 6015fcf5ef2aSThomas Huth } else { 6016fcf5ef2aSThomas Huth /* Unsigned */ 6017fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6018fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6019fcf5ef2aSThomas Huth /* Saturate */ 6020fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6021fcf5ef2aSThomas Huth } 6022fcf5ef2aSThomas Huth } 6023fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6024fcf5ef2aSThomas Huth /* Check overflow */ 6025fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6026fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6027fcf5ef2aSThomas Huth } 6028fcf5ef2aSThomas Huth gen_set_label(l1); 6029fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6030fcf5ef2aSThomas Huth } 6031fcf5ef2aSThomas Huth } else { 6032fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6033fcf5ef2aSThomas Huth } 6034fcf5ef2aSThomas Huth tcg_temp_free(t0); 6035fcf5ef2aSThomas Huth tcg_temp_free(t1); 6036fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6037fcf5ef2aSThomas Huth /* Update Rc0 */ 6038fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6039fcf5ef2aSThomas Huth } 6040fcf5ef2aSThomas Huth } 6041fcf5ef2aSThomas Huth 6042fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6043fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6044fcf5ef2aSThomas Huth { \ 6045fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6046fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6047fcf5ef2aSThomas Huth } 6048fcf5ef2aSThomas Huth 6049fcf5ef2aSThomas Huth /* macchw - macchw. */ 6050fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6051fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6052fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6053fcf5ef2aSThomas Huth /* macchws - macchws. */ 6054fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6055fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6056fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6057fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6058fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6059fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6060fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6061fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6062fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6063fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6064fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6065fcf5ef2aSThomas Huth /* machhw - machhw. */ 6066fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6067fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6068fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6069fcf5ef2aSThomas Huth /* machhws - machhws. */ 6070fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6071fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6072fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6073fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6074fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6075fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6076fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6077fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6078fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6079fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6080fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6081fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6082fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6083fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6084fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6085fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6086fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6087fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6088fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6089fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6090fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6091fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6092fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6093fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6094fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6095fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6096fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6097fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6099fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6101fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6103fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6104fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6105fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6106fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6107fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6108fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6109fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6110fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6111fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6112fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6113fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6114fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6115fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6116fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6117fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6118fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6119fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6120fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6121fcf5ef2aSThomas Huth 6122fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6124fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6126fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6128fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6130fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6132fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6134fcf5ef2aSThomas Huth 6135fcf5ef2aSThomas Huth /* mfdcr */ 6136fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6137fcf5ef2aSThomas Huth { 6138fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6139fcf5ef2aSThomas Huth GEN_PRIV; 6140fcf5ef2aSThomas Huth #else 6141fcf5ef2aSThomas Huth TCGv dcrn; 6142fcf5ef2aSThomas Huth 6143fcf5ef2aSThomas Huth CHK_SV; 6144fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6145fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6146fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6147fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6148fcf5ef2aSThomas Huth } 6149fcf5ef2aSThomas Huth 6150fcf5ef2aSThomas Huth /* mtdcr */ 6151fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6152fcf5ef2aSThomas Huth { 6153fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6154fcf5ef2aSThomas Huth GEN_PRIV; 6155fcf5ef2aSThomas Huth #else 6156fcf5ef2aSThomas Huth TCGv dcrn; 6157fcf5ef2aSThomas Huth 6158fcf5ef2aSThomas Huth CHK_SV; 6159fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6160fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6161fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6162fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6163fcf5ef2aSThomas Huth } 6164fcf5ef2aSThomas Huth 6165fcf5ef2aSThomas Huth /* mfdcrx */ 6166fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6167fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6168fcf5ef2aSThomas Huth { 6169fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6170fcf5ef2aSThomas Huth GEN_PRIV; 6171fcf5ef2aSThomas Huth #else 6172fcf5ef2aSThomas Huth CHK_SV; 6173fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6174fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6175fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6176fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6177fcf5ef2aSThomas Huth } 6178fcf5ef2aSThomas Huth 6179fcf5ef2aSThomas Huth /* mtdcrx */ 6180fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6181fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6182fcf5ef2aSThomas Huth { 6183fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6184fcf5ef2aSThomas Huth GEN_PRIV; 6185fcf5ef2aSThomas Huth #else 6186fcf5ef2aSThomas Huth CHK_SV; 6187fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6188fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6189fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6190fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6191fcf5ef2aSThomas Huth } 6192fcf5ef2aSThomas Huth 6193fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6194fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6195fcf5ef2aSThomas Huth { 6196fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6197fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6198fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6199fcf5ef2aSThomas Huth } 6200fcf5ef2aSThomas Huth 6201fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6202fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6203fcf5ef2aSThomas Huth { 6204fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6205fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6206fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6207fcf5ef2aSThomas Huth } 6208fcf5ef2aSThomas Huth 6209fcf5ef2aSThomas Huth /* dccci */ 6210fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6211fcf5ef2aSThomas Huth { 6212fcf5ef2aSThomas Huth CHK_SV; 6213fcf5ef2aSThomas Huth /* interpreted as no-op */ 6214fcf5ef2aSThomas Huth } 6215fcf5ef2aSThomas Huth 6216fcf5ef2aSThomas Huth /* dcread */ 6217fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6218fcf5ef2aSThomas Huth { 6219fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6220fcf5ef2aSThomas Huth GEN_PRIV; 6221fcf5ef2aSThomas Huth #else 6222fcf5ef2aSThomas Huth TCGv EA, val; 6223fcf5ef2aSThomas Huth 6224fcf5ef2aSThomas Huth CHK_SV; 6225fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6226fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6227fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6228fcf5ef2aSThomas Huth val = tcg_temp_new(); 6229fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6230fcf5ef2aSThomas Huth tcg_temp_free(val); 6231fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6232fcf5ef2aSThomas Huth tcg_temp_free(EA); 6233fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6234fcf5ef2aSThomas Huth } 6235fcf5ef2aSThomas Huth 6236fcf5ef2aSThomas Huth /* icbt */ 6237fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6238fcf5ef2aSThomas Huth { 6239efe843d8SDavid Gibson /* 6240efe843d8SDavid Gibson * interpreted as no-op 6241efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6242efe843d8SDavid Gibson * does not generate any exception 6243fcf5ef2aSThomas Huth */ 6244fcf5ef2aSThomas Huth } 6245fcf5ef2aSThomas Huth 6246fcf5ef2aSThomas Huth /* iccci */ 6247fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6248fcf5ef2aSThomas Huth { 6249fcf5ef2aSThomas Huth CHK_SV; 6250fcf5ef2aSThomas Huth /* interpreted as no-op */ 6251fcf5ef2aSThomas Huth } 6252fcf5ef2aSThomas Huth 6253fcf5ef2aSThomas Huth /* icread */ 6254fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6255fcf5ef2aSThomas Huth { 6256fcf5ef2aSThomas Huth CHK_SV; 6257fcf5ef2aSThomas Huth /* interpreted as no-op */ 6258fcf5ef2aSThomas Huth } 6259fcf5ef2aSThomas Huth 6260fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6261fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6262fcf5ef2aSThomas Huth { 6263fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6264fcf5ef2aSThomas Huth GEN_PRIV; 6265fcf5ef2aSThomas Huth #else 6266fcf5ef2aSThomas Huth CHK_SV; 6267fcf5ef2aSThomas Huth /* Restore CPU state */ 6268fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 6269fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6270fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6271fcf5ef2aSThomas Huth } 6272fcf5ef2aSThomas Huth 6273fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6274fcf5ef2aSThomas Huth { 6275fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6276fcf5ef2aSThomas Huth GEN_PRIV; 6277fcf5ef2aSThomas Huth #else 6278fcf5ef2aSThomas Huth CHK_SV; 6279fcf5ef2aSThomas Huth /* Restore CPU state */ 6280fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 6281fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6282fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6283fcf5ef2aSThomas Huth } 6284fcf5ef2aSThomas Huth 6285fcf5ef2aSThomas Huth /* BookE specific */ 6286fcf5ef2aSThomas Huth 6287fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6288fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6289fcf5ef2aSThomas Huth { 6290fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6291fcf5ef2aSThomas Huth GEN_PRIV; 6292fcf5ef2aSThomas Huth #else 6293fcf5ef2aSThomas Huth CHK_SV; 6294fcf5ef2aSThomas Huth /* Restore CPU state */ 6295fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 6296fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6297fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6298fcf5ef2aSThomas Huth } 6299fcf5ef2aSThomas Huth 6300fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6301fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6302fcf5ef2aSThomas Huth { 6303fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6304fcf5ef2aSThomas Huth GEN_PRIV; 6305fcf5ef2aSThomas Huth #else 6306fcf5ef2aSThomas Huth CHK_SV; 6307fcf5ef2aSThomas Huth /* Restore CPU state */ 6308fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 6309fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6310fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6311fcf5ef2aSThomas Huth } 6312fcf5ef2aSThomas Huth 6313fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6314fcf5ef2aSThomas Huth 6315fcf5ef2aSThomas Huth /* tlbre */ 6316fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6317fcf5ef2aSThomas Huth { 6318fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6319fcf5ef2aSThomas Huth GEN_PRIV; 6320fcf5ef2aSThomas Huth #else 6321fcf5ef2aSThomas Huth CHK_SV; 6322fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6323fcf5ef2aSThomas Huth case 0: 6324fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6325fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6326fcf5ef2aSThomas Huth break; 6327fcf5ef2aSThomas Huth case 1: 6328fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6329fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6330fcf5ef2aSThomas Huth break; 6331fcf5ef2aSThomas Huth default: 6332fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6333fcf5ef2aSThomas Huth break; 6334fcf5ef2aSThomas Huth } 6335fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6336fcf5ef2aSThomas Huth } 6337fcf5ef2aSThomas Huth 6338fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6339fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6340fcf5ef2aSThomas Huth { 6341fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6342fcf5ef2aSThomas Huth GEN_PRIV; 6343fcf5ef2aSThomas Huth #else 6344fcf5ef2aSThomas Huth TCGv t0; 6345fcf5ef2aSThomas Huth 6346fcf5ef2aSThomas Huth CHK_SV; 6347fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6348fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6349fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6350fcf5ef2aSThomas Huth tcg_temp_free(t0); 6351fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6352fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6353fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6354fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6355fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6356fcf5ef2aSThomas Huth gen_set_label(l1); 6357fcf5ef2aSThomas Huth } 6358fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6359fcf5ef2aSThomas Huth } 6360fcf5ef2aSThomas Huth 6361fcf5ef2aSThomas Huth /* tlbwe */ 6362fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6363fcf5ef2aSThomas Huth { 6364fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6365fcf5ef2aSThomas Huth GEN_PRIV; 6366fcf5ef2aSThomas Huth #else 6367fcf5ef2aSThomas Huth CHK_SV; 6368fcf5ef2aSThomas Huth 6369fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6370fcf5ef2aSThomas Huth case 0: 6371fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6372fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6373fcf5ef2aSThomas Huth break; 6374fcf5ef2aSThomas Huth case 1: 6375fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6376fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6377fcf5ef2aSThomas Huth break; 6378fcf5ef2aSThomas Huth default: 6379fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6380fcf5ef2aSThomas Huth break; 6381fcf5ef2aSThomas Huth } 6382fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6383fcf5ef2aSThomas Huth } 6384fcf5ef2aSThomas Huth 6385fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6386fcf5ef2aSThomas Huth 6387fcf5ef2aSThomas Huth /* tlbre */ 6388fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6389fcf5ef2aSThomas Huth { 6390fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6391fcf5ef2aSThomas Huth GEN_PRIV; 6392fcf5ef2aSThomas Huth #else 6393fcf5ef2aSThomas Huth CHK_SV; 6394fcf5ef2aSThomas Huth 6395fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6396fcf5ef2aSThomas Huth case 0: 6397fcf5ef2aSThomas Huth case 1: 6398fcf5ef2aSThomas Huth case 2: 6399fcf5ef2aSThomas Huth { 6400fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6401fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6402fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6403fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6404fcf5ef2aSThomas Huth } 6405fcf5ef2aSThomas Huth break; 6406fcf5ef2aSThomas Huth default: 6407fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6408fcf5ef2aSThomas Huth break; 6409fcf5ef2aSThomas Huth } 6410fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6411fcf5ef2aSThomas Huth } 6412fcf5ef2aSThomas Huth 6413fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6414fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6415fcf5ef2aSThomas Huth { 6416fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6417fcf5ef2aSThomas Huth GEN_PRIV; 6418fcf5ef2aSThomas Huth #else 6419fcf5ef2aSThomas Huth TCGv t0; 6420fcf5ef2aSThomas Huth 6421fcf5ef2aSThomas Huth CHK_SV; 6422fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6423fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6424fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6425fcf5ef2aSThomas Huth tcg_temp_free(t0); 6426fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6427fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6428fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6429fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6430fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6431fcf5ef2aSThomas Huth gen_set_label(l1); 6432fcf5ef2aSThomas Huth } 6433fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6434fcf5ef2aSThomas Huth } 6435fcf5ef2aSThomas Huth 6436fcf5ef2aSThomas Huth /* tlbwe */ 6437fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6438fcf5ef2aSThomas Huth { 6439fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6440fcf5ef2aSThomas Huth GEN_PRIV; 6441fcf5ef2aSThomas Huth #else 6442fcf5ef2aSThomas Huth CHK_SV; 6443fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6444fcf5ef2aSThomas Huth case 0: 6445fcf5ef2aSThomas Huth case 1: 6446fcf5ef2aSThomas Huth case 2: 6447fcf5ef2aSThomas Huth { 6448fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6449fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6450fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6451fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6452fcf5ef2aSThomas Huth } 6453fcf5ef2aSThomas Huth break; 6454fcf5ef2aSThomas Huth default: 6455fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6456fcf5ef2aSThomas Huth break; 6457fcf5ef2aSThomas Huth } 6458fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6459fcf5ef2aSThomas Huth } 6460fcf5ef2aSThomas Huth 6461fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6462fcf5ef2aSThomas Huth 6463fcf5ef2aSThomas Huth /* tlbre */ 6464fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6465fcf5ef2aSThomas Huth { 6466fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6467fcf5ef2aSThomas Huth GEN_PRIV; 6468fcf5ef2aSThomas Huth #else 6469fcf5ef2aSThomas Huth CHK_SV; 6470fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6471fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6472fcf5ef2aSThomas Huth } 6473fcf5ef2aSThomas Huth 6474fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6475fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6476fcf5ef2aSThomas Huth { 6477fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6478fcf5ef2aSThomas Huth GEN_PRIV; 6479fcf5ef2aSThomas Huth #else 6480fcf5ef2aSThomas Huth TCGv t0; 6481fcf5ef2aSThomas Huth 6482fcf5ef2aSThomas Huth CHK_SV; 6483fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6484fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6485fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6486fcf5ef2aSThomas Huth } else { 6487fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6488fcf5ef2aSThomas Huth } 6489fcf5ef2aSThomas Huth 6490fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6491fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6492fcf5ef2aSThomas Huth tcg_temp_free(t0); 6493fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6494fcf5ef2aSThomas Huth } 6495fcf5ef2aSThomas Huth 6496fcf5ef2aSThomas Huth /* tlbwe */ 6497fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6498fcf5ef2aSThomas Huth { 6499fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6500fcf5ef2aSThomas Huth GEN_PRIV; 6501fcf5ef2aSThomas Huth #else 6502fcf5ef2aSThomas Huth CHK_SV; 6503fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6504fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6505fcf5ef2aSThomas Huth } 6506fcf5ef2aSThomas Huth 6507fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6508fcf5ef2aSThomas Huth { 6509fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6510fcf5ef2aSThomas Huth GEN_PRIV; 6511fcf5ef2aSThomas Huth #else 6512fcf5ef2aSThomas Huth TCGv t0; 6513fcf5ef2aSThomas Huth 6514fcf5ef2aSThomas Huth CHK_SV; 6515fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6516fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6517fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6518fcf5ef2aSThomas Huth tcg_temp_free(t0); 6519fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6520fcf5ef2aSThomas Huth } 6521fcf5ef2aSThomas Huth 6522fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6523fcf5ef2aSThomas Huth { 6524fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6525fcf5ef2aSThomas Huth GEN_PRIV; 6526fcf5ef2aSThomas Huth #else 6527fcf5ef2aSThomas Huth TCGv t0; 6528fcf5ef2aSThomas Huth 6529fcf5ef2aSThomas Huth CHK_SV; 6530fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6531fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6532fcf5ef2aSThomas Huth 6533fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 6534fcf5ef2aSThomas Huth case 0: 6535fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6536fcf5ef2aSThomas Huth break; 6537fcf5ef2aSThomas Huth case 1: 6538fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6539fcf5ef2aSThomas Huth break; 6540fcf5ef2aSThomas Huth case 3: 6541fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6542fcf5ef2aSThomas Huth break; 6543fcf5ef2aSThomas Huth default: 6544fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6545fcf5ef2aSThomas Huth break; 6546fcf5ef2aSThomas Huth } 6547fcf5ef2aSThomas Huth 6548fcf5ef2aSThomas Huth tcg_temp_free(t0); 6549fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6550fcf5ef2aSThomas Huth } 6551fcf5ef2aSThomas Huth 6552fcf5ef2aSThomas Huth 6553fcf5ef2aSThomas Huth /* wrtee */ 6554fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6555fcf5ef2aSThomas Huth { 6556fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6557fcf5ef2aSThomas Huth GEN_PRIV; 6558fcf5ef2aSThomas Huth #else 6559fcf5ef2aSThomas Huth TCGv t0; 6560fcf5ef2aSThomas Huth 6561fcf5ef2aSThomas Huth CHK_SV; 6562fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6563fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6564fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6565fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6566fcf5ef2aSThomas Huth tcg_temp_free(t0); 6567efe843d8SDavid Gibson /* 6568efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6569efe843d8SDavid Gibson * just set msr_ee to 1 6570fcf5ef2aSThomas Huth */ 6571fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6572fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6573fcf5ef2aSThomas Huth } 6574fcf5ef2aSThomas Huth 6575fcf5ef2aSThomas Huth /* wrteei */ 6576fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6577fcf5ef2aSThomas Huth { 6578fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6579fcf5ef2aSThomas Huth GEN_PRIV; 6580fcf5ef2aSThomas Huth #else 6581fcf5ef2aSThomas Huth CHK_SV; 6582fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6583fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6584fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6585fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6586fcf5ef2aSThomas Huth } else { 6587fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6588fcf5ef2aSThomas Huth } 6589fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6590fcf5ef2aSThomas Huth } 6591fcf5ef2aSThomas Huth 6592fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6593fcf5ef2aSThomas Huth 6594fcf5ef2aSThomas Huth /* dlmzb */ 6595fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6596fcf5ef2aSThomas Huth { 6597fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6598fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6599fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6600fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6601fcf5ef2aSThomas Huth } 6602fcf5ef2aSThomas Huth 6603fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6604fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6605fcf5ef2aSThomas Huth { 6606fcf5ef2aSThomas Huth /* interpreted as no-op */ 6607fcf5ef2aSThomas Huth } 6608fcf5ef2aSThomas Huth 6609fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6610fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6611fcf5ef2aSThomas Huth { 661227a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 661327a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 661427a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 661527a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 661627a3ea7eSBALATON Zoltan } 661727a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6618fcf5ef2aSThomas Huth } 6619fcf5ef2aSThomas Huth 6620fcf5ef2aSThomas Huth /* icbt */ 6621fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6622fcf5ef2aSThomas Huth { 6623efe843d8SDavid Gibson /* 6624efe843d8SDavid Gibson * interpreted as no-op 6625efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6626efe843d8SDavid Gibson * does not generate any exception 6627fcf5ef2aSThomas Huth */ 6628fcf5ef2aSThomas Huth } 6629fcf5ef2aSThomas Huth 6630fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6631fcf5ef2aSThomas Huth 6632fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6633fcf5ef2aSThomas Huth { 6634fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6635fcf5ef2aSThomas Huth GEN_PRIV; 6636fcf5ef2aSThomas Huth #else 6637ebca5e6dSCédric Le Goater CHK_HV; 6638d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 66397af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 66407af1e7b0SCédric Le Goater } else { 6641fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 66427af1e7b0SCédric Le Goater } 6643fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6644fcf5ef2aSThomas Huth } 6645fcf5ef2aSThomas Huth 6646fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6647fcf5ef2aSThomas Huth { 6648fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6649fcf5ef2aSThomas Huth GEN_PRIV; 6650fcf5ef2aSThomas Huth #else 6651ebca5e6dSCédric Le Goater CHK_HV; 6652d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 66537af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 66547af1e7b0SCédric Le Goater } else { 6655fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 66567af1e7b0SCédric Le Goater } 6657fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6658fcf5ef2aSThomas Huth } 6659fcf5ef2aSThomas Huth 66607af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 66617af1e7b0SCédric Le Goater { 66627af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 66637af1e7b0SCédric Le Goater GEN_PRIV; 66647af1e7b0SCédric Le Goater #else 66657af1e7b0SCédric Le Goater CHK_HV; 66667af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 66677af1e7b0SCédric Le Goater /* interpreted as no-op */ 66687af1e7b0SCédric Le Goater } 6669fcf5ef2aSThomas Huth 6670fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6671fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6672fcf5ef2aSThomas Huth { 6673fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6674fcf5ef2aSThomas Huth 6675fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6676fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6677fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6678fcf5ef2aSThomas Huth } 6679fcf5ef2aSThomas Huth 6680fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6681fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6682fcf5ef2aSThomas Huth { 6683fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6684fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6685fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6686fcf5ef2aSThomas Huth 6687fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6688fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6689fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6690fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6691fcf5ef2aSThomas Huth } else { 6692fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6693fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6694fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6695fcf5ef2aSThomas Huth } 6696fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6697fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6698fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6699fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6700fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6701fcf5ef2aSThomas Huth } 6702fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6703fcf5ef2aSThomas Huth 6704fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6705fcf5ef2aSThomas Huth { 6706fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6707fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6708fcf5ef2aSThomas Huth return; 6709fcf5ef2aSThomas Huth } 6710fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6711fcf5ef2aSThomas Huth } 6712fcf5ef2aSThomas Huth 6713fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6714fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6715fcf5ef2aSThomas Huth { \ 6716fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6717fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6718fcf5ef2aSThomas Huth return; \ 6719fcf5ef2aSThomas Huth } \ 6720efe843d8SDavid Gibson /* \ 6721efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6722fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6723fcf5ef2aSThomas Huth * \ 6724fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6725fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6726fcf5ef2aSThomas Huth */ \ 6727fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6728fcf5ef2aSThomas Huth } 6729fcf5ef2aSThomas Huth 6730fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6731fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6732fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6733fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6734fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6735fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6736fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6737efe843d8SDavid Gibson 6738b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6739b8b4576eSSuraj Jitindar Singh { 6740efe843d8SDavid Gibson /* Do Nothing */ 6741b8b4576eSSuraj Jitindar Singh } 6742fcf5ef2aSThomas Huth 674380b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 674480b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 674580b8c1eeSNikunj A Dadhania { \ 6746efe843d8SDavid Gibson /* \ 6747efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6748efe843d8SDavid Gibson * implementation of the copy paste facility \ 674980b8c1eeSNikunj A Dadhania */ \ 675080b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 675180b8c1eeSNikunj A Dadhania } 675280b8c1eeSNikunj A Dadhania 675380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 675480b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 675580b8c1eeSNikunj A Dadhania 6756fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6757fcf5ef2aSThomas Huth { 6758fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6759fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6760fcf5ef2aSThomas Huth return; 6761fcf5ef2aSThomas Huth } 6762efe843d8SDavid Gibson /* 6763efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6764efe843d8SDavid Gibson * simple: 6765fcf5ef2aSThomas Huth * 6766fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6767fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6768fcf5ef2aSThomas Huth */ 6769fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6770fcf5ef2aSThomas Huth } 6771fcf5ef2aSThomas Huth 6772fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6773fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6774fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6775fcf5ef2aSThomas Huth { \ 6776fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6777fcf5ef2aSThomas Huth } 6778fcf5ef2aSThomas Huth 6779fcf5ef2aSThomas Huth #else 6780fcf5ef2aSThomas Huth 6781fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6782fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6783fcf5ef2aSThomas Huth { \ 6784fcf5ef2aSThomas Huth CHK_SV; \ 6785fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6786fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6787fcf5ef2aSThomas Huth return; \ 6788fcf5ef2aSThomas Huth } \ 6789efe843d8SDavid Gibson /* \ 6790efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6791fcf5ef2aSThomas Huth * simple: \ 6792fcf5ef2aSThomas Huth * \ 6793fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6794fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6795fcf5ef2aSThomas Huth */ \ 6796fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6797fcf5ef2aSThomas Huth } 6798fcf5ef2aSThomas Huth 6799fcf5ef2aSThomas Huth #endif 6800fcf5ef2aSThomas Huth 6801fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6802fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6803fcf5ef2aSThomas Huth 68041a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 68051a404c91SMark Cave-Ayland { 6806e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 68071a404c91SMark Cave-Ayland } 68081a404c91SMark Cave-Ayland 68091a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 68101a404c91SMark Cave-Ayland { 6811e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 68121a404c91SMark Cave-Ayland } 68131a404c91SMark Cave-Ayland 6814c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6815c4a18dbfSMark Cave-Ayland { 681637da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6817c4a18dbfSMark Cave-Ayland } 6818c4a18dbfSMark Cave-Ayland 6819c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6820c4a18dbfSMark Cave-Ayland { 682137da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6822c4a18dbfSMark Cave-Ayland } 6823c4a18dbfSMark Cave-Ayland 6824fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6825fcf5ef2aSThomas Huth 6826fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6827fcf5ef2aSThomas Huth 6828fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6829fcf5ef2aSThomas Huth 6830fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6831fcf5ef2aSThomas Huth 6832fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6833fcf5ef2aSThomas Huth 68345cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 68355cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 68365cb091a4SNikunj A Dadhania { 68375cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 68385cb091a4SNikunj A Dadhania case 0: /* lfdp */ 68395cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 68405cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 68415cb091a4SNikunj A Dadhania } 68425cb091a4SNikunj A Dadhania break; 68435cb091a4SNikunj A Dadhania case 2: /* lxsd */ 68445cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 68455cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 68465cb091a4SNikunj A Dadhania } 68475cb091a4SNikunj A Dadhania break; 68485cb091a4SNikunj A Dadhania case 3: /* lxssp */ 68495cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 68505cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 68515cb091a4SNikunj A Dadhania } 68525cb091a4SNikunj A Dadhania break; 68535cb091a4SNikunj A Dadhania } 68545cb091a4SNikunj A Dadhania return gen_invalid(ctx); 68555cb091a4SNikunj A Dadhania } 68565cb091a4SNikunj A Dadhania 6857d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6858e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6859e3001664SNikunj A Dadhania { 6860e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6861e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6862e3001664SNikunj A Dadhania case 1: /* lxv */ 6863d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6864d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6865d59ba583SNikunj A Dadhania } 6866e3001664SNikunj A Dadhania break; 6867e3001664SNikunj A Dadhania case 5: /* stxv */ 6868d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6869d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6870d59ba583SNikunj A Dadhania } 6871e3001664SNikunj A Dadhania break; 6872e3001664SNikunj A Dadhania } 6873e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6874e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6875e3001664SNikunj A Dadhania case 0: /* stfdp */ 6876e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6877e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6878e3001664SNikunj A Dadhania } 6879e3001664SNikunj A Dadhania break; 6880e3001664SNikunj A Dadhania case 2: /* stxsd */ 6881e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6882e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6883e3001664SNikunj A Dadhania } 6884e3001664SNikunj A Dadhania break; 6885e3001664SNikunj A Dadhania case 3: /* stxssp */ 6886e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6887e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6888e3001664SNikunj A Dadhania } 6889e3001664SNikunj A Dadhania break; 6890e3001664SNikunj A Dadhania } 6891e3001664SNikunj A Dadhania } 6892e3001664SNikunj A Dadhania return gen_invalid(ctx); 6893e3001664SNikunj A Dadhania } 6894e3001664SNikunj A Dadhania 6895fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6896fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6897fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6898fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6899fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6900fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6901fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6902fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6903fcf5ef2aSThomas Huth #endif 6904fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6905fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6906fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6907fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6908fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6909fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6910fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6911fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6912fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6913fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6914fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6915fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6916fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6917fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6918fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6919fcf5ef2aSThomas Huth #endif 6920fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6921fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6922fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6923fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6924fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6925fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6926fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 692780b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6928b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 692980b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6930fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6931fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6932fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6933fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6934fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6935fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6936fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6937fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6938fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6939fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6940fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6941fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6942fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6943fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6944fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6945fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6946fcf5ef2aSThomas Huth #endif 6947fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6948fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6949fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6950fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6951fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6952fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6953fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6954fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6955fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6956fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6957fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6958fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6959fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6960fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6961fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6962fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6963fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6964fcf5ef2aSThomas Huth #endif 6965fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6966fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6967fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6968fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6969fcf5ef2aSThomas Huth #endif 69705cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 69715cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6972d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6973e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6974fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6975fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6976fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6977fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6978fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6979fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6980c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6981fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6982fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6983fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6984fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6985a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6986a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6987fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6988fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6989fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6990fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6991a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6992a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6993fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6994fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6995fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6996fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6997fcf5ef2aSThomas Huth #endif 6998fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6999fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7000c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7001fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7002fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7003fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7004fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7005fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7006fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7007fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7008fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7009fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 7010cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7011fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7012fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7013fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7014fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7015fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7016fcf5ef2aSThomas Huth #endif 7017fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 7018fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7019fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7020fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7021fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7022fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7023fcf5ef2aSThomas Huth #endif 7024fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7025fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7026fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7027fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7028fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7029fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7030fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7031fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7032fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7033b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7034fcf5ef2aSThomas Huth #endif 7035fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7036fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7037fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 703850728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7039fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7040fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 704150728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7042fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 704350728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7044fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 704550728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7046fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7047fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 704850728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7049fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 705099d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7051fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7052fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 705350728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7054fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7055fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7056fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7057fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7058fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7059fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7060fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7061fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7062fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7063fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7064fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7065fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7066fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7067fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7068fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7069fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7070fcf5ef2aSThomas Huth #endif 7071fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7072efe843d8SDavid Gibson /* 7073efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7074efe843d8SDavid Gibson * different ISA versions 7075efe843d8SDavid Gibson */ 7076fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7077fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7078c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7079c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7080fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7081fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7082fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7083fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7084a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 708562d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7086fcf5ef2aSThomas Huth #endif 7087fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7088fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7089fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7090fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7091fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7092fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7093fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7094fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7095fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7096fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7097fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7098fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7099fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7100fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7101fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7102fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7103fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7104fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7105fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7106fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7107fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7108fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7109fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7110fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7111fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7112fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7113fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7114fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7115fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7116fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7117fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7118fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7119fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7120fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7121fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7122fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7123fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7124fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7125fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7126fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7127fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7128fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7129fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7130fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7131fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7132fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7133fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7134fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7135fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7136fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7137fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7138fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7139fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7140fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7141fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7142fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7143fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7144fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7145fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7146fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7147fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7148fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7149fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7150fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7151fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7152fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7153fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7154fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7155fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7156fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7157fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7158fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7159fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7160fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7161fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7162fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7163fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7164fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7165fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7166fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7167fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7168fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7169fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7170fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7171fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7172fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7173fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7174fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7175fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7176fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7177fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7178fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7179fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7180fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 71817af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 71827af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7183fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7184fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7185fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7186fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7187fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 718827a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7189fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7190fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 71910c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 71920c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7193fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7194fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7195fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7196fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7197fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7198fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7199fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7200fcf5ef2aSThomas Huth PPC2_ISA300), 7201fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7202fcf5ef2aSThomas Huth #endif 7203fcf5ef2aSThomas Huth 7204fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7205fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7206fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7207fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7208fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7209fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7210fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7211fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7212fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7213fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7214fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7215fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7216fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7217fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7218fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 72194c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7220fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7221fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7222fcf5ef2aSThomas Huth 7223fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7224fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7225fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7226fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7227fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7228fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7229fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7230fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7231fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7232fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7233fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7234fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7235fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7236fcf5ef2aSThomas Huth 7237fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7238fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7239fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7240fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7241fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7242fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7243fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7244fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7245fcf5ef2aSThomas Huth 7246fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7247fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7248fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7249fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7250fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7251fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7252fcf5ef2aSThomas Huth 7253fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7254fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7255fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7256fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7257fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7258fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7259fcf5ef2aSThomas Huth #endif 7260fcf5ef2aSThomas Huth 7261fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7262fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7263fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7264fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7265fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7266fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7267fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7268fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7269fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7270fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7271fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7272fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7273fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7274fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7275fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7276fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7277fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7278fcf5ef2aSThomas Huth 7279fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7280fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7281fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7282fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7283fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7284fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7285fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7286fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7287fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7288fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7289fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7290fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7291fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7292fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7293fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7294fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7295fcf5ef2aSThomas Huth #endif 7296fcf5ef2aSThomas Huth 7297fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7298fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7299fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7300fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7301fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7302fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7303fcf5ef2aSThomas Huth PPC_64B) 7304fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7305fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7306fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7307fcf5ef2aSThomas Huth PPC_64B), \ 7308fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7309fcf5ef2aSThomas Huth PPC_64B), \ 7310fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7311fcf5ef2aSThomas Huth PPC_64B) 7312fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7313fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7314fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7315fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7316fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7317fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7318fcf5ef2aSThomas Huth #endif 7319fcf5ef2aSThomas Huth 7320fcf5ef2aSThomas Huth #undef GEN_LD 7321fcf5ef2aSThomas Huth #undef GEN_LDU 7322fcf5ef2aSThomas Huth #undef GEN_LDUX 7323fcf5ef2aSThomas Huth #undef GEN_LDX_E 7324fcf5ef2aSThomas Huth #undef GEN_LDS 7325fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 7326fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7327fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 7328fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7329fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7330fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7331fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7332fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7333fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 7334fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 7335fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 7336fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7337fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7338fcf5ef2aSThomas Huth 7339fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7340fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7341fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7342fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7343fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7344fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7345fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7346fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7347fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7348fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7349fcf5ef2aSThomas Huth 7350fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7351fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7352fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7353fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7354fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7355fcf5ef2aSThomas Huth #endif 7356fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7357fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7358fcf5ef2aSThomas Huth 735950728199SRoman Kapl /* External PID based load */ 736050728199SRoman Kapl #undef GEN_LDEPX 736150728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 736250728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 736350728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 736450728199SRoman Kapl 736550728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 736650728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 736750728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 736850728199SRoman Kapl #if defined(TARGET_PPC64) 736950728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 737050728199SRoman Kapl #endif 737150728199SRoman Kapl 7372fcf5ef2aSThomas Huth #undef GEN_ST 7373fcf5ef2aSThomas Huth #undef GEN_STU 7374fcf5ef2aSThomas Huth #undef GEN_STUX 7375fcf5ef2aSThomas Huth #undef GEN_STX_E 7376fcf5ef2aSThomas Huth #undef GEN_STS 7377fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 7378fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7379fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 7380fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7381fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 7382fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7383fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 73840123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7385fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 7386fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 7387fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 7388fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7389fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 7390fcf5ef2aSThomas Huth 7391fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7392fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7393fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7394fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7395fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7396fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7397fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7398fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7399fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7400fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7401fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7402fcf5ef2aSThomas Huth #endif 7403fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7404fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7405fcf5ef2aSThomas Huth 740650728199SRoman Kapl #undef GEN_STEPX 740750728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 740850728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 740950728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 741050728199SRoman Kapl 741150728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 741250728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 741350728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 741450728199SRoman Kapl #if defined(TARGET_PPC64) 741550728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 741650728199SRoman Kapl #endif 741750728199SRoman Kapl 7418fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7419fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7420fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7421fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7422fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7423fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7424fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7425fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7426fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7427fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7428fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7429fcf5ef2aSThomas Huth 7430fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7431fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7432fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7433fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7434fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7435fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7436fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7437fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7438fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7439fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7440fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7441fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7442fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7443fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7444fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7445fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7446fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7447fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7448fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7449fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7450fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7451fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7452fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7453fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7454fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7455fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7456fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7457fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7458fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7459fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7460fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7461fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7462fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7463fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7464fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7465fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7466fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7467fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7468fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7469fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7470fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7471fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7472fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7473fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7474fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7475fcf5ef2aSThomas Huth 7476fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7477fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7478fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7479fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7480fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7481fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7482fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7483fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7484fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7485fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7486fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7487fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7488fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7489fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7490fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7491fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7492fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7493fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7494fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7495fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7496fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7497fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7498fcf5ef2aSThomas Huth 7499fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 7500fcf5ef2aSThomas Huth 7501fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 7502fcf5ef2aSThomas Huth 7503fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 7504fcf5ef2aSThomas Huth 7505fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 7506fcf5ef2aSThomas Huth 7507fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 7508fcf5ef2aSThomas Huth }; 7509fcf5ef2aSThomas Huth 7510fcf5ef2aSThomas Huth #include "helper_regs.h" 75115b27a92dSPaolo Bonzini #include "translate_init.inc.c" 7512fcf5ef2aSThomas Huth 7513fcf5ef2aSThomas Huth /*****************************************************************************/ 7514fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 751590c84c56SMarkus Armbruster void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7516fcf5ef2aSThomas Huth { 7517fcf5ef2aSThomas Huth #define RGPL 4 7518fcf5ef2aSThomas Huth #define RFPL 4 7519fcf5ef2aSThomas Huth 7520fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7521fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 7522fcf5ef2aSThomas Huth int i; 7523fcf5ef2aSThomas Huth 752490c84c56SMarkus Armbruster qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7525fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7526fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 7527fcf5ef2aSThomas Huth cs->cpu_index); 752890c84c56SMarkus Armbruster qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7529fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 7530fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 7531fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 7532fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 753390c84c56SMarkus Armbruster qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7534fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7535a8dafa52SSuraj Jitindar Singh " DECR " TARGET_FMT_lu 7536fcf5ef2aSThomas Huth #endif 7537fcf5ef2aSThomas Huth "\n", 7538fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7539fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7540fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 7541fcf5ef2aSThomas Huth #endif 7542fcf5ef2aSThomas Huth ); 7543fcf5ef2aSThomas Huth #endif 7544fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7545efe843d8SDavid Gibson if ((i & (RGPL - 1)) == 0) { 754690c84c56SMarkus Armbruster qemu_fprintf(f, "GPR%02d", i); 7547efe843d8SDavid Gibson } 754890c84c56SMarkus Armbruster qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7549efe843d8SDavid Gibson if ((i & (RGPL - 1)) == (RGPL - 1)) { 755090c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 7551fcf5ef2aSThomas Huth } 7552efe843d8SDavid Gibson } 755390c84c56SMarkus Armbruster qemu_fprintf(f, "CR "); 7554fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 755590c84c56SMarkus Armbruster qemu_fprintf(f, "%01x", env->crf[i]); 755690c84c56SMarkus Armbruster qemu_fprintf(f, " ["); 7557fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 7558fcf5ef2aSThomas Huth char a = '-'; 7559efe843d8SDavid Gibson if (env->crf[i] & 0x08) { 7560fcf5ef2aSThomas Huth a = 'L'; 7561efe843d8SDavid Gibson } else if (env->crf[i] & 0x04) { 7562fcf5ef2aSThomas Huth a = 'G'; 7563efe843d8SDavid Gibson } else if (env->crf[i] & 0x02) { 7564fcf5ef2aSThomas Huth a = 'E'; 7565efe843d8SDavid Gibson } 756690c84c56SMarkus Armbruster qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7567fcf5ef2aSThomas Huth } 756890c84c56SMarkus Armbruster qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7569fcf5ef2aSThomas Huth env->reserve_addr); 7570685f1ce2SRichard Henderson 7571685f1ce2SRichard Henderson if (flags & CPU_DUMP_FPU) { 7572fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7573685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == 0) { 757490c84c56SMarkus Armbruster qemu_fprintf(f, "FPR%02d", i); 7575685f1ce2SRichard Henderson } 757690c84c56SMarkus Armbruster qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7577685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == (RFPL - 1)) { 757890c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 7579fcf5ef2aSThomas Huth } 7580685f1ce2SRichard Henderson } 758190c84c56SMarkus Armbruster qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7582685f1ce2SRichard Henderson } 7583685f1ce2SRichard Henderson 7584fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 758590c84c56SMarkus Armbruster qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7586fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7587fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7588fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7589fcf5ef2aSThomas Huth 759090c84c56SMarkus Armbruster qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7591fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7592fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7593fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7594fcf5ef2aSThomas Huth 759590c84c56SMarkus Armbruster qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7596fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7597fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7598fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7599fcf5ef2aSThomas Huth 7600fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7601fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7602a790e82bSBenjamin Herrenschmidt env->excp_model == POWERPC_EXCP_POWER8 || 7603a790e82bSBenjamin Herrenschmidt env->excp_model == POWERPC_EXCP_POWER9) { 760490c84c56SMarkus Armbruster qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7605fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7606fcf5ef2aSThomas Huth } 7607fcf5ef2aSThomas Huth #endif 7608fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 760990c84c56SMarkus Armbruster qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7610fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7611fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7612fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7613fcf5ef2aSThomas Huth 761490c84c56SMarkus Armbruster qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7615fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7616fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7617fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7618fcf5ef2aSThomas Huth 761990c84c56SMarkus Armbruster qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7620fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7621fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7622fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7623fcf5ef2aSThomas Huth 762490c84c56SMarkus Armbruster qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7625fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7626fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7627fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7628fcf5ef2aSThomas Huth 7629fcf5ef2aSThomas Huth /* FSL-specific */ 763090c84c56SMarkus Armbruster qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7631fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7632fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7633fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7634fcf5ef2aSThomas Huth 7635fcf5ef2aSThomas Huth /* 7636fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7637fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7638fcf5ef2aSThomas Huth */ 7639fcf5ef2aSThomas Huth } 7640fcf5ef2aSThomas Huth 7641fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7642fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 764390c84c56SMarkus Armbruster qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7644fcf5ef2aSThomas Huth } 7645fcf5ef2aSThomas Huth #endif 7646fcf5ef2aSThomas Huth 7647efe843d8SDavid Gibson if (env->spr_cb[SPR_LPCR].name) { 764890c84c56SMarkus Armbruster qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7649efe843d8SDavid Gibson } 7650d801a61eSSuraj Jitindar Singh 76510941d728SDavid Gibson switch (env->mmu_model) { 7652fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7653fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7654fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7655fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7656fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 76570941d728SDavid Gibson case POWERPC_MMU_64B: 76580941d728SDavid Gibson case POWERPC_MMU_2_03: 76590941d728SDavid Gibson case POWERPC_MMU_2_06: 76600941d728SDavid Gibson case POWERPC_MMU_2_07: 76610941d728SDavid Gibson case POWERPC_MMU_3_00: 7662fcf5ef2aSThomas Huth #endif 76634f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 766490c84c56SMarkus Armbruster qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 76654f4f28ffSSuraj Jitindar Singh } 76664a7518e0SCédric Le Goater if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 766790c84c56SMarkus Armbruster qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 76684a7518e0SCédric Le Goater } 766990c84c56SMarkus Armbruster qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7670fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7671fcf5ef2aSThomas Huth break; 7672fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 767390c84c56SMarkus Armbruster qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7674fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7675fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7676fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7677fcf5ef2aSThomas Huth 767890c84c56SMarkus Armbruster qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7679fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7680fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7681fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7682fcf5ef2aSThomas Huth 768390c84c56SMarkus Armbruster qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7684fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7685fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7686fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7687fcf5ef2aSThomas Huth break; 7688fcf5ef2aSThomas Huth default: 7689fcf5ef2aSThomas Huth break; 7690fcf5ef2aSThomas Huth } 7691fcf5ef2aSThomas Huth #endif 7692fcf5ef2aSThomas Huth 7693fcf5ef2aSThomas Huth #undef RGPL 7694fcf5ef2aSThomas Huth #undef RFPL 7695fcf5ef2aSThomas Huth } 7696fcf5ef2aSThomas Huth 769711cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 7698fcf5ef2aSThomas Huth { 7699fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7700fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7701fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7702fcf5ef2aSThomas Huth int op1, op2, op3; 7703fcf5ef2aSThomas Huth 7704fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7705fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7706fcf5ef2aSThomas Huth handler = t1[op1]; 7707fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7708fcf5ef2aSThomas Huth t2 = ind_table(handler); 7709fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7710fcf5ef2aSThomas Huth handler = t2[op2]; 7711fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7712fcf5ef2aSThomas Huth t3 = ind_table(handler); 7713fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7714fcf5ef2aSThomas Huth handler = t3[op3]; 7715efe843d8SDavid Gibson if (handler->count == 0) { 7716fcf5ef2aSThomas Huth continue; 7717efe843d8SDavid Gibson } 771811cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 7719fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7720fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7721fcf5ef2aSThomas Huth handler->oname, 7722fcf5ef2aSThomas Huth handler->count, handler->count); 7723fcf5ef2aSThomas Huth } 7724fcf5ef2aSThomas Huth } else { 7725efe843d8SDavid Gibson if (handler->count == 0) { 7726fcf5ef2aSThomas Huth continue; 7727efe843d8SDavid Gibson } 772811cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 7729fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7730fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7731fcf5ef2aSThomas Huth handler->count, handler->count); 7732fcf5ef2aSThomas Huth } 7733fcf5ef2aSThomas Huth } 7734fcf5ef2aSThomas Huth } else { 7735efe843d8SDavid Gibson if (handler->count == 0) { 7736fcf5ef2aSThomas Huth continue; 7737efe843d8SDavid Gibson } 773811cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 7739fcf5ef2aSThomas Huth " %" PRId64 "\n", 7740fcf5ef2aSThomas Huth op1, op1, handler->oname, 7741fcf5ef2aSThomas Huth handler->count, handler->count); 7742fcf5ef2aSThomas Huth } 7743fcf5ef2aSThomas Huth } 7744fcf5ef2aSThomas Huth #endif 7745fcf5ef2aSThomas Huth } 7746fcf5ef2aSThomas Huth 7747b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7748fcf5ef2aSThomas Huth { 7749b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 77509c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 7751b0c2d521SEmilio G. Cota int bound; 7752fcf5ef2aSThomas Huth 7753b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 7754b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 7755b0c2d521SEmilio G. Cota ctx->pr = msr_pr; 7756b0c2d521SEmilio G. Cota ctx->mem_idx = env->dmmu_idx; 7757b0c2d521SEmilio G. Cota ctx->dr = msr_dr; 7758fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7759b0c2d521SEmilio G. Cota ctx->hv = msr_hv || !env->has_hv_mode; 7760fcf5ef2aSThomas Huth #endif 7761b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7762b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7763b0c2d521SEmilio G. Cota ctx->access_type = -1; 7764b0c2d521SEmilio G. Cota ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7765b0c2d521SEmilio G. Cota ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7766b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 77670e3bf489SRoman Kapl ctx->flags = env->flags; 7768fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7769b0c2d521SEmilio G. Cota ctx->sf_mode = msr_is_64bit(env, env->msr); 7770b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7771fcf5ef2aSThomas Huth #endif 7772e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7773e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 7774e69ba2b4SDavid Gibson || (env->mmu_model & POWERPC_MMU_64B); 7775fcf5ef2aSThomas Huth 7776b0c2d521SEmilio G. Cota ctx->fpu_enabled = !!msr_fp; 7777efe843d8SDavid Gibson if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { 7778b0c2d521SEmilio G. Cota ctx->spe_enabled = !!msr_spe; 7779efe843d8SDavid Gibson } else { 7780b0c2d521SEmilio G. Cota ctx->spe_enabled = false; 7781efe843d8SDavid Gibson } 7782efe843d8SDavid Gibson if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { 7783b0c2d521SEmilio G. Cota ctx->altivec_enabled = !!msr_vr; 7784efe843d8SDavid Gibson } else { 7785b0c2d521SEmilio G. Cota ctx->altivec_enabled = false; 7786efe843d8SDavid Gibson } 7787fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7788b0c2d521SEmilio G. Cota ctx->vsx_enabled = !!msr_vsx; 7789fcf5ef2aSThomas Huth } else { 7790b0c2d521SEmilio G. Cota ctx->vsx_enabled = false; 7791fcf5ef2aSThomas Huth } 7792fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7793fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7794b0c2d521SEmilio G. Cota ctx->tm_enabled = !!msr_tm; 7795fcf5ef2aSThomas Huth } else { 7796b0c2d521SEmilio G. Cota ctx->tm_enabled = false; 7797fcf5ef2aSThomas Huth } 7798fcf5ef2aSThomas Huth #endif 7799b0c2d521SEmilio G. Cota ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7800efe843d8SDavid Gibson if ((env->flags & POWERPC_FLAG_SE) && msr_se) { 7801b0c2d521SEmilio G. Cota ctx->singlestep_enabled = CPU_SINGLE_STEP; 7802efe843d8SDavid Gibson } else { 7803b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 7804efe843d8SDavid Gibson } 7805efe843d8SDavid Gibson if ((env->flags & POWERPC_FLAG_BE) && msr_be) { 7806b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7807efe843d8SDavid Gibson } 78080e3bf489SRoman Kapl if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 78090e3bf489SRoman Kapl ctx->singlestep_enabled = 0; 78100e3bf489SRoman Kapl target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 78110e3bf489SRoman Kapl if (dbcr0 & DBCR0_ICMP) { 78120e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_SINGLE_STEP; 78130e3bf489SRoman Kapl } 78140e3bf489SRoman Kapl if (dbcr0 & DBCR0_BRT) { 78150e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_BRANCH_STEP; 78160e3bf489SRoman Kapl } 78170e3bf489SRoman Kapl 78180e3bf489SRoman Kapl } 7819b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7820b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7821fcf5ef2aSThomas Huth } 7822fcf5ef2aSThomas Huth #if defined(DO_SINGLE_STEP) && 0 7823fcf5ef2aSThomas Huth /* Single step trace mode */ 7824fcf5ef2aSThomas Huth msr_se = 1; 7825fcf5ef2aSThomas Huth #endif 7826b0c2d521SEmilio G. Cota 7827b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7828b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7829fcf5ef2aSThomas Huth } 7830fcf5ef2aSThomas Huth 7831b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7832b0c2d521SEmilio G. Cota { 7833b0c2d521SEmilio G. Cota } 7834fcf5ef2aSThomas Huth 7835b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7836b0c2d521SEmilio G. Cota { 7837b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7838b0c2d521SEmilio G. Cota } 7839b0c2d521SEmilio G. Cota 7840b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7841b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 7842b0c2d521SEmilio G. Cota { 7843b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7844b0c2d521SEmilio G. Cota 7845b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 78462a8ceefcSEmilio G. Cota dcbase->is_jmp = DISAS_NORETURN; 7847efe843d8SDavid Gibson /* 7848efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 7849efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 7850efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 7851efe843d8SDavid Gibson * setting tb->size below does the right thing. 7852efe843d8SDavid Gibson */ 7853b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7854b0c2d521SEmilio G. Cota return true; 7855fcf5ef2aSThomas Huth } 7856fcf5ef2aSThomas Huth 7857b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7858b0c2d521SEmilio G. Cota { 7859b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7860b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 7861b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 7862b0c2d521SEmilio G. Cota 7863fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7864fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7865b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7866b0c2d521SEmilio G. Cota 7867b0c2d521SEmilio G. Cota if (unlikely(need_byteswap(ctx))) { 7868b0c2d521SEmilio G. Cota ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); 7869fcf5ef2aSThomas Huth } else { 7870b0c2d521SEmilio G. Cota ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); 7871fcf5ef2aSThomas Huth } 7872fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7873b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7874b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7875b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 7876b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7877fcf5ef2aSThomas Huth table = env->opcodes; 7878b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 7879fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7880fcf5ef2aSThomas Huth table = ind_table(handler); 7881b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 7882fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7883fcf5ef2aSThomas Huth table = ind_table(handler); 7884b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 7885fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7886fcf5ef2aSThomas Huth table = ind_table(handler); 7887b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 7888fcf5ef2aSThomas Huth } 7889fcf5ef2aSThomas Huth } 7890fcf5ef2aSThomas Huth } 7891fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7892fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7893fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7894fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7895fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7896b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7897b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7898b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7899fcf5ef2aSThomas Huth } else { 7900fcf5ef2aSThomas Huth uint32_t inval; 7901fcf5ef2aSThomas Huth 7902b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7903b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 7904fcf5ef2aSThomas Huth inval = handler->inval2; 7905fcf5ef2aSThomas Huth } else { 7906fcf5ef2aSThomas Huth inval = handler->inval1; 7907fcf5ef2aSThomas Huth } 7908fcf5ef2aSThomas Huth 7909b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 7910fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7911fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7912b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 7913b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7914b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7915b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4); 7916b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7917b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 7918b0c2d521SEmilio G. Cota return; 7919fcf5ef2aSThomas Huth } 7920fcf5ef2aSThomas Huth } 7921b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 7922fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7923fcf5ef2aSThomas Huth handler->count++; 7924fcf5ef2aSThomas Huth #endif 7925fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7926b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7927b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7928b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 7929b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 7930b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 7931e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 79320e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 7933fcf5ef2aSThomas Huth } 7934b0c2d521SEmilio G. Cota 7935fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7936b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7937b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7938b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7939fcf5ef2aSThomas Huth } 7940b0c2d521SEmilio G. Cota 7941b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7942b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 7943fcf5ef2aSThomas Huth } 7944b0c2d521SEmilio G. Cota 7945b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7946b0c2d521SEmilio G. Cota { 7947b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7948b0c2d521SEmilio G. Cota 7949b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 7950b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 7951b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7952b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7953b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 7954fcf5ef2aSThomas Huth } 7955fcf5ef2aSThomas Huth /* Generate the return instruction */ 795607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7957fcf5ef2aSThomas Huth } 7958fcf5ef2aSThomas Huth } 7959b0c2d521SEmilio G. Cota 7960b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7961b0c2d521SEmilio G. Cota { 7962b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7963b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7964b0c2d521SEmilio G. Cota } 7965b0c2d521SEmilio G. Cota 7966b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7967b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7968b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7969b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7970b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 7971b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7972b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7973b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7974b0c2d521SEmilio G. Cota }; 7975b0c2d521SEmilio G. Cota 79768b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 7977b0c2d521SEmilio G. Cota { 7978b0c2d521SEmilio G. Cota DisasContext ctx; 7979b0c2d521SEmilio G. Cota 79808b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 7981fcf5ef2aSThomas Huth } 7982fcf5ef2aSThomas Huth 7983fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7984fcf5ef2aSThomas Huth target_ulong *data) 7985fcf5ef2aSThomas Huth { 7986fcf5ef2aSThomas Huth env->nip = data[0]; 7987fcf5ef2aSThomas Huth } 7988