1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char *p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 125fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 131fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 133fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 135fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 137dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 139dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 143fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 144fcf5ef2aSThomas Huth "reserve_addr"); 145253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 146253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 147253ce7b2SNikunj A Dadhania "reserve_val"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 150fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 153efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 154efe843d8SDavid Gibson "access_type"); 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth /* internal defines */ 158fcf5ef2aSThomas Huth struct DisasContext { 159b6bac4bcSEmilio G. Cota DisasContextBase base; 1602c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 161fcf5ef2aSThomas Huth uint32_t opcode; 162fcf5ef2aSThomas Huth /* Routine used to access memory */ 163fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 164fcf5ef2aSThomas Huth bool lazy_tlb_flush; 165fcf5ef2aSThomas Huth bool need_access_type; 166fcf5ef2aSThomas Huth int mem_idx; 167fcf5ef2aSThomas Huth int access_type; 168fcf5ef2aSThomas Huth /* Translation flags */ 16914776ab5STony Nguyen MemOp default_tcg_memop_mask; 170fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 171fcf5ef2aSThomas Huth bool sf_mode; 172fcf5ef2aSThomas Huth bool has_cfar; 173fcf5ef2aSThomas Huth #endif 174fcf5ef2aSThomas Huth bool fpu_enabled; 175fcf5ef2aSThomas Huth bool altivec_enabled; 176fcf5ef2aSThomas Huth bool vsx_enabled; 177fcf5ef2aSThomas Huth bool spe_enabled; 178fcf5ef2aSThomas Huth bool tm_enabled; 179c6fd28fdSSuraj Jitindar Singh bool gtse; 180fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 181fcf5ef2aSThomas Huth int singlestep_enabled; 1820e3bf489SRoman Kapl uint32_t flags; 183fcf5ef2aSThomas Huth uint64_t insns_flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags2; 185fcf5ef2aSThomas Huth }; 186fcf5ef2aSThomas Huth 187a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 188a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 189a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 190a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 191a9b5b3d0SRichard Henderson 192fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 193fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 194fcf5ef2aSThomas Huth { 195fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 196fcf5ef2aSThomas Huth return ctx->le_mode; 197fcf5ef2aSThomas Huth #else 198fcf5ef2aSThomas Huth return !ctx->le_mode; 199fcf5ef2aSThomas Huth #endif 200fcf5ef2aSThomas Huth } 201fcf5ef2aSThomas Huth 202fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 203fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 204fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 205fcf5ef2aSThomas Huth #else 206fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 207fcf5ef2aSThomas Huth #endif 208fcf5ef2aSThomas Huth 209fcf5ef2aSThomas Huth struct opc_handler_t { 210fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 211fcf5ef2aSThomas Huth uint32_t inval1; 212fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 213fcf5ef2aSThomas Huth uint32_t inval2; 214fcf5ef2aSThomas Huth /* instruction type */ 215fcf5ef2aSThomas Huth uint64_t type; 216fcf5ef2aSThomas Huth /* extended instruction type */ 217fcf5ef2aSThomas Huth uint64_t type2; 218fcf5ef2aSThomas Huth /* handler */ 219fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 220fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 221fcf5ef2aSThomas Huth const char *oname; 222fcf5ef2aSThomas Huth #endif 223fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 224fcf5ef2aSThomas Huth uint64_t count; 225fcf5ef2aSThomas Huth #endif 226fcf5ef2aSThomas Huth }; 227fcf5ef2aSThomas Huth 2280e3bf489SRoman Kapl /* SPR load/store helpers */ 2290e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2300e3bf489SRoman Kapl { 2310e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2320e3bf489SRoman Kapl } 2330e3bf489SRoman Kapl 2340e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2350e3bf489SRoman Kapl { 2360e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2370e3bf489SRoman Kapl } 2380e3bf489SRoman Kapl 239fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 240fcf5ef2aSThomas Huth { 241fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 242fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 243fcf5ef2aSThomas Huth ctx->access_type = access_type; 244fcf5ef2aSThomas Huth } 245fcf5ef2aSThomas Huth } 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 248fcf5ef2aSThomas Huth { 249fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 250fcf5ef2aSThomas Huth nip = (uint32_t)nip; 251fcf5ef2aSThomas Huth } 252fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 253fcf5ef2aSThomas Huth } 254fcf5ef2aSThomas Huth 255fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 256fcf5ef2aSThomas Huth { 257fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 258fcf5ef2aSThomas Huth 259efe843d8SDavid Gibson /* 260efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 261efe843d8SDavid Gibson * faulting instruction 262fcf5ef2aSThomas Huth */ 2632c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 264fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 265fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 266fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 267fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 268fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2693d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 270fcf5ef2aSThomas Huth } 271fcf5ef2aSThomas Huth 272fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 273fcf5ef2aSThomas Huth { 274fcf5ef2aSThomas Huth TCGv_i32 t0; 275fcf5ef2aSThomas Huth 276efe843d8SDavid Gibson /* 277efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 278efe843d8SDavid Gibson * faulting instruction 279fcf5ef2aSThomas Huth */ 2802c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 281fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 282fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 283fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2843d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 285fcf5ef2aSThomas Huth } 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 288fcf5ef2aSThomas Huth target_ulong nip) 289fcf5ef2aSThomas Huth { 290fcf5ef2aSThomas Huth TCGv_i32 t0; 291fcf5ef2aSThomas Huth 292fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 293fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 294fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 295fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2963d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 297fcf5ef2aSThomas Huth } 298fcf5ef2aSThomas Huth 299f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 300f5b6daacSRichard Henderson { 301f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 302f5b6daacSRichard Henderson gen_io_start(); 303f5b6daacSRichard Henderson /* 304f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 305f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 306f5b6daacSRichard Henderson * decide if we need to return to the main loop. 307f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 308f5b6daacSRichard Henderson */ 309f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 310f5b6daacSRichard Henderson } 311f5b6daacSRichard Henderson } 312f5b6daacSRichard Henderson 313e150ac89SRoman Kapl /* 314e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 315e150ac89SRoman Kapl * SPR registers for this exception. 316e150ac89SRoman Kapl * 317e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 318e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3190e3bf489SRoman Kapl */ 320e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3210e3bf489SRoman Kapl { 3220e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3230e3bf489SRoman Kapl target_ulong dbsr = 0; 324e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3250e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 326e150ac89SRoman Kapl } else { 327e150ac89SRoman Kapl /* Must have been branch */ 3280e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3290e3bf489SRoman Kapl } 3300e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3310e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3320e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3330e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3340e3bf489SRoman Kapl tcg_temp_free(t0); 3350e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3360e3bf489SRoman Kapl } else { 337e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3380e3bf489SRoman Kapl } 3390e3bf489SRoman Kapl } 3400e3bf489SRoman Kapl 341fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 342fcf5ef2aSThomas Huth { 3432736fc61SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 3443d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 345fcf5ef2aSThomas Huth } 346fcf5ef2aSThomas Huth 347fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 348fcf5ef2aSThomas Huth { 349fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 350fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 353fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 354fcf5ef2aSThomas Huth { 355fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 358fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 359fcf5ef2aSThomas Huth { 360fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 361fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 362fcf5ef2aSThomas Huth } 363fcf5ef2aSThomas Huth 36437f219c8SBruno Larsen (billionai) /*****************************************************************************/ 36537f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 36637f219c8SBruno Larsen (billionai) 367a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36837f219c8SBruno Larsen (billionai) { 36937f219c8SBruno Larsen (billionai) #if 0 37037f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 37137f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 37237f219c8SBruno Larsen (billionai) #endif 37337f219c8SBruno Larsen (billionai) } 37437f219c8SBruno Larsen (billionai) 37537f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 37637f219c8SBruno Larsen (billionai) 37737f219c8SBruno Larsen (billionai) /* 37837f219c8SBruno Larsen (billionai) * Generic callbacks: 37937f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 38037f219c8SBruno Larsen (billionai) */ 38137f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 38237f219c8SBruno Larsen (billionai) { 38337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 38437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 38537f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 38637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38737f219c8SBruno Larsen (billionai) #endif 38837f219c8SBruno Larsen (billionai) } 38937f219c8SBruno Larsen (billionai) 390a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 39137f219c8SBruno Larsen (billionai) { 39237f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 39337f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 39437f219c8SBruno Larsen (billionai) } 39537f219c8SBruno Larsen (billionai) 39637f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39737f219c8SBruno Larsen (billionai) { 39837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 40037f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 40137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 40237f219c8SBruno Larsen (billionai) #endif 40337f219c8SBruno Larsen (billionai) } 40437f219c8SBruno Larsen (billionai) 405a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 40637f219c8SBruno Larsen (billionai) { 40737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40837f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40937f219c8SBruno Larsen (billionai) } 41037f219c8SBruno Larsen (billionai) 41137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 412a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 41337f219c8SBruno Larsen (billionai) { 41437f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 41537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 41637f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 41737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 41837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 41937f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42037f219c8SBruno Larsen (billionai) #else 42137f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 42237f219c8SBruno Larsen (billionai) #endif 42337f219c8SBruno Larsen (billionai) } 42437f219c8SBruno Larsen (billionai) 425a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 42637f219c8SBruno Larsen (billionai) { 42737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42837f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 42937f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 43037f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 43137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 43237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 43437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 43537f219c8SBruno Larsen (billionai) } 43637f219c8SBruno Larsen (billionai) 437a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 43837f219c8SBruno Larsen (billionai) { 43937f219c8SBruno Larsen (billionai) } 44037f219c8SBruno Larsen (billionai) 44137f219c8SBruno Larsen (billionai) #endif 44237f219c8SBruno Larsen (billionai) 44337f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 44437f219c8SBruno Larsen (billionai) /* XER */ 445a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 44637f219c8SBruno Larsen (billionai) { 44737f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 44837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 45037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 45137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 45237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 45337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 45437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 45537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 45637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 45737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45837f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 45937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 46037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 46237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46337f219c8SBruno Larsen (billionai) } 46437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 46537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 46637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 46737f219c8SBruno Larsen (billionai) } 46837f219c8SBruno Larsen (billionai) 469a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 47037f219c8SBruno Larsen (billionai) { 47137f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 47237f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 47337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 47437f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 47537f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 47637f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 47737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 47837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 47937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 48037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 48137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 48237f219c8SBruno Larsen (billionai) } 48337f219c8SBruno Larsen (billionai) 48437f219c8SBruno Larsen (billionai) /* LR */ 485a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 48637f219c8SBruno Larsen (billionai) { 48737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 48837f219c8SBruno Larsen (billionai) } 48937f219c8SBruno Larsen (billionai) 490a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 49137f219c8SBruno Larsen (billionai) { 49237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 49337f219c8SBruno Larsen (billionai) } 49437f219c8SBruno Larsen (billionai) 49537f219c8SBruno Larsen (billionai) /* CFAR */ 49637f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 497a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 49837f219c8SBruno Larsen (billionai) { 49937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 50037f219c8SBruno Larsen (billionai) } 50137f219c8SBruno Larsen (billionai) 502a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 50337f219c8SBruno Larsen (billionai) { 50437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 50537f219c8SBruno Larsen (billionai) } 50637f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 50737f219c8SBruno Larsen (billionai) 50837f219c8SBruno Larsen (billionai) /* CTR */ 509a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 51037f219c8SBruno Larsen (billionai) { 51137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 51237f219c8SBruno Larsen (billionai) } 51337f219c8SBruno Larsen (billionai) 514a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 51537f219c8SBruno Larsen (billionai) { 51637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 51737f219c8SBruno Larsen (billionai) } 51837f219c8SBruno Larsen (billionai) 51937f219c8SBruno Larsen (billionai) /* User read access to SPR */ 52037f219c8SBruno Larsen (billionai) /* USPRx */ 52137f219c8SBruno Larsen (billionai) /* UMMCRx */ 52237f219c8SBruno Larsen (billionai) /* UPMCx */ 52337f219c8SBruno Larsen (billionai) /* USIA */ 52437f219c8SBruno Larsen (billionai) /* UDECR */ 525a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 52637f219c8SBruno Larsen (billionai) { 52737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 52837f219c8SBruno Larsen (billionai) } 52937f219c8SBruno Larsen (billionai) 53037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 531a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 53237f219c8SBruno Larsen (billionai) { 53337f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 53437f219c8SBruno Larsen (billionai) } 53537f219c8SBruno Larsen (billionai) #endif 53637f219c8SBruno Larsen (billionai) 53737f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 53837f219c8SBruno Larsen (billionai) /* DECR */ 53937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 540a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 54137f219c8SBruno Larsen (billionai) { 542f5b6daacSRichard Henderson gen_icount_io_start(ctx); 54337f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 54437f219c8SBruno Larsen (billionai) } 54537f219c8SBruno Larsen (billionai) 546a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 54737f219c8SBruno Larsen (billionai) { 548f5b6daacSRichard Henderson gen_icount_io_start(ctx); 54937f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 55037f219c8SBruno Larsen (billionai) } 55137f219c8SBruno Larsen (billionai) #endif 55237f219c8SBruno Larsen (billionai) 55337f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 55437f219c8SBruno Larsen (billionai) /* Time base */ 555a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 55637f219c8SBruno Larsen (billionai) { 557f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55837f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 55937f219c8SBruno Larsen (billionai) } 56037f219c8SBruno Larsen (billionai) 561a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 56237f219c8SBruno Larsen (billionai) { 563f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56437f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 56537f219c8SBruno Larsen (billionai) } 56637f219c8SBruno Larsen (billionai) 567a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 56837f219c8SBruno Larsen (billionai) { 56937f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 57037f219c8SBruno Larsen (billionai) } 57137f219c8SBruno Larsen (billionai) 572a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 57337f219c8SBruno Larsen (billionai) { 57437f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 57537f219c8SBruno Larsen (billionai) } 57637f219c8SBruno Larsen (billionai) 57737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 578a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 57937f219c8SBruno Larsen (billionai) { 580f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58137f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 58237f219c8SBruno Larsen (billionai) } 58337f219c8SBruno Larsen (billionai) 584a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 58537f219c8SBruno Larsen (billionai) { 586f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58737f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 58837f219c8SBruno Larsen (billionai) } 58937f219c8SBruno Larsen (billionai) 590a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 59137f219c8SBruno Larsen (billionai) { 59237f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 59337f219c8SBruno Larsen (billionai) } 59437f219c8SBruno Larsen (billionai) 595a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 59637f219c8SBruno Larsen (billionai) { 59737f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 59837f219c8SBruno Larsen (billionai) } 59937f219c8SBruno Larsen (billionai) 60037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 601a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 60237f219c8SBruno Larsen (billionai) { 603f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60437f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 60537f219c8SBruno Larsen (billionai) } 60637f219c8SBruno Larsen (billionai) 607a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 60837f219c8SBruno Larsen (billionai) { 609f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61037f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 61137f219c8SBruno Larsen (billionai) } 61237f219c8SBruno Larsen (billionai) 61337f219c8SBruno Larsen (billionai) /* HDECR */ 614a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 61537f219c8SBruno Larsen (billionai) { 616f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61737f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 61837f219c8SBruno Larsen (billionai) } 61937f219c8SBruno Larsen (billionai) 620a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 62137f219c8SBruno Larsen (billionai) { 622f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62337f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 62437f219c8SBruno Larsen (billionai) } 62537f219c8SBruno Larsen (billionai) 626a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 62737f219c8SBruno Larsen (billionai) { 628f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62937f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 63037f219c8SBruno Larsen (billionai) } 63137f219c8SBruno Larsen (billionai) 632a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 63337f219c8SBruno Larsen (billionai) { 634f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63537f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 63637f219c8SBruno Larsen (billionai) } 63737f219c8SBruno Larsen (billionai) 638a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 63937f219c8SBruno Larsen (billionai) { 640f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64137f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 64237f219c8SBruno Larsen (billionai) } 64337f219c8SBruno Larsen (billionai) 64437f219c8SBruno Larsen (billionai) #endif 64537f219c8SBruno Larsen (billionai) #endif 64637f219c8SBruno Larsen (billionai) 64737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 64837f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 64937f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 650a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 65137f219c8SBruno Larsen (billionai) { 65237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 65337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 65437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) 657a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 66237f219c8SBruno Larsen (billionai) } 66337f219c8SBruno Larsen (billionai) 664a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 66537f219c8SBruno Larsen (billionai) { 66637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 66737f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66937f219c8SBruno Larsen (billionai) } 67037f219c8SBruno Larsen (billionai) 671a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 67237f219c8SBruno Larsen (billionai) { 67337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 67437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 67537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67637f219c8SBruno Larsen (billionai) } 67737f219c8SBruno Larsen (billionai) 678a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 67937f219c8SBruno Larsen (billionai) { 68037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 68137f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 685a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 68637f219c8SBruno Larsen (billionai) { 68737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 68837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69037f219c8SBruno Larsen (billionai) } 69137f219c8SBruno Larsen (billionai) 69237f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 69337f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 694a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 69537f219c8SBruno Larsen (billionai) { 69637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69837f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 69937f219c8SBruno Larsen (billionai) } 70037f219c8SBruno Larsen (billionai) 701a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 70237f219c8SBruno Larsen (billionai) { 70337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70537f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) 708a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 70937f219c8SBruno Larsen (billionai) { 71037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 71137f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) 715a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 71637f219c8SBruno Larsen (billionai) { 71737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 71837f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) 722a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 72337f219c8SBruno Larsen (billionai) { 72437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 72537f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 729a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 73037f219c8SBruno Larsen (billionai) { 73137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 73237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73437f219c8SBruno Larsen (billionai) } 73537f219c8SBruno Larsen (billionai) 73637f219c8SBruno Larsen (billionai) /* SDR1 */ 737a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 73837f219c8SBruno Larsen (billionai) { 73937f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 74037f219c8SBruno Larsen (billionai) } 74137f219c8SBruno Larsen (billionai) 74237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 74337f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 74437f219c8SBruno Larsen (billionai) /* PIDR */ 745a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 74637f219c8SBruno Larsen (billionai) { 74737f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 74837f219c8SBruno Larsen (billionai) } 74937f219c8SBruno Larsen (billionai) 750a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 75137f219c8SBruno Larsen (billionai) { 75237f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 75337f219c8SBruno Larsen (billionai) } 75437f219c8SBruno Larsen (billionai) 755a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 75637f219c8SBruno Larsen (billionai) { 75737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 75837f219c8SBruno Larsen (billionai) } 75937f219c8SBruno Larsen (billionai) 760a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 76137f219c8SBruno Larsen (billionai) { 76237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 76337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 76437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 76537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 76637f219c8SBruno Larsen (billionai) } 767a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 76837f219c8SBruno Larsen (billionai) { 76937f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 772a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 77337f219c8SBruno Larsen (billionai) { 77437f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 77537f219c8SBruno Larsen (billionai) } 77637f219c8SBruno Larsen (billionai) 77737f219c8SBruno Larsen (billionai) /* DPDES */ 778a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 77937f219c8SBruno Larsen (billionai) { 78037f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 78137f219c8SBruno Larsen (billionai) } 78237f219c8SBruno Larsen (billionai) 783a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 78437f219c8SBruno Larsen (billionai) { 78537f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 78637f219c8SBruno Larsen (billionai) } 78737f219c8SBruno Larsen (billionai) #endif 78837f219c8SBruno Larsen (billionai) #endif 78937f219c8SBruno Larsen (billionai) 79037f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 79137f219c8SBruno Larsen (billionai) /* RTC */ 792a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 79337f219c8SBruno Larsen (billionai) { 79437f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 79537f219c8SBruno Larsen (billionai) } 79637f219c8SBruno Larsen (billionai) 797a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 79837f219c8SBruno Larsen (billionai) { 79937f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 80037f219c8SBruno Larsen (billionai) } 80137f219c8SBruno Larsen (billionai) 80237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 803a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 80437f219c8SBruno Larsen (billionai) { 80537f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 80637f219c8SBruno Larsen (billionai) } 80737f219c8SBruno Larsen (billionai) 808a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 80937f219c8SBruno Larsen (billionai) { 81037f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 81137f219c8SBruno Larsen (billionai) } 81237f219c8SBruno Larsen (billionai) 813a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 81437f219c8SBruno Larsen (billionai) { 81537f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 81637f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 817d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81837f219c8SBruno Larsen (billionai) } 81937f219c8SBruno Larsen (billionai) #endif 82037f219c8SBruno Larsen (billionai) 82137f219c8SBruno Larsen (billionai) /* Unified bats */ 82237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 823a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 82437f219c8SBruno Larsen (billionai) { 82537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 82637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 82737f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 82837f219c8SBruno Larsen (billionai) } 82937f219c8SBruno Larsen (billionai) 830a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 83137f219c8SBruno Larsen (billionai) { 83237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 83337f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 83437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) 837a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 83837f219c8SBruno Larsen (billionai) { 83937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 84037f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 84137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 84237f219c8SBruno Larsen (billionai) } 84337f219c8SBruno Larsen (billionai) #endif 84437f219c8SBruno Larsen (billionai) 84537f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 84637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 847a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 84837f219c8SBruno Larsen (billionai) { 849f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85037f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 85137f219c8SBruno Larsen (billionai) } 85237f219c8SBruno Larsen (billionai) 853a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 85437f219c8SBruno Larsen (billionai) { 855f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85637f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 85737f219c8SBruno Larsen (billionai) } 85837f219c8SBruno Larsen (billionai) 859a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 86037f219c8SBruno Larsen (billionai) { 861f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 86337f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 86437f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 865d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 86637f219c8SBruno Larsen (billionai) } 86737f219c8SBruno Larsen (billionai) 868a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86937f219c8SBruno Larsen (billionai) { 870f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87137f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 87237f219c8SBruno Larsen (billionai) } 87337f219c8SBruno Larsen (billionai) 874a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 87537f219c8SBruno Larsen (billionai) { 876f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87737f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 87837f219c8SBruno Larsen (billionai) } 87937f219c8SBruno Larsen (billionai) 880a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 88137f219c8SBruno Larsen (billionai) { 882f5b6daacSRichard Henderson gen_icount_io_start(ctx); 88337f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 88437f219c8SBruno Larsen (billionai) } 88537f219c8SBruno Larsen (billionai) #endif 88637f219c8SBruno Larsen (billionai) 88737f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 88837f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 88937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 890a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 89137f219c8SBruno Larsen (billionai) { 89237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 89337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 89437f219c8SBruno Larsen (billionai) } 89537f219c8SBruno Larsen (billionai) 896a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 89737f219c8SBruno Larsen (billionai) { 89837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 89937f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 90037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 90137f219c8SBruno Larsen (billionai) } 90237f219c8SBruno Larsen (billionai) 903a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 90437f219c8SBruno Larsen (billionai) { 90537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90937f219c8SBruno Larsen (billionai) } 91037f219c8SBruno Larsen (billionai) #endif 91137f219c8SBruno Larsen (billionai) 91237f219c8SBruno Larsen (billionai) /* SPE specific registers */ 913a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 91437f219c8SBruno Larsen (billionai) { 91537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91637f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91737f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91937f219c8SBruno Larsen (billionai) } 92037f219c8SBruno Larsen (billionai) 921a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 92237f219c8SBruno Larsen (billionai) { 92337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 92437f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 92537f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92737f219c8SBruno Larsen (billionai) } 92837f219c8SBruno Larsen (billionai) 92937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 93037f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 931a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 93237f219c8SBruno Larsen (billionai) { 93337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 93437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 93537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 93637f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93937f219c8SBruno Larsen (billionai) } 94037f219c8SBruno Larsen (billionai) 941a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 94237f219c8SBruno Larsen (billionai) { 94337f219c8SBruno Larsen (billionai) int sprn_offs; 94437f219c8SBruno Larsen (billionai) 94537f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 94637f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 94737f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94937f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 95037f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 95137f219c8SBruno Larsen (billionai) } else { 95237f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 95337f219c8SBruno Larsen (billionai) sprn, sprn); 95437f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 95537f219c8SBruno Larsen (billionai) return; 95637f219c8SBruno Larsen (billionai) } 95737f219c8SBruno Larsen (billionai) 95837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 96037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 96137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 96237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 96337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 96437f219c8SBruno Larsen (billionai) } 96537f219c8SBruno Larsen (billionai) #endif 96637f219c8SBruno Larsen (billionai) 96737f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 96837f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 969a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 97037f219c8SBruno Larsen (billionai) { 97137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 97337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 97437f219c8SBruno Larsen (billionai) 97537f219c8SBruno Larsen (billionai) /* 97637f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 97737f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97837f219c8SBruno Larsen (billionai) */ 97937f219c8SBruno Larsen (billionai) 98037f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 98137f219c8SBruno Larsen (billionai) if (ctx->pr) { 98237f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 98337f219c8SBruno Larsen (billionai) } else { 98437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 98537f219c8SBruno Larsen (billionai) } 98637f219c8SBruno Larsen (billionai) 98737f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98937f219c8SBruno Larsen (billionai) 99037f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 99137f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 99237f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 99337f219c8SBruno Larsen (billionai) 99437f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 99537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 99637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 99737f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 99837f219c8SBruno Larsen (billionai) 99937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 100037f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 100137f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 100237f219c8SBruno Larsen (billionai) } 100337f219c8SBruno Larsen (billionai) 1004a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 100537f219c8SBruno Larsen (billionai) { 100637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100937f219c8SBruno Larsen (billionai) 101037f219c8SBruno Larsen (billionai) /* 101137f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 101237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 101337f219c8SBruno Larsen (billionai) */ 101437f219c8SBruno Larsen (billionai) 101537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 101637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101737f219c8SBruno Larsen (billionai) 101837f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 102037f219c8SBruno Larsen (billionai) 102137f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 102237f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 102337f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 102437f219c8SBruno Larsen (billionai) 102537f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 102637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 102837f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 102937f219c8SBruno Larsen (billionai) 103037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 103137f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 103237f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 103337f219c8SBruno Larsen (billionai) } 103437f219c8SBruno Larsen (billionai) 1035a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 103637f219c8SBruno Larsen (billionai) { 103737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103837f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103937f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 104037f219c8SBruno Larsen (billionai) 104137f219c8SBruno Larsen (billionai) /* 104237f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 104337f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 104437f219c8SBruno Larsen (billionai) */ 104537f219c8SBruno Larsen (billionai) 104637f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104837f219c8SBruno Larsen (billionai) 104937f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 105037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 105137f219c8SBruno Larsen (billionai) 105237f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 105337f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 105437f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 105537f219c8SBruno Larsen (billionai) 105637f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 105937f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 106037f219c8SBruno Larsen (billionai) 106137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 106237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 106337f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 106437f219c8SBruno Larsen (billionai) } 106537f219c8SBruno Larsen (billionai) #endif 106637f219c8SBruno Larsen (billionai) #endif 106737f219c8SBruno Larsen (billionai) 106837f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1069a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 107037f219c8SBruno Larsen (billionai) { 107137f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 107237f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 107337f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 107437f219c8SBruno Larsen (billionai) } 107537f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 107637f219c8SBruno Larsen (billionai) 107737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1078a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 107937f219c8SBruno Larsen (billionai) { 108037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108137f219c8SBruno Larsen (billionai) 108237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 108337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108537f219c8SBruno Larsen (billionai) } 108637f219c8SBruno Larsen (billionai) 1087a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 108837f219c8SBruno Larsen (billionai) { 108937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109037f219c8SBruno Larsen (billionai) 109137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 109237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109437f219c8SBruno Larsen (billionai) } 109537f219c8SBruno Larsen (billionai) 1096a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 109737f219c8SBruno Larsen (billionai) { 109837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109937f219c8SBruno Larsen (billionai) 110037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 110137f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 110237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 110337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 110437f219c8SBruno Larsen (billionai) } 110537f219c8SBruno Larsen (billionai) 1106a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 110737f219c8SBruno Larsen (billionai) { 110837f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 110937f219c8SBruno Larsen (billionai) } 111037f219c8SBruno Larsen (billionai) 1111a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 111237f219c8SBruno Larsen (billionai) { 111337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 111437f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 111537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 111637f219c8SBruno Larsen (billionai) } 1117a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 111837f219c8SBruno Larsen (billionai) { 111937f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 112037f219c8SBruno Larsen (billionai) } 1121a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 112237f219c8SBruno Larsen (billionai) { 112337f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 112437f219c8SBruno Larsen (billionai) } 112537f219c8SBruno Larsen (billionai) 112637f219c8SBruno Larsen (billionai) #endif 112737f219c8SBruno Larsen (billionai) 112837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1129a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 113037f219c8SBruno Larsen (billionai) { 113137f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 113237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 113337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 113437f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 113537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 113637f219c8SBruno Larsen (billionai) tcg_temp_free(val); 113737f219c8SBruno Larsen (billionai) } 113837f219c8SBruno Larsen (billionai) 1139a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 114037f219c8SBruno Larsen (billionai) { 114137f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 114237f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 114337f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 114437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 114537f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 114637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 114737f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 114837f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 114937f219c8SBruno Larsen (billionai) } 115037f219c8SBruno Larsen (billionai) 115137f219c8SBruno Larsen (billionai) #endif 115237f219c8SBruno Larsen (billionai) 115337f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 115437f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 115537f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 115637f219c8SBruno Larsen (billionai) { 115737f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 115837f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 115937f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116037f219c8SBruno Larsen (billionai) 116137f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 116237f219c8SBruno Larsen (billionai) 116337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 116437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 116537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 116637f219c8SBruno Larsen (billionai) } 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 116937f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 117037f219c8SBruno Larsen (billionai) { 117137f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 117237f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 117337f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 117437f219c8SBruno Larsen (billionai) 117537f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 117637f219c8SBruno Larsen (billionai) 117737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 118037f219c8SBruno Larsen (billionai) } 118137f219c8SBruno Larsen (billionai) 1182a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 118337f219c8SBruno Larsen (billionai) { 118437f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 118537f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 118637f219c8SBruno Larsen (billionai) 118737f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118837f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 118937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 119037f219c8SBruno Larsen (billionai) 119137f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 119237f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 119337f219c8SBruno Larsen (billionai) } 119437f219c8SBruno Larsen (billionai) 1195a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 119637f219c8SBruno Larsen (billionai) { 119737f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119837f219c8SBruno Larsen (billionai) 119937f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 120037f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 120137f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 120237f219c8SBruno Larsen (billionai) 120337f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 120437f219c8SBruno Larsen (billionai) } 120537f219c8SBruno Larsen (billionai) 120637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1207a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 120837f219c8SBruno Larsen (billionai) { 120937f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 121037f219c8SBruno Larsen (billionai) 121137f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 121237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 121337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 121437f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 121537f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 121637f219c8SBruno Larsen (billionai) } 121737f219c8SBruno Larsen (billionai) 1218a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 121937f219c8SBruno Larsen (billionai) { 122037f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 122137f219c8SBruno Larsen (billionai) } 122237f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 122337f219c8SBruno Larsen (billionai) 1224a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 122537f219c8SBruno Larsen (billionai) { 122637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122837f219c8SBruno Larsen (billionai) } 122937f219c8SBruno Larsen (billionai) 1230a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 123137f219c8SBruno Larsen (billionai) { 123237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 123337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123437f219c8SBruno Larsen (billionai) } 123537f219c8SBruno Larsen (billionai) 1236a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 123737f219c8SBruno Larsen (billionai) { 123837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123937f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 124037f219c8SBruno Larsen (billionai) } 124137f219c8SBruno Larsen (billionai) 1242a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 124337f219c8SBruno Larsen (billionai) { 124437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124637f219c8SBruno Larsen (billionai) } 124737f219c8SBruno Larsen (billionai) 1248a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 124937f219c8SBruno Larsen (billionai) { 125037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125137f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 125237f219c8SBruno Larsen (billionai) } 125337f219c8SBruno Larsen (billionai) 1254a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 125537f219c8SBruno Larsen (billionai) { 125637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125737f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125837f219c8SBruno Larsen (billionai) } 125937f219c8SBruno Larsen (billionai) 1260a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 126137f219c8SBruno Larsen (billionai) { 126237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 126437f219c8SBruno Larsen (billionai) } 126537f219c8SBruno Larsen (billionai) 1266a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 126737f219c8SBruno Larsen (billionai) { 126837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 127037f219c8SBruno Larsen (billionai) } 127137f219c8SBruno Larsen (billionai) 1272a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 127337f219c8SBruno Larsen (billionai) { 127437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127537f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 127637f219c8SBruno Larsen (billionai) } 127737f219c8SBruno Larsen (billionai) 1278a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 127937f219c8SBruno Larsen (billionai) { 128037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 128137f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 128237f219c8SBruno Larsen (billionai) } 128337f219c8SBruno Larsen (billionai) #endif 128437f219c8SBruno Larsen (billionai) 1285fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1286fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1287fcf5ef2aSThomas Huth 1288fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1289fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1290fcf5ef2aSThomas Huth 1291fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1292fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1293fcf5ef2aSThomas Huth 1294fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1295fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1296fcf5ef2aSThomas Huth 1297fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1298fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1299fcf5ef2aSThomas Huth 1300fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1301fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1302fcf5ef2aSThomas Huth 1303fcf5ef2aSThomas Huth typedef struct opcode_t { 1304fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1305fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1306fcf5ef2aSThomas Huth unsigned char pad[4]; 1307fcf5ef2aSThomas Huth #endif 1308fcf5ef2aSThomas Huth opc_handler_t handler; 1309fcf5ef2aSThomas Huth const char *oname; 1310fcf5ef2aSThomas Huth } opcode_t; 1311fcf5ef2aSThomas Huth 1312fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1313fcf5ef2aSThomas Huth #define GEN_PRIV \ 1314fcf5ef2aSThomas Huth do { \ 1315fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1316fcf5ef2aSThomas Huth } while (0) 1317fcf5ef2aSThomas Huth 1318fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1319fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1320fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1321fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1322fcf5ef2aSThomas Huth #else 1323fcf5ef2aSThomas Huth #define CHK_HV \ 1324fcf5ef2aSThomas Huth do { \ 1325fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1326fcf5ef2aSThomas Huth GEN_PRIV; \ 1327fcf5ef2aSThomas Huth } \ 1328fcf5ef2aSThomas Huth } while (0) 1329fcf5ef2aSThomas Huth #define CHK_SV \ 1330fcf5ef2aSThomas Huth do { \ 1331fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1332fcf5ef2aSThomas Huth GEN_PRIV; \ 1333fcf5ef2aSThomas Huth } \ 1334fcf5ef2aSThomas Huth } while (0) 1335fcf5ef2aSThomas Huth #define CHK_HVRM \ 1336fcf5ef2aSThomas Huth do { \ 1337fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1338fcf5ef2aSThomas Huth GEN_PRIV; \ 1339fcf5ef2aSThomas Huth } \ 1340fcf5ef2aSThomas Huth } while (0) 1341fcf5ef2aSThomas Huth #endif 1342fcf5ef2aSThomas Huth 1343fcf5ef2aSThomas Huth #define CHK_NONE 1344fcf5ef2aSThomas Huth 1345fcf5ef2aSThomas Huth /*****************************************************************************/ 1346fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1347fcf5ef2aSThomas Huth 1348fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 1349fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1350fcf5ef2aSThomas Huth { \ 1351fcf5ef2aSThomas Huth .opc1 = op1, \ 1352fcf5ef2aSThomas Huth .opc2 = op2, \ 1353fcf5ef2aSThomas Huth .opc3 = op3, \ 1354fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1355fcf5ef2aSThomas Huth .handler = { \ 1356fcf5ef2aSThomas Huth .inval1 = invl, \ 1357fcf5ef2aSThomas Huth .type = _typ, \ 1358fcf5ef2aSThomas Huth .type2 = _typ2, \ 1359fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1360fcf5ef2aSThomas Huth .oname = stringify(name), \ 1361fcf5ef2aSThomas Huth }, \ 1362fcf5ef2aSThomas Huth .oname = stringify(name), \ 1363fcf5ef2aSThomas Huth } 1364fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1365fcf5ef2aSThomas Huth { \ 1366fcf5ef2aSThomas Huth .opc1 = op1, \ 1367fcf5ef2aSThomas Huth .opc2 = op2, \ 1368fcf5ef2aSThomas Huth .opc3 = op3, \ 1369fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1370fcf5ef2aSThomas Huth .handler = { \ 1371fcf5ef2aSThomas Huth .inval1 = invl1, \ 1372fcf5ef2aSThomas Huth .inval2 = invl2, \ 1373fcf5ef2aSThomas Huth .type = _typ, \ 1374fcf5ef2aSThomas Huth .type2 = _typ2, \ 1375fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1376fcf5ef2aSThomas Huth .oname = stringify(name), \ 1377fcf5ef2aSThomas Huth }, \ 1378fcf5ef2aSThomas Huth .oname = stringify(name), \ 1379fcf5ef2aSThomas Huth } 1380fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1381fcf5ef2aSThomas Huth { \ 1382fcf5ef2aSThomas Huth .opc1 = op1, \ 1383fcf5ef2aSThomas Huth .opc2 = op2, \ 1384fcf5ef2aSThomas Huth .opc3 = op3, \ 1385fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1386fcf5ef2aSThomas Huth .handler = { \ 1387fcf5ef2aSThomas Huth .inval1 = invl, \ 1388fcf5ef2aSThomas Huth .type = _typ, \ 1389fcf5ef2aSThomas Huth .type2 = _typ2, \ 1390fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1391fcf5ef2aSThomas Huth .oname = onam, \ 1392fcf5ef2aSThomas Huth }, \ 1393fcf5ef2aSThomas Huth .oname = onam, \ 1394fcf5ef2aSThomas Huth } 1395fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1396fcf5ef2aSThomas Huth { \ 1397fcf5ef2aSThomas Huth .opc1 = op1, \ 1398fcf5ef2aSThomas Huth .opc2 = op2, \ 1399fcf5ef2aSThomas Huth .opc3 = op3, \ 1400fcf5ef2aSThomas Huth .opc4 = op4, \ 1401fcf5ef2aSThomas Huth .handler = { \ 1402fcf5ef2aSThomas Huth .inval1 = invl, \ 1403fcf5ef2aSThomas Huth .type = _typ, \ 1404fcf5ef2aSThomas Huth .type2 = _typ2, \ 1405fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1406fcf5ef2aSThomas Huth .oname = stringify(name), \ 1407fcf5ef2aSThomas Huth }, \ 1408fcf5ef2aSThomas Huth .oname = stringify(name), \ 1409fcf5ef2aSThomas Huth } 1410fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1411fcf5ef2aSThomas Huth { \ 1412fcf5ef2aSThomas Huth .opc1 = op1, \ 1413fcf5ef2aSThomas Huth .opc2 = op2, \ 1414fcf5ef2aSThomas Huth .opc3 = op3, \ 1415fcf5ef2aSThomas Huth .opc4 = op4, \ 1416fcf5ef2aSThomas Huth .handler = { \ 1417fcf5ef2aSThomas Huth .inval1 = invl, \ 1418fcf5ef2aSThomas Huth .type = _typ, \ 1419fcf5ef2aSThomas Huth .type2 = _typ2, \ 1420fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1421fcf5ef2aSThomas Huth .oname = onam, \ 1422fcf5ef2aSThomas Huth }, \ 1423fcf5ef2aSThomas Huth .oname = onam, \ 1424fcf5ef2aSThomas Huth } 1425fcf5ef2aSThomas Huth #else 1426fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1427fcf5ef2aSThomas Huth { \ 1428fcf5ef2aSThomas Huth .opc1 = op1, \ 1429fcf5ef2aSThomas Huth .opc2 = op2, \ 1430fcf5ef2aSThomas Huth .opc3 = op3, \ 1431fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1432fcf5ef2aSThomas Huth .handler = { \ 1433fcf5ef2aSThomas Huth .inval1 = invl, \ 1434fcf5ef2aSThomas Huth .type = _typ, \ 1435fcf5ef2aSThomas Huth .type2 = _typ2, \ 1436fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1437fcf5ef2aSThomas Huth }, \ 1438fcf5ef2aSThomas Huth .oname = stringify(name), \ 1439fcf5ef2aSThomas Huth } 1440fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1441fcf5ef2aSThomas Huth { \ 1442fcf5ef2aSThomas Huth .opc1 = op1, \ 1443fcf5ef2aSThomas Huth .opc2 = op2, \ 1444fcf5ef2aSThomas Huth .opc3 = op3, \ 1445fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1446fcf5ef2aSThomas Huth .handler = { \ 1447fcf5ef2aSThomas Huth .inval1 = invl1, \ 1448fcf5ef2aSThomas Huth .inval2 = invl2, \ 1449fcf5ef2aSThomas Huth .type = _typ, \ 1450fcf5ef2aSThomas Huth .type2 = _typ2, \ 1451fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1452fcf5ef2aSThomas Huth }, \ 1453fcf5ef2aSThomas Huth .oname = stringify(name), \ 1454fcf5ef2aSThomas Huth } 1455fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1456fcf5ef2aSThomas Huth { \ 1457fcf5ef2aSThomas Huth .opc1 = op1, \ 1458fcf5ef2aSThomas Huth .opc2 = op2, \ 1459fcf5ef2aSThomas Huth .opc3 = op3, \ 1460fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1461fcf5ef2aSThomas Huth .handler = { \ 1462fcf5ef2aSThomas Huth .inval1 = invl, \ 1463fcf5ef2aSThomas Huth .type = _typ, \ 1464fcf5ef2aSThomas Huth .type2 = _typ2, \ 1465fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1466fcf5ef2aSThomas Huth }, \ 1467fcf5ef2aSThomas Huth .oname = onam, \ 1468fcf5ef2aSThomas Huth } 1469fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1470fcf5ef2aSThomas Huth { \ 1471fcf5ef2aSThomas Huth .opc1 = op1, \ 1472fcf5ef2aSThomas Huth .opc2 = op2, \ 1473fcf5ef2aSThomas Huth .opc3 = op3, \ 1474fcf5ef2aSThomas Huth .opc4 = op4, \ 1475fcf5ef2aSThomas Huth .handler = { \ 1476fcf5ef2aSThomas Huth .inval1 = invl, \ 1477fcf5ef2aSThomas Huth .type = _typ, \ 1478fcf5ef2aSThomas Huth .type2 = _typ2, \ 1479fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1480fcf5ef2aSThomas Huth }, \ 1481fcf5ef2aSThomas Huth .oname = stringify(name), \ 1482fcf5ef2aSThomas Huth } 1483fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1484fcf5ef2aSThomas Huth { \ 1485fcf5ef2aSThomas Huth .opc1 = op1, \ 1486fcf5ef2aSThomas Huth .opc2 = op2, \ 1487fcf5ef2aSThomas Huth .opc3 = op3, \ 1488fcf5ef2aSThomas Huth .opc4 = op4, \ 1489fcf5ef2aSThomas Huth .handler = { \ 1490fcf5ef2aSThomas Huth .inval1 = invl, \ 1491fcf5ef2aSThomas Huth .type = _typ, \ 1492fcf5ef2aSThomas Huth .type2 = _typ2, \ 1493fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1494fcf5ef2aSThomas Huth }, \ 1495fcf5ef2aSThomas Huth .oname = onam, \ 1496fcf5ef2aSThomas Huth } 1497fcf5ef2aSThomas Huth #endif 1498fcf5ef2aSThomas Huth 1499fcf5ef2aSThomas Huth /* Invalid instruction */ 1500fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1501fcf5ef2aSThomas Huth { 1502fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1503fcf5ef2aSThomas Huth } 1504fcf5ef2aSThomas Huth 1505fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1506fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1507fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1508fcf5ef2aSThomas Huth .type = PPC_NONE, 1509fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1510fcf5ef2aSThomas Huth .handler = gen_invalid, 1511fcf5ef2aSThomas Huth }; 1512fcf5ef2aSThomas Huth 1513fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1514fcf5ef2aSThomas Huth 1515fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1516fcf5ef2aSThomas Huth { 1517fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1518b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1519b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1520fcf5ef2aSThomas Huth 1521b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1522b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1523efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1524efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1525b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1526efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1527efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1528b62b3686Spbonzini@redhat.com 1529b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1530fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1531b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1532fcf5ef2aSThomas Huth 1533fcf5ef2aSThomas Huth tcg_temp_free(t0); 1534b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1535b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1536fcf5ef2aSThomas Huth } 1537fcf5ef2aSThomas Huth 1538fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1539fcf5ef2aSThomas Huth { 1540fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1541fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1542fcf5ef2aSThomas Huth tcg_temp_free(t0); 1543fcf5ef2aSThomas Huth } 1544fcf5ef2aSThomas Huth 1545fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1546fcf5ef2aSThomas Huth { 1547fcf5ef2aSThomas Huth TCGv t0, t1; 1548fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1549fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1550fcf5ef2aSThomas Huth if (s) { 1551fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1552fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1553fcf5ef2aSThomas Huth } else { 1554fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1555fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1556fcf5ef2aSThomas Huth } 1557fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1558fcf5ef2aSThomas Huth tcg_temp_free(t1); 1559fcf5ef2aSThomas Huth tcg_temp_free(t0); 1560fcf5ef2aSThomas Huth } 1561fcf5ef2aSThomas Huth 1562fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1563fcf5ef2aSThomas Huth { 1564fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1565fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1566fcf5ef2aSThomas Huth tcg_temp_free(t0); 1567fcf5ef2aSThomas Huth } 1568fcf5ef2aSThomas Huth 1569fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1570fcf5ef2aSThomas Huth { 1571fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1572fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1573fcf5ef2aSThomas Huth } else { 1574fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1575fcf5ef2aSThomas Huth } 1576fcf5ef2aSThomas Huth } 1577fcf5ef2aSThomas Huth 1578fcf5ef2aSThomas Huth /* cmp */ 1579fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1580fcf5ef2aSThomas Huth { 1581fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1582fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1583fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1584fcf5ef2aSThomas Huth } else { 1585fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1586fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1587fcf5ef2aSThomas Huth } 1588fcf5ef2aSThomas Huth } 1589fcf5ef2aSThomas Huth 1590fcf5ef2aSThomas Huth /* cmpi */ 1591fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1592fcf5ef2aSThomas Huth { 1593fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1594fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1595fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1596fcf5ef2aSThomas Huth } else { 1597fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1598fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1599fcf5ef2aSThomas Huth } 1600fcf5ef2aSThomas Huth } 1601fcf5ef2aSThomas Huth 1602fcf5ef2aSThomas Huth /* cmpl */ 1603fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1604fcf5ef2aSThomas Huth { 1605fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1606fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1607fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1608fcf5ef2aSThomas Huth } else { 1609fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1610fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1611fcf5ef2aSThomas Huth } 1612fcf5ef2aSThomas Huth } 1613fcf5ef2aSThomas Huth 1614fcf5ef2aSThomas Huth /* cmpli */ 1615fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1616fcf5ef2aSThomas Huth { 1617fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1618fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1619fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1620fcf5ef2aSThomas Huth } else { 1621fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1622fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1623fcf5ef2aSThomas Huth } 1624fcf5ef2aSThomas Huth } 1625fcf5ef2aSThomas Huth 1626fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1627fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1628fcf5ef2aSThomas Huth { 1629fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1630fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1631fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1632fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1633fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1634fcf5ef2aSThomas Huth 1635fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1636fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1637fcf5ef2aSThomas Huth 1638fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1639fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1640fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1641fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1642fcf5ef2aSThomas Huth 1643fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1644fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1645fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1646fcf5ef2aSThomas Huth 1647fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1648fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1649fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1650fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1651fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1652fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1653fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1654fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1655fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1656fcf5ef2aSThomas Huth } 1657efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1658fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1659fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1660fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1661fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1662fcf5ef2aSThomas Huth } 1663fcf5ef2aSThomas Huth 1664fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1665fcf5ef2aSThomas Huth /* cmpeqb */ 1666fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1667fcf5ef2aSThomas Huth { 1668fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1669fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth #endif 1672fcf5ef2aSThomas Huth 1673fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1674fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1675fcf5ef2aSThomas Huth { 1676fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1677fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1678fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1679fcf5ef2aSThomas Huth TCGv zr; 1680fcf5ef2aSThomas Huth 1681fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1682fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1683fcf5ef2aSThomas Huth 1684fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1685fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1686fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1687fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1688fcf5ef2aSThomas Huth tcg_temp_free(zr); 1689fcf5ef2aSThomas Huth tcg_temp_free(t0); 1690fcf5ef2aSThomas Huth } 1691fcf5ef2aSThomas Huth 1692fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1693fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1694fcf5ef2aSThomas Huth { 1695fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1696fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1697fcf5ef2aSThomas Huth } 1698fcf5ef2aSThomas Huth 1699fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1700fcf5ef2aSThomas Huth 1701fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1702fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1703fcf5ef2aSThomas Huth { 1704fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1705fcf5ef2aSThomas Huth 1706fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1707fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1708fcf5ef2aSThomas Huth if (sub) { 1709fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1710fcf5ef2aSThomas Huth } else { 1711fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1712fcf5ef2aSThomas Huth } 1713fcf5ef2aSThomas Huth tcg_temp_free(t0); 1714fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1715dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1716dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1717dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1718fcf5ef2aSThomas Huth } 1719dc0ad844SNikunj A Dadhania } else { 1720dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1721dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1722dc0ad844SNikunj A Dadhania } 172338a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1724dc0ad844SNikunj A Dadhania } 1725fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1726fcf5ef2aSThomas Huth } 1727fcf5ef2aSThomas Huth 17286b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 17296b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 17304c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 17316b10d008SNikunj A Dadhania { 17326b10d008SNikunj A Dadhania TCGv t0; 17336b10d008SNikunj A Dadhania 17346b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 17356b10d008SNikunj A Dadhania return; 17366b10d008SNikunj A Dadhania } 17376b10d008SNikunj A Dadhania 17386b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 173933903d0aSNikunj A Dadhania if (sub) { 174033903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 174133903d0aSNikunj A Dadhania } else { 17426b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 174333903d0aSNikunj A Dadhania } 17446b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 17454c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 17466b10d008SNikunj A Dadhania tcg_temp_free(t0); 17476b10d008SNikunj A Dadhania } 17486b10d008SNikunj A Dadhania 1749fcf5ef2aSThomas Huth /* Common add function */ 1750fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 17514c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 17524c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1753fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1754fcf5ef2aSThomas Huth { 1755fcf5ef2aSThomas Huth TCGv t0 = ret; 1756fcf5ef2aSThomas Huth 1757fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1758fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1759fcf5ef2aSThomas Huth } 1760fcf5ef2aSThomas Huth 1761fcf5ef2aSThomas Huth if (compute_ca) { 1762fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1763efe843d8SDavid Gibson /* 1764efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1765efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1766efe843d8SDavid Gibson * produce the carry into bit 32. 1767efe843d8SDavid Gibson */ 1768fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1769fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1770fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1771fcf5ef2aSThomas Huth if (add_ca) { 17724c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1773fcf5ef2aSThomas Huth } 17744c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1775fcf5ef2aSThomas Huth tcg_temp_free(t1); 17764c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 17776b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 17784c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 17796b10d008SNikunj A Dadhania } 1780fcf5ef2aSThomas Huth } else { 1781fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1782fcf5ef2aSThomas Huth if (add_ca) { 17834c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 17844c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1785fcf5ef2aSThomas Huth } else { 17864c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1787fcf5ef2aSThomas Huth } 17884c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1789fcf5ef2aSThomas Huth tcg_temp_free(zero); 1790fcf5ef2aSThomas Huth } 1791fcf5ef2aSThomas Huth } else { 1792fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1793fcf5ef2aSThomas Huth if (add_ca) { 17944c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1795fcf5ef2aSThomas Huth } 1796fcf5ef2aSThomas Huth } 1797fcf5ef2aSThomas Huth 1798fcf5ef2aSThomas Huth if (compute_ov) { 1799fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1800fcf5ef2aSThomas Huth } 1801fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1802fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1803fcf5ef2aSThomas Huth } 1804fcf5ef2aSThomas Huth 180511f4e8f8SRichard Henderson if (t0 != ret) { 1806fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1807fcf5ef2aSThomas Huth tcg_temp_free(t0); 1808fcf5ef2aSThomas Huth } 1809fcf5ef2aSThomas Huth } 1810fcf5ef2aSThomas Huth /* Add functions with two operands */ 18114c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1812fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1813fcf5ef2aSThomas Huth { \ 1814fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1815fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 18164c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1817fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1818fcf5ef2aSThomas Huth } 1819fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 18204c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1821fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1822fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1823fcf5ef2aSThomas Huth { \ 1824fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1825fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1826fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 18274c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1828fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1829fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1830fcf5ef2aSThomas Huth } 1831fcf5ef2aSThomas Huth 1832fcf5ef2aSThomas Huth /* add add. addo addo. */ 18334c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 18344c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1835fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 18364c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 18374c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1838fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 18394c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 18404c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1841fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 18424c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 18434c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 18444c5920afSSuraj Jitindar Singh /* addex */ 18454c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1846fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 18474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 18484c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1849fcf5ef2aSThomas Huth /* addi */ 1850fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 1851fcf5ef2aSThomas Huth { 1852fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1853fcf5ef2aSThomas Huth 1854fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1855fcf5ef2aSThomas Huth /* li case */ 1856fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 1857fcf5ef2aSThomas Huth } else { 1858fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1859fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 1860fcf5ef2aSThomas Huth } 1861fcf5ef2aSThomas Huth } 1862fcf5ef2aSThomas Huth /* addic addic.*/ 1863fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1864fcf5ef2aSThomas Huth { 1865fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1866fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 18674c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1868fcf5ef2aSThomas Huth tcg_temp_free(c); 1869fcf5ef2aSThomas Huth } 1870fcf5ef2aSThomas Huth 1871fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1872fcf5ef2aSThomas Huth { 1873fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1874fcf5ef2aSThomas Huth } 1875fcf5ef2aSThomas Huth 1876fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1877fcf5ef2aSThomas Huth { 1878fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1879fcf5ef2aSThomas Huth } 1880fcf5ef2aSThomas Huth 1881fcf5ef2aSThomas Huth /* addis */ 1882fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 1883fcf5ef2aSThomas Huth { 1884fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1885fcf5ef2aSThomas Huth 1886fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1887fcf5ef2aSThomas Huth /* lis case */ 1888fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 1889fcf5ef2aSThomas Huth } else { 1890fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1891fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 1892fcf5ef2aSThomas Huth } 1893fcf5ef2aSThomas Huth } 1894fcf5ef2aSThomas Huth 1895fcf5ef2aSThomas Huth /* addpcis */ 1896fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 1897fcf5ef2aSThomas Huth { 1898fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 1899fcf5ef2aSThomas Huth 1900b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 1901fcf5ef2aSThomas Huth } 1902fcf5ef2aSThomas Huth 1903fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1904fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1905fcf5ef2aSThomas Huth { 1906fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1907fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1908fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1909fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1910fcf5ef2aSThomas Huth 1911fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1912fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1913fcf5ef2aSThomas Huth if (sign) { 1914fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1915fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1916fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1917fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1918fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1919fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1920fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1921fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1922fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1923fcf5ef2aSThomas Huth } else { 1924fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1925fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1926fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1927fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1928fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1929fcf5ef2aSThomas Huth } 1930fcf5ef2aSThomas Huth if (compute_ov) { 1931fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1932c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1933c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1934c44027ffSNikunj A Dadhania } 1935fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1936fcf5ef2aSThomas Huth } 1937fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1938fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1939fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1940fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1941fcf5ef2aSThomas Huth 1942efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1943fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1944fcf5ef2aSThomas Huth } 1945efe843d8SDavid Gibson } 1946fcf5ef2aSThomas Huth /* Div functions */ 1947fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1948fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1949fcf5ef2aSThomas Huth { \ 1950fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1951fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1952fcf5ef2aSThomas Huth sign, compute_ov); \ 1953fcf5ef2aSThomas Huth } 1954fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1955fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1956fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1957fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1958fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1959fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1960fcf5ef2aSThomas Huth 1961fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1962fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1963fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1964fcf5ef2aSThomas Huth { \ 1965fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1966fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1967fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1968fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1969fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1970fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1971fcf5ef2aSThomas Huth } \ 1972fcf5ef2aSThomas Huth } 1973fcf5ef2aSThomas Huth 1974fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1975fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1976fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1977fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1978fcf5ef2aSThomas Huth 1979fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1980fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1981fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1982fcf5ef2aSThomas Huth { 1983fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1984fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1985fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1986fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1987fcf5ef2aSThomas Huth 1988fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1989fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1990fcf5ef2aSThomas Huth if (sign) { 1991fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1992fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1993fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1994fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1995fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1996fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1997fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1998fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1999fcf5ef2aSThomas Huth } else { 2000fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 2001fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2002fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2003fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 2004fcf5ef2aSThomas Huth } 2005fcf5ef2aSThomas Huth if (compute_ov) { 2006fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 2007c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2008c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 2009c44027ffSNikunj A Dadhania } 2010fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2011fcf5ef2aSThomas Huth } 2012fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2013fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2014fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2015fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2016fcf5ef2aSThomas Huth 2017efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2018fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2019fcf5ef2aSThomas Huth } 2020efe843d8SDavid Gibson } 2021fcf5ef2aSThomas Huth 2022fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 2023fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2024fcf5ef2aSThomas Huth { \ 2025fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2026fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2027fcf5ef2aSThomas Huth sign, compute_ov); \ 2028fcf5ef2aSThomas Huth } 2029c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 2030fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 2031fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 2032c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 2033fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 2034fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 2035fcf5ef2aSThomas Huth 2036fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 2037fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 2038fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 2039fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 2040fcf5ef2aSThomas Huth #endif 2041fcf5ef2aSThomas Huth 2042fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 2043fcf5ef2aSThomas Huth TCGv arg2, int sign) 2044fcf5ef2aSThomas Huth { 2045fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2046fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2047fcf5ef2aSThomas Huth 2048fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2049fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2050fcf5ef2aSThomas Huth if (sign) { 2051fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2052fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2053fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2054fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2055fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2056fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2057fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2058fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2059fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2060fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 2061fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 2062fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2063fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2064fcf5ef2aSThomas Huth } else { 2065fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 2066fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 2067fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 2068fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 2069fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2070fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2071fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2072fcf5ef2aSThomas Huth } 2073fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2074fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2075fcf5ef2aSThomas Huth } 2076fcf5ef2aSThomas Huth 2077fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 2078fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2079fcf5ef2aSThomas Huth { \ 2080fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2081fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2082fcf5ef2aSThomas Huth sign); \ 2083fcf5ef2aSThomas Huth } 2084fcf5ef2aSThomas Huth 2085fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 2086fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 2087fcf5ef2aSThomas Huth 2088fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2089fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 2090fcf5ef2aSThomas Huth TCGv arg2, int sign) 2091fcf5ef2aSThomas Huth { 2092fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2093fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2094fcf5ef2aSThomas Huth 2095fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2096fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2097fcf5ef2aSThomas Huth if (sign) { 2098fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2099fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2100fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2101fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2102fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2103fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2104fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2105fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2106fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2107fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 2108fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2109fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2110fcf5ef2aSThomas Huth } else { 2111fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 2112fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2113fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2114fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2115fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2116fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2117fcf5ef2aSThomas Huth } 2118fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2119fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2120fcf5ef2aSThomas Huth } 2121fcf5ef2aSThomas Huth 2122fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2123fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2124fcf5ef2aSThomas Huth { \ 2125fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2126fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2127fcf5ef2aSThomas Huth sign); \ 2128fcf5ef2aSThomas Huth } 2129fcf5ef2aSThomas Huth 2130fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2131fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2132fcf5ef2aSThomas Huth #endif 2133fcf5ef2aSThomas Huth 2134fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2135fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2136fcf5ef2aSThomas Huth { 2137fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2138fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2139fcf5ef2aSThomas Huth 2140fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2141fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2142fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2143fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2144fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2145fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2146efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2147fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2148fcf5ef2aSThomas Huth } 2149efe843d8SDavid Gibson } 2150fcf5ef2aSThomas Huth 2151fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2152fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2153fcf5ef2aSThomas Huth { 2154fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2155fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2156fcf5ef2aSThomas Huth 2157fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2158fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2159fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2160fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2161fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2162fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2163efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2164fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2165fcf5ef2aSThomas Huth } 2166efe843d8SDavid Gibson } 2167fcf5ef2aSThomas Huth 2168fcf5ef2aSThomas Huth /* mullw mullw. */ 2169fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2170fcf5ef2aSThomas Huth { 2171fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2172fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2173fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2174fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2175fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2176fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2177fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2178fcf5ef2aSThomas Huth tcg_temp_free(t0); 2179fcf5ef2aSThomas Huth tcg_temp_free(t1); 2180fcf5ef2aSThomas Huth #else 2181fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2182fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2183fcf5ef2aSThomas Huth #endif 2184efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2185fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2186fcf5ef2aSThomas Huth } 2187efe843d8SDavid Gibson } 2188fcf5ef2aSThomas Huth 2189fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2190fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2191fcf5ef2aSThomas Huth { 2192fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2193fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2194fcf5ef2aSThomas Huth 2195fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2196fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2197fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2198fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2199fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2200fcf5ef2aSThomas Huth #else 2201fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2202fcf5ef2aSThomas Huth #endif 2203fcf5ef2aSThomas Huth 2204fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2205fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2206fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 220761aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 220861aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 220961aa9a69SNikunj A Dadhania } 2210fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2211fcf5ef2aSThomas Huth 2212fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2213fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2214efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2215fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2216fcf5ef2aSThomas Huth } 2217efe843d8SDavid Gibson } 2218fcf5ef2aSThomas Huth 2219fcf5ef2aSThomas Huth /* mulli */ 2220fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2221fcf5ef2aSThomas Huth { 2222fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2223fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2224fcf5ef2aSThomas Huth } 2225fcf5ef2aSThomas Huth 2226fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2227fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2228fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2229fcf5ef2aSThomas Huth { 2230fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2231fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2232fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2233fcf5ef2aSThomas Huth tcg_temp_free(lo); 2234fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2235fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2236fcf5ef2aSThomas Huth } 2237fcf5ef2aSThomas Huth } 2238fcf5ef2aSThomas Huth 2239fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2240fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2241fcf5ef2aSThomas Huth { 2242fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2243fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2244fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2245fcf5ef2aSThomas Huth tcg_temp_free(lo); 2246fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2247fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2248fcf5ef2aSThomas Huth } 2249fcf5ef2aSThomas Huth } 2250fcf5ef2aSThomas Huth 2251fcf5ef2aSThomas Huth /* mulld mulld. */ 2252fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2253fcf5ef2aSThomas Huth { 2254fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2255fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2256efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2257fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2258fcf5ef2aSThomas Huth } 2259efe843d8SDavid Gibson } 2260fcf5ef2aSThomas Huth 2261fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2262fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2263fcf5ef2aSThomas Huth { 2264fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2265fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2266fcf5ef2aSThomas Huth 2267fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2268fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2269fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2270fcf5ef2aSThomas Huth 2271fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2272fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 227361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 227461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 227561aa9a69SNikunj A Dadhania } 2276fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2277fcf5ef2aSThomas Huth 2278fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2279fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2280fcf5ef2aSThomas Huth 2281fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2282fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2283fcf5ef2aSThomas Huth } 2284fcf5ef2aSThomas Huth } 2285fcf5ef2aSThomas Huth #endif 2286fcf5ef2aSThomas Huth 2287fcf5ef2aSThomas Huth /* Common subf function */ 2288fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2289fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2290fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2291fcf5ef2aSThomas Huth { 2292fcf5ef2aSThomas Huth TCGv t0 = ret; 2293fcf5ef2aSThomas Huth 2294fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2295fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2296fcf5ef2aSThomas Huth } 2297fcf5ef2aSThomas Huth 2298fcf5ef2aSThomas Huth if (compute_ca) { 2299fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2300fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2301efe843d8SDavid Gibson /* 2302efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2303efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2304efe843d8SDavid Gibson * produce the carry into bit 32. 2305efe843d8SDavid Gibson */ 2306fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2307fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2308fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2309fcf5ef2aSThomas Huth if (add_ca) { 2310fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2311fcf5ef2aSThomas Huth } else { 2312fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2313fcf5ef2aSThomas Huth } 2314fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2315fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2316fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2317fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2318fcf5ef2aSThomas Huth tcg_temp_free(t1); 2319e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 232033903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 232133903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 232233903d0aSNikunj A Dadhania } 2323fcf5ef2aSThomas Huth } else if (add_ca) { 2324fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2325fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2326fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2327fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2328fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 23294c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2330fcf5ef2aSThomas Huth tcg_temp_free(zero); 2331fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2332fcf5ef2aSThomas Huth } else { 2333fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2334fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 23354c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2336fcf5ef2aSThomas Huth } 2337fcf5ef2aSThomas Huth } else if (add_ca) { 2338efe843d8SDavid Gibson /* 2339efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2340efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2341efe843d8SDavid Gibson */ 2342fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2343fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2344fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2345fcf5ef2aSThomas Huth } else { 2346fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2347fcf5ef2aSThomas Huth } 2348fcf5ef2aSThomas Huth 2349fcf5ef2aSThomas Huth if (compute_ov) { 2350fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2351fcf5ef2aSThomas Huth } 2352fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2353fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2354fcf5ef2aSThomas Huth } 2355fcf5ef2aSThomas Huth 235611f4e8f8SRichard Henderson if (t0 != ret) { 2357fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2358fcf5ef2aSThomas Huth tcg_temp_free(t0); 2359fcf5ef2aSThomas Huth } 2360fcf5ef2aSThomas Huth } 2361fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2362fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2363fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2364fcf5ef2aSThomas Huth { \ 2365fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2366fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2367fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2368fcf5ef2aSThomas Huth } 2369fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2370fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2371fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2372fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2373fcf5ef2aSThomas Huth { \ 2374fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2375fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2376fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2377fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2378fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2379fcf5ef2aSThomas Huth } 2380fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2381fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2382fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2383fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2384fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2385fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2386fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2387fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2388fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2389fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2390fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2391fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2392fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2393fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2394fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2395fcf5ef2aSThomas Huth 2396fcf5ef2aSThomas Huth /* subfic */ 2397fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2398fcf5ef2aSThomas Huth { 2399fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2400fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2401fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2402fcf5ef2aSThomas Huth tcg_temp_free(c); 2403fcf5ef2aSThomas Huth } 2404fcf5ef2aSThomas Huth 2405fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2406fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2407fcf5ef2aSThomas Huth { 2408fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2409fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2410fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2411fcf5ef2aSThomas Huth tcg_temp_free(zero); 2412fcf5ef2aSThomas Huth } 2413fcf5ef2aSThomas Huth 2414fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2415fcf5ef2aSThomas Huth { 24161480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 24171480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 24181480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 24191480d71cSNikunj A Dadhania } 2420fcf5ef2aSThomas Huth } 2421fcf5ef2aSThomas Huth 2422fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2423fcf5ef2aSThomas Huth { 2424fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2425fcf5ef2aSThomas Huth } 2426fcf5ef2aSThomas Huth 2427fcf5ef2aSThomas Huth /*** Integer logical ***/ 2428fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2429fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2430fcf5ef2aSThomas Huth { \ 2431fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2432fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2433fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2434fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2435fcf5ef2aSThomas Huth } 2436fcf5ef2aSThomas Huth 2437fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2438fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2439fcf5ef2aSThomas Huth { \ 2440fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2441fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2442fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2443fcf5ef2aSThomas Huth } 2444fcf5ef2aSThomas Huth 2445fcf5ef2aSThomas Huth /* and & and. */ 2446fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2447fcf5ef2aSThomas Huth /* andc & andc. */ 2448fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2449fcf5ef2aSThomas Huth 2450fcf5ef2aSThomas Huth /* andi. */ 2451fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2452fcf5ef2aSThomas Huth { 2453efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2454efe843d8SDavid Gibson UIMM(ctx->opcode)); 2455fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2456fcf5ef2aSThomas Huth } 2457fcf5ef2aSThomas Huth 2458fcf5ef2aSThomas Huth /* andis. */ 2459fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2460fcf5ef2aSThomas Huth { 2461efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2462efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2463fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2464fcf5ef2aSThomas Huth } 2465fcf5ef2aSThomas Huth 2466fcf5ef2aSThomas Huth /* cntlzw */ 2467fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2468fcf5ef2aSThomas Huth { 24699b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 24709b8514e5SRichard Henderson 24719b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 24729b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 24739b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 24749b8514e5SRichard Henderson tcg_temp_free_i32(t); 24759b8514e5SRichard Henderson 2476efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2477fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2478fcf5ef2aSThomas Huth } 2479efe843d8SDavid Gibson } 2480fcf5ef2aSThomas Huth 2481fcf5ef2aSThomas Huth /* cnttzw */ 2482fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2483fcf5ef2aSThomas Huth { 24849b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 24859b8514e5SRichard Henderson 24869b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 24879b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 24889b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 24899b8514e5SRichard Henderson tcg_temp_free_i32(t); 24909b8514e5SRichard Henderson 2491fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2492fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2493fcf5ef2aSThomas Huth } 2494fcf5ef2aSThomas Huth } 2495fcf5ef2aSThomas Huth 2496fcf5ef2aSThomas Huth /* eqv & eqv. */ 2497fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2498fcf5ef2aSThomas Huth /* extsb & extsb. */ 2499fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2500fcf5ef2aSThomas Huth /* extsh & extsh. */ 2501fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2502fcf5ef2aSThomas Huth /* nand & nand. */ 2503fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2504fcf5ef2aSThomas Huth /* nor & nor. */ 2505fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2506fcf5ef2aSThomas Huth 2507fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2508fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2509fcf5ef2aSThomas Huth { 2510fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2511fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2512fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2513fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2514fcf5ef2aSThomas Huth 2515fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2516b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2517fcf5ef2aSThomas Huth } 2518fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2519fcf5ef2aSThomas Huth 2520fcf5ef2aSThomas Huth /* or & or. */ 2521fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2522fcf5ef2aSThomas Huth { 2523fcf5ef2aSThomas Huth int rs, ra, rb; 2524fcf5ef2aSThomas Huth 2525fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2526fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2527fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2528fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2529fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2530efe843d8SDavid Gibson if (rs != rb) { 2531fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2532efe843d8SDavid Gibson } else { 2533fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2534efe843d8SDavid Gibson } 2535efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2536fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2537efe843d8SDavid Gibson } 2538fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2539fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2540fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2541fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2542fcf5ef2aSThomas Huth int prio = 0; 2543fcf5ef2aSThomas Huth 2544fcf5ef2aSThomas Huth switch (rs) { 2545fcf5ef2aSThomas Huth case 1: 2546fcf5ef2aSThomas Huth /* Set process priority to low */ 2547fcf5ef2aSThomas Huth prio = 2; 2548fcf5ef2aSThomas Huth break; 2549fcf5ef2aSThomas Huth case 6: 2550fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2551fcf5ef2aSThomas Huth prio = 3; 2552fcf5ef2aSThomas Huth break; 2553fcf5ef2aSThomas Huth case 2: 2554fcf5ef2aSThomas Huth /* Set process priority to normal */ 2555fcf5ef2aSThomas Huth prio = 4; 2556fcf5ef2aSThomas Huth break; 2557fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2558fcf5ef2aSThomas Huth case 31: 2559fcf5ef2aSThomas Huth if (!ctx->pr) { 2560fcf5ef2aSThomas Huth /* Set process priority to very low */ 2561fcf5ef2aSThomas Huth prio = 1; 2562fcf5ef2aSThomas Huth } 2563fcf5ef2aSThomas Huth break; 2564fcf5ef2aSThomas Huth case 5: 2565fcf5ef2aSThomas Huth if (!ctx->pr) { 2566fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2567fcf5ef2aSThomas Huth prio = 5; 2568fcf5ef2aSThomas Huth } 2569fcf5ef2aSThomas Huth break; 2570fcf5ef2aSThomas Huth case 3: 2571fcf5ef2aSThomas Huth if (!ctx->pr) { 2572fcf5ef2aSThomas Huth /* Set process priority to high */ 2573fcf5ef2aSThomas Huth prio = 6; 2574fcf5ef2aSThomas Huth } 2575fcf5ef2aSThomas Huth break; 2576fcf5ef2aSThomas Huth case 7: 2577fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2578fcf5ef2aSThomas Huth /* Set process priority to very high */ 2579fcf5ef2aSThomas Huth prio = 7; 2580fcf5ef2aSThomas Huth } 2581fcf5ef2aSThomas Huth break; 2582fcf5ef2aSThomas Huth #endif 2583fcf5ef2aSThomas Huth default: 2584fcf5ef2aSThomas Huth break; 2585fcf5ef2aSThomas Huth } 2586fcf5ef2aSThomas Huth if (prio) { 2587fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2588fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2589fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2590fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2591fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2592fcf5ef2aSThomas Huth tcg_temp_free(t0); 2593fcf5ef2aSThomas Huth } 2594fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2595efe843d8SDavid Gibson /* 2596efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2597efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2598efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2599efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2600fcf5ef2aSThomas Huth */ 2601fcf5ef2aSThomas Huth gen_pause(ctx); 2602fcf5ef2aSThomas Huth #endif 2603fcf5ef2aSThomas Huth #endif 2604fcf5ef2aSThomas Huth } 2605fcf5ef2aSThomas Huth } 2606fcf5ef2aSThomas Huth /* orc & orc. */ 2607fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2608fcf5ef2aSThomas Huth 2609fcf5ef2aSThomas Huth /* xor & xor. */ 2610fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2611fcf5ef2aSThomas Huth { 2612fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2613efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2614efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2615efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2616efe843d8SDavid Gibson } else { 2617fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2618efe843d8SDavid Gibson } 2619efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2620fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2621fcf5ef2aSThomas Huth } 2622efe843d8SDavid Gibson } 2623fcf5ef2aSThomas Huth 2624fcf5ef2aSThomas Huth /* ori */ 2625fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2626fcf5ef2aSThomas Huth { 2627fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2628fcf5ef2aSThomas Huth 2629fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2630fcf5ef2aSThomas Huth return; 2631fcf5ef2aSThomas Huth } 2632fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2633fcf5ef2aSThomas Huth } 2634fcf5ef2aSThomas Huth 2635fcf5ef2aSThomas Huth /* oris */ 2636fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2637fcf5ef2aSThomas Huth { 2638fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2639fcf5ef2aSThomas Huth 2640fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2641fcf5ef2aSThomas Huth /* NOP */ 2642fcf5ef2aSThomas Huth return; 2643fcf5ef2aSThomas Huth } 2644efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2645efe843d8SDavid Gibson uimm << 16); 2646fcf5ef2aSThomas Huth } 2647fcf5ef2aSThomas Huth 2648fcf5ef2aSThomas Huth /* xori */ 2649fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2650fcf5ef2aSThomas Huth { 2651fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2652fcf5ef2aSThomas Huth 2653fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2654fcf5ef2aSThomas Huth /* NOP */ 2655fcf5ef2aSThomas Huth return; 2656fcf5ef2aSThomas Huth } 2657fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2658fcf5ef2aSThomas Huth } 2659fcf5ef2aSThomas Huth 2660fcf5ef2aSThomas Huth /* xoris */ 2661fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2662fcf5ef2aSThomas Huth { 2663fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2664fcf5ef2aSThomas Huth 2665fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2666fcf5ef2aSThomas Huth /* NOP */ 2667fcf5ef2aSThomas Huth return; 2668fcf5ef2aSThomas Huth } 2669efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2670efe843d8SDavid Gibson uimm << 16); 2671fcf5ef2aSThomas Huth } 2672fcf5ef2aSThomas Huth 2673fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2674fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2675fcf5ef2aSThomas Huth { 2676fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2677fcf5ef2aSThomas Huth } 2678fcf5ef2aSThomas Huth 2679fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2680fcf5ef2aSThomas Huth { 268179770002SRichard Henderson #if defined(TARGET_PPC64) 2682fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 268379770002SRichard Henderson #else 268479770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 268579770002SRichard Henderson #endif 2686fcf5ef2aSThomas Huth } 2687fcf5ef2aSThomas Huth 2688fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2689fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2690fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2691fcf5ef2aSThomas Huth { 269279770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2693fcf5ef2aSThomas Huth } 2694fcf5ef2aSThomas Huth #endif 2695fcf5ef2aSThomas Huth 2696fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2697fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2698fcf5ef2aSThomas Huth { 2699fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2700fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2701fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2702fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2703fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2704fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2705fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2706fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2707fcf5ef2aSThomas Huth tcg_temp_free(t0); 2708fcf5ef2aSThomas Huth } 2709fcf5ef2aSThomas Huth 2710fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2711fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2712fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2713fcf5ef2aSThomas Huth { 2714fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2715fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2716fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2717fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2718fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2719fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2720fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2721fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2722fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2723fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2724fcf5ef2aSThomas Huth tcg_temp_free(t0); 2725fcf5ef2aSThomas Huth } 2726fcf5ef2aSThomas Huth #endif 2727fcf5ef2aSThomas Huth 2728fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2729fcf5ef2aSThomas Huth /* bpermd */ 2730fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2731fcf5ef2aSThomas Huth { 2732fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2733fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2734fcf5ef2aSThomas Huth } 2735fcf5ef2aSThomas Huth #endif 2736fcf5ef2aSThomas Huth 2737fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2738fcf5ef2aSThomas Huth /* extsw & extsw. */ 2739fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2740fcf5ef2aSThomas Huth 2741fcf5ef2aSThomas Huth /* cntlzd */ 2742fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2743fcf5ef2aSThomas Huth { 27449b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2745efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2746fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2747fcf5ef2aSThomas Huth } 2748efe843d8SDavid Gibson } 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth /* cnttzd */ 2751fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2752fcf5ef2aSThomas Huth { 27539b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2754fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2755fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2756fcf5ef2aSThomas Huth } 2757fcf5ef2aSThomas Huth } 2758fcf5ef2aSThomas Huth 2759fcf5ef2aSThomas Huth /* darn */ 2760fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2761fcf5ef2aSThomas Huth { 2762fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2763fcf5ef2aSThomas Huth 27647e4357f6SRichard Henderson if (l > 2) { 27657e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 27667e4357f6SRichard Henderson } else { 2767f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2768fcf5ef2aSThomas Huth if (l == 0) { 2769fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 27707e4357f6SRichard Henderson } else { 2771fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2772fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 27737e4357f6SRichard Henderson } 2774fcf5ef2aSThomas Huth } 2775fcf5ef2aSThomas Huth } 2776fcf5ef2aSThomas Huth #endif 2777fcf5ef2aSThomas Huth 2778fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2779fcf5ef2aSThomas Huth 2780fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2781fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2782fcf5ef2aSThomas Huth { 2783fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2784fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2785fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2786fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2787fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2788fcf5ef2aSThomas Huth 2789fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2790fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2791fcf5ef2aSThomas Huth } else { 2792fcf5ef2aSThomas Huth target_ulong mask; 2793c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2794fcf5ef2aSThomas Huth TCGv t1; 2795fcf5ef2aSThomas Huth 2796fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2797fcf5ef2aSThomas Huth mb += 32; 2798fcf5ef2aSThomas Huth me += 32; 2799fcf5ef2aSThomas Huth #endif 2800fcf5ef2aSThomas Huth mask = MASK(mb, me); 2801fcf5ef2aSThomas Huth 2802c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2803c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2804c4f6a4a3SDaniele Buono mask_in_32b = false; 2805c4f6a4a3SDaniele Buono } 2806c4f6a4a3SDaniele Buono #endif 2807fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2808c4f6a4a3SDaniele Buono if (mask_in_32b) { 2809fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2810fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2811fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2812fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2813fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2814fcf5ef2aSThomas Huth } else { 2815fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2816fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2817fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2818fcf5ef2aSThomas Huth #else 2819fcf5ef2aSThomas Huth g_assert_not_reached(); 2820fcf5ef2aSThomas Huth #endif 2821fcf5ef2aSThomas Huth } 2822fcf5ef2aSThomas Huth 2823fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2824fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2825fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2826fcf5ef2aSThomas Huth tcg_temp_free(t1); 2827fcf5ef2aSThomas Huth } 2828fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2829fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2830fcf5ef2aSThomas Huth } 2831fcf5ef2aSThomas Huth } 2832fcf5ef2aSThomas Huth 2833fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2834fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2835fcf5ef2aSThomas Huth { 2836fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2837fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28387b4d326fSRichard Henderson int sh = SH(ctx->opcode); 28397b4d326fSRichard Henderson int mb = MB(ctx->opcode); 28407b4d326fSRichard Henderson int me = ME(ctx->opcode); 28417b4d326fSRichard Henderson int len = me - mb + 1; 28427b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2843fcf5ef2aSThomas Huth 28447b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 28457b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28467b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 28477b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2848fcf5ef2aSThomas Huth } else { 2849fcf5ef2aSThomas Huth target_ulong mask; 2850c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2851fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2852fcf5ef2aSThomas Huth mb += 32; 2853fcf5ef2aSThomas Huth me += 32; 2854fcf5ef2aSThomas Huth #endif 2855fcf5ef2aSThomas Huth mask = MASK(mb, me); 2856c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2857c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2858c4f6a4a3SDaniele Buono mask_in_32b = false; 2859c4f6a4a3SDaniele Buono } 2860c4f6a4a3SDaniele Buono #endif 2861c4f6a4a3SDaniele Buono if (mask_in_32b) { 28627b4d326fSRichard Henderson if (sh == 0) { 28637b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 286494f040aaSVitaly Chikunov } else { 2865fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2866fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2867fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2868fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2869fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2870fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 287194f040aaSVitaly Chikunov } 2872fcf5ef2aSThomas Huth } else { 2873fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2874fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2875fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2876fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2877fcf5ef2aSThomas Huth #else 2878fcf5ef2aSThomas Huth g_assert_not_reached(); 2879fcf5ef2aSThomas Huth #endif 2880fcf5ef2aSThomas Huth } 2881fcf5ef2aSThomas Huth } 2882fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2883fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2884fcf5ef2aSThomas Huth } 2885fcf5ef2aSThomas Huth } 2886fcf5ef2aSThomas Huth 2887fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2888fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2889fcf5ef2aSThomas Huth { 2890fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2891fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2892fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2893fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2894fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2895fcf5ef2aSThomas Huth target_ulong mask; 2896c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2897fcf5ef2aSThomas Huth 2898fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2899fcf5ef2aSThomas Huth mb += 32; 2900fcf5ef2aSThomas Huth me += 32; 2901fcf5ef2aSThomas Huth #endif 2902fcf5ef2aSThomas Huth mask = MASK(mb, me); 2903fcf5ef2aSThomas Huth 2904c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2905c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2906c4f6a4a3SDaniele Buono mask_in_32b = false; 2907c4f6a4a3SDaniele Buono } 2908c4f6a4a3SDaniele Buono #endif 2909c4f6a4a3SDaniele Buono if (mask_in_32b) { 2910fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2911fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2912fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2913fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2914fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2915fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2916fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2917fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2918fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2919fcf5ef2aSThomas Huth } else { 2920fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2921fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2922fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2923fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2924fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2925fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2926fcf5ef2aSThomas Huth #else 2927fcf5ef2aSThomas Huth g_assert_not_reached(); 2928fcf5ef2aSThomas Huth #endif 2929fcf5ef2aSThomas Huth } 2930fcf5ef2aSThomas Huth 2931fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2932fcf5ef2aSThomas Huth 2933fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2934fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2935fcf5ef2aSThomas Huth } 2936fcf5ef2aSThomas Huth } 2937fcf5ef2aSThomas Huth 2938fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2939fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2940fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2941fcf5ef2aSThomas Huth { \ 2942fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2943fcf5ef2aSThomas Huth } \ 2944fcf5ef2aSThomas Huth \ 2945fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2946fcf5ef2aSThomas Huth { \ 2947fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2948fcf5ef2aSThomas Huth } 2949fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2950fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2951fcf5ef2aSThomas Huth { \ 2952fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2953fcf5ef2aSThomas Huth } \ 2954fcf5ef2aSThomas Huth \ 2955fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2956fcf5ef2aSThomas Huth { \ 2957fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2958fcf5ef2aSThomas Huth } \ 2959fcf5ef2aSThomas Huth \ 2960fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2961fcf5ef2aSThomas Huth { \ 2962fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2963fcf5ef2aSThomas Huth } \ 2964fcf5ef2aSThomas Huth \ 2965fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2966fcf5ef2aSThomas Huth { \ 2967fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2968fcf5ef2aSThomas Huth } 2969fcf5ef2aSThomas Huth 2970fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2971fcf5ef2aSThomas Huth { 2972fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2973fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 29747b4d326fSRichard Henderson int len = me - mb + 1; 29757b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2976fcf5ef2aSThomas Huth 29777b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 29787b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 29797b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 29807b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2981fcf5ef2aSThomas Huth } else { 2982fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2983fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2984fcf5ef2aSThomas Huth } 2985fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2986fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2987fcf5ef2aSThomas Huth } 2988fcf5ef2aSThomas Huth } 2989fcf5ef2aSThomas Huth 2990fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2991fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2992fcf5ef2aSThomas Huth { 2993fcf5ef2aSThomas Huth uint32_t sh, mb; 2994fcf5ef2aSThomas Huth 2995fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2996fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2997fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2998fcf5ef2aSThomas Huth } 2999fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 3000fcf5ef2aSThomas Huth 3001fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 3002fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 3003fcf5ef2aSThomas Huth { 3004fcf5ef2aSThomas Huth uint32_t sh, me; 3005fcf5ef2aSThomas Huth 3006fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3007fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3008fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 3009fcf5ef2aSThomas Huth } 3010fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 3011fcf5ef2aSThomas Huth 3012fcf5ef2aSThomas Huth /* rldic - rldic. */ 3013fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 3014fcf5ef2aSThomas Huth { 3015fcf5ef2aSThomas Huth uint32_t sh, mb; 3016fcf5ef2aSThomas Huth 3017fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3018fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3019fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 3020fcf5ef2aSThomas Huth } 3021fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 3022fcf5ef2aSThomas Huth 3023fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 3024fcf5ef2aSThomas Huth { 3025fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3026fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3027fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3028fcf5ef2aSThomas Huth TCGv t0; 3029fcf5ef2aSThomas Huth 3030fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3031fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 3032fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 3033fcf5ef2aSThomas Huth tcg_temp_free(t0); 3034fcf5ef2aSThomas Huth 3035fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3036fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3037fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3038fcf5ef2aSThomas Huth } 3039fcf5ef2aSThomas Huth } 3040fcf5ef2aSThomas Huth 3041fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 3042fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 3043fcf5ef2aSThomas Huth { 3044fcf5ef2aSThomas Huth uint32_t mb; 3045fcf5ef2aSThomas Huth 3046fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3047fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 3048fcf5ef2aSThomas Huth } 3049fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 3050fcf5ef2aSThomas Huth 3051fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 3052fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 3053fcf5ef2aSThomas Huth { 3054fcf5ef2aSThomas Huth uint32_t me; 3055fcf5ef2aSThomas Huth 3056fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3057fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 3058fcf5ef2aSThomas Huth } 3059fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 3060fcf5ef2aSThomas Huth 3061fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 3062fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 3063fcf5ef2aSThomas Huth { 3064fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3065fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3066fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 3067fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 3068fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 3069fcf5ef2aSThomas Huth 3070fcf5ef2aSThomas Huth if (mb <= me) { 3071fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 3072fcf5ef2aSThomas Huth } else { 3073fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 3074fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3075fcf5ef2aSThomas Huth 3076fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 3077fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 3078fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 3079fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 3080fcf5ef2aSThomas Huth tcg_temp_free(t1); 3081fcf5ef2aSThomas Huth } 3082fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3083fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3084fcf5ef2aSThomas Huth } 3085fcf5ef2aSThomas Huth } 3086fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 3087fcf5ef2aSThomas Huth #endif 3088fcf5ef2aSThomas Huth 3089fcf5ef2aSThomas Huth /*** Integer shift ***/ 3090fcf5ef2aSThomas Huth 3091fcf5ef2aSThomas Huth /* slw & slw. */ 3092fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 3093fcf5ef2aSThomas Huth { 3094fcf5ef2aSThomas Huth TCGv t0, t1; 3095fcf5ef2aSThomas Huth 3096fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3097fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3098fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3099fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3100fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3101fcf5ef2aSThomas Huth #else 3102fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3103fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3104fcf5ef2aSThomas Huth #endif 3105fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3106fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3107fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3108fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3109fcf5ef2aSThomas Huth tcg_temp_free(t1); 3110fcf5ef2aSThomas Huth tcg_temp_free(t0); 3111fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 3112efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3113fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3114fcf5ef2aSThomas Huth } 3115efe843d8SDavid Gibson } 3116fcf5ef2aSThomas Huth 3117fcf5ef2aSThomas Huth /* sraw & sraw. */ 3118fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3119fcf5ef2aSThomas Huth { 3120fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3121fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3122efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3123fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3124fcf5ef2aSThomas Huth } 3125efe843d8SDavid Gibson } 3126fcf5ef2aSThomas Huth 3127fcf5ef2aSThomas Huth /* srawi & srawi. */ 3128fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3129fcf5ef2aSThomas Huth { 3130fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3131fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3132fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3133fcf5ef2aSThomas Huth if (sh == 0) { 3134fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3135fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3136af1c259fSSandipan Das if (is_isa300(ctx)) { 3137af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3138af1c259fSSandipan Das } 3139fcf5ef2aSThomas Huth } else { 3140fcf5ef2aSThomas Huth TCGv t0; 3141fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3142fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3143fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3144fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3145fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3146fcf5ef2aSThomas Huth tcg_temp_free(t0); 3147fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3148af1c259fSSandipan Das if (is_isa300(ctx)) { 3149af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3150af1c259fSSandipan Das } 3151fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3152fcf5ef2aSThomas Huth } 3153fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3154fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3155fcf5ef2aSThomas Huth } 3156fcf5ef2aSThomas Huth } 3157fcf5ef2aSThomas Huth 3158fcf5ef2aSThomas Huth /* srw & srw. */ 3159fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3160fcf5ef2aSThomas Huth { 3161fcf5ef2aSThomas Huth TCGv t0, t1; 3162fcf5ef2aSThomas Huth 3163fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3164fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3165fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3166fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3167fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3168fcf5ef2aSThomas Huth #else 3169fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3170fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3171fcf5ef2aSThomas Huth #endif 3172fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3173fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3174fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3175fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3176fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3177fcf5ef2aSThomas Huth tcg_temp_free(t1); 3178fcf5ef2aSThomas Huth tcg_temp_free(t0); 3179efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3180fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3181fcf5ef2aSThomas Huth } 3182efe843d8SDavid Gibson } 3183fcf5ef2aSThomas Huth 3184fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3185fcf5ef2aSThomas Huth /* sld & sld. */ 3186fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3187fcf5ef2aSThomas Huth { 3188fcf5ef2aSThomas Huth TCGv t0, t1; 3189fcf5ef2aSThomas Huth 3190fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3191fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3192fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3193fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3194fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3195fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3196fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3197fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3198fcf5ef2aSThomas Huth tcg_temp_free(t1); 3199fcf5ef2aSThomas Huth tcg_temp_free(t0); 3200efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3201fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3202fcf5ef2aSThomas Huth } 3203efe843d8SDavid Gibson } 3204fcf5ef2aSThomas Huth 3205fcf5ef2aSThomas Huth /* srad & srad. */ 3206fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3207fcf5ef2aSThomas Huth { 3208fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3209fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3210efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3211fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3212fcf5ef2aSThomas Huth } 3213efe843d8SDavid Gibson } 3214fcf5ef2aSThomas Huth /* sradi & sradi. */ 3215fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3216fcf5ef2aSThomas Huth { 3217fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3218fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3219fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3220fcf5ef2aSThomas Huth if (sh == 0) { 3221fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3222fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3223af1c259fSSandipan Das if (is_isa300(ctx)) { 3224af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3225af1c259fSSandipan Das } 3226fcf5ef2aSThomas Huth } else { 3227fcf5ef2aSThomas Huth TCGv t0; 3228fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3229fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3230fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3231fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3232fcf5ef2aSThomas Huth tcg_temp_free(t0); 3233fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3234af1c259fSSandipan Das if (is_isa300(ctx)) { 3235af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3236af1c259fSSandipan Das } 3237fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3238fcf5ef2aSThomas Huth } 3239fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3240fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3241fcf5ef2aSThomas Huth } 3242fcf5ef2aSThomas Huth } 3243fcf5ef2aSThomas Huth 3244fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3245fcf5ef2aSThomas Huth { 3246fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3247fcf5ef2aSThomas Huth } 3248fcf5ef2aSThomas Huth 3249fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3250fcf5ef2aSThomas Huth { 3251fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3252fcf5ef2aSThomas Huth } 3253fcf5ef2aSThomas Huth 3254fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3255fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3256fcf5ef2aSThomas Huth { 3257fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3258fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3259fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3260fcf5ef2aSThomas Huth 3261fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3262fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3263fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3264fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3265fcf5ef2aSThomas Huth } 3266fcf5ef2aSThomas Huth } 3267fcf5ef2aSThomas Huth 3268fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3269fcf5ef2aSThomas Huth { 3270fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3271fcf5ef2aSThomas Huth } 3272fcf5ef2aSThomas Huth 3273fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3274fcf5ef2aSThomas Huth { 3275fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3276fcf5ef2aSThomas Huth } 3277fcf5ef2aSThomas Huth 3278fcf5ef2aSThomas Huth /* srd & srd. */ 3279fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3280fcf5ef2aSThomas Huth { 3281fcf5ef2aSThomas Huth TCGv t0, t1; 3282fcf5ef2aSThomas Huth 3283fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3284fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3285fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3286fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3287fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3288fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3289fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3290fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3291fcf5ef2aSThomas Huth tcg_temp_free(t1); 3292fcf5ef2aSThomas Huth tcg_temp_free(t0); 3293efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3294fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3295fcf5ef2aSThomas Huth } 3296efe843d8SDavid Gibson } 3297fcf5ef2aSThomas Huth #endif 3298fcf5ef2aSThomas Huth 3299fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3300fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3301fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3302fcf5ef2aSThomas Huth target_long maskl) 3303fcf5ef2aSThomas Huth { 3304fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3305fcf5ef2aSThomas Huth 3306fcf5ef2aSThomas Huth simm &= ~maskl; 3307fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3308fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3309fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3310fcf5ef2aSThomas Huth } 3311fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3312fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3313fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3314fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3315fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3316fcf5ef2aSThomas Huth } 3317fcf5ef2aSThomas Huth } else { 3318fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3319fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3320fcf5ef2aSThomas Huth } else { 3321fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3322fcf5ef2aSThomas Huth } 3323fcf5ef2aSThomas Huth } 3324fcf5ef2aSThomas Huth } 3325fcf5ef2aSThomas Huth 3326fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3327fcf5ef2aSThomas Huth { 3328fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3329fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3330fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3331fcf5ef2aSThomas Huth } else { 3332fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3333fcf5ef2aSThomas Huth } 3334fcf5ef2aSThomas Huth } else { 3335fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3336fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3337fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3338fcf5ef2aSThomas Huth } 3339fcf5ef2aSThomas Huth } 3340fcf5ef2aSThomas Huth } 3341fcf5ef2aSThomas Huth 3342fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3343fcf5ef2aSThomas Huth { 3344fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3345fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3346fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3347fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3348fcf5ef2aSThomas Huth } else { 3349fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3350fcf5ef2aSThomas Huth } 3351fcf5ef2aSThomas Huth } 3352fcf5ef2aSThomas Huth 3353fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3354fcf5ef2aSThomas Huth target_long val) 3355fcf5ef2aSThomas Huth { 3356fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3357fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3358fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3359fcf5ef2aSThomas Huth } 3360fcf5ef2aSThomas Huth } 3361fcf5ef2aSThomas Huth 3362fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3363fcf5ef2aSThomas Huth { 3364fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3365fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3366fcf5ef2aSThomas Huth } 3367fcf5ef2aSThomas Huth 3368fcf5ef2aSThomas Huth /*** Integer load ***/ 3369fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3370fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3371fcf5ef2aSThomas Huth 3372fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3373fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3374fcf5ef2aSThomas Huth TCGv val, \ 3375fcf5ef2aSThomas Huth TCGv addr) \ 3376fcf5ef2aSThomas Huth { \ 3377fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3378fcf5ef2aSThomas Huth } 3379fcf5ef2aSThomas Huth 3380fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3381fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3382fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3383fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3384fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3385fcf5ef2aSThomas Huth 3386fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3387fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3388fcf5ef2aSThomas Huth 3389fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3390fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3391fcf5ef2aSThomas Huth TCGv_i64 val, \ 3392fcf5ef2aSThomas Huth TCGv addr) \ 3393fcf5ef2aSThomas Huth { \ 3394fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3395fcf5ef2aSThomas Huth } 3396fcf5ef2aSThomas Huth 3397fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3398fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3399fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3400fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3401fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3402fcf5ef2aSThomas Huth 3403fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3404fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3405fcf5ef2aSThomas Huth #endif 3406fcf5ef2aSThomas Huth 3407fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3408fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3409fcf5ef2aSThomas Huth TCGv val, \ 3410fcf5ef2aSThomas Huth TCGv addr) \ 3411fcf5ef2aSThomas Huth { \ 3412fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3413fcf5ef2aSThomas Huth } 3414fcf5ef2aSThomas Huth 3415fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3416fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3417fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3418fcf5ef2aSThomas Huth 3419fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3420fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3421fcf5ef2aSThomas Huth 3422fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3423fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3424fcf5ef2aSThomas Huth TCGv_i64 val, \ 3425fcf5ef2aSThomas Huth TCGv addr) \ 3426fcf5ef2aSThomas Huth { \ 3427fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3428fcf5ef2aSThomas Huth } 3429fcf5ef2aSThomas Huth 3430fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3431fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3432fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3433fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3434fcf5ef2aSThomas Huth 3435fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3436fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3437fcf5ef2aSThomas Huth #endif 3438fcf5ef2aSThomas Huth 3439fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 3440fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3441fcf5ef2aSThomas Huth { \ 3442fcf5ef2aSThomas Huth TCGv EA; \ 3443fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3444fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3445fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3446fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3447fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3448fcf5ef2aSThomas Huth } 3449fcf5ef2aSThomas Huth 3450fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 3451fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 3452fcf5ef2aSThomas Huth { \ 3453fcf5ef2aSThomas Huth TCGv EA; \ 3454fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3455fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3456fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3457fcf5ef2aSThomas Huth return; \ 3458fcf5ef2aSThomas Huth } \ 3459fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3460fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3461fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3462fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3463fcf5ef2aSThomas Huth else \ 3464fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3465fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3466fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3467fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3468fcf5ef2aSThomas Huth } 3469fcf5ef2aSThomas Huth 3470fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 3471fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3472fcf5ef2aSThomas Huth { \ 3473fcf5ef2aSThomas Huth TCGv EA; \ 3474fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3475fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3476fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3477fcf5ef2aSThomas Huth return; \ 3478fcf5ef2aSThomas Huth } \ 3479fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3480fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3481fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3482fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3483fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3484fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3485fcf5ef2aSThomas Huth } 3486fcf5ef2aSThomas Huth 3487fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3488fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3489fcf5ef2aSThomas Huth { \ 3490fcf5ef2aSThomas Huth TCGv EA; \ 3491fcf5ef2aSThomas Huth chk; \ 3492fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3493fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3494fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3495fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3496fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3497fcf5ef2aSThomas Huth } 3498fcf5ef2aSThomas Huth 3499fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3500fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3501fcf5ef2aSThomas Huth 3502fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3503fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3504fcf5ef2aSThomas Huth 3505fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 3506fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 3507fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 3508fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 3509fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 3510fcf5ef2aSThomas Huth 3511fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 3512fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 3513fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 3514fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 3515fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 3516fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 3517fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 3518fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 351950728199SRoman Kapl 352050728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 352150728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 352250728199SRoman Kapl { \ 352350728199SRoman Kapl TCGv EA; \ 352450728199SRoman Kapl CHK_SV; \ 352550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 352650728199SRoman Kapl EA = tcg_temp_new(); \ 352750728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 352850728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 352950728199SRoman Kapl tcg_temp_free(EA); \ 353050728199SRoman Kapl } 353150728199SRoman Kapl 353250728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 353350728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 353450728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 353550728199SRoman Kapl #if defined(TARGET_PPC64) 353650728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 353750728199SRoman Kapl #endif 353850728199SRoman Kapl 3539fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3540fcf5ef2aSThomas Huth /* lwaux */ 3541fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 3542fcf5ef2aSThomas Huth /* lwax */ 3543fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 3544fcf5ef2aSThomas Huth /* ldux */ 3545fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 3546fcf5ef2aSThomas Huth /* ldx */ 3547fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 3548fcf5ef2aSThomas Huth 3549fcf5ef2aSThomas Huth /* CI load/store variants */ 3550fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3551fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3552fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3553fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3554fcf5ef2aSThomas Huth 3555fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 3556fcf5ef2aSThomas Huth { 3557fcf5ef2aSThomas Huth TCGv EA; 3558fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3559fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 3560fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 3561fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3562fcf5ef2aSThomas Huth return; 3563fcf5ef2aSThomas Huth } 3564fcf5ef2aSThomas Huth } 3565fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3566fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3567fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3568fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 3569fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 3570fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3571fcf5ef2aSThomas Huth } else { 3572fcf5ef2aSThomas Huth /* ld - ldu */ 3573fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3574fcf5ef2aSThomas Huth } 3575efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3576fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3577efe843d8SDavid Gibson } 3578fcf5ef2aSThomas Huth tcg_temp_free(EA); 3579fcf5ef2aSThomas Huth } 3580fcf5ef2aSThomas Huth 3581fcf5ef2aSThomas Huth /* lq */ 3582fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3583fcf5ef2aSThomas Huth { 3584fcf5ef2aSThomas Huth int ra, rd; 358594bf2658SRichard Henderson TCGv EA, hi, lo; 3586fcf5ef2aSThomas Huth 3587fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3588fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3589fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3590fcf5ef2aSThomas Huth 3591fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3592fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3593fcf5ef2aSThomas Huth return; 3594fcf5ef2aSThomas Huth } 3595fcf5ef2aSThomas Huth 3596fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3597fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3598fcf5ef2aSThomas Huth return; 3599fcf5ef2aSThomas Huth } 3600fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3601fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3602fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3603fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3604fcf5ef2aSThomas Huth return; 3605fcf5ef2aSThomas Huth } 3606fcf5ef2aSThomas Huth 3607fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3608fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3609fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3610fcf5ef2aSThomas Huth 361194bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 361294bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 361394bf2658SRichard Henderson hi = cpu_gpr[rd]; 361494bf2658SRichard Henderson 361594bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3616f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 361794bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 361894bf2658SRichard Henderson if (ctx->le_mode) { 361994bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 362094bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3621fcf5ef2aSThomas Huth } else { 362294bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 362394bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 362494bf2658SRichard Henderson } 362594bf2658SRichard Henderson tcg_temp_free_i32(oi); 362694bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3627f34ec0f6SRichard Henderson } else { 362894bf2658SRichard Henderson /* Restart with exclusive lock. */ 362994bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 363094bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3631f34ec0f6SRichard Henderson } 363294bf2658SRichard Henderson } else if (ctx->le_mode) { 363394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3634fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 363594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 363694bf2658SRichard Henderson } else { 363794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 363894bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 363994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3640fcf5ef2aSThomas Huth } 3641fcf5ef2aSThomas Huth tcg_temp_free(EA); 3642fcf5ef2aSThomas Huth } 3643fcf5ef2aSThomas Huth #endif 3644fcf5ef2aSThomas Huth 3645fcf5ef2aSThomas Huth /*** Integer store ***/ 3646fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3647fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3648fcf5ef2aSThomas Huth { \ 3649fcf5ef2aSThomas Huth TCGv EA; \ 3650fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3651fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3652fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3653fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3654fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3655fcf5ef2aSThomas Huth } 3656fcf5ef2aSThomas Huth 3657fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3658fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3659fcf5ef2aSThomas Huth { \ 3660fcf5ef2aSThomas Huth TCGv EA; \ 3661fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3662fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3663fcf5ef2aSThomas Huth return; \ 3664fcf5ef2aSThomas Huth } \ 3665fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3666fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3667fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3668fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3669fcf5ef2aSThomas Huth else \ 3670fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3671fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3672fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3673fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3674fcf5ef2aSThomas Huth } 3675fcf5ef2aSThomas Huth 3676fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3677fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3678fcf5ef2aSThomas Huth { \ 3679fcf5ef2aSThomas Huth TCGv EA; \ 3680fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3681fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3682fcf5ef2aSThomas Huth return; \ 3683fcf5ef2aSThomas Huth } \ 3684fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3685fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3686fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3687fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3688fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3689fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3690fcf5ef2aSThomas Huth } 3691fcf5ef2aSThomas Huth 3692fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3693fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3694fcf5ef2aSThomas Huth { \ 3695fcf5ef2aSThomas Huth TCGv EA; \ 3696fcf5ef2aSThomas Huth chk; \ 3697fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3698fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3699fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3700fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3701fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3702fcf5ef2aSThomas Huth } 3703fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3704fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3705fcf5ef2aSThomas Huth 3706fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3707fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3708fcf5ef2aSThomas Huth 3709fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3710fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3711fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3712fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3713fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3714fcf5ef2aSThomas Huth 3715fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3716fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3717fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3718fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3719fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3720fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 372150728199SRoman Kapl 372250728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 372350728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 372450728199SRoman Kapl { \ 372550728199SRoman Kapl TCGv EA; \ 372650728199SRoman Kapl CHK_SV; \ 372750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 372850728199SRoman Kapl EA = tcg_temp_new(); \ 372950728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 373050728199SRoman Kapl tcg_gen_qemu_st_tl( \ 373150728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 373250728199SRoman Kapl tcg_temp_free(EA); \ 373350728199SRoman Kapl } 373450728199SRoman Kapl 373550728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 373650728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 373750728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 373850728199SRoman Kapl #if defined(TARGET_PPC64) 373950728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 374050728199SRoman Kapl #endif 374150728199SRoman Kapl 3742fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3743fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3744fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3745fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3746fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3747fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3748fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3749fcf5ef2aSThomas Huth 3750fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3751fcf5ef2aSThomas Huth { 3752fcf5ef2aSThomas Huth int rs; 3753fcf5ef2aSThomas Huth TCGv EA; 3754fcf5ef2aSThomas Huth 3755fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3756fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3757fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3758fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3759f89ced5fSRichard Henderson TCGv hi, lo; 3760fcf5ef2aSThomas Huth 3761fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3762fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3763fcf5ef2aSThomas Huth } 3764fcf5ef2aSThomas Huth 3765fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3766fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3767fcf5ef2aSThomas Huth return; 3768fcf5ef2aSThomas Huth } 3769fcf5ef2aSThomas Huth 3770fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3771fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3772fcf5ef2aSThomas Huth return; 3773fcf5ef2aSThomas Huth } 3774fcf5ef2aSThomas Huth 3775fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3776fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3777fcf5ef2aSThomas Huth return; 3778fcf5ef2aSThomas Huth } 3779fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3780fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3781fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3782fcf5ef2aSThomas Huth 3783f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3784f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3785f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3786f89ced5fSRichard Henderson 3787f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3788f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3789f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3790f89ced5fSRichard Henderson if (ctx->le_mode) { 3791f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3792f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3793fcf5ef2aSThomas Huth } else { 3794f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3795f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3796f89ced5fSRichard Henderson } 3797f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3798f34ec0f6SRichard Henderson } else { 3799f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3800f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3801f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3802f34ec0f6SRichard Henderson } 3803f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3804f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3805fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3806f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3807f89ced5fSRichard Henderson } else { 3808f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3809f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3810f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3811fcf5ef2aSThomas Huth } 3812fcf5ef2aSThomas Huth tcg_temp_free(EA); 3813fcf5ef2aSThomas Huth } else { 3814fcf5ef2aSThomas Huth /* std / stdu */ 3815fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3816fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3817fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3818fcf5ef2aSThomas Huth return; 3819fcf5ef2aSThomas Huth } 3820fcf5ef2aSThomas Huth } 3821fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3822fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3823fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3824fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3825efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3826fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3827efe843d8SDavid Gibson } 3828fcf5ef2aSThomas Huth tcg_temp_free(EA); 3829fcf5ef2aSThomas Huth } 3830fcf5ef2aSThomas Huth } 3831fcf5ef2aSThomas Huth #endif 3832fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3833fcf5ef2aSThomas Huth 3834fcf5ef2aSThomas Huth /* lhbrx */ 3835fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3836fcf5ef2aSThomas Huth 3837fcf5ef2aSThomas Huth /* lwbrx */ 3838fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3839fcf5ef2aSThomas Huth 3840fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3841fcf5ef2aSThomas Huth /* ldbrx */ 3842fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3843fcf5ef2aSThomas Huth /* stdbrx */ 3844fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3845fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3846fcf5ef2aSThomas Huth 3847fcf5ef2aSThomas Huth /* sthbrx */ 3848fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3849fcf5ef2aSThomas Huth /* stwbrx */ 3850fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3851fcf5ef2aSThomas Huth 3852fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3853fcf5ef2aSThomas Huth 3854fcf5ef2aSThomas Huth /* lmw */ 3855fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3856fcf5ef2aSThomas Huth { 3857fcf5ef2aSThomas Huth TCGv t0; 3858fcf5ef2aSThomas Huth TCGv_i32 t1; 3859fcf5ef2aSThomas Huth 3860fcf5ef2aSThomas Huth if (ctx->le_mode) { 3861fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3862fcf5ef2aSThomas Huth return; 3863fcf5ef2aSThomas Huth } 3864fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3865fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3866fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3867fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3868fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3869fcf5ef2aSThomas Huth tcg_temp_free(t0); 3870fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3871fcf5ef2aSThomas Huth } 3872fcf5ef2aSThomas Huth 3873fcf5ef2aSThomas Huth /* stmw */ 3874fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3875fcf5ef2aSThomas Huth { 3876fcf5ef2aSThomas Huth TCGv t0; 3877fcf5ef2aSThomas Huth TCGv_i32 t1; 3878fcf5ef2aSThomas Huth 3879fcf5ef2aSThomas Huth if (ctx->le_mode) { 3880fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3881fcf5ef2aSThomas Huth return; 3882fcf5ef2aSThomas Huth } 3883fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3884fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3885fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3886fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3887fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3888fcf5ef2aSThomas Huth tcg_temp_free(t0); 3889fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3890fcf5ef2aSThomas Huth } 3891fcf5ef2aSThomas Huth 3892fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3893fcf5ef2aSThomas Huth 3894fcf5ef2aSThomas Huth /* lswi */ 3895efe843d8SDavid Gibson /* 3896efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3897efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3898efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3899efe843d8SDavid Gibson * spec... 3900fcf5ef2aSThomas Huth */ 3901fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3902fcf5ef2aSThomas Huth { 3903fcf5ef2aSThomas Huth TCGv t0; 3904fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3905fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3906fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3907fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3908fcf5ef2aSThomas Huth int nr; 3909fcf5ef2aSThomas Huth 3910fcf5ef2aSThomas Huth if (ctx->le_mode) { 3911fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3912fcf5ef2aSThomas Huth return; 3913fcf5ef2aSThomas Huth } 3914efe843d8SDavid Gibson if (nb == 0) { 3915fcf5ef2aSThomas Huth nb = 32; 3916efe843d8SDavid Gibson } 3917f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3918fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3919fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3920fcf5ef2aSThomas Huth return; 3921fcf5ef2aSThomas Huth } 3922fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3923fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3924fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3925fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3926fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3927fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3928fcf5ef2aSThomas Huth tcg_temp_free(t0); 3929fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3930fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3931fcf5ef2aSThomas Huth } 3932fcf5ef2aSThomas Huth 3933fcf5ef2aSThomas Huth /* lswx */ 3934fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3935fcf5ef2aSThomas Huth { 3936fcf5ef2aSThomas Huth TCGv t0; 3937fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3938fcf5ef2aSThomas Huth 3939fcf5ef2aSThomas Huth if (ctx->le_mode) { 3940fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3941fcf5ef2aSThomas Huth return; 3942fcf5ef2aSThomas Huth } 3943fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3944fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3945fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3946fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3947fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3948fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3949fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3950fcf5ef2aSThomas Huth tcg_temp_free(t0); 3951fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3952fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3953fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3954fcf5ef2aSThomas Huth } 3955fcf5ef2aSThomas Huth 3956fcf5ef2aSThomas Huth /* stswi */ 3957fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3958fcf5ef2aSThomas Huth { 3959fcf5ef2aSThomas Huth TCGv t0; 3960fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3961fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3962fcf5ef2aSThomas Huth 3963fcf5ef2aSThomas Huth if (ctx->le_mode) { 3964fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3965fcf5ef2aSThomas Huth return; 3966fcf5ef2aSThomas Huth } 3967fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3968fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3969fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3970efe843d8SDavid Gibson if (nb == 0) { 3971fcf5ef2aSThomas Huth nb = 32; 3972efe843d8SDavid Gibson } 3973fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3974fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3975fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3976fcf5ef2aSThomas Huth tcg_temp_free(t0); 3977fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3978fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3979fcf5ef2aSThomas Huth } 3980fcf5ef2aSThomas Huth 3981fcf5ef2aSThomas Huth /* stswx */ 3982fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3983fcf5ef2aSThomas Huth { 3984fcf5ef2aSThomas Huth TCGv t0; 3985fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3986fcf5ef2aSThomas Huth 3987fcf5ef2aSThomas Huth if (ctx->le_mode) { 3988fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3989fcf5ef2aSThomas Huth return; 3990fcf5ef2aSThomas Huth } 3991fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3992fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3993fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3994fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3995fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3996fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3997fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3998fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3999fcf5ef2aSThomas Huth tcg_temp_free(t0); 4000fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4001fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4002fcf5ef2aSThomas Huth } 4003fcf5ef2aSThomas Huth 4004fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 4005fcf5ef2aSThomas Huth /* eieio */ 4006fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 4007fcf5ef2aSThomas Huth { 4008c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 4009c8fd8373SCédric Le Goater 4010c8fd8373SCédric Le Goater /* 4011c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 4012c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 4013c8fd8373SCédric Le Goater */ 4014c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 4015c8fd8373SCédric Le Goater /* 4016c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 4017c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 4018c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 4019c8fd8373SCédric Le Goater * complain to the user. 4020c8fd8373SCédric Le Goater */ 4021c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 4022c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 40232c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 4024c8fd8373SCédric Le Goater } else { 4025c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 4026c8fd8373SCédric Le Goater } 4027c8fd8373SCédric Le Goater } 4028c8fd8373SCédric Le Goater 4029c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 4030fcf5ef2aSThomas Huth } 4031fcf5ef2aSThomas Huth 4032fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4033fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 4034fcf5ef2aSThomas Huth { 4035fcf5ef2aSThomas Huth TCGv_i32 t; 4036fcf5ef2aSThomas Huth TCGLabel *l; 4037fcf5ef2aSThomas Huth 4038fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 4039fcf5ef2aSThomas Huth return; 4040fcf5ef2aSThomas Huth } 4041fcf5ef2aSThomas Huth l = gen_new_label(); 4042fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 4043fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4044fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 4045fcf5ef2aSThomas Huth if (global) { 4046fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 4047fcf5ef2aSThomas Huth } else { 4048fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 4049fcf5ef2aSThomas Huth } 4050fcf5ef2aSThomas Huth gen_set_label(l); 4051fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4052fcf5ef2aSThomas Huth } 4053fcf5ef2aSThomas Huth #else 4054fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 4055fcf5ef2aSThomas Huth #endif 4056fcf5ef2aSThomas Huth 4057fcf5ef2aSThomas Huth /* isync */ 4058fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 4059fcf5ef2aSThomas Huth { 4060fcf5ef2aSThomas Huth /* 4061fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 4062fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 4063fcf5ef2aSThomas Huth */ 4064fcf5ef2aSThomas Huth if (!ctx->pr) { 4065fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 4066fcf5ef2aSThomas Huth } 40674771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4068d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4069fcf5ef2aSThomas Huth } 4070fcf5ef2aSThomas Huth 4071fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 4072fcf5ef2aSThomas Huth 407314776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 40742a4e6c1bSRichard Henderson { 40752a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 40762a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 40772a4e6c1bSRichard Henderson 40782a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 40792a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 40802a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 40812a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 40822a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 40832a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 40842a4e6c1bSRichard Henderson tcg_temp_free(t0); 40852a4e6c1bSRichard Henderson } 40862a4e6c1bSRichard Henderson 4087fcf5ef2aSThomas Huth #define LARX(name, memop) \ 4088fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4089fcf5ef2aSThomas Huth { \ 40902a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 4091fcf5ef2aSThomas Huth } 4092fcf5ef2aSThomas Huth 4093fcf5ef2aSThomas Huth /* lwarx */ 4094fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 4095fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 4096fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 4097fcf5ef2aSThomas Huth 409814776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 409920923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 410020923c1dSRichard Henderson { 410120923c1dSRichard Henderson TCGv t = tcg_temp_new(); 410220923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 410320923c1dSRichard Henderson TCGv u = tcg_temp_new(); 410420923c1dSRichard Henderson 410520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 410620923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 410720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 410820923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 410920923c1dSRichard Henderson 411020923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 411120923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 411220923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 411320923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 411420923c1dSRichard Henderson 411520923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 411620923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 411720923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 411820923c1dSRichard Henderson 411920923c1dSRichard Henderson tcg_temp_free(t); 412020923c1dSRichard Henderson tcg_temp_free(t2); 412120923c1dSRichard Henderson tcg_temp_free(u); 412220923c1dSRichard Henderson } 412320923c1dSRichard Henderson 412414776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 412520ba8504SRichard Henderson { 412620ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 412720ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 412820923c1dSRichard Henderson int rt = rD(ctx->opcode); 412920923c1dSRichard Henderson bool need_serial; 413020ba8504SRichard Henderson TCGv src, dst; 413120ba8504SRichard Henderson 413220ba8504SRichard Henderson gen_addr_register(ctx, EA); 413320923c1dSRichard Henderson dst = cpu_gpr[rt]; 413420923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 413520ba8504SRichard Henderson 413620923c1dSRichard Henderson need_serial = false; 413720ba8504SRichard Henderson memop |= MO_ALIGN; 413820ba8504SRichard Henderson switch (gpr_FC) { 413920ba8504SRichard Henderson case 0: /* Fetch and add */ 414020ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 414120ba8504SRichard Henderson break; 414220ba8504SRichard Henderson case 1: /* Fetch and xor */ 414320ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 414420ba8504SRichard Henderson break; 414520ba8504SRichard Henderson case 2: /* Fetch and or */ 414620ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 414720ba8504SRichard Henderson break; 414820ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 414920ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 415020ba8504SRichard Henderson break; 4151b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 4152b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 4153b8ce0f86SRichard Henderson break; 4154b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 4155b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 4156b8ce0f86SRichard Henderson break; 4157b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 4158b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 4159b8ce0f86SRichard Henderson break; 4160b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 4161b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 4162b8ce0f86SRichard Henderson break; 416320ba8504SRichard Henderson case 8: /* Swap */ 416420ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 416520ba8504SRichard Henderson break; 416620923c1dSRichard Henderson 416720923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 416820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 416920923c1dSRichard Henderson need_serial = true; 417020923c1dSRichard Henderson } else { 417120923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 417220923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 417320923c1dSRichard Henderson 417420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 417520923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 417620923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 417720923c1dSRichard Henderson } else { 417820923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 417920923c1dSRichard Henderson } 418020923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 418120923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 418220923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 418320923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 418420923c1dSRichard Henderson 418520923c1dSRichard Henderson tcg_temp_free(t0); 418620923c1dSRichard Henderson tcg_temp_free(t1); 418720923c1dSRichard Henderson } 418820ba8504SRichard Henderson break; 418920923c1dSRichard Henderson 419020923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 419120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 419220923c1dSRichard Henderson need_serial = true; 419320923c1dSRichard Henderson } else { 419420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 419520923c1dSRichard Henderson } 419620923c1dSRichard Henderson break; 419720923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 419820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 419920923c1dSRichard Henderson need_serial = true; 420020923c1dSRichard Henderson } else { 420120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 420220923c1dSRichard Henderson } 420320923c1dSRichard Henderson break; 420420923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 420520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 420620923c1dSRichard Henderson need_serial = true; 420720923c1dSRichard Henderson } else { 420820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 420920923c1dSRichard Henderson } 421020923c1dSRichard Henderson break; 421120923c1dSRichard Henderson 421220ba8504SRichard Henderson default: 421320ba8504SRichard Henderson /* invoke data storage error handler */ 421420ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 421520ba8504SRichard Henderson } 421620ba8504SRichard Henderson tcg_temp_free(EA); 421720923c1dSRichard Henderson 421820923c1dSRichard Henderson if (need_serial) { 421920923c1dSRichard Henderson /* Restart with exclusive lock. */ 422020923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 422120923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 422220923c1dSRichard Henderson } 4223a68a6146SBalamuruhan S } 4224a68a6146SBalamuruhan S 422520ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 422620ba8504SRichard Henderson { 422720ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 422820ba8504SRichard Henderson } 422920ba8504SRichard Henderson 423020ba8504SRichard Henderson #ifdef TARGET_PPC64 423120ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 423220ba8504SRichard Henderson { 423320ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 423420ba8504SRichard Henderson } 4235a68a6146SBalamuruhan S #endif 4236a68a6146SBalamuruhan S 423714776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 42389deb041cSRichard Henderson { 42399deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 42409deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 42419deb041cSRichard Henderson TCGv src, discard; 42429deb041cSRichard Henderson 42439deb041cSRichard Henderson gen_addr_register(ctx, EA); 42449deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 42459deb041cSRichard Henderson discard = tcg_temp_new(); 42469deb041cSRichard Henderson 42479deb041cSRichard Henderson memop |= MO_ALIGN; 42489deb041cSRichard Henderson switch (gpr_FC) { 42499deb041cSRichard Henderson case 0: /* add and Store */ 42509deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 42519deb041cSRichard Henderson break; 42529deb041cSRichard Henderson case 1: /* xor and Store */ 42539deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 42549deb041cSRichard Henderson break; 42559deb041cSRichard Henderson case 2: /* Or and Store */ 42569deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 42579deb041cSRichard Henderson break; 42589deb041cSRichard Henderson case 3: /* 'and' and Store */ 42599deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 42609deb041cSRichard Henderson break; 42619deb041cSRichard Henderson case 4: /* Store max unsigned */ 4262b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4263b8ce0f86SRichard Henderson break; 42649deb041cSRichard Henderson case 5: /* Store max signed */ 4265b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4266b8ce0f86SRichard Henderson break; 42679deb041cSRichard Henderson case 6: /* Store min unsigned */ 4268b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4269b8ce0f86SRichard Henderson break; 42709deb041cSRichard Henderson case 7: /* Store min signed */ 4271b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4272b8ce0f86SRichard Henderson break; 42739deb041cSRichard Henderson case 24: /* Store twin */ 42747fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 42757fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 42767fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 42777fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 42787fbc2b20SRichard Henderson } else { 42797fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 42807fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 42817fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 42827fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 42837fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 42847fbc2b20SRichard Henderson 42857fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 42867fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 42877fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 42887fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 42897fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 42907fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 42917fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 42927fbc2b20SRichard Henderson 42937fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 42947fbc2b20SRichard Henderson tcg_temp_free(s2); 42957fbc2b20SRichard Henderson tcg_temp_free(s); 42967fbc2b20SRichard Henderson tcg_temp_free(t2); 42977fbc2b20SRichard Henderson tcg_temp_free(t); 42987fbc2b20SRichard Henderson } 42999deb041cSRichard Henderson break; 43009deb041cSRichard Henderson default: 43019deb041cSRichard Henderson /* invoke data storage error handler */ 43029deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 43039deb041cSRichard Henderson } 43049deb041cSRichard Henderson tcg_temp_free(discard); 43059deb041cSRichard Henderson tcg_temp_free(EA); 4306a3401188SBalamuruhan S } 4307a3401188SBalamuruhan S 43089deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 43099deb041cSRichard Henderson { 43109deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 43119deb041cSRichard Henderson } 43129deb041cSRichard Henderson 43139deb041cSRichard Henderson #ifdef TARGET_PPC64 43149deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 43159deb041cSRichard Henderson { 43169deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 43179deb041cSRichard Henderson } 4318a3401188SBalamuruhan S #endif 4319a3401188SBalamuruhan S 432014776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4321fcf5ef2aSThomas Huth { 4322253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4323253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4324d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4325d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4326fcf5ef2aSThomas Huth 4327d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4328d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4329d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4330d8b86898SRichard Henderson tcg_temp_free(t0); 4331253ce7b2SNikunj A Dadhania 4332253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4333253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4334253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4335253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4336253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4337253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4338253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4339253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4340253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4341253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4342253ce7b2SNikunj A Dadhania 4343fcf5ef2aSThomas Huth gen_set_label(l1); 43444771df23SNikunj A Dadhania 4345efe843d8SDavid Gibson /* 4346efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4347efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4348efe843d8SDavid Gibson */ 43494771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4350253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4351253ce7b2SNikunj A Dadhania 4352253ce7b2SNikunj A Dadhania gen_set_label(l2); 4353fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4354fcf5ef2aSThomas Huth } 4355fcf5ef2aSThomas Huth 4356fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4357fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4358fcf5ef2aSThomas Huth { \ 4359d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4360fcf5ef2aSThomas Huth } 4361fcf5ef2aSThomas Huth 4362fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4363fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4364fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4365fcf5ef2aSThomas Huth 4366fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4367fcf5ef2aSThomas Huth /* ldarx */ 4368fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4369fcf5ef2aSThomas Huth /* stdcx. */ 4370fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4371fcf5ef2aSThomas Huth 4372fcf5ef2aSThomas Huth /* lqarx */ 4373fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4374fcf5ef2aSThomas Huth { 4375fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 437694bf2658SRichard Henderson TCGv EA, hi, lo; 4377fcf5ef2aSThomas Huth 4378fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4379fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4380fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4381fcf5ef2aSThomas Huth return; 4382fcf5ef2aSThomas Huth } 4383fcf5ef2aSThomas Huth 4384fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 438594bf2658SRichard Henderson EA = tcg_temp_new(); 4386fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 438794bf2658SRichard Henderson 438894bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 438994bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 439094bf2658SRichard Henderson hi = cpu_gpr[rd]; 439194bf2658SRichard Henderson 439294bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4393f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 439494bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 439594bf2658SRichard Henderson if (ctx->le_mode) { 439694bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 439794bf2658SRichard Henderson ctx->mem_idx)); 439894bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4399fcf5ef2aSThomas Huth } else { 440094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 440194bf2658SRichard Henderson ctx->mem_idx)); 440294bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4403fcf5ef2aSThomas Huth } 440494bf2658SRichard Henderson tcg_temp_free_i32(oi); 440594bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4406f34ec0f6SRichard Henderson } else { 440794bf2658SRichard Henderson /* Restart with exclusive lock. */ 440894bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 440994bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 441094bf2658SRichard Henderson tcg_temp_free(EA); 441194bf2658SRichard Henderson return; 4412f34ec0f6SRichard Henderson } 441394bf2658SRichard Henderson } else if (ctx->le_mode) { 441494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4415fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4416fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 441794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 441894bf2658SRichard Henderson } else { 441994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 442094bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 442194bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 442294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 442394bf2658SRichard Henderson } 4424fcf5ef2aSThomas Huth tcg_temp_free(EA); 442594bf2658SRichard Henderson 442694bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 442794bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4428fcf5ef2aSThomas Huth } 4429fcf5ef2aSThomas Huth 4430fcf5ef2aSThomas Huth /* stqcx. */ 4431fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4432fcf5ef2aSThomas Huth { 44334a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 44344a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4435fcf5ef2aSThomas Huth 44364a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4437fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4438fcf5ef2aSThomas Huth return; 4439fcf5ef2aSThomas Huth } 44404a9b3c5dSRichard Henderson 4441fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 44424a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4443fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4444fcf5ef2aSThomas Huth 44454a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 44464a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 44474a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4448fcf5ef2aSThomas Huth 44494a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4450f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 44514a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 44524a9b3c5dSRichard Henderson if (ctx->le_mode) { 4453f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4454f34ec0f6SRichard Henderson EA, lo, hi, oi); 4455fcf5ef2aSThomas Huth } else { 4456f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4457f34ec0f6SRichard Henderson EA, lo, hi, oi); 4458fcf5ef2aSThomas Huth } 4459f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4460f34ec0f6SRichard Henderson } else { 44614a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 44624a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 44634a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4464f34ec0f6SRichard Henderson } 4465fcf5ef2aSThomas Huth tcg_temp_free(EA); 44664a9b3c5dSRichard Henderson } else { 44674a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 44684a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 44694a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 44704a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4471fcf5ef2aSThomas Huth 44724a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 44734a9b3c5dSRichard Henderson tcg_temp_free(EA); 44744a9b3c5dSRichard Henderson 44754a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 44764a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 44774a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 44784a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 44794a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 44804a9b3c5dSRichard Henderson 44814a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 44824a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 44834a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 44844a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 44854a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 44864a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 44874a9b3c5dSRichard Henderson 44884a9b3c5dSRichard Henderson /* Success */ 44894a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 44904a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 44914a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 44924a9b3c5dSRichard Henderson 44934a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 44944a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 44954a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 44964a9b3c5dSRichard Henderson 44974a9b3c5dSRichard Henderson gen_set_label(lab_fail); 44984a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 44994a9b3c5dSRichard Henderson 45004a9b3c5dSRichard Henderson gen_set_label(lab_over); 45014a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 45024a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 45034a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 45044a9b3c5dSRichard Henderson } 45054a9b3c5dSRichard Henderson } 4506fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4507fcf5ef2aSThomas Huth 4508fcf5ef2aSThomas Huth /* sync */ 4509fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4510fcf5ef2aSThomas Huth { 4511fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4512fcf5ef2aSThomas Huth 4513fcf5ef2aSThomas Huth /* 4514fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4515fcf5ef2aSThomas Huth * 4516fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4517fcf5ef2aSThomas Huth * 4518fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4519fcf5ef2aSThomas Huth * check MSR_PR as well. 4520fcf5ef2aSThomas Huth */ 4521fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4522fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4523fcf5ef2aSThomas Huth } 45244771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4525fcf5ef2aSThomas Huth } 4526fcf5ef2aSThomas Huth 4527fcf5ef2aSThomas Huth /* wait */ 4528fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4529fcf5ef2aSThomas Huth { 4530fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4531fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4532fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4533fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4534fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4535b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4536fcf5ef2aSThomas Huth } 4537fcf5ef2aSThomas Huth 4538fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4539fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4540fcf5ef2aSThomas Huth { 4541fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4542fcf5ef2aSThomas Huth GEN_PRIV; 4543fcf5ef2aSThomas Huth #else 4544fcf5ef2aSThomas Huth TCGv_i32 t; 4545fcf5ef2aSThomas Huth 4546fcf5ef2aSThomas Huth CHK_HV; 4547fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4548fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4549fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4550154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4551154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4552fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4553fcf5ef2aSThomas Huth } 4554fcf5ef2aSThomas Huth 4555fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4556fcf5ef2aSThomas Huth { 4557fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4558fcf5ef2aSThomas Huth GEN_PRIV; 4559fcf5ef2aSThomas Huth #else 4560fcf5ef2aSThomas Huth TCGv_i32 t; 4561fcf5ef2aSThomas Huth 4562fcf5ef2aSThomas Huth CHK_HV; 4563fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4564fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4565fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4566154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4567154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4568fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4569fcf5ef2aSThomas Huth } 4570fcf5ef2aSThomas Huth 4571cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4572cdee0e72SNikunj A Dadhania { 457321c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 457421c0d66aSBenjamin Herrenschmidt GEN_PRIV; 457521c0d66aSBenjamin Herrenschmidt #else 457621c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 457721c0d66aSBenjamin Herrenschmidt 457821c0d66aSBenjamin Herrenschmidt CHK_HV; 457921c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 458021c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 458121c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 458221c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 458321c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 458421c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4585cdee0e72SNikunj A Dadhania } 4586cdee0e72SNikunj A Dadhania 4587fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4588fcf5ef2aSThomas Huth { 4589fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4590fcf5ef2aSThomas Huth GEN_PRIV; 4591fcf5ef2aSThomas Huth #else 4592fcf5ef2aSThomas Huth TCGv_i32 t; 4593fcf5ef2aSThomas Huth 4594fcf5ef2aSThomas Huth CHK_HV; 4595fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4596fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4597fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4598154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4599154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4600fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4601fcf5ef2aSThomas Huth } 4602fcf5ef2aSThomas Huth 4603fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4604fcf5ef2aSThomas Huth { 4605fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4606fcf5ef2aSThomas Huth GEN_PRIV; 4607fcf5ef2aSThomas Huth #else 4608fcf5ef2aSThomas Huth TCGv_i32 t; 4609fcf5ef2aSThomas Huth 4610fcf5ef2aSThomas Huth CHK_HV; 4611fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4612fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4613fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4614154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4615154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4616fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4617fcf5ef2aSThomas Huth } 4618fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4619fcf5ef2aSThomas Huth 4620fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4621fcf5ef2aSThomas Huth { 4622fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4623efe843d8SDavid Gibson if (ctx->has_cfar) { 4624fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4625efe843d8SDavid Gibson } 4626fcf5ef2aSThomas Huth #endif 4627fcf5ef2aSThomas Huth } 4628fcf5ef2aSThomas Huth 4629fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4630fcf5ef2aSThomas Huth { 4631fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4632fcf5ef2aSThomas Huth return false; 4633fcf5ef2aSThomas Huth } 4634fcf5ef2aSThomas Huth 4635fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4636b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4637fcf5ef2aSThomas Huth #else 4638fcf5ef2aSThomas Huth return true; 4639fcf5ef2aSThomas Huth #endif 4640fcf5ef2aSThomas Huth } 4641fcf5ef2aSThomas Huth 46420e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 46430e3bf489SRoman Kapl { 46440e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 46450e3bf489SRoman Kapl if (unlikely(sse)) { 46460e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 46470e3bf489SRoman Kapl gen_debug_exception(ctx); 46480e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4649e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 46500e3bf489SRoman Kapl gen_exception(ctx, excp); 46510e3bf489SRoman Kapl } 46520e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 46530e3bf489SRoman Kapl } else { 46540e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 46550e3bf489SRoman Kapl } 46560e3bf489SRoman Kapl } 46570e3bf489SRoman Kapl 4658fcf5ef2aSThomas Huth /*** Branch ***/ 4659c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4660fcf5ef2aSThomas Huth { 4661fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4662fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4663fcf5ef2aSThomas Huth } 4664fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4665fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4666fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 466707ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4668fcf5ef2aSThomas Huth } else { 4669fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 46700e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4671fcf5ef2aSThomas Huth } 4672fcf5ef2aSThomas Huth } 4673fcf5ef2aSThomas Huth 4674fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4675fcf5ef2aSThomas Huth { 4676fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4677fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4678fcf5ef2aSThomas Huth } 4679fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth 4682fcf5ef2aSThomas Huth /* b ba bl bla */ 4683fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4684fcf5ef2aSThomas Huth { 4685fcf5ef2aSThomas Huth target_ulong li, target; 4686fcf5ef2aSThomas Huth 4687fcf5ef2aSThomas Huth /* sign extend LI */ 4688fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4689fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4690fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 46912c2bcb1bSRichard Henderson target = ctx->cia + li; 4692fcf5ef2aSThomas Huth } else { 4693fcf5ef2aSThomas Huth target = li; 4694fcf5ef2aSThomas Huth } 4695fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4696b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4697fcf5ef2aSThomas Huth } 46982c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4699fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 47006086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4701fcf5ef2aSThomas Huth } 4702fcf5ef2aSThomas Huth 4703fcf5ef2aSThomas Huth #define BCOND_IM 0 4704fcf5ef2aSThomas Huth #define BCOND_LR 1 4705fcf5ef2aSThomas Huth #define BCOND_CTR 2 4706fcf5ef2aSThomas Huth #define BCOND_TAR 3 4707fcf5ef2aSThomas Huth 4708c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4709fcf5ef2aSThomas Huth { 4710fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4711fcf5ef2aSThomas Huth TCGLabel *l1; 4712fcf5ef2aSThomas Huth TCGv target; 47130e3bf489SRoman Kapl 4714fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4715fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4716efe843d8SDavid Gibson if (type == BCOND_CTR) { 4717fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4718efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4719fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4720efe843d8SDavid Gibson } else { 4721fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4722efe843d8SDavid Gibson } 4723fcf5ef2aSThomas Huth } else { 4724f764718dSRichard Henderson target = NULL; 4725fcf5ef2aSThomas Huth } 4726efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4727b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4728efe843d8SDavid Gibson } 4729fcf5ef2aSThomas Huth l1 = gen_new_label(); 4730fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4731fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4732fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4733fa200c95SGreg Kurz 4734fa200c95SGreg Kurz if (type == BCOND_CTR) { 4735fa200c95SGreg Kurz /* 4736fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4737fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4738fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 473915d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 474015d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 474115d68c5eSGreg Kurz * it basically useless and thus never used in real code. 474215d68c5eSGreg Kurz * 474315d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 474415d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 474515d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 474615d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 474715d68c5eSGreg Kurz * doing anything else harmful. 4748fa200c95SGreg Kurz */ 4749d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4750fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 47519acc95cdSGreg Kurz tcg_temp_free(temp); 47529acc95cdSGreg Kurz tcg_temp_free(target); 4753fcf5ef2aSThomas Huth return; 4754fcf5ef2aSThomas Huth } 4755fa200c95SGreg Kurz 4756fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4757fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4758fa200c95SGreg Kurz } else { 4759fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4760fa200c95SGreg Kurz } 4761fa200c95SGreg Kurz if (bo & 0x2) { 4762fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4763fa200c95SGreg Kurz } else { 4764fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4765fa200c95SGreg Kurz } 4766fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4767fa200c95SGreg Kurz } else { 4768fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4769fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4770fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4771fcf5ef2aSThomas Huth } else { 4772fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4773fcf5ef2aSThomas Huth } 4774fcf5ef2aSThomas Huth if (bo & 0x2) { 4775fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4776fcf5ef2aSThomas Huth } else { 4777fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4778fcf5ef2aSThomas Huth } 4779fa200c95SGreg Kurz } 4780fcf5ef2aSThomas Huth tcg_temp_free(temp); 4781fcf5ef2aSThomas Huth } 4782fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4783fcf5ef2aSThomas Huth /* Test CR */ 4784fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4785fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4786fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4787fcf5ef2aSThomas Huth 4788fcf5ef2aSThomas Huth if (bo & 0x8) { 4789fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4790fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4791fcf5ef2aSThomas Huth } else { 4792fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4793fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4794fcf5ef2aSThomas Huth } 4795fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4796fcf5ef2aSThomas Huth } 47972c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4798fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4799fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4800fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 48012c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4802fcf5ef2aSThomas Huth } else { 4803fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4804fcf5ef2aSThomas Huth } 4805fcf5ef2aSThomas Huth } else { 4806fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4807fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4808fcf5ef2aSThomas Huth } else { 4809fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4810fcf5ef2aSThomas Huth } 48110e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4812c4a2e3a9SRichard Henderson tcg_temp_free(target); 4813c4a2e3a9SRichard Henderson } 4814fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 48150e3bf489SRoman Kapl /* fallthrough case */ 4816fcf5ef2aSThomas Huth gen_set_label(l1); 4817b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4818fcf5ef2aSThomas Huth } 48196086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4820fcf5ef2aSThomas Huth } 4821fcf5ef2aSThomas Huth 4822fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4823fcf5ef2aSThomas Huth { 4824fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4825fcf5ef2aSThomas Huth } 4826fcf5ef2aSThomas Huth 4827fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4828fcf5ef2aSThomas Huth { 4829fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4830fcf5ef2aSThomas Huth } 4831fcf5ef2aSThomas Huth 4832fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4833fcf5ef2aSThomas Huth { 4834fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4835fcf5ef2aSThomas Huth } 4836fcf5ef2aSThomas Huth 4837fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4838fcf5ef2aSThomas Huth { 4839fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4840fcf5ef2aSThomas Huth } 4841fcf5ef2aSThomas Huth 4842fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4843fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4844fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4845fcf5ef2aSThomas Huth { \ 4846fcf5ef2aSThomas Huth uint8_t bitmask; \ 4847fcf5ef2aSThomas Huth int sh; \ 4848fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4849fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4850fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4851fcf5ef2aSThomas Huth if (sh > 0) \ 4852fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4853fcf5ef2aSThomas Huth else if (sh < 0) \ 4854fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4855fcf5ef2aSThomas Huth else \ 4856fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4857fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4858fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4859fcf5ef2aSThomas Huth if (sh > 0) \ 4860fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4861fcf5ef2aSThomas Huth else if (sh < 0) \ 4862fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4863fcf5ef2aSThomas Huth else \ 4864fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4865fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4866fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4867fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4868fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4869fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4870fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4871fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4872fcf5ef2aSThomas Huth } 4873fcf5ef2aSThomas Huth 4874fcf5ef2aSThomas Huth /* crand */ 4875fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4876fcf5ef2aSThomas Huth /* crandc */ 4877fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4878fcf5ef2aSThomas Huth /* creqv */ 4879fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4880fcf5ef2aSThomas Huth /* crnand */ 4881fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4882fcf5ef2aSThomas Huth /* crnor */ 4883fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4884fcf5ef2aSThomas Huth /* cror */ 4885fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4886fcf5ef2aSThomas Huth /* crorc */ 4887fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4888fcf5ef2aSThomas Huth /* crxor */ 4889fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4890fcf5ef2aSThomas Huth 4891fcf5ef2aSThomas Huth /* mcrf */ 4892fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4893fcf5ef2aSThomas Huth { 4894fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4895fcf5ef2aSThomas Huth } 4896fcf5ef2aSThomas Huth 4897fcf5ef2aSThomas Huth /*** System linkage ***/ 4898fcf5ef2aSThomas Huth 4899fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4900fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4901fcf5ef2aSThomas Huth { 4902fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4903fcf5ef2aSThomas Huth GEN_PRIV; 4904fcf5ef2aSThomas Huth #else 4905efe843d8SDavid Gibson /* 4906efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4907fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4908fcf5ef2aSThomas Huth */ 4909d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4910fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4911fcf5ef2aSThomas Huth return; 4912fcf5ef2aSThomas Huth } 4913fcf5ef2aSThomas Huth /* Restore CPU state */ 4914fcf5ef2aSThomas Huth CHK_SV; 4915f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49162c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4917fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 491859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4919fcf5ef2aSThomas Huth #endif 4920fcf5ef2aSThomas Huth } 4921fcf5ef2aSThomas Huth 4922fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4923fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4924fcf5ef2aSThomas Huth { 4925fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4926fcf5ef2aSThomas Huth GEN_PRIV; 4927fcf5ef2aSThomas Huth #else 4928fcf5ef2aSThomas Huth /* Restore CPU state */ 4929fcf5ef2aSThomas Huth CHK_SV; 4930f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49312c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4932fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 493359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4934fcf5ef2aSThomas Huth #endif 4935fcf5ef2aSThomas Huth } 4936fcf5ef2aSThomas Huth 49373c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 49383c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 49393c89b8d6SNicholas Piggin { 49403c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 49413c89b8d6SNicholas Piggin GEN_PRIV; 49423c89b8d6SNicholas Piggin #else 49433c89b8d6SNicholas Piggin /* Restore CPU state */ 49443c89b8d6SNicholas Piggin CHK_SV; 4945f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49462c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 49473c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 494859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 49493c89b8d6SNicholas Piggin #endif 49503c89b8d6SNicholas Piggin } 49513c89b8d6SNicholas Piggin #endif 49523c89b8d6SNicholas Piggin 4953fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4954fcf5ef2aSThomas Huth { 4955fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4956fcf5ef2aSThomas Huth GEN_PRIV; 4957fcf5ef2aSThomas Huth #else 4958fcf5ef2aSThomas Huth /* Restore CPU state */ 4959fcf5ef2aSThomas Huth CHK_HV; 4960fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 496159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4962fcf5ef2aSThomas Huth #endif 4963fcf5ef2aSThomas Huth } 4964fcf5ef2aSThomas Huth #endif 4965fcf5ef2aSThomas Huth 4966fcf5ef2aSThomas Huth /* sc */ 4967fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4968fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4969fcf5ef2aSThomas Huth #else 4970fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 49713c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4972fcf5ef2aSThomas Huth #endif 4973fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4974fcf5ef2aSThomas Huth { 4975fcf5ef2aSThomas Huth uint32_t lev; 4976fcf5ef2aSThomas Huth 4977fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4978fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4979fcf5ef2aSThomas Huth } 4980fcf5ef2aSThomas Huth 49813c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 49823c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 49833c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 49843c89b8d6SNicholas Piggin { 4985f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 49863c89b8d6SNicholas Piggin 4987f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 49882c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4989f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 49903c89b8d6SNicholas Piggin 4991*7a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 49923c89b8d6SNicholas Piggin } 49933c89b8d6SNicholas Piggin #endif 49943c89b8d6SNicholas Piggin #endif 49953c89b8d6SNicholas Piggin 4996fcf5ef2aSThomas Huth /*** Trap ***/ 4997fcf5ef2aSThomas Huth 4998fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4999fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 5000fcf5ef2aSThomas Huth { 5001fcf5ef2aSThomas Huth /* Trap never */ 5002fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 5003fcf5ef2aSThomas Huth return true; 5004fcf5ef2aSThomas Huth } 5005fcf5ef2aSThomas Huth /* Trap always */ 5006fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 5007fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 5008fcf5ef2aSThomas Huth return true; 5009fcf5ef2aSThomas Huth } 5010fcf5ef2aSThomas Huth return false; 5011fcf5ef2aSThomas Huth } 5012fcf5ef2aSThomas Huth 5013fcf5ef2aSThomas Huth /* tw */ 5014fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 5015fcf5ef2aSThomas Huth { 5016fcf5ef2aSThomas Huth TCGv_i32 t0; 5017fcf5ef2aSThomas Huth 5018fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5019fcf5ef2aSThomas Huth return; 5020fcf5ef2aSThomas Huth } 5021fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5022fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5023fcf5ef2aSThomas Huth t0); 5024fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5025fcf5ef2aSThomas Huth } 5026fcf5ef2aSThomas Huth 5027fcf5ef2aSThomas Huth /* twi */ 5028fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 5029fcf5ef2aSThomas Huth { 5030fcf5ef2aSThomas Huth TCGv t0; 5031fcf5ef2aSThomas Huth TCGv_i32 t1; 5032fcf5ef2aSThomas Huth 5033fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5034fcf5ef2aSThomas Huth return; 5035fcf5ef2aSThomas Huth } 5036fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5037fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5038fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5039fcf5ef2aSThomas Huth tcg_temp_free(t0); 5040fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5041fcf5ef2aSThomas Huth } 5042fcf5ef2aSThomas Huth 5043fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5044fcf5ef2aSThomas Huth /* td */ 5045fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 5046fcf5ef2aSThomas Huth { 5047fcf5ef2aSThomas Huth TCGv_i32 t0; 5048fcf5ef2aSThomas Huth 5049fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5050fcf5ef2aSThomas Huth return; 5051fcf5ef2aSThomas Huth } 5052fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5053fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5054fcf5ef2aSThomas Huth t0); 5055fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5056fcf5ef2aSThomas Huth } 5057fcf5ef2aSThomas Huth 5058fcf5ef2aSThomas Huth /* tdi */ 5059fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 5060fcf5ef2aSThomas Huth { 5061fcf5ef2aSThomas Huth TCGv t0; 5062fcf5ef2aSThomas Huth TCGv_i32 t1; 5063fcf5ef2aSThomas Huth 5064fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5065fcf5ef2aSThomas Huth return; 5066fcf5ef2aSThomas Huth } 5067fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5068fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5069fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5070fcf5ef2aSThomas Huth tcg_temp_free(t0); 5071fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5072fcf5ef2aSThomas Huth } 5073fcf5ef2aSThomas Huth #endif 5074fcf5ef2aSThomas Huth 5075fcf5ef2aSThomas Huth /*** Processor control ***/ 5076fcf5ef2aSThomas Huth 5077fcf5ef2aSThomas Huth /* mcrxr */ 5078fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 5079fcf5ef2aSThomas Huth { 5080fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5081fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 5082fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5083fcf5ef2aSThomas Huth 5084fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 5085fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 5086fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 5087fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 5088fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 5089fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 5090fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 5091fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 5092fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5093fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5094fcf5ef2aSThomas Huth 5095fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 5096fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5097fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5098fcf5ef2aSThomas Huth } 5099fcf5ef2aSThomas Huth 5100b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 5101b63d0434SNikunj A Dadhania /* mcrxrx */ 5102b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 5103b63d0434SNikunj A Dadhania { 5104b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 5105b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 5106b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5107b63d0434SNikunj A Dadhania 5108b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 5109b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 5110b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 5111b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 5112b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 5113b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 5114b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 5115b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 5116b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 5117b63d0434SNikunj A Dadhania tcg_temp_free(t0); 5118b63d0434SNikunj A Dadhania tcg_temp_free(t1); 5119b63d0434SNikunj A Dadhania } 5120b63d0434SNikunj A Dadhania #endif 5121b63d0434SNikunj A Dadhania 5122fcf5ef2aSThomas Huth /* mfcr mfocrf */ 5123fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 5124fcf5ef2aSThomas Huth { 5125fcf5ef2aSThomas Huth uint32_t crm, crn; 5126fcf5ef2aSThomas Huth 5127fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 5128fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5129fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 5130fcf5ef2aSThomas Huth crn = ctz32(crm); 5131fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 5132fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 5133fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 5134fcf5ef2aSThomas Huth } 5135fcf5ef2aSThomas Huth } else { 5136fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5137fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 5138fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5139fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 5140fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5141fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 5142fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5143fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 5144fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5145fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 5146fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5147fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 5148fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5149fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 5150fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5151fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 5152fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5153fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5154fcf5ef2aSThomas Huth } 5155fcf5ef2aSThomas Huth } 5156fcf5ef2aSThomas Huth 5157fcf5ef2aSThomas Huth /* mfmsr */ 5158fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 5159fcf5ef2aSThomas Huth { 5160fcf5ef2aSThomas Huth CHK_SV; 5161fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 5162fcf5ef2aSThomas Huth } 5163fcf5ef2aSThomas Huth 5164fcf5ef2aSThomas Huth /* mfspr */ 5165fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 5166fcf5ef2aSThomas Huth { 5167fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 5168fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5169fcf5ef2aSThomas Huth 5170fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5171fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5172fcf5ef2aSThomas Huth #else 5173fcf5ef2aSThomas Huth if (ctx->pr) { 5174fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5175fcf5ef2aSThomas Huth } else if (ctx->hv) { 5176fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 5177fcf5ef2aSThomas Huth } else { 5178fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 5179fcf5ef2aSThomas Huth } 5180fcf5ef2aSThomas Huth #endif 5181fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 5182fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 5183fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 5184fcf5ef2aSThomas Huth } else { 5185fcf5ef2aSThomas Huth /* Privilege exception */ 5186efe843d8SDavid Gibson /* 5187efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 5188fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 5189fcf5ef2aSThomas Huth * allowing userland application to read the PVR 5190fcf5ef2aSThomas Huth */ 5191fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 519231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 519331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 51942c2bcb1bSRichard Henderson ctx->cia); 5195fcf5ef2aSThomas Huth } 5196fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5197fcf5ef2aSThomas Huth } 5198fcf5ef2aSThomas Huth } else { 5199fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5200fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5201fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5202fcf5ef2aSThomas Huth /* This is a nop */ 5203fcf5ef2aSThomas Huth return; 5204fcf5ef2aSThomas Huth } 5205fcf5ef2aSThomas Huth /* Not defined */ 520631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 520731085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 52082c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5209fcf5ef2aSThomas Huth 5210efe843d8SDavid Gibson /* 5211efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5212efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5213fcf5ef2aSThomas Huth */ 5214fcf5ef2aSThomas Huth if (sprn & 0x10) { 5215fcf5ef2aSThomas Huth if (ctx->pr) { 5216fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5217fcf5ef2aSThomas Huth } 5218fcf5ef2aSThomas Huth } else { 5219fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5220fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5221fcf5ef2aSThomas Huth } 5222fcf5ef2aSThomas Huth } 5223fcf5ef2aSThomas Huth } 5224fcf5ef2aSThomas Huth } 5225fcf5ef2aSThomas Huth 5226fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5227fcf5ef2aSThomas Huth { 5228fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5229fcf5ef2aSThomas Huth } 5230fcf5ef2aSThomas Huth 5231fcf5ef2aSThomas Huth /* mftb */ 5232fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5233fcf5ef2aSThomas Huth { 5234fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5235fcf5ef2aSThomas Huth } 5236fcf5ef2aSThomas Huth 5237fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5238fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5239fcf5ef2aSThomas Huth { 5240fcf5ef2aSThomas Huth uint32_t crm, crn; 5241fcf5ef2aSThomas Huth 5242fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5243fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5244fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5245fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5246fcf5ef2aSThomas Huth crn = ctz32(crm); 5247fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5248fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5249fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5250fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5251fcf5ef2aSThomas Huth } 5252fcf5ef2aSThomas Huth } else { 5253fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5254fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5255fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5256fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5257fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5258fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5259fcf5ef2aSThomas Huth } 5260fcf5ef2aSThomas Huth } 5261fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5262fcf5ef2aSThomas Huth } 5263fcf5ef2aSThomas Huth } 5264fcf5ef2aSThomas Huth 5265fcf5ef2aSThomas Huth /* mtmsr */ 5266fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5267fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5268fcf5ef2aSThomas Huth { 5269fcf5ef2aSThomas Huth CHK_SV; 5270fcf5ef2aSThomas Huth 5271fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5272f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5273fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 52745ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5275fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 52765ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5277efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5278efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 52795ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5280efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 52815ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 52825ed19506SNicholas Piggin 52835ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5284fcf5ef2aSThomas Huth tcg_temp_free(t0); 52855ed19506SNicholas Piggin tcg_temp_free(t1); 52865ed19506SNicholas Piggin 5287fcf5ef2aSThomas Huth } else { 5288efe843d8SDavid Gibson /* 5289efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5290efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5291efe843d8SDavid Gibson * ppc_store_msr 5292fcf5ef2aSThomas Huth */ 5293b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5294fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5295fcf5ef2aSThomas Huth } 52965ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5297d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5298fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5299fcf5ef2aSThomas Huth } 5300fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5301fcf5ef2aSThomas Huth 5302fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5303fcf5ef2aSThomas Huth { 5304fcf5ef2aSThomas Huth CHK_SV; 5305fcf5ef2aSThomas Huth 5306fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5307f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5308fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 53095ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5310fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 53115ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5312efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5313efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 53145ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5315efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 53165ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 53175ed19506SNicholas Piggin 53185ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5319fcf5ef2aSThomas Huth tcg_temp_free(t0); 53205ed19506SNicholas Piggin tcg_temp_free(t1); 53215ed19506SNicholas Piggin 5322fcf5ef2aSThomas Huth } else { 5323fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5324fcf5ef2aSThomas Huth 5325efe843d8SDavid Gibson /* 5326efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5327efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5328efe843d8SDavid Gibson * ppc_store_msr 5329fcf5ef2aSThomas Huth */ 5330b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5331fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5332fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5333fcf5ef2aSThomas Huth #else 5334fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5335fcf5ef2aSThomas Huth #endif 5336fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5337fcf5ef2aSThomas Huth tcg_temp_free(msr); 5338fcf5ef2aSThomas Huth } 53395ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5340d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5341fcf5ef2aSThomas Huth #endif 5342fcf5ef2aSThomas Huth } 5343fcf5ef2aSThomas Huth 5344fcf5ef2aSThomas Huth /* mtspr */ 5345fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5346fcf5ef2aSThomas Huth { 5347fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5348fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5349fcf5ef2aSThomas Huth 5350fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5351fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5352fcf5ef2aSThomas Huth #else 5353fcf5ef2aSThomas Huth if (ctx->pr) { 5354fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5355fcf5ef2aSThomas Huth } else if (ctx->hv) { 5356fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5357fcf5ef2aSThomas Huth } else { 5358fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5359fcf5ef2aSThomas Huth } 5360fcf5ef2aSThomas Huth #endif 5361fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5362fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5363fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5364fcf5ef2aSThomas Huth } else { 5365fcf5ef2aSThomas Huth /* Privilege exception */ 536631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 536731085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 53682c2bcb1bSRichard Henderson ctx->cia); 5369fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5370fcf5ef2aSThomas Huth } 5371fcf5ef2aSThomas Huth } else { 5372fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5373fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5374fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5375fcf5ef2aSThomas Huth /* This is a nop */ 5376fcf5ef2aSThomas Huth return; 5377fcf5ef2aSThomas Huth } 5378fcf5ef2aSThomas Huth 5379fcf5ef2aSThomas Huth /* Not defined */ 538031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 538131085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 53822c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5383fcf5ef2aSThomas Huth 5384fcf5ef2aSThomas Huth 5385efe843d8SDavid Gibson /* 5386efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5387efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5388fcf5ef2aSThomas Huth */ 5389fcf5ef2aSThomas Huth if (sprn & 0x10) { 5390fcf5ef2aSThomas Huth if (ctx->pr) { 5391fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5392fcf5ef2aSThomas Huth } 5393fcf5ef2aSThomas Huth } else { 5394fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5395fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5396fcf5ef2aSThomas Huth } 5397fcf5ef2aSThomas Huth } 5398fcf5ef2aSThomas Huth } 5399fcf5ef2aSThomas Huth } 5400fcf5ef2aSThomas Huth 5401fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5402fcf5ef2aSThomas Huth /* setb */ 5403fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5404fcf5ef2aSThomas Huth { 5405fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5406fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5407fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5408fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5409fcf5ef2aSThomas Huth 5410fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5411fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5412fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5413fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5414fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5415fcf5ef2aSThomas Huth 5416fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5417fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5418fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5419fcf5ef2aSThomas Huth } 5420fcf5ef2aSThomas Huth #endif 5421fcf5ef2aSThomas Huth 5422fcf5ef2aSThomas Huth /*** Cache management ***/ 5423fcf5ef2aSThomas Huth 5424fcf5ef2aSThomas Huth /* dcbf */ 5425fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5426fcf5ef2aSThomas Huth { 5427fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5428fcf5ef2aSThomas Huth TCGv t0; 5429fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5430fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5431fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5432fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5433fcf5ef2aSThomas Huth tcg_temp_free(t0); 5434fcf5ef2aSThomas Huth } 5435fcf5ef2aSThomas Huth 543650728199SRoman Kapl /* dcbfep (external PID dcbf) */ 543750728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 543850728199SRoman Kapl { 543950728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 544050728199SRoman Kapl TCGv t0; 544150728199SRoman Kapl CHK_SV; 544250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 544350728199SRoman Kapl t0 = tcg_temp_new(); 544450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 544550728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 544650728199SRoman Kapl tcg_temp_free(t0); 544750728199SRoman Kapl } 544850728199SRoman Kapl 5449fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5450fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5451fcf5ef2aSThomas Huth { 5452fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5453fcf5ef2aSThomas Huth GEN_PRIV; 5454fcf5ef2aSThomas Huth #else 5455fcf5ef2aSThomas Huth TCGv EA, val; 5456fcf5ef2aSThomas Huth 5457fcf5ef2aSThomas Huth CHK_SV; 5458fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5459fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5460fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5461fcf5ef2aSThomas Huth val = tcg_temp_new(); 5462fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5463fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5464fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5465fcf5ef2aSThomas Huth tcg_temp_free(val); 5466fcf5ef2aSThomas Huth tcg_temp_free(EA); 5467fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5468fcf5ef2aSThomas Huth } 5469fcf5ef2aSThomas Huth 5470fcf5ef2aSThomas Huth /* dcdst */ 5471fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5472fcf5ef2aSThomas Huth { 5473fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5474fcf5ef2aSThomas Huth TCGv t0; 5475fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5476fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5477fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5478fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5479fcf5ef2aSThomas Huth tcg_temp_free(t0); 5480fcf5ef2aSThomas Huth } 5481fcf5ef2aSThomas Huth 548250728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 548350728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 548450728199SRoman Kapl { 548550728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 548650728199SRoman Kapl TCGv t0; 548750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 548850728199SRoman Kapl t0 = tcg_temp_new(); 548950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 549050728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 549150728199SRoman Kapl tcg_temp_free(t0); 549250728199SRoman Kapl } 549350728199SRoman Kapl 5494fcf5ef2aSThomas Huth /* dcbt */ 5495fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5496fcf5ef2aSThomas Huth { 5497efe843d8SDavid Gibson /* 5498efe843d8SDavid Gibson * interpreted as no-op 5499efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5500efe843d8SDavid Gibson * does not generate any exception 5501fcf5ef2aSThomas Huth */ 5502fcf5ef2aSThomas Huth } 5503fcf5ef2aSThomas Huth 550450728199SRoman Kapl /* dcbtep */ 550550728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 550650728199SRoman Kapl { 5507efe843d8SDavid Gibson /* 5508efe843d8SDavid Gibson * interpreted as no-op 5509efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5510efe843d8SDavid Gibson * does not generate any exception 551150728199SRoman Kapl */ 551250728199SRoman Kapl } 551350728199SRoman Kapl 5514fcf5ef2aSThomas Huth /* dcbtst */ 5515fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5516fcf5ef2aSThomas Huth { 5517efe843d8SDavid Gibson /* 5518efe843d8SDavid Gibson * interpreted as no-op 5519efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5520efe843d8SDavid Gibson * does not generate any exception 5521fcf5ef2aSThomas Huth */ 5522fcf5ef2aSThomas Huth } 5523fcf5ef2aSThomas Huth 552450728199SRoman Kapl /* dcbtstep */ 552550728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 552650728199SRoman Kapl { 5527efe843d8SDavid Gibson /* 5528efe843d8SDavid Gibson * interpreted as no-op 5529efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5530efe843d8SDavid Gibson * does not generate any exception 553150728199SRoman Kapl */ 553250728199SRoman Kapl } 553350728199SRoman Kapl 5534fcf5ef2aSThomas Huth /* dcbtls */ 5535fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5536fcf5ef2aSThomas Huth { 5537fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5538fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5539fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5540fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5541fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5542fcf5ef2aSThomas Huth tcg_temp_free(t0); 5543fcf5ef2aSThomas Huth } 5544fcf5ef2aSThomas Huth 5545fcf5ef2aSThomas Huth /* dcbz */ 5546fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5547fcf5ef2aSThomas Huth { 5548fcf5ef2aSThomas Huth TCGv tcgv_addr; 5549fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5550fcf5ef2aSThomas Huth 5551fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5552fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5553fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5554fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5555fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5556fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5557fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5558fcf5ef2aSThomas Huth } 5559fcf5ef2aSThomas Huth 556050728199SRoman Kapl /* dcbzep */ 556150728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 556250728199SRoman Kapl { 556350728199SRoman Kapl TCGv tcgv_addr; 556450728199SRoman Kapl TCGv_i32 tcgv_op; 556550728199SRoman Kapl 556650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 556750728199SRoman Kapl tcgv_addr = tcg_temp_new(); 556850728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 556950728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 557050728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 557150728199SRoman Kapl tcg_temp_free(tcgv_addr); 557250728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 557350728199SRoman Kapl } 557450728199SRoman Kapl 5575fcf5ef2aSThomas Huth /* dst / dstt */ 5576fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5577fcf5ef2aSThomas Huth { 5578fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5579fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5580fcf5ef2aSThomas Huth } else { 5581fcf5ef2aSThomas Huth /* interpreted as no-op */ 5582fcf5ef2aSThomas Huth } 5583fcf5ef2aSThomas Huth } 5584fcf5ef2aSThomas Huth 5585fcf5ef2aSThomas Huth /* dstst /dststt */ 5586fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5587fcf5ef2aSThomas Huth { 5588fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5589fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5590fcf5ef2aSThomas Huth } else { 5591fcf5ef2aSThomas Huth /* interpreted as no-op */ 5592fcf5ef2aSThomas Huth } 5593fcf5ef2aSThomas Huth 5594fcf5ef2aSThomas Huth } 5595fcf5ef2aSThomas Huth 5596fcf5ef2aSThomas Huth /* dss / dssall */ 5597fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5598fcf5ef2aSThomas Huth { 5599fcf5ef2aSThomas Huth /* interpreted as no-op */ 5600fcf5ef2aSThomas Huth } 5601fcf5ef2aSThomas Huth 5602fcf5ef2aSThomas Huth /* icbi */ 5603fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5604fcf5ef2aSThomas Huth { 5605fcf5ef2aSThomas Huth TCGv t0; 5606fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5607fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5608fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5609fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5610fcf5ef2aSThomas Huth tcg_temp_free(t0); 5611fcf5ef2aSThomas Huth } 5612fcf5ef2aSThomas Huth 561350728199SRoman Kapl /* icbiep */ 561450728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 561550728199SRoman Kapl { 561650728199SRoman Kapl TCGv t0; 561750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 561850728199SRoman Kapl t0 = tcg_temp_new(); 561950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 562050728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 562150728199SRoman Kapl tcg_temp_free(t0); 562250728199SRoman Kapl } 562350728199SRoman Kapl 5624fcf5ef2aSThomas Huth /* Optional: */ 5625fcf5ef2aSThomas Huth /* dcba */ 5626fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5627fcf5ef2aSThomas Huth { 5628efe843d8SDavid Gibson /* 5629efe843d8SDavid Gibson * interpreted as no-op 5630efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5631fcf5ef2aSThomas Huth * but does not generate any exception 5632fcf5ef2aSThomas Huth */ 5633fcf5ef2aSThomas Huth } 5634fcf5ef2aSThomas Huth 5635fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5636fcf5ef2aSThomas Huth /* Supervisor only: */ 5637fcf5ef2aSThomas Huth 5638fcf5ef2aSThomas Huth /* mfsr */ 5639fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5640fcf5ef2aSThomas Huth { 5641fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5642fcf5ef2aSThomas Huth GEN_PRIV; 5643fcf5ef2aSThomas Huth #else 5644fcf5ef2aSThomas Huth TCGv t0; 5645fcf5ef2aSThomas Huth 5646fcf5ef2aSThomas Huth CHK_SV; 5647fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5648fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5649fcf5ef2aSThomas Huth tcg_temp_free(t0); 5650fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5651fcf5ef2aSThomas Huth } 5652fcf5ef2aSThomas Huth 5653fcf5ef2aSThomas Huth /* mfsrin */ 5654fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5655fcf5ef2aSThomas Huth { 5656fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5657fcf5ef2aSThomas Huth GEN_PRIV; 5658fcf5ef2aSThomas Huth #else 5659fcf5ef2aSThomas Huth TCGv t0; 5660fcf5ef2aSThomas Huth 5661fcf5ef2aSThomas Huth CHK_SV; 5662fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5663e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5664fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5665fcf5ef2aSThomas Huth tcg_temp_free(t0); 5666fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5667fcf5ef2aSThomas Huth } 5668fcf5ef2aSThomas Huth 5669fcf5ef2aSThomas Huth /* mtsr */ 5670fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5671fcf5ef2aSThomas Huth { 5672fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5673fcf5ef2aSThomas Huth GEN_PRIV; 5674fcf5ef2aSThomas Huth #else 5675fcf5ef2aSThomas Huth TCGv t0; 5676fcf5ef2aSThomas Huth 5677fcf5ef2aSThomas Huth CHK_SV; 5678fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5679fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5680fcf5ef2aSThomas Huth tcg_temp_free(t0); 5681fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5682fcf5ef2aSThomas Huth } 5683fcf5ef2aSThomas Huth 5684fcf5ef2aSThomas Huth /* mtsrin */ 5685fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5686fcf5ef2aSThomas Huth { 5687fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5688fcf5ef2aSThomas Huth GEN_PRIV; 5689fcf5ef2aSThomas Huth #else 5690fcf5ef2aSThomas Huth TCGv t0; 5691fcf5ef2aSThomas Huth CHK_SV; 5692fcf5ef2aSThomas Huth 5693fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5694e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5695fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5696fcf5ef2aSThomas Huth tcg_temp_free(t0); 5697fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5698fcf5ef2aSThomas Huth } 5699fcf5ef2aSThomas Huth 5700fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5701fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5702fcf5ef2aSThomas Huth 5703fcf5ef2aSThomas Huth /* mfsr */ 5704fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5705fcf5ef2aSThomas Huth { 5706fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5707fcf5ef2aSThomas Huth GEN_PRIV; 5708fcf5ef2aSThomas Huth #else 5709fcf5ef2aSThomas Huth TCGv t0; 5710fcf5ef2aSThomas Huth 5711fcf5ef2aSThomas Huth CHK_SV; 5712fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5713fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5714fcf5ef2aSThomas Huth tcg_temp_free(t0); 5715fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5716fcf5ef2aSThomas Huth } 5717fcf5ef2aSThomas Huth 5718fcf5ef2aSThomas Huth /* mfsrin */ 5719fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5720fcf5ef2aSThomas Huth { 5721fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5722fcf5ef2aSThomas Huth GEN_PRIV; 5723fcf5ef2aSThomas Huth #else 5724fcf5ef2aSThomas Huth TCGv t0; 5725fcf5ef2aSThomas Huth 5726fcf5ef2aSThomas Huth CHK_SV; 5727fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5728e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5729fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5730fcf5ef2aSThomas Huth tcg_temp_free(t0); 5731fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5732fcf5ef2aSThomas Huth } 5733fcf5ef2aSThomas Huth 5734fcf5ef2aSThomas Huth /* mtsr */ 5735fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5736fcf5ef2aSThomas Huth { 5737fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5738fcf5ef2aSThomas Huth GEN_PRIV; 5739fcf5ef2aSThomas Huth #else 5740fcf5ef2aSThomas Huth TCGv t0; 5741fcf5ef2aSThomas Huth 5742fcf5ef2aSThomas Huth CHK_SV; 5743fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5744fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5745fcf5ef2aSThomas Huth tcg_temp_free(t0); 5746fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5747fcf5ef2aSThomas Huth } 5748fcf5ef2aSThomas Huth 5749fcf5ef2aSThomas Huth /* mtsrin */ 5750fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5751fcf5ef2aSThomas Huth { 5752fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5753fcf5ef2aSThomas Huth GEN_PRIV; 5754fcf5ef2aSThomas Huth #else 5755fcf5ef2aSThomas Huth TCGv t0; 5756fcf5ef2aSThomas Huth 5757fcf5ef2aSThomas Huth CHK_SV; 5758fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5759e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5760fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5761fcf5ef2aSThomas Huth tcg_temp_free(t0); 5762fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5763fcf5ef2aSThomas Huth } 5764fcf5ef2aSThomas Huth 5765fcf5ef2aSThomas Huth /* slbmte */ 5766fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5767fcf5ef2aSThomas Huth { 5768fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5769fcf5ef2aSThomas Huth GEN_PRIV; 5770fcf5ef2aSThomas Huth #else 5771fcf5ef2aSThomas Huth CHK_SV; 5772fcf5ef2aSThomas Huth 5773fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5774fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5775fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5776fcf5ef2aSThomas Huth } 5777fcf5ef2aSThomas Huth 5778fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5779fcf5ef2aSThomas Huth { 5780fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5781fcf5ef2aSThomas Huth GEN_PRIV; 5782fcf5ef2aSThomas Huth #else 5783fcf5ef2aSThomas Huth CHK_SV; 5784fcf5ef2aSThomas Huth 5785fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5786fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5787fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5788fcf5ef2aSThomas Huth } 5789fcf5ef2aSThomas Huth 5790fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5791fcf5ef2aSThomas Huth { 5792fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5793fcf5ef2aSThomas Huth GEN_PRIV; 5794fcf5ef2aSThomas Huth #else 5795fcf5ef2aSThomas Huth CHK_SV; 5796fcf5ef2aSThomas Huth 5797fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5798fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5799fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5800fcf5ef2aSThomas Huth } 5801fcf5ef2aSThomas Huth 5802fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5803fcf5ef2aSThomas Huth { 5804fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5805fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5806fcf5ef2aSThomas Huth #else 5807fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5808fcf5ef2aSThomas Huth 5809fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5810fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5811fcf5ef2aSThomas Huth return; 5812fcf5ef2aSThomas Huth } 5813fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5814fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5815fcf5ef2aSThomas Huth l1 = gen_new_label(); 5816fcf5ef2aSThomas Huth l2 = gen_new_label(); 5817fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5818fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5819efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5820fcf5ef2aSThomas Huth tcg_gen_br(l2); 5821fcf5ef2aSThomas Huth gen_set_label(l1); 5822fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5823fcf5ef2aSThomas Huth gen_set_label(l2); 5824fcf5ef2aSThomas Huth #endif 5825fcf5ef2aSThomas Huth } 5826fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5827fcf5ef2aSThomas Huth 5828fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5829fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5830fcf5ef2aSThomas Huth 5831fcf5ef2aSThomas Huth /* tlbia */ 5832fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5833fcf5ef2aSThomas Huth { 5834fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5835fcf5ef2aSThomas Huth GEN_PRIV; 5836fcf5ef2aSThomas Huth #else 5837fcf5ef2aSThomas Huth CHK_HV; 5838fcf5ef2aSThomas Huth 5839fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5840fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5841fcf5ef2aSThomas Huth } 5842fcf5ef2aSThomas Huth 5843fcf5ef2aSThomas Huth /* tlbiel */ 5844fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5845fcf5ef2aSThomas Huth { 5846fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5847fcf5ef2aSThomas Huth GEN_PRIV; 5848fcf5ef2aSThomas Huth #else 5849fcf5ef2aSThomas Huth CHK_SV; 5850fcf5ef2aSThomas Huth 5851fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5852fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5853fcf5ef2aSThomas Huth } 5854fcf5ef2aSThomas Huth 5855fcf5ef2aSThomas Huth /* tlbie */ 5856fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5857fcf5ef2aSThomas Huth { 5858fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5859fcf5ef2aSThomas Huth GEN_PRIV; 5860fcf5ef2aSThomas Huth #else 5861fcf5ef2aSThomas Huth TCGv_i32 t1; 5862c6fd28fdSSuraj Jitindar Singh 5863c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 586491c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5865c6fd28fdSSuraj Jitindar Singh } else { 5866c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5867c6fd28fdSSuraj Jitindar Singh } 5868fcf5ef2aSThomas Huth 5869fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5870fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5871fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5872fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5873fcf5ef2aSThomas Huth tcg_temp_free(t0); 5874fcf5ef2aSThomas Huth } else { 5875fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5876fcf5ef2aSThomas Huth } 5877fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5878fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5879fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5880fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5881fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5882fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5883fcf5ef2aSThomas Huth } 5884fcf5ef2aSThomas Huth 5885fcf5ef2aSThomas Huth /* tlbsync */ 5886fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5887fcf5ef2aSThomas Huth { 5888fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5889fcf5ef2aSThomas Huth GEN_PRIV; 5890fcf5ef2aSThomas Huth #else 589191c60f12SCédric Le Goater 589291c60f12SCédric Le Goater if (ctx->gtse) { 589391c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 589491c60f12SCédric Le Goater } else { 589591c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 589691c60f12SCédric Le Goater } 5897fcf5ef2aSThomas Huth 5898fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5899fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5900fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5901fcf5ef2aSThomas Huth } 5902fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5903fcf5ef2aSThomas Huth } 5904fcf5ef2aSThomas Huth 5905fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5906fcf5ef2aSThomas Huth /* slbia */ 5907fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5908fcf5ef2aSThomas Huth { 5909fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5910fcf5ef2aSThomas Huth GEN_PRIV; 5911fcf5ef2aSThomas Huth #else 59120418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 59130418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 59140418bf78SNicholas Piggin 5915fcf5ef2aSThomas Huth CHK_SV; 5916fcf5ef2aSThomas Huth 59170418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 59183119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5919fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5920fcf5ef2aSThomas Huth } 5921fcf5ef2aSThomas Huth 5922fcf5ef2aSThomas Huth /* slbie */ 5923fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5924fcf5ef2aSThomas Huth { 5925fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5926fcf5ef2aSThomas Huth GEN_PRIV; 5927fcf5ef2aSThomas Huth #else 5928fcf5ef2aSThomas Huth CHK_SV; 5929fcf5ef2aSThomas Huth 5930fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5931fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5932fcf5ef2aSThomas Huth } 5933a63f1dfcSNikunj A Dadhania 5934a63f1dfcSNikunj A Dadhania /* slbieg */ 5935a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5936a63f1dfcSNikunj A Dadhania { 5937a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5938a63f1dfcSNikunj A Dadhania GEN_PRIV; 5939a63f1dfcSNikunj A Dadhania #else 5940a63f1dfcSNikunj A Dadhania CHK_SV; 5941a63f1dfcSNikunj A Dadhania 5942a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5943a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5944a63f1dfcSNikunj A Dadhania } 5945a63f1dfcSNikunj A Dadhania 594662d897caSNikunj A Dadhania /* slbsync */ 594762d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 594862d897caSNikunj A Dadhania { 594962d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 595062d897caSNikunj A Dadhania GEN_PRIV; 595162d897caSNikunj A Dadhania #else 595262d897caSNikunj A Dadhania CHK_SV; 595362d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 595462d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 595562d897caSNikunj A Dadhania } 595662d897caSNikunj A Dadhania 5957fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5958fcf5ef2aSThomas Huth 5959fcf5ef2aSThomas Huth /*** External control ***/ 5960fcf5ef2aSThomas Huth /* Optional: */ 5961fcf5ef2aSThomas Huth 5962fcf5ef2aSThomas Huth /* eciwx */ 5963fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5964fcf5ef2aSThomas Huth { 5965fcf5ef2aSThomas Huth TCGv t0; 5966fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5967fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5968fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5969fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5970c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5971c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5972fcf5ef2aSThomas Huth tcg_temp_free(t0); 5973fcf5ef2aSThomas Huth } 5974fcf5ef2aSThomas Huth 5975fcf5ef2aSThomas Huth /* ecowx */ 5976fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5977fcf5ef2aSThomas Huth { 5978fcf5ef2aSThomas Huth TCGv t0; 5979fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5980fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5981fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5982fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5983c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5984c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5985fcf5ef2aSThomas Huth tcg_temp_free(t0); 5986fcf5ef2aSThomas Huth } 5987fcf5ef2aSThomas Huth 5988fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5989fcf5ef2aSThomas Huth 5990fcf5ef2aSThomas Huth /* abs - abs. */ 5991fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5992fcf5ef2aSThomas Huth { 5993fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5994fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5995fe21b785SRichard Henderson 5996fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5997efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5998fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5999fcf5ef2aSThomas Huth } 6000efe843d8SDavid Gibson } 6001fcf5ef2aSThomas Huth 6002fcf5ef2aSThomas Huth /* abso - abso. */ 6003fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 6004fcf5ef2aSThomas Huth { 6005fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6006fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6007fe21b785SRichard Henderson 6008fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 6009fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6010fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 6011efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6012fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6013fcf5ef2aSThomas Huth } 6014efe843d8SDavid Gibson } 6015fcf5ef2aSThomas Huth 6016fcf5ef2aSThomas Huth /* clcs */ 6017fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 6018fcf5ef2aSThomas Huth { 6019fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 6020fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6021fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6022fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 6023fcf5ef2aSThomas Huth } 6024fcf5ef2aSThomas Huth 6025fcf5ef2aSThomas Huth /* div - div. */ 6026fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 6027fcf5ef2aSThomas Huth { 6028fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6029fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6030efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6031fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6032fcf5ef2aSThomas Huth } 6033efe843d8SDavid Gibson } 6034fcf5ef2aSThomas Huth 6035fcf5ef2aSThomas Huth /* divo - divo. */ 6036fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 6037fcf5ef2aSThomas Huth { 6038fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6039fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6040efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6041fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6042fcf5ef2aSThomas Huth } 6043efe843d8SDavid Gibson } 6044fcf5ef2aSThomas Huth 6045fcf5ef2aSThomas Huth /* divs - divs. */ 6046fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 6047fcf5ef2aSThomas Huth { 6048fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6049fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6050efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6051fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6052fcf5ef2aSThomas Huth } 6053efe843d8SDavid Gibson } 6054fcf5ef2aSThomas Huth 6055fcf5ef2aSThomas Huth /* divso - divso. */ 6056fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 6057fcf5ef2aSThomas Huth { 6058fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 6059fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6060efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6061fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6062fcf5ef2aSThomas Huth } 6063efe843d8SDavid Gibson } 6064fcf5ef2aSThomas Huth 6065fcf5ef2aSThomas Huth /* doz - doz. */ 6066fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 6067fcf5ef2aSThomas Huth { 6068fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6069fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6070efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6071efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6072efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 6073efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 6074fcf5ef2aSThomas Huth tcg_gen_br(l2); 6075fcf5ef2aSThomas Huth gen_set_label(l1); 6076fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6077fcf5ef2aSThomas Huth gen_set_label(l2); 6078efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6079fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6080fcf5ef2aSThomas Huth } 6081efe843d8SDavid Gibson } 6082fcf5ef2aSThomas Huth 6083fcf5ef2aSThomas Huth /* dozo - dozo. */ 6084fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 6085fcf5ef2aSThomas Huth { 6086fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6087fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6088fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6089fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6090fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6091fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6092fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6093efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6094efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6095fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6096fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6097fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 6098fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6099fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 6100fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6101fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6102fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6103fcf5ef2aSThomas Huth tcg_gen_br(l2); 6104fcf5ef2aSThomas Huth gen_set_label(l1); 6105fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6106fcf5ef2aSThomas Huth gen_set_label(l2); 6107fcf5ef2aSThomas Huth tcg_temp_free(t0); 6108fcf5ef2aSThomas Huth tcg_temp_free(t1); 6109fcf5ef2aSThomas Huth tcg_temp_free(t2); 6110efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6111fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6112fcf5ef2aSThomas Huth } 6113efe843d8SDavid Gibson } 6114fcf5ef2aSThomas Huth 6115fcf5ef2aSThomas Huth /* dozi */ 6116fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 6117fcf5ef2aSThomas Huth { 6118fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 6119fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6120fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6121fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 6122fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 6123fcf5ef2aSThomas Huth tcg_gen_br(l2); 6124fcf5ef2aSThomas Huth gen_set_label(l1); 6125fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6126fcf5ef2aSThomas Huth gen_set_label(l2); 6127efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6128fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6129fcf5ef2aSThomas Huth } 6130efe843d8SDavid Gibson } 6131fcf5ef2aSThomas Huth 6132fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 6133fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 6134fcf5ef2aSThomas Huth { 6135fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6136fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 6137fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 6138fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 6139fcf5ef2aSThomas Huth 6140fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6141fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 6142fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6143fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 6144fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 6145fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 6146fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 6147efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6148fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 6149efe843d8SDavid Gibson } 6150fcf5ef2aSThomas Huth tcg_temp_free(t0); 6151fcf5ef2aSThomas Huth } 6152fcf5ef2aSThomas Huth 6153fcf5ef2aSThomas Huth /* maskg - maskg. */ 6154fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 6155fcf5ef2aSThomas Huth { 6156fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6157fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6158fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6159fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6160fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 6161fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 6162fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6163fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 6164fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 6165fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 6166fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 6167fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 6168fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 6169fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6170fcf5ef2aSThomas Huth gen_set_label(l1); 6171fcf5ef2aSThomas Huth tcg_temp_free(t0); 6172fcf5ef2aSThomas Huth tcg_temp_free(t1); 6173fcf5ef2aSThomas Huth tcg_temp_free(t2); 6174fcf5ef2aSThomas Huth tcg_temp_free(t3); 6175efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6176fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6177fcf5ef2aSThomas Huth } 6178efe843d8SDavid Gibson } 6179fcf5ef2aSThomas Huth 6180fcf5ef2aSThomas Huth /* maskir - maskir. */ 6181fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 6182fcf5ef2aSThomas Huth { 6183fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6184fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6185fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6186fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6187fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6188fcf5ef2aSThomas Huth tcg_temp_free(t0); 6189fcf5ef2aSThomas Huth tcg_temp_free(t1); 6190efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6191fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6192fcf5ef2aSThomas Huth } 6193efe843d8SDavid Gibson } 6194fcf5ef2aSThomas Huth 6195fcf5ef2aSThomas Huth /* mul - mul. */ 6196fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 6197fcf5ef2aSThomas Huth { 6198fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6199fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6200fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6201fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6202fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6203fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6204fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6205fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6206fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6207fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6208fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6209fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6210fcf5ef2aSThomas Huth tcg_temp_free(t2); 6211efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6212fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6213fcf5ef2aSThomas Huth } 6214efe843d8SDavid Gibson } 6215fcf5ef2aSThomas Huth 6216fcf5ef2aSThomas Huth /* mulo - mulo. */ 6217fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6218fcf5ef2aSThomas Huth { 6219fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6220fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6221fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6222fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6223fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6224fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6225fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6226fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6227fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6228fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6229fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6230fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6231fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6232fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6233fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6234fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6235fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6236fcf5ef2aSThomas Huth gen_set_label(l1); 6237fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6238fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6239fcf5ef2aSThomas Huth tcg_temp_free(t2); 6240efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6241fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6242fcf5ef2aSThomas Huth } 6243efe843d8SDavid Gibson } 6244fcf5ef2aSThomas Huth 6245fcf5ef2aSThomas Huth /* nabs - nabs. */ 6246fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6247fcf5ef2aSThomas Huth { 6248fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6249fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6250fe21b785SRichard Henderson 6251fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6252fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6253efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6254fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6255fcf5ef2aSThomas Huth } 6256efe843d8SDavid Gibson } 6257fcf5ef2aSThomas Huth 6258fcf5ef2aSThomas Huth /* nabso - nabso. */ 6259fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6260fcf5ef2aSThomas Huth { 6261fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6262fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6263fe21b785SRichard Henderson 6264fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6265fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6266fcf5ef2aSThomas Huth /* nabs never overflows */ 6267fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6268efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6269fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6270fcf5ef2aSThomas Huth } 6271efe843d8SDavid Gibson } 6272fcf5ef2aSThomas Huth 6273fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6274fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6275fcf5ef2aSThomas Huth { 6276fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6277fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6278fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6279fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6280fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6281fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6282efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6283efe843d8SDavid Gibson ~MASK(mb, me)); 6284fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6285fcf5ef2aSThomas Huth tcg_temp_free(t0); 6286efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6287fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6288fcf5ef2aSThomas Huth } 6289efe843d8SDavid Gibson } 6290fcf5ef2aSThomas Huth 6291fcf5ef2aSThomas Huth /* rrib - rrib. */ 6292fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6293fcf5ef2aSThomas Huth { 6294fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6295fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6296fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6297fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6298fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6299fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6300fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6301fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6302fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6303fcf5ef2aSThomas Huth tcg_temp_free(t0); 6304fcf5ef2aSThomas Huth tcg_temp_free(t1); 6305efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6306fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6307fcf5ef2aSThomas Huth } 6308efe843d8SDavid Gibson } 6309fcf5ef2aSThomas Huth 6310fcf5ef2aSThomas Huth /* sle - sle. */ 6311fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6312fcf5ef2aSThomas Huth { 6313fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6314fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6315fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6316fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6317fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6318fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6319fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6320fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6321fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6322fcf5ef2aSThomas Huth tcg_temp_free(t0); 6323fcf5ef2aSThomas Huth tcg_temp_free(t1); 6324efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6325fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6326fcf5ef2aSThomas Huth } 6327efe843d8SDavid Gibson } 6328fcf5ef2aSThomas Huth 6329fcf5ef2aSThomas Huth /* sleq - sleq. */ 6330fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6331fcf5ef2aSThomas Huth { 6332fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6333fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6334fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6335fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6336fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6337fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6338fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6339fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6340fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6341fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6342fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6343fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6344fcf5ef2aSThomas Huth tcg_temp_free(t0); 6345fcf5ef2aSThomas Huth tcg_temp_free(t1); 6346fcf5ef2aSThomas Huth tcg_temp_free(t2); 6347efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6348fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6349fcf5ef2aSThomas Huth } 6350efe843d8SDavid Gibson } 6351fcf5ef2aSThomas Huth 6352fcf5ef2aSThomas Huth /* sliq - sliq. */ 6353fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6354fcf5ef2aSThomas Huth { 6355fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6356fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6357fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6358fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6359fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6360fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6361fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6362fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6363fcf5ef2aSThomas Huth tcg_temp_free(t0); 6364fcf5ef2aSThomas Huth tcg_temp_free(t1); 6365efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6366fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6367fcf5ef2aSThomas Huth } 6368efe843d8SDavid Gibson } 6369fcf5ef2aSThomas Huth 6370fcf5ef2aSThomas Huth /* slliq - slliq. */ 6371fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6372fcf5ef2aSThomas Huth { 6373fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6374fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6375fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6376fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6377fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6378fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6379fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6380fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6381fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6382fcf5ef2aSThomas Huth tcg_temp_free(t0); 6383fcf5ef2aSThomas Huth tcg_temp_free(t1); 6384efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6385fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6386fcf5ef2aSThomas Huth } 6387efe843d8SDavid Gibson } 6388fcf5ef2aSThomas Huth 6389fcf5ef2aSThomas Huth /* sllq - sllq. */ 6390fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6391fcf5ef2aSThomas Huth { 6392fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6393fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6394fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6395fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6396fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6397fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6398fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6399fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6400fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6401fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6402fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6403fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6404fcf5ef2aSThomas Huth tcg_gen_br(l2); 6405fcf5ef2aSThomas Huth gen_set_label(l1); 6406fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6407fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6408fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6409fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6410fcf5ef2aSThomas Huth gen_set_label(l2); 6411fcf5ef2aSThomas Huth tcg_temp_free(t0); 6412fcf5ef2aSThomas Huth tcg_temp_free(t1); 6413fcf5ef2aSThomas Huth tcg_temp_free(t2); 6414efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6415fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6416fcf5ef2aSThomas Huth } 6417efe843d8SDavid Gibson } 6418fcf5ef2aSThomas Huth 6419fcf5ef2aSThomas Huth /* slq - slq. */ 6420fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6421fcf5ef2aSThomas Huth { 6422fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6423fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6424fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6425fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6426fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6427fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6428fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6429fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6430fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6431fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6432fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6433fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6434fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6435fcf5ef2aSThomas Huth gen_set_label(l1); 6436fcf5ef2aSThomas Huth tcg_temp_free(t0); 6437fcf5ef2aSThomas Huth tcg_temp_free(t1); 6438efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6439fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6440fcf5ef2aSThomas Huth } 6441efe843d8SDavid Gibson } 6442fcf5ef2aSThomas Huth 6443fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6444fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6445fcf5ef2aSThomas Huth { 6446fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6447fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6448fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6449fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6450fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6451fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6452fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6453fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6454fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6455fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6456fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6457fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6458fcf5ef2aSThomas Huth gen_set_label(l1); 6459fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6460fcf5ef2aSThomas Huth tcg_temp_free(t0); 6461fcf5ef2aSThomas Huth tcg_temp_free(t1); 6462efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6463fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6464fcf5ef2aSThomas Huth } 6465efe843d8SDavid Gibson } 6466fcf5ef2aSThomas Huth 6467fcf5ef2aSThomas Huth /* sraq - sraq. */ 6468fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6469fcf5ef2aSThomas Huth { 6470fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6471fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6472fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6473fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6474fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6475fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6476fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6477fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6478fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6479fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6480fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6481fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6482fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6483fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6484fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6485fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6486fcf5ef2aSThomas Huth gen_set_label(l1); 6487fcf5ef2aSThomas Huth tcg_temp_free(t0); 6488fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6489fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6490fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6491fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6492fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6493fcf5ef2aSThomas Huth gen_set_label(l2); 6494fcf5ef2aSThomas Huth tcg_temp_free(t1); 6495fcf5ef2aSThomas Huth tcg_temp_free(t2); 6496efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6497fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6498fcf5ef2aSThomas Huth } 6499efe843d8SDavid Gibson } 6500fcf5ef2aSThomas Huth 6501fcf5ef2aSThomas Huth /* sre - sre. */ 6502fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6503fcf5ef2aSThomas Huth { 6504fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6505fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6506fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6507fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6508fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6509fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6510fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6511fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6512fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6513fcf5ef2aSThomas Huth tcg_temp_free(t0); 6514fcf5ef2aSThomas Huth tcg_temp_free(t1); 6515efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6516fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6517fcf5ef2aSThomas Huth } 6518efe843d8SDavid Gibson } 6519fcf5ef2aSThomas Huth 6520fcf5ef2aSThomas Huth /* srea - srea. */ 6521fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6522fcf5ef2aSThomas Huth { 6523fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6524fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6525fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6526fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6527fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6528fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6529fcf5ef2aSThomas Huth tcg_temp_free(t0); 6530fcf5ef2aSThomas Huth tcg_temp_free(t1); 6531efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6532fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6533fcf5ef2aSThomas Huth } 6534efe843d8SDavid Gibson } 6535fcf5ef2aSThomas Huth 6536fcf5ef2aSThomas Huth /* sreq */ 6537fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6538fcf5ef2aSThomas Huth { 6539fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6540fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6541fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6542fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6543fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6544fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6545fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6546fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6547fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6548fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6549fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6550fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6551fcf5ef2aSThomas Huth tcg_temp_free(t0); 6552fcf5ef2aSThomas Huth tcg_temp_free(t1); 6553fcf5ef2aSThomas Huth tcg_temp_free(t2); 6554efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6555fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6556fcf5ef2aSThomas Huth } 6557efe843d8SDavid Gibson } 6558fcf5ef2aSThomas Huth 6559fcf5ef2aSThomas Huth /* sriq */ 6560fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6561fcf5ef2aSThomas Huth { 6562fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6563fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6564fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6565fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6566fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6567fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6568fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6569fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6570fcf5ef2aSThomas Huth tcg_temp_free(t0); 6571fcf5ef2aSThomas Huth tcg_temp_free(t1); 6572efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6573fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6574fcf5ef2aSThomas Huth } 6575efe843d8SDavid Gibson } 6576fcf5ef2aSThomas Huth 6577fcf5ef2aSThomas Huth /* srliq */ 6578fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6579fcf5ef2aSThomas Huth { 6580fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6581fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6582fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6583fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6584fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6585fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6586fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6587fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6588fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6589fcf5ef2aSThomas Huth tcg_temp_free(t0); 6590fcf5ef2aSThomas Huth tcg_temp_free(t1); 6591efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6592fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6593fcf5ef2aSThomas Huth } 6594efe843d8SDavid Gibson } 6595fcf5ef2aSThomas Huth 6596fcf5ef2aSThomas Huth /* srlq */ 6597fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6598fcf5ef2aSThomas Huth { 6599fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6600fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6601fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6602fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6603fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6604fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6605fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6606fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6607fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6608fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6609fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6610fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6611fcf5ef2aSThomas Huth tcg_gen_br(l2); 6612fcf5ef2aSThomas Huth gen_set_label(l1); 6613fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6614fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6615fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6616fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6617fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6618fcf5ef2aSThomas Huth gen_set_label(l2); 6619fcf5ef2aSThomas Huth tcg_temp_free(t0); 6620fcf5ef2aSThomas Huth tcg_temp_free(t1); 6621fcf5ef2aSThomas Huth tcg_temp_free(t2); 6622efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6623fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6624fcf5ef2aSThomas Huth } 6625efe843d8SDavid Gibson } 6626fcf5ef2aSThomas Huth 6627fcf5ef2aSThomas Huth /* srq */ 6628fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6629fcf5ef2aSThomas Huth { 6630fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6631fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6632fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6633fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6634fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6635fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6636fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6637fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6638fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6639fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6640fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6641fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6642fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6643fcf5ef2aSThomas Huth gen_set_label(l1); 6644fcf5ef2aSThomas Huth tcg_temp_free(t0); 6645fcf5ef2aSThomas Huth tcg_temp_free(t1); 6646efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6647fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6648fcf5ef2aSThomas Huth } 6649efe843d8SDavid Gibson } 6650fcf5ef2aSThomas Huth 6651fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6652fcf5ef2aSThomas Huth 6653fcf5ef2aSThomas Huth /* dsa */ 6654fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6655fcf5ef2aSThomas Huth { 6656fcf5ef2aSThomas Huth /* XXX: TODO */ 6657fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6658fcf5ef2aSThomas Huth } 6659fcf5ef2aSThomas Huth 6660fcf5ef2aSThomas Huth /* esa */ 6661fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6662fcf5ef2aSThomas Huth { 6663fcf5ef2aSThomas Huth /* XXX: TODO */ 6664fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6665fcf5ef2aSThomas Huth } 6666fcf5ef2aSThomas Huth 6667fcf5ef2aSThomas Huth /* mfrom */ 6668fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6669fcf5ef2aSThomas Huth { 6670fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6671fcf5ef2aSThomas Huth GEN_PRIV; 6672fcf5ef2aSThomas Huth #else 6673fcf5ef2aSThomas Huth CHK_SV; 6674fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6675fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6676fcf5ef2aSThomas Huth } 6677fcf5ef2aSThomas Huth 6678fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6679fcf5ef2aSThomas Huth 6680fcf5ef2aSThomas Huth /* tlbld */ 6681fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6682fcf5ef2aSThomas Huth { 6683fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6684fcf5ef2aSThomas Huth GEN_PRIV; 6685fcf5ef2aSThomas Huth #else 6686fcf5ef2aSThomas Huth CHK_SV; 6687fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6688fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6689fcf5ef2aSThomas Huth } 6690fcf5ef2aSThomas Huth 6691fcf5ef2aSThomas Huth /* tlbli */ 6692fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6693fcf5ef2aSThomas Huth { 6694fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6695fcf5ef2aSThomas Huth GEN_PRIV; 6696fcf5ef2aSThomas Huth #else 6697fcf5ef2aSThomas Huth CHK_SV; 6698fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6699fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6700fcf5ef2aSThomas Huth } 6701fcf5ef2aSThomas Huth 6702fcf5ef2aSThomas Huth /* 74xx TLB management */ 6703fcf5ef2aSThomas Huth 6704fcf5ef2aSThomas Huth /* tlbld */ 6705fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6706fcf5ef2aSThomas Huth { 6707fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6708fcf5ef2aSThomas Huth GEN_PRIV; 6709fcf5ef2aSThomas Huth #else 6710fcf5ef2aSThomas Huth CHK_SV; 6711fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6712fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6713fcf5ef2aSThomas Huth } 6714fcf5ef2aSThomas Huth 6715fcf5ef2aSThomas Huth /* tlbli */ 6716fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6717fcf5ef2aSThomas Huth { 6718fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6719fcf5ef2aSThomas Huth GEN_PRIV; 6720fcf5ef2aSThomas Huth #else 6721fcf5ef2aSThomas Huth CHK_SV; 6722fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6723fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6724fcf5ef2aSThomas Huth } 6725fcf5ef2aSThomas Huth 6726fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6727fcf5ef2aSThomas Huth 6728fcf5ef2aSThomas Huth /* clf */ 6729fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6730fcf5ef2aSThomas Huth { 6731fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6732fcf5ef2aSThomas Huth } 6733fcf5ef2aSThomas Huth 6734fcf5ef2aSThomas Huth /* cli */ 6735fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6736fcf5ef2aSThomas Huth { 6737fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6738fcf5ef2aSThomas Huth GEN_PRIV; 6739fcf5ef2aSThomas Huth #else 6740fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6741fcf5ef2aSThomas Huth CHK_SV; 6742fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6743fcf5ef2aSThomas Huth } 6744fcf5ef2aSThomas Huth 6745fcf5ef2aSThomas Huth /* dclst */ 6746fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6747fcf5ef2aSThomas Huth { 6748fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6749fcf5ef2aSThomas Huth } 6750fcf5ef2aSThomas Huth 6751fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6752fcf5ef2aSThomas Huth { 6753fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6754fcf5ef2aSThomas Huth GEN_PRIV; 6755fcf5ef2aSThomas Huth #else 6756fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6757fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6758fcf5ef2aSThomas Huth TCGv t0; 6759fcf5ef2aSThomas Huth 6760fcf5ef2aSThomas Huth CHK_SV; 6761fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6762fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6763e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6764fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6765fcf5ef2aSThomas Huth tcg_temp_free(t0); 6766efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6767fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6768efe843d8SDavid Gibson } 6769fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6770fcf5ef2aSThomas Huth } 6771fcf5ef2aSThomas Huth 6772fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6773fcf5ef2aSThomas Huth { 6774fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6775fcf5ef2aSThomas Huth GEN_PRIV; 6776fcf5ef2aSThomas Huth #else 6777fcf5ef2aSThomas Huth TCGv t0; 6778fcf5ef2aSThomas Huth 6779fcf5ef2aSThomas Huth CHK_SV; 6780fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6781fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6782fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6783fcf5ef2aSThomas Huth tcg_temp_free(t0); 6784fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6785fcf5ef2aSThomas Huth } 6786fcf5ef2aSThomas Huth 6787fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6788fcf5ef2aSThomas Huth { 6789fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6790fcf5ef2aSThomas Huth GEN_PRIV; 6791fcf5ef2aSThomas Huth #else 6792fcf5ef2aSThomas Huth CHK_SV; 6793fcf5ef2aSThomas Huth 6794fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 679559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6796fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6797fcf5ef2aSThomas Huth } 6798fcf5ef2aSThomas Huth 6799fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6800fcf5ef2aSThomas Huth 6801fcf5ef2aSThomas Huth /* BookE specific instructions */ 6802fcf5ef2aSThomas Huth 6803fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6804fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6805fcf5ef2aSThomas Huth { 6806fcf5ef2aSThomas Huth /* XXX: TODO */ 6807fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6808fcf5ef2aSThomas Huth } 6809fcf5ef2aSThomas Huth 6810fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6811fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6812fcf5ef2aSThomas Huth { 6813fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6814fcf5ef2aSThomas Huth GEN_PRIV; 6815fcf5ef2aSThomas Huth #else 6816fcf5ef2aSThomas Huth TCGv t0; 6817fcf5ef2aSThomas Huth 6818fcf5ef2aSThomas Huth CHK_SV; 6819fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6820fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6821fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6822fcf5ef2aSThomas Huth tcg_temp_free(t0); 6823fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6824fcf5ef2aSThomas Huth } 6825fcf5ef2aSThomas Huth 6826fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6827fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6828fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6829fcf5ef2aSThomas Huth { 6830fcf5ef2aSThomas Huth TCGv t0, t1; 6831fcf5ef2aSThomas Huth 6832fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6833fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6834fcf5ef2aSThomas Huth 6835fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6836fcf5ef2aSThomas Huth case 0x05: 6837fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6838fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6839fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6840fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6841fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6842fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6843fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6844fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6845fcf5ef2aSThomas Huth break; 6846fcf5ef2aSThomas Huth case 0x04: 6847fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6848fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6849fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6850fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6851fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6852fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6853fcf5ef2aSThomas Huth break; 6854fcf5ef2aSThomas Huth case 0x01: 6855fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6856fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6857fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6858fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6859fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6860fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6861fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6862fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6863fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6864fcf5ef2aSThomas Huth break; 6865fcf5ef2aSThomas Huth case 0x00: 6866fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6867fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6868fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6869fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6870fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6871fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6872fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6873fcf5ef2aSThomas Huth break; 6874fcf5ef2aSThomas Huth case 0x0D: 6875fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6876fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6877fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6878fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6879fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6880fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6881fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6882fcf5ef2aSThomas Huth break; 6883fcf5ef2aSThomas Huth case 0x0C: 6884fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6885fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6886fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6887fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6888fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6889fcf5ef2aSThomas Huth break; 6890fcf5ef2aSThomas Huth } 6891fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6892fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6893fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6894fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6895fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6896fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6897fcf5ef2aSThomas Huth } else { 6898fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6899fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6900fcf5ef2aSThomas Huth } 6901fcf5ef2aSThomas Huth 6902fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6903fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6904fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6905fcf5ef2aSThomas Huth 6906fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6907fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6908fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6909fcf5ef2aSThomas Huth } 6910fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6911fcf5ef2aSThomas Huth /* Signed */ 6912fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6913fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6914fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6915fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6916fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6917fcf5ef2aSThomas Huth /* Saturate */ 6918fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6919fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6920fcf5ef2aSThomas Huth } 6921fcf5ef2aSThomas Huth } else { 6922fcf5ef2aSThomas Huth /* Unsigned */ 6923fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6924fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6925fcf5ef2aSThomas Huth /* Saturate */ 6926fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6927fcf5ef2aSThomas Huth } 6928fcf5ef2aSThomas Huth } 6929fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6930fcf5ef2aSThomas Huth /* Check overflow */ 6931fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6932fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6933fcf5ef2aSThomas Huth } 6934fcf5ef2aSThomas Huth gen_set_label(l1); 6935fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6936fcf5ef2aSThomas Huth } 6937fcf5ef2aSThomas Huth } else { 6938fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6939fcf5ef2aSThomas Huth } 6940fcf5ef2aSThomas Huth tcg_temp_free(t0); 6941fcf5ef2aSThomas Huth tcg_temp_free(t1); 6942fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6943fcf5ef2aSThomas Huth /* Update Rc0 */ 6944fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6945fcf5ef2aSThomas Huth } 6946fcf5ef2aSThomas Huth } 6947fcf5ef2aSThomas Huth 6948fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6949fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6950fcf5ef2aSThomas Huth { \ 6951fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6952fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6953fcf5ef2aSThomas Huth } 6954fcf5ef2aSThomas Huth 6955fcf5ef2aSThomas Huth /* macchw - macchw. */ 6956fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6957fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6958fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6959fcf5ef2aSThomas Huth /* macchws - macchws. */ 6960fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6961fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6962fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6963fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6964fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6965fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6966fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6967fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6968fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6969fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6970fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6971fcf5ef2aSThomas Huth /* machhw - machhw. */ 6972fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6973fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6974fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6975fcf5ef2aSThomas Huth /* machhws - machhws. */ 6976fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6977fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6978fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6979fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6980fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6981fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6982fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6983fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6984fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6985fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6986fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6987fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6988fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6989fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6990fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6991fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6992fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6993fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6994fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6995fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6996fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6997fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6998fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6999fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 7000fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 7001fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 7002fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 7003fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 7004fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 7005fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 7006fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 7007fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 7008fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 7009fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 7010fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 7011fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 7012fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 7013fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 7014fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 7015fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 7016fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 7017fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 7018fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 7019fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 7020fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 7021fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 7022fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 7023fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 7024fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 7025fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 7026fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 7027fcf5ef2aSThomas Huth 7028fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 7029fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 7030fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 7031fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 7032fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 7033fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 7034fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7035fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 7036fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7037fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 7038fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7039fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 7040fcf5ef2aSThomas Huth 7041fcf5ef2aSThomas Huth /* mfdcr */ 7042fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 7043fcf5ef2aSThomas Huth { 7044fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7045fcf5ef2aSThomas Huth GEN_PRIV; 7046fcf5ef2aSThomas Huth #else 7047fcf5ef2aSThomas Huth TCGv dcrn; 7048fcf5ef2aSThomas Huth 7049fcf5ef2aSThomas Huth CHK_SV; 7050fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7051fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 7052fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7053fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7054fcf5ef2aSThomas Huth } 7055fcf5ef2aSThomas Huth 7056fcf5ef2aSThomas Huth /* mtdcr */ 7057fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 7058fcf5ef2aSThomas Huth { 7059fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7060fcf5ef2aSThomas Huth GEN_PRIV; 7061fcf5ef2aSThomas Huth #else 7062fcf5ef2aSThomas Huth TCGv dcrn; 7063fcf5ef2aSThomas Huth 7064fcf5ef2aSThomas Huth CHK_SV; 7065fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7066fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 7067fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7068fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7069fcf5ef2aSThomas Huth } 7070fcf5ef2aSThomas Huth 7071fcf5ef2aSThomas Huth /* mfdcrx */ 7072fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7073fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 7074fcf5ef2aSThomas Huth { 7075fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7076fcf5ef2aSThomas Huth GEN_PRIV; 7077fcf5ef2aSThomas Huth #else 7078fcf5ef2aSThomas Huth CHK_SV; 7079fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7080fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7081fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7082fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7083fcf5ef2aSThomas Huth } 7084fcf5ef2aSThomas Huth 7085fcf5ef2aSThomas Huth /* mtdcrx */ 7086fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7087fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 7088fcf5ef2aSThomas Huth { 7089fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7090fcf5ef2aSThomas Huth GEN_PRIV; 7091fcf5ef2aSThomas Huth #else 7092fcf5ef2aSThomas Huth CHK_SV; 7093fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7094fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7095fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7096fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7097fcf5ef2aSThomas Huth } 7098fcf5ef2aSThomas Huth 7099fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 7100fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 7101fcf5ef2aSThomas Huth { 7102fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7103fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7104fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7105fcf5ef2aSThomas Huth } 7106fcf5ef2aSThomas Huth 7107fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 7108fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 7109fcf5ef2aSThomas Huth { 7110fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7111fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7112fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7113fcf5ef2aSThomas Huth } 7114fcf5ef2aSThomas Huth 7115fcf5ef2aSThomas Huth /* dccci */ 7116fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 7117fcf5ef2aSThomas Huth { 7118fcf5ef2aSThomas Huth CHK_SV; 7119fcf5ef2aSThomas Huth /* interpreted as no-op */ 7120fcf5ef2aSThomas Huth } 7121fcf5ef2aSThomas Huth 7122fcf5ef2aSThomas Huth /* dcread */ 7123fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 7124fcf5ef2aSThomas Huth { 7125fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7126fcf5ef2aSThomas Huth GEN_PRIV; 7127fcf5ef2aSThomas Huth #else 7128fcf5ef2aSThomas Huth TCGv EA, val; 7129fcf5ef2aSThomas Huth 7130fcf5ef2aSThomas Huth CHK_SV; 7131fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 7132fcf5ef2aSThomas Huth EA = tcg_temp_new(); 7133fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 7134fcf5ef2aSThomas Huth val = tcg_temp_new(); 7135fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 7136fcf5ef2aSThomas Huth tcg_temp_free(val); 7137fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 7138fcf5ef2aSThomas Huth tcg_temp_free(EA); 7139fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7140fcf5ef2aSThomas Huth } 7141fcf5ef2aSThomas Huth 7142fcf5ef2aSThomas Huth /* icbt */ 7143fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 7144fcf5ef2aSThomas Huth { 7145efe843d8SDavid Gibson /* 7146efe843d8SDavid Gibson * interpreted as no-op 7147efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7148efe843d8SDavid Gibson * does not generate any exception 7149fcf5ef2aSThomas Huth */ 7150fcf5ef2aSThomas Huth } 7151fcf5ef2aSThomas Huth 7152fcf5ef2aSThomas Huth /* iccci */ 7153fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 7154fcf5ef2aSThomas Huth { 7155fcf5ef2aSThomas Huth CHK_SV; 7156fcf5ef2aSThomas Huth /* interpreted as no-op */ 7157fcf5ef2aSThomas Huth } 7158fcf5ef2aSThomas Huth 7159fcf5ef2aSThomas Huth /* icread */ 7160fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 7161fcf5ef2aSThomas Huth { 7162fcf5ef2aSThomas Huth CHK_SV; 7163fcf5ef2aSThomas Huth /* interpreted as no-op */ 7164fcf5ef2aSThomas Huth } 7165fcf5ef2aSThomas Huth 7166fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 7167fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 7168fcf5ef2aSThomas Huth { 7169fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7170fcf5ef2aSThomas Huth GEN_PRIV; 7171fcf5ef2aSThomas Huth #else 7172fcf5ef2aSThomas Huth CHK_SV; 7173fcf5ef2aSThomas Huth /* Restore CPU state */ 7174fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 717559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7176fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7177fcf5ef2aSThomas Huth } 7178fcf5ef2aSThomas Huth 7179fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 7180fcf5ef2aSThomas Huth { 7181fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7182fcf5ef2aSThomas Huth GEN_PRIV; 7183fcf5ef2aSThomas Huth #else 7184fcf5ef2aSThomas Huth CHK_SV; 7185fcf5ef2aSThomas Huth /* Restore CPU state */ 7186fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 718759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7188fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7189fcf5ef2aSThomas Huth } 7190fcf5ef2aSThomas Huth 7191fcf5ef2aSThomas Huth /* BookE specific */ 7192fcf5ef2aSThomas Huth 7193fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7194fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 7195fcf5ef2aSThomas Huth { 7196fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7197fcf5ef2aSThomas Huth GEN_PRIV; 7198fcf5ef2aSThomas Huth #else 7199fcf5ef2aSThomas Huth CHK_SV; 7200fcf5ef2aSThomas Huth /* Restore CPU state */ 7201fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 720259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7203fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7204fcf5ef2aSThomas Huth } 7205fcf5ef2aSThomas Huth 7206fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7207fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 7208fcf5ef2aSThomas Huth { 7209fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7210fcf5ef2aSThomas Huth GEN_PRIV; 7211fcf5ef2aSThomas Huth #else 7212fcf5ef2aSThomas Huth CHK_SV; 7213fcf5ef2aSThomas Huth /* Restore CPU state */ 7214fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 721559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7216fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7217fcf5ef2aSThomas Huth } 7218fcf5ef2aSThomas Huth 7219fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7220fcf5ef2aSThomas Huth 7221fcf5ef2aSThomas Huth /* tlbre */ 7222fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7223fcf5ef2aSThomas Huth { 7224fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7225fcf5ef2aSThomas Huth GEN_PRIV; 7226fcf5ef2aSThomas Huth #else 7227fcf5ef2aSThomas Huth CHK_SV; 7228fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7229fcf5ef2aSThomas Huth case 0: 7230fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7231fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7232fcf5ef2aSThomas Huth break; 7233fcf5ef2aSThomas Huth case 1: 7234fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7235fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7236fcf5ef2aSThomas Huth break; 7237fcf5ef2aSThomas Huth default: 7238fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7239fcf5ef2aSThomas Huth break; 7240fcf5ef2aSThomas Huth } 7241fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7242fcf5ef2aSThomas Huth } 7243fcf5ef2aSThomas Huth 7244fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7245fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7246fcf5ef2aSThomas Huth { 7247fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7248fcf5ef2aSThomas Huth GEN_PRIV; 7249fcf5ef2aSThomas Huth #else 7250fcf5ef2aSThomas Huth TCGv t0; 7251fcf5ef2aSThomas Huth 7252fcf5ef2aSThomas Huth CHK_SV; 7253fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7254fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7255fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7256fcf5ef2aSThomas Huth tcg_temp_free(t0); 7257fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7258fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7259fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7260fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7261fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7262fcf5ef2aSThomas Huth gen_set_label(l1); 7263fcf5ef2aSThomas Huth } 7264fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7265fcf5ef2aSThomas Huth } 7266fcf5ef2aSThomas Huth 7267fcf5ef2aSThomas Huth /* tlbwe */ 7268fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7269fcf5ef2aSThomas Huth { 7270fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7271fcf5ef2aSThomas Huth GEN_PRIV; 7272fcf5ef2aSThomas Huth #else 7273fcf5ef2aSThomas Huth CHK_SV; 7274fcf5ef2aSThomas Huth 7275fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7276fcf5ef2aSThomas Huth case 0: 7277fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7278fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7279fcf5ef2aSThomas Huth break; 7280fcf5ef2aSThomas Huth case 1: 7281fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7282fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7283fcf5ef2aSThomas Huth break; 7284fcf5ef2aSThomas Huth default: 7285fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7286fcf5ef2aSThomas Huth break; 7287fcf5ef2aSThomas Huth } 7288fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7289fcf5ef2aSThomas Huth } 7290fcf5ef2aSThomas Huth 7291fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7292fcf5ef2aSThomas Huth 7293fcf5ef2aSThomas Huth /* tlbre */ 7294fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7295fcf5ef2aSThomas Huth { 7296fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7297fcf5ef2aSThomas Huth GEN_PRIV; 7298fcf5ef2aSThomas Huth #else 7299fcf5ef2aSThomas Huth CHK_SV; 7300fcf5ef2aSThomas Huth 7301fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7302fcf5ef2aSThomas Huth case 0: 7303fcf5ef2aSThomas Huth case 1: 7304fcf5ef2aSThomas Huth case 2: 7305fcf5ef2aSThomas Huth { 7306fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7307fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7308fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7309fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7310fcf5ef2aSThomas Huth } 7311fcf5ef2aSThomas Huth break; 7312fcf5ef2aSThomas Huth default: 7313fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7314fcf5ef2aSThomas Huth break; 7315fcf5ef2aSThomas Huth } 7316fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7317fcf5ef2aSThomas Huth } 7318fcf5ef2aSThomas Huth 7319fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7320fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7321fcf5ef2aSThomas Huth { 7322fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7323fcf5ef2aSThomas Huth GEN_PRIV; 7324fcf5ef2aSThomas Huth #else 7325fcf5ef2aSThomas Huth TCGv t0; 7326fcf5ef2aSThomas Huth 7327fcf5ef2aSThomas Huth CHK_SV; 7328fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7329fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7330fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7331fcf5ef2aSThomas Huth tcg_temp_free(t0); 7332fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7333fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7334fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7335fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7336fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7337fcf5ef2aSThomas Huth gen_set_label(l1); 7338fcf5ef2aSThomas Huth } 7339fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7340fcf5ef2aSThomas Huth } 7341fcf5ef2aSThomas Huth 7342fcf5ef2aSThomas Huth /* tlbwe */ 7343fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7344fcf5ef2aSThomas Huth { 7345fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7346fcf5ef2aSThomas Huth GEN_PRIV; 7347fcf5ef2aSThomas Huth #else 7348fcf5ef2aSThomas Huth CHK_SV; 7349fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7350fcf5ef2aSThomas Huth case 0: 7351fcf5ef2aSThomas Huth case 1: 7352fcf5ef2aSThomas Huth case 2: 7353fcf5ef2aSThomas Huth { 7354fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7355fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7356fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7357fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7358fcf5ef2aSThomas Huth } 7359fcf5ef2aSThomas Huth break; 7360fcf5ef2aSThomas Huth default: 7361fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7362fcf5ef2aSThomas Huth break; 7363fcf5ef2aSThomas Huth } 7364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7365fcf5ef2aSThomas Huth } 7366fcf5ef2aSThomas Huth 7367fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7368fcf5ef2aSThomas Huth 7369fcf5ef2aSThomas Huth /* tlbre */ 7370fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7371fcf5ef2aSThomas Huth { 7372fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7373fcf5ef2aSThomas Huth GEN_PRIV; 7374fcf5ef2aSThomas Huth #else 7375fcf5ef2aSThomas Huth CHK_SV; 7376fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7377fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7378fcf5ef2aSThomas Huth } 7379fcf5ef2aSThomas Huth 7380fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7381fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7382fcf5ef2aSThomas Huth { 7383fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7384fcf5ef2aSThomas Huth GEN_PRIV; 7385fcf5ef2aSThomas Huth #else 7386fcf5ef2aSThomas Huth TCGv t0; 7387fcf5ef2aSThomas Huth 7388fcf5ef2aSThomas Huth CHK_SV; 7389fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7390fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7391fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7392fcf5ef2aSThomas Huth } else { 7393fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7394fcf5ef2aSThomas Huth } 7395fcf5ef2aSThomas Huth 7396fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7397fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7398fcf5ef2aSThomas Huth tcg_temp_free(t0); 7399fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7400fcf5ef2aSThomas Huth } 7401fcf5ef2aSThomas Huth 7402fcf5ef2aSThomas Huth /* tlbwe */ 7403fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7404fcf5ef2aSThomas Huth { 7405fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7406fcf5ef2aSThomas Huth GEN_PRIV; 7407fcf5ef2aSThomas Huth #else 7408fcf5ef2aSThomas Huth CHK_SV; 7409fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7410fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7411fcf5ef2aSThomas Huth } 7412fcf5ef2aSThomas Huth 7413fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7414fcf5ef2aSThomas Huth { 7415fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7416fcf5ef2aSThomas Huth GEN_PRIV; 7417fcf5ef2aSThomas Huth #else 7418fcf5ef2aSThomas Huth TCGv t0; 7419fcf5ef2aSThomas Huth 7420fcf5ef2aSThomas Huth CHK_SV; 7421fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7422fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7423fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7424fcf5ef2aSThomas Huth tcg_temp_free(t0); 7425fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7426fcf5ef2aSThomas Huth } 7427fcf5ef2aSThomas Huth 7428fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7429fcf5ef2aSThomas Huth { 7430fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7431fcf5ef2aSThomas Huth GEN_PRIV; 7432fcf5ef2aSThomas Huth #else 7433fcf5ef2aSThomas Huth TCGv t0; 7434fcf5ef2aSThomas Huth 7435fcf5ef2aSThomas Huth CHK_SV; 7436fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7437fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7438fcf5ef2aSThomas Huth 7439fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7440fcf5ef2aSThomas Huth case 0: 7441fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7442fcf5ef2aSThomas Huth break; 7443fcf5ef2aSThomas Huth case 1: 7444fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7445fcf5ef2aSThomas Huth break; 7446fcf5ef2aSThomas Huth case 3: 7447fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7448fcf5ef2aSThomas Huth break; 7449fcf5ef2aSThomas Huth default: 7450fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7451fcf5ef2aSThomas Huth break; 7452fcf5ef2aSThomas Huth } 7453fcf5ef2aSThomas Huth 7454fcf5ef2aSThomas Huth tcg_temp_free(t0); 7455fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7456fcf5ef2aSThomas Huth } 7457fcf5ef2aSThomas Huth 7458fcf5ef2aSThomas Huth 7459fcf5ef2aSThomas Huth /* wrtee */ 7460fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7461fcf5ef2aSThomas Huth { 7462fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7463fcf5ef2aSThomas Huth GEN_PRIV; 7464fcf5ef2aSThomas Huth #else 7465fcf5ef2aSThomas Huth TCGv t0; 7466fcf5ef2aSThomas Huth 7467fcf5ef2aSThomas Huth CHK_SV; 7468fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7469fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7470fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7471fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7472fcf5ef2aSThomas Huth tcg_temp_free(t0); 7473efe843d8SDavid Gibson /* 7474efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7475efe843d8SDavid Gibson * just set msr_ee to 1 7476fcf5ef2aSThomas Huth */ 7477d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7478fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7479fcf5ef2aSThomas Huth } 7480fcf5ef2aSThomas Huth 7481fcf5ef2aSThomas Huth /* wrteei */ 7482fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7483fcf5ef2aSThomas Huth { 7484fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7485fcf5ef2aSThomas Huth GEN_PRIV; 7486fcf5ef2aSThomas Huth #else 7487fcf5ef2aSThomas Huth CHK_SV; 7488fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7489fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7490fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7491d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7492fcf5ef2aSThomas Huth } else { 7493fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7494fcf5ef2aSThomas Huth } 7495fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7496fcf5ef2aSThomas Huth } 7497fcf5ef2aSThomas Huth 7498fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7499fcf5ef2aSThomas Huth 7500fcf5ef2aSThomas Huth /* dlmzb */ 7501fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7502fcf5ef2aSThomas Huth { 7503fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7504fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7505fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7506fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7507fcf5ef2aSThomas Huth } 7508fcf5ef2aSThomas Huth 7509fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7510fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7511fcf5ef2aSThomas Huth { 7512fcf5ef2aSThomas Huth /* interpreted as no-op */ 7513fcf5ef2aSThomas Huth } 7514fcf5ef2aSThomas Huth 7515fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7516fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7517fcf5ef2aSThomas Huth { 751827a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 751927a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 752027a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 752127a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 752227a3ea7eSBALATON Zoltan } 752327a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7524fcf5ef2aSThomas Huth } 7525fcf5ef2aSThomas Huth 7526fcf5ef2aSThomas Huth /* icbt */ 7527fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7528fcf5ef2aSThomas Huth { 7529efe843d8SDavid Gibson /* 7530efe843d8SDavid Gibson * interpreted as no-op 7531efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7532efe843d8SDavid Gibson * does not generate any exception 7533fcf5ef2aSThomas Huth */ 7534fcf5ef2aSThomas Huth } 7535fcf5ef2aSThomas Huth 7536fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7537fcf5ef2aSThomas Huth 7538fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7539fcf5ef2aSThomas Huth { 7540fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7541fcf5ef2aSThomas Huth GEN_PRIV; 7542fcf5ef2aSThomas Huth #else 7543ebca5e6dSCédric Le Goater CHK_HV; 7544d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 75457af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 75467af1e7b0SCédric Le Goater } else { 7547fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 75487af1e7b0SCédric Le Goater } 7549fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7550fcf5ef2aSThomas Huth } 7551fcf5ef2aSThomas Huth 7552fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7553fcf5ef2aSThomas Huth { 7554fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7555fcf5ef2aSThomas Huth GEN_PRIV; 7556fcf5ef2aSThomas Huth #else 7557ebca5e6dSCédric Le Goater CHK_HV; 7558d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 75597af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 75607af1e7b0SCédric Le Goater } else { 7561fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 75627af1e7b0SCédric Le Goater } 7563fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7564fcf5ef2aSThomas Huth } 7565fcf5ef2aSThomas Huth 75665ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 75675ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 75685ba7ba1dSCédric Le Goater { 75695ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 75705ba7ba1dSCédric Le Goater GEN_PRIV; 75715ba7ba1dSCédric Le Goater #else 75725ba7ba1dSCédric Le Goater CHK_SV; 75735ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 75745ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 75755ba7ba1dSCédric Le Goater } 75765ba7ba1dSCédric Le Goater 75775ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 75785ba7ba1dSCédric Le Goater { 75795ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 75805ba7ba1dSCédric Le Goater GEN_PRIV; 75815ba7ba1dSCédric Le Goater #else 75825ba7ba1dSCédric Le Goater CHK_SV; 75835ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 75845ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 75855ba7ba1dSCédric Le Goater } 75865ba7ba1dSCédric Le Goater #endif 75875ba7ba1dSCédric Le Goater 75887af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 75897af1e7b0SCédric Le Goater { 75907af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 75917af1e7b0SCédric Le Goater GEN_PRIV; 75927af1e7b0SCédric Le Goater #else 75937af1e7b0SCédric Le Goater CHK_HV; 75947af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 75957af1e7b0SCédric Le Goater /* interpreted as no-op */ 75967af1e7b0SCédric Le Goater } 7597fcf5ef2aSThomas Huth 7598fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7599fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7600fcf5ef2aSThomas Huth { 7601fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7602fcf5ef2aSThomas Huth 7603fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7604fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7605fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7606fcf5ef2aSThomas Huth } 7607fcf5ef2aSThomas Huth 7608fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7609fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7610fcf5ef2aSThomas Huth { 7611fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7612fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7613fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7614fcf5ef2aSThomas Huth 7615fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7616fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7617fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7618fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7619fcf5ef2aSThomas Huth } else { 7620fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7621fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7622fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7623fcf5ef2aSThomas Huth } 7624fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7625fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7626fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7627fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7628fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7629fcf5ef2aSThomas Huth } 7630fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7631fcf5ef2aSThomas Huth 7632fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7633fcf5ef2aSThomas Huth { 7634fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7635fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7636fcf5ef2aSThomas Huth return; 7637fcf5ef2aSThomas Huth } 7638fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7639fcf5ef2aSThomas Huth } 7640fcf5ef2aSThomas Huth 7641fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7642fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7643fcf5ef2aSThomas Huth { \ 7644fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7645fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7646fcf5ef2aSThomas Huth return; \ 7647fcf5ef2aSThomas Huth } \ 7648efe843d8SDavid Gibson /* \ 7649efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7650fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7651fcf5ef2aSThomas Huth * \ 7652fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7653fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7654fcf5ef2aSThomas Huth */ \ 7655fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7656fcf5ef2aSThomas Huth } 7657fcf5ef2aSThomas Huth 7658fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7659fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7660fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7661fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7662fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7663fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7664fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7665efe843d8SDavid Gibson 7666b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7667b8b4576eSSuraj Jitindar Singh { 7668efe843d8SDavid Gibson /* Do Nothing */ 7669b8b4576eSSuraj Jitindar Singh } 7670fcf5ef2aSThomas Huth 767180b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 767280b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 767380b8c1eeSNikunj A Dadhania { \ 7674efe843d8SDavid Gibson /* \ 7675efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7676efe843d8SDavid Gibson * implementation of the copy paste facility \ 767780b8c1eeSNikunj A Dadhania */ \ 767880b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 767980b8c1eeSNikunj A Dadhania } 768080b8c1eeSNikunj A Dadhania 768180b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 768280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 768380b8c1eeSNikunj A Dadhania 7684fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7685fcf5ef2aSThomas Huth { 7686fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7687fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7688fcf5ef2aSThomas Huth return; 7689fcf5ef2aSThomas Huth } 7690efe843d8SDavid Gibson /* 7691efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7692efe843d8SDavid Gibson * simple: 7693fcf5ef2aSThomas Huth * 7694fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7695fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7696fcf5ef2aSThomas Huth */ 7697fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7698fcf5ef2aSThomas Huth } 7699fcf5ef2aSThomas Huth 7700fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7701fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7702fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7703fcf5ef2aSThomas Huth { \ 7704fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7705fcf5ef2aSThomas Huth } 7706fcf5ef2aSThomas Huth 7707fcf5ef2aSThomas Huth #else 7708fcf5ef2aSThomas Huth 7709fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7710fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7711fcf5ef2aSThomas Huth { \ 7712fcf5ef2aSThomas Huth CHK_SV; \ 7713fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7714fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7715fcf5ef2aSThomas Huth return; \ 7716fcf5ef2aSThomas Huth } \ 7717efe843d8SDavid Gibson /* \ 7718efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7719fcf5ef2aSThomas Huth * simple: \ 7720fcf5ef2aSThomas Huth * \ 7721fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7722fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7723fcf5ef2aSThomas Huth */ \ 7724fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7725fcf5ef2aSThomas Huth } 7726fcf5ef2aSThomas Huth 7727fcf5ef2aSThomas Huth #endif 7728fcf5ef2aSThomas Huth 7729fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7730fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7731fcf5ef2aSThomas Huth 77321a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 77331a404c91SMark Cave-Ayland { 7734e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 77351a404c91SMark Cave-Ayland } 77361a404c91SMark Cave-Ayland 77371a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 77381a404c91SMark Cave-Ayland { 7739e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 77401a404c91SMark Cave-Ayland } 77411a404c91SMark Cave-Ayland 7742c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7743c4a18dbfSMark Cave-Ayland { 774437da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7745c4a18dbfSMark Cave-Ayland } 7746c4a18dbfSMark Cave-Ayland 7747c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7748c4a18dbfSMark Cave-Ayland { 774937da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7750c4a18dbfSMark Cave-Ayland } 7751c4a18dbfSMark Cave-Ayland 7752139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7753fcf5ef2aSThomas Huth 7754139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7755fcf5ef2aSThomas Huth 7756139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7757fcf5ef2aSThomas Huth 7758139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7759fcf5ef2aSThomas Huth 7760139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7761fcf5ef2aSThomas Huth 77625cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 77635cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 77645cb091a4SNikunj A Dadhania { 77655cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 77665cb091a4SNikunj A Dadhania case 0: /* lfdp */ 77675cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 77685cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 77695cb091a4SNikunj A Dadhania } 77705cb091a4SNikunj A Dadhania break; 77715cb091a4SNikunj A Dadhania case 2: /* lxsd */ 77725cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 77735cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 77745cb091a4SNikunj A Dadhania } 77755cb091a4SNikunj A Dadhania break; 77765cb091a4SNikunj A Dadhania case 3: /* lxssp */ 77775cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 77785cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 77795cb091a4SNikunj A Dadhania } 77805cb091a4SNikunj A Dadhania break; 77815cb091a4SNikunj A Dadhania } 77825cb091a4SNikunj A Dadhania return gen_invalid(ctx); 77835cb091a4SNikunj A Dadhania } 77845cb091a4SNikunj A Dadhania 7785d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7786e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7787e3001664SNikunj A Dadhania { 7788e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7789e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7790e3001664SNikunj A Dadhania case 1: /* lxv */ 7791d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7792d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7793d59ba583SNikunj A Dadhania } 7794e3001664SNikunj A Dadhania break; 7795e3001664SNikunj A Dadhania case 5: /* stxv */ 7796d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7797d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7798d59ba583SNikunj A Dadhania } 7799e3001664SNikunj A Dadhania break; 7800e3001664SNikunj A Dadhania } 7801e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7802e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7803e3001664SNikunj A Dadhania case 0: /* stfdp */ 7804e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7805e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7806e3001664SNikunj A Dadhania } 7807e3001664SNikunj A Dadhania break; 7808e3001664SNikunj A Dadhania case 2: /* stxsd */ 7809e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7810e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7811e3001664SNikunj A Dadhania } 7812e3001664SNikunj A Dadhania break; 7813e3001664SNikunj A Dadhania case 3: /* stxssp */ 7814e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7815e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7816e3001664SNikunj A Dadhania } 7817e3001664SNikunj A Dadhania break; 7818e3001664SNikunj A Dadhania } 7819e3001664SNikunj A Dadhania } 7820e3001664SNikunj A Dadhania return gen_invalid(ctx); 7821e3001664SNikunj A Dadhania } 7822e3001664SNikunj A Dadhania 78239d69cfa2SLijun Pan #if defined(TARGET_PPC64) 78249d69cfa2SLijun Pan /* brd */ 78259d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 78269d69cfa2SLijun Pan { 78279d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 78289d69cfa2SLijun Pan } 78299d69cfa2SLijun Pan 78309d69cfa2SLijun Pan /* brw */ 78319d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 78329d69cfa2SLijun Pan { 78339d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 78349d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 78359d69cfa2SLijun Pan 78369d69cfa2SLijun Pan } 78379d69cfa2SLijun Pan 78389d69cfa2SLijun Pan /* brh */ 78399d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 78409d69cfa2SLijun Pan { 78419d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 78429d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 78439d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 78449d69cfa2SLijun Pan 78459d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 78469d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 78479d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 78489d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 78499d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 78509d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 78519d69cfa2SLijun Pan 78529d69cfa2SLijun Pan tcg_temp_free_i64(t0); 78539d69cfa2SLijun Pan tcg_temp_free_i64(t1); 78549d69cfa2SLijun Pan tcg_temp_free_i64(t2); 78559d69cfa2SLijun Pan } 78569d69cfa2SLijun Pan #endif 78579d69cfa2SLijun Pan 7858fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 78599d69cfa2SLijun Pan #if defined(TARGET_PPC64) 78609d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 78619d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 78629d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 78639d69cfa2SLijun Pan #endif 7864fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7865fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7866fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7867fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7868fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7869fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7870fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7871fcf5ef2aSThomas Huth #endif 7872fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7873fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7874fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7875fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7876fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7877fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7878fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7879fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7880fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7881fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7882fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7883fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7884fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7885fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7886fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7887fcf5ef2aSThomas Huth #endif 7888fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7889fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7890fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7891fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7892fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7893fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7894fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 789580b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7896b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 789780b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7898fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7899fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7900fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7901fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7902fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7903fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7904fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7905fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7906fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7907fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7908fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7909fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7910fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7911fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7912fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7913fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7914fcf5ef2aSThomas Huth #endif 7915fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7916fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7917fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7918fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7919fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7920fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7921fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7922fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7923fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7924fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7925fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7926fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7927fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7928fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7929fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7930fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7931fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7932fcf5ef2aSThomas Huth #endif 7933fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7934fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 7935fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7936fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7937fcf5ef2aSThomas Huth #endif 79385cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 79395cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7940d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7941e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7942fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7943fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7944fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7945fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7946fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7947fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7948c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7949fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7950fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7951fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7952fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7953a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7954a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7955fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7956fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7957fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7958fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7959a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7960a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7961fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7962fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7963fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7964fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7965fcf5ef2aSThomas Huth #endif 7966fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7967fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7968c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7969fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7970fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7971fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7972fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7973fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7974fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7975fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7976fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7977fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 79783c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 79793c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 79803c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 79813c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 79823c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 79833c89b8d6SNicholas Piggin #endif 7984cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7985fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7986fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7987fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7988fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7989fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7990fcf5ef2aSThomas Huth #endif 79913c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 79923c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 79933c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7994fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7995fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7996fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7997fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7998fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7999fcf5ef2aSThomas Huth #endif 8000fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 8001fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 8002fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 8003fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 8004fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 8005fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 8006fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8007fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 8008fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 8009b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 8010fcf5ef2aSThomas Huth #endif 8011fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 8012fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 8013fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 801450728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8015fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 8016fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 801750728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8018fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 801950728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8020fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 802150728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8022fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 8023fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 802450728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8025fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 802699d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 8027fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 8028fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 802950728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8030fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 8031fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 8032fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 8033fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 8034fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 8035fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8036fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 8037fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 8038fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8039fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 8040fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 8041fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8042fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 8043fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 8044fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 8045fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 8046fcf5ef2aSThomas Huth #endif 8047fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 8048efe843d8SDavid Gibson /* 8049efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 8050efe843d8SDavid Gibson * different ISA versions 8051efe843d8SDavid Gibson */ 8052fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 8053fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 8054c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 8055c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 8056fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 8057fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8058fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 8059fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 8060a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 806162d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8062fcf5ef2aSThomas Huth #endif 8063fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 8064fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 8065fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 8066fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 8067fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 8068fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 8069fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 8070fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 8071fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 8072fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 8073fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 8074fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8075fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 8076fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 8077fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 8078fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 8079fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 8080fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 8081fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 8082fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8083fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 8084fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 8085fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 8086fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 8087fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 8088fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 8089fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 8090fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 8091fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 8092fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 8093fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 8094fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 8095fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 8096fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 8097fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 8098fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 8099fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 8100fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 8101fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 8102fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 8103fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 8104fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 8105fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 8106fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 8107fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 8108fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 8109fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 8110fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 8111fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 8112fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8113fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8114fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 8115fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 8116fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8117fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8118fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 8119fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 8120fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 8121fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 8122fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 8123fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 8124fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 8125fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 8126fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 8127fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 8128fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 8129fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 8130fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 8131fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 8132fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 8133fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 8134fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 8135fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 8136fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 8137fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 8138fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 8139fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 8140fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 8141fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 8142fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 8143fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 8144fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8145fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 8146fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8147fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 8148fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8149fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 8150fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8151fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 8152fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8153fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 8154fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 8155fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 8156fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 81577af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 81587af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 8159fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8160fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8161fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8162fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8163fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 816427a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8165fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8166fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 81670c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 81680c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8169fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8170fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8171fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8172fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8173fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8174fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8175fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8176fcf5ef2aSThomas Huth PPC2_ISA300), 8177fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 81785ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 81795ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 81805ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 81815ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8182fcf5ef2aSThomas Huth #endif 8183fcf5ef2aSThomas Huth 8184fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8185fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8186fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8187fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8188fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8189fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8190fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8191fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8192fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8193fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8194fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8195fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8196fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8197fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8198fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 81994c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8200fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8201fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8202fcf5ef2aSThomas Huth 8203fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8204fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8205fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8206fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8207fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8208fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8209fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8210fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8211fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8212fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8213fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8214fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8215fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8216fcf5ef2aSThomas Huth 8217fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8218fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8219fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8220fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8221fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8222fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8223fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8224fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8225fcf5ef2aSThomas Huth 8226fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8227fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8228fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8229fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8230fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8231fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8232fcf5ef2aSThomas Huth 8233fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8234fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8235fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8236fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8237fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8238fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8239fcf5ef2aSThomas Huth #endif 8240fcf5ef2aSThomas Huth 8241fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8242fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8243fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8244fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8245fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8246fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8247fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8248fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8249fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8250fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8251fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8252fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8253fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8254fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8255fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8256fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8257fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8258fcf5ef2aSThomas Huth 8259fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8260fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8261fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8262fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8263fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8264fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8265fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8266fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8267fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8268fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8269fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8270fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8271fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8272fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8273fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8274fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8275fcf5ef2aSThomas Huth #endif 8276fcf5ef2aSThomas Huth 8277fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8278fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8279fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8280fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8281fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8282fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8283fcf5ef2aSThomas Huth PPC_64B) 8284fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8285fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8286fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8287fcf5ef2aSThomas Huth PPC_64B), \ 8288fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8289fcf5ef2aSThomas Huth PPC_64B), \ 8290fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8291fcf5ef2aSThomas Huth PPC_64B) 8292fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8293fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8294fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8295fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8296fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8297fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8298fcf5ef2aSThomas Huth #endif 8299fcf5ef2aSThomas Huth 8300fcf5ef2aSThomas Huth #undef GEN_LD 8301fcf5ef2aSThomas Huth #undef GEN_LDU 8302fcf5ef2aSThomas Huth #undef GEN_LDUX 8303fcf5ef2aSThomas Huth #undef GEN_LDX_E 8304fcf5ef2aSThomas Huth #undef GEN_LDS 8305fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 8306fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8307fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 8308fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 8309fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 8310fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8311fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8312fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8313fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 8314fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 8315fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 8316fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 8317fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 8318fcf5ef2aSThomas Huth 8319fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 8320fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 8321fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 8322fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 8323fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8324fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 8325fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 8326fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 8327fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 8328fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8329fcf5ef2aSThomas Huth 8330fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8331fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8332fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8333fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8334fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8335fcf5ef2aSThomas Huth #endif 8336fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8337fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8338fcf5ef2aSThomas Huth 833950728199SRoman Kapl /* External PID based load */ 834050728199SRoman Kapl #undef GEN_LDEPX 834150728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 834250728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 834350728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 834450728199SRoman Kapl 834550728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 834650728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 834750728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 834850728199SRoman Kapl #if defined(TARGET_PPC64) 834950728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 835050728199SRoman Kapl #endif 835150728199SRoman Kapl 8352fcf5ef2aSThomas Huth #undef GEN_ST 8353fcf5ef2aSThomas Huth #undef GEN_STU 8354fcf5ef2aSThomas Huth #undef GEN_STUX 8355fcf5ef2aSThomas Huth #undef GEN_STX_E 8356fcf5ef2aSThomas Huth #undef GEN_STS 8357fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8358fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8359fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8360fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8361fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8362fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8363fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 83640123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8365fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8366fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8367fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8368fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8369fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8370fcf5ef2aSThomas Huth 8371fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8372fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8373fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8374fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8375fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8376fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8377fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8378fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8379fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8380fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8381fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8382fcf5ef2aSThomas Huth #endif 8383fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8384fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8385fcf5ef2aSThomas Huth 838650728199SRoman Kapl #undef GEN_STEPX 838750728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 838850728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 838950728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 839050728199SRoman Kapl 839150728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 839250728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 839350728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 839450728199SRoman Kapl #if defined(TARGET_PPC64) 839550728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 839650728199SRoman Kapl #endif 839750728199SRoman Kapl 8398fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8399fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8400fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8401fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8402fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8403fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8404fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8405fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8406fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8407fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8408fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8409fcf5ef2aSThomas Huth 8410fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8411fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8412fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8413fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8414fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8415fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8416fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8417fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8418fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8419fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8420fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8421fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8422fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8423fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8424fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8425fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8426fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8427fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8428fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8429fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8430fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8431fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8432fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8433fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8434fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8435fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8436fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8437fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8438fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8439fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8440fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8441fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8442fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8443fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8444fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8445fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8446fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8447fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8448fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8449fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8450fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8451fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8452fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8453fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8454fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8455fcf5ef2aSThomas Huth 8456fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8457fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8458fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8459fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8460fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8461fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8462fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8463fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8464fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8465fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8466fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8467fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8468fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8469fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8470fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8471fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8472fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8473fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8474fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8475fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8476fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8477fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8478fcf5ef2aSThomas Huth 8479139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8480fcf5ef2aSThomas Huth 8481139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8482fcf5ef2aSThomas Huth 8483139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8484fcf5ef2aSThomas Huth 8485139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8486fcf5ef2aSThomas Huth 8487139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8488fcf5ef2aSThomas Huth }; 8489fcf5ef2aSThomas Huth 84907468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 84917468e2c8SBruno Larsen (billionai) /* Opcode types */ 84927468e2c8SBruno Larsen (billionai) enum { 84937468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 84947468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 84957468e2c8SBruno Larsen (billionai) }; 84967468e2c8SBruno Larsen (billionai) 84977468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 84987468e2c8SBruno Larsen (billionai) 84997468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 85007468e2c8SBruno Larsen (billionai) { 85017468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 85027468e2c8SBruno Larsen (billionai) } 85037468e2c8SBruno Larsen (billionai) 85047468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 85057468e2c8SBruno Larsen (billionai) { 85067468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 85077468e2c8SBruno Larsen (billionai) } 85087468e2c8SBruno Larsen (billionai) 85097468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 85107468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 85117468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 85127468e2c8SBruno Larsen (billionai) { 85137468e2c8SBruno Larsen (billionai) int i; 85147468e2c8SBruno Larsen (billionai) 85157468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 85167468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 85177468e2c8SBruno Larsen (billionai) } 85187468e2c8SBruno Larsen (billionai) } 85197468e2c8SBruno Larsen (billionai) 85207468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 85217468e2c8SBruno Larsen (billionai) { 85227468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 85237468e2c8SBruno Larsen (billionai) 85247468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 85257468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 85267468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 85277468e2c8SBruno Larsen (billionai) 85287468e2c8SBruno Larsen (billionai) return 0; 85297468e2c8SBruno Larsen (billionai) } 85307468e2c8SBruno Larsen (billionai) 85317468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 85327468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 85337468e2c8SBruno Larsen (billionai) { 85347468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 85357468e2c8SBruno Larsen (billionai) return -1; 85367468e2c8SBruno Larsen (billionai) } 85377468e2c8SBruno Larsen (billionai) table[idx] = handler; 85387468e2c8SBruno Larsen (billionai) 85397468e2c8SBruno Larsen (billionai) return 0; 85407468e2c8SBruno Larsen (billionai) } 85417468e2c8SBruno Larsen (billionai) 85427468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 85437468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 85447468e2c8SBruno Larsen (billionai) { 85457468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 85467468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 85477468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 85487468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 85497468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 85507468e2c8SBruno Larsen (billionai) ppc_opcodes[idx]->oname, handler->oname); 85517468e2c8SBruno Larsen (billionai) #endif 85527468e2c8SBruno Larsen (billionai) return -1; 85537468e2c8SBruno Larsen (billionai) } 85547468e2c8SBruno Larsen (billionai) 85557468e2c8SBruno Larsen (billionai) return 0; 85567468e2c8SBruno Larsen (billionai) } 85577468e2c8SBruno Larsen (billionai) 85587468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 85597468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 85607468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 85617468e2c8SBruno Larsen (billionai) { 85627468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 85637468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 85647468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 85657468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 85667468e2c8SBruno Larsen (billionai) return -1; 85677468e2c8SBruno Larsen (billionai) } 85687468e2c8SBruno Larsen (billionai) } else { 85697468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 85707468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 85717468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 85727468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 85737468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 85747468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 85757468e2c8SBruno Larsen (billionai) #endif 85767468e2c8SBruno Larsen (billionai) return -1; 85777468e2c8SBruno Larsen (billionai) } 85787468e2c8SBruno Larsen (billionai) } 85797468e2c8SBruno Larsen (billionai) if (handler != NULL && 85807468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 85817468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 85827468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 85837468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 85847468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 85857468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 85867468e2c8SBruno Larsen (billionai) #endif 85877468e2c8SBruno Larsen (billionai) return -1; 85887468e2c8SBruno Larsen (billionai) } 85897468e2c8SBruno Larsen (billionai) 85907468e2c8SBruno Larsen (billionai) return 0; 85917468e2c8SBruno Larsen (billionai) } 85927468e2c8SBruno Larsen (billionai) 85937468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 85947468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 85957468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 85967468e2c8SBruno Larsen (billionai) { 85977468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 85987468e2c8SBruno Larsen (billionai) } 85997468e2c8SBruno Larsen (billionai) 86007468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 86017468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86027468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 86037468e2c8SBruno Larsen (billionai) { 86047468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 86057468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 86067468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 86077468e2c8SBruno Larsen (billionai) return -1; 86087468e2c8SBruno Larsen (billionai) } 86097468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 86107468e2c8SBruno Larsen (billionai) handler) < 0) { 86117468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 86127468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 86137468e2c8SBruno Larsen (billionai) return -1; 86147468e2c8SBruno Larsen (billionai) } 86157468e2c8SBruno Larsen (billionai) 86167468e2c8SBruno Larsen (billionai) return 0; 86177468e2c8SBruno Larsen (billionai) } 86187468e2c8SBruno Larsen (billionai) 86197468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 86207468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86217468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 86227468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86237468e2c8SBruno Larsen (billionai) { 86247468e2c8SBruno Larsen (billionai) opc_handler_t **table; 86257468e2c8SBruno Larsen (billionai) 86267468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 86277468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 86287468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 86297468e2c8SBruno Larsen (billionai) return -1; 86307468e2c8SBruno Larsen (billionai) } 86317468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 86327468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 86337468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 86347468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 86357468e2c8SBruno Larsen (billionai) return -1; 86367468e2c8SBruno Larsen (billionai) } 86377468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 86387468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 86397468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 86407468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 86417468e2c8SBruno Larsen (billionai) return -1; 86427468e2c8SBruno Larsen (billionai) } 86437468e2c8SBruno Larsen (billionai) return 0; 86447468e2c8SBruno Larsen (billionai) } 86457468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 86467468e2c8SBruno Larsen (billionai) { 86477468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 86487468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 86497468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 86507468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 86517468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 86527468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 86537468e2c8SBruno Larsen (billionai) return -1; 86547468e2c8SBruno Larsen (billionai) } 86557468e2c8SBruno Larsen (billionai) } else { 86567468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 86577468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 86587468e2c8SBruno Larsen (billionai) return -1; 86597468e2c8SBruno Larsen (billionai) } 86607468e2c8SBruno Larsen (billionai) } 86617468e2c8SBruno Larsen (billionai) } else { 86627468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 86637468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 86647468e2c8SBruno Larsen (billionai) return -1; 86657468e2c8SBruno Larsen (billionai) } 86667468e2c8SBruno Larsen (billionai) } 86677468e2c8SBruno Larsen (billionai) } else { 86687468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 86697468e2c8SBruno Larsen (billionai) return -1; 86707468e2c8SBruno Larsen (billionai) } 86717468e2c8SBruno Larsen (billionai) } 86727468e2c8SBruno Larsen (billionai) 86737468e2c8SBruno Larsen (billionai) return 0; 86747468e2c8SBruno Larsen (billionai) } 86757468e2c8SBruno Larsen (billionai) 86767468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 86777468e2c8SBruno Larsen (billionai) { 86787468e2c8SBruno Larsen (billionai) int i, count, tmp; 86797468e2c8SBruno Larsen (billionai) 86807468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 86817468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 86827468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 86837468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86847468e2c8SBruno Larsen (billionai) } 86857468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 86867468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 86877468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 86887468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 86897468e2c8SBruno Larsen (billionai) if (tmp == 0) { 86907468e2c8SBruno Larsen (billionai) free(table[i]); 86917468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86927468e2c8SBruno Larsen (billionai) } else { 86937468e2c8SBruno Larsen (billionai) count++; 86947468e2c8SBruno Larsen (billionai) } 86957468e2c8SBruno Larsen (billionai) } else { 86967468e2c8SBruno Larsen (billionai) count++; 86977468e2c8SBruno Larsen (billionai) } 86987468e2c8SBruno Larsen (billionai) } 86997468e2c8SBruno Larsen (billionai) } 87007468e2c8SBruno Larsen (billionai) 87017468e2c8SBruno Larsen (billionai) return count; 87027468e2c8SBruno Larsen (billionai) } 87037468e2c8SBruno Larsen (billionai) 87047468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 87057468e2c8SBruno Larsen (billionai) { 87067468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 87077468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 87087468e2c8SBruno Larsen (billionai) } 87097468e2c8SBruno Larsen (billionai) } 87107468e2c8SBruno Larsen (billionai) 87117468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 87127468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 87137468e2c8SBruno Larsen (billionai) { 87147468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 87157468e2c8SBruno Larsen (billionai) opcode_t *opc; 87167468e2c8SBruno Larsen (billionai) 87177468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 87187468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 87197468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 87207468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 87217468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 87227468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 87237468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 87247468e2c8SBruno Larsen (billionai) opc->opc3); 87257468e2c8SBruno Larsen (billionai) return; 87267468e2c8SBruno Larsen (billionai) } 87277468e2c8SBruno Larsen (billionai) } 87287468e2c8SBruno Larsen (billionai) } 87297468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 87307468e2c8SBruno Larsen (billionai) fflush(stdout); 87317468e2c8SBruno Larsen (billionai) fflush(stderr); 87327468e2c8SBruno Larsen (billionai) } 87337468e2c8SBruno Larsen (billionai) 87347468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 87357468e2c8SBruno Larsen (billionai) { 87367468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 87377468e2c8SBruno Larsen (billionai) int i, j, k; 87387468e2c8SBruno Larsen (billionai) 87397468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 87407468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 87417468e2c8SBruno Larsen (billionai) continue; 87427468e2c8SBruno Larsen (billionai) } 87437468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 87447468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 87457468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 87467468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 87477468e2c8SBruno Larsen (billionai) continue; 87487468e2c8SBruno Larsen (billionai) } 87497468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 87507468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 87517468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 87527468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 87537468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 87547468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 87557468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 87567468e2c8SBruno Larsen (billionai) } 87577468e2c8SBruno Larsen (billionai) } 87587468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 87597468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 87607468e2c8SBruno Larsen (billionai) } 87617468e2c8SBruno Larsen (billionai) } 87627468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 87637468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 87647468e2c8SBruno Larsen (billionai) } 87657468e2c8SBruno Larsen (billionai) } 87667468e2c8SBruno Larsen (billionai) } 87677468e2c8SBruno Larsen (billionai) 87687468e2c8SBruno Larsen (billionai) #if defined(PPC_DUMP_CPU) 87697468e2c8SBruno Larsen (billionai) static void dump_ppc_insns(CPUPPCState *env) 87707468e2c8SBruno Larsen (billionai) { 87717468e2c8SBruno Larsen (billionai) opc_handler_t **table, *handler; 87727468e2c8SBruno Larsen (billionai) const char *p, *q; 87737468e2c8SBruno Larsen (billionai) uint8_t opc1, opc2, opc3, opc4; 87747468e2c8SBruno Larsen (billionai) 87757468e2c8SBruno Larsen (billionai) printf("Instructions set:\n"); 87767468e2c8SBruno Larsen (billionai) /* opc1 is 6 bits long */ 87777468e2c8SBruno Larsen (billionai) for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 87787468e2c8SBruno Larsen (billionai) table = env->opcodes; 87797468e2c8SBruno Larsen (billionai) handler = table[opc1]; 87807468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 87817468e2c8SBruno Larsen (billionai) /* opc2 is 5 bits long */ 87827468e2c8SBruno Larsen (billionai) for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 87837468e2c8SBruno Larsen (billionai) table = env->opcodes; 87847468e2c8SBruno Larsen (billionai) handler = env->opcodes[opc1]; 87857468e2c8SBruno Larsen (billionai) table = ind_table(handler); 87867468e2c8SBruno Larsen (billionai) handler = table[opc2]; 87877468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 87887468e2c8SBruno Larsen (billionai) table = ind_table(handler); 87897468e2c8SBruno Larsen (billionai) /* opc3 is 5 bits long */ 87907468e2c8SBruno Larsen (billionai) for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 87917468e2c8SBruno Larsen (billionai) opc3++) { 87927468e2c8SBruno Larsen (billionai) handler = table[opc3]; 87937468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 87947468e2c8SBruno Larsen (billionai) table = ind_table(handler); 87957468e2c8SBruno Larsen (billionai) /* opc4 is 5 bits long */ 87967468e2c8SBruno Larsen (billionai) for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 87977468e2c8SBruno Larsen (billionai) opc4++) { 87987468e2c8SBruno Larsen (billionai) handler = table[opc4]; 87997468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 88007468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x %02x -- " 88017468e2c8SBruno Larsen (billionai) "(%02d %04d %02d) : %s\n", 88027468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc4, 88037468e2c8SBruno Larsen (billionai) opc1, (opc3 << 5) | opc2, opc4, 88047468e2c8SBruno Larsen (billionai) handler->oname); 88057468e2c8SBruno Larsen (billionai) } 88067468e2c8SBruno Larsen (billionai) } 88077468e2c8SBruno Larsen (billionai) } else { 88087468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 88097468e2c8SBruno Larsen (billionai) /* Special hack to properly dump SPE insns */ 88107468e2c8SBruno Larsen (billionai) p = strchr(handler->oname, '_'); 88117468e2c8SBruno Larsen (billionai) if (p == NULL) { 88127468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x (%02d %04d) : " 88137468e2c8SBruno Larsen (billionai) "%s\n", 88147468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc1, 88157468e2c8SBruno Larsen (billionai) (opc3 << 5) | opc2, 88167468e2c8SBruno Larsen (billionai) handler->oname); 88177468e2c8SBruno Larsen (billionai) } else { 88187468e2c8SBruno Larsen (billionai) q = "speundef"; 88197468e2c8SBruno Larsen (billionai) if ((p - handler->oname) != strlen(q) 88207468e2c8SBruno Larsen (billionai) || (memcmp(handler->oname, q, strlen(q)) 88217468e2c8SBruno Larsen (billionai) != 0)) { 88227468e2c8SBruno Larsen (billionai) /* First instruction */ 88237468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x" 88247468e2c8SBruno Larsen (billionai) "(%02d %04d) : %.*s\n", 88257468e2c8SBruno Larsen (billionai) opc1, opc2 << 1, opc3, opc1, 88267468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1), 88277468e2c8SBruno Larsen (billionai) (int)(p - handler->oname), 88287468e2c8SBruno Larsen (billionai) handler->oname); 88297468e2c8SBruno Larsen (billionai) } 88307468e2c8SBruno Larsen (billionai) if (strcmp(p + 1, q) != 0) { 88317468e2c8SBruno Larsen (billionai) /* Second instruction */ 88327468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x " 88337468e2c8SBruno Larsen (billionai) "(%02d %04d) : %s\n", opc1, 88347468e2c8SBruno Larsen (billionai) (opc2 << 1) | 1, opc3, opc1, 88357468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1) | 1, 88367468e2c8SBruno Larsen (billionai) p + 1); 88377468e2c8SBruno Larsen (billionai) } 88387468e2c8SBruno Larsen (billionai) } 88397468e2c8SBruno Larsen (billionai) } 88407468e2c8SBruno Larsen (billionai) } 88417468e2c8SBruno Larsen (billionai) } 88427468e2c8SBruno Larsen (billionai) } else { 88437468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 88447468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 88457468e2c8SBruno Larsen (billionai) opc1, opc2, opc1, opc2, handler->oname); 88467468e2c8SBruno Larsen (billionai) } 88477468e2c8SBruno Larsen (billionai) } 88487468e2c8SBruno Larsen (billionai) } 88497468e2c8SBruno Larsen (billionai) } else { 88507468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 88517468e2c8SBruno Larsen (billionai) printf("INSN: %02x -- -- (%02d ----) : %s\n", 88527468e2c8SBruno Larsen (billionai) opc1, opc1, handler->oname); 88537468e2c8SBruno Larsen (billionai) } 88547468e2c8SBruno Larsen (billionai) } 88557468e2c8SBruno Larsen (billionai) } 88567468e2c8SBruno Larsen (billionai) } 88577468e2c8SBruno Larsen (billionai) #endif 88587468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 88597468e2c8SBruno Larsen (billionai) { 88607468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 88617468e2c8SBruno Larsen (billionai) 88627468e2c8SBruno Larsen (billionai) /* 88637468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 88647468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 88657468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 88667468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 88677468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 88687468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 88697468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 88707468e2c8SBruno Larsen (billionai) */ 88717468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 88727468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 88737468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 88747468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 88757468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 88767468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 88777468e2c8SBruno Larsen (billionai) } 88787468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 88797468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 88807468e2c8SBruno Larsen (billionai) return 0; 88817468e2c8SBruno Larsen (billionai) } 88827468e2c8SBruno Larsen (billionai) 88837468e2c8SBruno Larsen (billionai) 888411cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 8885fcf5ef2aSThomas Huth { 8886fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 8887fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 8888fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 8889fcf5ef2aSThomas Huth int op1, op2, op3; 8890fcf5ef2aSThomas Huth 8891fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 8892fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 8893fcf5ef2aSThomas Huth handler = t1[op1]; 8894fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 8895fcf5ef2aSThomas Huth t2 = ind_table(handler); 8896fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 8897fcf5ef2aSThomas Huth handler = t2[op2]; 8898fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 8899fcf5ef2aSThomas Huth t3 = ind_table(handler); 8900fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 8901fcf5ef2aSThomas Huth handler = t3[op3]; 8902efe843d8SDavid Gibson if (handler->count == 0) { 8903fcf5ef2aSThomas Huth continue; 8904efe843d8SDavid Gibson } 890511cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 8906fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 8907fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 8908fcf5ef2aSThomas Huth handler->oname, 8909fcf5ef2aSThomas Huth handler->count, handler->count); 8910fcf5ef2aSThomas Huth } 8911fcf5ef2aSThomas Huth } else { 8912efe843d8SDavid Gibson if (handler->count == 0) { 8913fcf5ef2aSThomas Huth continue; 8914efe843d8SDavid Gibson } 891511cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 8916fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 8917fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 8918fcf5ef2aSThomas Huth handler->count, handler->count); 8919fcf5ef2aSThomas Huth } 8920fcf5ef2aSThomas Huth } 8921fcf5ef2aSThomas Huth } else { 8922efe843d8SDavid Gibson if (handler->count == 0) { 8923fcf5ef2aSThomas Huth continue; 8924efe843d8SDavid Gibson } 892511cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 8926fcf5ef2aSThomas Huth " %" PRId64 "\n", 8927fcf5ef2aSThomas Huth op1, op1, handler->oname, 8928fcf5ef2aSThomas Huth handler->count, handler->count); 8929fcf5ef2aSThomas Huth } 8930fcf5ef2aSThomas Huth } 8931fcf5ef2aSThomas Huth #endif 8932fcf5ef2aSThomas Huth } 8933fcf5ef2aSThomas Huth 8934624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8935624cb07fSRichard Henderson { 8936624cb07fSRichard Henderson opc_handler_t **table, *handler; 8937624cb07fSRichard Henderson uint32_t inval; 8938624cb07fSRichard Henderson 8939624cb07fSRichard Henderson ctx->opcode = insn; 8940624cb07fSRichard Henderson 8941624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8942624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8943624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8944624cb07fSRichard Henderson 8945624cb07fSRichard Henderson table = cpu->opcodes; 8946624cb07fSRichard Henderson handler = table[opc1(insn)]; 8947624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8948624cb07fSRichard Henderson table = ind_table(handler); 8949624cb07fSRichard Henderson handler = table[opc2(insn)]; 8950624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8951624cb07fSRichard Henderson table = ind_table(handler); 8952624cb07fSRichard Henderson handler = table[opc3(insn)]; 8953624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8954624cb07fSRichard Henderson table = ind_table(handler); 8955624cb07fSRichard Henderson handler = table[opc4(insn)]; 8956624cb07fSRichard Henderson } 8957624cb07fSRichard Henderson } 8958624cb07fSRichard Henderson } 8959624cb07fSRichard Henderson 8960624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8961624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8962624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8963624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8964624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8965624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8966624cb07fSRichard Henderson insn, ctx->cia); 8967624cb07fSRichard Henderson return false; 8968624cb07fSRichard Henderson } 8969624cb07fSRichard Henderson 8970624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8971624cb07fSRichard Henderson && Rc(insn))) { 8972624cb07fSRichard Henderson inval = handler->inval2; 8973624cb07fSRichard Henderson } else { 8974624cb07fSRichard Henderson inval = handler->inval1; 8975624cb07fSRichard Henderson } 8976624cb07fSRichard Henderson 8977624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8978624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8979624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8980624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8981624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8982624cb07fSRichard Henderson insn, ctx->cia); 8983624cb07fSRichard Henderson return false; 8984624cb07fSRichard Henderson } 8985624cb07fSRichard Henderson 8986624cb07fSRichard Henderson handler->handler(ctx); 8987624cb07fSRichard Henderson return true; 8988624cb07fSRichard Henderson } 8989624cb07fSRichard Henderson 8990b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8991fcf5ef2aSThomas Huth { 8992b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 89939c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 89942df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8995b0c2d521SEmilio G. Cota int bound; 8996fcf5ef2aSThomas Huth 8997b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 89982df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8999d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 90002df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 90012df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 9002b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 9003b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 9004b0c2d521SEmilio G. Cota ctx->access_type = -1; 9005d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 90062df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 9007b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 90080e3bf489SRoman Kapl ctx->flags = env->flags; 9009fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 90102df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 9011b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 9012fcf5ef2aSThomas Huth #endif 9013e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 9014e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 9015d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 9016fcf5ef2aSThomas Huth 90172df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 90182df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 90192df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 90202df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 90212df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 9022f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 90232df4fe7aSRichard Henderson 9024b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 90252df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 90262df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 9027efe843d8SDavid Gibson } 90282df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 9029b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 9030efe843d8SDavid Gibson } 9031b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9032b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 9033fcf5ef2aSThomas Huth } 9034b0c2d521SEmilio G. Cota 9035b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 9036b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 9037fcf5ef2aSThomas Huth } 9038fcf5ef2aSThomas Huth 9039b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 9040b0c2d521SEmilio G. Cota { 9041b0c2d521SEmilio G. Cota } 9042fcf5ef2aSThomas Huth 9043b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 9044b0c2d521SEmilio G. Cota { 9045b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 9046b0c2d521SEmilio G. Cota } 9047b0c2d521SEmilio G. Cota 9048b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 9049b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 9050b0c2d521SEmilio G. Cota { 9051b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9052b0c2d521SEmilio G. Cota 90532736fc61SRichard Henderson gen_update_nip(ctx, ctx->base.pc_next); 9054b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9055efe843d8SDavid Gibson /* 9056efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 9057efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 9058efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 9059efe843d8SDavid Gibson * setting tb->size below does the right thing. 9060efe843d8SDavid Gibson */ 9061b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9062b0c2d521SEmilio G. Cota return true; 9063fcf5ef2aSThomas Huth } 9064fcf5ef2aSThomas Huth 9065b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 9066b0c2d521SEmilio G. Cota { 9067b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 906828876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 9069b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 9070624cb07fSRichard Henderson uint32_t insn; 9071624cb07fSRichard Henderson bool ok; 9072b0c2d521SEmilio G. Cota 9073fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 9074fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 9075b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 9076b0c2d521SEmilio G. Cota 90772c2bcb1bSRichard Henderson ctx->cia = ctx->base.pc_next; 9078624cb07fSRichard Henderson insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); 9079b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9080fcf5ef2aSThomas Huth 9081624cb07fSRichard Henderson ok = decode_legacy(cpu, ctx, insn); 9082624cb07fSRichard Henderson if (!ok) { 9083624cb07fSRichard Henderson gen_invalid(ctx); 9084fcf5ef2aSThomas Huth } 9085624cb07fSRichard Henderson 9086fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9087fcf5ef2aSThomas Huth handler->count++; 9088fcf5ef2aSThomas Huth #endif 90893d8a5b69SRichard Henderson 9090fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 9091b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 9092b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 90933d8a5b69SRichard Henderson ctx->base.is_jmp != DISAS_NORETURN)) { 9094e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 90950e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 9096fcf5ef2aSThomas Huth } 9097b0c2d521SEmilio G. Cota 9098fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 9099b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 9100b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 9101b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 9102fcf5ef2aSThomas Huth } 9103fcf5ef2aSThomas Huth } 9104b0c2d521SEmilio G. Cota 9105b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 9106b0c2d521SEmilio G. Cota { 9107b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9108a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 9109a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 9110b0c2d521SEmilio G. Cota 9111a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 9112a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 91133d8a5b69SRichard Henderson return; 91143d8a5b69SRichard Henderson } 91153d8a5b69SRichard Henderson 9116a9b5b3d0SRichard Henderson /* Honor single stepping. */ 9117b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9118a9b5b3d0SRichard Henderson switch (is_jmp) { 9119a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 9120a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 9121a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 9122a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9123a9b5b3d0SRichard Henderson break; 9124a9b5b3d0SRichard Henderson case DISAS_EXIT: 9125a9b5b3d0SRichard Henderson case DISAS_CHAIN: 9126a9b5b3d0SRichard Henderson break; 9127a9b5b3d0SRichard Henderson default: 9128a9b5b3d0SRichard Henderson g_assert_not_reached(); 9129fcf5ef2aSThomas Huth } 9130a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 9131a9b5b3d0SRichard Henderson return; 9132a9b5b3d0SRichard Henderson } 9133a9b5b3d0SRichard Henderson 9134a9b5b3d0SRichard Henderson switch (is_jmp) { 9135a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 9136a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 9137a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 9138a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9139a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 9140a9b5b3d0SRichard Henderson break; 9141a9b5b3d0SRichard Henderson } 9142a9b5b3d0SRichard Henderson /* fall through */ 9143a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 9144a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9145a9b5b3d0SRichard Henderson /* fall through */ 9146a9b5b3d0SRichard Henderson case DISAS_CHAIN: 9147a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 9148a9b5b3d0SRichard Henderson break; 9149a9b5b3d0SRichard Henderson 9150a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 9151a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 9152a9b5b3d0SRichard Henderson /* fall through */ 9153a9b5b3d0SRichard Henderson case DISAS_EXIT: 915407ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 9155a9b5b3d0SRichard Henderson break; 9156a9b5b3d0SRichard Henderson 9157a9b5b3d0SRichard Henderson default: 9158a9b5b3d0SRichard Henderson g_assert_not_reached(); 9159fcf5ef2aSThomas Huth } 9160fcf5ef2aSThomas Huth } 9161b0c2d521SEmilio G. Cota 9162b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 9163b0c2d521SEmilio G. Cota { 9164b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 9165b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 9166b0c2d521SEmilio G. Cota } 9167b0c2d521SEmilio G. Cota 9168b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 9169b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 9170b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 9171b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 9172b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 9173b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 9174b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 9175b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 9176b0c2d521SEmilio G. Cota }; 9177b0c2d521SEmilio G. Cota 91788b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 9179b0c2d521SEmilio G. Cota { 9180b0c2d521SEmilio G. Cota DisasContext ctx; 9181b0c2d521SEmilio G. Cota 91828b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 9183fcf5ef2aSThomas Huth } 9184fcf5ef2aSThomas Huth 9185fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 9186fcf5ef2aSThomas Huth target_ulong *data) 9187fcf5ef2aSThomas Huth { 9188fcf5ef2aSThomas Huth env->nip = data[0]; 9189fcf5ef2aSThomas Huth } 9190