1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 38a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 39fcf5ef2aSThomas Huth 403e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 413e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 44fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 47efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 1572c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 158fcf5ef2aSThomas Huth uint32_t opcode; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 1771db3632aSMatheus Ferst bool hr; 178f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 179f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 180fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 181fcf5ef2aSThomas Huth int singlestep_enabled; 1820e3bf489SRoman Kapl uint32_t flags; 183fcf5ef2aSThomas Huth uint64_t insns_flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags2; 185fcf5ef2aSThomas Huth }; 186fcf5ef2aSThomas Huth 187a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 188a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 189a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 190a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 191a9b5b3d0SRichard Henderson 192fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 193fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 194fcf5ef2aSThomas Huth { 195fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 196fcf5ef2aSThomas Huth return ctx->le_mode; 197fcf5ef2aSThomas Huth #else 198fcf5ef2aSThomas Huth return !ctx->le_mode; 199fcf5ef2aSThomas Huth #endif 200fcf5ef2aSThomas Huth } 201fcf5ef2aSThomas Huth 202fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 203fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 204fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 205fcf5ef2aSThomas Huth #else 206fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 207fcf5ef2aSThomas Huth #endif 208fcf5ef2aSThomas Huth 209fcf5ef2aSThomas Huth struct opc_handler_t { 210fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 211fcf5ef2aSThomas Huth uint32_t inval1; 212fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 213fcf5ef2aSThomas Huth uint32_t inval2; 214fcf5ef2aSThomas Huth /* instruction type */ 215fcf5ef2aSThomas Huth uint64_t type; 216fcf5ef2aSThomas Huth /* extended instruction type */ 217fcf5ef2aSThomas Huth uint64_t type2; 218fcf5ef2aSThomas Huth /* handler */ 219fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 220fcf5ef2aSThomas Huth }; 221fcf5ef2aSThomas Huth 2220e3bf489SRoman Kapl /* SPR load/store helpers */ 2230e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2240e3bf489SRoman Kapl { 2250e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2260e3bf489SRoman Kapl } 2270e3bf489SRoman Kapl 2280e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2290e3bf489SRoman Kapl { 2300e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2310e3bf489SRoman Kapl } 2320e3bf489SRoman Kapl 233fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 234fcf5ef2aSThomas Huth { 235fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 236fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 237fcf5ef2aSThomas Huth ctx->access_type = access_type; 238fcf5ef2aSThomas Huth } 239fcf5ef2aSThomas Huth } 240fcf5ef2aSThomas Huth 241fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 242fcf5ef2aSThomas Huth { 243fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 244fcf5ef2aSThomas Huth nip = (uint32_t)nip; 245fcf5ef2aSThomas Huth } 246fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 247fcf5ef2aSThomas Huth } 248fcf5ef2aSThomas Huth 249fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 250fcf5ef2aSThomas Huth { 251fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 252fcf5ef2aSThomas Huth 253efe843d8SDavid Gibson /* 254efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 255efe843d8SDavid Gibson * faulting instruction 256fcf5ef2aSThomas Huth */ 2572c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 258fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 259fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 260fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 261fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 262fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2633d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 264fcf5ef2aSThomas Huth } 265fcf5ef2aSThomas Huth 266fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 267fcf5ef2aSThomas Huth { 268fcf5ef2aSThomas Huth TCGv_i32 t0; 269fcf5ef2aSThomas Huth 270efe843d8SDavid Gibson /* 271efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 272efe843d8SDavid Gibson * faulting instruction 273fcf5ef2aSThomas Huth */ 2742c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 275fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 276fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 277fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2783d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 279fcf5ef2aSThomas Huth } 280fcf5ef2aSThomas Huth 281fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 282fcf5ef2aSThomas Huth target_ulong nip) 283fcf5ef2aSThomas Huth { 284fcf5ef2aSThomas Huth TCGv_i32 t0; 285fcf5ef2aSThomas Huth 286fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 287fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 288fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 289fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2903d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 291fcf5ef2aSThomas Huth } 292fcf5ef2aSThomas Huth 293f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 294f5b6daacSRichard Henderson { 295f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 296f5b6daacSRichard Henderson gen_io_start(); 297f5b6daacSRichard Henderson /* 298f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 299f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 300f5b6daacSRichard Henderson * decide if we need to return to the main loop. 301f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 302f5b6daacSRichard Henderson */ 303f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 304f5b6daacSRichard Henderson } 305f5b6daacSRichard Henderson } 306f5b6daacSRichard Henderson 307e150ac89SRoman Kapl /* 308e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 309e150ac89SRoman Kapl * SPR registers for this exception. 310e150ac89SRoman Kapl * 311e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 312e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3130e3bf489SRoman Kapl */ 314e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3150e3bf489SRoman Kapl { 3160e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3170e3bf489SRoman Kapl target_ulong dbsr = 0; 318e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3190e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 320e150ac89SRoman Kapl } else { 321e150ac89SRoman Kapl /* Must have been branch */ 3220e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3230e3bf489SRoman Kapl } 3240e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3250e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3260e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3270e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3280e3bf489SRoman Kapl tcg_temp_free(t0); 3290e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3300e3bf489SRoman Kapl } else { 331e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3320e3bf489SRoman Kapl } 3330e3bf489SRoman Kapl } 3340e3bf489SRoman Kapl 335fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 336fcf5ef2aSThomas Huth { 3379498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3383d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 339fcf5ef2aSThomas Huth } 340fcf5ef2aSThomas Huth 341fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 342fcf5ef2aSThomas Huth { 343fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 344fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 345fcf5ef2aSThomas Huth } 346fcf5ef2aSThomas Huth 347fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 348fcf5ef2aSThomas Huth { 349fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 350fcf5ef2aSThomas Huth } 351fcf5ef2aSThomas Huth 352fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 353fcf5ef2aSThomas Huth { 354fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 355fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 35837f219c8SBruno Larsen (billionai) /*****************************************************************************/ 35937f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 36037f219c8SBruno Larsen (billionai) 361a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36237f219c8SBruno Larsen (billionai) { 36337f219c8SBruno Larsen (billionai) #if 0 36437f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36537f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36637f219c8SBruno Larsen (billionai) #endif 36737f219c8SBruno Larsen (billionai) } 36837f219c8SBruno Larsen (billionai) 36937f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 37037f219c8SBruno Larsen (billionai) 37137f219c8SBruno Larsen (billionai) /* 37237f219c8SBruno Larsen (billionai) * Generic callbacks: 37337f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37437f219c8SBruno Larsen (billionai) */ 37537f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37637f219c8SBruno Larsen (billionai) { 37737f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 37937f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 38037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38137f219c8SBruno Larsen (billionai) #endif 38237f219c8SBruno Larsen (billionai) } 38337f219c8SBruno Larsen (billionai) 384a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38537f219c8SBruno Larsen (billionai) { 38637f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38737f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38837f219c8SBruno Larsen (billionai) } 38937f219c8SBruno Larsen (billionai) 39037f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39137f219c8SBruno Larsen (billionai) { 39237f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39437f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39637f219c8SBruno Larsen (billionai) #endif 39737f219c8SBruno Larsen (billionai) } 39837f219c8SBruno Larsen (billionai) 399a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 40037f219c8SBruno Larsen (billionai) { 40137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40237f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40337f219c8SBruno Larsen (billionai) } 40437f219c8SBruno Larsen (billionai) 40537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 406a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 40737f219c8SBruno Larsen (billionai) { 40837f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 40937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 41037f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 41137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 41237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 41337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41437f219c8SBruno Larsen (billionai) #else 41537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 41637f219c8SBruno Larsen (billionai) #endif 41737f219c8SBruno Larsen (billionai) } 41837f219c8SBruno Larsen (billionai) 419a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 42037f219c8SBruno Larsen (billionai) { 42137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 42337f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 42437f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 42537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 42637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 42937f219c8SBruno Larsen (billionai) } 43037f219c8SBruno Larsen (billionai) 431a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 43237f219c8SBruno Larsen (billionai) { 43337f219c8SBruno Larsen (billionai) } 43437f219c8SBruno Larsen (billionai) 43537f219c8SBruno Larsen (billionai) #endif 43637f219c8SBruno Larsen (billionai) 43737f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 43837f219c8SBruno Larsen (billionai) /* XER */ 439a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 44037f219c8SBruno Larsen (billionai) { 44137f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 44237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44337f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44437f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 44537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 44637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 44737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 44837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 44937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 45037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 45137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45237f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 45337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 45437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 45637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45737f219c8SBruno Larsen (billionai) } 45837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 46037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 46137f219c8SBruno Larsen (billionai) } 46237f219c8SBruno Larsen (billionai) 463a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 46437f219c8SBruno Larsen (billionai) { 46537f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 46637f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 46737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 46837f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 46937f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 47037f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 47137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 47237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 47337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 47437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 47537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 47637f219c8SBruno Larsen (billionai) } 47737f219c8SBruno Larsen (billionai) 47837f219c8SBruno Larsen (billionai) /* LR */ 479a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 48037f219c8SBruno Larsen (billionai) { 48137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 48237f219c8SBruno Larsen (billionai) } 48337f219c8SBruno Larsen (billionai) 484a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 48537f219c8SBruno Larsen (billionai) { 48637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 48737f219c8SBruno Larsen (billionai) } 48837f219c8SBruno Larsen (billionai) 48937f219c8SBruno Larsen (billionai) /* CFAR */ 49037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 491a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 49237f219c8SBruno Larsen (billionai) { 49337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 49437f219c8SBruno Larsen (billionai) } 49537f219c8SBruno Larsen (billionai) 496a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 49737f219c8SBruno Larsen (billionai) { 49837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 49937f219c8SBruno Larsen (billionai) } 50037f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 50137f219c8SBruno Larsen (billionai) 50237f219c8SBruno Larsen (billionai) /* CTR */ 503a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 50437f219c8SBruno Larsen (billionai) { 50537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 50637f219c8SBruno Larsen (billionai) } 50737f219c8SBruno Larsen (billionai) 508a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 50937f219c8SBruno Larsen (billionai) { 51037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 51137f219c8SBruno Larsen (billionai) } 51237f219c8SBruno Larsen (billionai) 51337f219c8SBruno Larsen (billionai) /* User read access to SPR */ 51437f219c8SBruno Larsen (billionai) /* USPRx */ 51537f219c8SBruno Larsen (billionai) /* UMMCRx */ 51637f219c8SBruno Larsen (billionai) /* UPMCx */ 51737f219c8SBruno Larsen (billionai) /* USIA */ 51837f219c8SBruno Larsen (billionai) /* UDECR */ 519a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 52037f219c8SBruno Larsen (billionai) { 52137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 52237f219c8SBruno Larsen (billionai) } 52337f219c8SBruno Larsen (billionai) 52437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 525a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 52637f219c8SBruno Larsen (billionai) { 52737f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 52837f219c8SBruno Larsen (billionai) } 52937f219c8SBruno Larsen (billionai) #endif 53037f219c8SBruno Larsen (billionai) 53137f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 53237f219c8SBruno Larsen (billionai) /* DECR */ 53337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 534a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 53537f219c8SBruno Larsen (billionai) { 536f5b6daacSRichard Henderson gen_icount_io_start(ctx); 53737f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 53837f219c8SBruno Larsen (billionai) } 53937f219c8SBruno Larsen (billionai) 540a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 54137f219c8SBruno Larsen (billionai) { 542f5b6daacSRichard Henderson gen_icount_io_start(ctx); 54337f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 54437f219c8SBruno Larsen (billionai) } 54537f219c8SBruno Larsen (billionai) #endif 54637f219c8SBruno Larsen (billionai) 54737f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 54837f219c8SBruno Larsen (billionai) /* Time base */ 549a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 55037f219c8SBruno Larsen (billionai) { 551f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55237f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 55337f219c8SBruno Larsen (billionai) } 55437f219c8SBruno Larsen (billionai) 555a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 55637f219c8SBruno Larsen (billionai) { 557f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55837f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 55937f219c8SBruno Larsen (billionai) } 56037f219c8SBruno Larsen (billionai) 561a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 56237f219c8SBruno Larsen (billionai) { 56337f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 56437f219c8SBruno Larsen (billionai) } 56537f219c8SBruno Larsen (billionai) 566a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 56737f219c8SBruno Larsen (billionai) { 56837f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 56937f219c8SBruno Larsen (billionai) } 57037f219c8SBruno Larsen (billionai) 57137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 572a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 57337f219c8SBruno Larsen (billionai) { 574f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57537f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 57637f219c8SBruno Larsen (billionai) } 57737f219c8SBruno Larsen (billionai) 578a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 57937f219c8SBruno Larsen (billionai) { 580f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58137f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 58237f219c8SBruno Larsen (billionai) } 58337f219c8SBruno Larsen (billionai) 584a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 58537f219c8SBruno Larsen (billionai) { 58637f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 58737f219c8SBruno Larsen (billionai) } 58837f219c8SBruno Larsen (billionai) 589a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 59037f219c8SBruno Larsen (billionai) { 59137f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 59237f219c8SBruno Larsen (billionai) } 59337f219c8SBruno Larsen (billionai) 59437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 595a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 59637f219c8SBruno Larsen (billionai) { 597f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59837f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 59937f219c8SBruno Larsen (billionai) } 60037f219c8SBruno Larsen (billionai) 601a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 60237f219c8SBruno Larsen (billionai) { 603f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60437f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 60537f219c8SBruno Larsen (billionai) } 60637f219c8SBruno Larsen (billionai) 60737f219c8SBruno Larsen (billionai) /* HDECR */ 608a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 60937f219c8SBruno Larsen (billionai) { 610f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61137f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 61237f219c8SBruno Larsen (billionai) } 61337f219c8SBruno Larsen (billionai) 614a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 61537f219c8SBruno Larsen (billionai) { 616f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61737f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 61837f219c8SBruno Larsen (billionai) } 61937f219c8SBruno Larsen (billionai) 620a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 62137f219c8SBruno Larsen (billionai) { 622f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62337f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 62437f219c8SBruno Larsen (billionai) } 62537f219c8SBruno Larsen (billionai) 626a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 62737f219c8SBruno Larsen (billionai) { 628f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62937f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 63037f219c8SBruno Larsen (billionai) } 63137f219c8SBruno Larsen (billionai) 632a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 63337f219c8SBruno Larsen (billionai) { 634f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63537f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 63637f219c8SBruno Larsen (billionai) } 63737f219c8SBruno Larsen (billionai) 63837f219c8SBruno Larsen (billionai) #endif 63937f219c8SBruno Larsen (billionai) #endif 64037f219c8SBruno Larsen (billionai) 64137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 64237f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 64337f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 644a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 64537f219c8SBruno Larsen (billionai) { 64637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 64737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 64837f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 64937f219c8SBruno Larsen (billionai) } 65037f219c8SBruno Larsen (billionai) 651a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 65237f219c8SBruno Larsen (billionai) { 65337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 65437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 65537f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 65637f219c8SBruno Larsen (billionai) } 65737f219c8SBruno Larsen (billionai) 658a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 65937f219c8SBruno Larsen (billionai) { 66037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 66137f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66337f219c8SBruno Larsen (billionai) } 66437f219c8SBruno Larsen (billionai) 665a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 66637f219c8SBruno Larsen (billionai) { 66737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 66837f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67037f219c8SBruno Larsen (billionai) } 67137f219c8SBruno Larsen (billionai) 672a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 67337f219c8SBruno Larsen (billionai) { 67437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 67537f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 67637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67737f219c8SBruno Larsen (billionai) } 67837f219c8SBruno Larsen (billionai) 679a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 68037f219c8SBruno Larsen (billionai) { 68137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 68237f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68437f219c8SBruno Larsen (billionai) } 68537f219c8SBruno Larsen (billionai) 68637f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 68737f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 688a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 68937f219c8SBruno Larsen (billionai) { 69037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69237f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 69337f219c8SBruno Larsen (billionai) } 69437f219c8SBruno Larsen (billionai) 695a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 69637f219c8SBruno Larsen (billionai) { 69737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69937f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 70037f219c8SBruno Larsen (billionai) } 70137f219c8SBruno Larsen (billionai) 702a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 70337f219c8SBruno Larsen (billionai) { 70437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 70537f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 70637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70737f219c8SBruno Larsen (billionai) } 70837f219c8SBruno Larsen (billionai) 709a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 71037f219c8SBruno Larsen (billionai) { 71137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 71237f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71437f219c8SBruno Larsen (billionai) } 71537f219c8SBruno Larsen (billionai) 716a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 71737f219c8SBruno Larsen (billionai) { 71837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 71937f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72137f219c8SBruno Larsen (billionai) } 72237f219c8SBruno Larsen (billionai) 723a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 72437f219c8SBruno Larsen (billionai) { 72537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 72637f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72837f219c8SBruno Larsen (billionai) } 72937f219c8SBruno Larsen (billionai) 73037f219c8SBruno Larsen (billionai) /* SDR1 */ 731a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 73237f219c8SBruno Larsen (billionai) { 73337f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 73437f219c8SBruno Larsen (billionai) } 73537f219c8SBruno Larsen (billionai) 73637f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 73737f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 73837f219c8SBruno Larsen (billionai) /* PIDR */ 739a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 74037f219c8SBruno Larsen (billionai) { 74137f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 74237f219c8SBruno Larsen (billionai) } 74337f219c8SBruno Larsen (billionai) 744a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 74737f219c8SBruno Larsen (billionai) } 74837f219c8SBruno Larsen (billionai) 749a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 75037f219c8SBruno Larsen (billionai) { 75137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 75237f219c8SBruno Larsen (billionai) } 75337f219c8SBruno Larsen (billionai) 754a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 75537f219c8SBruno Larsen (billionai) { 75637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 75737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 75837f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 75937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 76037f219c8SBruno Larsen (billionai) } 761a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 76237f219c8SBruno Larsen (billionai) { 76337f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 76437f219c8SBruno Larsen (billionai) } 76537f219c8SBruno Larsen (billionai) 766a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 76737f219c8SBruno Larsen (billionai) { 76837f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 76937f219c8SBruno Larsen (billionai) } 77037f219c8SBruno Larsen (billionai) 77137f219c8SBruno Larsen (billionai) /* DPDES */ 772a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 77337f219c8SBruno Larsen (billionai) { 77437f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 77537f219c8SBruno Larsen (billionai) } 77637f219c8SBruno Larsen (billionai) 777a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 77837f219c8SBruno Larsen (billionai) { 77937f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 78037f219c8SBruno Larsen (billionai) } 78137f219c8SBruno Larsen (billionai) #endif 78237f219c8SBruno Larsen (billionai) #endif 78337f219c8SBruno Larsen (billionai) 78437f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 78537f219c8SBruno Larsen (billionai) /* RTC */ 786a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 78737f219c8SBruno Larsen (billionai) { 78837f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 78937f219c8SBruno Larsen (billionai) } 79037f219c8SBruno Larsen (billionai) 791a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 79237f219c8SBruno Larsen (billionai) { 79337f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 79437f219c8SBruno Larsen (billionai) } 79537f219c8SBruno Larsen (billionai) 79637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 797a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 79837f219c8SBruno Larsen (billionai) { 79937f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 80037f219c8SBruno Larsen (billionai) } 80137f219c8SBruno Larsen (billionai) 802a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 80337f219c8SBruno Larsen (billionai) { 80437f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 80537f219c8SBruno Larsen (billionai) } 80637f219c8SBruno Larsen (billionai) 807a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 80837f219c8SBruno Larsen (billionai) { 80937f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 81037f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 811d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81237f219c8SBruno Larsen (billionai) } 81337f219c8SBruno Larsen (billionai) #endif 81437f219c8SBruno Larsen (billionai) 81537f219c8SBruno Larsen (billionai) /* Unified bats */ 81637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 817a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 81837f219c8SBruno Larsen (billionai) { 81937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 82037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 82137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 82237f219c8SBruno Larsen (billionai) } 82337f219c8SBruno Larsen (billionai) 824a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 82537f219c8SBruno Larsen (billionai) { 82637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 82737f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 82837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 82937f219c8SBruno Larsen (billionai) } 83037f219c8SBruno Larsen (billionai) 831a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 83237f219c8SBruno Larsen (billionai) { 83337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 83437f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 83537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 83637f219c8SBruno Larsen (billionai) } 83737f219c8SBruno Larsen (billionai) #endif 83837f219c8SBruno Larsen (billionai) 83937f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 84037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 841a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 84237f219c8SBruno Larsen (billionai) { 843f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84437f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84537f219c8SBruno Larsen (billionai) } 84637f219c8SBruno Larsen (billionai) 847a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84837f219c8SBruno Larsen (billionai) { 849f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85037f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 85137f219c8SBruno Larsen (billionai) } 85237f219c8SBruno Larsen (billionai) 853a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85437f219c8SBruno Larsen (billionai) { 855f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85737f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85837f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 859d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 86037f219c8SBruno Larsen (billionai) } 86137f219c8SBruno Larsen (billionai) 862a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86337f219c8SBruno Larsen (billionai) { 864f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86537f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86637f219c8SBruno Larsen (billionai) } 86737f219c8SBruno Larsen (billionai) 868a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 86937f219c8SBruno Larsen (billionai) { 870f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87137f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 87237f219c8SBruno Larsen (billionai) } 87337f219c8SBruno Larsen (billionai) 874a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 87537f219c8SBruno Larsen (billionai) { 876f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87737f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 87837f219c8SBruno Larsen (billionai) } 87937f219c8SBruno Larsen (billionai) #endif 88037f219c8SBruno Larsen (billionai) 88137f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 88237f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 88337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 884a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 88537f219c8SBruno Larsen (billionai) { 88637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 88737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 88837f219c8SBruno Larsen (billionai) } 88937f219c8SBruno Larsen (billionai) 890a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 89137f219c8SBruno Larsen (billionai) { 89237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 89337f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 89437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89537f219c8SBruno Larsen (billionai) } 89637f219c8SBruno Larsen (billionai) 897a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 89837f219c8SBruno Larsen (billionai) { 89937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90337f219c8SBruno Larsen (billionai) } 90437f219c8SBruno Larsen (billionai) #endif 90537f219c8SBruno Larsen (billionai) 90637f219c8SBruno Larsen (billionai) /* SPE specific registers */ 907a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 90837f219c8SBruno Larsen (billionai) { 90937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91037f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91137f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91337f219c8SBruno Larsen (billionai) } 91437f219c8SBruno Larsen (billionai) 915a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91637f219c8SBruno Larsen (billionai) { 91737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91837f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 91937f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92137f219c8SBruno Larsen (billionai) } 92237f219c8SBruno Larsen (billionai) 92337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92437f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 925a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92637f219c8SBruno Larsen (billionai) { 92737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 92937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 93037f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93337f219c8SBruno Larsen (billionai) } 93437f219c8SBruno Larsen (billionai) 935a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93637f219c8SBruno Larsen (billionai) { 93737f219c8SBruno Larsen (billionai) int sprn_offs; 93837f219c8SBruno Larsen (billionai) 93937f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 94037f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 94137f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94237f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94337f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94437f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94537f219c8SBruno Larsen (billionai) } else { 94637f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 94737f219c8SBruno Larsen (billionai) sprn, sprn); 94837f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 94937f219c8SBruno Larsen (billionai) return; 95037f219c8SBruno Larsen (billionai) } 95137f219c8SBruno Larsen (billionai) 95237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95537f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 95837f219c8SBruno Larsen (billionai) } 95937f219c8SBruno Larsen (billionai) #endif 96037f219c8SBruno Larsen (billionai) 96137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 96237f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 963a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96437f219c8SBruno Larsen (billionai) { 96537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96837f219c8SBruno Larsen (billionai) 96937f219c8SBruno Larsen (billionai) /* 97037f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 97137f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97237f219c8SBruno Larsen (billionai) */ 97337f219c8SBruno Larsen (billionai) 97437f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97537f219c8SBruno Larsen (billionai) if (ctx->pr) { 97637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97737f219c8SBruno Larsen (billionai) } else { 97837f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97937f219c8SBruno Larsen (billionai) } 98037f219c8SBruno Larsen (billionai) 98137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98337f219c8SBruno Larsen (billionai) 98437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98737f219c8SBruno Larsen (billionai) 98837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 99037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 99137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 99237f219c8SBruno Larsen (billionai) 99337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 99437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 99537f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 99637f219c8SBruno Larsen (billionai) } 99737f219c8SBruno Larsen (billionai) 998a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 99937f219c8SBruno Larsen (billionai) { 100037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100337f219c8SBruno Larsen (billionai) 100437f219c8SBruno Larsen (billionai) /* 100537f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100737f219c8SBruno Larsen (billionai) */ 100837f219c8SBruno Larsen (billionai) 100937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 101037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101137f219c8SBruno Larsen (billionai) 101237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101437f219c8SBruno Larsen (billionai) 101537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101837f219c8SBruno Larsen (billionai) 101937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 102037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 102237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 102337f219c8SBruno Larsen (billionai) 102437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 102637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 102737f219c8SBruno Larsen (billionai) } 102837f219c8SBruno Larsen (billionai) 1029a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 103037f219c8SBruno Larsen (billionai) { 103137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103437f219c8SBruno Larsen (billionai) 103537f219c8SBruno Larsen (billionai) /* 103637f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 103737f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 103837f219c8SBruno Larsen (billionai) */ 103937f219c8SBruno Larsen (billionai) 104037f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104237f219c8SBruno Larsen (billionai) 104337f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 104537f219c8SBruno Larsen (billionai) 104637f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 104737f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 104837f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 104937f219c8SBruno Larsen (billionai) 105037f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 105337f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 105437f219c8SBruno Larsen (billionai) 105537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105637f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 105737f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 105837f219c8SBruno Larsen (billionai) } 105937f219c8SBruno Larsen (billionai) #endif 106037f219c8SBruno Larsen (billionai) #endif 106137f219c8SBruno Larsen (billionai) 106237f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1063a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 106437f219c8SBruno Larsen (billionai) { 106537f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 106637f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 106737f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 106837f219c8SBruno Larsen (billionai) } 106937f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 107037f219c8SBruno Larsen (billionai) 107137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1072a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 107337f219c8SBruno Larsen (billionai) { 107437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107537f219c8SBruno Larsen (billionai) 107637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 107737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107937f219c8SBruno Larsen (billionai) } 108037f219c8SBruno Larsen (billionai) 1081a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 108237f219c8SBruno Larsen (billionai) { 108337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108437f219c8SBruno Larsen (billionai) 108537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 108637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108837f219c8SBruno Larsen (billionai) } 108937f219c8SBruno Larsen (billionai) 1090a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 109137f219c8SBruno Larsen (billionai) { 109237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109337f219c8SBruno Larsen (billionai) 109437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 109537f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 109637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109837f219c8SBruno Larsen (billionai) } 109937f219c8SBruno Larsen (billionai) 1100a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 110137f219c8SBruno Larsen (billionai) { 110237f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 110337f219c8SBruno Larsen (billionai) } 110437f219c8SBruno Larsen (billionai) 1105a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 110637f219c8SBruno Larsen (billionai) { 110737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 110837f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 110937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 111037f219c8SBruno Larsen (billionai) } 1111a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 111237f219c8SBruno Larsen (billionai) { 111337f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 111437f219c8SBruno Larsen (billionai) } 1115a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 111637f219c8SBruno Larsen (billionai) { 111737f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 111837f219c8SBruno Larsen (billionai) } 111937f219c8SBruno Larsen (billionai) 112037f219c8SBruno Larsen (billionai) #endif 112137f219c8SBruno Larsen (billionai) 112237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1123a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 112437f219c8SBruno Larsen (billionai) { 112537f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 112637f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 112737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 112837f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 112937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 113037f219c8SBruno Larsen (billionai) tcg_temp_free(val); 113137f219c8SBruno Larsen (billionai) } 113237f219c8SBruno Larsen (billionai) 1133a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 113437f219c8SBruno Larsen (billionai) { 113537f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 113637f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 113737f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 113837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 113937f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 114037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 114137f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 114237f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 114337f219c8SBruno Larsen (billionai) } 114437f219c8SBruno Larsen (billionai) 114537f219c8SBruno Larsen (billionai) #endif 114637f219c8SBruno Larsen (billionai) 114737f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 114837f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 114937f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 115037f219c8SBruno Larsen (billionai) { 115137f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 115237f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 115337f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 115437f219c8SBruno Larsen (billionai) 115537f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 115637f219c8SBruno Larsen (billionai) 115737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 115837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 115937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 116037f219c8SBruno Larsen (billionai) } 116137f219c8SBruno Larsen (billionai) 116237f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 116337f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116437f219c8SBruno Larsen (billionai) { 116537f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 116637f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 116737f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116837f219c8SBruno Larsen (billionai) 116937f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 117037f219c8SBruno Larsen (billionai) 117137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 117437f219c8SBruno Larsen (billionai) } 117537f219c8SBruno Larsen (billionai) 1176a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 117737f219c8SBruno Larsen (billionai) { 117837f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 117937f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 118037f219c8SBruno Larsen (billionai) 118137f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118237f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 118337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 118437f219c8SBruno Larsen (billionai) 118537f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 118637f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 118737f219c8SBruno Larsen (billionai) } 118837f219c8SBruno Larsen (billionai) 1189a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 119037f219c8SBruno Larsen (billionai) { 119137f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119237f219c8SBruno Larsen (billionai) 119337f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119437f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 119537f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 119637f219c8SBruno Larsen (billionai) 119737f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 119837f219c8SBruno Larsen (billionai) } 119937f219c8SBruno Larsen (billionai) 120037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1201a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 120237f219c8SBruno Larsen (billionai) { 120337f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 120437f219c8SBruno Larsen (billionai) 120537f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 120637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 120737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 120837f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 120937f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 121037f219c8SBruno Larsen (billionai) } 121137f219c8SBruno Larsen (billionai) 1212a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 121337f219c8SBruno Larsen (billionai) { 121437f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 121537f219c8SBruno Larsen (billionai) } 121637f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 121737f219c8SBruno Larsen (billionai) 1218a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 121937f219c8SBruno Larsen (billionai) { 122037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122137f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122237f219c8SBruno Larsen (billionai) } 122337f219c8SBruno Larsen (billionai) 1224a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 122537f219c8SBruno Larsen (billionai) { 122637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 122837f219c8SBruno Larsen (billionai) } 122937f219c8SBruno Larsen (billionai) 1230a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 123137f219c8SBruno Larsen (billionai) { 123237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123437f219c8SBruno Larsen (billionai) } 123537f219c8SBruno Larsen (billionai) 1236a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 123737f219c8SBruno Larsen (billionai) { 123837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124037f219c8SBruno Larsen (billionai) } 124137f219c8SBruno Larsen (billionai) 1242a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 124337f219c8SBruno Larsen (billionai) { 124437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124537f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124637f219c8SBruno Larsen (billionai) } 124737f219c8SBruno Larsen (billionai) 1248a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 124937f219c8SBruno Larsen (billionai) { 125037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125137f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125237f219c8SBruno Larsen (billionai) } 125337f219c8SBruno Larsen (billionai) 1254a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 125537f219c8SBruno Larsen (billionai) { 125637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125837f219c8SBruno Larsen (billionai) } 125937f219c8SBruno Larsen (billionai) 1260a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 126137f219c8SBruno Larsen (billionai) { 126237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126437f219c8SBruno Larsen (billionai) } 126537f219c8SBruno Larsen (billionai) 1266a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 126737f219c8SBruno Larsen (billionai) { 126837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126937f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 127037f219c8SBruno Larsen (billionai) } 127137f219c8SBruno Larsen (billionai) 1272a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 127337f219c8SBruno Larsen (billionai) { 127437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127537f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 127637f219c8SBruno Larsen (billionai) } 127737f219c8SBruno Larsen (billionai) #endif 127837f219c8SBruno Larsen (billionai) 1279fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1280fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1281fcf5ef2aSThomas Huth 1282fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1283fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1284fcf5ef2aSThomas Huth 1285fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1286fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1287fcf5ef2aSThomas Huth 1288fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1289fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1290fcf5ef2aSThomas Huth 1291fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1292fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1293fcf5ef2aSThomas Huth 1294fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1295fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1296fcf5ef2aSThomas Huth 1297fcf5ef2aSThomas Huth typedef struct opcode_t { 1298fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1299fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1300fcf5ef2aSThomas Huth unsigned char pad[4]; 1301fcf5ef2aSThomas Huth #endif 1302fcf5ef2aSThomas Huth opc_handler_t handler; 1303fcf5ef2aSThomas Huth const char *oname; 1304fcf5ef2aSThomas Huth } opcode_t; 1305fcf5ef2aSThomas Huth 1306fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1307fcf5ef2aSThomas Huth #define GEN_PRIV \ 1308fcf5ef2aSThomas Huth do { \ 1309fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1310fcf5ef2aSThomas Huth } while (0) 1311fcf5ef2aSThomas Huth 1312fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1313fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1314fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1315fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1316fcf5ef2aSThomas Huth #else 1317fcf5ef2aSThomas Huth #define CHK_HV \ 1318fcf5ef2aSThomas Huth do { \ 1319fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1320fcf5ef2aSThomas Huth GEN_PRIV; \ 1321fcf5ef2aSThomas Huth } \ 1322fcf5ef2aSThomas Huth } while (0) 1323fcf5ef2aSThomas Huth #define CHK_SV \ 1324fcf5ef2aSThomas Huth do { \ 1325fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1326fcf5ef2aSThomas Huth GEN_PRIV; \ 1327fcf5ef2aSThomas Huth } \ 1328fcf5ef2aSThomas Huth } while (0) 1329fcf5ef2aSThomas Huth #define CHK_HVRM \ 1330fcf5ef2aSThomas Huth do { \ 1331fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1332fcf5ef2aSThomas Huth GEN_PRIV; \ 1333fcf5ef2aSThomas Huth } \ 1334fcf5ef2aSThomas Huth } while (0) 1335fcf5ef2aSThomas Huth #endif 1336fcf5ef2aSThomas Huth 1337fcf5ef2aSThomas Huth #define CHK_NONE 1338fcf5ef2aSThomas Huth 1339fcf5ef2aSThomas Huth /*****************************************************************************/ 1340fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1341fcf5ef2aSThomas Huth 1342fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1343fcf5ef2aSThomas Huth { \ 1344fcf5ef2aSThomas Huth .opc1 = op1, \ 1345fcf5ef2aSThomas Huth .opc2 = op2, \ 1346fcf5ef2aSThomas Huth .opc3 = op3, \ 1347fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1348fcf5ef2aSThomas Huth .handler = { \ 1349fcf5ef2aSThomas Huth .inval1 = invl, \ 1350fcf5ef2aSThomas Huth .type = _typ, \ 1351fcf5ef2aSThomas Huth .type2 = _typ2, \ 1352fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1353fcf5ef2aSThomas Huth }, \ 1354fcf5ef2aSThomas Huth .oname = stringify(name), \ 1355fcf5ef2aSThomas Huth } 1356fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1357fcf5ef2aSThomas Huth { \ 1358fcf5ef2aSThomas Huth .opc1 = op1, \ 1359fcf5ef2aSThomas Huth .opc2 = op2, \ 1360fcf5ef2aSThomas Huth .opc3 = op3, \ 1361fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1362fcf5ef2aSThomas Huth .handler = { \ 1363fcf5ef2aSThomas Huth .inval1 = invl1, \ 1364fcf5ef2aSThomas Huth .inval2 = invl2, \ 1365fcf5ef2aSThomas Huth .type = _typ, \ 1366fcf5ef2aSThomas Huth .type2 = _typ2, \ 1367fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1368fcf5ef2aSThomas Huth }, \ 1369fcf5ef2aSThomas Huth .oname = stringify(name), \ 1370fcf5ef2aSThomas Huth } 1371fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1372fcf5ef2aSThomas Huth { \ 1373fcf5ef2aSThomas Huth .opc1 = op1, \ 1374fcf5ef2aSThomas Huth .opc2 = op2, \ 1375fcf5ef2aSThomas Huth .opc3 = op3, \ 1376fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1377fcf5ef2aSThomas Huth .handler = { \ 1378fcf5ef2aSThomas Huth .inval1 = invl, \ 1379fcf5ef2aSThomas Huth .type = _typ, \ 1380fcf5ef2aSThomas Huth .type2 = _typ2, \ 1381fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1382fcf5ef2aSThomas Huth }, \ 1383fcf5ef2aSThomas Huth .oname = onam, \ 1384fcf5ef2aSThomas Huth } 1385fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1386fcf5ef2aSThomas Huth { \ 1387fcf5ef2aSThomas Huth .opc1 = op1, \ 1388fcf5ef2aSThomas Huth .opc2 = op2, \ 1389fcf5ef2aSThomas Huth .opc3 = op3, \ 1390fcf5ef2aSThomas Huth .opc4 = op4, \ 1391fcf5ef2aSThomas Huth .handler = { \ 1392fcf5ef2aSThomas Huth .inval1 = invl, \ 1393fcf5ef2aSThomas Huth .type = _typ, \ 1394fcf5ef2aSThomas Huth .type2 = _typ2, \ 1395fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1396fcf5ef2aSThomas Huth }, \ 1397fcf5ef2aSThomas Huth .oname = stringify(name), \ 1398fcf5ef2aSThomas Huth } 1399fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1400fcf5ef2aSThomas Huth { \ 1401fcf5ef2aSThomas Huth .opc1 = op1, \ 1402fcf5ef2aSThomas Huth .opc2 = op2, \ 1403fcf5ef2aSThomas Huth .opc3 = op3, \ 1404fcf5ef2aSThomas Huth .opc4 = op4, \ 1405fcf5ef2aSThomas Huth .handler = { \ 1406fcf5ef2aSThomas Huth .inval1 = invl, \ 1407fcf5ef2aSThomas Huth .type = _typ, \ 1408fcf5ef2aSThomas Huth .type2 = _typ2, \ 1409fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1410fcf5ef2aSThomas Huth }, \ 1411fcf5ef2aSThomas Huth .oname = onam, \ 1412fcf5ef2aSThomas Huth } 1413fcf5ef2aSThomas Huth 1414fcf5ef2aSThomas Huth /* Invalid instruction */ 1415fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1416fcf5ef2aSThomas Huth { 1417fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1418fcf5ef2aSThomas Huth } 1419fcf5ef2aSThomas Huth 1420fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1421fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1422fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1423fcf5ef2aSThomas Huth .type = PPC_NONE, 1424fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1425fcf5ef2aSThomas Huth .handler = gen_invalid, 1426fcf5ef2aSThomas Huth }; 1427fcf5ef2aSThomas Huth 1428fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1429fcf5ef2aSThomas Huth 1430fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1431fcf5ef2aSThomas Huth { 1432fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1433b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1434b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1435fcf5ef2aSThomas Huth 1436b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1437b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1438efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1439efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1440b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1441efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1442efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1443b62b3686Spbonzini@redhat.com 1444b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1445fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1446b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1447fcf5ef2aSThomas Huth 1448fcf5ef2aSThomas Huth tcg_temp_free(t0); 1449b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1450b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1451fcf5ef2aSThomas Huth } 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1454fcf5ef2aSThomas Huth { 1455fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1456fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1457fcf5ef2aSThomas Huth tcg_temp_free(t0); 1458fcf5ef2aSThomas Huth } 1459fcf5ef2aSThomas Huth 1460fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1461fcf5ef2aSThomas Huth { 1462fcf5ef2aSThomas Huth TCGv t0, t1; 1463fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1464fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1465fcf5ef2aSThomas Huth if (s) { 1466fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1467fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1468fcf5ef2aSThomas Huth } else { 1469fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1470fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1471fcf5ef2aSThomas Huth } 1472fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1473fcf5ef2aSThomas Huth tcg_temp_free(t1); 1474fcf5ef2aSThomas Huth tcg_temp_free(t0); 1475fcf5ef2aSThomas Huth } 1476fcf5ef2aSThomas Huth 1477fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1478fcf5ef2aSThomas Huth { 1479fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1480fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1481fcf5ef2aSThomas Huth tcg_temp_free(t0); 1482fcf5ef2aSThomas Huth } 1483fcf5ef2aSThomas Huth 1484fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1485fcf5ef2aSThomas Huth { 1486fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1487fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1488fcf5ef2aSThomas Huth } else { 1489fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1490fcf5ef2aSThomas Huth } 1491fcf5ef2aSThomas Huth } 1492fcf5ef2aSThomas Huth 1493fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1494fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1495fcf5ef2aSThomas Huth { 1496fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1497fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1498fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1499fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1500fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1501fcf5ef2aSThomas Huth 1502fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1503fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1504fcf5ef2aSThomas Huth 1505fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1506fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1507fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1508fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1509fcf5ef2aSThomas Huth 1510fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1511fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1512fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1513fcf5ef2aSThomas Huth 1514fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1515fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1516fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1517fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1518fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1519fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1520fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1521fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1522fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1523fcf5ef2aSThomas Huth } 1524efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1525fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1526fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1527fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1528fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1529fcf5ef2aSThomas Huth } 1530fcf5ef2aSThomas Huth 1531fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1532fcf5ef2aSThomas Huth /* cmpeqb */ 1533fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1534fcf5ef2aSThomas Huth { 1535fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1536fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1537fcf5ef2aSThomas Huth } 1538fcf5ef2aSThomas Huth #endif 1539fcf5ef2aSThomas Huth 1540fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1541fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1542fcf5ef2aSThomas Huth { 1543fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1544fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1545fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1546fcf5ef2aSThomas Huth TCGv zr; 1547fcf5ef2aSThomas Huth 1548fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1549fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1550fcf5ef2aSThomas Huth 1551fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1552fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1553fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1554fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1555fcf5ef2aSThomas Huth tcg_temp_free(zr); 1556fcf5ef2aSThomas Huth tcg_temp_free(t0); 1557fcf5ef2aSThomas Huth } 1558fcf5ef2aSThomas Huth 1559fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1560fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1561fcf5ef2aSThomas Huth { 1562fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1563fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1564fcf5ef2aSThomas Huth } 1565fcf5ef2aSThomas Huth 1566fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1567fcf5ef2aSThomas Huth 1568fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1569fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1570fcf5ef2aSThomas Huth { 1571fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1572fcf5ef2aSThomas Huth 1573fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1574fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1575fcf5ef2aSThomas Huth if (sub) { 1576fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1577fcf5ef2aSThomas Huth } else { 1578fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1579fcf5ef2aSThomas Huth } 1580fcf5ef2aSThomas Huth tcg_temp_free(t0); 1581fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1582dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1583dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1584dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1585fcf5ef2aSThomas Huth } 1586dc0ad844SNikunj A Dadhania } else { 1587dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1588dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1589dc0ad844SNikunj A Dadhania } 159038a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1591dc0ad844SNikunj A Dadhania } 1592fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1593fcf5ef2aSThomas Huth } 1594fcf5ef2aSThomas Huth 15956b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15966b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15974c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15986b10d008SNikunj A Dadhania { 15996b10d008SNikunj A Dadhania TCGv t0; 16006b10d008SNikunj A Dadhania 16016b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16026b10d008SNikunj A Dadhania return; 16036b10d008SNikunj A Dadhania } 16046b10d008SNikunj A Dadhania 16056b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 160633903d0aSNikunj A Dadhania if (sub) { 160733903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 160833903d0aSNikunj A Dadhania } else { 16096b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 161033903d0aSNikunj A Dadhania } 16116b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16124c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16136b10d008SNikunj A Dadhania tcg_temp_free(t0); 16146b10d008SNikunj A Dadhania } 16156b10d008SNikunj A Dadhania 1616fcf5ef2aSThomas Huth /* Common add function */ 1617fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16184c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16194c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1620fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1621fcf5ef2aSThomas Huth { 1622fcf5ef2aSThomas Huth TCGv t0 = ret; 1623fcf5ef2aSThomas Huth 1624fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1625fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1626fcf5ef2aSThomas Huth } 1627fcf5ef2aSThomas Huth 1628fcf5ef2aSThomas Huth if (compute_ca) { 1629fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1630efe843d8SDavid Gibson /* 1631efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1632efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1633efe843d8SDavid Gibson * produce the carry into bit 32. 1634efe843d8SDavid Gibson */ 1635fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1636fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1637fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1638fcf5ef2aSThomas Huth if (add_ca) { 16394c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1640fcf5ef2aSThomas Huth } 16414c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1642fcf5ef2aSThomas Huth tcg_temp_free(t1); 16434c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16446b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16454c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16466b10d008SNikunj A Dadhania } 1647fcf5ef2aSThomas Huth } else { 1648fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1649fcf5ef2aSThomas Huth if (add_ca) { 16504c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16514c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1652fcf5ef2aSThomas Huth } else { 16534c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1654fcf5ef2aSThomas Huth } 16554c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1656fcf5ef2aSThomas Huth tcg_temp_free(zero); 1657fcf5ef2aSThomas Huth } 1658fcf5ef2aSThomas Huth } else { 1659fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1660fcf5ef2aSThomas Huth if (add_ca) { 16614c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1662fcf5ef2aSThomas Huth } 1663fcf5ef2aSThomas Huth } 1664fcf5ef2aSThomas Huth 1665fcf5ef2aSThomas Huth if (compute_ov) { 1666fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1667fcf5ef2aSThomas Huth } 1668fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1669fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth 167211f4e8f8SRichard Henderson if (t0 != ret) { 1673fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1674fcf5ef2aSThomas Huth tcg_temp_free(t0); 1675fcf5ef2aSThomas Huth } 1676fcf5ef2aSThomas Huth } 1677fcf5ef2aSThomas Huth /* Add functions with two operands */ 16784c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1679fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1680fcf5ef2aSThomas Huth { \ 1681fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1682fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16834c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1684fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1685fcf5ef2aSThomas Huth } 1686fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16874c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1688fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1689fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1690fcf5ef2aSThomas Huth { \ 1691fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1692fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1693fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16944c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1695fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1696fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1697fcf5ef2aSThomas Huth } 1698fcf5ef2aSThomas Huth 1699fcf5ef2aSThomas Huth /* add add. addo addo. */ 17004c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17014c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1702fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17034c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17044c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1705fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17064c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17074c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1708fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17094c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17104c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17114c5920afSSuraj Jitindar Singh /* addex */ 17124c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1713fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17144c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17154c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1716fcf5ef2aSThomas Huth /* addic addic.*/ 1717fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1718fcf5ef2aSThomas Huth { 1719fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1720fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17214c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1722fcf5ef2aSThomas Huth tcg_temp_free(c); 1723fcf5ef2aSThomas Huth } 1724fcf5ef2aSThomas Huth 1725fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1726fcf5ef2aSThomas Huth { 1727fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1728fcf5ef2aSThomas Huth } 1729fcf5ef2aSThomas Huth 1730fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1731fcf5ef2aSThomas Huth { 1732fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1733fcf5ef2aSThomas Huth } 1734fcf5ef2aSThomas Huth 1735fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1736fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1737fcf5ef2aSThomas Huth { 1738fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1739fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1740fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1741fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1742fcf5ef2aSThomas Huth 1743fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1744fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1745fcf5ef2aSThomas Huth if (sign) { 1746fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1747fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1748fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1749fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1750fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1751fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1752fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1753fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1754fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1755fcf5ef2aSThomas Huth } else { 1756fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1757fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1758fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1759fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1760fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1761fcf5ef2aSThomas Huth } 1762fcf5ef2aSThomas Huth if (compute_ov) { 1763fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1764c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1765c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1766c44027ffSNikunj A Dadhania } 1767fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1768fcf5ef2aSThomas Huth } 1769fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1770fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1771fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1772fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1773fcf5ef2aSThomas Huth 1774efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1775fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1776fcf5ef2aSThomas Huth } 1777efe843d8SDavid Gibson } 1778fcf5ef2aSThomas Huth /* Div functions */ 1779fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1780fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1781fcf5ef2aSThomas Huth { \ 1782fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1783fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1784fcf5ef2aSThomas Huth sign, compute_ov); \ 1785fcf5ef2aSThomas Huth } 1786fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1787fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1788fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1789fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1790fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1791fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1792fcf5ef2aSThomas Huth 1793fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1794fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1795fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1796fcf5ef2aSThomas Huth { \ 1797fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1798fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1799fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1800fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1801fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1802fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1803fcf5ef2aSThomas Huth } \ 1804fcf5ef2aSThomas Huth } 1805fcf5ef2aSThomas Huth 1806fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1807fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1808fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1809fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1810fcf5ef2aSThomas Huth 1811fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1812fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1813fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1814fcf5ef2aSThomas Huth { 1815fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1816fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1817fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1818fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1819fcf5ef2aSThomas Huth 1820fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1821fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1822fcf5ef2aSThomas Huth if (sign) { 1823fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1824fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1825fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1826fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1827fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1828fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1829fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1830fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1831fcf5ef2aSThomas Huth } else { 1832fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1833fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1834fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1835fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1836fcf5ef2aSThomas Huth } 1837fcf5ef2aSThomas Huth if (compute_ov) { 1838fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1839c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1840c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1841c44027ffSNikunj A Dadhania } 1842fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1843fcf5ef2aSThomas Huth } 1844fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1845fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1846fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1847fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1848fcf5ef2aSThomas Huth 1849efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1850fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1851fcf5ef2aSThomas Huth } 1852efe843d8SDavid Gibson } 1853fcf5ef2aSThomas Huth 1854fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1855fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1856fcf5ef2aSThomas Huth { \ 1857fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1858fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1859fcf5ef2aSThomas Huth sign, compute_ov); \ 1860fcf5ef2aSThomas Huth } 1861c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1862fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1863fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1864c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1865fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1866fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1867fcf5ef2aSThomas Huth 1868fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1869fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1870fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1871fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1872fcf5ef2aSThomas Huth #endif 1873fcf5ef2aSThomas Huth 1874fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1875fcf5ef2aSThomas Huth TCGv arg2, int sign) 1876fcf5ef2aSThomas Huth { 1877fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1878fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1879fcf5ef2aSThomas Huth 1880fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1881fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1882fcf5ef2aSThomas Huth if (sign) { 1883fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1884fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1885fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1886fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1887fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1888fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1889fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1890fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1891fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1892fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1893fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1894fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1895fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1896fcf5ef2aSThomas Huth } else { 1897fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1898fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1899fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1900fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1901fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1902fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1903fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1904fcf5ef2aSThomas Huth } 1905fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1906fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1907fcf5ef2aSThomas Huth } 1908fcf5ef2aSThomas Huth 1909fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1910fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1911fcf5ef2aSThomas Huth { \ 1912fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1913fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1914fcf5ef2aSThomas Huth sign); \ 1915fcf5ef2aSThomas Huth } 1916fcf5ef2aSThomas Huth 1917fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1918fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1919fcf5ef2aSThomas Huth 1920fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1921fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1922fcf5ef2aSThomas Huth TCGv arg2, int sign) 1923fcf5ef2aSThomas Huth { 1924fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1925fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1926fcf5ef2aSThomas Huth 1927fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1928fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1929fcf5ef2aSThomas Huth if (sign) { 1930fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1931fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1932fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1933fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1934fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1935fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1936fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1937fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1938fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1939fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1940fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1941fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1942fcf5ef2aSThomas Huth } else { 1943fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1944fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1945fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1946fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1947fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1948fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1949fcf5ef2aSThomas Huth } 1950fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1951fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1952fcf5ef2aSThomas Huth } 1953fcf5ef2aSThomas Huth 1954fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1955fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1956fcf5ef2aSThomas Huth { \ 1957fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1958fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1959fcf5ef2aSThomas Huth sign); \ 1960fcf5ef2aSThomas Huth } 1961fcf5ef2aSThomas Huth 1962fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1963fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1964fcf5ef2aSThomas Huth #endif 1965fcf5ef2aSThomas Huth 1966fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1967fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1968fcf5ef2aSThomas Huth { 1969fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1970fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1971fcf5ef2aSThomas Huth 1972fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1973fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1974fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1975fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1976fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1977fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1978efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1979fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1980fcf5ef2aSThomas Huth } 1981efe843d8SDavid Gibson } 1982fcf5ef2aSThomas Huth 1983fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1984fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1985fcf5ef2aSThomas Huth { 1986fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1987fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1988fcf5ef2aSThomas Huth 1989fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1990fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1991fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1992fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1993fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1994fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1995efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1996fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1997fcf5ef2aSThomas Huth } 1998efe843d8SDavid Gibson } 1999fcf5ef2aSThomas Huth 2000fcf5ef2aSThomas Huth /* mullw mullw. */ 2001fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2002fcf5ef2aSThomas Huth { 2003fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2004fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2005fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2006fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2007fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2008fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2009fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2010fcf5ef2aSThomas Huth tcg_temp_free(t0); 2011fcf5ef2aSThomas Huth tcg_temp_free(t1); 2012fcf5ef2aSThomas Huth #else 2013fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2014fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2015fcf5ef2aSThomas Huth #endif 2016efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2017fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2018fcf5ef2aSThomas Huth } 2019efe843d8SDavid Gibson } 2020fcf5ef2aSThomas Huth 2021fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2022fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2023fcf5ef2aSThomas Huth { 2024fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2025fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2026fcf5ef2aSThomas Huth 2027fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2028fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2029fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2030fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2031fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2032fcf5ef2aSThomas Huth #else 2033fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2034fcf5ef2aSThomas Huth #endif 2035fcf5ef2aSThomas Huth 2036fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2037fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2038fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 203961aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 204061aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 204161aa9a69SNikunj A Dadhania } 2042fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2043fcf5ef2aSThomas Huth 2044fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2045fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2046efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2047fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2048fcf5ef2aSThomas Huth } 2049efe843d8SDavid Gibson } 2050fcf5ef2aSThomas Huth 2051fcf5ef2aSThomas Huth /* mulli */ 2052fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2053fcf5ef2aSThomas Huth { 2054fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2055fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2056fcf5ef2aSThomas Huth } 2057fcf5ef2aSThomas Huth 2058fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2059fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2060fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2061fcf5ef2aSThomas Huth { 2062fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2063fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2064fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2065fcf5ef2aSThomas Huth tcg_temp_free(lo); 2066fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2067fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2068fcf5ef2aSThomas Huth } 2069fcf5ef2aSThomas Huth } 2070fcf5ef2aSThomas Huth 2071fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2072fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2073fcf5ef2aSThomas Huth { 2074fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2075fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2076fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2077fcf5ef2aSThomas Huth tcg_temp_free(lo); 2078fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2079fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2080fcf5ef2aSThomas Huth } 2081fcf5ef2aSThomas Huth } 2082fcf5ef2aSThomas Huth 2083fcf5ef2aSThomas Huth /* mulld mulld. */ 2084fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2085fcf5ef2aSThomas Huth { 2086fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2087fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2088efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2089fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2090fcf5ef2aSThomas Huth } 2091efe843d8SDavid Gibson } 2092fcf5ef2aSThomas Huth 2093fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2094fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2095fcf5ef2aSThomas Huth { 2096fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2097fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2098fcf5ef2aSThomas Huth 2099fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2100fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2101fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2102fcf5ef2aSThomas Huth 2103fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2104fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 210561aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 210661aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 210761aa9a69SNikunj A Dadhania } 2108fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2109fcf5ef2aSThomas Huth 2110fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2111fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2112fcf5ef2aSThomas Huth 2113fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2114fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2115fcf5ef2aSThomas Huth } 2116fcf5ef2aSThomas Huth } 2117fcf5ef2aSThomas Huth #endif 2118fcf5ef2aSThomas Huth 2119fcf5ef2aSThomas Huth /* Common subf function */ 2120fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2121fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2122fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2123fcf5ef2aSThomas Huth { 2124fcf5ef2aSThomas Huth TCGv t0 = ret; 2125fcf5ef2aSThomas Huth 2126fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2127fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2128fcf5ef2aSThomas Huth } 2129fcf5ef2aSThomas Huth 2130fcf5ef2aSThomas Huth if (compute_ca) { 2131fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2132fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2133efe843d8SDavid Gibson /* 2134efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2135efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2136efe843d8SDavid Gibson * produce the carry into bit 32. 2137efe843d8SDavid Gibson */ 2138fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2139fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2140fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2141fcf5ef2aSThomas Huth if (add_ca) { 2142fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2143fcf5ef2aSThomas Huth } else { 2144fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2145fcf5ef2aSThomas Huth } 2146fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2147fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2148fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2149fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2150fcf5ef2aSThomas Huth tcg_temp_free(t1); 2151e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 215233903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 215333903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 215433903d0aSNikunj A Dadhania } 2155fcf5ef2aSThomas Huth } else if (add_ca) { 2156fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2157fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2158fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2159fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2160fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21614c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2162fcf5ef2aSThomas Huth tcg_temp_free(zero); 2163fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2164fcf5ef2aSThomas Huth } else { 2165fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2166fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21674c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2168fcf5ef2aSThomas Huth } 2169fcf5ef2aSThomas Huth } else if (add_ca) { 2170efe843d8SDavid Gibson /* 2171efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2172efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2173efe843d8SDavid Gibson */ 2174fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2175fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2176fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2177fcf5ef2aSThomas Huth } else { 2178fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2179fcf5ef2aSThomas Huth } 2180fcf5ef2aSThomas Huth 2181fcf5ef2aSThomas Huth if (compute_ov) { 2182fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2183fcf5ef2aSThomas Huth } 2184fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2185fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2186fcf5ef2aSThomas Huth } 2187fcf5ef2aSThomas Huth 218811f4e8f8SRichard Henderson if (t0 != ret) { 2189fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2190fcf5ef2aSThomas Huth tcg_temp_free(t0); 2191fcf5ef2aSThomas Huth } 2192fcf5ef2aSThomas Huth } 2193fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2194fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2195fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2196fcf5ef2aSThomas Huth { \ 2197fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2198fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2199fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2200fcf5ef2aSThomas Huth } 2201fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2202fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2203fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2204fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2205fcf5ef2aSThomas Huth { \ 2206fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2207fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2208fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2209fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2210fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2211fcf5ef2aSThomas Huth } 2212fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2213fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2214fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2215fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2216fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2217fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2218fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2219fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2220fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2221fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2222fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2223fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2224fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2225fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2226fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2227fcf5ef2aSThomas Huth 2228fcf5ef2aSThomas Huth /* subfic */ 2229fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2230fcf5ef2aSThomas Huth { 2231fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2232fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2233fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2234fcf5ef2aSThomas Huth tcg_temp_free(c); 2235fcf5ef2aSThomas Huth } 2236fcf5ef2aSThomas Huth 2237fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2238fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2239fcf5ef2aSThomas Huth { 2240fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2241fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2242fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2243fcf5ef2aSThomas Huth tcg_temp_free(zero); 2244fcf5ef2aSThomas Huth } 2245fcf5ef2aSThomas Huth 2246fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2247fcf5ef2aSThomas Huth { 22481480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22491480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22501480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22511480d71cSNikunj A Dadhania } 2252fcf5ef2aSThomas Huth } 2253fcf5ef2aSThomas Huth 2254fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2255fcf5ef2aSThomas Huth { 2256fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2257fcf5ef2aSThomas Huth } 2258fcf5ef2aSThomas Huth 2259fcf5ef2aSThomas Huth /*** Integer logical ***/ 2260fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2261fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2262fcf5ef2aSThomas Huth { \ 2263fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2264fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2265fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2266fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2267fcf5ef2aSThomas Huth } 2268fcf5ef2aSThomas Huth 2269fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2270fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2271fcf5ef2aSThomas Huth { \ 2272fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2273fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2274fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2275fcf5ef2aSThomas Huth } 2276fcf5ef2aSThomas Huth 2277fcf5ef2aSThomas Huth /* and & and. */ 2278fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2279fcf5ef2aSThomas Huth /* andc & andc. */ 2280fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2281fcf5ef2aSThomas Huth 2282fcf5ef2aSThomas Huth /* andi. */ 2283fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2284fcf5ef2aSThomas Huth { 2285efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2286efe843d8SDavid Gibson UIMM(ctx->opcode)); 2287fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2288fcf5ef2aSThomas Huth } 2289fcf5ef2aSThomas Huth 2290fcf5ef2aSThomas Huth /* andis. */ 2291fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2292fcf5ef2aSThomas Huth { 2293efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2294efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2295fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2296fcf5ef2aSThomas Huth } 2297fcf5ef2aSThomas Huth 2298fcf5ef2aSThomas Huth /* cntlzw */ 2299fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2300fcf5ef2aSThomas Huth { 23019b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23029b8514e5SRichard Henderson 23039b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23049b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23059b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23069b8514e5SRichard Henderson tcg_temp_free_i32(t); 23079b8514e5SRichard Henderson 2308efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2309fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2310fcf5ef2aSThomas Huth } 2311efe843d8SDavid Gibson } 2312fcf5ef2aSThomas Huth 2313fcf5ef2aSThomas Huth /* cnttzw */ 2314fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2315fcf5ef2aSThomas Huth { 23169b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23179b8514e5SRichard Henderson 23189b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23199b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23209b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23219b8514e5SRichard Henderson tcg_temp_free_i32(t); 23229b8514e5SRichard Henderson 2323fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2324fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2325fcf5ef2aSThomas Huth } 2326fcf5ef2aSThomas Huth } 2327fcf5ef2aSThomas Huth 2328fcf5ef2aSThomas Huth /* eqv & eqv. */ 2329fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2330fcf5ef2aSThomas Huth /* extsb & extsb. */ 2331fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2332fcf5ef2aSThomas Huth /* extsh & extsh. */ 2333fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2334fcf5ef2aSThomas Huth /* nand & nand. */ 2335fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2336fcf5ef2aSThomas Huth /* nor & nor. */ 2337fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2338fcf5ef2aSThomas Huth 2339fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2340fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2341fcf5ef2aSThomas Huth { 2342fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2343fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2344fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2345fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2346fcf5ef2aSThomas Huth 2347fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2348b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2349fcf5ef2aSThomas Huth } 2350fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2351fcf5ef2aSThomas Huth 2352fcf5ef2aSThomas Huth /* or & or. */ 2353fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2354fcf5ef2aSThomas Huth { 2355fcf5ef2aSThomas Huth int rs, ra, rb; 2356fcf5ef2aSThomas Huth 2357fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2358fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2359fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2360fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2361fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2362efe843d8SDavid Gibson if (rs != rb) { 2363fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2364efe843d8SDavid Gibson } else { 2365fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2366efe843d8SDavid Gibson } 2367efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2368fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2369efe843d8SDavid Gibson } 2370fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2371fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2372fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2373fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2374fcf5ef2aSThomas Huth int prio = 0; 2375fcf5ef2aSThomas Huth 2376fcf5ef2aSThomas Huth switch (rs) { 2377fcf5ef2aSThomas Huth case 1: 2378fcf5ef2aSThomas Huth /* Set process priority to low */ 2379fcf5ef2aSThomas Huth prio = 2; 2380fcf5ef2aSThomas Huth break; 2381fcf5ef2aSThomas Huth case 6: 2382fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2383fcf5ef2aSThomas Huth prio = 3; 2384fcf5ef2aSThomas Huth break; 2385fcf5ef2aSThomas Huth case 2: 2386fcf5ef2aSThomas Huth /* Set process priority to normal */ 2387fcf5ef2aSThomas Huth prio = 4; 2388fcf5ef2aSThomas Huth break; 2389fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2390fcf5ef2aSThomas Huth case 31: 2391fcf5ef2aSThomas Huth if (!ctx->pr) { 2392fcf5ef2aSThomas Huth /* Set process priority to very low */ 2393fcf5ef2aSThomas Huth prio = 1; 2394fcf5ef2aSThomas Huth } 2395fcf5ef2aSThomas Huth break; 2396fcf5ef2aSThomas Huth case 5: 2397fcf5ef2aSThomas Huth if (!ctx->pr) { 2398fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2399fcf5ef2aSThomas Huth prio = 5; 2400fcf5ef2aSThomas Huth } 2401fcf5ef2aSThomas Huth break; 2402fcf5ef2aSThomas Huth case 3: 2403fcf5ef2aSThomas Huth if (!ctx->pr) { 2404fcf5ef2aSThomas Huth /* Set process priority to high */ 2405fcf5ef2aSThomas Huth prio = 6; 2406fcf5ef2aSThomas Huth } 2407fcf5ef2aSThomas Huth break; 2408fcf5ef2aSThomas Huth case 7: 2409fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2410fcf5ef2aSThomas Huth /* Set process priority to very high */ 2411fcf5ef2aSThomas Huth prio = 7; 2412fcf5ef2aSThomas Huth } 2413fcf5ef2aSThomas Huth break; 2414fcf5ef2aSThomas Huth #endif 2415fcf5ef2aSThomas Huth default: 2416fcf5ef2aSThomas Huth break; 2417fcf5ef2aSThomas Huth } 2418fcf5ef2aSThomas Huth if (prio) { 2419fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2420fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2421fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2422fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2423fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2424fcf5ef2aSThomas Huth tcg_temp_free(t0); 2425fcf5ef2aSThomas Huth } 2426fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2427efe843d8SDavid Gibson /* 2428efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2429efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2430efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2431efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2432fcf5ef2aSThomas Huth */ 2433fcf5ef2aSThomas Huth gen_pause(ctx); 2434fcf5ef2aSThomas Huth #endif 2435fcf5ef2aSThomas Huth #endif 2436fcf5ef2aSThomas Huth } 2437fcf5ef2aSThomas Huth } 2438fcf5ef2aSThomas Huth /* orc & orc. */ 2439fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2440fcf5ef2aSThomas Huth 2441fcf5ef2aSThomas Huth /* xor & xor. */ 2442fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2443fcf5ef2aSThomas Huth { 2444fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2445efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2446efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2447efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2448efe843d8SDavid Gibson } else { 2449fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2450efe843d8SDavid Gibson } 2451efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2452fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2453fcf5ef2aSThomas Huth } 2454efe843d8SDavid Gibson } 2455fcf5ef2aSThomas Huth 2456fcf5ef2aSThomas Huth /* ori */ 2457fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2458fcf5ef2aSThomas Huth { 2459fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2460fcf5ef2aSThomas Huth 2461fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2462fcf5ef2aSThomas Huth return; 2463fcf5ef2aSThomas Huth } 2464fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2465fcf5ef2aSThomas Huth } 2466fcf5ef2aSThomas Huth 2467fcf5ef2aSThomas Huth /* oris */ 2468fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2469fcf5ef2aSThomas Huth { 2470fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2471fcf5ef2aSThomas Huth 2472fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2473fcf5ef2aSThomas Huth /* NOP */ 2474fcf5ef2aSThomas Huth return; 2475fcf5ef2aSThomas Huth } 2476efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2477efe843d8SDavid Gibson uimm << 16); 2478fcf5ef2aSThomas Huth } 2479fcf5ef2aSThomas Huth 2480fcf5ef2aSThomas Huth /* xori */ 2481fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2482fcf5ef2aSThomas Huth { 2483fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2484fcf5ef2aSThomas Huth 2485fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2486fcf5ef2aSThomas Huth /* NOP */ 2487fcf5ef2aSThomas Huth return; 2488fcf5ef2aSThomas Huth } 2489fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2490fcf5ef2aSThomas Huth } 2491fcf5ef2aSThomas Huth 2492fcf5ef2aSThomas Huth /* xoris */ 2493fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2494fcf5ef2aSThomas Huth { 2495fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2496fcf5ef2aSThomas Huth 2497fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2498fcf5ef2aSThomas Huth /* NOP */ 2499fcf5ef2aSThomas Huth return; 2500fcf5ef2aSThomas Huth } 2501efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2502efe843d8SDavid Gibson uimm << 16); 2503fcf5ef2aSThomas Huth } 2504fcf5ef2aSThomas Huth 2505fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2506fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2507fcf5ef2aSThomas Huth { 2508fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2509fcf5ef2aSThomas Huth } 2510fcf5ef2aSThomas Huth 2511fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2512fcf5ef2aSThomas Huth { 251379770002SRichard Henderson #if defined(TARGET_PPC64) 2514fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251579770002SRichard Henderson #else 251679770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251779770002SRichard Henderson #endif 2518fcf5ef2aSThomas Huth } 2519fcf5ef2aSThomas Huth 2520fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2521fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2522fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2523fcf5ef2aSThomas Huth { 252479770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2525fcf5ef2aSThomas Huth } 2526fcf5ef2aSThomas Huth #endif 2527fcf5ef2aSThomas Huth 2528fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2529fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2530fcf5ef2aSThomas Huth { 2531fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2532fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2533fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2534fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2535fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2536fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2537fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2538fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2539fcf5ef2aSThomas Huth tcg_temp_free(t0); 2540fcf5ef2aSThomas Huth } 2541fcf5ef2aSThomas Huth 2542fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2543fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2544fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2545fcf5ef2aSThomas Huth { 2546fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2547fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2548fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2549fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2550fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2551fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2552fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2553fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2554fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2555fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2556fcf5ef2aSThomas Huth tcg_temp_free(t0); 2557fcf5ef2aSThomas Huth } 2558fcf5ef2aSThomas Huth #endif 2559fcf5ef2aSThomas Huth 2560fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2561fcf5ef2aSThomas Huth /* bpermd */ 2562fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2563fcf5ef2aSThomas Huth { 2564fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2565fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2566fcf5ef2aSThomas Huth } 2567fcf5ef2aSThomas Huth #endif 2568fcf5ef2aSThomas Huth 2569fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2570fcf5ef2aSThomas Huth /* extsw & extsw. */ 2571fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2572fcf5ef2aSThomas Huth 2573fcf5ef2aSThomas Huth /* cntlzd */ 2574fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2575fcf5ef2aSThomas Huth { 25769b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2577efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2578fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2579fcf5ef2aSThomas Huth } 2580efe843d8SDavid Gibson } 2581fcf5ef2aSThomas Huth 2582fcf5ef2aSThomas Huth /* cnttzd */ 2583fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2584fcf5ef2aSThomas Huth { 25859b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2586fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2587fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2588fcf5ef2aSThomas Huth } 2589fcf5ef2aSThomas Huth } 2590fcf5ef2aSThomas Huth 2591fcf5ef2aSThomas Huth /* darn */ 2592fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2593fcf5ef2aSThomas Huth { 2594fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2595fcf5ef2aSThomas Huth 25967e4357f6SRichard Henderson if (l > 2) { 25977e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25987e4357f6SRichard Henderson } else { 2599f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2600fcf5ef2aSThomas Huth if (l == 0) { 2601fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26027e4357f6SRichard Henderson } else { 2603fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2604fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26057e4357f6SRichard Henderson } 2606fcf5ef2aSThomas Huth } 2607fcf5ef2aSThomas Huth } 2608fcf5ef2aSThomas Huth #endif 2609fcf5ef2aSThomas Huth 2610fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2611fcf5ef2aSThomas Huth 2612fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2613fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2614fcf5ef2aSThomas Huth { 2615fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2616fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2617fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2618fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2619fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2620fcf5ef2aSThomas Huth 2621fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2622fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2623fcf5ef2aSThomas Huth } else { 2624fcf5ef2aSThomas Huth target_ulong mask; 2625c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2626fcf5ef2aSThomas Huth TCGv t1; 2627fcf5ef2aSThomas Huth 2628fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2629fcf5ef2aSThomas Huth mb += 32; 2630fcf5ef2aSThomas Huth me += 32; 2631fcf5ef2aSThomas Huth #endif 2632fcf5ef2aSThomas Huth mask = MASK(mb, me); 2633fcf5ef2aSThomas Huth 2634c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2635c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2636c4f6a4a3SDaniele Buono mask_in_32b = false; 2637c4f6a4a3SDaniele Buono } 2638c4f6a4a3SDaniele Buono #endif 2639fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2640c4f6a4a3SDaniele Buono if (mask_in_32b) { 2641fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2642fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2643fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2644fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2645fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2646fcf5ef2aSThomas Huth } else { 2647fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2648fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2649fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2650fcf5ef2aSThomas Huth #else 2651fcf5ef2aSThomas Huth g_assert_not_reached(); 2652fcf5ef2aSThomas Huth #endif 2653fcf5ef2aSThomas Huth } 2654fcf5ef2aSThomas Huth 2655fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2656fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2657fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2658fcf5ef2aSThomas Huth tcg_temp_free(t1); 2659fcf5ef2aSThomas Huth } 2660fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2661fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2662fcf5ef2aSThomas Huth } 2663fcf5ef2aSThomas Huth } 2664fcf5ef2aSThomas Huth 2665fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2666fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2667fcf5ef2aSThomas Huth { 2668fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2669fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26707b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26717b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26727b4d326fSRichard Henderson int me = ME(ctx->opcode); 26737b4d326fSRichard Henderson int len = me - mb + 1; 26747b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2675fcf5ef2aSThomas Huth 26767b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26777b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26787b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26797b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2680fcf5ef2aSThomas Huth } else { 2681fcf5ef2aSThomas Huth target_ulong mask; 2682c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2683fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2684fcf5ef2aSThomas Huth mb += 32; 2685fcf5ef2aSThomas Huth me += 32; 2686fcf5ef2aSThomas Huth #endif 2687fcf5ef2aSThomas Huth mask = MASK(mb, me); 2688c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2689c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2690c4f6a4a3SDaniele Buono mask_in_32b = false; 2691c4f6a4a3SDaniele Buono } 2692c4f6a4a3SDaniele Buono #endif 2693c4f6a4a3SDaniele Buono if (mask_in_32b) { 26947b4d326fSRichard Henderson if (sh == 0) { 26957b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 269694f040aaSVitaly Chikunov } else { 2697fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2698fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2699fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2700fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2701fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2702fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 270394f040aaSVitaly Chikunov } 2704fcf5ef2aSThomas Huth } else { 2705fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2706fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2707fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2708fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2709fcf5ef2aSThomas Huth #else 2710fcf5ef2aSThomas Huth g_assert_not_reached(); 2711fcf5ef2aSThomas Huth #endif 2712fcf5ef2aSThomas Huth } 2713fcf5ef2aSThomas Huth } 2714fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2715fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2716fcf5ef2aSThomas Huth } 2717fcf5ef2aSThomas Huth } 2718fcf5ef2aSThomas Huth 2719fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2720fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2721fcf5ef2aSThomas Huth { 2722fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2723fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2724fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2725fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2726fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2727fcf5ef2aSThomas Huth target_ulong mask; 2728c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2729fcf5ef2aSThomas Huth 2730fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2731fcf5ef2aSThomas Huth mb += 32; 2732fcf5ef2aSThomas Huth me += 32; 2733fcf5ef2aSThomas Huth #endif 2734fcf5ef2aSThomas Huth mask = MASK(mb, me); 2735fcf5ef2aSThomas Huth 2736c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2737c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2738c4f6a4a3SDaniele Buono mask_in_32b = false; 2739c4f6a4a3SDaniele Buono } 2740c4f6a4a3SDaniele Buono #endif 2741c4f6a4a3SDaniele Buono if (mask_in_32b) { 2742fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2743fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2744fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2745fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2746fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2747fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2748fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2749fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2750fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2751fcf5ef2aSThomas Huth } else { 2752fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2753fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2754fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2755fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2756fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2757fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2758fcf5ef2aSThomas Huth #else 2759fcf5ef2aSThomas Huth g_assert_not_reached(); 2760fcf5ef2aSThomas Huth #endif 2761fcf5ef2aSThomas Huth } 2762fcf5ef2aSThomas Huth 2763fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2764fcf5ef2aSThomas Huth 2765fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2766fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2767fcf5ef2aSThomas Huth } 2768fcf5ef2aSThomas Huth } 2769fcf5ef2aSThomas Huth 2770fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2771fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2772fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2773fcf5ef2aSThomas Huth { \ 2774fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2775fcf5ef2aSThomas Huth } \ 2776fcf5ef2aSThomas Huth \ 2777fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2778fcf5ef2aSThomas Huth { \ 2779fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2780fcf5ef2aSThomas Huth } 2781fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2782fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2783fcf5ef2aSThomas Huth { \ 2784fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2785fcf5ef2aSThomas Huth } \ 2786fcf5ef2aSThomas Huth \ 2787fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2788fcf5ef2aSThomas Huth { \ 2789fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2790fcf5ef2aSThomas Huth } \ 2791fcf5ef2aSThomas Huth \ 2792fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2793fcf5ef2aSThomas Huth { \ 2794fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2795fcf5ef2aSThomas Huth } \ 2796fcf5ef2aSThomas Huth \ 2797fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2798fcf5ef2aSThomas Huth { \ 2799fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2800fcf5ef2aSThomas Huth } 2801fcf5ef2aSThomas Huth 2802fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2803fcf5ef2aSThomas Huth { 2804fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2805fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28067b4d326fSRichard Henderson int len = me - mb + 1; 28077b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2808fcf5ef2aSThomas Huth 28097b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28107b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28117b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28127b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2813fcf5ef2aSThomas Huth } else { 2814fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2815fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2816fcf5ef2aSThomas Huth } 2817fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2818fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2819fcf5ef2aSThomas Huth } 2820fcf5ef2aSThomas Huth } 2821fcf5ef2aSThomas Huth 2822fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2823fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2824fcf5ef2aSThomas Huth { 2825fcf5ef2aSThomas Huth uint32_t sh, mb; 2826fcf5ef2aSThomas Huth 2827fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2828fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2829fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2830fcf5ef2aSThomas Huth } 2831fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2832fcf5ef2aSThomas Huth 2833fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2834fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2835fcf5ef2aSThomas Huth { 2836fcf5ef2aSThomas Huth uint32_t sh, me; 2837fcf5ef2aSThomas Huth 2838fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2839fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2840fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2841fcf5ef2aSThomas Huth } 2842fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2843fcf5ef2aSThomas Huth 2844fcf5ef2aSThomas Huth /* rldic - rldic. */ 2845fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2846fcf5ef2aSThomas Huth { 2847fcf5ef2aSThomas Huth uint32_t sh, mb; 2848fcf5ef2aSThomas Huth 2849fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2850fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2851fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2852fcf5ef2aSThomas Huth } 2853fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2854fcf5ef2aSThomas Huth 2855fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2856fcf5ef2aSThomas Huth { 2857fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2858fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2859fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2860fcf5ef2aSThomas Huth TCGv t0; 2861fcf5ef2aSThomas Huth 2862fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2863fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2864fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2865fcf5ef2aSThomas Huth tcg_temp_free(t0); 2866fcf5ef2aSThomas Huth 2867fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2868fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2869fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2870fcf5ef2aSThomas Huth } 2871fcf5ef2aSThomas Huth } 2872fcf5ef2aSThomas Huth 2873fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2874fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2875fcf5ef2aSThomas Huth { 2876fcf5ef2aSThomas Huth uint32_t mb; 2877fcf5ef2aSThomas Huth 2878fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2879fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2880fcf5ef2aSThomas Huth } 2881fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2882fcf5ef2aSThomas Huth 2883fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2884fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2885fcf5ef2aSThomas Huth { 2886fcf5ef2aSThomas Huth uint32_t me; 2887fcf5ef2aSThomas Huth 2888fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2889fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2890fcf5ef2aSThomas Huth } 2891fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2892fcf5ef2aSThomas Huth 2893fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2894fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2895fcf5ef2aSThomas Huth { 2896fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2897fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2898fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2899fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2900fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2901fcf5ef2aSThomas Huth 2902fcf5ef2aSThomas Huth if (mb <= me) { 2903fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2904fcf5ef2aSThomas Huth } else { 2905fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2906fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2907fcf5ef2aSThomas Huth 2908fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2909fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2910fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2911fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2912fcf5ef2aSThomas Huth tcg_temp_free(t1); 2913fcf5ef2aSThomas Huth } 2914fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2915fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2916fcf5ef2aSThomas Huth } 2917fcf5ef2aSThomas Huth } 2918fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2919fcf5ef2aSThomas Huth #endif 2920fcf5ef2aSThomas Huth 2921fcf5ef2aSThomas Huth /*** Integer shift ***/ 2922fcf5ef2aSThomas Huth 2923fcf5ef2aSThomas Huth /* slw & slw. */ 2924fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2925fcf5ef2aSThomas Huth { 2926fcf5ef2aSThomas Huth TCGv t0, t1; 2927fcf5ef2aSThomas Huth 2928fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2929fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2930fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2931fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2932fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2933fcf5ef2aSThomas Huth #else 2934fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2935fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2936fcf5ef2aSThomas Huth #endif 2937fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2938fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2939fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2940fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2941fcf5ef2aSThomas Huth tcg_temp_free(t1); 2942fcf5ef2aSThomas Huth tcg_temp_free(t0); 2943fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2944efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2945fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2946fcf5ef2aSThomas Huth } 2947efe843d8SDavid Gibson } 2948fcf5ef2aSThomas Huth 2949fcf5ef2aSThomas Huth /* sraw & sraw. */ 2950fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2951fcf5ef2aSThomas Huth { 2952fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2953fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2954efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2955fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2956fcf5ef2aSThomas Huth } 2957efe843d8SDavid Gibson } 2958fcf5ef2aSThomas Huth 2959fcf5ef2aSThomas Huth /* srawi & srawi. */ 2960fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2961fcf5ef2aSThomas Huth { 2962fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2963fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2964fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2965fcf5ef2aSThomas Huth if (sh == 0) { 2966fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2967fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2968af1c259fSSandipan Das if (is_isa300(ctx)) { 2969af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2970af1c259fSSandipan Das } 2971fcf5ef2aSThomas Huth } else { 2972fcf5ef2aSThomas Huth TCGv t0; 2973fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2974fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2975fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2976fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2977fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2978fcf5ef2aSThomas Huth tcg_temp_free(t0); 2979fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2980af1c259fSSandipan Das if (is_isa300(ctx)) { 2981af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2982af1c259fSSandipan Das } 2983fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2984fcf5ef2aSThomas Huth } 2985fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2986fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2987fcf5ef2aSThomas Huth } 2988fcf5ef2aSThomas Huth } 2989fcf5ef2aSThomas Huth 2990fcf5ef2aSThomas Huth /* srw & srw. */ 2991fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2992fcf5ef2aSThomas Huth { 2993fcf5ef2aSThomas Huth TCGv t0, t1; 2994fcf5ef2aSThomas Huth 2995fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2996fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2997fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2998fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2999fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3000fcf5ef2aSThomas Huth #else 3001fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3002fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3003fcf5ef2aSThomas Huth #endif 3004fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3005fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3006fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3007fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3008fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3009fcf5ef2aSThomas Huth tcg_temp_free(t1); 3010fcf5ef2aSThomas Huth tcg_temp_free(t0); 3011efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3012fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3013fcf5ef2aSThomas Huth } 3014efe843d8SDavid Gibson } 3015fcf5ef2aSThomas Huth 3016fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3017fcf5ef2aSThomas Huth /* sld & sld. */ 3018fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3019fcf5ef2aSThomas Huth { 3020fcf5ef2aSThomas Huth TCGv t0, t1; 3021fcf5ef2aSThomas Huth 3022fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3023fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3024fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3025fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3026fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3027fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3028fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3029fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3030fcf5ef2aSThomas Huth tcg_temp_free(t1); 3031fcf5ef2aSThomas Huth tcg_temp_free(t0); 3032efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3033fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3034fcf5ef2aSThomas Huth } 3035efe843d8SDavid Gibson } 3036fcf5ef2aSThomas Huth 3037fcf5ef2aSThomas Huth /* srad & srad. */ 3038fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3039fcf5ef2aSThomas Huth { 3040fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3041fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3042efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3043fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3044fcf5ef2aSThomas Huth } 3045efe843d8SDavid Gibson } 3046fcf5ef2aSThomas Huth /* sradi & sradi. */ 3047fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3048fcf5ef2aSThomas Huth { 3049fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3050fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3051fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3052fcf5ef2aSThomas Huth if (sh == 0) { 3053fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3054fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3055af1c259fSSandipan Das if (is_isa300(ctx)) { 3056af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3057af1c259fSSandipan Das } 3058fcf5ef2aSThomas Huth } else { 3059fcf5ef2aSThomas Huth TCGv t0; 3060fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3061fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3062fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3063fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3064fcf5ef2aSThomas Huth tcg_temp_free(t0); 3065fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3066af1c259fSSandipan Das if (is_isa300(ctx)) { 3067af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3068af1c259fSSandipan Das } 3069fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3070fcf5ef2aSThomas Huth } 3071fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3072fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3073fcf5ef2aSThomas Huth } 3074fcf5ef2aSThomas Huth } 3075fcf5ef2aSThomas Huth 3076fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3077fcf5ef2aSThomas Huth { 3078fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3079fcf5ef2aSThomas Huth } 3080fcf5ef2aSThomas Huth 3081fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3082fcf5ef2aSThomas Huth { 3083fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3084fcf5ef2aSThomas Huth } 3085fcf5ef2aSThomas Huth 3086fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3087fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3088fcf5ef2aSThomas Huth { 3089fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3090fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3091fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3092fcf5ef2aSThomas Huth 3093fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3094fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3095fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3096fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3097fcf5ef2aSThomas Huth } 3098fcf5ef2aSThomas Huth } 3099fcf5ef2aSThomas Huth 3100fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3101fcf5ef2aSThomas Huth { 3102fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3103fcf5ef2aSThomas Huth } 3104fcf5ef2aSThomas Huth 3105fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3106fcf5ef2aSThomas Huth { 3107fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3108fcf5ef2aSThomas Huth } 3109fcf5ef2aSThomas Huth 3110fcf5ef2aSThomas Huth /* srd & srd. */ 3111fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3112fcf5ef2aSThomas Huth { 3113fcf5ef2aSThomas Huth TCGv t0, t1; 3114fcf5ef2aSThomas Huth 3115fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3116fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3117fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3118fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3119fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3120fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3121fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3122fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3123fcf5ef2aSThomas Huth tcg_temp_free(t1); 3124fcf5ef2aSThomas Huth tcg_temp_free(t0); 3125efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3126fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3127fcf5ef2aSThomas Huth } 3128efe843d8SDavid Gibson } 3129fcf5ef2aSThomas Huth #endif 3130fcf5ef2aSThomas Huth 3131fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3132fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3133fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3134fcf5ef2aSThomas Huth target_long maskl) 3135fcf5ef2aSThomas Huth { 3136fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3137fcf5ef2aSThomas Huth 3138fcf5ef2aSThomas Huth simm &= ~maskl; 3139fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3140fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3141fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3142fcf5ef2aSThomas Huth } 3143fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3144fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3145fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3146fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3147fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3148fcf5ef2aSThomas Huth } 3149fcf5ef2aSThomas Huth } else { 3150fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3151fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3152fcf5ef2aSThomas Huth } else { 3153fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3154fcf5ef2aSThomas Huth } 3155fcf5ef2aSThomas Huth } 3156fcf5ef2aSThomas Huth } 3157fcf5ef2aSThomas Huth 3158fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3159fcf5ef2aSThomas Huth { 3160fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3161fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3162fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3163fcf5ef2aSThomas Huth } else { 3164fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3165fcf5ef2aSThomas Huth } 3166fcf5ef2aSThomas Huth } else { 3167fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3168fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3169fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3170fcf5ef2aSThomas Huth } 3171fcf5ef2aSThomas Huth } 3172fcf5ef2aSThomas Huth } 3173fcf5ef2aSThomas Huth 3174fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3175fcf5ef2aSThomas Huth { 3176fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3177fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3178fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3179fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3180fcf5ef2aSThomas Huth } else { 3181fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3182fcf5ef2aSThomas Huth } 3183fcf5ef2aSThomas Huth } 3184fcf5ef2aSThomas Huth 3185fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3186fcf5ef2aSThomas Huth target_long val) 3187fcf5ef2aSThomas Huth { 3188fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3189fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3190fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3191fcf5ef2aSThomas Huth } 3192fcf5ef2aSThomas Huth } 3193fcf5ef2aSThomas Huth 3194fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3195fcf5ef2aSThomas Huth { 3196fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3197fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3198fcf5ef2aSThomas Huth } 3199fcf5ef2aSThomas Huth 3200eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3201eb63efd9SFernando Eckhardt Valle { 3202eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3203eb63efd9SFernando Eckhardt Valle if (ra) { 3204eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3205eb63efd9SFernando Eckhardt Valle } else { 3206eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3207eb63efd9SFernando Eckhardt Valle } 3208eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3209eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3210eb63efd9SFernando Eckhardt Valle } 3211eb63efd9SFernando Eckhardt Valle return ea; 3212eb63efd9SFernando Eckhardt Valle } 3213eb63efd9SFernando Eckhardt Valle 3214fcf5ef2aSThomas Huth /*** Integer load ***/ 3215fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3216fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3217fcf5ef2aSThomas Huth 3218fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3219fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3220fcf5ef2aSThomas Huth TCGv val, \ 3221fcf5ef2aSThomas Huth TCGv addr) \ 3222fcf5ef2aSThomas Huth { \ 3223fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3224fcf5ef2aSThomas Huth } 3225fcf5ef2aSThomas Huth 3226fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3227fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3228fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3229fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3230fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3231fcf5ef2aSThomas Huth 3232fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3233fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3234fcf5ef2aSThomas Huth 3235fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3236fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3237fcf5ef2aSThomas Huth TCGv_i64 val, \ 3238fcf5ef2aSThomas Huth TCGv addr) \ 3239fcf5ef2aSThomas Huth { \ 3240fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3241fcf5ef2aSThomas Huth } 3242fcf5ef2aSThomas Huth 3243fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3244fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3245fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3246fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3247fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3248fcf5ef2aSThomas Huth 3249fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3250fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3251fcf5ef2aSThomas Huth #endif 3252fcf5ef2aSThomas Huth 3253fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3254fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3255fcf5ef2aSThomas Huth TCGv val, \ 3256fcf5ef2aSThomas Huth TCGv addr) \ 3257fcf5ef2aSThomas Huth { \ 3258fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3259fcf5ef2aSThomas Huth } 3260fcf5ef2aSThomas Huth 3261e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3262fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3263e8f4c8d6SRichard Henderson #endif 3264fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3265fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3266fcf5ef2aSThomas Huth 3267fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3268fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3269fcf5ef2aSThomas Huth 3270fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3271fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3272fcf5ef2aSThomas Huth TCGv_i64 val, \ 3273fcf5ef2aSThomas Huth TCGv addr) \ 3274fcf5ef2aSThomas Huth { \ 3275fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3276fcf5ef2aSThomas Huth } 3277fcf5ef2aSThomas Huth 3278fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3279fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3280fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3281fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3282fcf5ef2aSThomas Huth 3283fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3284fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3285fcf5ef2aSThomas Huth #endif 3286fcf5ef2aSThomas Huth 3287fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3288fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3289fcf5ef2aSThomas Huth { \ 3290fcf5ef2aSThomas Huth TCGv EA; \ 3291fcf5ef2aSThomas Huth chk; \ 3292fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3293fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3294fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3295fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3296fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3297fcf5ef2aSThomas Huth } 3298fcf5ef2aSThomas Huth 3299fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3300fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3301fcf5ef2aSThomas Huth 3302fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3303fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3304fcf5ef2aSThomas Huth 330550728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 330650728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 330750728199SRoman Kapl { \ 330850728199SRoman Kapl TCGv EA; \ 330950728199SRoman Kapl CHK_SV; \ 331050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 331150728199SRoman Kapl EA = tcg_temp_new(); \ 331250728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 331350728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 331450728199SRoman Kapl tcg_temp_free(EA); \ 331550728199SRoman Kapl } 331650728199SRoman Kapl 331750728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 331850728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 331950728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 332050728199SRoman Kapl #if defined(TARGET_PPC64) 332150728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 332250728199SRoman Kapl #endif 332350728199SRoman Kapl 3324fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3325fcf5ef2aSThomas Huth /* CI load/store variants */ 3326fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3327fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3328fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3329fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3330fcf5ef2aSThomas Huth 3331fcf5ef2aSThomas Huth /* lq */ 3332fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3333fcf5ef2aSThomas Huth { 3334fcf5ef2aSThomas Huth int ra, rd; 333594bf2658SRichard Henderson TCGv EA, hi, lo; 3336fcf5ef2aSThomas Huth 3337fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3338fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3339fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3340fcf5ef2aSThomas Huth 3341fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3342fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3343fcf5ef2aSThomas Huth return; 3344fcf5ef2aSThomas Huth } 3345fcf5ef2aSThomas Huth 3346fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3347fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3348fcf5ef2aSThomas Huth return; 3349fcf5ef2aSThomas Huth } 3350fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3351fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3352fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3353fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3354fcf5ef2aSThomas Huth return; 3355fcf5ef2aSThomas Huth } 3356fcf5ef2aSThomas Huth 3357fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3358fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3359fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3360fcf5ef2aSThomas Huth 336194bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 336294bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 336394bf2658SRichard Henderson hi = cpu_gpr[rd]; 336494bf2658SRichard Henderson 336594bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3366f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 336794bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 336894bf2658SRichard Henderson if (ctx->le_mode) { 336994bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 337094bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3371fcf5ef2aSThomas Huth } else { 337294bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 337394bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 337494bf2658SRichard Henderson } 337594bf2658SRichard Henderson tcg_temp_free_i32(oi); 337694bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3377f34ec0f6SRichard Henderson } else { 337894bf2658SRichard Henderson /* Restart with exclusive lock. */ 337994bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 338094bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3381f34ec0f6SRichard Henderson } 338294bf2658SRichard Henderson } else if (ctx->le_mode) { 338394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3384fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 338594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 338694bf2658SRichard Henderson } else { 338794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 338894bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 338994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3390fcf5ef2aSThomas Huth } 3391fcf5ef2aSThomas Huth tcg_temp_free(EA); 3392fcf5ef2aSThomas Huth } 3393fcf5ef2aSThomas Huth #endif 3394fcf5ef2aSThomas Huth 3395fcf5ef2aSThomas Huth /*** Integer store ***/ 3396fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3397fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3398fcf5ef2aSThomas Huth { \ 3399fcf5ef2aSThomas Huth TCGv EA; \ 3400fcf5ef2aSThomas Huth chk; \ 3401fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3402fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3403fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3404fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3405fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3406fcf5ef2aSThomas Huth } 3407fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3408fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3409fcf5ef2aSThomas Huth 3410fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3411fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3412fcf5ef2aSThomas Huth 341350728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 341450728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 341550728199SRoman Kapl { \ 341650728199SRoman Kapl TCGv EA; \ 341750728199SRoman Kapl CHK_SV; \ 341850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 341950728199SRoman Kapl EA = tcg_temp_new(); \ 342050728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 342150728199SRoman Kapl tcg_gen_qemu_st_tl( \ 342250728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 342350728199SRoman Kapl tcg_temp_free(EA); \ 342450728199SRoman Kapl } 342550728199SRoman Kapl 342650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 342750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 342850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 342950728199SRoman Kapl #if defined(TARGET_PPC64) 343050728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 343150728199SRoman Kapl #endif 343250728199SRoman Kapl 3433fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3434fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3435fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3436fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3437fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3438fcf5ef2aSThomas Huth 3439fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3440fcf5ef2aSThomas Huth { 3441fcf5ef2aSThomas Huth int rs; 3442fcf5ef2aSThomas Huth TCGv EA; 3443fcf5ef2aSThomas Huth 3444fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3445fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3446fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3447fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3448f89ced5fSRichard Henderson TCGv hi, lo; 3449fcf5ef2aSThomas Huth 3450fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3451fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3452fcf5ef2aSThomas Huth } 3453fcf5ef2aSThomas Huth 3454fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3455fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3456fcf5ef2aSThomas Huth return; 3457fcf5ef2aSThomas Huth } 3458fcf5ef2aSThomas Huth 3459fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3460fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3461fcf5ef2aSThomas Huth return; 3462fcf5ef2aSThomas Huth } 3463fcf5ef2aSThomas Huth 3464fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3465fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3466fcf5ef2aSThomas Huth return; 3467fcf5ef2aSThomas Huth } 3468fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3469fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3470fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3471fcf5ef2aSThomas Huth 3472f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3473f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3474f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3475f89ced5fSRichard Henderson 3476f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3477f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3478f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3479f89ced5fSRichard Henderson if (ctx->le_mode) { 348068e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128, 348168e33d86SRichard Henderson ctx->mem_idx)); 3482f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3483fcf5ef2aSThomas Huth } else { 348468e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128, 348568e33d86SRichard Henderson ctx->mem_idx)); 3486f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3487f89ced5fSRichard Henderson } 3488f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3489f34ec0f6SRichard Henderson } else { 3490f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3491f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3492f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3493f34ec0f6SRichard Henderson } 3494f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3495f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3496fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3497f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3498f89ced5fSRichard Henderson } else { 3499f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3500f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3501f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3502fcf5ef2aSThomas Huth } 3503fcf5ef2aSThomas Huth tcg_temp_free(EA); 3504fcf5ef2aSThomas Huth } else { 3505fcf5ef2aSThomas Huth /* std / stdu */ 3506fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3507fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3508fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3509fcf5ef2aSThomas Huth return; 3510fcf5ef2aSThomas Huth } 3511fcf5ef2aSThomas Huth } 3512fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3513fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3514fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3515fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3516efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3517fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3518efe843d8SDavid Gibson } 3519fcf5ef2aSThomas Huth tcg_temp_free(EA); 3520fcf5ef2aSThomas Huth } 3521fcf5ef2aSThomas Huth } 3522fcf5ef2aSThomas Huth #endif 3523fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3524fcf5ef2aSThomas Huth 3525fcf5ef2aSThomas Huth /* lhbrx */ 3526fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3527fcf5ef2aSThomas Huth 3528fcf5ef2aSThomas Huth /* lwbrx */ 3529fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3530fcf5ef2aSThomas Huth 3531fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3532fcf5ef2aSThomas Huth /* ldbrx */ 3533fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3534fcf5ef2aSThomas Huth /* stdbrx */ 3535fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3536fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3537fcf5ef2aSThomas Huth 3538fcf5ef2aSThomas Huth /* sthbrx */ 3539fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3540fcf5ef2aSThomas Huth /* stwbrx */ 3541fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3542fcf5ef2aSThomas Huth 3543fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3544fcf5ef2aSThomas Huth 3545fcf5ef2aSThomas Huth /* lmw */ 3546fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3547fcf5ef2aSThomas Huth { 3548fcf5ef2aSThomas Huth TCGv t0; 3549fcf5ef2aSThomas Huth TCGv_i32 t1; 3550fcf5ef2aSThomas Huth 3551fcf5ef2aSThomas Huth if (ctx->le_mode) { 3552fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3553fcf5ef2aSThomas Huth return; 3554fcf5ef2aSThomas Huth } 3555fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3556fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3557fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3558fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3559fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3560fcf5ef2aSThomas Huth tcg_temp_free(t0); 3561fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3562fcf5ef2aSThomas Huth } 3563fcf5ef2aSThomas Huth 3564fcf5ef2aSThomas Huth /* stmw */ 3565fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3566fcf5ef2aSThomas Huth { 3567fcf5ef2aSThomas Huth TCGv t0; 3568fcf5ef2aSThomas Huth TCGv_i32 t1; 3569fcf5ef2aSThomas Huth 3570fcf5ef2aSThomas Huth if (ctx->le_mode) { 3571fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3572fcf5ef2aSThomas Huth return; 3573fcf5ef2aSThomas Huth } 3574fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3575fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3576fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3577fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3578fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3579fcf5ef2aSThomas Huth tcg_temp_free(t0); 3580fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3581fcf5ef2aSThomas Huth } 3582fcf5ef2aSThomas Huth 3583fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3584fcf5ef2aSThomas Huth 3585fcf5ef2aSThomas Huth /* lswi */ 3586efe843d8SDavid Gibson /* 3587efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3588efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3589efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3590efe843d8SDavid Gibson * spec... 3591fcf5ef2aSThomas Huth */ 3592fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3593fcf5ef2aSThomas Huth { 3594fcf5ef2aSThomas Huth TCGv t0; 3595fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3596fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3597fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3598fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3599fcf5ef2aSThomas Huth int nr; 3600fcf5ef2aSThomas Huth 3601fcf5ef2aSThomas Huth if (ctx->le_mode) { 3602fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3603fcf5ef2aSThomas Huth return; 3604fcf5ef2aSThomas Huth } 3605efe843d8SDavid Gibson if (nb == 0) { 3606fcf5ef2aSThomas Huth nb = 32; 3607efe843d8SDavid Gibson } 3608f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3609fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3610fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3611fcf5ef2aSThomas Huth return; 3612fcf5ef2aSThomas Huth } 3613fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3614fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3615fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3616fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3617fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3618fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3619fcf5ef2aSThomas Huth tcg_temp_free(t0); 3620fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3621fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3622fcf5ef2aSThomas Huth } 3623fcf5ef2aSThomas Huth 3624fcf5ef2aSThomas Huth /* lswx */ 3625fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3626fcf5ef2aSThomas Huth { 3627fcf5ef2aSThomas Huth TCGv t0; 3628fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3629fcf5ef2aSThomas Huth 3630fcf5ef2aSThomas Huth if (ctx->le_mode) { 3631fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3632fcf5ef2aSThomas Huth return; 3633fcf5ef2aSThomas Huth } 3634fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3635fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3636fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3637fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3638fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3639fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3640fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3641fcf5ef2aSThomas Huth tcg_temp_free(t0); 3642fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3643fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3644fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3645fcf5ef2aSThomas Huth } 3646fcf5ef2aSThomas Huth 3647fcf5ef2aSThomas Huth /* stswi */ 3648fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3649fcf5ef2aSThomas Huth { 3650fcf5ef2aSThomas Huth TCGv t0; 3651fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3652fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3653fcf5ef2aSThomas Huth 3654fcf5ef2aSThomas Huth if (ctx->le_mode) { 3655fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3656fcf5ef2aSThomas Huth return; 3657fcf5ef2aSThomas Huth } 3658fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3659fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3660fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3661efe843d8SDavid Gibson if (nb == 0) { 3662fcf5ef2aSThomas Huth nb = 32; 3663efe843d8SDavid Gibson } 3664fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3665fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3666fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3667fcf5ef2aSThomas Huth tcg_temp_free(t0); 3668fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3669fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3670fcf5ef2aSThomas Huth } 3671fcf5ef2aSThomas Huth 3672fcf5ef2aSThomas Huth /* stswx */ 3673fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3674fcf5ef2aSThomas Huth { 3675fcf5ef2aSThomas Huth TCGv t0; 3676fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3677fcf5ef2aSThomas Huth 3678fcf5ef2aSThomas Huth if (ctx->le_mode) { 3679fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3680fcf5ef2aSThomas Huth return; 3681fcf5ef2aSThomas Huth } 3682fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3683fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3684fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3685fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3686fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3687fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3688fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3689fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3690fcf5ef2aSThomas Huth tcg_temp_free(t0); 3691fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3692fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3693fcf5ef2aSThomas Huth } 3694fcf5ef2aSThomas Huth 3695fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3696fcf5ef2aSThomas Huth /* eieio */ 3697fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3698fcf5ef2aSThomas Huth { 3699c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3700c8fd8373SCédric Le Goater 3701c8fd8373SCédric Le Goater /* 3702c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3703c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3704c8fd8373SCédric Le Goater */ 3705c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3706c8fd8373SCédric Le Goater /* 3707c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3708c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3709c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3710c8fd8373SCédric Le Goater * complain to the user. 3711c8fd8373SCédric Le Goater */ 3712c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3713c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 37142c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3715c8fd8373SCédric Le Goater } else { 3716c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3717c8fd8373SCédric Le Goater } 3718c8fd8373SCédric Le Goater } 3719c8fd8373SCédric Le Goater 3720c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3721fcf5ef2aSThomas Huth } 3722fcf5ef2aSThomas Huth 3723fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3724fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3725fcf5ef2aSThomas Huth { 3726fcf5ef2aSThomas Huth TCGv_i32 t; 3727fcf5ef2aSThomas Huth TCGLabel *l; 3728fcf5ef2aSThomas Huth 3729fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3730fcf5ef2aSThomas Huth return; 3731fcf5ef2aSThomas Huth } 3732fcf5ef2aSThomas Huth l = gen_new_label(); 3733fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3734fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3735fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3736fcf5ef2aSThomas Huth if (global) { 3737fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3738fcf5ef2aSThomas Huth } else { 3739fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3740fcf5ef2aSThomas Huth } 3741fcf5ef2aSThomas Huth gen_set_label(l); 3742fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3743fcf5ef2aSThomas Huth } 3744fcf5ef2aSThomas Huth #else 3745fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3746fcf5ef2aSThomas Huth #endif 3747fcf5ef2aSThomas Huth 3748fcf5ef2aSThomas Huth /* isync */ 3749fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3750fcf5ef2aSThomas Huth { 3751fcf5ef2aSThomas Huth /* 3752fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3753fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3754fcf5ef2aSThomas Huth */ 3755fcf5ef2aSThomas Huth if (!ctx->pr) { 3756fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3757fcf5ef2aSThomas Huth } 37584771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3759d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3760fcf5ef2aSThomas Huth } 3761fcf5ef2aSThomas Huth 3762fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3763fcf5ef2aSThomas Huth 376414776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 37652a4e6c1bSRichard Henderson { 37662a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 37672a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 37682a4e6c1bSRichard Henderson 37692a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 37702a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 37712a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 37722a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 37732a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 37742a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 37752a4e6c1bSRichard Henderson tcg_temp_free(t0); 37762a4e6c1bSRichard Henderson } 37772a4e6c1bSRichard Henderson 3778fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3779fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3780fcf5ef2aSThomas Huth { \ 37812a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3782fcf5ef2aSThomas Huth } 3783fcf5ef2aSThomas Huth 3784fcf5ef2aSThomas Huth /* lwarx */ 3785fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3786fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3787fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3788fcf5ef2aSThomas Huth 378914776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 379020923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 379120923c1dSRichard Henderson { 379220923c1dSRichard Henderson TCGv t = tcg_temp_new(); 379320923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 379420923c1dSRichard Henderson TCGv u = tcg_temp_new(); 379520923c1dSRichard Henderson 379620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 379720923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 379820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 379920923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 380020923c1dSRichard Henderson 380120923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 380220923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 380320923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 380420923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 380520923c1dSRichard Henderson 380620923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 380720923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 380820923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 380920923c1dSRichard Henderson 381020923c1dSRichard Henderson tcg_temp_free(t); 381120923c1dSRichard Henderson tcg_temp_free(t2); 381220923c1dSRichard Henderson tcg_temp_free(u); 381320923c1dSRichard Henderson } 381420923c1dSRichard Henderson 381514776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 381620ba8504SRichard Henderson { 381720ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 381820ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 381920923c1dSRichard Henderson int rt = rD(ctx->opcode); 382020923c1dSRichard Henderson bool need_serial; 382120ba8504SRichard Henderson TCGv src, dst; 382220ba8504SRichard Henderson 382320ba8504SRichard Henderson gen_addr_register(ctx, EA); 382420923c1dSRichard Henderson dst = cpu_gpr[rt]; 382520923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 382620ba8504SRichard Henderson 382720923c1dSRichard Henderson need_serial = false; 382820ba8504SRichard Henderson memop |= MO_ALIGN; 382920ba8504SRichard Henderson switch (gpr_FC) { 383020ba8504SRichard Henderson case 0: /* Fetch and add */ 383120ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 383220ba8504SRichard Henderson break; 383320ba8504SRichard Henderson case 1: /* Fetch and xor */ 383420ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 383520ba8504SRichard Henderson break; 383620ba8504SRichard Henderson case 2: /* Fetch and or */ 383720ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 383820ba8504SRichard Henderson break; 383920ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 384020ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 384120ba8504SRichard Henderson break; 3842b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3843b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3844b8ce0f86SRichard Henderson break; 3845b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3846b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3847b8ce0f86SRichard Henderson break; 3848b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3849b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3850b8ce0f86SRichard Henderson break; 3851b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3852b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3853b8ce0f86SRichard Henderson break; 385420ba8504SRichard Henderson case 8: /* Swap */ 385520ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 385620ba8504SRichard Henderson break; 385720923c1dSRichard Henderson 385820923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 385920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 386020923c1dSRichard Henderson need_serial = true; 386120923c1dSRichard Henderson } else { 386220923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 386320923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 386420923c1dSRichard Henderson 386520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 386620923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 386720923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 386820923c1dSRichard Henderson } else { 386920923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 387020923c1dSRichard Henderson } 387120923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 387220923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 387320923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 387420923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 387520923c1dSRichard Henderson 387620923c1dSRichard Henderson tcg_temp_free(t0); 387720923c1dSRichard Henderson tcg_temp_free(t1); 387820923c1dSRichard Henderson } 387920ba8504SRichard Henderson break; 388020923c1dSRichard Henderson 388120923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 388220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 388320923c1dSRichard Henderson need_serial = true; 388420923c1dSRichard Henderson } else { 388520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 388620923c1dSRichard Henderson } 388720923c1dSRichard Henderson break; 388820923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 388920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 389020923c1dSRichard Henderson need_serial = true; 389120923c1dSRichard Henderson } else { 389220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 389320923c1dSRichard Henderson } 389420923c1dSRichard Henderson break; 389520923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 389620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 389720923c1dSRichard Henderson need_serial = true; 389820923c1dSRichard Henderson } else { 389920923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 390020923c1dSRichard Henderson } 390120923c1dSRichard Henderson break; 390220923c1dSRichard Henderson 390320ba8504SRichard Henderson default: 390420ba8504SRichard Henderson /* invoke data storage error handler */ 390520ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 390620ba8504SRichard Henderson } 390720ba8504SRichard Henderson tcg_temp_free(EA); 390820923c1dSRichard Henderson 390920923c1dSRichard Henderson if (need_serial) { 391020923c1dSRichard Henderson /* Restart with exclusive lock. */ 391120923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 391220923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 391320923c1dSRichard Henderson } 3914a68a6146SBalamuruhan S } 3915a68a6146SBalamuruhan S 391620ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 391720ba8504SRichard Henderson { 391820ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 391920ba8504SRichard Henderson } 392020ba8504SRichard Henderson 392120ba8504SRichard Henderson #ifdef TARGET_PPC64 392220ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 392320ba8504SRichard Henderson { 392420ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 392520ba8504SRichard Henderson } 3926a68a6146SBalamuruhan S #endif 3927a68a6146SBalamuruhan S 392814776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 39299deb041cSRichard Henderson { 39309deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 39319deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 39329deb041cSRichard Henderson TCGv src, discard; 39339deb041cSRichard Henderson 39349deb041cSRichard Henderson gen_addr_register(ctx, EA); 39359deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 39369deb041cSRichard Henderson discard = tcg_temp_new(); 39379deb041cSRichard Henderson 39389deb041cSRichard Henderson memop |= MO_ALIGN; 39399deb041cSRichard Henderson switch (gpr_FC) { 39409deb041cSRichard Henderson case 0: /* add and Store */ 39419deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39429deb041cSRichard Henderson break; 39439deb041cSRichard Henderson case 1: /* xor and Store */ 39449deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39459deb041cSRichard Henderson break; 39469deb041cSRichard Henderson case 2: /* Or and Store */ 39479deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39489deb041cSRichard Henderson break; 39499deb041cSRichard Henderson case 3: /* 'and' and Store */ 39509deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39519deb041cSRichard Henderson break; 39529deb041cSRichard Henderson case 4: /* Store max unsigned */ 3953b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3954b8ce0f86SRichard Henderson break; 39559deb041cSRichard Henderson case 5: /* Store max signed */ 3956b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3957b8ce0f86SRichard Henderson break; 39589deb041cSRichard Henderson case 6: /* Store min unsigned */ 3959b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3960b8ce0f86SRichard Henderson break; 39619deb041cSRichard Henderson case 7: /* Store min signed */ 3962b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3963b8ce0f86SRichard Henderson break; 39649deb041cSRichard Henderson case 24: /* Store twin */ 39657fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 39667fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 39677fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 39687fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 39697fbc2b20SRichard Henderson } else { 39707fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 39717fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 39727fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 39737fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 39747fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 39757fbc2b20SRichard Henderson 39767fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 39777fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 39787fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 39797fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 39807fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 39817fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 39827fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 39837fbc2b20SRichard Henderson 39847fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 39857fbc2b20SRichard Henderson tcg_temp_free(s2); 39867fbc2b20SRichard Henderson tcg_temp_free(s); 39877fbc2b20SRichard Henderson tcg_temp_free(t2); 39887fbc2b20SRichard Henderson tcg_temp_free(t); 39897fbc2b20SRichard Henderson } 39909deb041cSRichard Henderson break; 39919deb041cSRichard Henderson default: 39929deb041cSRichard Henderson /* invoke data storage error handler */ 39939deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 39949deb041cSRichard Henderson } 39959deb041cSRichard Henderson tcg_temp_free(discard); 39969deb041cSRichard Henderson tcg_temp_free(EA); 3997a3401188SBalamuruhan S } 3998a3401188SBalamuruhan S 39999deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 40009deb041cSRichard Henderson { 40019deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 40029deb041cSRichard Henderson } 40039deb041cSRichard Henderson 40049deb041cSRichard Henderson #ifdef TARGET_PPC64 40059deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 40069deb041cSRichard Henderson { 40079deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 40089deb041cSRichard Henderson } 4009a3401188SBalamuruhan S #endif 4010a3401188SBalamuruhan S 401114776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4012fcf5ef2aSThomas Huth { 4013253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4014253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4015d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4016d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4017fcf5ef2aSThomas Huth 4018d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4019d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4020d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4021d8b86898SRichard Henderson tcg_temp_free(t0); 4022253ce7b2SNikunj A Dadhania 4023253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4024253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4025253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4026253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4027253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4028253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4029253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4030253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4031253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4032253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4033253ce7b2SNikunj A Dadhania 4034fcf5ef2aSThomas Huth gen_set_label(l1); 40354771df23SNikunj A Dadhania 4036efe843d8SDavid Gibson /* 4037efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4038efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4039efe843d8SDavid Gibson */ 40404771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4041253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4042253ce7b2SNikunj A Dadhania 4043253ce7b2SNikunj A Dadhania gen_set_label(l2); 4044fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4045fcf5ef2aSThomas Huth } 4046fcf5ef2aSThomas Huth 4047fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4048fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4049fcf5ef2aSThomas Huth { \ 4050d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4051fcf5ef2aSThomas Huth } 4052fcf5ef2aSThomas Huth 4053fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4054fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4055fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4056fcf5ef2aSThomas Huth 4057fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4058fcf5ef2aSThomas Huth /* ldarx */ 4059fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4060fcf5ef2aSThomas Huth /* stdcx. */ 4061fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4062fcf5ef2aSThomas Huth 4063fcf5ef2aSThomas Huth /* lqarx */ 4064fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4065fcf5ef2aSThomas Huth { 4066fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 406794bf2658SRichard Henderson TCGv EA, hi, lo; 4068fcf5ef2aSThomas Huth 4069fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4070fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4071fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4072fcf5ef2aSThomas Huth return; 4073fcf5ef2aSThomas Huth } 4074fcf5ef2aSThomas Huth 4075fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 407694bf2658SRichard Henderson EA = tcg_temp_new(); 4077fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 407894bf2658SRichard Henderson 407994bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 408094bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 408194bf2658SRichard Henderson hi = cpu_gpr[rd]; 408294bf2658SRichard Henderson 408394bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4084f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 408594bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 408694bf2658SRichard Henderson if (ctx->le_mode) { 408768e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 408894bf2658SRichard Henderson ctx->mem_idx)); 408994bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4090fcf5ef2aSThomas Huth } else { 409168e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 409294bf2658SRichard Henderson ctx->mem_idx)); 409394bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4094fcf5ef2aSThomas Huth } 409594bf2658SRichard Henderson tcg_temp_free_i32(oi); 409694bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4097f34ec0f6SRichard Henderson } else { 409894bf2658SRichard Henderson /* Restart with exclusive lock. */ 409994bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 410094bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 410194bf2658SRichard Henderson tcg_temp_free(EA); 410294bf2658SRichard Henderson return; 4103f34ec0f6SRichard Henderson } 410494bf2658SRichard Henderson } else if (ctx->le_mode) { 410594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4106fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4107fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 410894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 410994bf2658SRichard Henderson } else { 411094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 411194bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 411294bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 411394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 411494bf2658SRichard Henderson } 4115fcf5ef2aSThomas Huth tcg_temp_free(EA); 411694bf2658SRichard Henderson 411794bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 411894bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4119fcf5ef2aSThomas Huth } 4120fcf5ef2aSThomas Huth 4121fcf5ef2aSThomas Huth /* stqcx. */ 4122fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4123fcf5ef2aSThomas Huth { 41244a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 41254a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4126fcf5ef2aSThomas Huth 41274a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4128fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4129fcf5ef2aSThomas Huth return; 4130fcf5ef2aSThomas Huth } 41314a9b3c5dSRichard Henderson 4132fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 41334a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4134fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4135fcf5ef2aSThomas Huth 41364a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 41374a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 41384a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4139fcf5ef2aSThomas Huth 41404a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4141f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 414268e33d86SRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 41434a9b3c5dSRichard Henderson if (ctx->le_mode) { 4144f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4145f34ec0f6SRichard Henderson EA, lo, hi, oi); 4146fcf5ef2aSThomas Huth } else { 4147f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4148f34ec0f6SRichard Henderson EA, lo, hi, oi); 4149fcf5ef2aSThomas Huth } 4150f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4151f34ec0f6SRichard Henderson } else { 41524a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 41534a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 41544a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4155f34ec0f6SRichard Henderson } 4156fcf5ef2aSThomas Huth tcg_temp_free(EA); 41574a9b3c5dSRichard Henderson } else { 41584a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 41594a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 41604a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 41614a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4162fcf5ef2aSThomas Huth 41634a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 41644a9b3c5dSRichard Henderson tcg_temp_free(EA); 41654a9b3c5dSRichard Henderson 41664a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 41674a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 41684a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 41694a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 41704a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 41714a9b3c5dSRichard Henderson 41724a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 41734a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 41744a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 41754a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 41764a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 41774a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 41784a9b3c5dSRichard Henderson 41794a9b3c5dSRichard Henderson /* Success */ 41804a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 41814a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 41824a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 41834a9b3c5dSRichard Henderson 41844a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 41854a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 41864a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 41874a9b3c5dSRichard Henderson 41884a9b3c5dSRichard Henderson gen_set_label(lab_fail); 41894a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 41904a9b3c5dSRichard Henderson 41914a9b3c5dSRichard Henderson gen_set_label(lab_over); 41924a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 41934a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 41944a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 41954a9b3c5dSRichard Henderson } 41964a9b3c5dSRichard Henderson } 4197fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4198fcf5ef2aSThomas Huth 4199fcf5ef2aSThomas Huth /* sync */ 4200fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4201fcf5ef2aSThomas Huth { 4202fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4203fcf5ef2aSThomas Huth 4204fcf5ef2aSThomas Huth /* 4205fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4206fcf5ef2aSThomas Huth * 4207fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4208fcf5ef2aSThomas Huth * 4209fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4210fcf5ef2aSThomas Huth * check MSR_PR as well. 4211fcf5ef2aSThomas Huth */ 4212fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4213fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4214fcf5ef2aSThomas Huth } 42154771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4216fcf5ef2aSThomas Huth } 4217fcf5ef2aSThomas Huth 4218fcf5ef2aSThomas Huth /* wait */ 4219fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4220fcf5ef2aSThomas Huth { 4221fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4222fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4223fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4224fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4225fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4226b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4227fcf5ef2aSThomas Huth } 4228fcf5ef2aSThomas Huth 4229fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4230fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4231fcf5ef2aSThomas Huth { 4232fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4233fcf5ef2aSThomas Huth GEN_PRIV; 4234fcf5ef2aSThomas Huth #else 4235fcf5ef2aSThomas Huth TCGv_i32 t; 4236fcf5ef2aSThomas Huth 4237fcf5ef2aSThomas Huth CHK_HV; 4238fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4239fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4240fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4241154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4242154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4243fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4244fcf5ef2aSThomas Huth } 4245fcf5ef2aSThomas Huth 4246fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4247fcf5ef2aSThomas Huth { 4248fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4249fcf5ef2aSThomas Huth GEN_PRIV; 4250fcf5ef2aSThomas Huth #else 4251fcf5ef2aSThomas Huth TCGv_i32 t; 4252fcf5ef2aSThomas Huth 4253fcf5ef2aSThomas Huth CHK_HV; 4254fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4255fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4256fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4257154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4258154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4259fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4260fcf5ef2aSThomas Huth } 4261fcf5ef2aSThomas Huth 4262cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4263cdee0e72SNikunj A Dadhania { 426421c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 426521c0d66aSBenjamin Herrenschmidt GEN_PRIV; 426621c0d66aSBenjamin Herrenschmidt #else 426721c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 426821c0d66aSBenjamin Herrenschmidt 426921c0d66aSBenjamin Herrenschmidt CHK_HV; 427021c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 427121c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 427221c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 427321c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 427421c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 427521c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4276cdee0e72SNikunj A Dadhania } 4277cdee0e72SNikunj A Dadhania 4278fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4279fcf5ef2aSThomas Huth { 4280fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4281fcf5ef2aSThomas Huth GEN_PRIV; 4282fcf5ef2aSThomas Huth #else 4283fcf5ef2aSThomas Huth TCGv_i32 t; 4284fcf5ef2aSThomas Huth 4285fcf5ef2aSThomas Huth CHK_HV; 4286fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4287fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4288fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4289154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4290154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4291fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4292fcf5ef2aSThomas Huth } 4293fcf5ef2aSThomas Huth 4294fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4295fcf5ef2aSThomas Huth { 4296fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4297fcf5ef2aSThomas Huth GEN_PRIV; 4298fcf5ef2aSThomas Huth #else 4299fcf5ef2aSThomas Huth TCGv_i32 t; 4300fcf5ef2aSThomas Huth 4301fcf5ef2aSThomas Huth CHK_HV; 4302fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4303fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4304fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4305154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4306154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4307fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4308fcf5ef2aSThomas Huth } 4309fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4310fcf5ef2aSThomas Huth 4311fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4312fcf5ef2aSThomas Huth { 4313fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4314efe843d8SDavid Gibson if (ctx->has_cfar) { 4315fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4316efe843d8SDavid Gibson } 4317fcf5ef2aSThomas Huth #endif 4318fcf5ef2aSThomas Huth } 4319fcf5ef2aSThomas Huth 4320fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4321fcf5ef2aSThomas Huth { 43226e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4323fcf5ef2aSThomas Huth } 4324fcf5ef2aSThomas Huth 43250e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 43260e3bf489SRoman Kapl { 43279498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 43280e3bf489SRoman Kapl gen_debug_exception(ctx); 43290e3bf489SRoman Kapl } else { 43300e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 43310e3bf489SRoman Kapl } 43320e3bf489SRoman Kapl } 43330e3bf489SRoman Kapl 4334fcf5ef2aSThomas Huth /*** Branch ***/ 4335c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4336fcf5ef2aSThomas Huth { 4337fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4338fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4339fcf5ef2aSThomas Huth } 4340fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4341fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4342fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 434307ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4344fcf5ef2aSThomas Huth } else { 4345fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 43460e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4347fcf5ef2aSThomas Huth } 4348fcf5ef2aSThomas Huth } 4349fcf5ef2aSThomas Huth 4350fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4351fcf5ef2aSThomas Huth { 4352fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4353fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4354fcf5ef2aSThomas Huth } 4355fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4356fcf5ef2aSThomas Huth } 4357fcf5ef2aSThomas Huth 4358fcf5ef2aSThomas Huth /* b ba bl bla */ 4359fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4360fcf5ef2aSThomas Huth { 4361fcf5ef2aSThomas Huth target_ulong li, target; 4362fcf5ef2aSThomas Huth 4363fcf5ef2aSThomas Huth /* sign extend LI */ 4364fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4365fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4366fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43672c2bcb1bSRichard Henderson target = ctx->cia + li; 4368fcf5ef2aSThomas Huth } else { 4369fcf5ef2aSThomas Huth target = li; 4370fcf5ef2aSThomas Huth } 4371fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4372b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4373fcf5ef2aSThomas Huth } 43742c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4375fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 43766086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4377fcf5ef2aSThomas Huth } 4378fcf5ef2aSThomas Huth 4379fcf5ef2aSThomas Huth #define BCOND_IM 0 4380fcf5ef2aSThomas Huth #define BCOND_LR 1 4381fcf5ef2aSThomas Huth #define BCOND_CTR 2 4382fcf5ef2aSThomas Huth #define BCOND_TAR 3 4383fcf5ef2aSThomas Huth 4384c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4385fcf5ef2aSThomas Huth { 4386fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4387fcf5ef2aSThomas Huth TCGLabel *l1; 4388fcf5ef2aSThomas Huth TCGv target; 43890e3bf489SRoman Kapl 4390fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4391fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4392efe843d8SDavid Gibson if (type == BCOND_CTR) { 4393fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4394efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4395fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4396efe843d8SDavid Gibson } else { 4397fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4398efe843d8SDavid Gibson } 4399fcf5ef2aSThomas Huth } else { 4400f764718dSRichard Henderson target = NULL; 4401fcf5ef2aSThomas Huth } 4402efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4403b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4404efe843d8SDavid Gibson } 4405fcf5ef2aSThomas Huth l1 = gen_new_label(); 4406fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4407fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4408fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4409fa200c95SGreg Kurz 4410fa200c95SGreg Kurz if (type == BCOND_CTR) { 4411fa200c95SGreg Kurz /* 4412fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4413fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4414fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 441515d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 441615d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 441715d68c5eSGreg Kurz * it basically useless and thus never used in real code. 441815d68c5eSGreg Kurz * 441915d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 442015d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 442115d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 442215d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 442315d68c5eSGreg Kurz * doing anything else harmful. 4424fa200c95SGreg Kurz */ 4425d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4426fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 44279acc95cdSGreg Kurz tcg_temp_free(temp); 44289acc95cdSGreg Kurz tcg_temp_free(target); 4429fcf5ef2aSThomas Huth return; 4430fcf5ef2aSThomas Huth } 4431fa200c95SGreg Kurz 4432fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4433fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4434fa200c95SGreg Kurz } else { 4435fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4436fa200c95SGreg Kurz } 4437fa200c95SGreg Kurz if (bo & 0x2) { 4438fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4439fa200c95SGreg Kurz } else { 4440fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4441fa200c95SGreg Kurz } 4442fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4443fa200c95SGreg Kurz } else { 4444fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4445fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4446fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4447fcf5ef2aSThomas Huth } else { 4448fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4449fcf5ef2aSThomas Huth } 4450fcf5ef2aSThomas Huth if (bo & 0x2) { 4451fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4452fcf5ef2aSThomas Huth } else { 4453fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4454fcf5ef2aSThomas Huth } 4455fa200c95SGreg Kurz } 4456fcf5ef2aSThomas Huth tcg_temp_free(temp); 4457fcf5ef2aSThomas Huth } 4458fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4459fcf5ef2aSThomas Huth /* Test CR */ 4460fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4461fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4462fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4463fcf5ef2aSThomas Huth 4464fcf5ef2aSThomas Huth if (bo & 0x8) { 4465fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4466fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4467fcf5ef2aSThomas Huth } else { 4468fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4469fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4470fcf5ef2aSThomas Huth } 4471fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4472fcf5ef2aSThomas Huth } 44732c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4474fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4475fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4476fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 44772c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4478fcf5ef2aSThomas Huth } else { 4479fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4480fcf5ef2aSThomas Huth } 4481fcf5ef2aSThomas Huth } else { 4482fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4483fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4484fcf5ef2aSThomas Huth } else { 4485fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4486fcf5ef2aSThomas Huth } 44870e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4488c4a2e3a9SRichard Henderson tcg_temp_free(target); 4489c4a2e3a9SRichard Henderson } 4490fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 44910e3bf489SRoman Kapl /* fallthrough case */ 4492fcf5ef2aSThomas Huth gen_set_label(l1); 4493b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4494fcf5ef2aSThomas Huth } 44956086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4496fcf5ef2aSThomas Huth } 4497fcf5ef2aSThomas Huth 4498fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4499fcf5ef2aSThomas Huth { 4500fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4501fcf5ef2aSThomas Huth } 4502fcf5ef2aSThomas Huth 4503fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4504fcf5ef2aSThomas Huth { 4505fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4506fcf5ef2aSThomas Huth } 4507fcf5ef2aSThomas Huth 4508fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4509fcf5ef2aSThomas Huth { 4510fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4511fcf5ef2aSThomas Huth } 4512fcf5ef2aSThomas Huth 4513fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4514fcf5ef2aSThomas Huth { 4515fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4516fcf5ef2aSThomas Huth } 4517fcf5ef2aSThomas Huth 4518fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4519fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4520fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4521fcf5ef2aSThomas Huth { \ 4522fcf5ef2aSThomas Huth uint8_t bitmask; \ 4523fcf5ef2aSThomas Huth int sh; \ 4524fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4525fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4526fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4527fcf5ef2aSThomas Huth if (sh > 0) \ 4528fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4529fcf5ef2aSThomas Huth else if (sh < 0) \ 4530fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4531fcf5ef2aSThomas Huth else \ 4532fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4533fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4534fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4535fcf5ef2aSThomas Huth if (sh > 0) \ 4536fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4537fcf5ef2aSThomas Huth else if (sh < 0) \ 4538fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4539fcf5ef2aSThomas Huth else \ 4540fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4541fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4542fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4543fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4544fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4545fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4546fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4547fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4548fcf5ef2aSThomas Huth } 4549fcf5ef2aSThomas Huth 4550fcf5ef2aSThomas Huth /* crand */ 4551fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4552fcf5ef2aSThomas Huth /* crandc */ 4553fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4554fcf5ef2aSThomas Huth /* creqv */ 4555fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4556fcf5ef2aSThomas Huth /* crnand */ 4557fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4558fcf5ef2aSThomas Huth /* crnor */ 4559fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4560fcf5ef2aSThomas Huth /* cror */ 4561fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4562fcf5ef2aSThomas Huth /* crorc */ 4563fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4564fcf5ef2aSThomas Huth /* crxor */ 4565fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4566fcf5ef2aSThomas Huth 4567fcf5ef2aSThomas Huth /* mcrf */ 4568fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4569fcf5ef2aSThomas Huth { 4570fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4571fcf5ef2aSThomas Huth } 4572fcf5ef2aSThomas Huth 4573fcf5ef2aSThomas Huth /*** System linkage ***/ 4574fcf5ef2aSThomas Huth 4575fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4576fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4577fcf5ef2aSThomas Huth { 4578fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4579fcf5ef2aSThomas Huth GEN_PRIV; 4580fcf5ef2aSThomas Huth #else 4581efe843d8SDavid Gibson /* 4582efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4583fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4584fcf5ef2aSThomas Huth */ 4585d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4586fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4587fcf5ef2aSThomas Huth return; 4588fcf5ef2aSThomas Huth } 4589fcf5ef2aSThomas Huth /* Restore CPU state */ 4590fcf5ef2aSThomas Huth CHK_SV; 4591f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45922c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4593fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 459459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4595fcf5ef2aSThomas Huth #endif 4596fcf5ef2aSThomas Huth } 4597fcf5ef2aSThomas Huth 4598fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4599fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4600fcf5ef2aSThomas Huth { 4601fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4602fcf5ef2aSThomas Huth GEN_PRIV; 4603fcf5ef2aSThomas Huth #else 4604fcf5ef2aSThomas Huth /* Restore CPU state */ 4605fcf5ef2aSThomas Huth CHK_SV; 4606f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46072c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4608fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 460959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4610fcf5ef2aSThomas Huth #endif 4611fcf5ef2aSThomas Huth } 4612fcf5ef2aSThomas Huth 46133c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46143c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 46153c89b8d6SNicholas Piggin { 46163c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 46173c89b8d6SNicholas Piggin GEN_PRIV; 46183c89b8d6SNicholas Piggin #else 46193c89b8d6SNicholas Piggin /* Restore CPU state */ 46203c89b8d6SNicholas Piggin CHK_SV; 4621f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46222c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 46233c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 462459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 46253c89b8d6SNicholas Piggin #endif 46263c89b8d6SNicholas Piggin } 46273c89b8d6SNicholas Piggin #endif 46283c89b8d6SNicholas Piggin 4629fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4630fcf5ef2aSThomas Huth { 4631fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4632fcf5ef2aSThomas Huth GEN_PRIV; 4633fcf5ef2aSThomas Huth #else 4634fcf5ef2aSThomas Huth /* Restore CPU state */ 4635fcf5ef2aSThomas Huth CHK_HV; 4636fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 463759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4638fcf5ef2aSThomas Huth #endif 4639fcf5ef2aSThomas Huth } 4640fcf5ef2aSThomas Huth #endif 4641fcf5ef2aSThomas Huth 4642fcf5ef2aSThomas Huth /* sc */ 4643fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4644fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4645fcf5ef2aSThomas Huth #else 4646fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 46473c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4648fcf5ef2aSThomas Huth #endif 4649fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4650fcf5ef2aSThomas Huth { 4651fcf5ef2aSThomas Huth uint32_t lev; 4652fcf5ef2aSThomas Huth 4653fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4654fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4655fcf5ef2aSThomas Huth } 4656fcf5ef2aSThomas Huth 46573c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 46583c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46593c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 46603c89b8d6SNicholas Piggin { 4661f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 46623c89b8d6SNicholas Piggin 4663f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 46642c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4665f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 46663c89b8d6SNicholas Piggin 46677a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 46683c89b8d6SNicholas Piggin } 46693c89b8d6SNicholas Piggin #endif 46703c89b8d6SNicholas Piggin #endif 46713c89b8d6SNicholas Piggin 4672fcf5ef2aSThomas Huth /*** Trap ***/ 4673fcf5ef2aSThomas Huth 4674fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4675fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4676fcf5ef2aSThomas Huth { 4677fcf5ef2aSThomas Huth /* Trap never */ 4678fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4679fcf5ef2aSThomas Huth return true; 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth /* Trap always */ 4682fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4683fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4684fcf5ef2aSThomas Huth return true; 4685fcf5ef2aSThomas Huth } 4686fcf5ef2aSThomas Huth return false; 4687fcf5ef2aSThomas Huth } 4688fcf5ef2aSThomas Huth 4689fcf5ef2aSThomas Huth /* tw */ 4690fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4691fcf5ef2aSThomas Huth { 4692fcf5ef2aSThomas Huth TCGv_i32 t0; 4693fcf5ef2aSThomas Huth 4694fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4695fcf5ef2aSThomas Huth return; 4696fcf5ef2aSThomas Huth } 4697fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4698fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4699fcf5ef2aSThomas Huth t0); 4700fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4701fcf5ef2aSThomas Huth } 4702fcf5ef2aSThomas Huth 4703fcf5ef2aSThomas Huth /* twi */ 4704fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4705fcf5ef2aSThomas Huth { 4706fcf5ef2aSThomas Huth TCGv t0; 4707fcf5ef2aSThomas Huth TCGv_i32 t1; 4708fcf5ef2aSThomas Huth 4709fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4710fcf5ef2aSThomas Huth return; 4711fcf5ef2aSThomas Huth } 4712fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4713fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4714fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4715fcf5ef2aSThomas Huth tcg_temp_free(t0); 4716fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4717fcf5ef2aSThomas Huth } 4718fcf5ef2aSThomas Huth 4719fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4720fcf5ef2aSThomas Huth /* td */ 4721fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4722fcf5ef2aSThomas Huth { 4723fcf5ef2aSThomas Huth TCGv_i32 t0; 4724fcf5ef2aSThomas Huth 4725fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4726fcf5ef2aSThomas Huth return; 4727fcf5ef2aSThomas Huth } 4728fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4729fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4730fcf5ef2aSThomas Huth t0); 4731fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4732fcf5ef2aSThomas Huth } 4733fcf5ef2aSThomas Huth 4734fcf5ef2aSThomas Huth /* tdi */ 4735fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4736fcf5ef2aSThomas Huth { 4737fcf5ef2aSThomas Huth TCGv t0; 4738fcf5ef2aSThomas Huth TCGv_i32 t1; 4739fcf5ef2aSThomas Huth 4740fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4741fcf5ef2aSThomas Huth return; 4742fcf5ef2aSThomas Huth } 4743fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4744fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4745fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4746fcf5ef2aSThomas Huth tcg_temp_free(t0); 4747fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4748fcf5ef2aSThomas Huth } 4749fcf5ef2aSThomas Huth #endif 4750fcf5ef2aSThomas Huth 4751fcf5ef2aSThomas Huth /*** Processor control ***/ 4752fcf5ef2aSThomas Huth 4753fcf5ef2aSThomas Huth /* mcrxr */ 4754fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4755fcf5ef2aSThomas Huth { 4756fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4757fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4758fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4759fcf5ef2aSThomas Huth 4760fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4761fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4762fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4763fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4764fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4765fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4766fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4767fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4768fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4769fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4770fcf5ef2aSThomas Huth 4771fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4772fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4773fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4774fcf5ef2aSThomas Huth } 4775fcf5ef2aSThomas Huth 4776b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4777b63d0434SNikunj A Dadhania /* mcrxrx */ 4778b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4779b63d0434SNikunj A Dadhania { 4780b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4781b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4782b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4783b63d0434SNikunj A Dadhania 4784b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4785b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4786b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4787b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4788b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4789b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4790b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4791b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4792b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4793b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4794b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4795b63d0434SNikunj A Dadhania } 4796b63d0434SNikunj A Dadhania #endif 4797b63d0434SNikunj A Dadhania 4798fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4799fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4800fcf5ef2aSThomas Huth { 4801fcf5ef2aSThomas Huth uint32_t crm, crn; 4802fcf5ef2aSThomas Huth 4803fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4804fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4805fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4806fcf5ef2aSThomas Huth crn = ctz32(crm); 4807fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4808fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4809fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4810fcf5ef2aSThomas Huth } 4811fcf5ef2aSThomas Huth } else { 4812fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4813fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4814fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4815fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4816fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4817fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4818fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4819fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4820fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4821fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4822fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4823fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4824fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4825fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4826fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4827fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4828fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4829fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4830fcf5ef2aSThomas Huth } 4831fcf5ef2aSThomas Huth } 4832fcf5ef2aSThomas Huth 4833fcf5ef2aSThomas Huth /* mfmsr */ 4834fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4835fcf5ef2aSThomas Huth { 4836fcf5ef2aSThomas Huth CHK_SV; 4837fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4838fcf5ef2aSThomas Huth } 4839fcf5ef2aSThomas Huth 4840fcf5ef2aSThomas Huth /* mfspr */ 4841fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4842fcf5ef2aSThomas Huth { 4843fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4844fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4845fcf5ef2aSThomas Huth 4846fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4847fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4848fcf5ef2aSThomas Huth #else 4849fcf5ef2aSThomas Huth if (ctx->pr) { 4850fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4851fcf5ef2aSThomas Huth } else if (ctx->hv) { 4852fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4853fcf5ef2aSThomas Huth } else { 4854fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4855fcf5ef2aSThomas Huth } 4856fcf5ef2aSThomas Huth #endif 4857fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4858fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4859fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4860fcf5ef2aSThomas Huth } else { 4861fcf5ef2aSThomas Huth /* Privilege exception */ 4862efe843d8SDavid Gibson /* 4863efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4864fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4865fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4866fcf5ef2aSThomas Huth */ 4867fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 486831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 486931085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48702c2bcb1bSRichard Henderson ctx->cia); 4871fcf5ef2aSThomas Huth } 4872fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4873fcf5ef2aSThomas Huth } 4874fcf5ef2aSThomas Huth } else { 4875fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4876fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4877fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4878fcf5ef2aSThomas Huth /* This is a nop */ 4879fcf5ef2aSThomas Huth return; 4880fcf5ef2aSThomas Huth } 4881fcf5ef2aSThomas Huth /* Not defined */ 488231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 488331085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 48842c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4885fcf5ef2aSThomas Huth 4886efe843d8SDavid Gibson /* 4887efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4888efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4889fcf5ef2aSThomas Huth */ 4890fcf5ef2aSThomas Huth if (sprn & 0x10) { 4891fcf5ef2aSThomas Huth if (ctx->pr) { 4892fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4893fcf5ef2aSThomas Huth } 4894fcf5ef2aSThomas Huth } else { 4895fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4896fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4897fcf5ef2aSThomas Huth } 4898fcf5ef2aSThomas Huth } 4899fcf5ef2aSThomas Huth } 4900fcf5ef2aSThomas Huth } 4901fcf5ef2aSThomas Huth 4902fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4903fcf5ef2aSThomas Huth { 4904fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4905fcf5ef2aSThomas Huth } 4906fcf5ef2aSThomas Huth 4907fcf5ef2aSThomas Huth /* mftb */ 4908fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4909fcf5ef2aSThomas Huth { 4910fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4911fcf5ef2aSThomas Huth } 4912fcf5ef2aSThomas Huth 4913fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4914fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4915fcf5ef2aSThomas Huth { 4916fcf5ef2aSThomas Huth uint32_t crm, crn; 4917fcf5ef2aSThomas Huth 4918fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4919fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4920fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4921fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4922fcf5ef2aSThomas Huth crn = ctz32(crm); 4923fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4924fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4925fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4926fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4927fcf5ef2aSThomas Huth } 4928fcf5ef2aSThomas Huth } else { 4929fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4930fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4931fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4932fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4933fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4934fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4935fcf5ef2aSThomas Huth } 4936fcf5ef2aSThomas Huth } 4937fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4938fcf5ef2aSThomas Huth } 4939fcf5ef2aSThomas Huth } 4940fcf5ef2aSThomas Huth 4941fcf5ef2aSThomas Huth /* mtmsr */ 4942fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4943fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4944fcf5ef2aSThomas Huth { 4945caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4946caf590ddSNicholas Piggin gen_invalid(ctx); 4947caf590ddSNicholas Piggin return; 4948caf590ddSNicholas Piggin } 4949caf590ddSNicholas Piggin 4950fcf5ef2aSThomas Huth CHK_SV; 4951fcf5ef2aSThomas Huth 4952fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49536fa5726bSMatheus Ferst TCGv t0, t1; 49546fa5726bSMatheus Ferst target_ulong mask; 49556fa5726bSMatheus Ferst 49566fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49576fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49586fa5726bSMatheus Ferst 4959f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49606fa5726bSMatheus Ferst 4961fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49625ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49636fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4964fcf5ef2aSThomas Huth } else { 49656fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 49666fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 49676fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4968efe843d8SDavid Gibson /* 4969efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4970efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4971efe843d8SDavid Gibson * ppc_store_msr 4972fcf5ef2aSThomas Huth */ 4973b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4974fcf5ef2aSThomas Huth } 49756fa5726bSMatheus Ferst 49766fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 49776fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 49786fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 49796fa5726bSMatheus Ferst 49806fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 49816fa5726bSMatheus Ferst 49825ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4983d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 49846fa5726bSMatheus Ferst 49856fa5726bSMatheus Ferst tcg_temp_free(t0); 49866fa5726bSMatheus Ferst tcg_temp_free(t1); 4987fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4988fcf5ef2aSThomas Huth } 4989fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4990fcf5ef2aSThomas Huth 4991fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4992fcf5ef2aSThomas Huth { 4993fcf5ef2aSThomas Huth CHK_SV; 4994fcf5ef2aSThomas Huth 4995fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49966fa5726bSMatheus Ferst TCGv t0, t1; 49976fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 49986fa5726bSMatheus Ferst 49996fa5726bSMatheus Ferst t0 = tcg_temp_new(); 50006fa5726bSMatheus Ferst t1 = tcg_temp_new(); 50016fa5726bSMatheus Ferst 5002f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5003fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 50045ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 50056fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 5006fcf5ef2aSThomas Huth } else { 50076fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 50086fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 5009fcf5ef2aSThomas Huth 5010efe843d8SDavid Gibson /* 5011efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5012efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5013efe843d8SDavid Gibson * ppc_store_msr 5014fcf5ef2aSThomas Huth */ 5015b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5016fcf5ef2aSThomas Huth } 50176fa5726bSMatheus Ferst 50186fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 50196fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 50206fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 50216fa5726bSMatheus Ferst 50226fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 50236fa5726bSMatheus Ferst 50245ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5025d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 50266fa5726bSMatheus Ferst 50276fa5726bSMatheus Ferst tcg_temp_free(t0); 50286fa5726bSMatheus Ferst tcg_temp_free(t1); 5029fcf5ef2aSThomas Huth #endif 5030fcf5ef2aSThomas Huth } 5031fcf5ef2aSThomas Huth 5032fcf5ef2aSThomas Huth /* mtspr */ 5033fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5034fcf5ef2aSThomas Huth { 5035fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5036fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5037fcf5ef2aSThomas Huth 5038fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5039fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5040fcf5ef2aSThomas Huth #else 5041fcf5ef2aSThomas Huth if (ctx->pr) { 5042fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5043fcf5ef2aSThomas Huth } else if (ctx->hv) { 5044fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5045fcf5ef2aSThomas Huth } else { 5046fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5047fcf5ef2aSThomas Huth } 5048fcf5ef2aSThomas Huth #endif 5049fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5050fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5051fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5052fcf5ef2aSThomas Huth } else { 5053fcf5ef2aSThomas Huth /* Privilege exception */ 505431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 505531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 50562c2bcb1bSRichard Henderson ctx->cia); 5057fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5058fcf5ef2aSThomas Huth } 5059fcf5ef2aSThomas Huth } else { 5060fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5061fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5062fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5063fcf5ef2aSThomas Huth /* This is a nop */ 5064fcf5ef2aSThomas Huth return; 5065fcf5ef2aSThomas Huth } 5066fcf5ef2aSThomas Huth 5067fcf5ef2aSThomas Huth /* Not defined */ 506831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 506931085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 50702c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5071fcf5ef2aSThomas Huth 5072fcf5ef2aSThomas Huth 5073efe843d8SDavid Gibson /* 5074efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5075efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5076fcf5ef2aSThomas Huth */ 5077fcf5ef2aSThomas Huth if (sprn & 0x10) { 5078fcf5ef2aSThomas Huth if (ctx->pr) { 5079fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5080fcf5ef2aSThomas Huth } 5081fcf5ef2aSThomas Huth } else { 5082fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5083fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5084fcf5ef2aSThomas Huth } 5085fcf5ef2aSThomas Huth } 5086fcf5ef2aSThomas Huth } 5087fcf5ef2aSThomas Huth } 5088fcf5ef2aSThomas Huth 5089fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5090fcf5ef2aSThomas Huth /* setb */ 5091fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5092fcf5ef2aSThomas Huth { 5093fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 50946f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 50956f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5096fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5097fcf5ef2aSThomas Huth 5098fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5099fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5100fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5101fcf5ef2aSThomas Huth 5102fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5103fcf5ef2aSThomas Huth } 5104fcf5ef2aSThomas Huth #endif 5105fcf5ef2aSThomas Huth 5106fcf5ef2aSThomas Huth /*** Cache management ***/ 5107fcf5ef2aSThomas Huth 5108fcf5ef2aSThomas Huth /* dcbf */ 5109fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5110fcf5ef2aSThomas Huth { 5111fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5112fcf5ef2aSThomas Huth TCGv t0; 5113fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5114fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5115fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5116fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5117fcf5ef2aSThomas Huth tcg_temp_free(t0); 5118fcf5ef2aSThomas Huth } 5119fcf5ef2aSThomas Huth 512050728199SRoman Kapl /* dcbfep (external PID dcbf) */ 512150728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 512250728199SRoman Kapl { 512350728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 512450728199SRoman Kapl TCGv t0; 512550728199SRoman Kapl CHK_SV; 512650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 512750728199SRoman Kapl t0 = tcg_temp_new(); 512850728199SRoman Kapl gen_addr_reg_index(ctx, t0); 512950728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 513050728199SRoman Kapl tcg_temp_free(t0); 513150728199SRoman Kapl } 513250728199SRoman Kapl 5133fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5134fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5135fcf5ef2aSThomas Huth { 5136fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5137fcf5ef2aSThomas Huth GEN_PRIV; 5138fcf5ef2aSThomas Huth #else 5139fcf5ef2aSThomas Huth TCGv EA, val; 5140fcf5ef2aSThomas Huth 5141fcf5ef2aSThomas Huth CHK_SV; 5142fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5143fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5144fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5145fcf5ef2aSThomas Huth val = tcg_temp_new(); 5146fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5147fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5148fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5149fcf5ef2aSThomas Huth tcg_temp_free(val); 5150fcf5ef2aSThomas Huth tcg_temp_free(EA); 5151fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5152fcf5ef2aSThomas Huth } 5153fcf5ef2aSThomas Huth 5154fcf5ef2aSThomas Huth /* dcdst */ 5155fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5156fcf5ef2aSThomas Huth { 5157fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5158fcf5ef2aSThomas Huth TCGv t0; 5159fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5160fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5161fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5162fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5163fcf5ef2aSThomas Huth tcg_temp_free(t0); 5164fcf5ef2aSThomas Huth } 5165fcf5ef2aSThomas Huth 516650728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 516750728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 516850728199SRoman Kapl { 516950728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 517050728199SRoman Kapl TCGv t0; 517150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 517250728199SRoman Kapl t0 = tcg_temp_new(); 517350728199SRoman Kapl gen_addr_reg_index(ctx, t0); 517450728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 517550728199SRoman Kapl tcg_temp_free(t0); 517650728199SRoman Kapl } 517750728199SRoman Kapl 5178fcf5ef2aSThomas Huth /* dcbt */ 5179fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5180fcf5ef2aSThomas Huth { 5181efe843d8SDavid Gibson /* 5182efe843d8SDavid Gibson * interpreted as no-op 5183efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5184efe843d8SDavid Gibson * does not generate any exception 5185fcf5ef2aSThomas Huth */ 5186fcf5ef2aSThomas Huth } 5187fcf5ef2aSThomas Huth 518850728199SRoman Kapl /* dcbtep */ 518950728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 519050728199SRoman Kapl { 5191efe843d8SDavid Gibson /* 5192efe843d8SDavid Gibson * interpreted as no-op 5193efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5194efe843d8SDavid Gibson * does not generate any exception 519550728199SRoman Kapl */ 519650728199SRoman Kapl } 519750728199SRoman Kapl 5198fcf5ef2aSThomas Huth /* dcbtst */ 5199fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5200fcf5ef2aSThomas Huth { 5201efe843d8SDavid Gibson /* 5202efe843d8SDavid Gibson * interpreted as no-op 5203efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5204efe843d8SDavid Gibson * does not generate any exception 5205fcf5ef2aSThomas Huth */ 5206fcf5ef2aSThomas Huth } 5207fcf5ef2aSThomas Huth 520850728199SRoman Kapl /* dcbtstep */ 520950728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 521050728199SRoman Kapl { 5211efe843d8SDavid Gibson /* 5212efe843d8SDavid Gibson * interpreted as no-op 5213efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5214efe843d8SDavid Gibson * does not generate any exception 521550728199SRoman Kapl */ 521650728199SRoman Kapl } 521750728199SRoman Kapl 5218fcf5ef2aSThomas Huth /* dcbtls */ 5219fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5220fcf5ef2aSThomas Huth { 5221fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5222fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5223fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5224fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5225fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5226fcf5ef2aSThomas Huth tcg_temp_free(t0); 5227fcf5ef2aSThomas Huth } 5228fcf5ef2aSThomas Huth 5229fcf5ef2aSThomas Huth /* dcbz */ 5230fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5231fcf5ef2aSThomas Huth { 5232fcf5ef2aSThomas Huth TCGv tcgv_addr; 5233fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5234fcf5ef2aSThomas Huth 5235fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5236fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5237fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5238fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5239fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5240fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5241fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5242fcf5ef2aSThomas Huth } 5243fcf5ef2aSThomas Huth 524450728199SRoman Kapl /* dcbzep */ 524550728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 524650728199SRoman Kapl { 524750728199SRoman Kapl TCGv tcgv_addr; 524850728199SRoman Kapl TCGv_i32 tcgv_op; 524950728199SRoman Kapl 525050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 525150728199SRoman Kapl tcgv_addr = tcg_temp_new(); 525250728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 525350728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 525450728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 525550728199SRoman Kapl tcg_temp_free(tcgv_addr); 525650728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 525750728199SRoman Kapl } 525850728199SRoman Kapl 5259fcf5ef2aSThomas Huth /* dst / dstt */ 5260fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5261fcf5ef2aSThomas Huth { 5262fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5263fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5264fcf5ef2aSThomas Huth } else { 5265fcf5ef2aSThomas Huth /* interpreted as no-op */ 5266fcf5ef2aSThomas Huth } 5267fcf5ef2aSThomas Huth } 5268fcf5ef2aSThomas Huth 5269fcf5ef2aSThomas Huth /* dstst /dststt */ 5270fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5271fcf5ef2aSThomas Huth { 5272fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5273fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5274fcf5ef2aSThomas Huth } else { 5275fcf5ef2aSThomas Huth /* interpreted as no-op */ 5276fcf5ef2aSThomas Huth } 5277fcf5ef2aSThomas Huth 5278fcf5ef2aSThomas Huth } 5279fcf5ef2aSThomas Huth 5280fcf5ef2aSThomas Huth /* dss / dssall */ 5281fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5282fcf5ef2aSThomas Huth { 5283fcf5ef2aSThomas Huth /* interpreted as no-op */ 5284fcf5ef2aSThomas Huth } 5285fcf5ef2aSThomas Huth 5286fcf5ef2aSThomas Huth /* icbi */ 5287fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5288fcf5ef2aSThomas Huth { 5289fcf5ef2aSThomas Huth TCGv t0; 5290fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5291fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5292fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5293fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5294fcf5ef2aSThomas Huth tcg_temp_free(t0); 5295fcf5ef2aSThomas Huth } 5296fcf5ef2aSThomas Huth 529750728199SRoman Kapl /* icbiep */ 529850728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 529950728199SRoman Kapl { 530050728199SRoman Kapl TCGv t0; 530150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 530250728199SRoman Kapl t0 = tcg_temp_new(); 530350728199SRoman Kapl gen_addr_reg_index(ctx, t0); 530450728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 530550728199SRoman Kapl tcg_temp_free(t0); 530650728199SRoman Kapl } 530750728199SRoman Kapl 5308fcf5ef2aSThomas Huth /* Optional: */ 5309fcf5ef2aSThomas Huth /* dcba */ 5310fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5311fcf5ef2aSThomas Huth { 5312efe843d8SDavid Gibson /* 5313efe843d8SDavid Gibson * interpreted as no-op 5314efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5315fcf5ef2aSThomas Huth * but does not generate any exception 5316fcf5ef2aSThomas Huth */ 5317fcf5ef2aSThomas Huth } 5318fcf5ef2aSThomas Huth 5319fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5320fcf5ef2aSThomas Huth /* Supervisor only: */ 5321fcf5ef2aSThomas Huth 5322fcf5ef2aSThomas Huth /* mfsr */ 5323fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5324fcf5ef2aSThomas Huth { 5325fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5326fcf5ef2aSThomas Huth GEN_PRIV; 5327fcf5ef2aSThomas Huth #else 5328fcf5ef2aSThomas Huth TCGv t0; 5329fcf5ef2aSThomas Huth 5330fcf5ef2aSThomas Huth CHK_SV; 5331fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5332fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5333fcf5ef2aSThomas Huth tcg_temp_free(t0); 5334fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5335fcf5ef2aSThomas Huth } 5336fcf5ef2aSThomas Huth 5337fcf5ef2aSThomas Huth /* mfsrin */ 5338fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5339fcf5ef2aSThomas Huth { 5340fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5341fcf5ef2aSThomas Huth GEN_PRIV; 5342fcf5ef2aSThomas Huth #else 5343fcf5ef2aSThomas Huth TCGv t0; 5344fcf5ef2aSThomas Huth 5345fcf5ef2aSThomas Huth CHK_SV; 5346fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5347e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5348fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5349fcf5ef2aSThomas Huth tcg_temp_free(t0); 5350fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5351fcf5ef2aSThomas Huth } 5352fcf5ef2aSThomas Huth 5353fcf5ef2aSThomas Huth /* mtsr */ 5354fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5355fcf5ef2aSThomas Huth { 5356fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5357fcf5ef2aSThomas Huth GEN_PRIV; 5358fcf5ef2aSThomas Huth #else 5359fcf5ef2aSThomas Huth TCGv t0; 5360fcf5ef2aSThomas Huth 5361fcf5ef2aSThomas Huth CHK_SV; 5362fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5363fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5364fcf5ef2aSThomas Huth tcg_temp_free(t0); 5365fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5366fcf5ef2aSThomas Huth } 5367fcf5ef2aSThomas Huth 5368fcf5ef2aSThomas Huth /* mtsrin */ 5369fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5370fcf5ef2aSThomas Huth { 5371fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5372fcf5ef2aSThomas Huth GEN_PRIV; 5373fcf5ef2aSThomas Huth #else 5374fcf5ef2aSThomas Huth TCGv t0; 5375fcf5ef2aSThomas Huth CHK_SV; 5376fcf5ef2aSThomas Huth 5377fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5378e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5379fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5380fcf5ef2aSThomas Huth tcg_temp_free(t0); 5381fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5382fcf5ef2aSThomas Huth } 5383fcf5ef2aSThomas Huth 5384fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5385fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5386fcf5ef2aSThomas Huth 5387fcf5ef2aSThomas Huth /* mfsr */ 5388fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5389fcf5ef2aSThomas Huth { 5390fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5391fcf5ef2aSThomas Huth GEN_PRIV; 5392fcf5ef2aSThomas Huth #else 5393fcf5ef2aSThomas Huth TCGv t0; 5394fcf5ef2aSThomas Huth 5395fcf5ef2aSThomas Huth CHK_SV; 5396fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5397fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5398fcf5ef2aSThomas Huth tcg_temp_free(t0); 5399fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5400fcf5ef2aSThomas Huth } 5401fcf5ef2aSThomas Huth 5402fcf5ef2aSThomas Huth /* mfsrin */ 5403fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5404fcf5ef2aSThomas Huth { 5405fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5406fcf5ef2aSThomas Huth GEN_PRIV; 5407fcf5ef2aSThomas Huth #else 5408fcf5ef2aSThomas Huth TCGv t0; 5409fcf5ef2aSThomas Huth 5410fcf5ef2aSThomas Huth CHK_SV; 5411fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5412e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5413fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5414fcf5ef2aSThomas Huth tcg_temp_free(t0); 5415fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5416fcf5ef2aSThomas Huth } 5417fcf5ef2aSThomas Huth 5418fcf5ef2aSThomas Huth /* mtsr */ 5419fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5420fcf5ef2aSThomas Huth { 5421fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5422fcf5ef2aSThomas Huth GEN_PRIV; 5423fcf5ef2aSThomas Huth #else 5424fcf5ef2aSThomas Huth TCGv t0; 5425fcf5ef2aSThomas Huth 5426fcf5ef2aSThomas Huth CHK_SV; 5427fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5428fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5429fcf5ef2aSThomas Huth tcg_temp_free(t0); 5430fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5431fcf5ef2aSThomas Huth } 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth /* mtsrin */ 5434fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5435fcf5ef2aSThomas Huth { 5436fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5437fcf5ef2aSThomas Huth GEN_PRIV; 5438fcf5ef2aSThomas Huth #else 5439fcf5ef2aSThomas Huth TCGv t0; 5440fcf5ef2aSThomas Huth 5441fcf5ef2aSThomas Huth CHK_SV; 5442fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5443e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5444fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5445fcf5ef2aSThomas Huth tcg_temp_free(t0); 5446fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5447fcf5ef2aSThomas Huth } 5448fcf5ef2aSThomas Huth 5449fcf5ef2aSThomas Huth /* slbmte */ 5450fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5451fcf5ef2aSThomas Huth { 5452fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5453fcf5ef2aSThomas Huth GEN_PRIV; 5454fcf5ef2aSThomas Huth #else 5455fcf5ef2aSThomas Huth CHK_SV; 5456fcf5ef2aSThomas Huth 5457fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5458fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5459fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5460fcf5ef2aSThomas Huth } 5461fcf5ef2aSThomas Huth 5462fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5463fcf5ef2aSThomas Huth { 5464fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5465fcf5ef2aSThomas Huth GEN_PRIV; 5466fcf5ef2aSThomas Huth #else 5467fcf5ef2aSThomas Huth CHK_SV; 5468fcf5ef2aSThomas Huth 5469fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5470fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5471fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5472fcf5ef2aSThomas Huth } 5473fcf5ef2aSThomas Huth 5474fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5475fcf5ef2aSThomas Huth { 5476fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5477fcf5ef2aSThomas Huth GEN_PRIV; 5478fcf5ef2aSThomas Huth #else 5479fcf5ef2aSThomas Huth CHK_SV; 5480fcf5ef2aSThomas Huth 5481fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5482fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5483fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5484fcf5ef2aSThomas Huth } 5485fcf5ef2aSThomas Huth 5486fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5487fcf5ef2aSThomas Huth { 5488fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5489fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5490fcf5ef2aSThomas Huth #else 5491fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5492fcf5ef2aSThomas Huth 5493fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5494fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5495fcf5ef2aSThomas Huth return; 5496fcf5ef2aSThomas Huth } 5497fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5498fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5499fcf5ef2aSThomas Huth l1 = gen_new_label(); 5500fcf5ef2aSThomas Huth l2 = gen_new_label(); 5501fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5502fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5503efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5504fcf5ef2aSThomas Huth tcg_gen_br(l2); 5505fcf5ef2aSThomas Huth gen_set_label(l1); 5506fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5507fcf5ef2aSThomas Huth gen_set_label(l2); 5508fcf5ef2aSThomas Huth #endif 5509fcf5ef2aSThomas Huth } 5510fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5511fcf5ef2aSThomas Huth 5512fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5513fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5514fcf5ef2aSThomas Huth 5515fcf5ef2aSThomas Huth /* tlbia */ 5516fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5517fcf5ef2aSThomas Huth { 5518fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5519fcf5ef2aSThomas Huth GEN_PRIV; 5520fcf5ef2aSThomas Huth #else 5521fcf5ef2aSThomas Huth CHK_HV; 5522fcf5ef2aSThomas Huth 5523fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5524fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5525fcf5ef2aSThomas Huth } 5526fcf5ef2aSThomas Huth 5527fcf5ef2aSThomas Huth /* tlbiel */ 5528fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5529fcf5ef2aSThomas Huth { 5530fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5531fcf5ef2aSThomas Huth GEN_PRIV; 5532fcf5ef2aSThomas Huth #else 553392fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 553492fb92d3SMatheus Ferst 553592fb92d3SMatheus Ferst if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) { 553692fb92d3SMatheus Ferst /* 553792fb92d3SMatheus Ferst * tlbiel is privileged except when PSR=0 and HR=1, making it 553892fb92d3SMatheus Ferst * hypervisor privileged. 553992fb92d3SMatheus Ferst */ 554092fb92d3SMatheus Ferst GEN_PRIV; 554192fb92d3SMatheus Ferst } 5542fcf5ef2aSThomas Huth 5543fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5544fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5545fcf5ef2aSThomas Huth } 5546fcf5ef2aSThomas Huth 5547fcf5ef2aSThomas Huth /* tlbie */ 5548fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5549fcf5ef2aSThomas Huth { 5550fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5551fcf5ef2aSThomas Huth GEN_PRIV; 5552fcf5ef2aSThomas Huth #else 555392fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 5554fcf5ef2aSThomas Huth TCGv_i32 t1; 5555c6fd28fdSSuraj Jitindar Singh 555692fb92d3SMatheus Ferst if (ctx->pr) { 555792fb92d3SMatheus Ferst /* tlbie is privileged... */ 555892fb92d3SMatheus Ferst GEN_PRIV; 555992fb92d3SMatheus Ferst } else if (!ctx->hv) { 556092fb92d3SMatheus Ferst if (!ctx->gtse || (!psr && ctx->hr)) { 556192fb92d3SMatheus Ferst /* 556292fb92d3SMatheus Ferst * ... except when GTSE=0 or when PSR=0 and HR=1, making it 556392fb92d3SMatheus Ferst * hypervisor privileged. 556492fb92d3SMatheus Ferst */ 556592fb92d3SMatheus Ferst GEN_PRIV; 556692fb92d3SMatheus Ferst } 5567c6fd28fdSSuraj Jitindar Singh } 5568fcf5ef2aSThomas Huth 5569fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5570fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5571fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5572fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5573fcf5ef2aSThomas Huth tcg_temp_free(t0); 5574fcf5ef2aSThomas Huth } else { 5575fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5576fcf5ef2aSThomas Huth } 5577fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5578fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5579fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5580fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5581fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5582fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5583fcf5ef2aSThomas Huth } 5584fcf5ef2aSThomas Huth 5585fcf5ef2aSThomas Huth /* tlbsync */ 5586fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5587fcf5ef2aSThomas Huth { 5588fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5589fcf5ef2aSThomas Huth GEN_PRIV; 5590fcf5ef2aSThomas Huth #else 559191c60f12SCédric Le Goater 559291c60f12SCédric Le Goater if (ctx->gtse) { 559391c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 559491c60f12SCédric Le Goater } else { 559591c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 559691c60f12SCédric Le Goater } 5597fcf5ef2aSThomas Huth 5598fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5599fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5600fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5601fcf5ef2aSThomas Huth } 5602fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5603fcf5ef2aSThomas Huth } 5604fcf5ef2aSThomas Huth 5605fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5606fcf5ef2aSThomas Huth /* slbia */ 5607fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5608fcf5ef2aSThomas Huth { 5609fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5610fcf5ef2aSThomas Huth GEN_PRIV; 5611fcf5ef2aSThomas Huth #else 56120418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 56130418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 56140418bf78SNicholas Piggin 5615fcf5ef2aSThomas Huth CHK_SV; 5616fcf5ef2aSThomas Huth 56170418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 56183119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5619fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5620fcf5ef2aSThomas Huth } 5621fcf5ef2aSThomas Huth 5622fcf5ef2aSThomas Huth /* slbie */ 5623fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5624fcf5ef2aSThomas Huth { 5625fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5626fcf5ef2aSThomas Huth GEN_PRIV; 5627fcf5ef2aSThomas Huth #else 5628fcf5ef2aSThomas Huth CHK_SV; 5629fcf5ef2aSThomas Huth 5630fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5631fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5632fcf5ef2aSThomas Huth } 5633a63f1dfcSNikunj A Dadhania 5634a63f1dfcSNikunj A Dadhania /* slbieg */ 5635a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5636a63f1dfcSNikunj A Dadhania { 5637a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5638a63f1dfcSNikunj A Dadhania GEN_PRIV; 5639a63f1dfcSNikunj A Dadhania #else 5640a63f1dfcSNikunj A Dadhania CHK_SV; 5641a63f1dfcSNikunj A Dadhania 5642a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5643a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5644a63f1dfcSNikunj A Dadhania } 5645a63f1dfcSNikunj A Dadhania 564662d897caSNikunj A Dadhania /* slbsync */ 564762d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 564862d897caSNikunj A Dadhania { 564962d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 565062d897caSNikunj A Dadhania GEN_PRIV; 565162d897caSNikunj A Dadhania #else 565262d897caSNikunj A Dadhania CHK_SV; 565362d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 565462d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 565562d897caSNikunj A Dadhania } 565662d897caSNikunj A Dadhania 5657fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5658fcf5ef2aSThomas Huth 5659fcf5ef2aSThomas Huth /*** External control ***/ 5660fcf5ef2aSThomas Huth /* Optional: */ 5661fcf5ef2aSThomas Huth 5662fcf5ef2aSThomas Huth /* eciwx */ 5663fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5664fcf5ef2aSThomas Huth { 5665fcf5ef2aSThomas Huth TCGv t0; 5666fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5667fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5668fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5669fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5670c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5671c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5672fcf5ef2aSThomas Huth tcg_temp_free(t0); 5673fcf5ef2aSThomas Huth } 5674fcf5ef2aSThomas Huth 5675fcf5ef2aSThomas Huth /* ecowx */ 5676fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5677fcf5ef2aSThomas Huth { 5678fcf5ef2aSThomas Huth TCGv t0; 5679fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5680fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5681fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5682fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5683c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5684c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5685fcf5ef2aSThomas Huth tcg_temp_free(t0); 5686fcf5ef2aSThomas Huth } 5687fcf5ef2aSThomas Huth 5688fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5689fcf5ef2aSThomas Huth 5690fcf5ef2aSThomas Huth /* abs - abs. */ 5691fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5692fcf5ef2aSThomas Huth { 5693fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5694fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5695fe21b785SRichard Henderson 5696fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5697efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5698fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5699fcf5ef2aSThomas Huth } 5700efe843d8SDavid Gibson } 5701fcf5ef2aSThomas Huth 5702fcf5ef2aSThomas Huth /* abso - abso. */ 5703fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5704fcf5ef2aSThomas Huth { 5705fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5706fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5707fe21b785SRichard Henderson 5708fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5709fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5710fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5711efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5712fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5713fcf5ef2aSThomas Huth } 5714efe843d8SDavid Gibson } 5715fcf5ef2aSThomas Huth 5716fcf5ef2aSThomas Huth /* clcs */ 5717fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5718fcf5ef2aSThomas Huth { 5719fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5720fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5721fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5722fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5723fcf5ef2aSThomas Huth } 5724fcf5ef2aSThomas Huth 5725fcf5ef2aSThomas Huth /* div - div. */ 5726fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5727fcf5ef2aSThomas Huth { 5728fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5729fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5730efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5731fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5732fcf5ef2aSThomas Huth } 5733efe843d8SDavid Gibson } 5734fcf5ef2aSThomas Huth 5735fcf5ef2aSThomas Huth /* divo - divo. */ 5736fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5737fcf5ef2aSThomas Huth { 5738fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5739fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5740efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5741fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5742fcf5ef2aSThomas Huth } 5743efe843d8SDavid Gibson } 5744fcf5ef2aSThomas Huth 5745fcf5ef2aSThomas Huth /* divs - divs. */ 5746fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5747fcf5ef2aSThomas Huth { 5748fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5749fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5750efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5751fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5752fcf5ef2aSThomas Huth } 5753efe843d8SDavid Gibson } 5754fcf5ef2aSThomas Huth 5755fcf5ef2aSThomas Huth /* divso - divso. */ 5756fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5757fcf5ef2aSThomas Huth { 5758fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5759fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5760efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5761fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5762fcf5ef2aSThomas Huth } 5763efe843d8SDavid Gibson } 5764fcf5ef2aSThomas Huth 5765fcf5ef2aSThomas Huth /* doz - doz. */ 5766fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5767fcf5ef2aSThomas Huth { 5768fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5769fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5770efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5771efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5772efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5773efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5774fcf5ef2aSThomas Huth tcg_gen_br(l2); 5775fcf5ef2aSThomas Huth gen_set_label(l1); 5776fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5777fcf5ef2aSThomas Huth gen_set_label(l2); 5778efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5779fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5780fcf5ef2aSThomas Huth } 5781efe843d8SDavid Gibson } 5782fcf5ef2aSThomas Huth 5783fcf5ef2aSThomas Huth /* dozo - dozo. */ 5784fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5785fcf5ef2aSThomas Huth { 5786fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5787fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5788fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5789fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5790fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5791fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5792fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5793efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5794efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5795fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5796fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5797fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5798fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5799fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5800fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5801fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5802fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5803fcf5ef2aSThomas Huth tcg_gen_br(l2); 5804fcf5ef2aSThomas Huth gen_set_label(l1); 5805fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5806fcf5ef2aSThomas Huth gen_set_label(l2); 5807fcf5ef2aSThomas Huth tcg_temp_free(t0); 5808fcf5ef2aSThomas Huth tcg_temp_free(t1); 5809fcf5ef2aSThomas Huth tcg_temp_free(t2); 5810efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5811fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5812fcf5ef2aSThomas Huth } 5813efe843d8SDavid Gibson } 5814fcf5ef2aSThomas Huth 5815fcf5ef2aSThomas Huth /* dozi */ 5816fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5817fcf5ef2aSThomas Huth { 5818fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5819fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5820fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5821fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5822fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5823fcf5ef2aSThomas Huth tcg_gen_br(l2); 5824fcf5ef2aSThomas Huth gen_set_label(l1); 5825fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5826fcf5ef2aSThomas Huth gen_set_label(l2); 5827efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5828fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5829fcf5ef2aSThomas Huth } 5830efe843d8SDavid Gibson } 5831fcf5ef2aSThomas Huth 5832fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5833fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5834fcf5ef2aSThomas Huth { 5835fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5836fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5837fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5838fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5839fcf5ef2aSThomas Huth 5840fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5841fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5842fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5843fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5844fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5845fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5846fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5847efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5848fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5849efe843d8SDavid Gibson } 5850fcf5ef2aSThomas Huth tcg_temp_free(t0); 5851fcf5ef2aSThomas Huth } 5852fcf5ef2aSThomas Huth 5853fcf5ef2aSThomas Huth /* maskg - maskg. */ 5854fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5855fcf5ef2aSThomas Huth { 5856fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5857fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5858fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5859fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5860fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5861fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5862fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5863fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5864fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5865fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5866fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5867fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5868fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5869fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5870fcf5ef2aSThomas Huth gen_set_label(l1); 5871fcf5ef2aSThomas Huth tcg_temp_free(t0); 5872fcf5ef2aSThomas Huth tcg_temp_free(t1); 5873fcf5ef2aSThomas Huth tcg_temp_free(t2); 5874fcf5ef2aSThomas Huth tcg_temp_free(t3); 5875efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5876fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5877fcf5ef2aSThomas Huth } 5878efe843d8SDavid Gibson } 5879fcf5ef2aSThomas Huth 5880fcf5ef2aSThomas Huth /* maskir - maskir. */ 5881fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5882fcf5ef2aSThomas Huth { 5883fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5884fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5885fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5886fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5887fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5888fcf5ef2aSThomas Huth tcg_temp_free(t0); 5889fcf5ef2aSThomas Huth tcg_temp_free(t1); 5890efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5891fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5892fcf5ef2aSThomas Huth } 5893efe843d8SDavid Gibson } 5894fcf5ef2aSThomas Huth 5895fcf5ef2aSThomas Huth /* mul - mul. */ 5896fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5897fcf5ef2aSThomas Huth { 5898fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5899fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5900fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5901fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5902fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5903fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5904fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5905fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5906fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5907fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5908fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5909fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5910fcf5ef2aSThomas Huth tcg_temp_free(t2); 5911efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5912fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5913fcf5ef2aSThomas Huth } 5914efe843d8SDavid Gibson } 5915fcf5ef2aSThomas Huth 5916fcf5ef2aSThomas Huth /* mulo - mulo. */ 5917fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5918fcf5ef2aSThomas Huth { 5919fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5920fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5921fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5922fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5923fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5924fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5925fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5926fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5927fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5928fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5929fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5930fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5931fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5932fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5933fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5934fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5935fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5936fcf5ef2aSThomas Huth gen_set_label(l1); 5937fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5938fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5939fcf5ef2aSThomas Huth tcg_temp_free(t2); 5940efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5941fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5942fcf5ef2aSThomas Huth } 5943efe843d8SDavid Gibson } 5944fcf5ef2aSThomas Huth 5945fcf5ef2aSThomas Huth /* nabs - nabs. */ 5946fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5947fcf5ef2aSThomas Huth { 5948fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5949fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5950fe21b785SRichard Henderson 5951fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5952fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5953efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5954fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5955fcf5ef2aSThomas Huth } 5956efe843d8SDavid Gibson } 5957fcf5ef2aSThomas Huth 5958fcf5ef2aSThomas Huth /* nabso - nabso. */ 5959fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5960fcf5ef2aSThomas Huth { 5961fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5962fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5963fe21b785SRichard Henderson 5964fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5965fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5966fcf5ef2aSThomas Huth /* nabs never overflows */ 5967fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5968efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5969fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5970fcf5ef2aSThomas Huth } 5971efe843d8SDavid Gibson } 5972fcf5ef2aSThomas Huth 5973fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5974fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5975fcf5ef2aSThomas Huth { 5976fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5977fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5978fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5979fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5980fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5981fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5982efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5983efe843d8SDavid Gibson ~MASK(mb, me)); 5984fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5985fcf5ef2aSThomas Huth tcg_temp_free(t0); 5986efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5987fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5988fcf5ef2aSThomas Huth } 5989efe843d8SDavid Gibson } 5990fcf5ef2aSThomas Huth 5991fcf5ef2aSThomas Huth /* rrib - rrib. */ 5992fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5993fcf5ef2aSThomas Huth { 5994fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5995fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5996fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5997fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5998fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5999fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6000fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6001fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6002fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6003fcf5ef2aSThomas Huth tcg_temp_free(t0); 6004fcf5ef2aSThomas Huth tcg_temp_free(t1); 6005efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6006fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6007fcf5ef2aSThomas Huth } 6008efe843d8SDavid Gibson } 6009fcf5ef2aSThomas Huth 6010fcf5ef2aSThomas Huth /* sle - sle. */ 6011fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6012fcf5ef2aSThomas Huth { 6013fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6014fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6015fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6016fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6017fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6018fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6019fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6020fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6021fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6022fcf5ef2aSThomas Huth tcg_temp_free(t0); 6023fcf5ef2aSThomas Huth tcg_temp_free(t1); 6024efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6025fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6026fcf5ef2aSThomas Huth } 6027efe843d8SDavid Gibson } 6028fcf5ef2aSThomas Huth 6029fcf5ef2aSThomas Huth /* sleq - sleq. */ 6030fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6031fcf5ef2aSThomas Huth { 6032fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6033fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6034fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6035fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6036fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6037fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6038fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6039fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6040fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6041fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6042fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6043fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6044fcf5ef2aSThomas Huth tcg_temp_free(t0); 6045fcf5ef2aSThomas Huth tcg_temp_free(t1); 6046fcf5ef2aSThomas Huth tcg_temp_free(t2); 6047efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6048fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6049fcf5ef2aSThomas Huth } 6050efe843d8SDavid Gibson } 6051fcf5ef2aSThomas Huth 6052fcf5ef2aSThomas Huth /* sliq - sliq. */ 6053fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6054fcf5ef2aSThomas Huth { 6055fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6056fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6057fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6058fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6059fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6060fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6061fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6062fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6063fcf5ef2aSThomas Huth tcg_temp_free(t0); 6064fcf5ef2aSThomas Huth tcg_temp_free(t1); 6065efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6066fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6067fcf5ef2aSThomas Huth } 6068efe843d8SDavid Gibson } 6069fcf5ef2aSThomas Huth 6070fcf5ef2aSThomas Huth /* slliq - slliq. */ 6071fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6072fcf5ef2aSThomas Huth { 6073fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6074fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6075fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6076fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6077fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6078fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6079fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6080fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6081fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6082fcf5ef2aSThomas Huth tcg_temp_free(t0); 6083fcf5ef2aSThomas Huth tcg_temp_free(t1); 6084efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6085fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6086fcf5ef2aSThomas Huth } 6087efe843d8SDavid Gibson } 6088fcf5ef2aSThomas Huth 6089fcf5ef2aSThomas Huth /* sllq - sllq. */ 6090fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6091fcf5ef2aSThomas Huth { 6092fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6093fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6094fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6095fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6096fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6097fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6098fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6099fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6100fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6101fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6102fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6103fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6104fcf5ef2aSThomas Huth tcg_gen_br(l2); 6105fcf5ef2aSThomas Huth gen_set_label(l1); 6106fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6107fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6108fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6109fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6110fcf5ef2aSThomas Huth gen_set_label(l2); 6111fcf5ef2aSThomas Huth tcg_temp_free(t0); 6112fcf5ef2aSThomas Huth tcg_temp_free(t1); 6113fcf5ef2aSThomas Huth tcg_temp_free(t2); 6114efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6115fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6116fcf5ef2aSThomas Huth } 6117efe843d8SDavid Gibson } 6118fcf5ef2aSThomas Huth 6119fcf5ef2aSThomas Huth /* slq - slq. */ 6120fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6121fcf5ef2aSThomas Huth { 6122fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6123fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6124fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6125fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6126fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6127fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6128fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6129fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6130fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6131fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6132fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6133fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6134fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6135fcf5ef2aSThomas Huth gen_set_label(l1); 6136fcf5ef2aSThomas Huth tcg_temp_free(t0); 6137fcf5ef2aSThomas Huth tcg_temp_free(t1); 6138efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6139fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6140fcf5ef2aSThomas Huth } 6141efe843d8SDavid Gibson } 6142fcf5ef2aSThomas Huth 6143fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6144fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6145fcf5ef2aSThomas Huth { 6146fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6147fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6148fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6149fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6150fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6151fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6152fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6153fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6154fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6155fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6156fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6157fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6158fcf5ef2aSThomas Huth gen_set_label(l1); 6159fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6160fcf5ef2aSThomas Huth tcg_temp_free(t0); 6161fcf5ef2aSThomas Huth tcg_temp_free(t1); 6162efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6163fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6164fcf5ef2aSThomas Huth } 6165efe843d8SDavid Gibson } 6166fcf5ef2aSThomas Huth 6167fcf5ef2aSThomas Huth /* sraq - sraq. */ 6168fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6169fcf5ef2aSThomas Huth { 6170fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6171fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6172fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6173fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6174fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6175fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6176fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6177fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6178fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6179fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6180fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6181fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6182fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6183fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6184fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6185fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6186fcf5ef2aSThomas Huth gen_set_label(l1); 6187fcf5ef2aSThomas Huth tcg_temp_free(t0); 6188fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6189fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6190fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6191fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6192fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6193fcf5ef2aSThomas Huth gen_set_label(l2); 6194fcf5ef2aSThomas Huth tcg_temp_free(t1); 6195fcf5ef2aSThomas Huth tcg_temp_free(t2); 6196efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6197fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6198fcf5ef2aSThomas Huth } 6199efe843d8SDavid Gibson } 6200fcf5ef2aSThomas Huth 6201fcf5ef2aSThomas Huth /* sre - sre. */ 6202fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6203fcf5ef2aSThomas Huth { 6204fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6205fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6206fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6207fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6208fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6209fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6210fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6211fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6212fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6213fcf5ef2aSThomas Huth tcg_temp_free(t0); 6214fcf5ef2aSThomas Huth tcg_temp_free(t1); 6215efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6216fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6217fcf5ef2aSThomas Huth } 6218efe843d8SDavid Gibson } 6219fcf5ef2aSThomas Huth 6220fcf5ef2aSThomas Huth /* srea - srea. */ 6221fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6222fcf5ef2aSThomas Huth { 6223fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6224fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6225fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6226fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6227fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6228fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6229fcf5ef2aSThomas Huth tcg_temp_free(t0); 6230fcf5ef2aSThomas Huth tcg_temp_free(t1); 6231efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6232fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6233fcf5ef2aSThomas Huth } 6234efe843d8SDavid Gibson } 6235fcf5ef2aSThomas Huth 6236fcf5ef2aSThomas Huth /* sreq */ 6237fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6238fcf5ef2aSThomas Huth { 6239fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6240fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6241fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6242fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6243fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6244fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6245fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6246fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6247fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6248fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6249fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6250fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6251fcf5ef2aSThomas Huth tcg_temp_free(t0); 6252fcf5ef2aSThomas Huth tcg_temp_free(t1); 6253fcf5ef2aSThomas Huth tcg_temp_free(t2); 6254efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6255fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6256fcf5ef2aSThomas Huth } 6257efe843d8SDavid Gibson } 6258fcf5ef2aSThomas Huth 6259fcf5ef2aSThomas Huth /* sriq */ 6260fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6261fcf5ef2aSThomas Huth { 6262fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6263fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6264fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6265fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6266fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6267fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6268fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6269fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6270fcf5ef2aSThomas Huth tcg_temp_free(t0); 6271fcf5ef2aSThomas Huth tcg_temp_free(t1); 6272efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6273fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6274fcf5ef2aSThomas Huth } 6275efe843d8SDavid Gibson } 6276fcf5ef2aSThomas Huth 6277fcf5ef2aSThomas Huth /* srliq */ 6278fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6279fcf5ef2aSThomas Huth { 6280fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6281fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6282fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6283fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6284fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6285fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6286fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6287fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6288fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6289fcf5ef2aSThomas Huth tcg_temp_free(t0); 6290fcf5ef2aSThomas Huth tcg_temp_free(t1); 6291efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6292fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6293fcf5ef2aSThomas Huth } 6294efe843d8SDavid Gibson } 6295fcf5ef2aSThomas Huth 6296fcf5ef2aSThomas Huth /* srlq */ 6297fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6298fcf5ef2aSThomas Huth { 6299fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6300fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6301fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6302fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6303fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6304fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6305fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6306fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6307fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6308fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6309fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6310fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6311fcf5ef2aSThomas Huth tcg_gen_br(l2); 6312fcf5ef2aSThomas Huth gen_set_label(l1); 6313fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6314fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6315fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6316fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6317fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6318fcf5ef2aSThomas Huth gen_set_label(l2); 6319fcf5ef2aSThomas Huth tcg_temp_free(t0); 6320fcf5ef2aSThomas Huth tcg_temp_free(t1); 6321fcf5ef2aSThomas Huth tcg_temp_free(t2); 6322efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6323fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6324fcf5ef2aSThomas Huth } 6325efe843d8SDavid Gibson } 6326fcf5ef2aSThomas Huth 6327fcf5ef2aSThomas Huth /* srq */ 6328fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6329fcf5ef2aSThomas Huth { 6330fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6331fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6332fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6333fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6334fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6335fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6336fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6337fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6338fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6339fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6340fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6341fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6342fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6343fcf5ef2aSThomas Huth gen_set_label(l1); 6344fcf5ef2aSThomas Huth tcg_temp_free(t0); 6345fcf5ef2aSThomas Huth tcg_temp_free(t1); 6346efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6347fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6348fcf5ef2aSThomas Huth } 6349efe843d8SDavid Gibson } 6350fcf5ef2aSThomas Huth 6351fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6352fcf5ef2aSThomas Huth 6353fcf5ef2aSThomas Huth /* dsa */ 6354fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6355fcf5ef2aSThomas Huth { 6356fcf5ef2aSThomas Huth /* XXX: TODO */ 6357fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6358fcf5ef2aSThomas Huth } 6359fcf5ef2aSThomas Huth 6360fcf5ef2aSThomas Huth /* esa */ 6361fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6362fcf5ef2aSThomas Huth { 6363fcf5ef2aSThomas Huth /* XXX: TODO */ 6364fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6365fcf5ef2aSThomas Huth } 6366fcf5ef2aSThomas Huth 6367fcf5ef2aSThomas Huth /* mfrom */ 6368fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6369fcf5ef2aSThomas Huth { 6370fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6371fcf5ef2aSThomas Huth GEN_PRIV; 6372fcf5ef2aSThomas Huth #else 6373fcf5ef2aSThomas Huth CHK_SV; 6374fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6375fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6376fcf5ef2aSThomas Huth } 6377fcf5ef2aSThomas Huth 6378fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6379fcf5ef2aSThomas Huth 6380fcf5ef2aSThomas Huth /* tlbld */ 6381fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6382fcf5ef2aSThomas Huth { 6383fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6384fcf5ef2aSThomas Huth GEN_PRIV; 6385fcf5ef2aSThomas Huth #else 6386fcf5ef2aSThomas Huth CHK_SV; 6387fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6388fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6389fcf5ef2aSThomas Huth } 6390fcf5ef2aSThomas Huth 6391fcf5ef2aSThomas Huth /* tlbli */ 6392fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6393fcf5ef2aSThomas Huth { 6394fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6395fcf5ef2aSThomas Huth GEN_PRIV; 6396fcf5ef2aSThomas Huth #else 6397fcf5ef2aSThomas Huth CHK_SV; 6398fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6399fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6400fcf5ef2aSThomas Huth } 6401fcf5ef2aSThomas Huth 6402fcf5ef2aSThomas Huth /* 74xx TLB management */ 6403fcf5ef2aSThomas Huth 6404fcf5ef2aSThomas Huth /* tlbld */ 6405fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6406fcf5ef2aSThomas Huth { 6407fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6408fcf5ef2aSThomas Huth GEN_PRIV; 6409fcf5ef2aSThomas Huth #else 6410fcf5ef2aSThomas Huth CHK_SV; 6411fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6412fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6413fcf5ef2aSThomas Huth } 6414fcf5ef2aSThomas Huth 6415fcf5ef2aSThomas Huth /* tlbli */ 6416fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6417fcf5ef2aSThomas Huth { 6418fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6419fcf5ef2aSThomas Huth GEN_PRIV; 6420fcf5ef2aSThomas Huth #else 6421fcf5ef2aSThomas Huth CHK_SV; 6422fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6423fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6424fcf5ef2aSThomas Huth } 6425fcf5ef2aSThomas Huth 6426fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6427fcf5ef2aSThomas Huth 6428fcf5ef2aSThomas Huth /* clf */ 6429fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6430fcf5ef2aSThomas Huth { 6431fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6432fcf5ef2aSThomas Huth } 6433fcf5ef2aSThomas Huth 6434fcf5ef2aSThomas Huth /* cli */ 6435fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6436fcf5ef2aSThomas Huth { 6437fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6438fcf5ef2aSThomas Huth GEN_PRIV; 6439fcf5ef2aSThomas Huth #else 6440fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6441fcf5ef2aSThomas Huth CHK_SV; 6442fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6443fcf5ef2aSThomas Huth } 6444fcf5ef2aSThomas Huth 6445fcf5ef2aSThomas Huth /* dclst */ 6446fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6447fcf5ef2aSThomas Huth { 6448fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6449fcf5ef2aSThomas Huth } 6450fcf5ef2aSThomas Huth 6451fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6452fcf5ef2aSThomas Huth { 6453fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6454fcf5ef2aSThomas Huth GEN_PRIV; 6455fcf5ef2aSThomas Huth #else 6456fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6457fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6458fcf5ef2aSThomas Huth TCGv t0; 6459fcf5ef2aSThomas Huth 6460fcf5ef2aSThomas Huth CHK_SV; 6461fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6462fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6463e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6464fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6465fcf5ef2aSThomas Huth tcg_temp_free(t0); 6466efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6467fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6468efe843d8SDavid Gibson } 6469fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6470fcf5ef2aSThomas Huth } 6471fcf5ef2aSThomas Huth 6472fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6473fcf5ef2aSThomas Huth { 6474fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6475fcf5ef2aSThomas Huth GEN_PRIV; 6476fcf5ef2aSThomas Huth #else 6477fcf5ef2aSThomas Huth TCGv t0; 6478fcf5ef2aSThomas Huth 6479fcf5ef2aSThomas Huth CHK_SV; 6480fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6481fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6482fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6483fcf5ef2aSThomas Huth tcg_temp_free(t0); 6484fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6485fcf5ef2aSThomas Huth } 6486fcf5ef2aSThomas Huth 6487fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6488fcf5ef2aSThomas Huth { 6489fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6490fcf5ef2aSThomas Huth GEN_PRIV; 6491fcf5ef2aSThomas Huth #else 6492fcf5ef2aSThomas Huth CHK_SV; 6493fcf5ef2aSThomas Huth 6494fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 649559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6496fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6497fcf5ef2aSThomas Huth } 6498fcf5ef2aSThomas Huth 6499fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6500fcf5ef2aSThomas Huth 6501fcf5ef2aSThomas Huth /* BookE specific instructions */ 6502fcf5ef2aSThomas Huth 6503fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6504fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6505fcf5ef2aSThomas Huth { 6506fcf5ef2aSThomas Huth /* XXX: TODO */ 6507fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6508fcf5ef2aSThomas Huth } 6509fcf5ef2aSThomas Huth 6510fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6511fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6512fcf5ef2aSThomas Huth { 6513fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6514fcf5ef2aSThomas Huth GEN_PRIV; 6515fcf5ef2aSThomas Huth #else 6516fcf5ef2aSThomas Huth TCGv t0; 6517fcf5ef2aSThomas Huth 6518fcf5ef2aSThomas Huth CHK_SV; 6519fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6520fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6521fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6522fcf5ef2aSThomas Huth tcg_temp_free(t0); 6523fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6524fcf5ef2aSThomas Huth } 6525fcf5ef2aSThomas Huth 6526fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6527fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6528fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6529fcf5ef2aSThomas Huth { 6530fcf5ef2aSThomas Huth TCGv t0, t1; 6531fcf5ef2aSThomas Huth 6532fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6533fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6534fcf5ef2aSThomas Huth 6535fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6536fcf5ef2aSThomas Huth case 0x05: 6537fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6538fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6539fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6540fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6541fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6542fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6543fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6544fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6545fcf5ef2aSThomas Huth break; 6546fcf5ef2aSThomas Huth case 0x04: 6547fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6548fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6549fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6550fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6551fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6552fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6553fcf5ef2aSThomas Huth break; 6554fcf5ef2aSThomas Huth case 0x01: 6555fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6556fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6557fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6558fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6559fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6560fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6561fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6562fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6563fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6564fcf5ef2aSThomas Huth break; 6565fcf5ef2aSThomas Huth case 0x00: 6566fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6567fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6568fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6569fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6570fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6571fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6572fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6573fcf5ef2aSThomas Huth break; 6574fcf5ef2aSThomas Huth case 0x0D: 6575fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6576fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6577fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6578fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6579fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6580fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6581fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6582fcf5ef2aSThomas Huth break; 6583fcf5ef2aSThomas Huth case 0x0C: 6584fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6585fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6586fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6587fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6588fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6589fcf5ef2aSThomas Huth break; 6590fcf5ef2aSThomas Huth } 6591fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6592fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6593fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6594fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6595fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6596fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6597fcf5ef2aSThomas Huth } else { 6598fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6599fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6600fcf5ef2aSThomas Huth } 6601fcf5ef2aSThomas Huth 6602fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6603fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6604fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6605fcf5ef2aSThomas Huth 6606fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6607fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6608fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6609fcf5ef2aSThomas Huth } 6610fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6611fcf5ef2aSThomas Huth /* Signed */ 6612fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6613fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6614fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6615fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6616fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6617fcf5ef2aSThomas Huth /* Saturate */ 6618fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6619fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6620fcf5ef2aSThomas Huth } 6621fcf5ef2aSThomas Huth } else { 6622fcf5ef2aSThomas Huth /* Unsigned */ 6623fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6624fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6625fcf5ef2aSThomas Huth /* Saturate */ 6626fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6627fcf5ef2aSThomas Huth } 6628fcf5ef2aSThomas Huth } 6629fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6630fcf5ef2aSThomas Huth /* Check overflow */ 6631fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6632fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6633fcf5ef2aSThomas Huth } 6634fcf5ef2aSThomas Huth gen_set_label(l1); 6635fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6636fcf5ef2aSThomas Huth } 6637fcf5ef2aSThomas Huth } else { 6638fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6639fcf5ef2aSThomas Huth } 6640fcf5ef2aSThomas Huth tcg_temp_free(t0); 6641fcf5ef2aSThomas Huth tcg_temp_free(t1); 6642fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6643fcf5ef2aSThomas Huth /* Update Rc0 */ 6644fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6645fcf5ef2aSThomas Huth } 6646fcf5ef2aSThomas Huth } 6647fcf5ef2aSThomas Huth 6648fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6649fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6650fcf5ef2aSThomas Huth { \ 6651fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6652fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6653fcf5ef2aSThomas Huth } 6654fcf5ef2aSThomas Huth 6655fcf5ef2aSThomas Huth /* macchw - macchw. */ 6656fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6657fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6658fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6659fcf5ef2aSThomas Huth /* macchws - macchws. */ 6660fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6661fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6662fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6663fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6664fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6665fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6666fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6667fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6668fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6669fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6670fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6671fcf5ef2aSThomas Huth /* machhw - machhw. */ 6672fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6673fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6674fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6675fcf5ef2aSThomas Huth /* machhws - machhws. */ 6676fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6677fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6678fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6679fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6680fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6681fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6682fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6683fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6684fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6685fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6686fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6687fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6688fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6689fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6690fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6691fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6692fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6693fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6694fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6695fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6696fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6697fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6698fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6699fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6700fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6701fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6702fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6703fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6704fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6705fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6706fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6707fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6708fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6709fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6710fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6711fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6712fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6713fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6714fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6715fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6716fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6717fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6718fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6719fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6720fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6721fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6722fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6723fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6724fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6725fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6726fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6727fcf5ef2aSThomas Huth 6728fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6729fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6730fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6731fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6732fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6733fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6734fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6735fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6736fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6737fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6738fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6739fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6740fcf5ef2aSThomas Huth 6741fcf5ef2aSThomas Huth /* mfdcr */ 6742fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6743fcf5ef2aSThomas Huth { 6744fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6745fcf5ef2aSThomas Huth GEN_PRIV; 6746fcf5ef2aSThomas Huth #else 6747fcf5ef2aSThomas Huth TCGv dcrn; 6748fcf5ef2aSThomas Huth 6749fcf5ef2aSThomas Huth CHK_SV; 6750fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6751fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6752fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6753fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6754fcf5ef2aSThomas Huth } 6755fcf5ef2aSThomas Huth 6756fcf5ef2aSThomas Huth /* mtdcr */ 6757fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6758fcf5ef2aSThomas Huth { 6759fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6760fcf5ef2aSThomas Huth GEN_PRIV; 6761fcf5ef2aSThomas Huth #else 6762fcf5ef2aSThomas Huth TCGv dcrn; 6763fcf5ef2aSThomas Huth 6764fcf5ef2aSThomas Huth CHK_SV; 6765fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6766fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6767fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6768fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6769fcf5ef2aSThomas Huth } 6770fcf5ef2aSThomas Huth 6771fcf5ef2aSThomas Huth /* mfdcrx */ 6772fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6773fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6774fcf5ef2aSThomas Huth { 6775fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6776fcf5ef2aSThomas Huth GEN_PRIV; 6777fcf5ef2aSThomas Huth #else 6778fcf5ef2aSThomas Huth CHK_SV; 6779fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6780fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6781fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6782fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6783fcf5ef2aSThomas Huth } 6784fcf5ef2aSThomas Huth 6785fcf5ef2aSThomas Huth /* mtdcrx */ 6786fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6787fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6788fcf5ef2aSThomas Huth { 6789fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6790fcf5ef2aSThomas Huth GEN_PRIV; 6791fcf5ef2aSThomas Huth #else 6792fcf5ef2aSThomas Huth CHK_SV; 6793fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6794fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6795fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6796fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6797fcf5ef2aSThomas Huth } 6798fcf5ef2aSThomas Huth 6799fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6800fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6801fcf5ef2aSThomas Huth { 6802fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6803fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6804fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6805fcf5ef2aSThomas Huth } 6806fcf5ef2aSThomas Huth 6807fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6808fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6809fcf5ef2aSThomas Huth { 6810fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6811fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6812fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6813fcf5ef2aSThomas Huth } 6814fcf5ef2aSThomas Huth 6815fcf5ef2aSThomas Huth /* dccci */ 6816fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6817fcf5ef2aSThomas Huth { 6818fcf5ef2aSThomas Huth CHK_SV; 6819fcf5ef2aSThomas Huth /* interpreted as no-op */ 6820fcf5ef2aSThomas Huth } 6821fcf5ef2aSThomas Huth 6822fcf5ef2aSThomas Huth /* dcread */ 6823fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6824fcf5ef2aSThomas Huth { 6825fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6826fcf5ef2aSThomas Huth GEN_PRIV; 6827fcf5ef2aSThomas Huth #else 6828fcf5ef2aSThomas Huth TCGv EA, val; 6829fcf5ef2aSThomas Huth 6830fcf5ef2aSThomas Huth CHK_SV; 6831fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6832fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6833fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6834fcf5ef2aSThomas Huth val = tcg_temp_new(); 6835fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6836fcf5ef2aSThomas Huth tcg_temp_free(val); 6837fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6838fcf5ef2aSThomas Huth tcg_temp_free(EA); 6839fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6840fcf5ef2aSThomas Huth } 6841fcf5ef2aSThomas Huth 6842fcf5ef2aSThomas Huth /* icbt */ 6843fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6844fcf5ef2aSThomas Huth { 6845efe843d8SDavid Gibson /* 6846efe843d8SDavid Gibson * interpreted as no-op 6847efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6848efe843d8SDavid Gibson * does not generate any exception 6849fcf5ef2aSThomas Huth */ 6850fcf5ef2aSThomas Huth } 6851fcf5ef2aSThomas Huth 6852fcf5ef2aSThomas Huth /* iccci */ 6853fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6854fcf5ef2aSThomas Huth { 6855fcf5ef2aSThomas Huth CHK_SV; 6856fcf5ef2aSThomas Huth /* interpreted as no-op */ 6857fcf5ef2aSThomas Huth } 6858fcf5ef2aSThomas Huth 6859fcf5ef2aSThomas Huth /* icread */ 6860fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6861fcf5ef2aSThomas Huth { 6862fcf5ef2aSThomas Huth CHK_SV; 6863fcf5ef2aSThomas Huth /* interpreted as no-op */ 6864fcf5ef2aSThomas Huth } 6865fcf5ef2aSThomas Huth 6866fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6867fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6868fcf5ef2aSThomas Huth { 6869fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6870fcf5ef2aSThomas Huth GEN_PRIV; 6871fcf5ef2aSThomas Huth #else 6872fcf5ef2aSThomas Huth CHK_SV; 6873fcf5ef2aSThomas Huth /* Restore CPU state */ 6874fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 687559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6876fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6877fcf5ef2aSThomas Huth } 6878fcf5ef2aSThomas Huth 6879fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6880fcf5ef2aSThomas Huth { 6881fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6882fcf5ef2aSThomas Huth GEN_PRIV; 6883fcf5ef2aSThomas Huth #else 6884fcf5ef2aSThomas Huth CHK_SV; 6885fcf5ef2aSThomas Huth /* Restore CPU state */ 6886fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 688759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6888fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6889fcf5ef2aSThomas Huth } 6890fcf5ef2aSThomas Huth 6891fcf5ef2aSThomas Huth /* BookE specific */ 6892fcf5ef2aSThomas Huth 6893fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6894fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6895fcf5ef2aSThomas Huth { 6896fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6897fcf5ef2aSThomas Huth GEN_PRIV; 6898fcf5ef2aSThomas Huth #else 6899fcf5ef2aSThomas Huth CHK_SV; 6900fcf5ef2aSThomas Huth /* Restore CPU state */ 6901fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 690259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6903fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6904fcf5ef2aSThomas Huth } 6905fcf5ef2aSThomas Huth 6906fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6907fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6908fcf5ef2aSThomas Huth { 6909fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6910fcf5ef2aSThomas Huth GEN_PRIV; 6911fcf5ef2aSThomas Huth #else 6912fcf5ef2aSThomas Huth CHK_SV; 6913fcf5ef2aSThomas Huth /* Restore CPU state */ 6914fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 691559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6916fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6917fcf5ef2aSThomas Huth } 6918fcf5ef2aSThomas Huth 6919fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6920fcf5ef2aSThomas Huth 6921fcf5ef2aSThomas Huth /* tlbre */ 6922fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6923fcf5ef2aSThomas Huth { 6924fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6925fcf5ef2aSThomas Huth GEN_PRIV; 6926fcf5ef2aSThomas Huth #else 6927fcf5ef2aSThomas Huth CHK_SV; 6928fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6929fcf5ef2aSThomas Huth case 0: 6930fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6931fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6932fcf5ef2aSThomas Huth break; 6933fcf5ef2aSThomas Huth case 1: 6934fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6935fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6936fcf5ef2aSThomas Huth break; 6937fcf5ef2aSThomas Huth default: 6938fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6939fcf5ef2aSThomas Huth break; 6940fcf5ef2aSThomas Huth } 6941fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6942fcf5ef2aSThomas Huth } 6943fcf5ef2aSThomas Huth 6944fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6945fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6946fcf5ef2aSThomas Huth { 6947fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6948fcf5ef2aSThomas Huth GEN_PRIV; 6949fcf5ef2aSThomas Huth #else 6950fcf5ef2aSThomas Huth TCGv t0; 6951fcf5ef2aSThomas Huth 6952fcf5ef2aSThomas Huth CHK_SV; 6953fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6954fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6955fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6956fcf5ef2aSThomas Huth tcg_temp_free(t0); 6957fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6958fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6959fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6960fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6961fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6962fcf5ef2aSThomas Huth gen_set_label(l1); 6963fcf5ef2aSThomas Huth } 6964fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6965fcf5ef2aSThomas Huth } 6966fcf5ef2aSThomas Huth 6967fcf5ef2aSThomas Huth /* tlbwe */ 6968fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6969fcf5ef2aSThomas Huth { 6970fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6971fcf5ef2aSThomas Huth GEN_PRIV; 6972fcf5ef2aSThomas Huth #else 6973fcf5ef2aSThomas Huth CHK_SV; 6974fcf5ef2aSThomas Huth 6975fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6976fcf5ef2aSThomas Huth case 0: 6977fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6978fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6979fcf5ef2aSThomas Huth break; 6980fcf5ef2aSThomas Huth case 1: 6981fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6982fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6983fcf5ef2aSThomas Huth break; 6984fcf5ef2aSThomas Huth default: 6985fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6986fcf5ef2aSThomas Huth break; 6987fcf5ef2aSThomas Huth } 6988fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6989fcf5ef2aSThomas Huth } 6990fcf5ef2aSThomas Huth 6991fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6992fcf5ef2aSThomas Huth 6993fcf5ef2aSThomas Huth /* tlbre */ 6994fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6995fcf5ef2aSThomas Huth { 6996fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6997fcf5ef2aSThomas Huth GEN_PRIV; 6998fcf5ef2aSThomas Huth #else 6999fcf5ef2aSThomas Huth CHK_SV; 7000fcf5ef2aSThomas Huth 7001fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7002fcf5ef2aSThomas Huth case 0: 7003fcf5ef2aSThomas Huth case 1: 7004fcf5ef2aSThomas Huth case 2: 7005fcf5ef2aSThomas Huth { 7006fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7007fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7008fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7009fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7010fcf5ef2aSThomas Huth } 7011fcf5ef2aSThomas Huth break; 7012fcf5ef2aSThomas Huth default: 7013fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7014fcf5ef2aSThomas Huth break; 7015fcf5ef2aSThomas Huth } 7016fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7017fcf5ef2aSThomas Huth } 7018fcf5ef2aSThomas Huth 7019fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7020fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7021fcf5ef2aSThomas Huth { 7022fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7023fcf5ef2aSThomas Huth GEN_PRIV; 7024fcf5ef2aSThomas Huth #else 7025fcf5ef2aSThomas Huth TCGv t0; 7026fcf5ef2aSThomas Huth 7027fcf5ef2aSThomas Huth CHK_SV; 7028fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7029fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7030fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7031fcf5ef2aSThomas Huth tcg_temp_free(t0); 7032fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7033fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7034fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7035fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7036fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7037fcf5ef2aSThomas Huth gen_set_label(l1); 7038fcf5ef2aSThomas Huth } 7039fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7040fcf5ef2aSThomas Huth } 7041fcf5ef2aSThomas Huth 7042fcf5ef2aSThomas Huth /* tlbwe */ 7043fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7044fcf5ef2aSThomas Huth { 7045fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7046fcf5ef2aSThomas Huth GEN_PRIV; 7047fcf5ef2aSThomas Huth #else 7048fcf5ef2aSThomas Huth CHK_SV; 7049fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7050fcf5ef2aSThomas Huth case 0: 7051fcf5ef2aSThomas Huth case 1: 7052fcf5ef2aSThomas Huth case 2: 7053fcf5ef2aSThomas Huth { 7054fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7055fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7056fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7057fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7058fcf5ef2aSThomas Huth } 7059fcf5ef2aSThomas Huth break; 7060fcf5ef2aSThomas Huth default: 7061fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7062fcf5ef2aSThomas Huth break; 7063fcf5ef2aSThomas Huth } 7064fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7065fcf5ef2aSThomas Huth } 7066fcf5ef2aSThomas Huth 7067fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7068fcf5ef2aSThomas Huth 7069fcf5ef2aSThomas Huth /* tlbre */ 7070fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7071fcf5ef2aSThomas Huth { 7072fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7073fcf5ef2aSThomas Huth GEN_PRIV; 7074fcf5ef2aSThomas Huth #else 7075fcf5ef2aSThomas Huth CHK_SV; 7076fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7077fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7078fcf5ef2aSThomas Huth } 7079fcf5ef2aSThomas Huth 7080fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7081fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7082fcf5ef2aSThomas Huth { 7083fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7084fcf5ef2aSThomas Huth GEN_PRIV; 7085fcf5ef2aSThomas Huth #else 7086fcf5ef2aSThomas Huth TCGv t0; 7087fcf5ef2aSThomas Huth 7088fcf5ef2aSThomas Huth CHK_SV; 7089fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7090fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7091fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7092fcf5ef2aSThomas Huth } else { 7093fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7094fcf5ef2aSThomas Huth } 7095fcf5ef2aSThomas Huth 7096fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7097fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7098fcf5ef2aSThomas Huth tcg_temp_free(t0); 7099fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7100fcf5ef2aSThomas Huth } 7101fcf5ef2aSThomas Huth 7102fcf5ef2aSThomas Huth /* tlbwe */ 7103fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7104fcf5ef2aSThomas Huth { 7105fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7106fcf5ef2aSThomas Huth GEN_PRIV; 7107fcf5ef2aSThomas Huth #else 7108fcf5ef2aSThomas Huth CHK_SV; 7109fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7110fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7111fcf5ef2aSThomas Huth } 7112fcf5ef2aSThomas Huth 7113fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7114fcf5ef2aSThomas Huth { 7115fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7116fcf5ef2aSThomas Huth GEN_PRIV; 7117fcf5ef2aSThomas Huth #else 7118fcf5ef2aSThomas Huth TCGv t0; 7119fcf5ef2aSThomas Huth 7120fcf5ef2aSThomas Huth CHK_SV; 7121fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7122fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7123fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7124fcf5ef2aSThomas Huth tcg_temp_free(t0); 7125fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7126fcf5ef2aSThomas Huth } 7127fcf5ef2aSThomas Huth 7128fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7129fcf5ef2aSThomas Huth { 7130fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7131fcf5ef2aSThomas Huth GEN_PRIV; 7132fcf5ef2aSThomas Huth #else 7133fcf5ef2aSThomas Huth TCGv t0; 7134fcf5ef2aSThomas Huth 7135fcf5ef2aSThomas Huth CHK_SV; 7136fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7137fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7138fcf5ef2aSThomas Huth 7139fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7140fcf5ef2aSThomas Huth case 0: 7141fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7142fcf5ef2aSThomas Huth break; 7143fcf5ef2aSThomas Huth case 1: 7144fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7145fcf5ef2aSThomas Huth break; 7146fcf5ef2aSThomas Huth case 3: 7147fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7148fcf5ef2aSThomas Huth break; 7149fcf5ef2aSThomas Huth default: 7150fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7151fcf5ef2aSThomas Huth break; 7152fcf5ef2aSThomas Huth } 7153fcf5ef2aSThomas Huth 7154fcf5ef2aSThomas Huth tcg_temp_free(t0); 7155fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7156fcf5ef2aSThomas Huth } 7157fcf5ef2aSThomas Huth 7158fcf5ef2aSThomas Huth 7159fcf5ef2aSThomas Huth /* wrtee */ 7160fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7161fcf5ef2aSThomas Huth { 7162fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7163fcf5ef2aSThomas Huth GEN_PRIV; 7164fcf5ef2aSThomas Huth #else 7165fcf5ef2aSThomas Huth TCGv t0; 7166fcf5ef2aSThomas Huth 7167fcf5ef2aSThomas Huth CHK_SV; 7168fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7169fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7170fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7171fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7172fcf5ef2aSThomas Huth tcg_temp_free(t0); 7173efe843d8SDavid Gibson /* 7174efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7175efe843d8SDavid Gibson * just set msr_ee to 1 7176fcf5ef2aSThomas Huth */ 7177d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7178fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7179fcf5ef2aSThomas Huth } 7180fcf5ef2aSThomas Huth 7181fcf5ef2aSThomas Huth /* wrteei */ 7182fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7183fcf5ef2aSThomas Huth { 7184fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7185fcf5ef2aSThomas Huth GEN_PRIV; 7186fcf5ef2aSThomas Huth #else 7187fcf5ef2aSThomas Huth CHK_SV; 7188fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7189fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7190fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7191d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7192fcf5ef2aSThomas Huth } else { 7193fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7194fcf5ef2aSThomas Huth } 7195fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7196fcf5ef2aSThomas Huth } 7197fcf5ef2aSThomas Huth 7198fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7199fcf5ef2aSThomas Huth 7200fcf5ef2aSThomas Huth /* dlmzb */ 7201fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7202fcf5ef2aSThomas Huth { 7203fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7204fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7205fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7206fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7207fcf5ef2aSThomas Huth } 7208fcf5ef2aSThomas Huth 7209fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7210fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7211fcf5ef2aSThomas Huth { 7212fcf5ef2aSThomas Huth /* interpreted as no-op */ 7213fcf5ef2aSThomas Huth } 7214fcf5ef2aSThomas Huth 7215fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7216fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7217fcf5ef2aSThomas Huth { 721827a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 721927a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 722027a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 722127a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 722227a3ea7eSBALATON Zoltan } 722327a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7224fcf5ef2aSThomas Huth } 7225fcf5ef2aSThomas Huth 7226fcf5ef2aSThomas Huth /* icbt */ 7227fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7228fcf5ef2aSThomas Huth { 7229efe843d8SDavid Gibson /* 7230efe843d8SDavid Gibson * interpreted as no-op 7231efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7232efe843d8SDavid Gibson * does not generate any exception 7233fcf5ef2aSThomas Huth */ 7234fcf5ef2aSThomas Huth } 7235fcf5ef2aSThomas Huth 7236fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7237fcf5ef2aSThomas Huth 7238fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7239fcf5ef2aSThomas Huth { 7240fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7241fcf5ef2aSThomas Huth GEN_PRIV; 7242fcf5ef2aSThomas Huth #else 7243ebca5e6dSCédric Le Goater CHK_HV; 7244d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 72457af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72467af1e7b0SCédric Le Goater } else { 7247fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72487af1e7b0SCédric Le Goater } 7249fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7250fcf5ef2aSThomas Huth } 7251fcf5ef2aSThomas Huth 7252fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7253fcf5ef2aSThomas Huth { 7254fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7255fcf5ef2aSThomas Huth GEN_PRIV; 7256fcf5ef2aSThomas Huth #else 7257ebca5e6dSCédric Le Goater CHK_HV; 7258d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 72597af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 72607af1e7b0SCédric Le Goater } else { 7261fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 72627af1e7b0SCédric Le Goater } 7263fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7264fcf5ef2aSThomas Huth } 7265fcf5ef2aSThomas Huth 72665ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 72675ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 72685ba7ba1dSCédric Le Goater { 72695ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 72705ba7ba1dSCédric Le Goater GEN_PRIV; 72715ba7ba1dSCédric Le Goater #else 72725ba7ba1dSCédric Le Goater CHK_SV; 72735ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72745ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72755ba7ba1dSCédric Le Goater } 72765ba7ba1dSCédric Le Goater 72775ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 72785ba7ba1dSCédric Le Goater { 72795ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 72805ba7ba1dSCédric Le Goater GEN_PRIV; 72815ba7ba1dSCédric Le Goater #else 72825ba7ba1dSCédric Le Goater CHK_SV; 72835ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72845ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72855ba7ba1dSCédric Le Goater } 72865ba7ba1dSCédric Le Goater #endif 72875ba7ba1dSCédric Le Goater 72887af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 72897af1e7b0SCédric Le Goater { 72907af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 72917af1e7b0SCédric Le Goater GEN_PRIV; 72927af1e7b0SCédric Le Goater #else 72937af1e7b0SCédric Le Goater CHK_HV; 72947af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72957af1e7b0SCédric Le Goater /* interpreted as no-op */ 72967af1e7b0SCédric Le Goater } 7297fcf5ef2aSThomas Huth 7298fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7299fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7300fcf5ef2aSThomas Huth { 7301fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7302fcf5ef2aSThomas Huth 7303fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7304fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7305fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7306fcf5ef2aSThomas Huth } 7307fcf5ef2aSThomas Huth 7308fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7309fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7310fcf5ef2aSThomas Huth { 7311fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7312fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7313fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7314fcf5ef2aSThomas Huth 7315fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7316fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7317fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7318fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7319fcf5ef2aSThomas Huth } else { 7320fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7321fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7322fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7323fcf5ef2aSThomas Huth } 7324fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7325fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7326fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7327fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7328fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7329fcf5ef2aSThomas Huth } 7330fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7331fcf5ef2aSThomas Huth 7332fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7333fcf5ef2aSThomas Huth { 7334fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7335fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7336fcf5ef2aSThomas Huth return; 7337fcf5ef2aSThomas Huth } 7338fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7339fcf5ef2aSThomas Huth } 7340fcf5ef2aSThomas Huth 7341fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7342fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7343fcf5ef2aSThomas Huth { \ 7344fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7345fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7346fcf5ef2aSThomas Huth return; \ 7347fcf5ef2aSThomas Huth } \ 7348efe843d8SDavid Gibson /* \ 7349efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7350fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7351fcf5ef2aSThomas Huth * \ 7352fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7353fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7354fcf5ef2aSThomas Huth */ \ 7355fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7356fcf5ef2aSThomas Huth } 7357fcf5ef2aSThomas Huth 7358fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7359fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7360fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7361fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7362fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7363fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7364fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7365efe843d8SDavid Gibson 7366b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7367b8b4576eSSuraj Jitindar Singh { 7368efe843d8SDavid Gibson /* Do Nothing */ 7369b8b4576eSSuraj Jitindar Singh } 7370fcf5ef2aSThomas Huth 737180b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 737280b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 737380b8c1eeSNikunj A Dadhania { \ 7374efe843d8SDavid Gibson /* \ 7375efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7376efe843d8SDavid Gibson * implementation of the copy paste facility \ 737780b8c1eeSNikunj A Dadhania */ \ 737880b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 737980b8c1eeSNikunj A Dadhania } 738080b8c1eeSNikunj A Dadhania 738180b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 738280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 738380b8c1eeSNikunj A Dadhania 7384fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7385fcf5ef2aSThomas Huth { 7386fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7387fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7388fcf5ef2aSThomas Huth return; 7389fcf5ef2aSThomas Huth } 7390efe843d8SDavid Gibson /* 7391efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7392efe843d8SDavid Gibson * simple: 7393fcf5ef2aSThomas Huth * 7394fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7395fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7396fcf5ef2aSThomas Huth */ 7397fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7398fcf5ef2aSThomas Huth } 7399fcf5ef2aSThomas Huth 7400fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7401fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7402fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7403fcf5ef2aSThomas Huth { \ 7404fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7405fcf5ef2aSThomas Huth } 7406fcf5ef2aSThomas Huth 7407fcf5ef2aSThomas Huth #else 7408fcf5ef2aSThomas Huth 7409fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7410fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7411fcf5ef2aSThomas Huth { \ 7412fcf5ef2aSThomas Huth CHK_SV; \ 7413fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7414fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7415fcf5ef2aSThomas Huth return; \ 7416fcf5ef2aSThomas Huth } \ 7417efe843d8SDavid Gibson /* \ 7418efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7419fcf5ef2aSThomas Huth * simple: \ 7420fcf5ef2aSThomas Huth * \ 7421fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7422fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7423fcf5ef2aSThomas Huth */ \ 7424fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7425fcf5ef2aSThomas Huth } 7426fcf5ef2aSThomas Huth 7427fcf5ef2aSThomas Huth #endif 7428fcf5ef2aSThomas Huth 7429fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7430fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7431fcf5ef2aSThomas Huth 74321a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 74331a404c91SMark Cave-Ayland { 7434e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 74351a404c91SMark Cave-Ayland } 74361a404c91SMark Cave-Ayland 74371a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 74381a404c91SMark Cave-Ayland { 7439e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 74401a404c91SMark Cave-Ayland } 74411a404c91SMark Cave-Ayland 7442c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7443c4a18dbfSMark Cave-Ayland { 744437da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7445c4a18dbfSMark Cave-Ayland } 7446c4a18dbfSMark Cave-Ayland 7447c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7448c4a18dbfSMark Cave-Ayland { 744937da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7450c4a18dbfSMark Cave-Ayland } 7451c4a18dbfSMark Cave-Ayland 7452c9826ae9SRichard Henderson /* 7453f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 7454f2aabda8SRichard Henderson */ 7455f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 7456f2aabda8SRichard Henderson { 7457f2aabda8SRichard Henderson return x * 4; 7458f2aabda8SRichard Henderson } 7459f2aabda8SRichard Henderson 7460f2aabda8SRichard Henderson /* 7461c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 7462c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 7463c9826ae9SRichard Henderson * proper variable. 7464c9826ae9SRichard Henderson */ 7465c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7466c9826ae9SRichard Henderson do { \ 7467c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7468c9826ae9SRichard Henderson return false; \ 7469c9826ae9SRichard Henderson } \ 7470c9826ae9SRichard Henderson } while (0) 7471c9826ae9SRichard Henderson 7472c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7473c9826ae9SRichard Henderson do { \ 7474c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7475c9826ae9SRichard Henderson return false; \ 7476c9826ae9SRichard Henderson } \ 7477c9826ae9SRichard Henderson } while (0) 7478c9826ae9SRichard Henderson 7479c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7480c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 7481c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 7482c9826ae9SRichard Henderson #else 7483c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7484c9826ae9SRichard Henderson #endif 7485c9826ae9SRichard Henderson 7486f2aabda8SRichard Henderson /* 7487f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 7488f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 7489f2aabda8SRichard Henderson */ 7490f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 7491f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7492f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 7493f2aabda8SRichard Henderson 7494f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 7495f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7496f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 7497f2aabda8SRichard Henderson 7498f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 7499f2aabda8SRichard Henderson 7500f2aabda8SRichard Henderson 750199082815SRichard Henderson #include "decode-insn32.c.inc" 750299082815SRichard Henderson #include "decode-insn64.c.inc" 7503565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 7504565cb109SGustavo Romero 7505*725b2d4dSFernando Eckhardt Valle /* 7506*725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 7507*725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 7508*725b2d4dSFernando Eckhardt Valle */ 7509*725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 7510*725b2d4dSFernando Eckhardt Valle { 7511*725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 7512*725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 7513*725b2d4dSFernando Eckhardt Valle d->si = a->si; 7514*725b2d4dSFernando Eckhardt Valle if (a->r) { 7515*725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 7516*725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 7517*725b2d4dSFernando Eckhardt Valle return false; 7518*725b2d4dSFernando Eckhardt Valle } 7519*725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 7520*725b2d4dSFernando Eckhardt Valle } 7521*725b2d4dSFernando Eckhardt Valle return true; 7522*725b2d4dSFernando Eckhardt Valle } 7523*725b2d4dSFernando Eckhardt Valle 752499082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 752599082815SRichard Henderson 7526139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7527fcf5ef2aSThomas Huth 7528139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7529fcf5ef2aSThomas Huth 7530139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7531a5f56954SMatheus Ferst #include "translate/vector-impl.c.inc" 7532fcf5ef2aSThomas Huth 7533139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7534fcf5ef2aSThomas Huth 7535139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7536fcf5ef2aSThomas Huth 75375cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 75385cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 75395cb091a4SNikunj A Dadhania { 75405cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 75415cb091a4SNikunj A Dadhania case 0: /* lfdp */ 75425cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 75435cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 75445cb091a4SNikunj A Dadhania } 75455cb091a4SNikunj A Dadhania break; 75465cb091a4SNikunj A Dadhania case 2: /* lxsd */ 75475cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 75485cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 75495cb091a4SNikunj A Dadhania } 75505cb091a4SNikunj A Dadhania break; 75515cb091a4SNikunj A Dadhania case 3: /* lxssp */ 75525cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 75535cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 75545cb091a4SNikunj A Dadhania } 75555cb091a4SNikunj A Dadhania break; 75565cb091a4SNikunj A Dadhania } 75575cb091a4SNikunj A Dadhania return gen_invalid(ctx); 75585cb091a4SNikunj A Dadhania } 75595cb091a4SNikunj A Dadhania 7560d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7561e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7562e3001664SNikunj A Dadhania { 7563e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7564e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7565e3001664SNikunj A Dadhania case 1: /* lxv */ 7566d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7567d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7568d59ba583SNikunj A Dadhania } 7569e3001664SNikunj A Dadhania break; 7570e3001664SNikunj A Dadhania case 5: /* stxv */ 7571d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7572d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7573d59ba583SNikunj A Dadhania } 7574e3001664SNikunj A Dadhania break; 7575e3001664SNikunj A Dadhania } 7576e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7577e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7578e3001664SNikunj A Dadhania case 0: /* stfdp */ 7579e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7580e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7581e3001664SNikunj A Dadhania } 7582e3001664SNikunj A Dadhania break; 7583e3001664SNikunj A Dadhania case 2: /* stxsd */ 7584e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7585e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7586e3001664SNikunj A Dadhania } 7587e3001664SNikunj A Dadhania break; 7588e3001664SNikunj A Dadhania case 3: /* stxssp */ 7589e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7590e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7591e3001664SNikunj A Dadhania } 7592e3001664SNikunj A Dadhania break; 7593e3001664SNikunj A Dadhania } 7594e3001664SNikunj A Dadhania } 7595e3001664SNikunj A Dadhania return gen_invalid(ctx); 7596e3001664SNikunj A Dadhania } 7597e3001664SNikunj A Dadhania 75989d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75999d69cfa2SLijun Pan /* brd */ 76009d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 76019d69cfa2SLijun Pan { 76029d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 76039d69cfa2SLijun Pan } 76049d69cfa2SLijun Pan 76059d69cfa2SLijun Pan /* brw */ 76069d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 76079d69cfa2SLijun Pan { 76089d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 76099d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 76109d69cfa2SLijun Pan 76119d69cfa2SLijun Pan } 76129d69cfa2SLijun Pan 76139d69cfa2SLijun Pan /* brh */ 76149d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 76159d69cfa2SLijun Pan { 7616491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 76179d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 76189d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 76199d69cfa2SLijun Pan 76209d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 7621491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 7622491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 76239d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 76249d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 76259d69cfa2SLijun Pan 76269d69cfa2SLijun Pan tcg_temp_free_i64(t1); 76279d69cfa2SLijun Pan tcg_temp_free_i64(t2); 76289d69cfa2SLijun Pan } 76299d69cfa2SLijun Pan #endif 76309d69cfa2SLijun Pan 7631fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 76329d69cfa2SLijun Pan #if defined(TARGET_PPC64) 76339d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 76349d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 76359d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 76369d69cfa2SLijun Pan #endif 7637fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7638fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7639fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7640fcf5ef2aSThomas Huth #endif 7641fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7642fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7643fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7644fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7645fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7646fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7647fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7648fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7649fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7650fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7651fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7652fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7653fcf5ef2aSThomas Huth #endif 7654fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7655fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7656fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7657fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7658fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7659fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7660fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 766180b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7662b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 766380b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7664fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7665fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7666fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7667fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7668fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7669fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7670fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7671fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7672fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7673fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7674fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7675fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7676fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7677fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7678fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7679fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7680fcf5ef2aSThomas Huth #endif 7681fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7682fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7683fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7684fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7685fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7686fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7687fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7688fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7689fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7690fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7691fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7692fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7693fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7694fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7695fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7696fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7697fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7698fcf5ef2aSThomas Huth #endif 7699fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7700fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7701fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7702fcf5ef2aSThomas Huth #endif 77035cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 77045cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7705d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7706e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7707fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7708fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7709fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7710fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7711fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7712fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7713c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7714fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7715fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7716fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7717fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7718a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7719a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7720fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7721fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7722fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7723fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7724a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7725a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7726fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7727fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7728fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7729fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7730fcf5ef2aSThomas Huth #endif 7731fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7732fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7733c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7734fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7735fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7736fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7737fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7738fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7739fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7740fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7741fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7742fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 77433c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 77443c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 77453c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 77463c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 77473c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 77483c89b8d6SNicholas Piggin #endif 7749cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7750fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7751fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7752fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7753fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7754fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7755fcf5ef2aSThomas Huth #endif 77563c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 77573c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 77583c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7759fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7760fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7761fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7762fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7763fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7764fcf5ef2aSThomas Huth #endif 7765fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7766fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7767fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7768fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7769fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7770fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7771fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7772fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7773fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7774b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7775fcf5ef2aSThomas Huth #endif 7776fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7777fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7778fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 777950728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7780fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7781fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 778250728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7783fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 778450728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7785fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 778650728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7787fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7788fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 778950728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7790fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 779199d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7792fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7793fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 779450728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7795fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7796fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7797fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7798fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7799fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7800fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7801fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7802fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7803fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7804fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7805fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7806fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7807fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7808fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7809fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7810fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7811fcf5ef2aSThomas Huth #endif 7812fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7813efe843d8SDavid Gibson /* 7814efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7815efe843d8SDavid Gibson * different ISA versions 7816efe843d8SDavid Gibson */ 7817fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7818fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7819c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7820c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7821fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7822fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7823fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7824fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7825a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 782662d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7827fcf5ef2aSThomas Huth #endif 7828fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7829fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7830fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7831fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7832fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7833fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7834fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7835fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7836fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7837fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7838fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7839fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7840fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7841fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7842fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7843fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7844fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7845fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7846fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7847fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7848fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7849fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7850fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7851fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7852fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7853fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7854fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7855fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7856fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7857fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7858fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7859fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7860fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7861fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7862fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7863fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7864fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7865fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7866fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7867fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7868fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7869fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7870fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7871fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7872fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7873fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7874fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7875fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7876fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7877fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7878fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7879fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7880fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7881fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7882fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7883fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7884fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7885fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7886fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7887fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7888fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7889fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7890fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7891fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7892fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7893fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7894fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7895fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7896fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7897fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7898fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7899fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7900fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7901fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7902fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7903fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7904fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7905fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7906fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7907fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7908fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7909fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7910fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7911fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7912fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7913fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7914fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7915fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7916fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7917fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7918fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7919fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7920fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7921fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 79227af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 79237af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7924fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7925fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7926fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7927fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7928fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 792927a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7930fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7931fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 79320c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 79330c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7934fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7935fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7936fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7937fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7938fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7939fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7940fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7941fcf5ef2aSThomas Huth PPC2_ISA300), 7942fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 79435ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 79445ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 79455ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 79465ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 7947fcf5ef2aSThomas Huth #endif 7948fcf5ef2aSThomas Huth 7949fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7950fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7951fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7952fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7953fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7954fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7955fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7956fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7957fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7958fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7959fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7960fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7961fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7962fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7963fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 79644c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7965fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7966fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7967fcf5ef2aSThomas Huth 7968fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7969fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7970fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7971fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7972fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7973fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7974fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7975fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7976fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7977fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7978fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7979fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7980fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7981fcf5ef2aSThomas Huth 7982fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7983fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7984fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7985fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7986fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7987fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7988fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7989fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7990fcf5ef2aSThomas Huth 7991fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7992fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7993fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7994fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7995fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7996fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7997fcf5ef2aSThomas Huth 7998fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7999fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8000fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8001fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8002fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8003fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8004fcf5ef2aSThomas Huth #endif 8005fcf5ef2aSThomas Huth 8006fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8007fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8008fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8009fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8010fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8011fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8012fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8013fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8014fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8015fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8016fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8017fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8018fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8019fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8020fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8021fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8022fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8023fcf5ef2aSThomas Huth 8024fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8025fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8026fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8027fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8028fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8029fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8030fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8031fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8032fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8033fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8034fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8035fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8036fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8037fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8038fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8039fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8040fcf5ef2aSThomas Huth #endif 8041fcf5ef2aSThomas Huth 8042fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8043fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8044fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8045fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8046fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8047fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8048fcf5ef2aSThomas Huth PPC_64B) 8049fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8050fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8051fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8052fcf5ef2aSThomas Huth PPC_64B), \ 8053fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8054fcf5ef2aSThomas Huth PPC_64B), \ 8055fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8056fcf5ef2aSThomas Huth PPC_64B) 8057fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8058fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8059fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8060fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8061fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8062fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8063fcf5ef2aSThomas Huth #endif 8064fcf5ef2aSThomas Huth 8065fcf5ef2aSThomas Huth #undef GEN_LDX_E 8066fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8067fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8068fcf5ef2aSThomas Huth 8069fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8070fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8071fcf5ef2aSThomas Huth 8072fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8073fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8074fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8075fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8076fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8077fcf5ef2aSThomas Huth #endif 8078fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8079fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8080fcf5ef2aSThomas Huth 808150728199SRoman Kapl /* External PID based load */ 808250728199SRoman Kapl #undef GEN_LDEPX 808350728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 808450728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 808550728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 808650728199SRoman Kapl 808750728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 808850728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 808950728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 809050728199SRoman Kapl #if defined(TARGET_PPC64) 809150728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 809250728199SRoman Kapl #endif 809350728199SRoman Kapl 8094fcf5ef2aSThomas Huth #undef GEN_STX_E 8095fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 80960123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8097fcf5ef2aSThomas Huth 8098fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8099fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8100fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8101fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8102fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8103fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8104fcf5ef2aSThomas Huth #endif 8105fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8106fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8107fcf5ef2aSThomas Huth 810850728199SRoman Kapl #undef GEN_STEPX 810950728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 811050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 811150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 811250728199SRoman Kapl 811350728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 811450728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 811550728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 811650728199SRoman Kapl #if defined(TARGET_PPC64) 811750728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 811850728199SRoman Kapl #endif 811950728199SRoman Kapl 8120fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8121fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8122fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8123fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8124fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8125fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8126fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8127fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8128fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8129fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8130fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8131fcf5ef2aSThomas Huth 8132fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8133fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8134fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8136fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8138fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8140fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8141fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8142fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8143fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8144fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8145fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8146fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8147fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8148fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8149fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8150fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8151fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8152fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8153fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8154fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8155fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8156fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8157fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8158fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8159fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8160fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8161fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8162fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8163fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8164fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8165fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8166fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8167fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8168fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8169fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8170fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8171fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8172fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8173fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8174fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8175fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8176fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8177fcf5ef2aSThomas Huth 8178fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8179fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8180fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8181fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8182fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8183fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8184fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8185fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8186fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8187fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8188fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8189fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8190fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8191fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8192fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8193fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8194fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8195fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8196fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8197fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8198fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8199fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8200fcf5ef2aSThomas Huth 8201139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8202fcf5ef2aSThomas Huth 8203139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8204fcf5ef2aSThomas Huth 8205139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8206fcf5ef2aSThomas Huth 8207139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8208fcf5ef2aSThomas Huth 8209139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8210fcf5ef2aSThomas Huth }; 8211fcf5ef2aSThomas Huth 82127468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 82137468e2c8SBruno Larsen (billionai) /* Opcode types */ 82147468e2c8SBruno Larsen (billionai) enum { 82157468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 82167468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 82177468e2c8SBruno Larsen (billionai) }; 82187468e2c8SBruno Larsen (billionai) 82197468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 82207468e2c8SBruno Larsen (billionai) 82217468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 82227468e2c8SBruno Larsen (billionai) { 82237468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 82247468e2c8SBruno Larsen (billionai) } 82257468e2c8SBruno Larsen (billionai) 82267468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 82277468e2c8SBruno Larsen (billionai) { 82287468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 82297468e2c8SBruno Larsen (billionai) } 82307468e2c8SBruno Larsen (billionai) 82317468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 82327468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 82337468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 82347468e2c8SBruno Larsen (billionai) { 82357468e2c8SBruno Larsen (billionai) int i; 82367468e2c8SBruno Larsen (billionai) 82377468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 82387468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 82397468e2c8SBruno Larsen (billionai) } 82407468e2c8SBruno Larsen (billionai) } 82417468e2c8SBruno Larsen (billionai) 82427468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 82437468e2c8SBruno Larsen (billionai) { 82447468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 82457468e2c8SBruno Larsen (billionai) 82467468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 82477468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 82487468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 82497468e2c8SBruno Larsen (billionai) 82507468e2c8SBruno Larsen (billionai) return 0; 82517468e2c8SBruno Larsen (billionai) } 82527468e2c8SBruno Larsen (billionai) 82537468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 82547468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82557468e2c8SBruno Larsen (billionai) { 82567468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 82577468e2c8SBruno Larsen (billionai) return -1; 82587468e2c8SBruno Larsen (billionai) } 82597468e2c8SBruno Larsen (billionai) table[idx] = handler; 82607468e2c8SBruno Larsen (billionai) 82617468e2c8SBruno Larsen (billionai) return 0; 82627468e2c8SBruno Larsen (billionai) } 82637468e2c8SBruno Larsen (billionai) 82647468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 82657468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 82667468e2c8SBruno Larsen (billionai) { 82677468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 82687468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 82697468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 82707468e2c8SBruno Larsen (billionai) return -1; 82717468e2c8SBruno Larsen (billionai) } 82727468e2c8SBruno Larsen (billionai) 82737468e2c8SBruno Larsen (billionai) return 0; 82747468e2c8SBruno Larsen (billionai) } 82757468e2c8SBruno Larsen (billionai) 82767468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 82777468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82787468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82797468e2c8SBruno Larsen (billionai) { 82807468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 82817468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 82827468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 82837468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 82847468e2c8SBruno Larsen (billionai) return -1; 82857468e2c8SBruno Larsen (billionai) } 82867468e2c8SBruno Larsen (billionai) } else { 82877468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 82887468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 82897468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 82907468e2c8SBruno Larsen (billionai) return -1; 82917468e2c8SBruno Larsen (billionai) } 82927468e2c8SBruno Larsen (billionai) } 82937468e2c8SBruno Larsen (billionai) if (handler != NULL && 82947468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 82957468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 82967468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 82977468e2c8SBruno Larsen (billionai) return -1; 82987468e2c8SBruno Larsen (billionai) } 82997468e2c8SBruno Larsen (billionai) 83007468e2c8SBruno Larsen (billionai) return 0; 83017468e2c8SBruno Larsen (billionai) } 83027468e2c8SBruno Larsen (billionai) 83037468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 83047468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 83057468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 83067468e2c8SBruno Larsen (billionai) { 83077468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 83087468e2c8SBruno Larsen (billionai) } 83097468e2c8SBruno Larsen (billionai) 83107468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 83117468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 83127468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 83137468e2c8SBruno Larsen (billionai) { 83147468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 83157468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 83167468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 83177468e2c8SBruno Larsen (billionai) return -1; 83187468e2c8SBruno Larsen (billionai) } 83197468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 83207468e2c8SBruno Larsen (billionai) handler) < 0) { 83217468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 83227468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 83237468e2c8SBruno Larsen (billionai) return -1; 83247468e2c8SBruno Larsen (billionai) } 83257468e2c8SBruno Larsen (billionai) 83267468e2c8SBruno Larsen (billionai) return 0; 83277468e2c8SBruno Larsen (billionai) } 83287468e2c8SBruno Larsen (billionai) 83297468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 83307468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 83317468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 83327468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 83337468e2c8SBruno Larsen (billionai) { 83347468e2c8SBruno Larsen (billionai) opc_handler_t **table; 83357468e2c8SBruno Larsen (billionai) 83367468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 83377468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 83387468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 83397468e2c8SBruno Larsen (billionai) return -1; 83407468e2c8SBruno Larsen (billionai) } 83417468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 83427468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 83437468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 83447468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 83457468e2c8SBruno Larsen (billionai) return -1; 83467468e2c8SBruno Larsen (billionai) } 83477468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 83487468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 83497468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 83507468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 83517468e2c8SBruno Larsen (billionai) return -1; 83527468e2c8SBruno Larsen (billionai) } 83537468e2c8SBruno Larsen (billionai) return 0; 83547468e2c8SBruno Larsen (billionai) } 83557468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 83567468e2c8SBruno Larsen (billionai) { 83577468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 83587468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 83597468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 83607468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 83617468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 83627468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 83637468e2c8SBruno Larsen (billionai) return -1; 83647468e2c8SBruno Larsen (billionai) } 83657468e2c8SBruno Larsen (billionai) } else { 83667468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 83677468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 83687468e2c8SBruno Larsen (billionai) return -1; 83697468e2c8SBruno Larsen (billionai) } 83707468e2c8SBruno Larsen (billionai) } 83717468e2c8SBruno Larsen (billionai) } else { 83727468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 83737468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 83747468e2c8SBruno Larsen (billionai) return -1; 83757468e2c8SBruno Larsen (billionai) } 83767468e2c8SBruno Larsen (billionai) } 83777468e2c8SBruno Larsen (billionai) } else { 83787468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 83797468e2c8SBruno Larsen (billionai) return -1; 83807468e2c8SBruno Larsen (billionai) } 83817468e2c8SBruno Larsen (billionai) } 83827468e2c8SBruno Larsen (billionai) 83837468e2c8SBruno Larsen (billionai) return 0; 83847468e2c8SBruno Larsen (billionai) } 83857468e2c8SBruno Larsen (billionai) 83867468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 83877468e2c8SBruno Larsen (billionai) { 83887468e2c8SBruno Larsen (billionai) int i, count, tmp; 83897468e2c8SBruno Larsen (billionai) 83907468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 83917468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 83927468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 83937468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83947468e2c8SBruno Larsen (billionai) } 83957468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 83967468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 83977468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 83987468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 83997468e2c8SBruno Larsen (billionai) if (tmp == 0) { 84007468e2c8SBruno Larsen (billionai) free(table[i]); 84017468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 84027468e2c8SBruno Larsen (billionai) } else { 84037468e2c8SBruno Larsen (billionai) count++; 84047468e2c8SBruno Larsen (billionai) } 84057468e2c8SBruno Larsen (billionai) } else { 84067468e2c8SBruno Larsen (billionai) count++; 84077468e2c8SBruno Larsen (billionai) } 84087468e2c8SBruno Larsen (billionai) } 84097468e2c8SBruno Larsen (billionai) } 84107468e2c8SBruno Larsen (billionai) 84117468e2c8SBruno Larsen (billionai) return count; 84127468e2c8SBruno Larsen (billionai) } 84137468e2c8SBruno Larsen (billionai) 84147468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 84157468e2c8SBruno Larsen (billionai) { 84167468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 84177468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 84187468e2c8SBruno Larsen (billionai) } 84197468e2c8SBruno Larsen (billionai) } 84207468e2c8SBruno Larsen (billionai) 84217468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 84227468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 84237468e2c8SBruno Larsen (billionai) { 84247468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 84257468e2c8SBruno Larsen (billionai) opcode_t *opc; 84267468e2c8SBruno Larsen (billionai) 84277468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 84287468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 84297468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 84307468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 84317468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 84327468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 84337468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 84347468e2c8SBruno Larsen (billionai) opc->opc3); 84357468e2c8SBruno Larsen (billionai) return; 84367468e2c8SBruno Larsen (billionai) } 84377468e2c8SBruno Larsen (billionai) } 84387468e2c8SBruno Larsen (billionai) } 84397468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 84407468e2c8SBruno Larsen (billionai) fflush(stdout); 84417468e2c8SBruno Larsen (billionai) fflush(stderr); 84427468e2c8SBruno Larsen (billionai) } 84437468e2c8SBruno Larsen (billionai) 84447468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 84457468e2c8SBruno Larsen (billionai) { 84467468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 84477468e2c8SBruno Larsen (billionai) int i, j, k; 84487468e2c8SBruno Larsen (billionai) 84497468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 84507468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 84517468e2c8SBruno Larsen (billionai) continue; 84527468e2c8SBruno Larsen (billionai) } 84537468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 84547468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 84557468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 84567468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 84577468e2c8SBruno Larsen (billionai) continue; 84587468e2c8SBruno Larsen (billionai) } 84597468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 84607468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 84617468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 84627468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 84637468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 84647468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 84657468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84667468e2c8SBruno Larsen (billionai) } 84677468e2c8SBruno Larsen (billionai) } 84687468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 84697468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84707468e2c8SBruno Larsen (billionai) } 84717468e2c8SBruno Larsen (billionai) } 84727468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 84737468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84747468e2c8SBruno Larsen (billionai) } 84757468e2c8SBruno Larsen (billionai) } 84767468e2c8SBruno Larsen (billionai) } 84777468e2c8SBruno Larsen (billionai) 84787468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 84797468e2c8SBruno Larsen (billionai) { 84807468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 84817468e2c8SBruno Larsen (billionai) 84827468e2c8SBruno Larsen (billionai) /* 84837468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 84847468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 84857468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 84867468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 84877468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 84887468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 84897468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 84907468e2c8SBruno Larsen (billionai) */ 84917468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 84927468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 84937468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 84947468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 84957468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 84967468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 84977468e2c8SBruno Larsen (billionai) } 84987468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 84997468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 85007468e2c8SBruno Larsen (billionai) return 0; 85017468e2c8SBruno Larsen (billionai) } 85027468e2c8SBruno Larsen (billionai) 8503624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8504624cb07fSRichard Henderson { 8505624cb07fSRichard Henderson opc_handler_t **table, *handler; 8506624cb07fSRichard Henderson uint32_t inval; 8507624cb07fSRichard Henderson 8508624cb07fSRichard Henderson ctx->opcode = insn; 8509624cb07fSRichard Henderson 8510624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8511624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8512624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8513624cb07fSRichard Henderson 8514624cb07fSRichard Henderson table = cpu->opcodes; 8515624cb07fSRichard Henderson handler = table[opc1(insn)]; 8516624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8517624cb07fSRichard Henderson table = ind_table(handler); 8518624cb07fSRichard Henderson handler = table[opc2(insn)]; 8519624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8520624cb07fSRichard Henderson table = ind_table(handler); 8521624cb07fSRichard Henderson handler = table[opc3(insn)]; 8522624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8523624cb07fSRichard Henderson table = ind_table(handler); 8524624cb07fSRichard Henderson handler = table[opc4(insn)]; 8525624cb07fSRichard Henderson } 8526624cb07fSRichard Henderson } 8527624cb07fSRichard Henderson } 8528624cb07fSRichard Henderson 8529624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8530624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8531624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8532624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8533624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8534624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8535624cb07fSRichard Henderson insn, ctx->cia); 8536624cb07fSRichard Henderson return false; 8537624cb07fSRichard Henderson } 8538624cb07fSRichard Henderson 8539624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8540624cb07fSRichard Henderson && Rc(insn))) { 8541624cb07fSRichard Henderson inval = handler->inval2; 8542624cb07fSRichard Henderson } else { 8543624cb07fSRichard Henderson inval = handler->inval1; 8544624cb07fSRichard Henderson } 8545624cb07fSRichard Henderson 8546624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8547624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8548624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8549624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8550624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8551624cb07fSRichard Henderson insn, ctx->cia); 8552624cb07fSRichard Henderson return false; 8553624cb07fSRichard Henderson } 8554624cb07fSRichard Henderson 8555624cb07fSRichard Henderson handler->handler(ctx); 8556624cb07fSRichard Henderson return true; 8557624cb07fSRichard Henderson } 8558624cb07fSRichard Henderson 8559b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8560fcf5ef2aSThomas Huth { 8561b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 85629c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 85632df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8564fcf5ef2aSThomas Huth 8565b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 85662df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8567d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 85682df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 85692df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 8570b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 8571b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 8572b0c2d521SEmilio G. Cota ctx->access_type = -1; 8573d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 85742df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8575b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 85760e3bf489SRoman Kapl ctx->flags = env->flags; 8577fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 85782df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8579b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8580fcf5ef2aSThomas Huth #endif 8581e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8582e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 8583d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 8584fcf5ef2aSThomas Huth 85852df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 85862df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 85872df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 85882df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 85892df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8590f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 85911db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 8592f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 8593f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 85942df4fe7aSRichard Henderson 8595b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 85962df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 85972df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 85989498d103SRichard Henderson ctx->base.max_insns = 1; 8599efe843d8SDavid Gibson } 86002df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 8601b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8602efe843d8SDavid Gibson } 860313b45575SRichard Henderson } 8604fcf5ef2aSThomas Huth 8605b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8606b0c2d521SEmilio G. Cota { 8607b0c2d521SEmilio G. Cota } 8608fcf5ef2aSThomas Huth 8609b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8610b0c2d521SEmilio G. Cota { 8611b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 8612b0c2d521SEmilio G. Cota } 8613b0c2d521SEmilio G. Cota 861499082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 861599082815SRichard Henderson { 861699082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 861799082815SRichard Henderson return opc1(insn) == 1; 861899082815SRichard Henderson } 861999082815SRichard Henderson 8620b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8621b0c2d521SEmilio G. Cota { 8622b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 862328876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 8624b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 862599082815SRichard Henderson target_ulong pc; 8626624cb07fSRichard Henderson uint32_t insn; 8627624cb07fSRichard Henderson bool ok; 8628b0c2d521SEmilio G. Cota 8629fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 8630fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8631b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8632b0c2d521SEmilio G. Cota 863399082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 86344e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 863599082815SRichard Henderson ctx->base.pc_next = pc += 4; 8636fcf5ef2aSThomas Huth 863799082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 863899082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 863999082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 864099082815SRichard Henderson } else if ((pc & 63) == 0) { 864199082815SRichard Henderson /* 864299082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 864399082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 864499082815SRichard Henderson * 64-byte address boundary (system alignment error). 864599082815SRichard Henderson */ 864699082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 864799082815SRichard Henderson ok = true; 864899082815SRichard Henderson } else { 86494e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 86504e116893SIlya Leoshkevich need_byteswap(ctx)); 865199082815SRichard Henderson ctx->base.pc_next = pc += 4; 865299082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 865399082815SRichard Henderson } 8654624cb07fSRichard Henderson if (!ok) { 8655624cb07fSRichard Henderson gen_invalid(ctx); 8656fcf5ef2aSThomas Huth } 8657624cb07fSRichard Henderson 865864a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 865999082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 866064a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 866164a0f644SRichard Henderson } 866264a0f644SRichard Henderson 866351eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 8664fcf5ef2aSThomas Huth } 8665b0c2d521SEmilio G. Cota 8666b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8667b0c2d521SEmilio G. Cota { 8668b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8669a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 8670a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 8671b0c2d521SEmilio G. Cota 8672a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 8673a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 86743d8a5b69SRichard Henderson return; 86753d8a5b69SRichard Henderson } 86763d8a5b69SRichard Henderson 8677a9b5b3d0SRichard Henderson /* Honor single stepping. */ 86789498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 86799498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 8680a9b5b3d0SRichard Henderson switch (is_jmp) { 8681a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8682a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8683a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8684a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8685a9b5b3d0SRichard Henderson break; 8686a9b5b3d0SRichard Henderson case DISAS_EXIT: 8687a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8688a9b5b3d0SRichard Henderson break; 8689a9b5b3d0SRichard Henderson default: 8690a9b5b3d0SRichard Henderson g_assert_not_reached(); 8691fcf5ef2aSThomas Huth } 869213b45575SRichard Henderson 8693a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 8694a9b5b3d0SRichard Henderson return; 8695a9b5b3d0SRichard Henderson } 8696a9b5b3d0SRichard Henderson 8697a9b5b3d0SRichard Henderson switch (is_jmp) { 8698a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8699a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 8700a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 8701a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8702a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 8703a9b5b3d0SRichard Henderson break; 8704a9b5b3d0SRichard Henderson } 8705a9b5b3d0SRichard Henderson /* fall through */ 8706a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8707a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8708a9b5b3d0SRichard Henderson /* fall through */ 8709a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8710a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 8711a9b5b3d0SRichard Henderson break; 8712a9b5b3d0SRichard Henderson 8713a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8714a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8715a9b5b3d0SRichard Henderson /* fall through */ 8716a9b5b3d0SRichard Henderson case DISAS_EXIT: 871707ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8718a9b5b3d0SRichard Henderson break; 8719a9b5b3d0SRichard Henderson 8720a9b5b3d0SRichard Henderson default: 8721a9b5b3d0SRichard Henderson g_assert_not_reached(); 8722fcf5ef2aSThomas Huth } 8723fcf5ef2aSThomas Huth } 8724b0c2d521SEmilio G. Cota 8725b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8726b0c2d521SEmilio G. Cota { 8727b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8728b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8729b0c2d521SEmilio G. Cota } 8730b0c2d521SEmilio G. Cota 8731b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8732b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8733b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8734b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8735b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8736b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8737b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8738b0c2d521SEmilio G. Cota }; 8739b0c2d521SEmilio G. Cota 87408b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8741b0c2d521SEmilio G. Cota { 8742b0c2d521SEmilio G. Cota DisasContext ctx; 8743b0c2d521SEmilio G. Cota 87448b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8745fcf5ef2aSThomas Huth } 8746fcf5ef2aSThomas Huth 8747fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8748fcf5ef2aSThomas Huth target_ulong *data) 8749fcf5ef2aSThomas Huth { 8750fcf5ef2aSThomas Huth env->nip = data[0]; 8751fcf5ef2aSThomas Huth } 8752