1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 38a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 39fcf5ef2aSThomas Huth 403e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 413e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 44fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 47efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 1572c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 158fcf5ef2aSThomas Huth uint32_t opcode; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 1771db3632aSMatheus Ferst bool hr; 178fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 179fcf5ef2aSThomas Huth int singlestep_enabled; 1800e3bf489SRoman Kapl uint32_t flags; 181fcf5ef2aSThomas Huth uint64_t insns_flags; 182fcf5ef2aSThomas Huth uint64_t insns_flags2; 183fcf5ef2aSThomas Huth }; 184fcf5ef2aSThomas Huth 185a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 186a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 187a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 188a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 189a9b5b3d0SRichard Henderson 190fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 191fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 192fcf5ef2aSThomas Huth { 193fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 194fcf5ef2aSThomas Huth return ctx->le_mode; 195fcf5ef2aSThomas Huth #else 196fcf5ef2aSThomas Huth return !ctx->le_mode; 197fcf5ef2aSThomas Huth #endif 198fcf5ef2aSThomas Huth } 199fcf5ef2aSThomas Huth 200fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 201fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 202fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 203fcf5ef2aSThomas Huth #else 204fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 205fcf5ef2aSThomas Huth #endif 206fcf5ef2aSThomas Huth 207fcf5ef2aSThomas Huth struct opc_handler_t { 208fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 209fcf5ef2aSThomas Huth uint32_t inval1; 210fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 211fcf5ef2aSThomas Huth uint32_t inval2; 212fcf5ef2aSThomas Huth /* instruction type */ 213fcf5ef2aSThomas Huth uint64_t type; 214fcf5ef2aSThomas Huth /* extended instruction type */ 215fcf5ef2aSThomas Huth uint64_t type2; 216fcf5ef2aSThomas Huth /* handler */ 217fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 218fcf5ef2aSThomas Huth }; 219fcf5ef2aSThomas Huth 2200e3bf489SRoman Kapl /* SPR load/store helpers */ 2210e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2220e3bf489SRoman Kapl { 2230e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2240e3bf489SRoman Kapl } 2250e3bf489SRoman Kapl 2260e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2270e3bf489SRoman Kapl { 2280e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2290e3bf489SRoman Kapl } 2300e3bf489SRoman Kapl 231fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 232fcf5ef2aSThomas Huth { 233fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 234fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 235fcf5ef2aSThomas Huth ctx->access_type = access_type; 236fcf5ef2aSThomas Huth } 237fcf5ef2aSThomas Huth } 238fcf5ef2aSThomas Huth 239fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 240fcf5ef2aSThomas Huth { 241fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 242fcf5ef2aSThomas Huth nip = (uint32_t)nip; 243fcf5ef2aSThomas Huth } 244fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 245fcf5ef2aSThomas Huth } 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 248fcf5ef2aSThomas Huth { 249fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 250fcf5ef2aSThomas Huth 251efe843d8SDavid Gibson /* 252efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 253efe843d8SDavid Gibson * faulting instruction 254fcf5ef2aSThomas Huth */ 2552c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 256fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 257fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 258fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 259fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 260fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2613d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 262fcf5ef2aSThomas Huth } 263fcf5ef2aSThomas Huth 264fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 265fcf5ef2aSThomas Huth { 266fcf5ef2aSThomas Huth TCGv_i32 t0; 267fcf5ef2aSThomas Huth 268efe843d8SDavid Gibson /* 269efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 270efe843d8SDavid Gibson * faulting instruction 271fcf5ef2aSThomas Huth */ 2722c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 273fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 274fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 275fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2763d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 277fcf5ef2aSThomas Huth } 278fcf5ef2aSThomas Huth 279fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 280fcf5ef2aSThomas Huth target_ulong nip) 281fcf5ef2aSThomas Huth { 282fcf5ef2aSThomas Huth TCGv_i32 t0; 283fcf5ef2aSThomas Huth 284fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 285fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 286fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 287fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2883d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 289fcf5ef2aSThomas Huth } 290fcf5ef2aSThomas Huth 291f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 292f5b6daacSRichard Henderson { 293f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 294f5b6daacSRichard Henderson gen_io_start(); 295f5b6daacSRichard Henderson /* 296f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 297f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 298f5b6daacSRichard Henderson * decide if we need to return to the main loop. 299f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 300f5b6daacSRichard Henderson */ 301f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 302f5b6daacSRichard Henderson } 303f5b6daacSRichard Henderson } 304f5b6daacSRichard Henderson 305e150ac89SRoman Kapl /* 306e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 307e150ac89SRoman Kapl * SPR registers for this exception. 308e150ac89SRoman Kapl * 309e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 310e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3110e3bf489SRoman Kapl */ 312e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3130e3bf489SRoman Kapl { 3140e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3150e3bf489SRoman Kapl target_ulong dbsr = 0; 316e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3170e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 318e150ac89SRoman Kapl } else { 319e150ac89SRoman Kapl /* Must have been branch */ 3200e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3210e3bf489SRoman Kapl } 3220e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3230e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3240e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3250e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3260e3bf489SRoman Kapl tcg_temp_free(t0); 3270e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3280e3bf489SRoman Kapl } else { 329e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3300e3bf489SRoman Kapl } 3310e3bf489SRoman Kapl } 3320e3bf489SRoman Kapl 333fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 334fcf5ef2aSThomas Huth { 3359498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3363d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 337fcf5ef2aSThomas Huth } 338fcf5ef2aSThomas Huth 339fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 340fcf5ef2aSThomas Huth { 341fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 342fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 343fcf5ef2aSThomas Huth } 344fcf5ef2aSThomas Huth 345fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 346fcf5ef2aSThomas Huth { 347fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 348fcf5ef2aSThomas Huth } 349fcf5ef2aSThomas Huth 350fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 351fcf5ef2aSThomas Huth { 352fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 353fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 354fcf5ef2aSThomas Huth } 355fcf5ef2aSThomas Huth 35637f219c8SBruno Larsen (billionai) /*****************************************************************************/ 35737f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 35837f219c8SBruno Larsen (billionai) 359a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36037f219c8SBruno Larsen (billionai) { 36137f219c8SBruno Larsen (billionai) #if 0 36237f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36337f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36437f219c8SBruno Larsen (billionai) #endif 36537f219c8SBruno Larsen (billionai) } 36637f219c8SBruno Larsen (billionai) 36737f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 36837f219c8SBruno Larsen (billionai) 36937f219c8SBruno Larsen (billionai) /* 37037f219c8SBruno Larsen (billionai) * Generic callbacks: 37137f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37237f219c8SBruno Larsen (billionai) */ 37337f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37437f219c8SBruno Larsen (billionai) { 37537f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 37737f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 37837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 37937f219c8SBruno Larsen (billionai) #endif 38037f219c8SBruno Larsen (billionai) } 38137f219c8SBruno Larsen (billionai) 382a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38337f219c8SBruno Larsen (billionai) { 38437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38537f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38637f219c8SBruno Larsen (billionai) } 38737f219c8SBruno Larsen (billionai) 38837f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 38937f219c8SBruno Larsen (billionai) { 39037f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39237f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39437f219c8SBruno Larsen (billionai) #endif 39537f219c8SBruno Larsen (billionai) } 39637f219c8SBruno Larsen (billionai) 397a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 39837f219c8SBruno Larsen (billionai) { 39937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40037f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40137f219c8SBruno Larsen (billionai) } 40237f219c8SBruno Larsen (billionai) 40337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 404a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 40537f219c8SBruno Larsen (billionai) { 40637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 40737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 40837f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 40937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 41037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 41137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41237f219c8SBruno Larsen (billionai) #else 41337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 41437f219c8SBruno Larsen (billionai) #endif 41537f219c8SBruno Larsen (billionai) } 41637f219c8SBruno Larsen (billionai) 417a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 41837f219c8SBruno Larsen (billionai) { 41937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 42137f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 42237f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 42337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 42437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42637f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 42737f219c8SBruno Larsen (billionai) } 42837f219c8SBruno Larsen (billionai) 429a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 43037f219c8SBruno Larsen (billionai) { 43137f219c8SBruno Larsen (billionai) } 43237f219c8SBruno Larsen (billionai) 43337f219c8SBruno Larsen (billionai) #endif 43437f219c8SBruno Larsen (billionai) 43537f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 43637f219c8SBruno Larsen (billionai) /* XER */ 437a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 43837f219c8SBruno Larsen (billionai) { 43937f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 44037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 44337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 44437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 44537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 44637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 44737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 44837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 44937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45037f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 45137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 45237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 45437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45537f219c8SBruno Larsen (billionai) } 45637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 45837f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 45937f219c8SBruno Larsen (billionai) } 46037f219c8SBruno Larsen (billionai) 461a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 46237f219c8SBruno Larsen (billionai) { 46337f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 46437f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 46537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 46637f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 46737f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 46837f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 46937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 47037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 47137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 47237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 47337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 47437f219c8SBruno Larsen (billionai) } 47537f219c8SBruno Larsen (billionai) 47637f219c8SBruno Larsen (billionai) /* LR */ 477a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 47837f219c8SBruno Larsen (billionai) { 47937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 48037f219c8SBruno Larsen (billionai) } 48137f219c8SBruno Larsen (billionai) 482a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 48337f219c8SBruno Larsen (billionai) { 48437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 48537f219c8SBruno Larsen (billionai) } 48637f219c8SBruno Larsen (billionai) 48737f219c8SBruno Larsen (billionai) /* CFAR */ 48837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 489a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 49037f219c8SBruno Larsen (billionai) { 49137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 49237f219c8SBruno Larsen (billionai) } 49337f219c8SBruno Larsen (billionai) 494a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 49537f219c8SBruno Larsen (billionai) { 49637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 49737f219c8SBruno Larsen (billionai) } 49837f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 49937f219c8SBruno Larsen (billionai) 50037f219c8SBruno Larsen (billionai) /* CTR */ 501a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 50237f219c8SBruno Larsen (billionai) { 50337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 50437f219c8SBruno Larsen (billionai) } 50537f219c8SBruno Larsen (billionai) 506a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 50737f219c8SBruno Larsen (billionai) { 50837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 50937f219c8SBruno Larsen (billionai) } 51037f219c8SBruno Larsen (billionai) 51137f219c8SBruno Larsen (billionai) /* User read access to SPR */ 51237f219c8SBruno Larsen (billionai) /* USPRx */ 51337f219c8SBruno Larsen (billionai) /* UMMCRx */ 51437f219c8SBruno Larsen (billionai) /* UPMCx */ 51537f219c8SBruno Larsen (billionai) /* USIA */ 51637f219c8SBruno Larsen (billionai) /* UDECR */ 517a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 51837f219c8SBruno Larsen (billionai) { 51937f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 52037f219c8SBruno Larsen (billionai) } 52137f219c8SBruno Larsen (billionai) 52237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 523a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 52437f219c8SBruno Larsen (billionai) { 52537f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 52637f219c8SBruno Larsen (billionai) } 52737f219c8SBruno Larsen (billionai) #endif 52837f219c8SBruno Larsen (billionai) 52937f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 53037f219c8SBruno Larsen (billionai) /* DECR */ 53137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 532a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 53337f219c8SBruno Larsen (billionai) { 534f5b6daacSRichard Henderson gen_icount_io_start(ctx); 53537f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 53637f219c8SBruno Larsen (billionai) } 53737f219c8SBruno Larsen (billionai) 538a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 53937f219c8SBruno Larsen (billionai) { 540f5b6daacSRichard Henderson gen_icount_io_start(ctx); 54137f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 54237f219c8SBruno Larsen (billionai) } 54337f219c8SBruno Larsen (billionai) #endif 54437f219c8SBruno Larsen (billionai) 54537f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 54637f219c8SBruno Larsen (billionai) /* Time base */ 547a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 54837f219c8SBruno Larsen (billionai) { 549f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55037f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 55137f219c8SBruno Larsen (billionai) } 55237f219c8SBruno Larsen (billionai) 553a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 55437f219c8SBruno Larsen (billionai) { 555f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55637f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 55737f219c8SBruno Larsen (billionai) } 55837f219c8SBruno Larsen (billionai) 559a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 56037f219c8SBruno Larsen (billionai) { 56137f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 56237f219c8SBruno Larsen (billionai) } 56337f219c8SBruno Larsen (billionai) 564a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 56537f219c8SBruno Larsen (billionai) { 56637f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 56737f219c8SBruno Larsen (billionai) } 56837f219c8SBruno Larsen (billionai) 56937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 570a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 57137f219c8SBruno Larsen (billionai) { 572f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57337f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 57437f219c8SBruno Larsen (billionai) } 57537f219c8SBruno Larsen (billionai) 576a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 57737f219c8SBruno Larsen (billionai) { 578f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57937f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 58037f219c8SBruno Larsen (billionai) } 58137f219c8SBruno Larsen (billionai) 582a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 58337f219c8SBruno Larsen (billionai) { 58437f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 58537f219c8SBruno Larsen (billionai) } 58637f219c8SBruno Larsen (billionai) 587a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 58837f219c8SBruno Larsen (billionai) { 58937f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 59037f219c8SBruno Larsen (billionai) } 59137f219c8SBruno Larsen (billionai) 59237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 593a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 59437f219c8SBruno Larsen (billionai) { 595f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59637f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 59737f219c8SBruno Larsen (billionai) } 59837f219c8SBruno Larsen (billionai) 599a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 60037f219c8SBruno Larsen (billionai) { 601f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60237f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 60337f219c8SBruno Larsen (billionai) } 60437f219c8SBruno Larsen (billionai) 60537f219c8SBruno Larsen (billionai) /* HDECR */ 606a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 60737f219c8SBruno Larsen (billionai) { 608f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60937f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 61037f219c8SBruno Larsen (billionai) } 61137f219c8SBruno Larsen (billionai) 612a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 61337f219c8SBruno Larsen (billionai) { 614f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61537f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 61637f219c8SBruno Larsen (billionai) } 61737f219c8SBruno Larsen (billionai) 618a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 61937f219c8SBruno Larsen (billionai) { 620f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62137f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 62237f219c8SBruno Larsen (billionai) } 62337f219c8SBruno Larsen (billionai) 624a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 62537f219c8SBruno Larsen (billionai) { 626f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62737f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 62837f219c8SBruno Larsen (billionai) } 62937f219c8SBruno Larsen (billionai) 630a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 63137f219c8SBruno Larsen (billionai) { 632f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63337f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 63437f219c8SBruno Larsen (billionai) } 63537f219c8SBruno Larsen (billionai) 63637f219c8SBruno Larsen (billionai) #endif 63737f219c8SBruno Larsen (billionai) #endif 63837f219c8SBruno Larsen (billionai) 63937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 64037f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 64137f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 642a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 64337f219c8SBruno Larsen (billionai) { 64437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 64537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 64637f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 64737f219c8SBruno Larsen (billionai) } 64837f219c8SBruno Larsen (billionai) 649a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 65037f219c8SBruno Larsen (billionai) { 65137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 65237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 65337f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 65437f219c8SBruno Larsen (billionai) } 65537f219c8SBruno Larsen (billionai) 656a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 65737f219c8SBruno Larsen (billionai) { 65837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 65937f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66137f219c8SBruno Larsen (billionai) } 66237f219c8SBruno Larsen (billionai) 663a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 66437f219c8SBruno Larsen (billionai) { 66537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 66637f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66837f219c8SBruno Larsen (billionai) } 66937f219c8SBruno Larsen (billionai) 670a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 67137f219c8SBruno Larsen (billionai) { 67237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 67337f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 67437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67537f219c8SBruno Larsen (billionai) } 67637f219c8SBruno Larsen (billionai) 677a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 67837f219c8SBruno Larsen (billionai) { 67937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 68037f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68237f219c8SBruno Larsen (billionai) } 68337f219c8SBruno Larsen (billionai) 68437f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 68537f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 686a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 68737f219c8SBruno Larsen (billionai) { 68837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 68937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69037f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 69137f219c8SBruno Larsen (billionai) } 69237f219c8SBruno Larsen (billionai) 693a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 69437f219c8SBruno Larsen (billionai) { 69537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69737f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 69837f219c8SBruno Larsen (billionai) } 69937f219c8SBruno Larsen (billionai) 700a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 70137f219c8SBruno Larsen (billionai) { 70237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 70337f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 70437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70537f219c8SBruno Larsen (billionai) } 70637f219c8SBruno Larsen (billionai) 707a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 70837f219c8SBruno Larsen (billionai) { 70937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 71037f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71237f219c8SBruno Larsen (billionai) } 71337f219c8SBruno Larsen (billionai) 714a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 71537f219c8SBruno Larsen (billionai) { 71637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 71737f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 71837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71937f219c8SBruno Larsen (billionai) } 72037f219c8SBruno Larsen (billionai) 721a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 72237f219c8SBruno Larsen (billionai) { 72337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 72437f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72637f219c8SBruno Larsen (billionai) } 72737f219c8SBruno Larsen (billionai) 72837f219c8SBruno Larsen (billionai) /* SDR1 */ 729a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 73037f219c8SBruno Larsen (billionai) { 73137f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 73237f219c8SBruno Larsen (billionai) } 73337f219c8SBruno Larsen (billionai) 73437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 73537f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 73637f219c8SBruno Larsen (billionai) /* PIDR */ 737a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 73837f219c8SBruno Larsen (billionai) { 73937f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 74037f219c8SBruno Larsen (billionai) } 74137f219c8SBruno Larsen (billionai) 742a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 74337f219c8SBruno Larsen (billionai) { 74437f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 74537f219c8SBruno Larsen (billionai) } 74637f219c8SBruno Larsen (billionai) 747a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 74837f219c8SBruno Larsen (billionai) { 74937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 75037f219c8SBruno Larsen (billionai) } 75137f219c8SBruno Larsen (billionai) 752a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 75337f219c8SBruno Larsen (billionai) { 75437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 75537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 75637f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 75737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 75837f219c8SBruno Larsen (billionai) } 759a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 76037f219c8SBruno Larsen (billionai) { 76137f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 76237f219c8SBruno Larsen (billionai) } 76337f219c8SBruno Larsen (billionai) 764a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 76537f219c8SBruno Larsen (billionai) { 76637f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 76737f219c8SBruno Larsen (billionai) } 76837f219c8SBruno Larsen (billionai) 76937f219c8SBruno Larsen (billionai) /* DPDES */ 770a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 77137f219c8SBruno Larsen (billionai) { 77237f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 77337f219c8SBruno Larsen (billionai) } 77437f219c8SBruno Larsen (billionai) 775a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 77637f219c8SBruno Larsen (billionai) { 77737f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 77837f219c8SBruno Larsen (billionai) } 77937f219c8SBruno Larsen (billionai) #endif 78037f219c8SBruno Larsen (billionai) #endif 78137f219c8SBruno Larsen (billionai) 78237f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 78337f219c8SBruno Larsen (billionai) /* RTC */ 784a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 78537f219c8SBruno Larsen (billionai) { 78637f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 78737f219c8SBruno Larsen (billionai) } 78837f219c8SBruno Larsen (billionai) 789a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 79037f219c8SBruno Larsen (billionai) { 79137f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 79237f219c8SBruno Larsen (billionai) } 79337f219c8SBruno Larsen (billionai) 79437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 795a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 79637f219c8SBruno Larsen (billionai) { 79737f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 79837f219c8SBruno Larsen (billionai) } 79937f219c8SBruno Larsen (billionai) 800a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 80137f219c8SBruno Larsen (billionai) { 80237f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 80337f219c8SBruno Larsen (billionai) } 80437f219c8SBruno Larsen (billionai) 805a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 80637f219c8SBruno Larsen (billionai) { 80737f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 80837f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 809d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81037f219c8SBruno Larsen (billionai) } 81137f219c8SBruno Larsen (billionai) #endif 81237f219c8SBruno Larsen (billionai) 81337f219c8SBruno Larsen (billionai) /* Unified bats */ 81437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 815a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 81637f219c8SBruno Larsen (billionai) { 81737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 81837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 81937f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 82037f219c8SBruno Larsen (billionai) } 82137f219c8SBruno Larsen (billionai) 822a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 82337f219c8SBruno Larsen (billionai) { 82437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 82537f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 82637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 82737f219c8SBruno Larsen (billionai) } 82837f219c8SBruno Larsen (billionai) 829a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 83037f219c8SBruno Larsen (billionai) { 83137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 83237f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 83337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 83437f219c8SBruno Larsen (billionai) } 83537f219c8SBruno Larsen (billionai) #endif 83637f219c8SBruno Larsen (billionai) 83737f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 83837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 839a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 84037f219c8SBruno Larsen (billionai) { 841f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84237f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84337f219c8SBruno Larsen (billionai) } 84437f219c8SBruno Larsen (billionai) 845a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84637f219c8SBruno Larsen (billionai) { 847f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84837f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 84937f219c8SBruno Larsen (billionai) } 85037f219c8SBruno Larsen (billionai) 851a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85237f219c8SBruno Larsen (billionai) { 853f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85537f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85637f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 857d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 85837f219c8SBruno Larsen (billionai) } 85937f219c8SBruno Larsen (billionai) 860a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86137f219c8SBruno Larsen (billionai) { 862f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86337f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86437f219c8SBruno Larsen (billionai) } 86537f219c8SBruno Larsen (billionai) 866a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 86737f219c8SBruno Larsen (billionai) { 868f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86937f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 87037f219c8SBruno Larsen (billionai) } 87137f219c8SBruno Larsen (billionai) 872a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 87337f219c8SBruno Larsen (billionai) { 874f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87537f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 87637f219c8SBruno Larsen (billionai) } 87737f219c8SBruno Larsen (billionai) #endif 87837f219c8SBruno Larsen (billionai) 87937f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 88037f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 88137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 882a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 88337f219c8SBruno Larsen (billionai) { 88437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 88537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 88637f219c8SBruno Larsen (billionai) } 88737f219c8SBruno Larsen (billionai) 888a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 88937f219c8SBruno Larsen (billionai) { 89037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 89137f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 89237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89337f219c8SBruno Larsen (billionai) } 89437f219c8SBruno Larsen (billionai) 895a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 89637f219c8SBruno Larsen (billionai) { 89737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 89837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 89937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90137f219c8SBruno Larsen (billionai) } 90237f219c8SBruno Larsen (billionai) #endif 90337f219c8SBruno Larsen (billionai) 90437f219c8SBruno Larsen (billionai) /* SPE specific registers */ 905a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 90637f219c8SBruno Larsen (billionai) { 90737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 90837f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 90937f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91137f219c8SBruno Larsen (billionai) } 91237f219c8SBruno Larsen (billionai) 913a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91437f219c8SBruno Larsen (billionai) { 91537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91637f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 91737f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91937f219c8SBruno Larsen (billionai) } 92037f219c8SBruno Larsen (billionai) 92137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92237f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 923a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92437f219c8SBruno Larsen (billionai) { 92537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 92737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 92837f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 92937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93137f219c8SBruno Larsen (billionai) } 93237f219c8SBruno Larsen (billionai) 933a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93437f219c8SBruno Larsen (billionai) { 93537f219c8SBruno Larsen (billionai) int sprn_offs; 93637f219c8SBruno Larsen (billionai) 93737f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 93837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 93937f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94037f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94137f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94237f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94337f219c8SBruno Larsen (billionai) } else { 94437f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 94537f219c8SBruno Larsen (billionai) sprn, sprn); 94637f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 94737f219c8SBruno Larsen (billionai) return; 94837f219c8SBruno Larsen (billionai) } 94937f219c8SBruno Larsen (billionai) 95037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 95637f219c8SBruno Larsen (billionai) } 95737f219c8SBruno Larsen (billionai) #endif 95837f219c8SBruno Larsen (billionai) 95937f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 96037f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 961a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96237f219c8SBruno Larsen (billionai) { 96337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) 96737f219c8SBruno Larsen (billionai) /* 96837f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 96937f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97037f219c8SBruno Larsen (billionai) */ 97137f219c8SBruno Larsen (billionai) 97237f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97337f219c8SBruno Larsen (billionai) if (ctx->pr) { 97437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97537f219c8SBruno Larsen (billionai) } else { 97637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97737f219c8SBruno Larsen (billionai) } 97837f219c8SBruno Larsen (billionai) 97937f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98137f219c8SBruno Larsen (billionai) 98237f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98337f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98437f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98537f219c8SBruno Larsen (billionai) 98637f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 98837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 98937f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 99037f219c8SBruno Larsen (billionai) 99137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 99237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 99337f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 99437f219c8SBruno Larsen (billionai) } 99537f219c8SBruno Larsen (billionai) 996a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 99737f219c8SBruno Larsen (billionai) { 99837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 99937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100137f219c8SBruno Larsen (billionai) 100237f219c8SBruno Larsen (billionai) /* 100337f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100437f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100537f219c8SBruno Larsen (billionai) */ 100637f219c8SBruno Larsen (billionai) 100737f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100837f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 100937f219c8SBruno Larsen (billionai) 101037f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101237f219c8SBruno Larsen (billionai) 101337f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101437f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101537f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101637f219c8SBruno Larsen (billionai) 101737f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 101937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 102037f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 102137f219c8SBruno Larsen (billionai) 102237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 102437f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 102537f219c8SBruno Larsen (billionai) } 102637f219c8SBruno Larsen (billionai) 1027a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 102837f219c8SBruno Larsen (billionai) { 102937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103237f219c8SBruno Larsen (billionai) 103337f219c8SBruno Larsen (billionai) /* 103437f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 103537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 103637f219c8SBruno Larsen (billionai) */ 103737f219c8SBruno Larsen (billionai) 103837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 103937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104037f219c8SBruno Larsen (billionai) 104137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 104337f219c8SBruno Larsen (billionai) 104437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 104537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 104637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 104737f219c8SBruno Larsen (billionai) 104837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 104937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 105137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 105237f219c8SBruno Larsen (billionai) 105337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 105537f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 105637f219c8SBruno Larsen (billionai) } 105737f219c8SBruno Larsen (billionai) #endif 105837f219c8SBruno Larsen (billionai) #endif 105937f219c8SBruno Larsen (billionai) 106037f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1061a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 106237f219c8SBruno Larsen (billionai) { 106337f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 106437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 106537f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 106637f219c8SBruno Larsen (billionai) } 106737f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 106837f219c8SBruno Larsen (billionai) 106937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1070a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 107137f219c8SBruno Larsen (billionai) { 107237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107337f219c8SBruno Larsen (billionai) 107437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 107537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107737f219c8SBruno Larsen (billionai) } 107837f219c8SBruno Larsen (billionai) 1079a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 108037f219c8SBruno Larsen (billionai) { 108137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108237f219c8SBruno Larsen (billionai) 108337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 108437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108637f219c8SBruno Larsen (billionai) } 108737f219c8SBruno Larsen (billionai) 1088a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 108937f219c8SBruno Larsen (billionai) { 109037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109137f219c8SBruno Larsen (billionai) 109237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 109337f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 109437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109637f219c8SBruno Larsen (billionai) } 109737f219c8SBruno Larsen (billionai) 1098a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 109937f219c8SBruno Larsen (billionai) { 110037f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 110137f219c8SBruno Larsen (billionai) } 110237f219c8SBruno Larsen (billionai) 1103a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 110437f219c8SBruno Larsen (billionai) { 110537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 110637f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 110737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 110837f219c8SBruno Larsen (billionai) } 1109a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 111037f219c8SBruno Larsen (billionai) { 111137f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 111237f219c8SBruno Larsen (billionai) } 1113a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 111437f219c8SBruno Larsen (billionai) { 111537f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 111637f219c8SBruno Larsen (billionai) } 111737f219c8SBruno Larsen (billionai) 111837f219c8SBruno Larsen (billionai) #endif 111937f219c8SBruno Larsen (billionai) 112037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1121a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 112237f219c8SBruno Larsen (billionai) { 112337f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 112437f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 112537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 112637f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 112737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 112837f219c8SBruno Larsen (billionai) tcg_temp_free(val); 112937f219c8SBruno Larsen (billionai) } 113037f219c8SBruno Larsen (billionai) 1131a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 113237f219c8SBruno Larsen (billionai) { 113337f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 113437f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 113537f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 113637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 113737f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 113837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 113937f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 114037f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 114137f219c8SBruno Larsen (billionai) } 114237f219c8SBruno Larsen (billionai) 114337f219c8SBruno Larsen (billionai) #endif 114437f219c8SBruno Larsen (billionai) 114537f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 114637f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 114737f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114837f219c8SBruno Larsen (billionai) { 114937f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 115037f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 115137f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 115237f219c8SBruno Larsen (billionai) 115337f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 115437f219c8SBruno Larsen (billionai) 115537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 115637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 115737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 115837f219c8SBruno Larsen (billionai) } 115937f219c8SBruno Larsen (billionai) 116037f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 116137f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116237f219c8SBruno Larsen (billionai) { 116337f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 116437f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 116537f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116637f219c8SBruno Larsen (billionai) 116737f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 116837f219c8SBruno Larsen (billionai) 116937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 117237f219c8SBruno Larsen (billionai) } 117337f219c8SBruno Larsen (billionai) 1174a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 117537f219c8SBruno Larsen (billionai) { 117637f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 117737f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 117837f219c8SBruno Larsen (billionai) 117937f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118037f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 118137f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 118237f219c8SBruno Larsen (billionai) 118337f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 118437f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 118537f219c8SBruno Larsen (billionai) } 118637f219c8SBruno Larsen (billionai) 1187a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 118837f219c8SBruno Larsen (billionai) { 118937f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119037f219c8SBruno Larsen (billionai) 119137f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119237f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 119337f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 119437f219c8SBruno Larsen (billionai) 119537f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 119637f219c8SBruno Larsen (billionai) } 119737f219c8SBruno Larsen (billionai) 119837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1199a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 120037f219c8SBruno Larsen (billionai) { 120137f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 120237f219c8SBruno Larsen (billionai) 120337f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 120437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 120537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 120637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 120737f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 120837f219c8SBruno Larsen (billionai) } 120937f219c8SBruno Larsen (billionai) 1210a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 121137f219c8SBruno Larsen (billionai) { 121237f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 121337f219c8SBruno Larsen (billionai) } 121437f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 121537f219c8SBruno Larsen (billionai) 1216a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 121737f219c8SBruno Larsen (billionai) { 121837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 121937f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122037f219c8SBruno Larsen (billionai) } 122137f219c8SBruno Larsen (billionai) 1222a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 122337f219c8SBruno Larsen (billionai) { 122437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 122637f219c8SBruno Larsen (billionai) } 122737f219c8SBruno Larsen (billionai) 1228a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 122937f219c8SBruno Larsen (billionai) { 123037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123137f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123237f219c8SBruno Larsen (billionai) } 123337f219c8SBruno Larsen (billionai) 1234a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 123537f219c8SBruno Larsen (billionai) { 123637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123837f219c8SBruno Larsen (billionai) } 123937f219c8SBruno Larsen (billionai) 1240a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 124137f219c8SBruno Larsen (billionai) { 124237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124337f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124437f219c8SBruno Larsen (billionai) } 124537f219c8SBruno Larsen (billionai) 1246a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 124737f219c8SBruno Larsen (billionai) { 124837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124937f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125037f219c8SBruno Larsen (billionai) } 125137f219c8SBruno Larsen (billionai) 1252a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 125337f219c8SBruno Larsen (billionai) { 125437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125537f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125637f219c8SBruno Larsen (billionai) } 125737f219c8SBruno Larsen (billionai) 1258a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 125937f219c8SBruno Larsen (billionai) { 126037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126137f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126237f219c8SBruno Larsen (billionai) } 126337f219c8SBruno Larsen (billionai) 1264a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 126537f219c8SBruno Larsen (billionai) { 126637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126737f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 126837f219c8SBruno Larsen (billionai) } 126937f219c8SBruno Larsen (billionai) 1270a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 127137f219c8SBruno Larsen (billionai) { 127237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127337f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 127437f219c8SBruno Larsen (billionai) } 127537f219c8SBruno Larsen (billionai) #endif 127637f219c8SBruno Larsen (billionai) 1277fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1278fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1279fcf5ef2aSThomas Huth 1280fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1281fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1282fcf5ef2aSThomas Huth 1283fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1284fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1285fcf5ef2aSThomas Huth 1286fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1287fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1288fcf5ef2aSThomas Huth 1289fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1290fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1291fcf5ef2aSThomas Huth 1292fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1293fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1294fcf5ef2aSThomas Huth 1295fcf5ef2aSThomas Huth typedef struct opcode_t { 1296fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1297fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1298fcf5ef2aSThomas Huth unsigned char pad[4]; 1299fcf5ef2aSThomas Huth #endif 1300fcf5ef2aSThomas Huth opc_handler_t handler; 1301fcf5ef2aSThomas Huth const char *oname; 1302fcf5ef2aSThomas Huth } opcode_t; 1303fcf5ef2aSThomas Huth 1304fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1305fcf5ef2aSThomas Huth #define GEN_PRIV \ 1306fcf5ef2aSThomas Huth do { \ 1307fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1308fcf5ef2aSThomas Huth } while (0) 1309fcf5ef2aSThomas Huth 1310fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1311fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1312fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1313fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1314fcf5ef2aSThomas Huth #else 1315fcf5ef2aSThomas Huth #define CHK_HV \ 1316fcf5ef2aSThomas Huth do { \ 1317fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1318fcf5ef2aSThomas Huth GEN_PRIV; \ 1319fcf5ef2aSThomas Huth } \ 1320fcf5ef2aSThomas Huth } while (0) 1321fcf5ef2aSThomas Huth #define CHK_SV \ 1322fcf5ef2aSThomas Huth do { \ 1323fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1324fcf5ef2aSThomas Huth GEN_PRIV; \ 1325fcf5ef2aSThomas Huth } \ 1326fcf5ef2aSThomas Huth } while (0) 1327fcf5ef2aSThomas Huth #define CHK_HVRM \ 1328fcf5ef2aSThomas Huth do { \ 1329fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1330fcf5ef2aSThomas Huth GEN_PRIV; \ 1331fcf5ef2aSThomas Huth } \ 1332fcf5ef2aSThomas Huth } while (0) 1333fcf5ef2aSThomas Huth #endif 1334fcf5ef2aSThomas Huth 1335fcf5ef2aSThomas Huth #define CHK_NONE 1336fcf5ef2aSThomas Huth 1337fcf5ef2aSThomas Huth /*****************************************************************************/ 1338fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1339fcf5ef2aSThomas Huth 1340fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1341fcf5ef2aSThomas Huth { \ 1342fcf5ef2aSThomas Huth .opc1 = op1, \ 1343fcf5ef2aSThomas Huth .opc2 = op2, \ 1344fcf5ef2aSThomas Huth .opc3 = op3, \ 1345fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1346fcf5ef2aSThomas Huth .handler = { \ 1347fcf5ef2aSThomas Huth .inval1 = invl, \ 1348fcf5ef2aSThomas Huth .type = _typ, \ 1349fcf5ef2aSThomas Huth .type2 = _typ2, \ 1350fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1351fcf5ef2aSThomas Huth }, \ 1352fcf5ef2aSThomas Huth .oname = stringify(name), \ 1353fcf5ef2aSThomas Huth } 1354fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1355fcf5ef2aSThomas Huth { \ 1356fcf5ef2aSThomas Huth .opc1 = op1, \ 1357fcf5ef2aSThomas Huth .opc2 = op2, \ 1358fcf5ef2aSThomas Huth .opc3 = op3, \ 1359fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1360fcf5ef2aSThomas Huth .handler = { \ 1361fcf5ef2aSThomas Huth .inval1 = invl1, \ 1362fcf5ef2aSThomas Huth .inval2 = invl2, \ 1363fcf5ef2aSThomas Huth .type = _typ, \ 1364fcf5ef2aSThomas Huth .type2 = _typ2, \ 1365fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1366fcf5ef2aSThomas Huth }, \ 1367fcf5ef2aSThomas Huth .oname = stringify(name), \ 1368fcf5ef2aSThomas Huth } 1369fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1370fcf5ef2aSThomas Huth { \ 1371fcf5ef2aSThomas Huth .opc1 = op1, \ 1372fcf5ef2aSThomas Huth .opc2 = op2, \ 1373fcf5ef2aSThomas Huth .opc3 = op3, \ 1374fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1375fcf5ef2aSThomas Huth .handler = { \ 1376fcf5ef2aSThomas Huth .inval1 = invl, \ 1377fcf5ef2aSThomas Huth .type = _typ, \ 1378fcf5ef2aSThomas Huth .type2 = _typ2, \ 1379fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1380fcf5ef2aSThomas Huth }, \ 1381fcf5ef2aSThomas Huth .oname = onam, \ 1382fcf5ef2aSThomas Huth } 1383fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1384fcf5ef2aSThomas Huth { \ 1385fcf5ef2aSThomas Huth .opc1 = op1, \ 1386fcf5ef2aSThomas Huth .opc2 = op2, \ 1387fcf5ef2aSThomas Huth .opc3 = op3, \ 1388fcf5ef2aSThomas Huth .opc4 = op4, \ 1389fcf5ef2aSThomas Huth .handler = { \ 1390fcf5ef2aSThomas Huth .inval1 = invl, \ 1391fcf5ef2aSThomas Huth .type = _typ, \ 1392fcf5ef2aSThomas Huth .type2 = _typ2, \ 1393fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1394fcf5ef2aSThomas Huth }, \ 1395fcf5ef2aSThomas Huth .oname = stringify(name), \ 1396fcf5ef2aSThomas Huth } 1397fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1398fcf5ef2aSThomas Huth { \ 1399fcf5ef2aSThomas Huth .opc1 = op1, \ 1400fcf5ef2aSThomas Huth .opc2 = op2, \ 1401fcf5ef2aSThomas Huth .opc3 = op3, \ 1402fcf5ef2aSThomas Huth .opc4 = op4, \ 1403fcf5ef2aSThomas Huth .handler = { \ 1404fcf5ef2aSThomas Huth .inval1 = invl, \ 1405fcf5ef2aSThomas Huth .type = _typ, \ 1406fcf5ef2aSThomas Huth .type2 = _typ2, \ 1407fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1408fcf5ef2aSThomas Huth }, \ 1409fcf5ef2aSThomas Huth .oname = onam, \ 1410fcf5ef2aSThomas Huth } 1411fcf5ef2aSThomas Huth 1412fcf5ef2aSThomas Huth /* Invalid instruction */ 1413fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1414fcf5ef2aSThomas Huth { 1415fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1416fcf5ef2aSThomas Huth } 1417fcf5ef2aSThomas Huth 1418fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1419fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1420fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1421fcf5ef2aSThomas Huth .type = PPC_NONE, 1422fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1423fcf5ef2aSThomas Huth .handler = gen_invalid, 1424fcf5ef2aSThomas Huth }; 1425fcf5ef2aSThomas Huth 1426fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1427fcf5ef2aSThomas Huth 1428fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1429fcf5ef2aSThomas Huth { 1430fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1431b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1432b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1433fcf5ef2aSThomas Huth 1434b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1435b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1436efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1437efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1438b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1439efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1440efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1441b62b3686Spbonzini@redhat.com 1442b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1443fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1444b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1445fcf5ef2aSThomas Huth 1446fcf5ef2aSThomas Huth tcg_temp_free(t0); 1447b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1448b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1449fcf5ef2aSThomas Huth } 1450fcf5ef2aSThomas Huth 1451fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1452fcf5ef2aSThomas Huth { 1453fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1454fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1455fcf5ef2aSThomas Huth tcg_temp_free(t0); 1456fcf5ef2aSThomas Huth } 1457fcf5ef2aSThomas Huth 1458fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1459fcf5ef2aSThomas Huth { 1460fcf5ef2aSThomas Huth TCGv t0, t1; 1461fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1462fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1463fcf5ef2aSThomas Huth if (s) { 1464fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1465fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1466fcf5ef2aSThomas Huth } else { 1467fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1468fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1469fcf5ef2aSThomas Huth } 1470fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1471fcf5ef2aSThomas Huth tcg_temp_free(t1); 1472fcf5ef2aSThomas Huth tcg_temp_free(t0); 1473fcf5ef2aSThomas Huth } 1474fcf5ef2aSThomas Huth 1475fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1476fcf5ef2aSThomas Huth { 1477fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1478fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1479fcf5ef2aSThomas Huth tcg_temp_free(t0); 1480fcf5ef2aSThomas Huth } 1481fcf5ef2aSThomas Huth 1482fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1483fcf5ef2aSThomas Huth { 1484fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1485fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1486fcf5ef2aSThomas Huth } else { 1487fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1488fcf5ef2aSThomas Huth } 1489fcf5ef2aSThomas Huth } 1490fcf5ef2aSThomas Huth 1491fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1492fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1493fcf5ef2aSThomas Huth { 1494fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1495fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1496fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1497fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1498fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1499fcf5ef2aSThomas Huth 1500fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1501fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1502fcf5ef2aSThomas Huth 1503fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1504fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1505fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1506fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1507fcf5ef2aSThomas Huth 1508fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1509fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1510fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1511fcf5ef2aSThomas Huth 1512fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1513fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1514fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1515fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1516fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1517fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1518fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1519fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1520fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1521fcf5ef2aSThomas Huth } 1522efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1523fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1524fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1525fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1526fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1527fcf5ef2aSThomas Huth } 1528fcf5ef2aSThomas Huth 1529fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1530fcf5ef2aSThomas Huth /* cmpeqb */ 1531fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1532fcf5ef2aSThomas Huth { 1533fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1534fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1535fcf5ef2aSThomas Huth } 1536fcf5ef2aSThomas Huth #endif 1537fcf5ef2aSThomas Huth 1538fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1539fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1540fcf5ef2aSThomas Huth { 1541fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1542fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1543fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1544fcf5ef2aSThomas Huth TCGv zr; 1545fcf5ef2aSThomas Huth 1546fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1547fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1548fcf5ef2aSThomas Huth 1549fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1550fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1551fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1552fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1553fcf5ef2aSThomas Huth tcg_temp_free(zr); 1554fcf5ef2aSThomas Huth tcg_temp_free(t0); 1555fcf5ef2aSThomas Huth } 1556fcf5ef2aSThomas Huth 1557fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1558fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1559fcf5ef2aSThomas Huth { 1560fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1561fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1562fcf5ef2aSThomas Huth } 1563fcf5ef2aSThomas Huth 1564fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1565fcf5ef2aSThomas Huth 1566fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1567fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1568fcf5ef2aSThomas Huth { 1569fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1570fcf5ef2aSThomas Huth 1571fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1572fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1573fcf5ef2aSThomas Huth if (sub) { 1574fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1575fcf5ef2aSThomas Huth } else { 1576fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1577fcf5ef2aSThomas Huth } 1578fcf5ef2aSThomas Huth tcg_temp_free(t0); 1579fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1580dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1581dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1582dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1583fcf5ef2aSThomas Huth } 1584dc0ad844SNikunj A Dadhania } else { 1585dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1586dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1587dc0ad844SNikunj A Dadhania } 158838a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1589dc0ad844SNikunj A Dadhania } 1590fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1591fcf5ef2aSThomas Huth } 1592fcf5ef2aSThomas Huth 15936b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15946b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15954c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15966b10d008SNikunj A Dadhania { 15976b10d008SNikunj A Dadhania TCGv t0; 15986b10d008SNikunj A Dadhania 15996b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16006b10d008SNikunj A Dadhania return; 16016b10d008SNikunj A Dadhania } 16026b10d008SNikunj A Dadhania 16036b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 160433903d0aSNikunj A Dadhania if (sub) { 160533903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 160633903d0aSNikunj A Dadhania } else { 16076b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 160833903d0aSNikunj A Dadhania } 16096b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16104c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16116b10d008SNikunj A Dadhania tcg_temp_free(t0); 16126b10d008SNikunj A Dadhania } 16136b10d008SNikunj A Dadhania 1614fcf5ef2aSThomas Huth /* Common add function */ 1615fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16164c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16174c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1618fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1619fcf5ef2aSThomas Huth { 1620fcf5ef2aSThomas Huth TCGv t0 = ret; 1621fcf5ef2aSThomas Huth 1622fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1623fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1624fcf5ef2aSThomas Huth } 1625fcf5ef2aSThomas Huth 1626fcf5ef2aSThomas Huth if (compute_ca) { 1627fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1628efe843d8SDavid Gibson /* 1629efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1630efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1631efe843d8SDavid Gibson * produce the carry into bit 32. 1632efe843d8SDavid Gibson */ 1633fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1634fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1635fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1636fcf5ef2aSThomas Huth if (add_ca) { 16374c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1638fcf5ef2aSThomas Huth } 16394c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1640fcf5ef2aSThomas Huth tcg_temp_free(t1); 16414c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16426b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16434c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16446b10d008SNikunj A Dadhania } 1645fcf5ef2aSThomas Huth } else { 1646fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1647fcf5ef2aSThomas Huth if (add_ca) { 16484c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16494c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1650fcf5ef2aSThomas Huth } else { 16514c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1652fcf5ef2aSThomas Huth } 16534c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1654fcf5ef2aSThomas Huth tcg_temp_free(zero); 1655fcf5ef2aSThomas Huth } 1656fcf5ef2aSThomas Huth } else { 1657fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1658fcf5ef2aSThomas Huth if (add_ca) { 16594c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1660fcf5ef2aSThomas Huth } 1661fcf5ef2aSThomas Huth } 1662fcf5ef2aSThomas Huth 1663fcf5ef2aSThomas Huth if (compute_ov) { 1664fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1665fcf5ef2aSThomas Huth } 1666fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1667fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1668fcf5ef2aSThomas Huth } 1669fcf5ef2aSThomas Huth 167011f4e8f8SRichard Henderson if (t0 != ret) { 1671fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1672fcf5ef2aSThomas Huth tcg_temp_free(t0); 1673fcf5ef2aSThomas Huth } 1674fcf5ef2aSThomas Huth } 1675fcf5ef2aSThomas Huth /* Add functions with two operands */ 16764c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1677fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1678fcf5ef2aSThomas Huth { \ 1679fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1680fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16814c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1682fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1683fcf5ef2aSThomas Huth } 1684fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16854c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1686fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1687fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1688fcf5ef2aSThomas Huth { \ 1689fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1690fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1691fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16924c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1693fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1694fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1695fcf5ef2aSThomas Huth } 1696fcf5ef2aSThomas Huth 1697fcf5ef2aSThomas Huth /* add add. addo addo. */ 16984c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16994c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1700fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17014c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17024c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1703fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17044c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17054c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1706fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17074c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17084c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17094c5920afSSuraj Jitindar Singh /* addex */ 17104c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1711fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17124c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17134c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1714fcf5ef2aSThomas Huth /* addic addic.*/ 1715fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1716fcf5ef2aSThomas Huth { 1717fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1718fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17194c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1720fcf5ef2aSThomas Huth tcg_temp_free(c); 1721fcf5ef2aSThomas Huth } 1722fcf5ef2aSThomas Huth 1723fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1724fcf5ef2aSThomas Huth { 1725fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1726fcf5ef2aSThomas Huth } 1727fcf5ef2aSThomas Huth 1728fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1729fcf5ef2aSThomas Huth { 1730fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1731fcf5ef2aSThomas Huth } 1732fcf5ef2aSThomas Huth 1733fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1734fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1735fcf5ef2aSThomas Huth { 1736fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1737fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1738fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1739fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1740fcf5ef2aSThomas Huth 1741fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1742fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1743fcf5ef2aSThomas Huth if (sign) { 1744fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1745fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1746fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1747fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1748fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1749fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1750fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1751fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1752fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1753fcf5ef2aSThomas Huth } else { 1754fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1755fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1756fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1757fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1758fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1759fcf5ef2aSThomas Huth } 1760fcf5ef2aSThomas Huth if (compute_ov) { 1761fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1762c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1763c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1764c44027ffSNikunj A Dadhania } 1765fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1766fcf5ef2aSThomas Huth } 1767fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1768fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1769fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1770fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1771fcf5ef2aSThomas Huth 1772efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1773fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1774fcf5ef2aSThomas Huth } 1775efe843d8SDavid Gibson } 1776fcf5ef2aSThomas Huth /* Div functions */ 1777fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1778fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1779fcf5ef2aSThomas Huth { \ 1780fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1781fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1782fcf5ef2aSThomas Huth sign, compute_ov); \ 1783fcf5ef2aSThomas Huth } 1784fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1785fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1786fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1787fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1788fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1789fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1790fcf5ef2aSThomas Huth 1791fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1792fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1793fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1794fcf5ef2aSThomas Huth { \ 1795fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1796fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1797fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1798fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1799fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1800fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1801fcf5ef2aSThomas Huth } \ 1802fcf5ef2aSThomas Huth } 1803fcf5ef2aSThomas Huth 1804fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1805fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1806fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1807fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1808fcf5ef2aSThomas Huth 1809fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1810fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1811fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1812fcf5ef2aSThomas Huth { 1813fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1814fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1815fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1816fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1817fcf5ef2aSThomas Huth 1818fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1819fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1820fcf5ef2aSThomas Huth if (sign) { 1821fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1822fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1823fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1824fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1825fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1826fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1827fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1828fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1829fcf5ef2aSThomas Huth } else { 1830fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1831fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1832fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1833fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1834fcf5ef2aSThomas Huth } 1835fcf5ef2aSThomas Huth if (compute_ov) { 1836fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1837c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1838c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1839c44027ffSNikunj A Dadhania } 1840fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1841fcf5ef2aSThomas Huth } 1842fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1843fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1844fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1845fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1846fcf5ef2aSThomas Huth 1847efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1848fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1849fcf5ef2aSThomas Huth } 1850efe843d8SDavid Gibson } 1851fcf5ef2aSThomas Huth 1852fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1853fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1854fcf5ef2aSThomas Huth { \ 1855fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1856fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1857fcf5ef2aSThomas Huth sign, compute_ov); \ 1858fcf5ef2aSThomas Huth } 1859c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1860fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1861fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1862c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1863fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1864fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1865fcf5ef2aSThomas Huth 1866fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1867fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1868fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1869fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1870fcf5ef2aSThomas Huth #endif 1871fcf5ef2aSThomas Huth 1872fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1873fcf5ef2aSThomas Huth TCGv arg2, int sign) 1874fcf5ef2aSThomas Huth { 1875fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1876fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1877fcf5ef2aSThomas Huth 1878fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1879fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1880fcf5ef2aSThomas Huth if (sign) { 1881fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1882fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1883fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1884fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1885fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1886fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1887fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1888fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1889fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1890fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1891fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1892fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1893fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1894fcf5ef2aSThomas Huth } else { 1895fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1896fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1897fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1898fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1899fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1900fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1901fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1902fcf5ef2aSThomas Huth } 1903fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1904fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1905fcf5ef2aSThomas Huth } 1906fcf5ef2aSThomas Huth 1907fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1908fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1909fcf5ef2aSThomas Huth { \ 1910fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1911fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1912fcf5ef2aSThomas Huth sign); \ 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth 1915fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1916fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1917fcf5ef2aSThomas Huth 1918fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1919fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1920fcf5ef2aSThomas Huth TCGv arg2, int sign) 1921fcf5ef2aSThomas Huth { 1922fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1923fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1924fcf5ef2aSThomas Huth 1925fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1926fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1927fcf5ef2aSThomas Huth if (sign) { 1928fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1929fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1930fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1931fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1932fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1933fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1934fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1935fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1936fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1937fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1938fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1939fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1940fcf5ef2aSThomas Huth } else { 1941fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1942fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1943fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1944fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1945fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1946fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1947fcf5ef2aSThomas Huth } 1948fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1949fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1950fcf5ef2aSThomas Huth } 1951fcf5ef2aSThomas Huth 1952fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1953fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1954fcf5ef2aSThomas Huth { \ 1955fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1956fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1957fcf5ef2aSThomas Huth sign); \ 1958fcf5ef2aSThomas Huth } 1959fcf5ef2aSThomas Huth 1960fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1961fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1962fcf5ef2aSThomas Huth #endif 1963fcf5ef2aSThomas Huth 1964fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1965fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1966fcf5ef2aSThomas Huth { 1967fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1968fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1969fcf5ef2aSThomas Huth 1970fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1971fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1972fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1973fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1974fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1975fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1976efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1977fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1978fcf5ef2aSThomas Huth } 1979efe843d8SDavid Gibson } 1980fcf5ef2aSThomas Huth 1981fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1982fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1983fcf5ef2aSThomas Huth { 1984fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1985fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1986fcf5ef2aSThomas Huth 1987fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1988fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1989fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1990fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1991fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1992fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1993efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1994fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1995fcf5ef2aSThomas Huth } 1996efe843d8SDavid Gibson } 1997fcf5ef2aSThomas Huth 1998fcf5ef2aSThomas Huth /* mullw mullw. */ 1999fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2000fcf5ef2aSThomas Huth { 2001fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2002fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2003fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2004fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2005fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2006fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2007fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2008fcf5ef2aSThomas Huth tcg_temp_free(t0); 2009fcf5ef2aSThomas Huth tcg_temp_free(t1); 2010fcf5ef2aSThomas Huth #else 2011fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2012fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2013fcf5ef2aSThomas Huth #endif 2014efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2015fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2016fcf5ef2aSThomas Huth } 2017efe843d8SDavid Gibson } 2018fcf5ef2aSThomas Huth 2019fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2020fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2021fcf5ef2aSThomas Huth { 2022fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2023fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2024fcf5ef2aSThomas Huth 2025fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2026fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2027fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2028fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2029fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2030fcf5ef2aSThomas Huth #else 2031fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2032fcf5ef2aSThomas Huth #endif 2033fcf5ef2aSThomas Huth 2034fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2035fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2036fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 203761aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 203861aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 203961aa9a69SNikunj A Dadhania } 2040fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2041fcf5ef2aSThomas Huth 2042fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2043fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2044efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2045fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2046fcf5ef2aSThomas Huth } 2047efe843d8SDavid Gibson } 2048fcf5ef2aSThomas Huth 2049fcf5ef2aSThomas Huth /* mulli */ 2050fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2051fcf5ef2aSThomas Huth { 2052fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2053fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2054fcf5ef2aSThomas Huth } 2055fcf5ef2aSThomas Huth 2056fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2057fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2058fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2059fcf5ef2aSThomas Huth { 2060fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2061fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2062fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2063fcf5ef2aSThomas Huth tcg_temp_free(lo); 2064fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2065fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2066fcf5ef2aSThomas Huth } 2067fcf5ef2aSThomas Huth } 2068fcf5ef2aSThomas Huth 2069fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2070fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2071fcf5ef2aSThomas Huth { 2072fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2073fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2074fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2075fcf5ef2aSThomas Huth tcg_temp_free(lo); 2076fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2077fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2078fcf5ef2aSThomas Huth } 2079fcf5ef2aSThomas Huth } 2080fcf5ef2aSThomas Huth 2081fcf5ef2aSThomas Huth /* mulld mulld. */ 2082fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2083fcf5ef2aSThomas Huth { 2084fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2085fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2086efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2087fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2088fcf5ef2aSThomas Huth } 2089efe843d8SDavid Gibson } 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2092fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2093fcf5ef2aSThomas Huth { 2094fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2095fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2096fcf5ef2aSThomas Huth 2097fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2098fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2099fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2100fcf5ef2aSThomas Huth 2101fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2102fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 210361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 210461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 210561aa9a69SNikunj A Dadhania } 2106fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2107fcf5ef2aSThomas Huth 2108fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2109fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2110fcf5ef2aSThomas Huth 2111fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2112fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2113fcf5ef2aSThomas Huth } 2114fcf5ef2aSThomas Huth } 2115fcf5ef2aSThomas Huth #endif 2116fcf5ef2aSThomas Huth 2117fcf5ef2aSThomas Huth /* Common subf function */ 2118fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2119fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2120fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2121fcf5ef2aSThomas Huth { 2122fcf5ef2aSThomas Huth TCGv t0 = ret; 2123fcf5ef2aSThomas Huth 2124fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2125fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2126fcf5ef2aSThomas Huth } 2127fcf5ef2aSThomas Huth 2128fcf5ef2aSThomas Huth if (compute_ca) { 2129fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2130fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2131efe843d8SDavid Gibson /* 2132efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2133efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2134efe843d8SDavid Gibson * produce the carry into bit 32. 2135efe843d8SDavid Gibson */ 2136fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2137fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2138fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2139fcf5ef2aSThomas Huth if (add_ca) { 2140fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2141fcf5ef2aSThomas Huth } else { 2142fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2143fcf5ef2aSThomas Huth } 2144fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2145fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2146fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2147fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2148fcf5ef2aSThomas Huth tcg_temp_free(t1); 2149e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 215033903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 215133903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 215233903d0aSNikunj A Dadhania } 2153fcf5ef2aSThomas Huth } else if (add_ca) { 2154fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2155fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2156fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2157fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2158fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21594c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2160fcf5ef2aSThomas Huth tcg_temp_free(zero); 2161fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2162fcf5ef2aSThomas Huth } else { 2163fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2164fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21654c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2166fcf5ef2aSThomas Huth } 2167fcf5ef2aSThomas Huth } else if (add_ca) { 2168efe843d8SDavid Gibson /* 2169efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2170efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2171efe843d8SDavid Gibson */ 2172fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2173fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2174fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2175fcf5ef2aSThomas Huth } else { 2176fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2177fcf5ef2aSThomas Huth } 2178fcf5ef2aSThomas Huth 2179fcf5ef2aSThomas Huth if (compute_ov) { 2180fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2181fcf5ef2aSThomas Huth } 2182fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2183fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2184fcf5ef2aSThomas Huth } 2185fcf5ef2aSThomas Huth 218611f4e8f8SRichard Henderson if (t0 != ret) { 2187fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2188fcf5ef2aSThomas Huth tcg_temp_free(t0); 2189fcf5ef2aSThomas Huth } 2190fcf5ef2aSThomas Huth } 2191fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2192fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2193fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2194fcf5ef2aSThomas Huth { \ 2195fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2196fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2197fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2198fcf5ef2aSThomas Huth } 2199fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2200fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2201fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2202fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2203fcf5ef2aSThomas Huth { \ 2204fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2205fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2206fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2207fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2208fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2209fcf5ef2aSThomas Huth } 2210fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2211fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2212fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2213fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2214fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2215fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2216fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2217fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2218fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2219fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2220fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2221fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2222fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2223fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2224fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2225fcf5ef2aSThomas Huth 2226fcf5ef2aSThomas Huth /* subfic */ 2227fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2228fcf5ef2aSThomas Huth { 2229fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2230fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2231fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2232fcf5ef2aSThomas Huth tcg_temp_free(c); 2233fcf5ef2aSThomas Huth } 2234fcf5ef2aSThomas Huth 2235fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2236fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2237fcf5ef2aSThomas Huth { 2238fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2239fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2240fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2241fcf5ef2aSThomas Huth tcg_temp_free(zero); 2242fcf5ef2aSThomas Huth } 2243fcf5ef2aSThomas Huth 2244fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2245fcf5ef2aSThomas Huth { 22461480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22471480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22481480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22491480d71cSNikunj A Dadhania } 2250fcf5ef2aSThomas Huth } 2251fcf5ef2aSThomas Huth 2252fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2253fcf5ef2aSThomas Huth { 2254fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2255fcf5ef2aSThomas Huth } 2256fcf5ef2aSThomas Huth 2257fcf5ef2aSThomas Huth /*** Integer logical ***/ 2258fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2259fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2260fcf5ef2aSThomas Huth { \ 2261fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2262fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2263fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2264fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2265fcf5ef2aSThomas Huth } 2266fcf5ef2aSThomas Huth 2267fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2268fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2269fcf5ef2aSThomas Huth { \ 2270fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2271fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2272fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2273fcf5ef2aSThomas Huth } 2274fcf5ef2aSThomas Huth 2275fcf5ef2aSThomas Huth /* and & and. */ 2276fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2277fcf5ef2aSThomas Huth /* andc & andc. */ 2278fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2279fcf5ef2aSThomas Huth 2280fcf5ef2aSThomas Huth /* andi. */ 2281fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2282fcf5ef2aSThomas Huth { 2283efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2284efe843d8SDavid Gibson UIMM(ctx->opcode)); 2285fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2286fcf5ef2aSThomas Huth } 2287fcf5ef2aSThomas Huth 2288fcf5ef2aSThomas Huth /* andis. */ 2289fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2290fcf5ef2aSThomas Huth { 2291efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2292efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2293fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2294fcf5ef2aSThomas Huth } 2295fcf5ef2aSThomas Huth 2296fcf5ef2aSThomas Huth /* cntlzw */ 2297fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2298fcf5ef2aSThomas Huth { 22999b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23009b8514e5SRichard Henderson 23019b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23029b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23039b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23049b8514e5SRichard Henderson tcg_temp_free_i32(t); 23059b8514e5SRichard Henderson 2306efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2307fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2308fcf5ef2aSThomas Huth } 2309efe843d8SDavid Gibson } 2310fcf5ef2aSThomas Huth 2311fcf5ef2aSThomas Huth /* cnttzw */ 2312fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2313fcf5ef2aSThomas Huth { 23149b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23159b8514e5SRichard Henderson 23169b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23179b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23189b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23199b8514e5SRichard Henderson tcg_temp_free_i32(t); 23209b8514e5SRichard Henderson 2321fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2322fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2323fcf5ef2aSThomas Huth } 2324fcf5ef2aSThomas Huth } 2325fcf5ef2aSThomas Huth 2326fcf5ef2aSThomas Huth /* eqv & eqv. */ 2327fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2328fcf5ef2aSThomas Huth /* extsb & extsb. */ 2329fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2330fcf5ef2aSThomas Huth /* extsh & extsh. */ 2331fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2332fcf5ef2aSThomas Huth /* nand & nand. */ 2333fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2334fcf5ef2aSThomas Huth /* nor & nor. */ 2335fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2336fcf5ef2aSThomas Huth 2337fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2338fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2339fcf5ef2aSThomas Huth { 2340fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2341fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2342fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2343fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2344fcf5ef2aSThomas Huth 2345fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2346b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2347fcf5ef2aSThomas Huth } 2348fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2349fcf5ef2aSThomas Huth 2350fcf5ef2aSThomas Huth /* or & or. */ 2351fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2352fcf5ef2aSThomas Huth { 2353fcf5ef2aSThomas Huth int rs, ra, rb; 2354fcf5ef2aSThomas Huth 2355fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2356fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2357fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2358fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2359fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2360efe843d8SDavid Gibson if (rs != rb) { 2361fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2362efe843d8SDavid Gibson } else { 2363fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2364efe843d8SDavid Gibson } 2365efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2366fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2367efe843d8SDavid Gibson } 2368fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2369fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2370fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2371fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2372fcf5ef2aSThomas Huth int prio = 0; 2373fcf5ef2aSThomas Huth 2374fcf5ef2aSThomas Huth switch (rs) { 2375fcf5ef2aSThomas Huth case 1: 2376fcf5ef2aSThomas Huth /* Set process priority to low */ 2377fcf5ef2aSThomas Huth prio = 2; 2378fcf5ef2aSThomas Huth break; 2379fcf5ef2aSThomas Huth case 6: 2380fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2381fcf5ef2aSThomas Huth prio = 3; 2382fcf5ef2aSThomas Huth break; 2383fcf5ef2aSThomas Huth case 2: 2384fcf5ef2aSThomas Huth /* Set process priority to normal */ 2385fcf5ef2aSThomas Huth prio = 4; 2386fcf5ef2aSThomas Huth break; 2387fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2388fcf5ef2aSThomas Huth case 31: 2389fcf5ef2aSThomas Huth if (!ctx->pr) { 2390fcf5ef2aSThomas Huth /* Set process priority to very low */ 2391fcf5ef2aSThomas Huth prio = 1; 2392fcf5ef2aSThomas Huth } 2393fcf5ef2aSThomas Huth break; 2394fcf5ef2aSThomas Huth case 5: 2395fcf5ef2aSThomas Huth if (!ctx->pr) { 2396fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2397fcf5ef2aSThomas Huth prio = 5; 2398fcf5ef2aSThomas Huth } 2399fcf5ef2aSThomas Huth break; 2400fcf5ef2aSThomas Huth case 3: 2401fcf5ef2aSThomas Huth if (!ctx->pr) { 2402fcf5ef2aSThomas Huth /* Set process priority to high */ 2403fcf5ef2aSThomas Huth prio = 6; 2404fcf5ef2aSThomas Huth } 2405fcf5ef2aSThomas Huth break; 2406fcf5ef2aSThomas Huth case 7: 2407fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2408fcf5ef2aSThomas Huth /* Set process priority to very high */ 2409fcf5ef2aSThomas Huth prio = 7; 2410fcf5ef2aSThomas Huth } 2411fcf5ef2aSThomas Huth break; 2412fcf5ef2aSThomas Huth #endif 2413fcf5ef2aSThomas Huth default: 2414fcf5ef2aSThomas Huth break; 2415fcf5ef2aSThomas Huth } 2416fcf5ef2aSThomas Huth if (prio) { 2417fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2418fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2419fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2420fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2421fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2422fcf5ef2aSThomas Huth tcg_temp_free(t0); 2423fcf5ef2aSThomas Huth } 2424fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2425efe843d8SDavid Gibson /* 2426efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2427efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2428efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2429efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2430fcf5ef2aSThomas Huth */ 2431fcf5ef2aSThomas Huth gen_pause(ctx); 2432fcf5ef2aSThomas Huth #endif 2433fcf5ef2aSThomas Huth #endif 2434fcf5ef2aSThomas Huth } 2435fcf5ef2aSThomas Huth } 2436fcf5ef2aSThomas Huth /* orc & orc. */ 2437fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2438fcf5ef2aSThomas Huth 2439fcf5ef2aSThomas Huth /* xor & xor. */ 2440fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2441fcf5ef2aSThomas Huth { 2442fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2443efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2444efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2445efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2446efe843d8SDavid Gibson } else { 2447fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2448efe843d8SDavid Gibson } 2449efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2450fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2451fcf5ef2aSThomas Huth } 2452efe843d8SDavid Gibson } 2453fcf5ef2aSThomas Huth 2454fcf5ef2aSThomas Huth /* ori */ 2455fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2456fcf5ef2aSThomas Huth { 2457fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2458fcf5ef2aSThomas Huth 2459fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2460fcf5ef2aSThomas Huth return; 2461fcf5ef2aSThomas Huth } 2462fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2463fcf5ef2aSThomas Huth } 2464fcf5ef2aSThomas Huth 2465fcf5ef2aSThomas Huth /* oris */ 2466fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2467fcf5ef2aSThomas Huth { 2468fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2469fcf5ef2aSThomas Huth 2470fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2471fcf5ef2aSThomas Huth /* NOP */ 2472fcf5ef2aSThomas Huth return; 2473fcf5ef2aSThomas Huth } 2474efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2475efe843d8SDavid Gibson uimm << 16); 2476fcf5ef2aSThomas Huth } 2477fcf5ef2aSThomas Huth 2478fcf5ef2aSThomas Huth /* xori */ 2479fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2480fcf5ef2aSThomas Huth { 2481fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2482fcf5ef2aSThomas Huth 2483fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2484fcf5ef2aSThomas Huth /* NOP */ 2485fcf5ef2aSThomas Huth return; 2486fcf5ef2aSThomas Huth } 2487fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2488fcf5ef2aSThomas Huth } 2489fcf5ef2aSThomas Huth 2490fcf5ef2aSThomas Huth /* xoris */ 2491fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2492fcf5ef2aSThomas Huth { 2493fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2494fcf5ef2aSThomas Huth 2495fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2496fcf5ef2aSThomas Huth /* NOP */ 2497fcf5ef2aSThomas Huth return; 2498fcf5ef2aSThomas Huth } 2499efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2500efe843d8SDavid Gibson uimm << 16); 2501fcf5ef2aSThomas Huth } 2502fcf5ef2aSThomas Huth 2503fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2504fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2505fcf5ef2aSThomas Huth { 2506fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2507fcf5ef2aSThomas Huth } 2508fcf5ef2aSThomas Huth 2509fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2510fcf5ef2aSThomas Huth { 251179770002SRichard Henderson #if defined(TARGET_PPC64) 2512fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251379770002SRichard Henderson #else 251479770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251579770002SRichard Henderson #endif 2516fcf5ef2aSThomas Huth } 2517fcf5ef2aSThomas Huth 2518fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2519fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2520fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2521fcf5ef2aSThomas Huth { 252279770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2523fcf5ef2aSThomas Huth } 2524fcf5ef2aSThomas Huth #endif 2525fcf5ef2aSThomas Huth 2526fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2527fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2528fcf5ef2aSThomas Huth { 2529fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2530fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2531fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2532fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2533fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2534fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2535fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2536fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2537fcf5ef2aSThomas Huth tcg_temp_free(t0); 2538fcf5ef2aSThomas Huth } 2539fcf5ef2aSThomas Huth 2540fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2541fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2542fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2543fcf5ef2aSThomas Huth { 2544fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2545fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2546fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2547fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2548fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2549fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2550fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2551fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2552fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2553fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2554fcf5ef2aSThomas Huth tcg_temp_free(t0); 2555fcf5ef2aSThomas Huth } 2556fcf5ef2aSThomas Huth #endif 2557fcf5ef2aSThomas Huth 2558fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2559fcf5ef2aSThomas Huth /* bpermd */ 2560fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2561fcf5ef2aSThomas Huth { 2562fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2563fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2564fcf5ef2aSThomas Huth } 2565fcf5ef2aSThomas Huth #endif 2566fcf5ef2aSThomas Huth 2567fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2568fcf5ef2aSThomas Huth /* extsw & extsw. */ 2569fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2570fcf5ef2aSThomas Huth 2571fcf5ef2aSThomas Huth /* cntlzd */ 2572fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2573fcf5ef2aSThomas Huth { 25749b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2575efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2576fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2577fcf5ef2aSThomas Huth } 2578efe843d8SDavid Gibson } 2579fcf5ef2aSThomas Huth 2580fcf5ef2aSThomas Huth /* cnttzd */ 2581fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2582fcf5ef2aSThomas Huth { 25839b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2584fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2585fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2586fcf5ef2aSThomas Huth } 2587fcf5ef2aSThomas Huth } 2588fcf5ef2aSThomas Huth 2589fcf5ef2aSThomas Huth /* darn */ 2590fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2591fcf5ef2aSThomas Huth { 2592fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2593fcf5ef2aSThomas Huth 25947e4357f6SRichard Henderson if (l > 2) { 25957e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25967e4357f6SRichard Henderson } else { 2597f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2598fcf5ef2aSThomas Huth if (l == 0) { 2599fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26007e4357f6SRichard Henderson } else { 2601fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2602fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26037e4357f6SRichard Henderson } 2604fcf5ef2aSThomas Huth } 2605fcf5ef2aSThomas Huth } 2606fcf5ef2aSThomas Huth #endif 2607fcf5ef2aSThomas Huth 2608fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2609fcf5ef2aSThomas Huth 2610fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2611fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2612fcf5ef2aSThomas Huth { 2613fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2614fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2615fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2616fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2617fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2618fcf5ef2aSThomas Huth 2619fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2620fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2621fcf5ef2aSThomas Huth } else { 2622fcf5ef2aSThomas Huth target_ulong mask; 2623c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2624fcf5ef2aSThomas Huth TCGv t1; 2625fcf5ef2aSThomas Huth 2626fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2627fcf5ef2aSThomas Huth mb += 32; 2628fcf5ef2aSThomas Huth me += 32; 2629fcf5ef2aSThomas Huth #endif 2630fcf5ef2aSThomas Huth mask = MASK(mb, me); 2631fcf5ef2aSThomas Huth 2632c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2633c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2634c4f6a4a3SDaniele Buono mask_in_32b = false; 2635c4f6a4a3SDaniele Buono } 2636c4f6a4a3SDaniele Buono #endif 2637fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2638c4f6a4a3SDaniele Buono if (mask_in_32b) { 2639fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2640fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2641fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2642fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2643fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2644fcf5ef2aSThomas Huth } else { 2645fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2646fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2647fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2648fcf5ef2aSThomas Huth #else 2649fcf5ef2aSThomas Huth g_assert_not_reached(); 2650fcf5ef2aSThomas Huth #endif 2651fcf5ef2aSThomas Huth } 2652fcf5ef2aSThomas Huth 2653fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2654fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2655fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2656fcf5ef2aSThomas Huth tcg_temp_free(t1); 2657fcf5ef2aSThomas Huth } 2658fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2659fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2660fcf5ef2aSThomas Huth } 2661fcf5ef2aSThomas Huth } 2662fcf5ef2aSThomas Huth 2663fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2664fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2665fcf5ef2aSThomas Huth { 2666fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2667fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26687b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26697b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26707b4d326fSRichard Henderson int me = ME(ctx->opcode); 26717b4d326fSRichard Henderson int len = me - mb + 1; 26727b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2673fcf5ef2aSThomas Huth 26747b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26757b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26767b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26777b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2678fcf5ef2aSThomas Huth } else { 2679fcf5ef2aSThomas Huth target_ulong mask; 2680c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2681fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2682fcf5ef2aSThomas Huth mb += 32; 2683fcf5ef2aSThomas Huth me += 32; 2684fcf5ef2aSThomas Huth #endif 2685fcf5ef2aSThomas Huth mask = MASK(mb, me); 2686c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2687c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2688c4f6a4a3SDaniele Buono mask_in_32b = false; 2689c4f6a4a3SDaniele Buono } 2690c4f6a4a3SDaniele Buono #endif 2691c4f6a4a3SDaniele Buono if (mask_in_32b) { 26927b4d326fSRichard Henderson if (sh == 0) { 26937b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 269494f040aaSVitaly Chikunov } else { 2695fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2696fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2697fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2698fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2699fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2700fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 270194f040aaSVitaly Chikunov } 2702fcf5ef2aSThomas Huth } else { 2703fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2704fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2705fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2706fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2707fcf5ef2aSThomas Huth #else 2708fcf5ef2aSThomas Huth g_assert_not_reached(); 2709fcf5ef2aSThomas Huth #endif 2710fcf5ef2aSThomas Huth } 2711fcf5ef2aSThomas Huth } 2712fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2713fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2714fcf5ef2aSThomas Huth } 2715fcf5ef2aSThomas Huth } 2716fcf5ef2aSThomas Huth 2717fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2718fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2719fcf5ef2aSThomas Huth { 2720fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2721fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2722fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2723fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2724fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2725fcf5ef2aSThomas Huth target_ulong mask; 2726c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2727fcf5ef2aSThomas Huth 2728fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2729fcf5ef2aSThomas Huth mb += 32; 2730fcf5ef2aSThomas Huth me += 32; 2731fcf5ef2aSThomas Huth #endif 2732fcf5ef2aSThomas Huth mask = MASK(mb, me); 2733fcf5ef2aSThomas Huth 2734c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2735c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2736c4f6a4a3SDaniele Buono mask_in_32b = false; 2737c4f6a4a3SDaniele Buono } 2738c4f6a4a3SDaniele Buono #endif 2739c4f6a4a3SDaniele Buono if (mask_in_32b) { 2740fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2741fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2742fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2743fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2744fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2745fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2746fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2747fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2748fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2749fcf5ef2aSThomas Huth } else { 2750fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2751fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2752fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2753fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2754fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2755fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2756fcf5ef2aSThomas Huth #else 2757fcf5ef2aSThomas Huth g_assert_not_reached(); 2758fcf5ef2aSThomas Huth #endif 2759fcf5ef2aSThomas Huth } 2760fcf5ef2aSThomas Huth 2761fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2762fcf5ef2aSThomas Huth 2763fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2764fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2765fcf5ef2aSThomas Huth } 2766fcf5ef2aSThomas Huth } 2767fcf5ef2aSThomas Huth 2768fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2769fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2770fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2771fcf5ef2aSThomas Huth { \ 2772fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2773fcf5ef2aSThomas Huth } \ 2774fcf5ef2aSThomas Huth \ 2775fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2776fcf5ef2aSThomas Huth { \ 2777fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2778fcf5ef2aSThomas Huth } 2779fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2780fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2781fcf5ef2aSThomas Huth { \ 2782fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2783fcf5ef2aSThomas Huth } \ 2784fcf5ef2aSThomas Huth \ 2785fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2786fcf5ef2aSThomas Huth { \ 2787fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2788fcf5ef2aSThomas Huth } \ 2789fcf5ef2aSThomas Huth \ 2790fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2791fcf5ef2aSThomas Huth { \ 2792fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2793fcf5ef2aSThomas Huth } \ 2794fcf5ef2aSThomas Huth \ 2795fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2796fcf5ef2aSThomas Huth { \ 2797fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2798fcf5ef2aSThomas Huth } 2799fcf5ef2aSThomas Huth 2800fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2801fcf5ef2aSThomas Huth { 2802fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2803fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28047b4d326fSRichard Henderson int len = me - mb + 1; 28057b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2806fcf5ef2aSThomas Huth 28077b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28087b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28097b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28107b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2811fcf5ef2aSThomas Huth } else { 2812fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2813fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2814fcf5ef2aSThomas Huth } 2815fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2816fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2817fcf5ef2aSThomas Huth } 2818fcf5ef2aSThomas Huth } 2819fcf5ef2aSThomas Huth 2820fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2821fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2822fcf5ef2aSThomas Huth { 2823fcf5ef2aSThomas Huth uint32_t sh, mb; 2824fcf5ef2aSThomas Huth 2825fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2826fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2827fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2828fcf5ef2aSThomas Huth } 2829fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2830fcf5ef2aSThomas Huth 2831fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2832fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2833fcf5ef2aSThomas Huth { 2834fcf5ef2aSThomas Huth uint32_t sh, me; 2835fcf5ef2aSThomas Huth 2836fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2837fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2838fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2839fcf5ef2aSThomas Huth } 2840fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2841fcf5ef2aSThomas Huth 2842fcf5ef2aSThomas Huth /* rldic - rldic. */ 2843fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2844fcf5ef2aSThomas Huth { 2845fcf5ef2aSThomas Huth uint32_t sh, mb; 2846fcf5ef2aSThomas Huth 2847fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2848fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2849fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2850fcf5ef2aSThomas Huth } 2851fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2852fcf5ef2aSThomas Huth 2853fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2854fcf5ef2aSThomas Huth { 2855fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2856fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2857fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2858fcf5ef2aSThomas Huth TCGv t0; 2859fcf5ef2aSThomas Huth 2860fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2861fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2862fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2863fcf5ef2aSThomas Huth tcg_temp_free(t0); 2864fcf5ef2aSThomas Huth 2865fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2866fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2867fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2868fcf5ef2aSThomas Huth } 2869fcf5ef2aSThomas Huth } 2870fcf5ef2aSThomas Huth 2871fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2872fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2873fcf5ef2aSThomas Huth { 2874fcf5ef2aSThomas Huth uint32_t mb; 2875fcf5ef2aSThomas Huth 2876fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2877fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2878fcf5ef2aSThomas Huth } 2879fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2880fcf5ef2aSThomas Huth 2881fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2882fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2883fcf5ef2aSThomas Huth { 2884fcf5ef2aSThomas Huth uint32_t me; 2885fcf5ef2aSThomas Huth 2886fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2887fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2888fcf5ef2aSThomas Huth } 2889fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2890fcf5ef2aSThomas Huth 2891fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2892fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2893fcf5ef2aSThomas Huth { 2894fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2895fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2896fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2897fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2898fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2899fcf5ef2aSThomas Huth 2900fcf5ef2aSThomas Huth if (mb <= me) { 2901fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2902fcf5ef2aSThomas Huth } else { 2903fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2904fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2905fcf5ef2aSThomas Huth 2906fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2907fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2908fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2909fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2910fcf5ef2aSThomas Huth tcg_temp_free(t1); 2911fcf5ef2aSThomas Huth } 2912fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2913fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2914fcf5ef2aSThomas Huth } 2915fcf5ef2aSThomas Huth } 2916fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2917fcf5ef2aSThomas Huth #endif 2918fcf5ef2aSThomas Huth 2919fcf5ef2aSThomas Huth /*** Integer shift ***/ 2920fcf5ef2aSThomas Huth 2921fcf5ef2aSThomas Huth /* slw & slw. */ 2922fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2923fcf5ef2aSThomas Huth { 2924fcf5ef2aSThomas Huth TCGv t0, t1; 2925fcf5ef2aSThomas Huth 2926fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2927fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2928fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2929fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2930fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2931fcf5ef2aSThomas Huth #else 2932fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2933fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2934fcf5ef2aSThomas Huth #endif 2935fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2936fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2937fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2938fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2939fcf5ef2aSThomas Huth tcg_temp_free(t1); 2940fcf5ef2aSThomas Huth tcg_temp_free(t0); 2941fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2942efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2943fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2944fcf5ef2aSThomas Huth } 2945efe843d8SDavid Gibson } 2946fcf5ef2aSThomas Huth 2947fcf5ef2aSThomas Huth /* sraw & sraw. */ 2948fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2949fcf5ef2aSThomas Huth { 2950fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2951fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2952efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2953fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2954fcf5ef2aSThomas Huth } 2955efe843d8SDavid Gibson } 2956fcf5ef2aSThomas Huth 2957fcf5ef2aSThomas Huth /* srawi & srawi. */ 2958fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2959fcf5ef2aSThomas Huth { 2960fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2961fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2962fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2963fcf5ef2aSThomas Huth if (sh == 0) { 2964fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2965fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2966af1c259fSSandipan Das if (is_isa300(ctx)) { 2967af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2968af1c259fSSandipan Das } 2969fcf5ef2aSThomas Huth } else { 2970fcf5ef2aSThomas Huth TCGv t0; 2971fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2972fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2973fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2974fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2975fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2976fcf5ef2aSThomas Huth tcg_temp_free(t0); 2977fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2978af1c259fSSandipan Das if (is_isa300(ctx)) { 2979af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2980af1c259fSSandipan Das } 2981fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2982fcf5ef2aSThomas Huth } 2983fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2984fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2985fcf5ef2aSThomas Huth } 2986fcf5ef2aSThomas Huth } 2987fcf5ef2aSThomas Huth 2988fcf5ef2aSThomas Huth /* srw & srw. */ 2989fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2990fcf5ef2aSThomas Huth { 2991fcf5ef2aSThomas Huth TCGv t0, t1; 2992fcf5ef2aSThomas Huth 2993fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2994fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2995fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2996fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2997fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2998fcf5ef2aSThomas Huth #else 2999fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3000fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3001fcf5ef2aSThomas Huth #endif 3002fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3003fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3004fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3005fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3006fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3007fcf5ef2aSThomas Huth tcg_temp_free(t1); 3008fcf5ef2aSThomas Huth tcg_temp_free(t0); 3009efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3010fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3011fcf5ef2aSThomas Huth } 3012efe843d8SDavid Gibson } 3013fcf5ef2aSThomas Huth 3014fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3015fcf5ef2aSThomas Huth /* sld & sld. */ 3016fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3017fcf5ef2aSThomas Huth { 3018fcf5ef2aSThomas Huth TCGv t0, t1; 3019fcf5ef2aSThomas Huth 3020fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3021fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3022fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3023fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3024fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3025fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3026fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3027fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3028fcf5ef2aSThomas Huth tcg_temp_free(t1); 3029fcf5ef2aSThomas Huth tcg_temp_free(t0); 3030efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3031fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3032fcf5ef2aSThomas Huth } 3033efe843d8SDavid Gibson } 3034fcf5ef2aSThomas Huth 3035fcf5ef2aSThomas Huth /* srad & srad. */ 3036fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3037fcf5ef2aSThomas Huth { 3038fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3039fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3040efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3041fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3042fcf5ef2aSThomas Huth } 3043efe843d8SDavid Gibson } 3044fcf5ef2aSThomas Huth /* sradi & sradi. */ 3045fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3046fcf5ef2aSThomas Huth { 3047fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3048fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3049fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3050fcf5ef2aSThomas Huth if (sh == 0) { 3051fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3052fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3053af1c259fSSandipan Das if (is_isa300(ctx)) { 3054af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3055af1c259fSSandipan Das } 3056fcf5ef2aSThomas Huth } else { 3057fcf5ef2aSThomas Huth TCGv t0; 3058fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3059fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3060fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3061fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3062fcf5ef2aSThomas Huth tcg_temp_free(t0); 3063fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3064af1c259fSSandipan Das if (is_isa300(ctx)) { 3065af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3066af1c259fSSandipan Das } 3067fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3068fcf5ef2aSThomas Huth } 3069fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3070fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3071fcf5ef2aSThomas Huth } 3072fcf5ef2aSThomas Huth } 3073fcf5ef2aSThomas Huth 3074fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3075fcf5ef2aSThomas Huth { 3076fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3077fcf5ef2aSThomas Huth } 3078fcf5ef2aSThomas Huth 3079fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3080fcf5ef2aSThomas Huth { 3081fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3082fcf5ef2aSThomas Huth } 3083fcf5ef2aSThomas Huth 3084fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3085fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3086fcf5ef2aSThomas Huth { 3087fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3088fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3089fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3090fcf5ef2aSThomas Huth 3091fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3092fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3093fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3094fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3095fcf5ef2aSThomas Huth } 3096fcf5ef2aSThomas Huth } 3097fcf5ef2aSThomas Huth 3098fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3099fcf5ef2aSThomas Huth { 3100fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3101fcf5ef2aSThomas Huth } 3102fcf5ef2aSThomas Huth 3103fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3104fcf5ef2aSThomas Huth { 3105fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3106fcf5ef2aSThomas Huth } 3107fcf5ef2aSThomas Huth 3108fcf5ef2aSThomas Huth /* srd & srd. */ 3109fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3110fcf5ef2aSThomas Huth { 3111fcf5ef2aSThomas Huth TCGv t0, t1; 3112fcf5ef2aSThomas Huth 3113fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3114fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3115fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3116fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3117fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3118fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3119fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3120fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3121fcf5ef2aSThomas Huth tcg_temp_free(t1); 3122fcf5ef2aSThomas Huth tcg_temp_free(t0); 3123efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3124fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3125fcf5ef2aSThomas Huth } 3126efe843d8SDavid Gibson } 3127fcf5ef2aSThomas Huth #endif 3128fcf5ef2aSThomas Huth 3129fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3130fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3131fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3132fcf5ef2aSThomas Huth target_long maskl) 3133fcf5ef2aSThomas Huth { 3134fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3135fcf5ef2aSThomas Huth 3136fcf5ef2aSThomas Huth simm &= ~maskl; 3137fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3138fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3139fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3140fcf5ef2aSThomas Huth } 3141fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3142fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3143fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3144fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3145fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3146fcf5ef2aSThomas Huth } 3147fcf5ef2aSThomas Huth } else { 3148fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3149fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3150fcf5ef2aSThomas Huth } else { 3151fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3152fcf5ef2aSThomas Huth } 3153fcf5ef2aSThomas Huth } 3154fcf5ef2aSThomas Huth } 3155fcf5ef2aSThomas Huth 3156fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3157fcf5ef2aSThomas Huth { 3158fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3159fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3160fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3161fcf5ef2aSThomas Huth } else { 3162fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3163fcf5ef2aSThomas Huth } 3164fcf5ef2aSThomas Huth } else { 3165fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3166fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3167fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3168fcf5ef2aSThomas Huth } 3169fcf5ef2aSThomas Huth } 3170fcf5ef2aSThomas Huth } 3171fcf5ef2aSThomas Huth 3172fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3173fcf5ef2aSThomas Huth { 3174fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3175fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3176fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3177fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3178fcf5ef2aSThomas Huth } else { 3179fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3180fcf5ef2aSThomas Huth } 3181fcf5ef2aSThomas Huth } 3182fcf5ef2aSThomas Huth 3183fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3184fcf5ef2aSThomas Huth target_long val) 3185fcf5ef2aSThomas Huth { 3186fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3187fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3188fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3189fcf5ef2aSThomas Huth } 3190fcf5ef2aSThomas Huth } 3191fcf5ef2aSThomas Huth 3192fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3193fcf5ef2aSThomas Huth { 3194fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3195fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3196fcf5ef2aSThomas Huth } 3197fcf5ef2aSThomas Huth 3198fcf5ef2aSThomas Huth /*** Integer load ***/ 3199fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3200fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3201fcf5ef2aSThomas Huth 3202fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3203fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3204fcf5ef2aSThomas Huth TCGv val, \ 3205fcf5ef2aSThomas Huth TCGv addr) \ 3206fcf5ef2aSThomas Huth { \ 3207fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3208fcf5ef2aSThomas Huth } 3209fcf5ef2aSThomas Huth 3210fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3211fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3212fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3213fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3214fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3215fcf5ef2aSThomas Huth 3216fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3217fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3218fcf5ef2aSThomas Huth 3219fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3220fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3221fcf5ef2aSThomas Huth TCGv_i64 val, \ 3222fcf5ef2aSThomas Huth TCGv addr) \ 3223fcf5ef2aSThomas Huth { \ 3224fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3225fcf5ef2aSThomas Huth } 3226fcf5ef2aSThomas Huth 3227fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3228fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3229fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3230fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3231fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3232fcf5ef2aSThomas Huth 3233fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3234fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3235fcf5ef2aSThomas Huth #endif 3236fcf5ef2aSThomas Huth 3237fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3238fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3239fcf5ef2aSThomas Huth TCGv val, \ 3240fcf5ef2aSThomas Huth TCGv addr) \ 3241fcf5ef2aSThomas Huth { \ 3242fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3243fcf5ef2aSThomas Huth } 3244fcf5ef2aSThomas Huth 3245e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3246fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3247e8f4c8d6SRichard Henderson #endif 3248fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3249fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3250fcf5ef2aSThomas Huth 3251fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3252fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3253fcf5ef2aSThomas Huth 3254fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3255fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3256fcf5ef2aSThomas Huth TCGv_i64 val, \ 3257fcf5ef2aSThomas Huth TCGv addr) \ 3258fcf5ef2aSThomas Huth { \ 3259fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3260fcf5ef2aSThomas Huth } 3261fcf5ef2aSThomas Huth 3262fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3263fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3264fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3265fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3266fcf5ef2aSThomas Huth 3267fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3268fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3269fcf5ef2aSThomas Huth #endif 3270fcf5ef2aSThomas Huth 3271fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3272fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3273fcf5ef2aSThomas Huth { \ 3274fcf5ef2aSThomas Huth TCGv EA; \ 3275fcf5ef2aSThomas Huth chk; \ 3276fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3277fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3278fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3279fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3280fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3281fcf5ef2aSThomas Huth } 3282fcf5ef2aSThomas Huth 3283fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3284fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3285fcf5ef2aSThomas Huth 3286fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3287fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3288fcf5ef2aSThomas Huth 328950728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 329050728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 329150728199SRoman Kapl { \ 329250728199SRoman Kapl TCGv EA; \ 329350728199SRoman Kapl CHK_SV; \ 329450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 329550728199SRoman Kapl EA = tcg_temp_new(); \ 329650728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 329750728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 329850728199SRoman Kapl tcg_temp_free(EA); \ 329950728199SRoman Kapl } 330050728199SRoman Kapl 330150728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 330250728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 330350728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 330450728199SRoman Kapl #if defined(TARGET_PPC64) 330550728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 330650728199SRoman Kapl #endif 330750728199SRoman Kapl 3308fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3309fcf5ef2aSThomas Huth /* CI load/store variants */ 3310fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3311fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3312fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3313fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3314fcf5ef2aSThomas Huth 3315fcf5ef2aSThomas Huth /* lq */ 3316fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3317fcf5ef2aSThomas Huth { 3318fcf5ef2aSThomas Huth int ra, rd; 331994bf2658SRichard Henderson TCGv EA, hi, lo; 3320fcf5ef2aSThomas Huth 3321fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3322fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3323fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3324fcf5ef2aSThomas Huth 3325fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3326fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3327fcf5ef2aSThomas Huth return; 3328fcf5ef2aSThomas Huth } 3329fcf5ef2aSThomas Huth 3330fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3331fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3332fcf5ef2aSThomas Huth return; 3333fcf5ef2aSThomas Huth } 3334fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3335fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3336fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3337fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3338fcf5ef2aSThomas Huth return; 3339fcf5ef2aSThomas Huth } 3340fcf5ef2aSThomas Huth 3341fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3342fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3343fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3344fcf5ef2aSThomas Huth 334594bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 334694bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 334794bf2658SRichard Henderson hi = cpu_gpr[rd]; 334894bf2658SRichard Henderson 334994bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3350f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 335194bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 335294bf2658SRichard Henderson if (ctx->le_mode) { 335394bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 335494bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3355fcf5ef2aSThomas Huth } else { 335694bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 335794bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 335894bf2658SRichard Henderson } 335994bf2658SRichard Henderson tcg_temp_free_i32(oi); 336094bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3361f34ec0f6SRichard Henderson } else { 336294bf2658SRichard Henderson /* Restart with exclusive lock. */ 336394bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 336494bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3365f34ec0f6SRichard Henderson } 336694bf2658SRichard Henderson } else if (ctx->le_mode) { 336794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3368fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 336994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 337094bf2658SRichard Henderson } else { 337194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 337294bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 337394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3374fcf5ef2aSThomas Huth } 3375fcf5ef2aSThomas Huth tcg_temp_free(EA); 3376fcf5ef2aSThomas Huth } 3377fcf5ef2aSThomas Huth #endif 3378fcf5ef2aSThomas Huth 3379fcf5ef2aSThomas Huth /*** Integer store ***/ 3380fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3381fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3382fcf5ef2aSThomas Huth { \ 3383fcf5ef2aSThomas Huth TCGv EA; \ 3384fcf5ef2aSThomas Huth chk; \ 3385fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3386fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3387fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3388fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3389fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3390fcf5ef2aSThomas Huth } 3391fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3392fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3393fcf5ef2aSThomas Huth 3394fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3395fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3396fcf5ef2aSThomas Huth 339750728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 339850728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 339950728199SRoman Kapl { \ 340050728199SRoman Kapl TCGv EA; \ 340150728199SRoman Kapl CHK_SV; \ 340250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 340350728199SRoman Kapl EA = tcg_temp_new(); \ 340450728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 340550728199SRoman Kapl tcg_gen_qemu_st_tl( \ 340650728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 340750728199SRoman Kapl tcg_temp_free(EA); \ 340850728199SRoman Kapl } 340950728199SRoman Kapl 341050728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 341150728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 341250728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 341350728199SRoman Kapl #if defined(TARGET_PPC64) 341450728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 341550728199SRoman Kapl #endif 341650728199SRoman Kapl 3417fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3418fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3419fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3420fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3421fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3422fcf5ef2aSThomas Huth 3423fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3424fcf5ef2aSThomas Huth { 3425fcf5ef2aSThomas Huth int rs; 3426fcf5ef2aSThomas Huth TCGv EA; 3427fcf5ef2aSThomas Huth 3428fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3429fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3430fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3431fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3432f89ced5fSRichard Henderson TCGv hi, lo; 3433fcf5ef2aSThomas Huth 3434fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3435fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3436fcf5ef2aSThomas Huth } 3437fcf5ef2aSThomas Huth 3438fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3439fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3440fcf5ef2aSThomas Huth return; 3441fcf5ef2aSThomas Huth } 3442fcf5ef2aSThomas Huth 3443fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3444fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3445fcf5ef2aSThomas Huth return; 3446fcf5ef2aSThomas Huth } 3447fcf5ef2aSThomas Huth 3448fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3449fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3450fcf5ef2aSThomas Huth return; 3451fcf5ef2aSThomas Huth } 3452fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3453fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3454fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3455fcf5ef2aSThomas Huth 3456f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3457f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3458f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3459f89ced5fSRichard Henderson 3460f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3461f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3462f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3463f89ced5fSRichard Henderson if (ctx->le_mode) { 346468e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128, 346568e33d86SRichard Henderson ctx->mem_idx)); 3466f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3467fcf5ef2aSThomas Huth } else { 346868e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128, 346968e33d86SRichard Henderson ctx->mem_idx)); 3470f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3471f89ced5fSRichard Henderson } 3472f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3473f34ec0f6SRichard Henderson } else { 3474f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3475f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3476f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3477f34ec0f6SRichard Henderson } 3478f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3479f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3480fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3481f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3482f89ced5fSRichard Henderson } else { 3483f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3484f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3485f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3486fcf5ef2aSThomas Huth } 3487fcf5ef2aSThomas Huth tcg_temp_free(EA); 3488fcf5ef2aSThomas Huth } else { 3489fcf5ef2aSThomas Huth /* std / stdu */ 3490fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3491fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3492fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3493fcf5ef2aSThomas Huth return; 3494fcf5ef2aSThomas Huth } 3495fcf5ef2aSThomas Huth } 3496fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3497fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3498fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3499fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3500efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3501fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3502efe843d8SDavid Gibson } 3503fcf5ef2aSThomas Huth tcg_temp_free(EA); 3504fcf5ef2aSThomas Huth } 3505fcf5ef2aSThomas Huth } 3506fcf5ef2aSThomas Huth #endif 3507fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3508fcf5ef2aSThomas Huth 3509fcf5ef2aSThomas Huth /* lhbrx */ 3510fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3511fcf5ef2aSThomas Huth 3512fcf5ef2aSThomas Huth /* lwbrx */ 3513fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3514fcf5ef2aSThomas Huth 3515fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3516fcf5ef2aSThomas Huth /* ldbrx */ 3517fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3518fcf5ef2aSThomas Huth /* stdbrx */ 3519fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3520fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3521fcf5ef2aSThomas Huth 3522fcf5ef2aSThomas Huth /* sthbrx */ 3523fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3524fcf5ef2aSThomas Huth /* stwbrx */ 3525fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3526fcf5ef2aSThomas Huth 3527fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3528fcf5ef2aSThomas Huth 3529fcf5ef2aSThomas Huth /* lmw */ 3530fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3531fcf5ef2aSThomas Huth { 3532fcf5ef2aSThomas Huth TCGv t0; 3533fcf5ef2aSThomas Huth TCGv_i32 t1; 3534fcf5ef2aSThomas Huth 3535fcf5ef2aSThomas Huth if (ctx->le_mode) { 3536fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3537fcf5ef2aSThomas Huth return; 3538fcf5ef2aSThomas Huth } 3539fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3540fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3541fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3542fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3543fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3544fcf5ef2aSThomas Huth tcg_temp_free(t0); 3545fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3546fcf5ef2aSThomas Huth } 3547fcf5ef2aSThomas Huth 3548fcf5ef2aSThomas Huth /* stmw */ 3549fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3550fcf5ef2aSThomas Huth { 3551fcf5ef2aSThomas Huth TCGv t0; 3552fcf5ef2aSThomas Huth TCGv_i32 t1; 3553fcf5ef2aSThomas Huth 3554fcf5ef2aSThomas Huth if (ctx->le_mode) { 3555fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3556fcf5ef2aSThomas Huth return; 3557fcf5ef2aSThomas Huth } 3558fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3559fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3560fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3561fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3562fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3563fcf5ef2aSThomas Huth tcg_temp_free(t0); 3564fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3565fcf5ef2aSThomas Huth } 3566fcf5ef2aSThomas Huth 3567fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3568fcf5ef2aSThomas Huth 3569fcf5ef2aSThomas Huth /* lswi */ 3570efe843d8SDavid Gibson /* 3571efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3572efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3573efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3574efe843d8SDavid Gibson * spec... 3575fcf5ef2aSThomas Huth */ 3576fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3577fcf5ef2aSThomas Huth { 3578fcf5ef2aSThomas Huth TCGv t0; 3579fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3580fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3581fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3582fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3583fcf5ef2aSThomas Huth int nr; 3584fcf5ef2aSThomas Huth 3585fcf5ef2aSThomas Huth if (ctx->le_mode) { 3586fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3587fcf5ef2aSThomas Huth return; 3588fcf5ef2aSThomas Huth } 3589efe843d8SDavid Gibson if (nb == 0) { 3590fcf5ef2aSThomas Huth nb = 32; 3591efe843d8SDavid Gibson } 3592f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3593fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3594fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3595fcf5ef2aSThomas Huth return; 3596fcf5ef2aSThomas Huth } 3597fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3598fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3599fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3600fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3601fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3602fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3603fcf5ef2aSThomas Huth tcg_temp_free(t0); 3604fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3605fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3606fcf5ef2aSThomas Huth } 3607fcf5ef2aSThomas Huth 3608fcf5ef2aSThomas Huth /* lswx */ 3609fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3610fcf5ef2aSThomas Huth { 3611fcf5ef2aSThomas Huth TCGv t0; 3612fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3613fcf5ef2aSThomas Huth 3614fcf5ef2aSThomas Huth if (ctx->le_mode) { 3615fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3616fcf5ef2aSThomas Huth return; 3617fcf5ef2aSThomas Huth } 3618fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3619fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3620fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3621fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3622fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3623fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3624fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3625fcf5ef2aSThomas Huth tcg_temp_free(t0); 3626fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3627fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3628fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3629fcf5ef2aSThomas Huth } 3630fcf5ef2aSThomas Huth 3631fcf5ef2aSThomas Huth /* stswi */ 3632fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3633fcf5ef2aSThomas Huth { 3634fcf5ef2aSThomas Huth TCGv t0; 3635fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3636fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3637fcf5ef2aSThomas Huth 3638fcf5ef2aSThomas Huth if (ctx->le_mode) { 3639fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3640fcf5ef2aSThomas Huth return; 3641fcf5ef2aSThomas Huth } 3642fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3643fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3644fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3645efe843d8SDavid Gibson if (nb == 0) { 3646fcf5ef2aSThomas Huth nb = 32; 3647efe843d8SDavid Gibson } 3648fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3649fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3650fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3651fcf5ef2aSThomas Huth tcg_temp_free(t0); 3652fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3653fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3654fcf5ef2aSThomas Huth } 3655fcf5ef2aSThomas Huth 3656fcf5ef2aSThomas Huth /* stswx */ 3657fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3658fcf5ef2aSThomas Huth { 3659fcf5ef2aSThomas Huth TCGv t0; 3660fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3661fcf5ef2aSThomas Huth 3662fcf5ef2aSThomas Huth if (ctx->le_mode) { 3663fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3664fcf5ef2aSThomas Huth return; 3665fcf5ef2aSThomas Huth } 3666fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3667fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3668fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3669fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3670fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3671fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3672fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3673fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3674fcf5ef2aSThomas Huth tcg_temp_free(t0); 3675fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3676fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3677fcf5ef2aSThomas Huth } 3678fcf5ef2aSThomas Huth 3679fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3680fcf5ef2aSThomas Huth /* eieio */ 3681fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3682fcf5ef2aSThomas Huth { 3683c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3684c8fd8373SCédric Le Goater 3685c8fd8373SCédric Le Goater /* 3686c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3687c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3688c8fd8373SCédric Le Goater */ 3689c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3690c8fd8373SCédric Le Goater /* 3691c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3692c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3693c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3694c8fd8373SCédric Le Goater * complain to the user. 3695c8fd8373SCédric Le Goater */ 3696c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3697c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 36982c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3699c8fd8373SCédric Le Goater } else { 3700c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3701c8fd8373SCédric Le Goater } 3702c8fd8373SCédric Le Goater } 3703c8fd8373SCédric Le Goater 3704c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3705fcf5ef2aSThomas Huth } 3706fcf5ef2aSThomas Huth 3707fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3708fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3709fcf5ef2aSThomas Huth { 3710fcf5ef2aSThomas Huth TCGv_i32 t; 3711fcf5ef2aSThomas Huth TCGLabel *l; 3712fcf5ef2aSThomas Huth 3713fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3714fcf5ef2aSThomas Huth return; 3715fcf5ef2aSThomas Huth } 3716fcf5ef2aSThomas Huth l = gen_new_label(); 3717fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3718fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3719fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3720fcf5ef2aSThomas Huth if (global) { 3721fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3722fcf5ef2aSThomas Huth } else { 3723fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3724fcf5ef2aSThomas Huth } 3725fcf5ef2aSThomas Huth gen_set_label(l); 3726fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3727fcf5ef2aSThomas Huth } 3728fcf5ef2aSThomas Huth #else 3729fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3730fcf5ef2aSThomas Huth #endif 3731fcf5ef2aSThomas Huth 3732fcf5ef2aSThomas Huth /* isync */ 3733fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3734fcf5ef2aSThomas Huth { 3735fcf5ef2aSThomas Huth /* 3736fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3737fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3738fcf5ef2aSThomas Huth */ 3739fcf5ef2aSThomas Huth if (!ctx->pr) { 3740fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3741fcf5ef2aSThomas Huth } 37424771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3743d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3744fcf5ef2aSThomas Huth } 3745fcf5ef2aSThomas Huth 3746fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3747fcf5ef2aSThomas Huth 374814776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 37492a4e6c1bSRichard Henderson { 37502a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 37512a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 37522a4e6c1bSRichard Henderson 37532a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 37542a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 37552a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 37562a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 37572a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 37582a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 37592a4e6c1bSRichard Henderson tcg_temp_free(t0); 37602a4e6c1bSRichard Henderson } 37612a4e6c1bSRichard Henderson 3762fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3763fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3764fcf5ef2aSThomas Huth { \ 37652a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3766fcf5ef2aSThomas Huth } 3767fcf5ef2aSThomas Huth 3768fcf5ef2aSThomas Huth /* lwarx */ 3769fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3770fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3771fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3772fcf5ef2aSThomas Huth 377314776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 377420923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 377520923c1dSRichard Henderson { 377620923c1dSRichard Henderson TCGv t = tcg_temp_new(); 377720923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 377820923c1dSRichard Henderson TCGv u = tcg_temp_new(); 377920923c1dSRichard Henderson 378020923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 378120923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 378220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 378320923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 378420923c1dSRichard Henderson 378520923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 378620923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 378720923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 378820923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 378920923c1dSRichard Henderson 379020923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 379120923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 379220923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 379320923c1dSRichard Henderson 379420923c1dSRichard Henderson tcg_temp_free(t); 379520923c1dSRichard Henderson tcg_temp_free(t2); 379620923c1dSRichard Henderson tcg_temp_free(u); 379720923c1dSRichard Henderson } 379820923c1dSRichard Henderson 379914776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 380020ba8504SRichard Henderson { 380120ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 380220ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 380320923c1dSRichard Henderson int rt = rD(ctx->opcode); 380420923c1dSRichard Henderson bool need_serial; 380520ba8504SRichard Henderson TCGv src, dst; 380620ba8504SRichard Henderson 380720ba8504SRichard Henderson gen_addr_register(ctx, EA); 380820923c1dSRichard Henderson dst = cpu_gpr[rt]; 380920923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 381020ba8504SRichard Henderson 381120923c1dSRichard Henderson need_serial = false; 381220ba8504SRichard Henderson memop |= MO_ALIGN; 381320ba8504SRichard Henderson switch (gpr_FC) { 381420ba8504SRichard Henderson case 0: /* Fetch and add */ 381520ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 381620ba8504SRichard Henderson break; 381720ba8504SRichard Henderson case 1: /* Fetch and xor */ 381820ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 381920ba8504SRichard Henderson break; 382020ba8504SRichard Henderson case 2: /* Fetch and or */ 382120ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 382220ba8504SRichard Henderson break; 382320ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 382420ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 382520ba8504SRichard Henderson break; 3826b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3827b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3828b8ce0f86SRichard Henderson break; 3829b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3830b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3831b8ce0f86SRichard Henderson break; 3832b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3833b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3834b8ce0f86SRichard Henderson break; 3835b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3836b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3837b8ce0f86SRichard Henderson break; 383820ba8504SRichard Henderson case 8: /* Swap */ 383920ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 384020ba8504SRichard Henderson break; 384120923c1dSRichard Henderson 384220923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 384320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 384420923c1dSRichard Henderson need_serial = true; 384520923c1dSRichard Henderson } else { 384620923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 384720923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 384820923c1dSRichard Henderson 384920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 385020923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 385120923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 385220923c1dSRichard Henderson } else { 385320923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 385420923c1dSRichard Henderson } 385520923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 385620923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 385720923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 385820923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 385920923c1dSRichard Henderson 386020923c1dSRichard Henderson tcg_temp_free(t0); 386120923c1dSRichard Henderson tcg_temp_free(t1); 386220923c1dSRichard Henderson } 386320ba8504SRichard Henderson break; 386420923c1dSRichard Henderson 386520923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 386620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 386720923c1dSRichard Henderson need_serial = true; 386820923c1dSRichard Henderson } else { 386920923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 387020923c1dSRichard Henderson } 387120923c1dSRichard Henderson break; 387220923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 387320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 387420923c1dSRichard Henderson need_serial = true; 387520923c1dSRichard Henderson } else { 387620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 387720923c1dSRichard Henderson } 387820923c1dSRichard Henderson break; 387920923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 388020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 388120923c1dSRichard Henderson need_serial = true; 388220923c1dSRichard Henderson } else { 388320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 388420923c1dSRichard Henderson } 388520923c1dSRichard Henderson break; 388620923c1dSRichard Henderson 388720ba8504SRichard Henderson default: 388820ba8504SRichard Henderson /* invoke data storage error handler */ 388920ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 389020ba8504SRichard Henderson } 389120ba8504SRichard Henderson tcg_temp_free(EA); 389220923c1dSRichard Henderson 389320923c1dSRichard Henderson if (need_serial) { 389420923c1dSRichard Henderson /* Restart with exclusive lock. */ 389520923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 389620923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 389720923c1dSRichard Henderson } 3898a68a6146SBalamuruhan S } 3899a68a6146SBalamuruhan S 390020ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 390120ba8504SRichard Henderson { 390220ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 390320ba8504SRichard Henderson } 390420ba8504SRichard Henderson 390520ba8504SRichard Henderson #ifdef TARGET_PPC64 390620ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 390720ba8504SRichard Henderson { 390820ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 390920ba8504SRichard Henderson } 3910a68a6146SBalamuruhan S #endif 3911a68a6146SBalamuruhan S 391214776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 39139deb041cSRichard Henderson { 39149deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 39159deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 39169deb041cSRichard Henderson TCGv src, discard; 39179deb041cSRichard Henderson 39189deb041cSRichard Henderson gen_addr_register(ctx, EA); 39199deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 39209deb041cSRichard Henderson discard = tcg_temp_new(); 39219deb041cSRichard Henderson 39229deb041cSRichard Henderson memop |= MO_ALIGN; 39239deb041cSRichard Henderson switch (gpr_FC) { 39249deb041cSRichard Henderson case 0: /* add and Store */ 39259deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39269deb041cSRichard Henderson break; 39279deb041cSRichard Henderson case 1: /* xor and Store */ 39289deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39299deb041cSRichard Henderson break; 39309deb041cSRichard Henderson case 2: /* Or and Store */ 39319deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39329deb041cSRichard Henderson break; 39339deb041cSRichard Henderson case 3: /* 'and' and Store */ 39349deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 39359deb041cSRichard Henderson break; 39369deb041cSRichard Henderson case 4: /* Store max unsigned */ 3937b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3938b8ce0f86SRichard Henderson break; 39399deb041cSRichard Henderson case 5: /* Store max signed */ 3940b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3941b8ce0f86SRichard Henderson break; 39429deb041cSRichard Henderson case 6: /* Store min unsigned */ 3943b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3944b8ce0f86SRichard Henderson break; 39459deb041cSRichard Henderson case 7: /* Store min signed */ 3946b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3947b8ce0f86SRichard Henderson break; 39489deb041cSRichard Henderson case 24: /* Store twin */ 39497fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 39507fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 39517fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 39527fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 39537fbc2b20SRichard Henderson } else { 39547fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 39557fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 39567fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 39577fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 39587fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 39597fbc2b20SRichard Henderson 39607fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 39617fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 39627fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 39637fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 39647fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 39657fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 39667fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 39677fbc2b20SRichard Henderson 39687fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 39697fbc2b20SRichard Henderson tcg_temp_free(s2); 39707fbc2b20SRichard Henderson tcg_temp_free(s); 39717fbc2b20SRichard Henderson tcg_temp_free(t2); 39727fbc2b20SRichard Henderson tcg_temp_free(t); 39737fbc2b20SRichard Henderson } 39749deb041cSRichard Henderson break; 39759deb041cSRichard Henderson default: 39769deb041cSRichard Henderson /* invoke data storage error handler */ 39779deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 39789deb041cSRichard Henderson } 39799deb041cSRichard Henderson tcg_temp_free(discard); 39809deb041cSRichard Henderson tcg_temp_free(EA); 3981a3401188SBalamuruhan S } 3982a3401188SBalamuruhan S 39839deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 39849deb041cSRichard Henderson { 39859deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 39869deb041cSRichard Henderson } 39879deb041cSRichard Henderson 39889deb041cSRichard Henderson #ifdef TARGET_PPC64 39899deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 39909deb041cSRichard Henderson { 39919deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 39929deb041cSRichard Henderson } 3993a3401188SBalamuruhan S #endif 3994a3401188SBalamuruhan S 399514776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3996fcf5ef2aSThomas Huth { 3997253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3998253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3999d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4000d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4001fcf5ef2aSThomas Huth 4002d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4003d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4004d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4005d8b86898SRichard Henderson tcg_temp_free(t0); 4006253ce7b2SNikunj A Dadhania 4007253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4008253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4009253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4010253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4011253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4012253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4013253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4014253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4015253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4016253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4017253ce7b2SNikunj A Dadhania 4018fcf5ef2aSThomas Huth gen_set_label(l1); 40194771df23SNikunj A Dadhania 4020efe843d8SDavid Gibson /* 4021efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4022efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4023efe843d8SDavid Gibson */ 40244771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4025253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4026253ce7b2SNikunj A Dadhania 4027253ce7b2SNikunj A Dadhania gen_set_label(l2); 4028fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4029fcf5ef2aSThomas Huth } 4030fcf5ef2aSThomas Huth 4031fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4032fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4033fcf5ef2aSThomas Huth { \ 4034d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4035fcf5ef2aSThomas Huth } 4036fcf5ef2aSThomas Huth 4037fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4038fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4039fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4040fcf5ef2aSThomas Huth 4041fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4042fcf5ef2aSThomas Huth /* ldarx */ 4043fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4044fcf5ef2aSThomas Huth /* stdcx. */ 4045fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4046fcf5ef2aSThomas Huth 4047fcf5ef2aSThomas Huth /* lqarx */ 4048fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4049fcf5ef2aSThomas Huth { 4050fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 405194bf2658SRichard Henderson TCGv EA, hi, lo; 4052fcf5ef2aSThomas Huth 4053fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4054fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4055fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4056fcf5ef2aSThomas Huth return; 4057fcf5ef2aSThomas Huth } 4058fcf5ef2aSThomas Huth 4059fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 406094bf2658SRichard Henderson EA = tcg_temp_new(); 4061fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 406294bf2658SRichard Henderson 406394bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 406494bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 406594bf2658SRichard Henderson hi = cpu_gpr[rd]; 406694bf2658SRichard Henderson 406794bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4068f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 406994bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 407094bf2658SRichard Henderson if (ctx->le_mode) { 407168e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 407294bf2658SRichard Henderson ctx->mem_idx)); 407394bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4074fcf5ef2aSThomas Huth } else { 407568e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 407694bf2658SRichard Henderson ctx->mem_idx)); 407794bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4078fcf5ef2aSThomas Huth } 407994bf2658SRichard Henderson tcg_temp_free_i32(oi); 408094bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4081f34ec0f6SRichard Henderson } else { 408294bf2658SRichard Henderson /* Restart with exclusive lock. */ 408394bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 408494bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 408594bf2658SRichard Henderson tcg_temp_free(EA); 408694bf2658SRichard Henderson return; 4087f34ec0f6SRichard Henderson } 408894bf2658SRichard Henderson } else if (ctx->le_mode) { 408994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4090fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4091fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 409294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 409394bf2658SRichard Henderson } else { 409494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 409594bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 409694bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 409794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 409894bf2658SRichard Henderson } 4099fcf5ef2aSThomas Huth tcg_temp_free(EA); 410094bf2658SRichard Henderson 410194bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 410294bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4103fcf5ef2aSThomas Huth } 4104fcf5ef2aSThomas Huth 4105fcf5ef2aSThomas Huth /* stqcx. */ 4106fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4107fcf5ef2aSThomas Huth { 41084a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 41094a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4110fcf5ef2aSThomas Huth 41114a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4112fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4113fcf5ef2aSThomas Huth return; 4114fcf5ef2aSThomas Huth } 41154a9b3c5dSRichard Henderson 4116fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 41174a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4118fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4119fcf5ef2aSThomas Huth 41204a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 41214a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 41224a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4123fcf5ef2aSThomas Huth 41244a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4125f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 412668e33d86SRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 41274a9b3c5dSRichard Henderson if (ctx->le_mode) { 4128f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4129f34ec0f6SRichard Henderson EA, lo, hi, oi); 4130fcf5ef2aSThomas Huth } else { 4131f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4132f34ec0f6SRichard Henderson EA, lo, hi, oi); 4133fcf5ef2aSThomas Huth } 4134f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4135f34ec0f6SRichard Henderson } else { 41364a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 41374a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 41384a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4139f34ec0f6SRichard Henderson } 4140fcf5ef2aSThomas Huth tcg_temp_free(EA); 41414a9b3c5dSRichard Henderson } else { 41424a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 41434a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 41444a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 41454a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4146fcf5ef2aSThomas Huth 41474a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 41484a9b3c5dSRichard Henderson tcg_temp_free(EA); 41494a9b3c5dSRichard Henderson 41504a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 41514a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 41524a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 41534a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 41544a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 41554a9b3c5dSRichard Henderson 41564a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 41574a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 41584a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 41594a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 41604a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 41614a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 41624a9b3c5dSRichard Henderson 41634a9b3c5dSRichard Henderson /* Success */ 41644a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 41654a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 41664a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 41674a9b3c5dSRichard Henderson 41684a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 41694a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 41704a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 41714a9b3c5dSRichard Henderson 41724a9b3c5dSRichard Henderson gen_set_label(lab_fail); 41734a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 41744a9b3c5dSRichard Henderson 41754a9b3c5dSRichard Henderson gen_set_label(lab_over); 41764a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 41774a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 41784a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 41794a9b3c5dSRichard Henderson } 41804a9b3c5dSRichard Henderson } 4181fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4182fcf5ef2aSThomas Huth 4183fcf5ef2aSThomas Huth /* sync */ 4184fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4185fcf5ef2aSThomas Huth { 4186fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4187fcf5ef2aSThomas Huth 4188fcf5ef2aSThomas Huth /* 4189fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4190fcf5ef2aSThomas Huth * 4191fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4192fcf5ef2aSThomas Huth * 4193fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4194fcf5ef2aSThomas Huth * check MSR_PR as well. 4195fcf5ef2aSThomas Huth */ 4196fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4197fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4198fcf5ef2aSThomas Huth } 41994771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4200fcf5ef2aSThomas Huth } 4201fcf5ef2aSThomas Huth 4202fcf5ef2aSThomas Huth /* wait */ 4203fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4204fcf5ef2aSThomas Huth { 4205fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4206fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4207fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4208fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4209fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4210b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4211fcf5ef2aSThomas Huth } 4212fcf5ef2aSThomas Huth 4213fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4214fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4215fcf5ef2aSThomas Huth { 4216fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4217fcf5ef2aSThomas Huth GEN_PRIV; 4218fcf5ef2aSThomas Huth #else 4219fcf5ef2aSThomas Huth TCGv_i32 t; 4220fcf5ef2aSThomas Huth 4221fcf5ef2aSThomas Huth CHK_HV; 4222fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4223fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4224fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4225154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4226154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4227fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4228fcf5ef2aSThomas Huth } 4229fcf5ef2aSThomas Huth 4230fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4231fcf5ef2aSThomas Huth { 4232fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4233fcf5ef2aSThomas Huth GEN_PRIV; 4234fcf5ef2aSThomas Huth #else 4235fcf5ef2aSThomas Huth TCGv_i32 t; 4236fcf5ef2aSThomas Huth 4237fcf5ef2aSThomas Huth CHK_HV; 4238fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4239fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4240fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4241154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4242154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4243fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4244fcf5ef2aSThomas Huth } 4245fcf5ef2aSThomas Huth 4246cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4247cdee0e72SNikunj A Dadhania { 424821c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 424921c0d66aSBenjamin Herrenschmidt GEN_PRIV; 425021c0d66aSBenjamin Herrenschmidt #else 425121c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 425221c0d66aSBenjamin Herrenschmidt 425321c0d66aSBenjamin Herrenschmidt CHK_HV; 425421c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 425521c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 425621c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 425721c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 425821c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 425921c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4260cdee0e72SNikunj A Dadhania } 4261cdee0e72SNikunj A Dadhania 4262fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4263fcf5ef2aSThomas Huth { 4264fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4265fcf5ef2aSThomas Huth GEN_PRIV; 4266fcf5ef2aSThomas Huth #else 4267fcf5ef2aSThomas Huth TCGv_i32 t; 4268fcf5ef2aSThomas Huth 4269fcf5ef2aSThomas Huth CHK_HV; 4270fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4271fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4272fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4273154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4274154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4275fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4276fcf5ef2aSThomas Huth } 4277fcf5ef2aSThomas Huth 4278fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4279fcf5ef2aSThomas Huth { 4280fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4281fcf5ef2aSThomas Huth GEN_PRIV; 4282fcf5ef2aSThomas Huth #else 4283fcf5ef2aSThomas Huth TCGv_i32 t; 4284fcf5ef2aSThomas Huth 4285fcf5ef2aSThomas Huth CHK_HV; 4286fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4287fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4288fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4289154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4290154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4291fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4292fcf5ef2aSThomas Huth } 4293fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4294fcf5ef2aSThomas Huth 4295fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4296fcf5ef2aSThomas Huth { 4297fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4298efe843d8SDavid Gibson if (ctx->has_cfar) { 4299fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4300efe843d8SDavid Gibson } 4301fcf5ef2aSThomas Huth #endif 4302fcf5ef2aSThomas Huth } 4303fcf5ef2aSThomas Huth 4304fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4305fcf5ef2aSThomas Huth { 43066e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4307fcf5ef2aSThomas Huth } 4308fcf5ef2aSThomas Huth 43090e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 43100e3bf489SRoman Kapl { 43119498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 43120e3bf489SRoman Kapl gen_debug_exception(ctx); 43130e3bf489SRoman Kapl } else { 43140e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 43150e3bf489SRoman Kapl } 43160e3bf489SRoman Kapl } 43170e3bf489SRoman Kapl 4318fcf5ef2aSThomas Huth /*** Branch ***/ 4319c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4320fcf5ef2aSThomas Huth { 4321fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4322fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4323fcf5ef2aSThomas Huth } 4324fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4325fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4326fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 432707ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4328fcf5ef2aSThomas Huth } else { 4329fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 43300e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4331fcf5ef2aSThomas Huth } 4332fcf5ef2aSThomas Huth } 4333fcf5ef2aSThomas Huth 4334fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4335fcf5ef2aSThomas Huth { 4336fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4337fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4338fcf5ef2aSThomas Huth } 4339fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4340fcf5ef2aSThomas Huth } 4341fcf5ef2aSThomas Huth 4342fcf5ef2aSThomas Huth /* b ba bl bla */ 4343fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4344fcf5ef2aSThomas Huth { 4345fcf5ef2aSThomas Huth target_ulong li, target; 4346fcf5ef2aSThomas Huth 4347fcf5ef2aSThomas Huth /* sign extend LI */ 4348fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4349fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4350fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43512c2bcb1bSRichard Henderson target = ctx->cia + li; 4352fcf5ef2aSThomas Huth } else { 4353fcf5ef2aSThomas Huth target = li; 4354fcf5ef2aSThomas Huth } 4355fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4356b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4357fcf5ef2aSThomas Huth } 43582c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4359fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 43606086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4361fcf5ef2aSThomas Huth } 4362fcf5ef2aSThomas Huth 4363fcf5ef2aSThomas Huth #define BCOND_IM 0 4364fcf5ef2aSThomas Huth #define BCOND_LR 1 4365fcf5ef2aSThomas Huth #define BCOND_CTR 2 4366fcf5ef2aSThomas Huth #define BCOND_TAR 3 4367fcf5ef2aSThomas Huth 4368c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4369fcf5ef2aSThomas Huth { 4370fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4371fcf5ef2aSThomas Huth TCGLabel *l1; 4372fcf5ef2aSThomas Huth TCGv target; 43730e3bf489SRoman Kapl 4374fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4375fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4376efe843d8SDavid Gibson if (type == BCOND_CTR) { 4377fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4378efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4379fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4380efe843d8SDavid Gibson } else { 4381fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4382efe843d8SDavid Gibson } 4383fcf5ef2aSThomas Huth } else { 4384f764718dSRichard Henderson target = NULL; 4385fcf5ef2aSThomas Huth } 4386efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4387b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4388efe843d8SDavid Gibson } 4389fcf5ef2aSThomas Huth l1 = gen_new_label(); 4390fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4391fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4392fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4393fa200c95SGreg Kurz 4394fa200c95SGreg Kurz if (type == BCOND_CTR) { 4395fa200c95SGreg Kurz /* 4396fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4397fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4398fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 439915d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 440015d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 440115d68c5eSGreg Kurz * it basically useless and thus never used in real code. 440215d68c5eSGreg Kurz * 440315d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 440415d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 440515d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 440615d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 440715d68c5eSGreg Kurz * doing anything else harmful. 4408fa200c95SGreg Kurz */ 4409d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4410fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 44119acc95cdSGreg Kurz tcg_temp_free(temp); 44129acc95cdSGreg Kurz tcg_temp_free(target); 4413fcf5ef2aSThomas Huth return; 4414fcf5ef2aSThomas Huth } 4415fa200c95SGreg Kurz 4416fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4417fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4418fa200c95SGreg Kurz } else { 4419fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4420fa200c95SGreg Kurz } 4421fa200c95SGreg Kurz if (bo & 0x2) { 4422fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4423fa200c95SGreg Kurz } else { 4424fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4425fa200c95SGreg Kurz } 4426fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4427fa200c95SGreg Kurz } else { 4428fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4429fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4430fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4431fcf5ef2aSThomas Huth } else { 4432fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4433fcf5ef2aSThomas Huth } 4434fcf5ef2aSThomas Huth if (bo & 0x2) { 4435fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4436fcf5ef2aSThomas Huth } else { 4437fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4438fcf5ef2aSThomas Huth } 4439fa200c95SGreg Kurz } 4440fcf5ef2aSThomas Huth tcg_temp_free(temp); 4441fcf5ef2aSThomas Huth } 4442fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4443fcf5ef2aSThomas Huth /* Test CR */ 4444fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4445fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4446fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4447fcf5ef2aSThomas Huth 4448fcf5ef2aSThomas Huth if (bo & 0x8) { 4449fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4450fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4451fcf5ef2aSThomas Huth } else { 4452fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4453fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4454fcf5ef2aSThomas Huth } 4455fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4456fcf5ef2aSThomas Huth } 44572c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4458fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4459fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4460fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 44612c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4462fcf5ef2aSThomas Huth } else { 4463fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4464fcf5ef2aSThomas Huth } 4465fcf5ef2aSThomas Huth } else { 4466fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4467fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4468fcf5ef2aSThomas Huth } else { 4469fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4470fcf5ef2aSThomas Huth } 44710e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4472c4a2e3a9SRichard Henderson tcg_temp_free(target); 4473c4a2e3a9SRichard Henderson } 4474fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 44750e3bf489SRoman Kapl /* fallthrough case */ 4476fcf5ef2aSThomas Huth gen_set_label(l1); 4477b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4478fcf5ef2aSThomas Huth } 44796086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4480fcf5ef2aSThomas Huth } 4481fcf5ef2aSThomas Huth 4482fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4483fcf5ef2aSThomas Huth { 4484fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4485fcf5ef2aSThomas Huth } 4486fcf5ef2aSThomas Huth 4487fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4488fcf5ef2aSThomas Huth { 4489fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4490fcf5ef2aSThomas Huth } 4491fcf5ef2aSThomas Huth 4492fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4493fcf5ef2aSThomas Huth { 4494fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4495fcf5ef2aSThomas Huth } 4496fcf5ef2aSThomas Huth 4497fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4498fcf5ef2aSThomas Huth { 4499fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4500fcf5ef2aSThomas Huth } 4501fcf5ef2aSThomas Huth 4502fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4503fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4504fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4505fcf5ef2aSThomas Huth { \ 4506fcf5ef2aSThomas Huth uint8_t bitmask; \ 4507fcf5ef2aSThomas Huth int sh; \ 4508fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4509fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4510fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4511fcf5ef2aSThomas Huth if (sh > 0) \ 4512fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4513fcf5ef2aSThomas Huth else if (sh < 0) \ 4514fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4515fcf5ef2aSThomas Huth else \ 4516fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4517fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4518fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4519fcf5ef2aSThomas Huth if (sh > 0) \ 4520fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4521fcf5ef2aSThomas Huth else if (sh < 0) \ 4522fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4523fcf5ef2aSThomas Huth else \ 4524fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4525fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4526fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4527fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4528fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4529fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4530fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4531fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4532fcf5ef2aSThomas Huth } 4533fcf5ef2aSThomas Huth 4534fcf5ef2aSThomas Huth /* crand */ 4535fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4536fcf5ef2aSThomas Huth /* crandc */ 4537fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4538fcf5ef2aSThomas Huth /* creqv */ 4539fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4540fcf5ef2aSThomas Huth /* crnand */ 4541fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4542fcf5ef2aSThomas Huth /* crnor */ 4543fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4544fcf5ef2aSThomas Huth /* cror */ 4545fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4546fcf5ef2aSThomas Huth /* crorc */ 4547fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4548fcf5ef2aSThomas Huth /* crxor */ 4549fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4550fcf5ef2aSThomas Huth 4551fcf5ef2aSThomas Huth /* mcrf */ 4552fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4553fcf5ef2aSThomas Huth { 4554fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4555fcf5ef2aSThomas Huth } 4556fcf5ef2aSThomas Huth 4557fcf5ef2aSThomas Huth /*** System linkage ***/ 4558fcf5ef2aSThomas Huth 4559fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4560fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4561fcf5ef2aSThomas Huth { 4562fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4563fcf5ef2aSThomas Huth GEN_PRIV; 4564fcf5ef2aSThomas Huth #else 4565efe843d8SDavid Gibson /* 4566efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4567fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4568fcf5ef2aSThomas Huth */ 4569d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4570fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4571fcf5ef2aSThomas Huth return; 4572fcf5ef2aSThomas Huth } 4573fcf5ef2aSThomas Huth /* Restore CPU state */ 4574fcf5ef2aSThomas Huth CHK_SV; 4575f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45762c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4577fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 457859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4579fcf5ef2aSThomas Huth #endif 4580fcf5ef2aSThomas Huth } 4581fcf5ef2aSThomas Huth 4582fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4583fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4584fcf5ef2aSThomas Huth { 4585fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4586fcf5ef2aSThomas Huth GEN_PRIV; 4587fcf5ef2aSThomas Huth #else 4588fcf5ef2aSThomas Huth /* Restore CPU state */ 4589fcf5ef2aSThomas Huth CHK_SV; 4590f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45912c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4592fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 459359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4594fcf5ef2aSThomas Huth #endif 4595fcf5ef2aSThomas Huth } 4596fcf5ef2aSThomas Huth 45973c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45983c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 45993c89b8d6SNicholas Piggin { 46003c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 46013c89b8d6SNicholas Piggin GEN_PRIV; 46023c89b8d6SNicholas Piggin #else 46033c89b8d6SNicholas Piggin /* Restore CPU state */ 46043c89b8d6SNicholas Piggin CHK_SV; 4605f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46062c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 46073c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 460859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 46093c89b8d6SNicholas Piggin #endif 46103c89b8d6SNicholas Piggin } 46113c89b8d6SNicholas Piggin #endif 46123c89b8d6SNicholas Piggin 4613fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4614fcf5ef2aSThomas Huth { 4615fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4616fcf5ef2aSThomas Huth GEN_PRIV; 4617fcf5ef2aSThomas Huth #else 4618fcf5ef2aSThomas Huth /* Restore CPU state */ 4619fcf5ef2aSThomas Huth CHK_HV; 4620fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 462159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4622fcf5ef2aSThomas Huth #endif 4623fcf5ef2aSThomas Huth } 4624fcf5ef2aSThomas Huth #endif 4625fcf5ef2aSThomas Huth 4626fcf5ef2aSThomas Huth /* sc */ 4627fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4628fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4629fcf5ef2aSThomas Huth #else 4630fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 46313c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4632fcf5ef2aSThomas Huth #endif 4633fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4634fcf5ef2aSThomas Huth { 4635fcf5ef2aSThomas Huth uint32_t lev; 4636fcf5ef2aSThomas Huth 4637fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4638fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4639fcf5ef2aSThomas Huth } 4640fcf5ef2aSThomas Huth 46413c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 46423c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46433c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 46443c89b8d6SNicholas Piggin { 4645f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 46463c89b8d6SNicholas Piggin 4647f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 46482c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4649f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 46503c89b8d6SNicholas Piggin 46517a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 46523c89b8d6SNicholas Piggin } 46533c89b8d6SNicholas Piggin #endif 46543c89b8d6SNicholas Piggin #endif 46553c89b8d6SNicholas Piggin 4656fcf5ef2aSThomas Huth /*** Trap ***/ 4657fcf5ef2aSThomas Huth 4658fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4659fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4660fcf5ef2aSThomas Huth { 4661fcf5ef2aSThomas Huth /* Trap never */ 4662fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4663fcf5ef2aSThomas Huth return true; 4664fcf5ef2aSThomas Huth } 4665fcf5ef2aSThomas Huth /* Trap always */ 4666fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4667fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4668fcf5ef2aSThomas Huth return true; 4669fcf5ef2aSThomas Huth } 4670fcf5ef2aSThomas Huth return false; 4671fcf5ef2aSThomas Huth } 4672fcf5ef2aSThomas Huth 4673fcf5ef2aSThomas Huth /* tw */ 4674fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4675fcf5ef2aSThomas Huth { 4676fcf5ef2aSThomas Huth TCGv_i32 t0; 4677fcf5ef2aSThomas Huth 4678fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4679fcf5ef2aSThomas Huth return; 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4682fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4683fcf5ef2aSThomas Huth t0); 4684fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4685fcf5ef2aSThomas Huth } 4686fcf5ef2aSThomas Huth 4687fcf5ef2aSThomas Huth /* twi */ 4688fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4689fcf5ef2aSThomas Huth { 4690fcf5ef2aSThomas Huth TCGv t0; 4691fcf5ef2aSThomas Huth TCGv_i32 t1; 4692fcf5ef2aSThomas Huth 4693fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4694fcf5ef2aSThomas Huth return; 4695fcf5ef2aSThomas Huth } 4696fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4697fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4698fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4699fcf5ef2aSThomas Huth tcg_temp_free(t0); 4700fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4701fcf5ef2aSThomas Huth } 4702fcf5ef2aSThomas Huth 4703fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4704fcf5ef2aSThomas Huth /* td */ 4705fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4706fcf5ef2aSThomas Huth { 4707fcf5ef2aSThomas Huth TCGv_i32 t0; 4708fcf5ef2aSThomas Huth 4709fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4710fcf5ef2aSThomas Huth return; 4711fcf5ef2aSThomas Huth } 4712fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4713fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4714fcf5ef2aSThomas Huth t0); 4715fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4716fcf5ef2aSThomas Huth } 4717fcf5ef2aSThomas Huth 4718fcf5ef2aSThomas Huth /* tdi */ 4719fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4720fcf5ef2aSThomas Huth { 4721fcf5ef2aSThomas Huth TCGv t0; 4722fcf5ef2aSThomas Huth TCGv_i32 t1; 4723fcf5ef2aSThomas Huth 4724fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4725fcf5ef2aSThomas Huth return; 4726fcf5ef2aSThomas Huth } 4727fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4728fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4729fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4730fcf5ef2aSThomas Huth tcg_temp_free(t0); 4731fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4732fcf5ef2aSThomas Huth } 4733fcf5ef2aSThomas Huth #endif 4734fcf5ef2aSThomas Huth 4735fcf5ef2aSThomas Huth /*** Processor control ***/ 4736fcf5ef2aSThomas Huth 4737fcf5ef2aSThomas Huth /* mcrxr */ 4738fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4739fcf5ef2aSThomas Huth { 4740fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4741fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4742fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4743fcf5ef2aSThomas Huth 4744fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4745fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4746fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4747fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4748fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4749fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4750fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4751fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4752fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4753fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4754fcf5ef2aSThomas Huth 4755fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4756fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4757fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4758fcf5ef2aSThomas Huth } 4759fcf5ef2aSThomas Huth 4760b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4761b63d0434SNikunj A Dadhania /* mcrxrx */ 4762b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4763b63d0434SNikunj A Dadhania { 4764b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4765b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4766b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4767b63d0434SNikunj A Dadhania 4768b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4769b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4770b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4771b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4772b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4773b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4774b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4775b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4776b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4777b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4778b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4779b63d0434SNikunj A Dadhania } 4780b63d0434SNikunj A Dadhania #endif 4781b63d0434SNikunj A Dadhania 4782fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4783fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4784fcf5ef2aSThomas Huth { 4785fcf5ef2aSThomas Huth uint32_t crm, crn; 4786fcf5ef2aSThomas Huth 4787fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4788fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4789fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4790fcf5ef2aSThomas Huth crn = ctz32(crm); 4791fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4792fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4793fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4794fcf5ef2aSThomas Huth } 4795fcf5ef2aSThomas Huth } else { 4796fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4797fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4798fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4799fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4800fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4801fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4802fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4803fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4804fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4805fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4806fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4807fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4808fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4809fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4810fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4811fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4812fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4813fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4814fcf5ef2aSThomas Huth } 4815fcf5ef2aSThomas Huth } 4816fcf5ef2aSThomas Huth 4817fcf5ef2aSThomas Huth /* mfmsr */ 4818fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4819fcf5ef2aSThomas Huth { 4820fcf5ef2aSThomas Huth CHK_SV; 4821fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4822fcf5ef2aSThomas Huth } 4823fcf5ef2aSThomas Huth 4824fcf5ef2aSThomas Huth /* mfspr */ 4825fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4826fcf5ef2aSThomas Huth { 4827fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4828fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4829fcf5ef2aSThomas Huth 4830fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4831fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4832fcf5ef2aSThomas Huth #else 4833fcf5ef2aSThomas Huth if (ctx->pr) { 4834fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4835fcf5ef2aSThomas Huth } else if (ctx->hv) { 4836fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4837fcf5ef2aSThomas Huth } else { 4838fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4839fcf5ef2aSThomas Huth } 4840fcf5ef2aSThomas Huth #endif 4841fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4842fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4843fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4844fcf5ef2aSThomas Huth } else { 4845fcf5ef2aSThomas Huth /* Privilege exception */ 4846efe843d8SDavid Gibson /* 4847efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4848fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4849fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4850fcf5ef2aSThomas Huth */ 4851fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 485231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 485331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48542c2bcb1bSRichard Henderson ctx->cia); 4855fcf5ef2aSThomas Huth } 4856fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4857fcf5ef2aSThomas Huth } 4858fcf5ef2aSThomas Huth } else { 4859fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4860fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4861fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4862fcf5ef2aSThomas Huth /* This is a nop */ 4863fcf5ef2aSThomas Huth return; 4864fcf5ef2aSThomas Huth } 4865fcf5ef2aSThomas Huth /* Not defined */ 486631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 486731085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 48682c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4869fcf5ef2aSThomas Huth 4870efe843d8SDavid Gibson /* 4871efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4872efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4873fcf5ef2aSThomas Huth */ 4874fcf5ef2aSThomas Huth if (sprn & 0x10) { 4875fcf5ef2aSThomas Huth if (ctx->pr) { 4876fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4877fcf5ef2aSThomas Huth } 4878fcf5ef2aSThomas Huth } else { 4879fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4880fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4881fcf5ef2aSThomas Huth } 4882fcf5ef2aSThomas Huth } 4883fcf5ef2aSThomas Huth } 4884fcf5ef2aSThomas Huth } 4885fcf5ef2aSThomas Huth 4886fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4887fcf5ef2aSThomas Huth { 4888fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4889fcf5ef2aSThomas Huth } 4890fcf5ef2aSThomas Huth 4891fcf5ef2aSThomas Huth /* mftb */ 4892fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4893fcf5ef2aSThomas Huth { 4894fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4895fcf5ef2aSThomas Huth } 4896fcf5ef2aSThomas Huth 4897fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4898fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4899fcf5ef2aSThomas Huth { 4900fcf5ef2aSThomas Huth uint32_t crm, crn; 4901fcf5ef2aSThomas Huth 4902fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4903fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4904fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4905fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4906fcf5ef2aSThomas Huth crn = ctz32(crm); 4907fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4908fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4909fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4910fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4911fcf5ef2aSThomas Huth } 4912fcf5ef2aSThomas Huth } else { 4913fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4914fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4915fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4916fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4917fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4918fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4919fcf5ef2aSThomas Huth } 4920fcf5ef2aSThomas Huth } 4921fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4922fcf5ef2aSThomas Huth } 4923fcf5ef2aSThomas Huth } 4924fcf5ef2aSThomas Huth 4925fcf5ef2aSThomas Huth /* mtmsr */ 4926fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4927fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4928fcf5ef2aSThomas Huth { 4929caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4930caf590ddSNicholas Piggin gen_invalid(ctx); 4931caf590ddSNicholas Piggin return; 4932caf590ddSNicholas Piggin } 4933caf590ddSNicholas Piggin 4934fcf5ef2aSThomas Huth CHK_SV; 4935fcf5ef2aSThomas Huth 4936fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4937*6fa5726bSMatheus Ferst TCGv t0, t1; 4938*6fa5726bSMatheus Ferst target_ulong mask; 4939*6fa5726bSMatheus Ferst 4940*6fa5726bSMatheus Ferst t0 = tcg_temp_new(); 4941*6fa5726bSMatheus Ferst t1 = tcg_temp_new(); 4942*6fa5726bSMatheus Ferst 4943f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4944*6fa5726bSMatheus Ferst 4945fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49465ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 4947*6fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4948fcf5ef2aSThomas Huth } else { 4949*6fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 4950*6fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4951*6fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4952efe843d8SDavid Gibson /* 4953efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4954efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4955efe843d8SDavid Gibson * ppc_store_msr 4956fcf5ef2aSThomas Huth */ 4957b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4958fcf5ef2aSThomas Huth } 4959*6fa5726bSMatheus Ferst 4960*6fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4961*6fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4962*6fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 4963*6fa5726bSMatheus Ferst 4964*6fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 4965*6fa5726bSMatheus Ferst 49665ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4967d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4968*6fa5726bSMatheus Ferst 4969*6fa5726bSMatheus Ferst tcg_temp_free(t0); 4970*6fa5726bSMatheus Ferst tcg_temp_free(t1); 4971fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4972fcf5ef2aSThomas Huth } 4973fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4974fcf5ef2aSThomas Huth 4975fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4976fcf5ef2aSThomas Huth { 4977fcf5ef2aSThomas Huth CHK_SV; 4978fcf5ef2aSThomas Huth 4979fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4980*6fa5726bSMatheus Ferst TCGv t0, t1; 4981*6fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 4982*6fa5726bSMatheus Ferst 4983*6fa5726bSMatheus Ferst t0 = tcg_temp_new(); 4984*6fa5726bSMatheus Ferst t1 = tcg_temp_new(); 4985*6fa5726bSMatheus Ferst 4986f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4987fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49885ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 4989*6fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4990fcf5ef2aSThomas Huth } else { 4991*6fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 4992*6fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4993fcf5ef2aSThomas Huth 4994efe843d8SDavid Gibson /* 4995efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4996efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4997efe843d8SDavid Gibson * ppc_store_msr 4998fcf5ef2aSThomas Huth */ 4999b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5000fcf5ef2aSThomas Huth } 5001*6fa5726bSMatheus Ferst 5002*6fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 5003*6fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 5004*6fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 5005*6fa5726bSMatheus Ferst 5006*6fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 5007*6fa5726bSMatheus Ferst 50085ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5009d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5010*6fa5726bSMatheus Ferst 5011*6fa5726bSMatheus Ferst tcg_temp_free(t0); 5012*6fa5726bSMatheus Ferst tcg_temp_free(t1); 5013fcf5ef2aSThomas Huth #endif 5014fcf5ef2aSThomas Huth } 5015fcf5ef2aSThomas Huth 5016fcf5ef2aSThomas Huth /* mtspr */ 5017fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5018fcf5ef2aSThomas Huth { 5019fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5020fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5021fcf5ef2aSThomas Huth 5022fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5023fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5024fcf5ef2aSThomas Huth #else 5025fcf5ef2aSThomas Huth if (ctx->pr) { 5026fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5027fcf5ef2aSThomas Huth } else if (ctx->hv) { 5028fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5029fcf5ef2aSThomas Huth } else { 5030fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5031fcf5ef2aSThomas Huth } 5032fcf5ef2aSThomas Huth #endif 5033fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5034fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5035fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5036fcf5ef2aSThomas Huth } else { 5037fcf5ef2aSThomas Huth /* Privilege exception */ 503831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 503931085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 50402c2bcb1bSRichard Henderson ctx->cia); 5041fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5042fcf5ef2aSThomas Huth } 5043fcf5ef2aSThomas Huth } else { 5044fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5045fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5046fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5047fcf5ef2aSThomas Huth /* This is a nop */ 5048fcf5ef2aSThomas Huth return; 5049fcf5ef2aSThomas Huth } 5050fcf5ef2aSThomas Huth 5051fcf5ef2aSThomas Huth /* Not defined */ 505231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 505331085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 50542c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5055fcf5ef2aSThomas Huth 5056fcf5ef2aSThomas Huth 5057efe843d8SDavid Gibson /* 5058efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5059efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5060fcf5ef2aSThomas Huth */ 5061fcf5ef2aSThomas Huth if (sprn & 0x10) { 5062fcf5ef2aSThomas Huth if (ctx->pr) { 5063fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5064fcf5ef2aSThomas Huth } 5065fcf5ef2aSThomas Huth } else { 5066fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5067fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5068fcf5ef2aSThomas Huth } 5069fcf5ef2aSThomas Huth } 5070fcf5ef2aSThomas Huth } 5071fcf5ef2aSThomas Huth } 5072fcf5ef2aSThomas Huth 5073fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5074fcf5ef2aSThomas Huth /* setb */ 5075fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5076fcf5ef2aSThomas Huth { 5077fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 50786f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 50796f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5080fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5081fcf5ef2aSThomas Huth 5082fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5083fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5084fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5085fcf5ef2aSThomas Huth 5086fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5087fcf5ef2aSThomas Huth } 5088fcf5ef2aSThomas Huth #endif 5089fcf5ef2aSThomas Huth 5090fcf5ef2aSThomas Huth /*** Cache management ***/ 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth /* dcbf */ 5093fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5094fcf5ef2aSThomas Huth { 5095fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5096fcf5ef2aSThomas Huth TCGv t0; 5097fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5098fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5099fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5100fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5101fcf5ef2aSThomas Huth tcg_temp_free(t0); 5102fcf5ef2aSThomas Huth } 5103fcf5ef2aSThomas Huth 510450728199SRoman Kapl /* dcbfep (external PID dcbf) */ 510550728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 510650728199SRoman Kapl { 510750728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 510850728199SRoman Kapl TCGv t0; 510950728199SRoman Kapl CHK_SV; 511050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 511150728199SRoman Kapl t0 = tcg_temp_new(); 511250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 511350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 511450728199SRoman Kapl tcg_temp_free(t0); 511550728199SRoman Kapl } 511650728199SRoman Kapl 5117fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5118fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5119fcf5ef2aSThomas Huth { 5120fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5121fcf5ef2aSThomas Huth GEN_PRIV; 5122fcf5ef2aSThomas Huth #else 5123fcf5ef2aSThomas Huth TCGv EA, val; 5124fcf5ef2aSThomas Huth 5125fcf5ef2aSThomas Huth CHK_SV; 5126fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5127fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5128fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5129fcf5ef2aSThomas Huth val = tcg_temp_new(); 5130fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5131fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5132fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5133fcf5ef2aSThomas Huth tcg_temp_free(val); 5134fcf5ef2aSThomas Huth tcg_temp_free(EA); 5135fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5136fcf5ef2aSThomas Huth } 5137fcf5ef2aSThomas Huth 5138fcf5ef2aSThomas Huth /* dcdst */ 5139fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5140fcf5ef2aSThomas Huth { 5141fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5142fcf5ef2aSThomas Huth TCGv t0; 5143fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5144fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5145fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5146fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5147fcf5ef2aSThomas Huth tcg_temp_free(t0); 5148fcf5ef2aSThomas Huth } 5149fcf5ef2aSThomas Huth 515050728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 515150728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 515250728199SRoman Kapl { 515350728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 515450728199SRoman Kapl TCGv t0; 515550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 515650728199SRoman Kapl t0 = tcg_temp_new(); 515750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 515850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 515950728199SRoman Kapl tcg_temp_free(t0); 516050728199SRoman Kapl } 516150728199SRoman Kapl 5162fcf5ef2aSThomas Huth /* dcbt */ 5163fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5164fcf5ef2aSThomas Huth { 5165efe843d8SDavid Gibson /* 5166efe843d8SDavid Gibson * interpreted as no-op 5167efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5168efe843d8SDavid Gibson * does not generate any exception 5169fcf5ef2aSThomas Huth */ 5170fcf5ef2aSThomas Huth } 5171fcf5ef2aSThomas Huth 517250728199SRoman Kapl /* dcbtep */ 517350728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 517450728199SRoman Kapl { 5175efe843d8SDavid Gibson /* 5176efe843d8SDavid Gibson * interpreted as no-op 5177efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5178efe843d8SDavid Gibson * does not generate any exception 517950728199SRoman Kapl */ 518050728199SRoman Kapl } 518150728199SRoman Kapl 5182fcf5ef2aSThomas Huth /* dcbtst */ 5183fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5184fcf5ef2aSThomas Huth { 5185efe843d8SDavid Gibson /* 5186efe843d8SDavid Gibson * interpreted as no-op 5187efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5188efe843d8SDavid Gibson * does not generate any exception 5189fcf5ef2aSThomas Huth */ 5190fcf5ef2aSThomas Huth } 5191fcf5ef2aSThomas Huth 519250728199SRoman Kapl /* dcbtstep */ 519350728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 519450728199SRoman Kapl { 5195efe843d8SDavid Gibson /* 5196efe843d8SDavid Gibson * interpreted as no-op 5197efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5198efe843d8SDavid Gibson * does not generate any exception 519950728199SRoman Kapl */ 520050728199SRoman Kapl } 520150728199SRoman Kapl 5202fcf5ef2aSThomas Huth /* dcbtls */ 5203fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5204fcf5ef2aSThomas Huth { 5205fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5206fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5207fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5208fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5209fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5210fcf5ef2aSThomas Huth tcg_temp_free(t0); 5211fcf5ef2aSThomas Huth } 5212fcf5ef2aSThomas Huth 5213fcf5ef2aSThomas Huth /* dcbz */ 5214fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5215fcf5ef2aSThomas Huth { 5216fcf5ef2aSThomas Huth TCGv tcgv_addr; 5217fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5218fcf5ef2aSThomas Huth 5219fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5220fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5221fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5222fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5223fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5224fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5225fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5226fcf5ef2aSThomas Huth } 5227fcf5ef2aSThomas Huth 522850728199SRoman Kapl /* dcbzep */ 522950728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 523050728199SRoman Kapl { 523150728199SRoman Kapl TCGv tcgv_addr; 523250728199SRoman Kapl TCGv_i32 tcgv_op; 523350728199SRoman Kapl 523450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 523550728199SRoman Kapl tcgv_addr = tcg_temp_new(); 523650728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 523750728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 523850728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 523950728199SRoman Kapl tcg_temp_free(tcgv_addr); 524050728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 524150728199SRoman Kapl } 524250728199SRoman Kapl 5243fcf5ef2aSThomas Huth /* dst / dstt */ 5244fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5245fcf5ef2aSThomas Huth { 5246fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5247fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5248fcf5ef2aSThomas Huth } else { 5249fcf5ef2aSThomas Huth /* interpreted as no-op */ 5250fcf5ef2aSThomas Huth } 5251fcf5ef2aSThomas Huth } 5252fcf5ef2aSThomas Huth 5253fcf5ef2aSThomas Huth /* dstst /dststt */ 5254fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5255fcf5ef2aSThomas Huth { 5256fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5257fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5258fcf5ef2aSThomas Huth } else { 5259fcf5ef2aSThomas Huth /* interpreted as no-op */ 5260fcf5ef2aSThomas Huth } 5261fcf5ef2aSThomas Huth 5262fcf5ef2aSThomas Huth } 5263fcf5ef2aSThomas Huth 5264fcf5ef2aSThomas Huth /* dss / dssall */ 5265fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5266fcf5ef2aSThomas Huth { 5267fcf5ef2aSThomas Huth /* interpreted as no-op */ 5268fcf5ef2aSThomas Huth } 5269fcf5ef2aSThomas Huth 5270fcf5ef2aSThomas Huth /* icbi */ 5271fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5272fcf5ef2aSThomas Huth { 5273fcf5ef2aSThomas Huth TCGv t0; 5274fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5275fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5276fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5277fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5278fcf5ef2aSThomas Huth tcg_temp_free(t0); 5279fcf5ef2aSThomas Huth } 5280fcf5ef2aSThomas Huth 528150728199SRoman Kapl /* icbiep */ 528250728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 528350728199SRoman Kapl { 528450728199SRoman Kapl TCGv t0; 528550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 528650728199SRoman Kapl t0 = tcg_temp_new(); 528750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 528850728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 528950728199SRoman Kapl tcg_temp_free(t0); 529050728199SRoman Kapl } 529150728199SRoman Kapl 5292fcf5ef2aSThomas Huth /* Optional: */ 5293fcf5ef2aSThomas Huth /* dcba */ 5294fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5295fcf5ef2aSThomas Huth { 5296efe843d8SDavid Gibson /* 5297efe843d8SDavid Gibson * interpreted as no-op 5298efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5299fcf5ef2aSThomas Huth * but does not generate any exception 5300fcf5ef2aSThomas Huth */ 5301fcf5ef2aSThomas Huth } 5302fcf5ef2aSThomas Huth 5303fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5304fcf5ef2aSThomas Huth /* Supervisor only: */ 5305fcf5ef2aSThomas Huth 5306fcf5ef2aSThomas Huth /* mfsr */ 5307fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5308fcf5ef2aSThomas Huth { 5309fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5310fcf5ef2aSThomas Huth GEN_PRIV; 5311fcf5ef2aSThomas Huth #else 5312fcf5ef2aSThomas Huth TCGv t0; 5313fcf5ef2aSThomas Huth 5314fcf5ef2aSThomas Huth CHK_SV; 5315fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5316fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5317fcf5ef2aSThomas Huth tcg_temp_free(t0); 5318fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5319fcf5ef2aSThomas Huth } 5320fcf5ef2aSThomas Huth 5321fcf5ef2aSThomas Huth /* mfsrin */ 5322fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5323fcf5ef2aSThomas Huth { 5324fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5325fcf5ef2aSThomas Huth GEN_PRIV; 5326fcf5ef2aSThomas Huth #else 5327fcf5ef2aSThomas Huth TCGv t0; 5328fcf5ef2aSThomas Huth 5329fcf5ef2aSThomas Huth CHK_SV; 5330fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5331e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5332fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5333fcf5ef2aSThomas Huth tcg_temp_free(t0); 5334fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5335fcf5ef2aSThomas Huth } 5336fcf5ef2aSThomas Huth 5337fcf5ef2aSThomas Huth /* mtsr */ 5338fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5339fcf5ef2aSThomas Huth { 5340fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5341fcf5ef2aSThomas Huth GEN_PRIV; 5342fcf5ef2aSThomas Huth #else 5343fcf5ef2aSThomas Huth TCGv t0; 5344fcf5ef2aSThomas Huth 5345fcf5ef2aSThomas Huth CHK_SV; 5346fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5347fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5348fcf5ef2aSThomas Huth tcg_temp_free(t0); 5349fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5350fcf5ef2aSThomas Huth } 5351fcf5ef2aSThomas Huth 5352fcf5ef2aSThomas Huth /* mtsrin */ 5353fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5354fcf5ef2aSThomas Huth { 5355fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5356fcf5ef2aSThomas Huth GEN_PRIV; 5357fcf5ef2aSThomas Huth #else 5358fcf5ef2aSThomas Huth TCGv t0; 5359fcf5ef2aSThomas Huth CHK_SV; 5360fcf5ef2aSThomas Huth 5361fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5362e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5363fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5364fcf5ef2aSThomas Huth tcg_temp_free(t0); 5365fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5366fcf5ef2aSThomas Huth } 5367fcf5ef2aSThomas Huth 5368fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5369fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5370fcf5ef2aSThomas Huth 5371fcf5ef2aSThomas Huth /* mfsr */ 5372fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5373fcf5ef2aSThomas Huth { 5374fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5375fcf5ef2aSThomas Huth GEN_PRIV; 5376fcf5ef2aSThomas Huth #else 5377fcf5ef2aSThomas Huth TCGv t0; 5378fcf5ef2aSThomas Huth 5379fcf5ef2aSThomas Huth CHK_SV; 5380fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5381fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5382fcf5ef2aSThomas Huth tcg_temp_free(t0); 5383fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5384fcf5ef2aSThomas Huth } 5385fcf5ef2aSThomas Huth 5386fcf5ef2aSThomas Huth /* mfsrin */ 5387fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5388fcf5ef2aSThomas Huth { 5389fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5390fcf5ef2aSThomas Huth GEN_PRIV; 5391fcf5ef2aSThomas Huth #else 5392fcf5ef2aSThomas Huth TCGv t0; 5393fcf5ef2aSThomas Huth 5394fcf5ef2aSThomas Huth CHK_SV; 5395fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5396e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5397fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5398fcf5ef2aSThomas Huth tcg_temp_free(t0); 5399fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5400fcf5ef2aSThomas Huth } 5401fcf5ef2aSThomas Huth 5402fcf5ef2aSThomas Huth /* mtsr */ 5403fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5404fcf5ef2aSThomas Huth { 5405fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5406fcf5ef2aSThomas Huth GEN_PRIV; 5407fcf5ef2aSThomas Huth #else 5408fcf5ef2aSThomas Huth TCGv t0; 5409fcf5ef2aSThomas Huth 5410fcf5ef2aSThomas Huth CHK_SV; 5411fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5412fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5413fcf5ef2aSThomas Huth tcg_temp_free(t0); 5414fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5415fcf5ef2aSThomas Huth } 5416fcf5ef2aSThomas Huth 5417fcf5ef2aSThomas Huth /* mtsrin */ 5418fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5419fcf5ef2aSThomas Huth { 5420fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5421fcf5ef2aSThomas Huth GEN_PRIV; 5422fcf5ef2aSThomas Huth #else 5423fcf5ef2aSThomas Huth TCGv t0; 5424fcf5ef2aSThomas Huth 5425fcf5ef2aSThomas Huth CHK_SV; 5426fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5427e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5428fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5429fcf5ef2aSThomas Huth tcg_temp_free(t0); 5430fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5431fcf5ef2aSThomas Huth } 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth /* slbmte */ 5434fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5435fcf5ef2aSThomas Huth { 5436fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5437fcf5ef2aSThomas Huth GEN_PRIV; 5438fcf5ef2aSThomas Huth #else 5439fcf5ef2aSThomas Huth CHK_SV; 5440fcf5ef2aSThomas Huth 5441fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5442fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5443fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5444fcf5ef2aSThomas Huth } 5445fcf5ef2aSThomas Huth 5446fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5447fcf5ef2aSThomas Huth { 5448fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5449fcf5ef2aSThomas Huth GEN_PRIV; 5450fcf5ef2aSThomas Huth #else 5451fcf5ef2aSThomas Huth CHK_SV; 5452fcf5ef2aSThomas Huth 5453fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5454fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5455fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5456fcf5ef2aSThomas Huth } 5457fcf5ef2aSThomas Huth 5458fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5459fcf5ef2aSThomas Huth { 5460fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5461fcf5ef2aSThomas Huth GEN_PRIV; 5462fcf5ef2aSThomas Huth #else 5463fcf5ef2aSThomas Huth CHK_SV; 5464fcf5ef2aSThomas Huth 5465fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5466fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5467fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5468fcf5ef2aSThomas Huth } 5469fcf5ef2aSThomas Huth 5470fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5471fcf5ef2aSThomas Huth { 5472fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5473fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5474fcf5ef2aSThomas Huth #else 5475fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5476fcf5ef2aSThomas Huth 5477fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5478fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5479fcf5ef2aSThomas Huth return; 5480fcf5ef2aSThomas Huth } 5481fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5482fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5483fcf5ef2aSThomas Huth l1 = gen_new_label(); 5484fcf5ef2aSThomas Huth l2 = gen_new_label(); 5485fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5486fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5487efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5488fcf5ef2aSThomas Huth tcg_gen_br(l2); 5489fcf5ef2aSThomas Huth gen_set_label(l1); 5490fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5491fcf5ef2aSThomas Huth gen_set_label(l2); 5492fcf5ef2aSThomas Huth #endif 5493fcf5ef2aSThomas Huth } 5494fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5495fcf5ef2aSThomas Huth 5496fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5497fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5498fcf5ef2aSThomas Huth 5499fcf5ef2aSThomas Huth /* tlbia */ 5500fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5501fcf5ef2aSThomas Huth { 5502fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5503fcf5ef2aSThomas Huth GEN_PRIV; 5504fcf5ef2aSThomas Huth #else 5505fcf5ef2aSThomas Huth CHK_HV; 5506fcf5ef2aSThomas Huth 5507fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5508fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5509fcf5ef2aSThomas Huth } 5510fcf5ef2aSThomas Huth 5511fcf5ef2aSThomas Huth /* tlbiel */ 5512fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5513fcf5ef2aSThomas Huth { 5514fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5515fcf5ef2aSThomas Huth GEN_PRIV; 5516fcf5ef2aSThomas Huth #else 551792fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 551892fb92d3SMatheus Ferst 551992fb92d3SMatheus Ferst if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) { 552092fb92d3SMatheus Ferst /* 552192fb92d3SMatheus Ferst * tlbiel is privileged except when PSR=0 and HR=1, making it 552292fb92d3SMatheus Ferst * hypervisor privileged. 552392fb92d3SMatheus Ferst */ 552492fb92d3SMatheus Ferst GEN_PRIV; 552592fb92d3SMatheus Ferst } 5526fcf5ef2aSThomas Huth 5527fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5528fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5529fcf5ef2aSThomas Huth } 5530fcf5ef2aSThomas Huth 5531fcf5ef2aSThomas Huth /* tlbie */ 5532fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5533fcf5ef2aSThomas Huth { 5534fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5535fcf5ef2aSThomas Huth GEN_PRIV; 5536fcf5ef2aSThomas Huth #else 553792fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 5538fcf5ef2aSThomas Huth TCGv_i32 t1; 5539c6fd28fdSSuraj Jitindar Singh 554092fb92d3SMatheus Ferst if (ctx->pr) { 554192fb92d3SMatheus Ferst /* tlbie is privileged... */ 554292fb92d3SMatheus Ferst GEN_PRIV; 554392fb92d3SMatheus Ferst } else if (!ctx->hv) { 554492fb92d3SMatheus Ferst if (!ctx->gtse || (!psr && ctx->hr)) { 554592fb92d3SMatheus Ferst /* 554692fb92d3SMatheus Ferst * ... except when GTSE=0 or when PSR=0 and HR=1, making it 554792fb92d3SMatheus Ferst * hypervisor privileged. 554892fb92d3SMatheus Ferst */ 554992fb92d3SMatheus Ferst GEN_PRIV; 555092fb92d3SMatheus Ferst } 5551c6fd28fdSSuraj Jitindar Singh } 5552fcf5ef2aSThomas Huth 5553fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5554fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5555fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5556fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5557fcf5ef2aSThomas Huth tcg_temp_free(t0); 5558fcf5ef2aSThomas Huth } else { 5559fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5560fcf5ef2aSThomas Huth } 5561fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5562fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5563fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5564fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5565fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5566fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5567fcf5ef2aSThomas Huth } 5568fcf5ef2aSThomas Huth 5569fcf5ef2aSThomas Huth /* tlbsync */ 5570fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5571fcf5ef2aSThomas Huth { 5572fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5573fcf5ef2aSThomas Huth GEN_PRIV; 5574fcf5ef2aSThomas Huth #else 557591c60f12SCédric Le Goater 557691c60f12SCédric Le Goater if (ctx->gtse) { 557791c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 557891c60f12SCédric Le Goater } else { 557991c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 558091c60f12SCédric Le Goater } 5581fcf5ef2aSThomas Huth 5582fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5583fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5584fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5585fcf5ef2aSThomas Huth } 5586fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5587fcf5ef2aSThomas Huth } 5588fcf5ef2aSThomas Huth 5589fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5590fcf5ef2aSThomas Huth /* slbia */ 5591fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5592fcf5ef2aSThomas Huth { 5593fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5594fcf5ef2aSThomas Huth GEN_PRIV; 5595fcf5ef2aSThomas Huth #else 55960418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 55970418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 55980418bf78SNicholas Piggin 5599fcf5ef2aSThomas Huth CHK_SV; 5600fcf5ef2aSThomas Huth 56010418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 56023119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5603fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5604fcf5ef2aSThomas Huth } 5605fcf5ef2aSThomas Huth 5606fcf5ef2aSThomas Huth /* slbie */ 5607fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5608fcf5ef2aSThomas Huth { 5609fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5610fcf5ef2aSThomas Huth GEN_PRIV; 5611fcf5ef2aSThomas Huth #else 5612fcf5ef2aSThomas Huth CHK_SV; 5613fcf5ef2aSThomas Huth 5614fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5615fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5616fcf5ef2aSThomas Huth } 5617a63f1dfcSNikunj A Dadhania 5618a63f1dfcSNikunj A Dadhania /* slbieg */ 5619a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5620a63f1dfcSNikunj A Dadhania { 5621a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5622a63f1dfcSNikunj A Dadhania GEN_PRIV; 5623a63f1dfcSNikunj A Dadhania #else 5624a63f1dfcSNikunj A Dadhania CHK_SV; 5625a63f1dfcSNikunj A Dadhania 5626a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5627a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5628a63f1dfcSNikunj A Dadhania } 5629a63f1dfcSNikunj A Dadhania 563062d897caSNikunj A Dadhania /* slbsync */ 563162d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 563262d897caSNikunj A Dadhania { 563362d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 563462d897caSNikunj A Dadhania GEN_PRIV; 563562d897caSNikunj A Dadhania #else 563662d897caSNikunj A Dadhania CHK_SV; 563762d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 563862d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 563962d897caSNikunj A Dadhania } 564062d897caSNikunj A Dadhania 5641fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5642fcf5ef2aSThomas Huth 5643fcf5ef2aSThomas Huth /*** External control ***/ 5644fcf5ef2aSThomas Huth /* Optional: */ 5645fcf5ef2aSThomas Huth 5646fcf5ef2aSThomas Huth /* eciwx */ 5647fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5648fcf5ef2aSThomas Huth { 5649fcf5ef2aSThomas Huth TCGv t0; 5650fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5651fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5652fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5653fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5654c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5655c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5656fcf5ef2aSThomas Huth tcg_temp_free(t0); 5657fcf5ef2aSThomas Huth } 5658fcf5ef2aSThomas Huth 5659fcf5ef2aSThomas Huth /* ecowx */ 5660fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5661fcf5ef2aSThomas Huth { 5662fcf5ef2aSThomas Huth TCGv t0; 5663fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5664fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5665fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5666fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5667c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5668c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5669fcf5ef2aSThomas Huth tcg_temp_free(t0); 5670fcf5ef2aSThomas Huth } 5671fcf5ef2aSThomas Huth 5672fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5673fcf5ef2aSThomas Huth 5674fcf5ef2aSThomas Huth /* abs - abs. */ 5675fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5676fcf5ef2aSThomas Huth { 5677fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5678fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5679fe21b785SRichard Henderson 5680fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5681efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5682fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5683fcf5ef2aSThomas Huth } 5684efe843d8SDavid Gibson } 5685fcf5ef2aSThomas Huth 5686fcf5ef2aSThomas Huth /* abso - abso. */ 5687fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5688fcf5ef2aSThomas Huth { 5689fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5690fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5691fe21b785SRichard Henderson 5692fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5693fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5694fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5695efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5696fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5697fcf5ef2aSThomas Huth } 5698efe843d8SDavid Gibson } 5699fcf5ef2aSThomas Huth 5700fcf5ef2aSThomas Huth /* clcs */ 5701fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5702fcf5ef2aSThomas Huth { 5703fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5704fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5705fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5706fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5707fcf5ef2aSThomas Huth } 5708fcf5ef2aSThomas Huth 5709fcf5ef2aSThomas Huth /* div - div. */ 5710fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5711fcf5ef2aSThomas Huth { 5712fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5713fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5714efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5715fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5716fcf5ef2aSThomas Huth } 5717efe843d8SDavid Gibson } 5718fcf5ef2aSThomas Huth 5719fcf5ef2aSThomas Huth /* divo - divo. */ 5720fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5721fcf5ef2aSThomas Huth { 5722fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5723fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5724efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5725fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5726fcf5ef2aSThomas Huth } 5727efe843d8SDavid Gibson } 5728fcf5ef2aSThomas Huth 5729fcf5ef2aSThomas Huth /* divs - divs. */ 5730fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5731fcf5ef2aSThomas Huth { 5732fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5733fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5734efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5735fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5736fcf5ef2aSThomas Huth } 5737efe843d8SDavid Gibson } 5738fcf5ef2aSThomas Huth 5739fcf5ef2aSThomas Huth /* divso - divso. */ 5740fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5741fcf5ef2aSThomas Huth { 5742fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5743fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5744efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5745fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5746fcf5ef2aSThomas Huth } 5747efe843d8SDavid Gibson } 5748fcf5ef2aSThomas Huth 5749fcf5ef2aSThomas Huth /* doz - doz. */ 5750fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5751fcf5ef2aSThomas Huth { 5752fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5753fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5754efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5755efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5756efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5757efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5758fcf5ef2aSThomas Huth tcg_gen_br(l2); 5759fcf5ef2aSThomas Huth gen_set_label(l1); 5760fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5761fcf5ef2aSThomas Huth gen_set_label(l2); 5762efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5763fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5764fcf5ef2aSThomas Huth } 5765efe843d8SDavid Gibson } 5766fcf5ef2aSThomas Huth 5767fcf5ef2aSThomas Huth /* dozo - dozo. */ 5768fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5769fcf5ef2aSThomas Huth { 5770fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5771fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5772fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5773fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5774fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5775fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5776fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5777efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5778efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5779fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5780fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5781fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5782fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5783fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5784fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5785fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5786fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5787fcf5ef2aSThomas Huth tcg_gen_br(l2); 5788fcf5ef2aSThomas Huth gen_set_label(l1); 5789fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5790fcf5ef2aSThomas Huth gen_set_label(l2); 5791fcf5ef2aSThomas Huth tcg_temp_free(t0); 5792fcf5ef2aSThomas Huth tcg_temp_free(t1); 5793fcf5ef2aSThomas Huth tcg_temp_free(t2); 5794efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5795fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5796fcf5ef2aSThomas Huth } 5797efe843d8SDavid Gibson } 5798fcf5ef2aSThomas Huth 5799fcf5ef2aSThomas Huth /* dozi */ 5800fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5801fcf5ef2aSThomas Huth { 5802fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5803fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5804fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5805fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5806fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5807fcf5ef2aSThomas Huth tcg_gen_br(l2); 5808fcf5ef2aSThomas Huth gen_set_label(l1); 5809fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5810fcf5ef2aSThomas Huth gen_set_label(l2); 5811efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5812fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5813fcf5ef2aSThomas Huth } 5814efe843d8SDavid Gibson } 5815fcf5ef2aSThomas Huth 5816fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5817fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5818fcf5ef2aSThomas Huth { 5819fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5820fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5821fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5822fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5823fcf5ef2aSThomas Huth 5824fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5825fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5826fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5827fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5828fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5829fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5830fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5831efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5832fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5833efe843d8SDavid Gibson } 5834fcf5ef2aSThomas Huth tcg_temp_free(t0); 5835fcf5ef2aSThomas Huth } 5836fcf5ef2aSThomas Huth 5837fcf5ef2aSThomas Huth /* maskg - maskg. */ 5838fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5839fcf5ef2aSThomas Huth { 5840fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5841fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5842fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5843fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5844fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5845fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5846fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5847fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5848fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5849fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5850fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5851fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5852fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5853fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5854fcf5ef2aSThomas Huth gen_set_label(l1); 5855fcf5ef2aSThomas Huth tcg_temp_free(t0); 5856fcf5ef2aSThomas Huth tcg_temp_free(t1); 5857fcf5ef2aSThomas Huth tcg_temp_free(t2); 5858fcf5ef2aSThomas Huth tcg_temp_free(t3); 5859efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5860fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5861fcf5ef2aSThomas Huth } 5862efe843d8SDavid Gibson } 5863fcf5ef2aSThomas Huth 5864fcf5ef2aSThomas Huth /* maskir - maskir. */ 5865fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5866fcf5ef2aSThomas Huth { 5867fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5868fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5869fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5870fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5871fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5872fcf5ef2aSThomas Huth tcg_temp_free(t0); 5873fcf5ef2aSThomas Huth tcg_temp_free(t1); 5874efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5875fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5876fcf5ef2aSThomas Huth } 5877efe843d8SDavid Gibson } 5878fcf5ef2aSThomas Huth 5879fcf5ef2aSThomas Huth /* mul - mul. */ 5880fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5881fcf5ef2aSThomas Huth { 5882fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5883fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5884fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5885fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5886fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5887fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5888fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5889fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5890fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5891fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5892fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5893fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5894fcf5ef2aSThomas Huth tcg_temp_free(t2); 5895efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5896fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5897fcf5ef2aSThomas Huth } 5898efe843d8SDavid Gibson } 5899fcf5ef2aSThomas Huth 5900fcf5ef2aSThomas Huth /* mulo - mulo. */ 5901fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5902fcf5ef2aSThomas Huth { 5903fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5904fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5905fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5906fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5907fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5908fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5909fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5910fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5911fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5912fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5913fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5914fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5915fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5916fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5917fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5918fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5919fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5920fcf5ef2aSThomas Huth gen_set_label(l1); 5921fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5922fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5923fcf5ef2aSThomas Huth tcg_temp_free(t2); 5924efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5925fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5926fcf5ef2aSThomas Huth } 5927efe843d8SDavid Gibson } 5928fcf5ef2aSThomas Huth 5929fcf5ef2aSThomas Huth /* nabs - nabs. */ 5930fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5931fcf5ef2aSThomas Huth { 5932fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5933fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5934fe21b785SRichard Henderson 5935fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5936fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5937efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5938fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5939fcf5ef2aSThomas Huth } 5940efe843d8SDavid Gibson } 5941fcf5ef2aSThomas Huth 5942fcf5ef2aSThomas Huth /* nabso - nabso. */ 5943fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5944fcf5ef2aSThomas Huth { 5945fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5946fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5947fe21b785SRichard Henderson 5948fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5949fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5950fcf5ef2aSThomas Huth /* nabs never overflows */ 5951fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5952efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5953fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5954fcf5ef2aSThomas Huth } 5955efe843d8SDavid Gibson } 5956fcf5ef2aSThomas Huth 5957fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5958fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5959fcf5ef2aSThomas Huth { 5960fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5961fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5962fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5963fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5964fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5965fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5966efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5967efe843d8SDavid Gibson ~MASK(mb, me)); 5968fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5969fcf5ef2aSThomas Huth tcg_temp_free(t0); 5970efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5971fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5972fcf5ef2aSThomas Huth } 5973efe843d8SDavid Gibson } 5974fcf5ef2aSThomas Huth 5975fcf5ef2aSThomas Huth /* rrib - rrib. */ 5976fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5977fcf5ef2aSThomas Huth { 5978fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5979fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5980fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5981fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5982fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5983fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5984fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5985fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5986fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5987fcf5ef2aSThomas Huth tcg_temp_free(t0); 5988fcf5ef2aSThomas Huth tcg_temp_free(t1); 5989efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5990fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5991fcf5ef2aSThomas Huth } 5992efe843d8SDavid Gibson } 5993fcf5ef2aSThomas Huth 5994fcf5ef2aSThomas Huth /* sle - sle. */ 5995fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5996fcf5ef2aSThomas Huth { 5997fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5998fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5999fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6000fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6001fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6002fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6003fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6004fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6005fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6006fcf5ef2aSThomas Huth tcg_temp_free(t0); 6007fcf5ef2aSThomas Huth tcg_temp_free(t1); 6008efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6009fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6010fcf5ef2aSThomas Huth } 6011efe843d8SDavid Gibson } 6012fcf5ef2aSThomas Huth 6013fcf5ef2aSThomas Huth /* sleq - sleq. */ 6014fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6015fcf5ef2aSThomas Huth { 6016fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6017fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6018fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6019fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6020fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6021fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6022fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6023fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6024fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6025fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6026fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6027fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6028fcf5ef2aSThomas Huth tcg_temp_free(t0); 6029fcf5ef2aSThomas Huth tcg_temp_free(t1); 6030fcf5ef2aSThomas Huth tcg_temp_free(t2); 6031efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6032fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6033fcf5ef2aSThomas Huth } 6034efe843d8SDavid Gibson } 6035fcf5ef2aSThomas Huth 6036fcf5ef2aSThomas Huth /* sliq - sliq. */ 6037fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6038fcf5ef2aSThomas Huth { 6039fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6040fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6041fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6042fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6043fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6044fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6045fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6046fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6047fcf5ef2aSThomas Huth tcg_temp_free(t0); 6048fcf5ef2aSThomas Huth tcg_temp_free(t1); 6049efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6050fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6051fcf5ef2aSThomas Huth } 6052efe843d8SDavid Gibson } 6053fcf5ef2aSThomas Huth 6054fcf5ef2aSThomas Huth /* slliq - slliq. */ 6055fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6056fcf5ef2aSThomas Huth { 6057fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6058fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6059fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6060fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6061fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6062fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6063fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6064fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6065fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6066fcf5ef2aSThomas Huth tcg_temp_free(t0); 6067fcf5ef2aSThomas Huth tcg_temp_free(t1); 6068efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6069fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6070fcf5ef2aSThomas Huth } 6071efe843d8SDavid Gibson } 6072fcf5ef2aSThomas Huth 6073fcf5ef2aSThomas Huth /* sllq - sllq. */ 6074fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6075fcf5ef2aSThomas Huth { 6076fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6077fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6078fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6079fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6080fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6081fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6082fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6083fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6084fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6085fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6086fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6087fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6088fcf5ef2aSThomas Huth tcg_gen_br(l2); 6089fcf5ef2aSThomas Huth gen_set_label(l1); 6090fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6091fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6092fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6093fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6094fcf5ef2aSThomas Huth gen_set_label(l2); 6095fcf5ef2aSThomas Huth tcg_temp_free(t0); 6096fcf5ef2aSThomas Huth tcg_temp_free(t1); 6097fcf5ef2aSThomas Huth tcg_temp_free(t2); 6098efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6099fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6100fcf5ef2aSThomas Huth } 6101efe843d8SDavid Gibson } 6102fcf5ef2aSThomas Huth 6103fcf5ef2aSThomas Huth /* slq - slq. */ 6104fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6105fcf5ef2aSThomas Huth { 6106fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6107fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6108fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6109fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6110fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6111fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6112fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6113fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6114fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6115fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6116fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6117fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6118fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6119fcf5ef2aSThomas Huth gen_set_label(l1); 6120fcf5ef2aSThomas Huth tcg_temp_free(t0); 6121fcf5ef2aSThomas Huth tcg_temp_free(t1); 6122efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6123fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6124fcf5ef2aSThomas Huth } 6125efe843d8SDavid Gibson } 6126fcf5ef2aSThomas Huth 6127fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6128fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6129fcf5ef2aSThomas Huth { 6130fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6131fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6132fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6133fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6134fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6135fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6136fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6137fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6138fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6139fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6140fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6141fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6142fcf5ef2aSThomas Huth gen_set_label(l1); 6143fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6144fcf5ef2aSThomas Huth tcg_temp_free(t0); 6145fcf5ef2aSThomas Huth tcg_temp_free(t1); 6146efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6147fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6148fcf5ef2aSThomas Huth } 6149efe843d8SDavid Gibson } 6150fcf5ef2aSThomas Huth 6151fcf5ef2aSThomas Huth /* sraq - sraq. */ 6152fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6153fcf5ef2aSThomas Huth { 6154fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6155fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6156fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6157fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6158fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6159fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6160fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6161fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6162fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6163fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6164fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6165fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6166fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6167fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6168fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6169fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6170fcf5ef2aSThomas Huth gen_set_label(l1); 6171fcf5ef2aSThomas Huth tcg_temp_free(t0); 6172fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6173fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6174fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6175fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6176fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6177fcf5ef2aSThomas Huth gen_set_label(l2); 6178fcf5ef2aSThomas Huth tcg_temp_free(t1); 6179fcf5ef2aSThomas Huth tcg_temp_free(t2); 6180efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6181fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6182fcf5ef2aSThomas Huth } 6183efe843d8SDavid Gibson } 6184fcf5ef2aSThomas Huth 6185fcf5ef2aSThomas Huth /* sre - sre. */ 6186fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6187fcf5ef2aSThomas Huth { 6188fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6189fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6190fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6191fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6192fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6193fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6194fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6195fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6196fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6197fcf5ef2aSThomas Huth tcg_temp_free(t0); 6198fcf5ef2aSThomas Huth tcg_temp_free(t1); 6199efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6200fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6201fcf5ef2aSThomas Huth } 6202efe843d8SDavid Gibson } 6203fcf5ef2aSThomas Huth 6204fcf5ef2aSThomas Huth /* srea - srea. */ 6205fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6206fcf5ef2aSThomas Huth { 6207fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6208fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6209fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6210fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6211fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6212fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6213fcf5ef2aSThomas Huth tcg_temp_free(t0); 6214fcf5ef2aSThomas Huth tcg_temp_free(t1); 6215efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6216fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6217fcf5ef2aSThomas Huth } 6218efe843d8SDavid Gibson } 6219fcf5ef2aSThomas Huth 6220fcf5ef2aSThomas Huth /* sreq */ 6221fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6222fcf5ef2aSThomas Huth { 6223fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6224fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6225fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6226fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6227fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6228fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6229fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6230fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6231fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6232fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6233fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6234fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6235fcf5ef2aSThomas Huth tcg_temp_free(t0); 6236fcf5ef2aSThomas Huth tcg_temp_free(t1); 6237fcf5ef2aSThomas Huth tcg_temp_free(t2); 6238efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6239fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6240fcf5ef2aSThomas Huth } 6241efe843d8SDavid Gibson } 6242fcf5ef2aSThomas Huth 6243fcf5ef2aSThomas Huth /* sriq */ 6244fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6245fcf5ef2aSThomas Huth { 6246fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6247fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6248fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6249fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6250fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6251fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6252fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6253fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6254fcf5ef2aSThomas Huth tcg_temp_free(t0); 6255fcf5ef2aSThomas Huth tcg_temp_free(t1); 6256efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6257fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6258fcf5ef2aSThomas Huth } 6259efe843d8SDavid Gibson } 6260fcf5ef2aSThomas Huth 6261fcf5ef2aSThomas Huth /* srliq */ 6262fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6263fcf5ef2aSThomas Huth { 6264fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6265fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6266fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6267fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6268fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6269fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6270fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6271fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6272fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6273fcf5ef2aSThomas Huth tcg_temp_free(t0); 6274fcf5ef2aSThomas Huth tcg_temp_free(t1); 6275efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6276fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6277fcf5ef2aSThomas Huth } 6278efe843d8SDavid Gibson } 6279fcf5ef2aSThomas Huth 6280fcf5ef2aSThomas Huth /* srlq */ 6281fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6282fcf5ef2aSThomas Huth { 6283fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6284fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6285fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6286fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6287fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6288fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6289fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6290fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6291fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6292fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6293fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6294fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6295fcf5ef2aSThomas Huth tcg_gen_br(l2); 6296fcf5ef2aSThomas Huth gen_set_label(l1); 6297fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6298fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6299fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6300fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6301fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6302fcf5ef2aSThomas Huth gen_set_label(l2); 6303fcf5ef2aSThomas Huth tcg_temp_free(t0); 6304fcf5ef2aSThomas Huth tcg_temp_free(t1); 6305fcf5ef2aSThomas Huth tcg_temp_free(t2); 6306efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6307fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6308fcf5ef2aSThomas Huth } 6309efe843d8SDavid Gibson } 6310fcf5ef2aSThomas Huth 6311fcf5ef2aSThomas Huth /* srq */ 6312fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6313fcf5ef2aSThomas Huth { 6314fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6315fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6316fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6317fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6318fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6319fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6320fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6321fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6322fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6323fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6324fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6325fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6326fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6327fcf5ef2aSThomas Huth gen_set_label(l1); 6328fcf5ef2aSThomas Huth tcg_temp_free(t0); 6329fcf5ef2aSThomas Huth tcg_temp_free(t1); 6330efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6331fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6332fcf5ef2aSThomas Huth } 6333efe843d8SDavid Gibson } 6334fcf5ef2aSThomas Huth 6335fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6336fcf5ef2aSThomas Huth 6337fcf5ef2aSThomas Huth /* dsa */ 6338fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6339fcf5ef2aSThomas Huth { 6340fcf5ef2aSThomas Huth /* XXX: TODO */ 6341fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6342fcf5ef2aSThomas Huth } 6343fcf5ef2aSThomas Huth 6344fcf5ef2aSThomas Huth /* esa */ 6345fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6346fcf5ef2aSThomas Huth { 6347fcf5ef2aSThomas Huth /* XXX: TODO */ 6348fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6349fcf5ef2aSThomas Huth } 6350fcf5ef2aSThomas Huth 6351fcf5ef2aSThomas Huth /* mfrom */ 6352fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6353fcf5ef2aSThomas Huth { 6354fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6355fcf5ef2aSThomas Huth GEN_PRIV; 6356fcf5ef2aSThomas Huth #else 6357fcf5ef2aSThomas Huth CHK_SV; 6358fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6359fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6360fcf5ef2aSThomas Huth } 6361fcf5ef2aSThomas Huth 6362fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6363fcf5ef2aSThomas Huth 6364fcf5ef2aSThomas Huth /* tlbld */ 6365fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6366fcf5ef2aSThomas Huth { 6367fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6368fcf5ef2aSThomas Huth GEN_PRIV; 6369fcf5ef2aSThomas Huth #else 6370fcf5ef2aSThomas Huth CHK_SV; 6371fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6372fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6373fcf5ef2aSThomas Huth } 6374fcf5ef2aSThomas Huth 6375fcf5ef2aSThomas Huth /* tlbli */ 6376fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6377fcf5ef2aSThomas Huth { 6378fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6379fcf5ef2aSThomas Huth GEN_PRIV; 6380fcf5ef2aSThomas Huth #else 6381fcf5ef2aSThomas Huth CHK_SV; 6382fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6383fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6384fcf5ef2aSThomas Huth } 6385fcf5ef2aSThomas Huth 6386fcf5ef2aSThomas Huth /* 74xx TLB management */ 6387fcf5ef2aSThomas Huth 6388fcf5ef2aSThomas Huth /* tlbld */ 6389fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6390fcf5ef2aSThomas Huth { 6391fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6392fcf5ef2aSThomas Huth GEN_PRIV; 6393fcf5ef2aSThomas Huth #else 6394fcf5ef2aSThomas Huth CHK_SV; 6395fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6396fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6397fcf5ef2aSThomas Huth } 6398fcf5ef2aSThomas Huth 6399fcf5ef2aSThomas Huth /* tlbli */ 6400fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6401fcf5ef2aSThomas Huth { 6402fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6403fcf5ef2aSThomas Huth GEN_PRIV; 6404fcf5ef2aSThomas Huth #else 6405fcf5ef2aSThomas Huth CHK_SV; 6406fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6407fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6408fcf5ef2aSThomas Huth } 6409fcf5ef2aSThomas Huth 6410fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6411fcf5ef2aSThomas Huth 6412fcf5ef2aSThomas Huth /* clf */ 6413fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6414fcf5ef2aSThomas Huth { 6415fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6416fcf5ef2aSThomas Huth } 6417fcf5ef2aSThomas Huth 6418fcf5ef2aSThomas Huth /* cli */ 6419fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6420fcf5ef2aSThomas Huth { 6421fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6422fcf5ef2aSThomas Huth GEN_PRIV; 6423fcf5ef2aSThomas Huth #else 6424fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6425fcf5ef2aSThomas Huth CHK_SV; 6426fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6427fcf5ef2aSThomas Huth } 6428fcf5ef2aSThomas Huth 6429fcf5ef2aSThomas Huth /* dclst */ 6430fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6431fcf5ef2aSThomas Huth { 6432fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6433fcf5ef2aSThomas Huth } 6434fcf5ef2aSThomas Huth 6435fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6436fcf5ef2aSThomas Huth { 6437fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6438fcf5ef2aSThomas Huth GEN_PRIV; 6439fcf5ef2aSThomas Huth #else 6440fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6441fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6442fcf5ef2aSThomas Huth TCGv t0; 6443fcf5ef2aSThomas Huth 6444fcf5ef2aSThomas Huth CHK_SV; 6445fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6446fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6447e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6448fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6449fcf5ef2aSThomas Huth tcg_temp_free(t0); 6450efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6451fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6452efe843d8SDavid Gibson } 6453fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6454fcf5ef2aSThomas Huth } 6455fcf5ef2aSThomas Huth 6456fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6457fcf5ef2aSThomas Huth { 6458fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6459fcf5ef2aSThomas Huth GEN_PRIV; 6460fcf5ef2aSThomas Huth #else 6461fcf5ef2aSThomas Huth TCGv t0; 6462fcf5ef2aSThomas Huth 6463fcf5ef2aSThomas Huth CHK_SV; 6464fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6465fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6466fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6467fcf5ef2aSThomas Huth tcg_temp_free(t0); 6468fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6469fcf5ef2aSThomas Huth } 6470fcf5ef2aSThomas Huth 6471fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6472fcf5ef2aSThomas Huth { 6473fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6474fcf5ef2aSThomas Huth GEN_PRIV; 6475fcf5ef2aSThomas Huth #else 6476fcf5ef2aSThomas Huth CHK_SV; 6477fcf5ef2aSThomas Huth 6478fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 647959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6480fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6481fcf5ef2aSThomas Huth } 6482fcf5ef2aSThomas Huth 6483fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6484fcf5ef2aSThomas Huth 6485fcf5ef2aSThomas Huth /* BookE specific instructions */ 6486fcf5ef2aSThomas Huth 6487fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6488fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6489fcf5ef2aSThomas Huth { 6490fcf5ef2aSThomas Huth /* XXX: TODO */ 6491fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6492fcf5ef2aSThomas Huth } 6493fcf5ef2aSThomas Huth 6494fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6495fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6496fcf5ef2aSThomas Huth { 6497fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6498fcf5ef2aSThomas Huth GEN_PRIV; 6499fcf5ef2aSThomas Huth #else 6500fcf5ef2aSThomas Huth TCGv t0; 6501fcf5ef2aSThomas Huth 6502fcf5ef2aSThomas Huth CHK_SV; 6503fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6504fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6505fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6506fcf5ef2aSThomas Huth tcg_temp_free(t0); 6507fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6508fcf5ef2aSThomas Huth } 6509fcf5ef2aSThomas Huth 6510fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6511fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6512fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6513fcf5ef2aSThomas Huth { 6514fcf5ef2aSThomas Huth TCGv t0, t1; 6515fcf5ef2aSThomas Huth 6516fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6517fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6518fcf5ef2aSThomas Huth 6519fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6520fcf5ef2aSThomas Huth case 0x05: 6521fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6522fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6523fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6524fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6525fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6526fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6527fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6528fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6529fcf5ef2aSThomas Huth break; 6530fcf5ef2aSThomas Huth case 0x04: 6531fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6532fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6533fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6534fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6535fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6536fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6537fcf5ef2aSThomas Huth break; 6538fcf5ef2aSThomas Huth case 0x01: 6539fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6540fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6541fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6542fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6543fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6544fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6545fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6546fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6547fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6548fcf5ef2aSThomas Huth break; 6549fcf5ef2aSThomas Huth case 0x00: 6550fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6551fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6552fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6553fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6554fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6555fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6556fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6557fcf5ef2aSThomas Huth break; 6558fcf5ef2aSThomas Huth case 0x0D: 6559fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6560fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6561fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6562fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6563fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6564fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6565fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6566fcf5ef2aSThomas Huth break; 6567fcf5ef2aSThomas Huth case 0x0C: 6568fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6569fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6570fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6571fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6572fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6573fcf5ef2aSThomas Huth break; 6574fcf5ef2aSThomas Huth } 6575fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6576fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6577fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6578fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6579fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6580fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6581fcf5ef2aSThomas Huth } else { 6582fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6583fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6584fcf5ef2aSThomas Huth } 6585fcf5ef2aSThomas Huth 6586fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6587fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6588fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6589fcf5ef2aSThomas Huth 6590fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6591fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6592fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6593fcf5ef2aSThomas Huth } 6594fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6595fcf5ef2aSThomas Huth /* Signed */ 6596fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6597fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6598fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6599fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6600fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6601fcf5ef2aSThomas Huth /* Saturate */ 6602fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6603fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6604fcf5ef2aSThomas Huth } 6605fcf5ef2aSThomas Huth } else { 6606fcf5ef2aSThomas Huth /* Unsigned */ 6607fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6608fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6609fcf5ef2aSThomas Huth /* Saturate */ 6610fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6611fcf5ef2aSThomas Huth } 6612fcf5ef2aSThomas Huth } 6613fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6614fcf5ef2aSThomas Huth /* Check overflow */ 6615fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6616fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6617fcf5ef2aSThomas Huth } 6618fcf5ef2aSThomas Huth gen_set_label(l1); 6619fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6620fcf5ef2aSThomas Huth } 6621fcf5ef2aSThomas Huth } else { 6622fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6623fcf5ef2aSThomas Huth } 6624fcf5ef2aSThomas Huth tcg_temp_free(t0); 6625fcf5ef2aSThomas Huth tcg_temp_free(t1); 6626fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6627fcf5ef2aSThomas Huth /* Update Rc0 */ 6628fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6629fcf5ef2aSThomas Huth } 6630fcf5ef2aSThomas Huth } 6631fcf5ef2aSThomas Huth 6632fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6633fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6634fcf5ef2aSThomas Huth { \ 6635fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6636fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6637fcf5ef2aSThomas Huth } 6638fcf5ef2aSThomas Huth 6639fcf5ef2aSThomas Huth /* macchw - macchw. */ 6640fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6641fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6642fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6643fcf5ef2aSThomas Huth /* macchws - macchws. */ 6644fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6645fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6646fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6647fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6648fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6649fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6650fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6651fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6652fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6653fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6654fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6655fcf5ef2aSThomas Huth /* machhw - machhw. */ 6656fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6657fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6658fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6659fcf5ef2aSThomas Huth /* machhws - machhws. */ 6660fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6661fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6662fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6663fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6664fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6665fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6666fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6667fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6668fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6669fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6670fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6671fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6672fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6673fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6674fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6675fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6676fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6677fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6678fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6679fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6680fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6681fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6682fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6683fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6684fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6685fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6686fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6687fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6688fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6689fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6690fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6691fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6692fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6693fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6694fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6695fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6696fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6697fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6698fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6699fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6700fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6701fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6702fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6703fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6704fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6705fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6706fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6707fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6708fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6709fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6710fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6711fcf5ef2aSThomas Huth 6712fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6713fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6714fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6715fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6716fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6717fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6718fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6719fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6720fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6721fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6722fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6723fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6724fcf5ef2aSThomas Huth 6725fcf5ef2aSThomas Huth /* mfdcr */ 6726fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6727fcf5ef2aSThomas Huth { 6728fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6729fcf5ef2aSThomas Huth GEN_PRIV; 6730fcf5ef2aSThomas Huth #else 6731fcf5ef2aSThomas Huth TCGv dcrn; 6732fcf5ef2aSThomas Huth 6733fcf5ef2aSThomas Huth CHK_SV; 6734fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6735fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6736fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6737fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6738fcf5ef2aSThomas Huth } 6739fcf5ef2aSThomas Huth 6740fcf5ef2aSThomas Huth /* mtdcr */ 6741fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6742fcf5ef2aSThomas Huth { 6743fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6744fcf5ef2aSThomas Huth GEN_PRIV; 6745fcf5ef2aSThomas Huth #else 6746fcf5ef2aSThomas Huth TCGv dcrn; 6747fcf5ef2aSThomas Huth 6748fcf5ef2aSThomas Huth CHK_SV; 6749fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6750fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6751fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6752fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6753fcf5ef2aSThomas Huth } 6754fcf5ef2aSThomas Huth 6755fcf5ef2aSThomas Huth /* mfdcrx */ 6756fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6757fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6758fcf5ef2aSThomas Huth { 6759fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6760fcf5ef2aSThomas Huth GEN_PRIV; 6761fcf5ef2aSThomas Huth #else 6762fcf5ef2aSThomas Huth CHK_SV; 6763fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6764fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6765fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6766fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6767fcf5ef2aSThomas Huth } 6768fcf5ef2aSThomas Huth 6769fcf5ef2aSThomas Huth /* mtdcrx */ 6770fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6771fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6772fcf5ef2aSThomas Huth { 6773fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6774fcf5ef2aSThomas Huth GEN_PRIV; 6775fcf5ef2aSThomas Huth #else 6776fcf5ef2aSThomas Huth CHK_SV; 6777fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6778fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6779fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6780fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6781fcf5ef2aSThomas Huth } 6782fcf5ef2aSThomas Huth 6783fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6784fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6785fcf5ef2aSThomas Huth { 6786fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6787fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6788fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6789fcf5ef2aSThomas Huth } 6790fcf5ef2aSThomas Huth 6791fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6792fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6793fcf5ef2aSThomas Huth { 6794fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6795fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6796fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6797fcf5ef2aSThomas Huth } 6798fcf5ef2aSThomas Huth 6799fcf5ef2aSThomas Huth /* dccci */ 6800fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6801fcf5ef2aSThomas Huth { 6802fcf5ef2aSThomas Huth CHK_SV; 6803fcf5ef2aSThomas Huth /* interpreted as no-op */ 6804fcf5ef2aSThomas Huth } 6805fcf5ef2aSThomas Huth 6806fcf5ef2aSThomas Huth /* dcread */ 6807fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6808fcf5ef2aSThomas Huth { 6809fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6810fcf5ef2aSThomas Huth GEN_PRIV; 6811fcf5ef2aSThomas Huth #else 6812fcf5ef2aSThomas Huth TCGv EA, val; 6813fcf5ef2aSThomas Huth 6814fcf5ef2aSThomas Huth CHK_SV; 6815fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6816fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6817fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6818fcf5ef2aSThomas Huth val = tcg_temp_new(); 6819fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6820fcf5ef2aSThomas Huth tcg_temp_free(val); 6821fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6822fcf5ef2aSThomas Huth tcg_temp_free(EA); 6823fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6824fcf5ef2aSThomas Huth } 6825fcf5ef2aSThomas Huth 6826fcf5ef2aSThomas Huth /* icbt */ 6827fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6828fcf5ef2aSThomas Huth { 6829efe843d8SDavid Gibson /* 6830efe843d8SDavid Gibson * interpreted as no-op 6831efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6832efe843d8SDavid Gibson * does not generate any exception 6833fcf5ef2aSThomas Huth */ 6834fcf5ef2aSThomas Huth } 6835fcf5ef2aSThomas Huth 6836fcf5ef2aSThomas Huth /* iccci */ 6837fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6838fcf5ef2aSThomas Huth { 6839fcf5ef2aSThomas Huth CHK_SV; 6840fcf5ef2aSThomas Huth /* interpreted as no-op */ 6841fcf5ef2aSThomas Huth } 6842fcf5ef2aSThomas Huth 6843fcf5ef2aSThomas Huth /* icread */ 6844fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6845fcf5ef2aSThomas Huth { 6846fcf5ef2aSThomas Huth CHK_SV; 6847fcf5ef2aSThomas Huth /* interpreted as no-op */ 6848fcf5ef2aSThomas Huth } 6849fcf5ef2aSThomas Huth 6850fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6851fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6852fcf5ef2aSThomas Huth { 6853fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6854fcf5ef2aSThomas Huth GEN_PRIV; 6855fcf5ef2aSThomas Huth #else 6856fcf5ef2aSThomas Huth CHK_SV; 6857fcf5ef2aSThomas Huth /* Restore CPU state */ 6858fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 685959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6860fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6861fcf5ef2aSThomas Huth } 6862fcf5ef2aSThomas Huth 6863fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6864fcf5ef2aSThomas Huth { 6865fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6866fcf5ef2aSThomas Huth GEN_PRIV; 6867fcf5ef2aSThomas Huth #else 6868fcf5ef2aSThomas Huth CHK_SV; 6869fcf5ef2aSThomas Huth /* Restore CPU state */ 6870fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 687159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6872fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6873fcf5ef2aSThomas Huth } 6874fcf5ef2aSThomas Huth 6875fcf5ef2aSThomas Huth /* BookE specific */ 6876fcf5ef2aSThomas Huth 6877fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6878fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6879fcf5ef2aSThomas Huth { 6880fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6881fcf5ef2aSThomas Huth GEN_PRIV; 6882fcf5ef2aSThomas Huth #else 6883fcf5ef2aSThomas Huth CHK_SV; 6884fcf5ef2aSThomas Huth /* Restore CPU state */ 6885fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 688659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6887fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6888fcf5ef2aSThomas Huth } 6889fcf5ef2aSThomas Huth 6890fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6891fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6892fcf5ef2aSThomas Huth { 6893fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6894fcf5ef2aSThomas Huth GEN_PRIV; 6895fcf5ef2aSThomas Huth #else 6896fcf5ef2aSThomas Huth CHK_SV; 6897fcf5ef2aSThomas Huth /* Restore CPU state */ 6898fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 689959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6900fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6901fcf5ef2aSThomas Huth } 6902fcf5ef2aSThomas Huth 6903fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6904fcf5ef2aSThomas Huth 6905fcf5ef2aSThomas Huth /* tlbre */ 6906fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6907fcf5ef2aSThomas Huth { 6908fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6909fcf5ef2aSThomas Huth GEN_PRIV; 6910fcf5ef2aSThomas Huth #else 6911fcf5ef2aSThomas Huth CHK_SV; 6912fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6913fcf5ef2aSThomas Huth case 0: 6914fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6915fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6916fcf5ef2aSThomas Huth break; 6917fcf5ef2aSThomas Huth case 1: 6918fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6919fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6920fcf5ef2aSThomas Huth break; 6921fcf5ef2aSThomas Huth default: 6922fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6923fcf5ef2aSThomas Huth break; 6924fcf5ef2aSThomas Huth } 6925fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6926fcf5ef2aSThomas Huth } 6927fcf5ef2aSThomas Huth 6928fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6929fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6930fcf5ef2aSThomas Huth { 6931fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6932fcf5ef2aSThomas Huth GEN_PRIV; 6933fcf5ef2aSThomas Huth #else 6934fcf5ef2aSThomas Huth TCGv t0; 6935fcf5ef2aSThomas Huth 6936fcf5ef2aSThomas Huth CHK_SV; 6937fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6938fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6939fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6940fcf5ef2aSThomas Huth tcg_temp_free(t0); 6941fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6942fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6943fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6944fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6945fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6946fcf5ef2aSThomas Huth gen_set_label(l1); 6947fcf5ef2aSThomas Huth } 6948fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6949fcf5ef2aSThomas Huth } 6950fcf5ef2aSThomas Huth 6951fcf5ef2aSThomas Huth /* tlbwe */ 6952fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6953fcf5ef2aSThomas Huth { 6954fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6955fcf5ef2aSThomas Huth GEN_PRIV; 6956fcf5ef2aSThomas Huth #else 6957fcf5ef2aSThomas Huth CHK_SV; 6958fcf5ef2aSThomas Huth 6959fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6960fcf5ef2aSThomas Huth case 0: 6961fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6962fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6963fcf5ef2aSThomas Huth break; 6964fcf5ef2aSThomas Huth case 1: 6965fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6966fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6967fcf5ef2aSThomas Huth break; 6968fcf5ef2aSThomas Huth default: 6969fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6970fcf5ef2aSThomas Huth break; 6971fcf5ef2aSThomas Huth } 6972fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6973fcf5ef2aSThomas Huth } 6974fcf5ef2aSThomas Huth 6975fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6976fcf5ef2aSThomas Huth 6977fcf5ef2aSThomas Huth /* tlbre */ 6978fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6979fcf5ef2aSThomas Huth { 6980fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6981fcf5ef2aSThomas Huth GEN_PRIV; 6982fcf5ef2aSThomas Huth #else 6983fcf5ef2aSThomas Huth CHK_SV; 6984fcf5ef2aSThomas Huth 6985fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6986fcf5ef2aSThomas Huth case 0: 6987fcf5ef2aSThomas Huth case 1: 6988fcf5ef2aSThomas Huth case 2: 6989fcf5ef2aSThomas Huth { 6990fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6991fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6992fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6993fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6994fcf5ef2aSThomas Huth } 6995fcf5ef2aSThomas Huth break; 6996fcf5ef2aSThomas Huth default: 6997fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6998fcf5ef2aSThomas Huth break; 6999fcf5ef2aSThomas Huth } 7000fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7001fcf5ef2aSThomas Huth } 7002fcf5ef2aSThomas Huth 7003fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7004fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7005fcf5ef2aSThomas Huth { 7006fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7007fcf5ef2aSThomas Huth GEN_PRIV; 7008fcf5ef2aSThomas Huth #else 7009fcf5ef2aSThomas Huth TCGv t0; 7010fcf5ef2aSThomas Huth 7011fcf5ef2aSThomas Huth CHK_SV; 7012fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7013fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7014fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7015fcf5ef2aSThomas Huth tcg_temp_free(t0); 7016fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7017fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7018fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7019fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7020fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7021fcf5ef2aSThomas Huth gen_set_label(l1); 7022fcf5ef2aSThomas Huth } 7023fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7024fcf5ef2aSThomas Huth } 7025fcf5ef2aSThomas Huth 7026fcf5ef2aSThomas Huth /* tlbwe */ 7027fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7028fcf5ef2aSThomas Huth { 7029fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7030fcf5ef2aSThomas Huth GEN_PRIV; 7031fcf5ef2aSThomas Huth #else 7032fcf5ef2aSThomas Huth CHK_SV; 7033fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7034fcf5ef2aSThomas Huth case 0: 7035fcf5ef2aSThomas Huth case 1: 7036fcf5ef2aSThomas Huth case 2: 7037fcf5ef2aSThomas Huth { 7038fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7039fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7040fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7041fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7042fcf5ef2aSThomas Huth } 7043fcf5ef2aSThomas Huth break; 7044fcf5ef2aSThomas Huth default: 7045fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7046fcf5ef2aSThomas Huth break; 7047fcf5ef2aSThomas Huth } 7048fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7049fcf5ef2aSThomas Huth } 7050fcf5ef2aSThomas Huth 7051fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7052fcf5ef2aSThomas Huth 7053fcf5ef2aSThomas Huth /* tlbre */ 7054fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7055fcf5ef2aSThomas Huth { 7056fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7057fcf5ef2aSThomas Huth GEN_PRIV; 7058fcf5ef2aSThomas Huth #else 7059fcf5ef2aSThomas Huth CHK_SV; 7060fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7061fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7062fcf5ef2aSThomas Huth } 7063fcf5ef2aSThomas Huth 7064fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7065fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7066fcf5ef2aSThomas Huth { 7067fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7068fcf5ef2aSThomas Huth GEN_PRIV; 7069fcf5ef2aSThomas Huth #else 7070fcf5ef2aSThomas Huth TCGv t0; 7071fcf5ef2aSThomas Huth 7072fcf5ef2aSThomas Huth CHK_SV; 7073fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7074fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7075fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7076fcf5ef2aSThomas Huth } else { 7077fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7078fcf5ef2aSThomas Huth } 7079fcf5ef2aSThomas Huth 7080fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7081fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7082fcf5ef2aSThomas Huth tcg_temp_free(t0); 7083fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7084fcf5ef2aSThomas Huth } 7085fcf5ef2aSThomas Huth 7086fcf5ef2aSThomas Huth /* tlbwe */ 7087fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7088fcf5ef2aSThomas Huth { 7089fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7090fcf5ef2aSThomas Huth GEN_PRIV; 7091fcf5ef2aSThomas Huth #else 7092fcf5ef2aSThomas Huth CHK_SV; 7093fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7094fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7095fcf5ef2aSThomas Huth } 7096fcf5ef2aSThomas Huth 7097fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7098fcf5ef2aSThomas Huth { 7099fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7100fcf5ef2aSThomas Huth GEN_PRIV; 7101fcf5ef2aSThomas Huth #else 7102fcf5ef2aSThomas Huth TCGv t0; 7103fcf5ef2aSThomas Huth 7104fcf5ef2aSThomas Huth CHK_SV; 7105fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7106fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7107fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7108fcf5ef2aSThomas Huth tcg_temp_free(t0); 7109fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7110fcf5ef2aSThomas Huth } 7111fcf5ef2aSThomas Huth 7112fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7113fcf5ef2aSThomas Huth { 7114fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7115fcf5ef2aSThomas Huth GEN_PRIV; 7116fcf5ef2aSThomas Huth #else 7117fcf5ef2aSThomas Huth TCGv t0; 7118fcf5ef2aSThomas Huth 7119fcf5ef2aSThomas Huth CHK_SV; 7120fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7121fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7122fcf5ef2aSThomas Huth 7123fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7124fcf5ef2aSThomas Huth case 0: 7125fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7126fcf5ef2aSThomas Huth break; 7127fcf5ef2aSThomas Huth case 1: 7128fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7129fcf5ef2aSThomas Huth break; 7130fcf5ef2aSThomas Huth case 3: 7131fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7132fcf5ef2aSThomas Huth break; 7133fcf5ef2aSThomas Huth default: 7134fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7135fcf5ef2aSThomas Huth break; 7136fcf5ef2aSThomas Huth } 7137fcf5ef2aSThomas Huth 7138fcf5ef2aSThomas Huth tcg_temp_free(t0); 7139fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7140fcf5ef2aSThomas Huth } 7141fcf5ef2aSThomas Huth 7142fcf5ef2aSThomas Huth 7143fcf5ef2aSThomas Huth /* wrtee */ 7144fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7145fcf5ef2aSThomas Huth { 7146fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7147fcf5ef2aSThomas Huth GEN_PRIV; 7148fcf5ef2aSThomas Huth #else 7149fcf5ef2aSThomas Huth TCGv t0; 7150fcf5ef2aSThomas Huth 7151fcf5ef2aSThomas Huth CHK_SV; 7152fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7153fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7154fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7155fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7156fcf5ef2aSThomas Huth tcg_temp_free(t0); 7157efe843d8SDavid Gibson /* 7158efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7159efe843d8SDavid Gibson * just set msr_ee to 1 7160fcf5ef2aSThomas Huth */ 7161d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7162fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7163fcf5ef2aSThomas Huth } 7164fcf5ef2aSThomas Huth 7165fcf5ef2aSThomas Huth /* wrteei */ 7166fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7167fcf5ef2aSThomas Huth { 7168fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7169fcf5ef2aSThomas Huth GEN_PRIV; 7170fcf5ef2aSThomas Huth #else 7171fcf5ef2aSThomas Huth CHK_SV; 7172fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7173fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7174fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7175d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7176fcf5ef2aSThomas Huth } else { 7177fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7178fcf5ef2aSThomas Huth } 7179fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7180fcf5ef2aSThomas Huth } 7181fcf5ef2aSThomas Huth 7182fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7183fcf5ef2aSThomas Huth 7184fcf5ef2aSThomas Huth /* dlmzb */ 7185fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7186fcf5ef2aSThomas Huth { 7187fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7188fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7189fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7190fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7191fcf5ef2aSThomas Huth } 7192fcf5ef2aSThomas Huth 7193fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7194fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7195fcf5ef2aSThomas Huth { 7196fcf5ef2aSThomas Huth /* interpreted as no-op */ 7197fcf5ef2aSThomas Huth } 7198fcf5ef2aSThomas Huth 7199fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7200fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7201fcf5ef2aSThomas Huth { 720227a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 720327a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 720427a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 720527a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 720627a3ea7eSBALATON Zoltan } 720727a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7208fcf5ef2aSThomas Huth } 7209fcf5ef2aSThomas Huth 7210fcf5ef2aSThomas Huth /* icbt */ 7211fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7212fcf5ef2aSThomas Huth { 7213efe843d8SDavid Gibson /* 7214efe843d8SDavid Gibson * interpreted as no-op 7215efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7216efe843d8SDavid Gibson * does not generate any exception 7217fcf5ef2aSThomas Huth */ 7218fcf5ef2aSThomas Huth } 7219fcf5ef2aSThomas Huth 7220fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7221fcf5ef2aSThomas Huth 7222fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7223fcf5ef2aSThomas Huth { 7224fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7225fcf5ef2aSThomas Huth GEN_PRIV; 7226fcf5ef2aSThomas Huth #else 7227ebca5e6dSCédric Le Goater CHK_HV; 7228d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 72297af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72307af1e7b0SCédric Le Goater } else { 7231fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72327af1e7b0SCédric Le Goater } 7233fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7234fcf5ef2aSThomas Huth } 7235fcf5ef2aSThomas Huth 7236fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7237fcf5ef2aSThomas Huth { 7238fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7239fcf5ef2aSThomas Huth GEN_PRIV; 7240fcf5ef2aSThomas Huth #else 7241ebca5e6dSCédric Le Goater CHK_HV; 7242d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 72437af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 72447af1e7b0SCédric Le Goater } else { 7245fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 72467af1e7b0SCédric Le Goater } 7247fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7248fcf5ef2aSThomas Huth } 7249fcf5ef2aSThomas Huth 72505ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 72515ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 72525ba7ba1dSCédric Le Goater { 72535ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 72545ba7ba1dSCédric Le Goater GEN_PRIV; 72555ba7ba1dSCédric Le Goater #else 72565ba7ba1dSCédric Le Goater CHK_SV; 72575ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72585ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72595ba7ba1dSCédric Le Goater } 72605ba7ba1dSCédric Le Goater 72615ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 72625ba7ba1dSCédric Le Goater { 72635ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 72645ba7ba1dSCédric Le Goater GEN_PRIV; 72655ba7ba1dSCédric Le Goater #else 72665ba7ba1dSCédric Le Goater CHK_SV; 72675ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 72685ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72695ba7ba1dSCédric Le Goater } 72705ba7ba1dSCédric Le Goater #endif 72715ba7ba1dSCédric Le Goater 72727af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 72737af1e7b0SCédric Le Goater { 72747af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 72757af1e7b0SCédric Le Goater GEN_PRIV; 72767af1e7b0SCédric Le Goater #else 72777af1e7b0SCédric Le Goater CHK_HV; 72787af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72797af1e7b0SCédric Le Goater /* interpreted as no-op */ 72807af1e7b0SCédric Le Goater } 7281fcf5ef2aSThomas Huth 7282fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7283fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7284fcf5ef2aSThomas Huth { 7285fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7286fcf5ef2aSThomas Huth 7287fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7288fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7289fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7290fcf5ef2aSThomas Huth } 7291fcf5ef2aSThomas Huth 7292fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7293fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7294fcf5ef2aSThomas Huth { 7295fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7296fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7297fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7298fcf5ef2aSThomas Huth 7299fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7300fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7301fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7302fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7303fcf5ef2aSThomas Huth } else { 7304fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7305fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7306fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7307fcf5ef2aSThomas Huth } 7308fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7309fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7310fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7311fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7312fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7313fcf5ef2aSThomas Huth } 7314fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7315fcf5ef2aSThomas Huth 7316fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7317fcf5ef2aSThomas Huth { 7318fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7319fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7320fcf5ef2aSThomas Huth return; 7321fcf5ef2aSThomas Huth } 7322fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7323fcf5ef2aSThomas Huth } 7324fcf5ef2aSThomas Huth 7325fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7326fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7327fcf5ef2aSThomas Huth { \ 7328fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7329fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7330fcf5ef2aSThomas Huth return; \ 7331fcf5ef2aSThomas Huth } \ 7332efe843d8SDavid Gibson /* \ 7333efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7334fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7335fcf5ef2aSThomas Huth * \ 7336fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7337fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7338fcf5ef2aSThomas Huth */ \ 7339fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7340fcf5ef2aSThomas Huth } 7341fcf5ef2aSThomas Huth 7342fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7343fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7344fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7345fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7346fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7347fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7348fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7349efe843d8SDavid Gibson 7350b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7351b8b4576eSSuraj Jitindar Singh { 7352efe843d8SDavid Gibson /* Do Nothing */ 7353b8b4576eSSuraj Jitindar Singh } 7354fcf5ef2aSThomas Huth 735580b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 735680b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 735780b8c1eeSNikunj A Dadhania { \ 7358efe843d8SDavid Gibson /* \ 7359efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7360efe843d8SDavid Gibson * implementation of the copy paste facility \ 736180b8c1eeSNikunj A Dadhania */ \ 736280b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 736380b8c1eeSNikunj A Dadhania } 736480b8c1eeSNikunj A Dadhania 736580b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 736680b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 736780b8c1eeSNikunj A Dadhania 7368fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7369fcf5ef2aSThomas Huth { 7370fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7371fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7372fcf5ef2aSThomas Huth return; 7373fcf5ef2aSThomas Huth } 7374efe843d8SDavid Gibson /* 7375efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7376efe843d8SDavid Gibson * simple: 7377fcf5ef2aSThomas Huth * 7378fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7379fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7380fcf5ef2aSThomas Huth */ 7381fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7382fcf5ef2aSThomas Huth } 7383fcf5ef2aSThomas Huth 7384fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7385fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7386fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7387fcf5ef2aSThomas Huth { \ 7388fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7389fcf5ef2aSThomas Huth } 7390fcf5ef2aSThomas Huth 7391fcf5ef2aSThomas Huth #else 7392fcf5ef2aSThomas Huth 7393fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7394fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7395fcf5ef2aSThomas Huth { \ 7396fcf5ef2aSThomas Huth CHK_SV; \ 7397fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7398fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7399fcf5ef2aSThomas Huth return; \ 7400fcf5ef2aSThomas Huth } \ 7401efe843d8SDavid Gibson /* \ 7402efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7403fcf5ef2aSThomas Huth * simple: \ 7404fcf5ef2aSThomas Huth * \ 7405fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7406fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7407fcf5ef2aSThomas Huth */ \ 7408fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7409fcf5ef2aSThomas Huth } 7410fcf5ef2aSThomas Huth 7411fcf5ef2aSThomas Huth #endif 7412fcf5ef2aSThomas Huth 7413fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7414fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7415fcf5ef2aSThomas Huth 74161a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 74171a404c91SMark Cave-Ayland { 7418e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 74191a404c91SMark Cave-Ayland } 74201a404c91SMark Cave-Ayland 74211a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 74221a404c91SMark Cave-Ayland { 7423e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 74241a404c91SMark Cave-Ayland } 74251a404c91SMark Cave-Ayland 7426c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7427c4a18dbfSMark Cave-Ayland { 742837da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7429c4a18dbfSMark Cave-Ayland } 7430c4a18dbfSMark Cave-Ayland 7431c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7432c4a18dbfSMark Cave-Ayland { 743337da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7434c4a18dbfSMark Cave-Ayland } 7435c4a18dbfSMark Cave-Ayland 7436c9826ae9SRichard Henderson /* 7437f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 7438f2aabda8SRichard Henderson */ 7439f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 7440f2aabda8SRichard Henderson { 7441f2aabda8SRichard Henderson return x * 4; 7442f2aabda8SRichard Henderson } 7443f2aabda8SRichard Henderson 7444f2aabda8SRichard Henderson /* 7445c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 7446c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 7447c9826ae9SRichard Henderson * proper variable. 7448c9826ae9SRichard Henderson */ 7449c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7450c9826ae9SRichard Henderson do { \ 7451c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7452c9826ae9SRichard Henderson return false; \ 7453c9826ae9SRichard Henderson } \ 7454c9826ae9SRichard Henderson } while (0) 7455c9826ae9SRichard Henderson 7456c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7457c9826ae9SRichard Henderson do { \ 7458c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7459c9826ae9SRichard Henderson return false; \ 7460c9826ae9SRichard Henderson } \ 7461c9826ae9SRichard Henderson } while (0) 7462c9826ae9SRichard Henderson 7463c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7464c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 7465c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 7466c9826ae9SRichard Henderson #else 7467c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7468c9826ae9SRichard Henderson #endif 7469c9826ae9SRichard Henderson 7470f2aabda8SRichard Henderson /* 7471f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 7472f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 7473f2aabda8SRichard Henderson */ 7474f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 7475f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7476f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 7477f2aabda8SRichard Henderson 7478f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 7479f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7480f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 7481f2aabda8SRichard Henderson 7482f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 7483f2aabda8SRichard Henderson 7484f2aabda8SRichard Henderson 748599082815SRichard Henderson #include "decode-insn32.c.inc" 748699082815SRichard Henderson #include "decode-insn64.c.inc" 748799082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 748899082815SRichard Henderson 7489139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7490fcf5ef2aSThomas Huth 7491139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7492fcf5ef2aSThomas Huth 7493139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7494a5f56954SMatheus Ferst #include "translate/vector-impl.c.inc" 7495fcf5ef2aSThomas Huth 7496139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7497fcf5ef2aSThomas Huth 7498139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7499fcf5ef2aSThomas Huth 75005cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 75015cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 75025cb091a4SNikunj A Dadhania { 75035cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 75045cb091a4SNikunj A Dadhania case 0: /* lfdp */ 75055cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 75065cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 75075cb091a4SNikunj A Dadhania } 75085cb091a4SNikunj A Dadhania break; 75095cb091a4SNikunj A Dadhania case 2: /* lxsd */ 75105cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 75115cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 75125cb091a4SNikunj A Dadhania } 75135cb091a4SNikunj A Dadhania break; 75145cb091a4SNikunj A Dadhania case 3: /* lxssp */ 75155cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 75165cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 75175cb091a4SNikunj A Dadhania } 75185cb091a4SNikunj A Dadhania break; 75195cb091a4SNikunj A Dadhania } 75205cb091a4SNikunj A Dadhania return gen_invalid(ctx); 75215cb091a4SNikunj A Dadhania } 75225cb091a4SNikunj A Dadhania 7523d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7524e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7525e3001664SNikunj A Dadhania { 7526e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7527e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7528e3001664SNikunj A Dadhania case 1: /* lxv */ 7529d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7530d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7531d59ba583SNikunj A Dadhania } 7532e3001664SNikunj A Dadhania break; 7533e3001664SNikunj A Dadhania case 5: /* stxv */ 7534d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7535d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7536d59ba583SNikunj A Dadhania } 7537e3001664SNikunj A Dadhania break; 7538e3001664SNikunj A Dadhania } 7539e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7540e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7541e3001664SNikunj A Dadhania case 0: /* stfdp */ 7542e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7543e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7544e3001664SNikunj A Dadhania } 7545e3001664SNikunj A Dadhania break; 7546e3001664SNikunj A Dadhania case 2: /* stxsd */ 7547e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7548e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7549e3001664SNikunj A Dadhania } 7550e3001664SNikunj A Dadhania break; 7551e3001664SNikunj A Dadhania case 3: /* stxssp */ 7552e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7553e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7554e3001664SNikunj A Dadhania } 7555e3001664SNikunj A Dadhania break; 7556e3001664SNikunj A Dadhania } 7557e3001664SNikunj A Dadhania } 7558e3001664SNikunj A Dadhania return gen_invalid(ctx); 7559e3001664SNikunj A Dadhania } 7560e3001664SNikunj A Dadhania 75619d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75629d69cfa2SLijun Pan /* brd */ 75639d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 75649d69cfa2SLijun Pan { 75659d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75669d69cfa2SLijun Pan } 75679d69cfa2SLijun Pan 75689d69cfa2SLijun Pan /* brw */ 75699d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 75709d69cfa2SLijun Pan { 75719d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75729d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 75739d69cfa2SLijun Pan 75749d69cfa2SLijun Pan } 75759d69cfa2SLijun Pan 75769d69cfa2SLijun Pan /* brh */ 75779d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 75789d69cfa2SLijun Pan { 7579491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 75809d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 75819d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 75829d69cfa2SLijun Pan 75839d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 7584491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 7585491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 75869d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 75879d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 75889d69cfa2SLijun Pan 75899d69cfa2SLijun Pan tcg_temp_free_i64(t1); 75909d69cfa2SLijun Pan tcg_temp_free_i64(t2); 75919d69cfa2SLijun Pan } 75929d69cfa2SLijun Pan #endif 75939d69cfa2SLijun Pan 7594fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 75959d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75969d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 75979d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 75989d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 75999d69cfa2SLijun Pan #endif 7600fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7601fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7602fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7603fcf5ef2aSThomas Huth #endif 7604fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7605fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7606fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7607fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7608fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7609fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7610fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7611fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7612fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7613fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7614fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7615fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7616fcf5ef2aSThomas Huth #endif 7617fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7618fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7619fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7620fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7621fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7622fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7623fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 762480b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7625b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 762680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7627fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7628fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7629fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7630fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7631fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7632fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7633fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7634fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7635fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7636fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7637fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7638fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7639fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7640fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7641fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7642fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7643fcf5ef2aSThomas Huth #endif 7644fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7645fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7646fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7647fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7648fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7649fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7650fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7651fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7652fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7653fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7654fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7655fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7656fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7657fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7658fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7659fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7660fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7661fcf5ef2aSThomas Huth #endif 7662fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7663fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7664fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7665fcf5ef2aSThomas Huth #endif 76665cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 76675cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7668d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7669e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7670fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7671fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7672fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7673fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7674fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7675fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7676c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7677fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7678fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7679fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7680fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7681a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7682a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7683fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7684fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7685fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7686fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7687a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7688a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7689fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7690fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7691fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7692fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7693fcf5ef2aSThomas Huth #endif 7694fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7695fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7696c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7697fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7698fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7699fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7700fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7701fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7702fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7703fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7704fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7705fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 77063c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 77073c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 77083c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 77093c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 77103c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 77113c89b8d6SNicholas Piggin #endif 7712cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7713fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7714fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7715fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7716fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7717fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7718fcf5ef2aSThomas Huth #endif 77193c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 77203c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 77213c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7722fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7723fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7724fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7725fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7726fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7727fcf5ef2aSThomas Huth #endif 7728fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7729fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7730fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7731fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7732fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7733fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7734fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7735fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7736fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7737b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7738fcf5ef2aSThomas Huth #endif 7739fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7740fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7741fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 774250728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7743fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7744fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 774550728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7746fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 774750728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7748fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 774950728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7750fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7751fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 775250728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7753fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 775499d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7755fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7756fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 775750728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7758fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7759fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7760fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7761fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7762fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7763fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7764fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7765fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7766fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7767fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7768fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7769fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7770fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7771fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7772fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7773fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7774fcf5ef2aSThomas Huth #endif 7775fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7776efe843d8SDavid Gibson /* 7777efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7778efe843d8SDavid Gibson * different ISA versions 7779efe843d8SDavid Gibson */ 7780fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7781fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7782c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7783c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7784fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7785fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7786fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7787fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7788a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 778962d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7790fcf5ef2aSThomas Huth #endif 7791fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7792fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7793fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7794fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7795fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7796fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7797fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7798fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7799fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7800fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7801fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7802fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7803fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7804fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7805fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7806fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7807fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7808fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7809fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7810fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7811fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7812fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7813fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7814fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7815fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7816fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7817fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7818fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7819fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7820fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7821fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7822fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7823fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7824fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7825fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7826fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7827fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7828fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7829fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7830fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7831fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7832fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7833fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7834fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7835fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7836fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7837fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7838fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7839fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7840fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7841fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7842fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7843fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7844fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7845fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7846fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7847fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7848fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7849fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7850fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7851fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7852fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7853fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7854fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7855fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7856fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7857fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7858fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7859fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7860fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7861fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7862fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7863fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7864fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7865fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7866fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7867fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7868fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7869fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7870fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7871fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7872fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7873fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7874fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7875fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7876fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7877fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7878fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7879fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7880fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7881fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7882fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7883fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7884fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 78857af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 78867af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7887fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7888fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7889fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7890fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7891fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 789227a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7893fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7894fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 78950c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 78960c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7897fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7898fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7899fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7900fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7901fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7902fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7903fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7904fcf5ef2aSThomas Huth PPC2_ISA300), 7905fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 79065ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 79075ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 79085ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 79095ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 7910fcf5ef2aSThomas Huth #endif 7911fcf5ef2aSThomas Huth 7912fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7913fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7914fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7915fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7916fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7917fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7918fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7919fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7920fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7921fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7922fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7923fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7924fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7925fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7926fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 79274c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7928fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7929fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7930fcf5ef2aSThomas Huth 7931fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7932fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7933fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7934fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7935fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7936fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7937fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7938fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7939fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7940fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7941fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7942fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7943fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7944fcf5ef2aSThomas Huth 7945fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7946fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7947fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7948fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7949fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7950fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7951fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7952fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7953fcf5ef2aSThomas Huth 7954fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7955fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7956fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7957fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7958fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7959fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7960fcf5ef2aSThomas Huth 7961fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7962fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7963fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7964fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7965fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7966fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7967fcf5ef2aSThomas Huth #endif 7968fcf5ef2aSThomas Huth 7969fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7970fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7971fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7972fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7973fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7974fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7975fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7976fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7977fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7978fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7979fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7980fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7981fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7982fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7983fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7984fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7985fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7986fcf5ef2aSThomas Huth 7987fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7988fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7989fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7990fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7991fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7992fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7993fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7994fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7995fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7996fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7997fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7998fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7999fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8000fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8001fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8002fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8003fcf5ef2aSThomas Huth #endif 8004fcf5ef2aSThomas Huth 8005fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8006fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8007fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8008fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8009fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8010fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8011fcf5ef2aSThomas Huth PPC_64B) 8012fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8013fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8014fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8015fcf5ef2aSThomas Huth PPC_64B), \ 8016fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8017fcf5ef2aSThomas Huth PPC_64B), \ 8018fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8019fcf5ef2aSThomas Huth PPC_64B) 8020fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8021fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8022fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8023fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8024fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8025fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8026fcf5ef2aSThomas Huth #endif 8027fcf5ef2aSThomas Huth 8028fcf5ef2aSThomas Huth #undef GEN_LDX_E 8029fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8030fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8031fcf5ef2aSThomas Huth 8032fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8033fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8034fcf5ef2aSThomas Huth 8035fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8036fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8037fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8038fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8039fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8040fcf5ef2aSThomas Huth #endif 8041fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8042fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8043fcf5ef2aSThomas Huth 804450728199SRoman Kapl /* External PID based load */ 804550728199SRoman Kapl #undef GEN_LDEPX 804650728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 804750728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 804850728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 804950728199SRoman Kapl 805050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 805150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 805250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 805350728199SRoman Kapl #if defined(TARGET_PPC64) 805450728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 805550728199SRoman Kapl #endif 805650728199SRoman Kapl 8057fcf5ef2aSThomas Huth #undef GEN_STX_E 8058fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 80590123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8060fcf5ef2aSThomas Huth 8061fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8062fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8063fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8064fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8065fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8066fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8067fcf5ef2aSThomas Huth #endif 8068fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8069fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8070fcf5ef2aSThomas Huth 807150728199SRoman Kapl #undef GEN_STEPX 807250728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 807350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 807450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 807550728199SRoman Kapl 807650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 807750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 807850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 807950728199SRoman Kapl #if defined(TARGET_PPC64) 808050728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 808150728199SRoman Kapl #endif 808250728199SRoman Kapl 8083fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8084fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8085fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8086fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8087fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8088fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8089fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8090fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8091fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8092fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8093fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8094fcf5ef2aSThomas Huth 8095fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8096fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8097fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8104fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8106fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8108fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8110fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8112fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8114fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8116fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8118fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8120fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8122fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8124fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8126fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8128fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8130fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8132fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8134fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8136fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8138fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8140fcf5ef2aSThomas Huth 8141fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8142fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8143fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8144fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8145fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8146fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8147fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8148fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8149fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8150fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8151fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8152fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8153fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8154fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8155fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8156fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8157fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8158fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8159fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8160fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8161fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8162fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8163fcf5ef2aSThomas Huth 8164139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8165fcf5ef2aSThomas Huth 8166139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8167fcf5ef2aSThomas Huth 8168139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8169fcf5ef2aSThomas Huth 8170139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8171fcf5ef2aSThomas Huth 8172139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8173fcf5ef2aSThomas Huth }; 8174fcf5ef2aSThomas Huth 81757468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 81767468e2c8SBruno Larsen (billionai) /* Opcode types */ 81777468e2c8SBruno Larsen (billionai) enum { 81787468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 81797468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 81807468e2c8SBruno Larsen (billionai) }; 81817468e2c8SBruno Larsen (billionai) 81827468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 81837468e2c8SBruno Larsen (billionai) 81847468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 81857468e2c8SBruno Larsen (billionai) { 81867468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 81877468e2c8SBruno Larsen (billionai) } 81887468e2c8SBruno Larsen (billionai) 81897468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 81907468e2c8SBruno Larsen (billionai) { 81917468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 81927468e2c8SBruno Larsen (billionai) } 81937468e2c8SBruno Larsen (billionai) 81947468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 81957468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 81967468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 81977468e2c8SBruno Larsen (billionai) { 81987468e2c8SBruno Larsen (billionai) int i; 81997468e2c8SBruno Larsen (billionai) 82007468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 82017468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 82027468e2c8SBruno Larsen (billionai) } 82037468e2c8SBruno Larsen (billionai) } 82047468e2c8SBruno Larsen (billionai) 82057468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 82067468e2c8SBruno Larsen (billionai) { 82077468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 82087468e2c8SBruno Larsen (billionai) 82097468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 82107468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 82117468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 82127468e2c8SBruno Larsen (billionai) 82137468e2c8SBruno Larsen (billionai) return 0; 82147468e2c8SBruno Larsen (billionai) } 82157468e2c8SBruno Larsen (billionai) 82167468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 82177468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82187468e2c8SBruno Larsen (billionai) { 82197468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 82207468e2c8SBruno Larsen (billionai) return -1; 82217468e2c8SBruno Larsen (billionai) } 82227468e2c8SBruno Larsen (billionai) table[idx] = handler; 82237468e2c8SBruno Larsen (billionai) 82247468e2c8SBruno Larsen (billionai) return 0; 82257468e2c8SBruno Larsen (billionai) } 82267468e2c8SBruno Larsen (billionai) 82277468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 82287468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 82297468e2c8SBruno Larsen (billionai) { 82307468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 82317468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 82327468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 82337468e2c8SBruno Larsen (billionai) return -1; 82347468e2c8SBruno Larsen (billionai) } 82357468e2c8SBruno Larsen (billionai) 82367468e2c8SBruno Larsen (billionai) return 0; 82377468e2c8SBruno Larsen (billionai) } 82387468e2c8SBruno Larsen (billionai) 82397468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 82407468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82417468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82427468e2c8SBruno Larsen (billionai) { 82437468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 82447468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 82457468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 82467468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 82477468e2c8SBruno Larsen (billionai) return -1; 82487468e2c8SBruno Larsen (billionai) } 82497468e2c8SBruno Larsen (billionai) } else { 82507468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 82517468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 82527468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 82537468e2c8SBruno Larsen (billionai) return -1; 82547468e2c8SBruno Larsen (billionai) } 82557468e2c8SBruno Larsen (billionai) } 82567468e2c8SBruno Larsen (billionai) if (handler != NULL && 82577468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 82587468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 82597468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 82607468e2c8SBruno Larsen (billionai) return -1; 82617468e2c8SBruno Larsen (billionai) } 82627468e2c8SBruno Larsen (billionai) 82637468e2c8SBruno Larsen (billionai) return 0; 82647468e2c8SBruno Larsen (billionai) } 82657468e2c8SBruno Larsen (billionai) 82667468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 82677468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82687468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82697468e2c8SBruno Larsen (billionai) { 82707468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 82717468e2c8SBruno Larsen (billionai) } 82727468e2c8SBruno Larsen (billionai) 82737468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 82747468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82757468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 82767468e2c8SBruno Larsen (billionai) { 82777468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82787468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82797468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82807468e2c8SBruno Larsen (billionai) return -1; 82817468e2c8SBruno Larsen (billionai) } 82827468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 82837468e2c8SBruno Larsen (billionai) handler) < 0) { 82847468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 82857468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 82867468e2c8SBruno Larsen (billionai) return -1; 82877468e2c8SBruno Larsen (billionai) } 82887468e2c8SBruno Larsen (billionai) 82897468e2c8SBruno Larsen (billionai) return 0; 82907468e2c8SBruno Larsen (billionai) } 82917468e2c8SBruno Larsen (billionai) 82927468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 82937468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82947468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 82957468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82967468e2c8SBruno Larsen (billionai) { 82977468e2c8SBruno Larsen (billionai) opc_handler_t **table; 82987468e2c8SBruno Larsen (billionai) 82997468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 83007468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 83017468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 83027468e2c8SBruno Larsen (billionai) return -1; 83037468e2c8SBruno Larsen (billionai) } 83047468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 83057468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 83067468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 83077468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 83087468e2c8SBruno Larsen (billionai) return -1; 83097468e2c8SBruno Larsen (billionai) } 83107468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 83117468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 83127468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 83137468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 83147468e2c8SBruno Larsen (billionai) return -1; 83157468e2c8SBruno Larsen (billionai) } 83167468e2c8SBruno Larsen (billionai) return 0; 83177468e2c8SBruno Larsen (billionai) } 83187468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 83197468e2c8SBruno Larsen (billionai) { 83207468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 83217468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 83227468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 83237468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 83247468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 83257468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 83267468e2c8SBruno Larsen (billionai) return -1; 83277468e2c8SBruno Larsen (billionai) } 83287468e2c8SBruno Larsen (billionai) } else { 83297468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 83307468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 83317468e2c8SBruno Larsen (billionai) return -1; 83327468e2c8SBruno Larsen (billionai) } 83337468e2c8SBruno Larsen (billionai) } 83347468e2c8SBruno Larsen (billionai) } else { 83357468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 83367468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 83377468e2c8SBruno Larsen (billionai) return -1; 83387468e2c8SBruno Larsen (billionai) } 83397468e2c8SBruno Larsen (billionai) } 83407468e2c8SBruno Larsen (billionai) } else { 83417468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 83427468e2c8SBruno Larsen (billionai) return -1; 83437468e2c8SBruno Larsen (billionai) } 83447468e2c8SBruno Larsen (billionai) } 83457468e2c8SBruno Larsen (billionai) 83467468e2c8SBruno Larsen (billionai) return 0; 83477468e2c8SBruno Larsen (billionai) } 83487468e2c8SBruno Larsen (billionai) 83497468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 83507468e2c8SBruno Larsen (billionai) { 83517468e2c8SBruno Larsen (billionai) int i, count, tmp; 83527468e2c8SBruno Larsen (billionai) 83537468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 83547468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 83557468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 83567468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83577468e2c8SBruno Larsen (billionai) } 83587468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 83597468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 83607468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 83617468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 83627468e2c8SBruno Larsen (billionai) if (tmp == 0) { 83637468e2c8SBruno Larsen (billionai) free(table[i]); 83647468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83657468e2c8SBruno Larsen (billionai) } else { 83667468e2c8SBruno Larsen (billionai) count++; 83677468e2c8SBruno Larsen (billionai) } 83687468e2c8SBruno Larsen (billionai) } else { 83697468e2c8SBruno Larsen (billionai) count++; 83707468e2c8SBruno Larsen (billionai) } 83717468e2c8SBruno Larsen (billionai) } 83727468e2c8SBruno Larsen (billionai) } 83737468e2c8SBruno Larsen (billionai) 83747468e2c8SBruno Larsen (billionai) return count; 83757468e2c8SBruno Larsen (billionai) } 83767468e2c8SBruno Larsen (billionai) 83777468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 83787468e2c8SBruno Larsen (billionai) { 83797468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 83807468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 83817468e2c8SBruno Larsen (billionai) } 83827468e2c8SBruno Larsen (billionai) } 83837468e2c8SBruno Larsen (billionai) 83847468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 83857468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 83867468e2c8SBruno Larsen (billionai) { 83877468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 83887468e2c8SBruno Larsen (billionai) opcode_t *opc; 83897468e2c8SBruno Larsen (billionai) 83907468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 83917468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 83927468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 83937468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 83947468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 83957468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 83967468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 83977468e2c8SBruno Larsen (billionai) opc->opc3); 83987468e2c8SBruno Larsen (billionai) return; 83997468e2c8SBruno Larsen (billionai) } 84007468e2c8SBruno Larsen (billionai) } 84017468e2c8SBruno Larsen (billionai) } 84027468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 84037468e2c8SBruno Larsen (billionai) fflush(stdout); 84047468e2c8SBruno Larsen (billionai) fflush(stderr); 84057468e2c8SBruno Larsen (billionai) } 84067468e2c8SBruno Larsen (billionai) 84077468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 84087468e2c8SBruno Larsen (billionai) { 84097468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 84107468e2c8SBruno Larsen (billionai) int i, j, k; 84117468e2c8SBruno Larsen (billionai) 84127468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 84137468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 84147468e2c8SBruno Larsen (billionai) continue; 84157468e2c8SBruno Larsen (billionai) } 84167468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 84177468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 84187468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 84197468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 84207468e2c8SBruno Larsen (billionai) continue; 84217468e2c8SBruno Larsen (billionai) } 84227468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 84237468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 84247468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 84257468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 84267468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 84277468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 84287468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84297468e2c8SBruno Larsen (billionai) } 84307468e2c8SBruno Larsen (billionai) } 84317468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 84327468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84337468e2c8SBruno Larsen (billionai) } 84347468e2c8SBruno Larsen (billionai) } 84357468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 84367468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84377468e2c8SBruno Larsen (billionai) } 84387468e2c8SBruno Larsen (billionai) } 84397468e2c8SBruno Larsen (billionai) } 84407468e2c8SBruno Larsen (billionai) 84417468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 84427468e2c8SBruno Larsen (billionai) { 84437468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 84447468e2c8SBruno Larsen (billionai) 84457468e2c8SBruno Larsen (billionai) /* 84467468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 84477468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 84487468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 84497468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 84507468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 84517468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 84527468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 84537468e2c8SBruno Larsen (billionai) */ 84547468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 84557468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 84567468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 84577468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 84587468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 84597468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 84607468e2c8SBruno Larsen (billionai) } 84617468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 84627468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 84637468e2c8SBruno Larsen (billionai) return 0; 84647468e2c8SBruno Larsen (billionai) } 84657468e2c8SBruno Larsen (billionai) 8466624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8467624cb07fSRichard Henderson { 8468624cb07fSRichard Henderson opc_handler_t **table, *handler; 8469624cb07fSRichard Henderson uint32_t inval; 8470624cb07fSRichard Henderson 8471624cb07fSRichard Henderson ctx->opcode = insn; 8472624cb07fSRichard Henderson 8473624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8474624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8475624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8476624cb07fSRichard Henderson 8477624cb07fSRichard Henderson table = cpu->opcodes; 8478624cb07fSRichard Henderson handler = table[opc1(insn)]; 8479624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8480624cb07fSRichard Henderson table = ind_table(handler); 8481624cb07fSRichard Henderson handler = table[opc2(insn)]; 8482624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8483624cb07fSRichard Henderson table = ind_table(handler); 8484624cb07fSRichard Henderson handler = table[opc3(insn)]; 8485624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8486624cb07fSRichard Henderson table = ind_table(handler); 8487624cb07fSRichard Henderson handler = table[opc4(insn)]; 8488624cb07fSRichard Henderson } 8489624cb07fSRichard Henderson } 8490624cb07fSRichard Henderson } 8491624cb07fSRichard Henderson 8492624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8493624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8494624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8495624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8496624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8497624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8498624cb07fSRichard Henderson insn, ctx->cia); 8499624cb07fSRichard Henderson return false; 8500624cb07fSRichard Henderson } 8501624cb07fSRichard Henderson 8502624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8503624cb07fSRichard Henderson && Rc(insn))) { 8504624cb07fSRichard Henderson inval = handler->inval2; 8505624cb07fSRichard Henderson } else { 8506624cb07fSRichard Henderson inval = handler->inval1; 8507624cb07fSRichard Henderson } 8508624cb07fSRichard Henderson 8509624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8510624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8511624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8512624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8513624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8514624cb07fSRichard Henderson insn, ctx->cia); 8515624cb07fSRichard Henderson return false; 8516624cb07fSRichard Henderson } 8517624cb07fSRichard Henderson 8518624cb07fSRichard Henderson handler->handler(ctx); 8519624cb07fSRichard Henderson return true; 8520624cb07fSRichard Henderson } 8521624cb07fSRichard Henderson 8522b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8523fcf5ef2aSThomas Huth { 8524b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 85259c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 85262df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8527fcf5ef2aSThomas Huth 8528b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 85292df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8530d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 85312df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 85322df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 8533b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 8534b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 8535b0c2d521SEmilio G. Cota ctx->access_type = -1; 8536d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 85372df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8538b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 85390e3bf489SRoman Kapl ctx->flags = env->flags; 8540fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 85412df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8542b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8543fcf5ef2aSThomas Huth #endif 8544e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8545e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 8546d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 8547fcf5ef2aSThomas Huth 85482df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 85492df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 85502df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 85512df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 85522df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8553f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 85541db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 85552df4fe7aSRichard Henderson 8556b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 85572df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 85582df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 85599498d103SRichard Henderson ctx->base.max_insns = 1; 8560efe843d8SDavid Gibson } 85612df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 8562b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8563efe843d8SDavid Gibson } 856413b45575SRichard Henderson } 8565fcf5ef2aSThomas Huth 8566b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8567b0c2d521SEmilio G. Cota { 8568b0c2d521SEmilio G. Cota } 8569fcf5ef2aSThomas Huth 8570b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8571b0c2d521SEmilio G. Cota { 8572b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 8573b0c2d521SEmilio G. Cota } 8574b0c2d521SEmilio G. Cota 857599082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 857699082815SRichard Henderson { 857799082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 857899082815SRichard Henderson return opc1(insn) == 1; 857999082815SRichard Henderson } 858099082815SRichard Henderson 8581b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8582b0c2d521SEmilio G. Cota { 8583b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 858428876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 8585b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 858699082815SRichard Henderson target_ulong pc; 8587624cb07fSRichard Henderson uint32_t insn; 8588624cb07fSRichard Henderson bool ok; 8589b0c2d521SEmilio G. Cota 8590fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 8591fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8592b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8593b0c2d521SEmilio G. Cota 859499082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 85954e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 859699082815SRichard Henderson ctx->base.pc_next = pc += 4; 8597fcf5ef2aSThomas Huth 859899082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 859999082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 860099082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 860199082815SRichard Henderson } else if ((pc & 63) == 0) { 860299082815SRichard Henderson /* 860399082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 860499082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 860599082815SRichard Henderson * 64-byte address boundary (system alignment error). 860699082815SRichard Henderson */ 860799082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 860899082815SRichard Henderson ok = true; 860999082815SRichard Henderson } else { 86104e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 86114e116893SIlya Leoshkevich need_byteswap(ctx)); 861299082815SRichard Henderson ctx->base.pc_next = pc += 4; 861399082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 861499082815SRichard Henderson } 8615624cb07fSRichard Henderson if (!ok) { 8616624cb07fSRichard Henderson gen_invalid(ctx); 8617fcf5ef2aSThomas Huth } 8618624cb07fSRichard Henderson 861964a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 862099082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 862164a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 862264a0f644SRichard Henderson } 862364a0f644SRichard Henderson 862451eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 8625fcf5ef2aSThomas Huth } 8626b0c2d521SEmilio G. Cota 8627b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8628b0c2d521SEmilio G. Cota { 8629b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8630a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 8631a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 8632b0c2d521SEmilio G. Cota 8633a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 8634a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 86353d8a5b69SRichard Henderson return; 86363d8a5b69SRichard Henderson } 86373d8a5b69SRichard Henderson 8638a9b5b3d0SRichard Henderson /* Honor single stepping. */ 86399498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 86409498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 8641a9b5b3d0SRichard Henderson switch (is_jmp) { 8642a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8643a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8644a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8645a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8646a9b5b3d0SRichard Henderson break; 8647a9b5b3d0SRichard Henderson case DISAS_EXIT: 8648a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8649a9b5b3d0SRichard Henderson break; 8650a9b5b3d0SRichard Henderson default: 8651a9b5b3d0SRichard Henderson g_assert_not_reached(); 8652fcf5ef2aSThomas Huth } 865313b45575SRichard Henderson 8654a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 8655a9b5b3d0SRichard Henderson return; 8656a9b5b3d0SRichard Henderson } 8657a9b5b3d0SRichard Henderson 8658a9b5b3d0SRichard Henderson switch (is_jmp) { 8659a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8660a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 8661a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 8662a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8663a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 8664a9b5b3d0SRichard Henderson break; 8665a9b5b3d0SRichard Henderson } 8666a9b5b3d0SRichard Henderson /* fall through */ 8667a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8668a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8669a9b5b3d0SRichard Henderson /* fall through */ 8670a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8671a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 8672a9b5b3d0SRichard Henderson break; 8673a9b5b3d0SRichard Henderson 8674a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8675a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8676a9b5b3d0SRichard Henderson /* fall through */ 8677a9b5b3d0SRichard Henderson case DISAS_EXIT: 867807ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8679a9b5b3d0SRichard Henderson break; 8680a9b5b3d0SRichard Henderson 8681a9b5b3d0SRichard Henderson default: 8682a9b5b3d0SRichard Henderson g_assert_not_reached(); 8683fcf5ef2aSThomas Huth } 8684fcf5ef2aSThomas Huth } 8685b0c2d521SEmilio G. Cota 8686b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8687b0c2d521SEmilio G. Cota { 8688b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8689b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8690b0c2d521SEmilio G. Cota } 8691b0c2d521SEmilio G. Cota 8692b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8693b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8694b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8695b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8696b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8697b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8698b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8699b0c2d521SEmilio G. Cota }; 8700b0c2d521SEmilio G. Cota 87018b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8702b0c2d521SEmilio G. Cota { 8703b0c2d521SEmilio G. Cota DisasContext ctx; 8704b0c2d521SEmilio G. Cota 87058b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8706fcf5ef2aSThomas Huth } 8707fcf5ef2aSThomas Huth 8708fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8709fcf5ef2aSThomas Huth target_ulong *data) 8710fcf5ef2aSThomas Huth { 8711fcf5ef2aSThomas Huth env->nip = data[0]; 8712fcf5ef2aSThomas Huth } 8713