1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26fcf5ef2aSThomas Huth #include "tcg-op.h" 27fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #include "trace-tcg.h" 34fcf5ef2aSThomas Huth #include "exec/log.h" 35fcf5ef2aSThomas Huth 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 38fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 39fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 40fcf5ef2aSThomas Huth 41fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 42fcf5ef2aSThomas Huth //#define PPC_DEBUG_DISAS 43fcf5ef2aSThomas Huth //#define DO_PPC_STATISTICS 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 46fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 47fcf5ef2aSThomas Huth #else 48fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 49fcf5ef2aSThomas Huth #endif 50fcf5ef2aSThomas Huth /*****************************************************************************/ 51fcf5ef2aSThomas Huth /* Code translation helpers */ 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth /* global register indexes */ 54fcf5ef2aSThomas Huth static TCGv_env cpu_env; 55fcf5ef2aSThomas Huth static char cpu_reg_names[10*3 + 22*4 /* GPR */ 56fcf5ef2aSThomas Huth + 10*4 + 22*5 /* SPE GPRh */ 57fcf5ef2aSThomas Huth + 10*4 + 22*5 /* FPR */ 58fcf5ef2aSThomas Huth + 2*(10*6 + 22*7) /* AVRh, AVRl */ 59fcf5ef2aSThomas Huth + 10*5 + 22*6 /* VSR */ 60fcf5ef2aSThomas Huth + 8*5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[32]; 64fcf5ef2aSThomas Huth static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 65fcf5ef2aSThomas Huth static TCGv_i64 cpu_vsr[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 77fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth void ppc_translate_init(void) 82fcf5ef2aSThomas Huth { 83fcf5ef2aSThomas Huth int i; 84fcf5ef2aSThomas Huth char* p; 85fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 86fcf5ef2aSThomas Huth static int done_init = 0; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth if (done_init) 89fcf5ef2aSThomas Huth return; 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 92fcf5ef2aSThomas Huth tcg_ctx.tcg_env = cpu_env; 93fcf5ef2aSThomas Huth 94fcf5ef2aSThomas Huth p = cpu_reg_names; 95fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 96fcf5ef2aSThomas Huth 97fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 98fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 99fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 100fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 101fcf5ef2aSThomas Huth p += 5; 102fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 103fcf5ef2aSThomas Huth } 104fcf5ef2aSThomas Huth 105fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 106fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 107fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 108fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 109fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 110fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 111fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 112fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 114fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 115fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "fp%d", i); 118fcf5ef2aSThomas Huth cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpr[i]), p); 120fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 121fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dH", i); 124fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 125fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 127fcf5ef2aSThomas Huth #else 128fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 130fcf5ef2aSThomas Huth #endif 131fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 132fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 133fcf5ef2aSThomas Huth 134fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dL", i); 135fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 136fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 137fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 138fcf5ef2aSThomas Huth #else 139fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 141fcf5ef2aSThomas Huth #endif 142fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 143fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 144fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "vsr%d", i); 145fcf5ef2aSThomas Huth cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 146fcf5ef2aSThomas Huth offsetof(CPUPPCState, vsr[i]), p); 147fcf5ef2aSThomas Huth p += (i < 10) ? 5 : 6; 148fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 5 : 6; 149fcf5ef2aSThomas Huth } 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 152fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 155fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 158fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 159fcf5ef2aSThomas Huth 160fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 161fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 162fcf5ef2aSThomas Huth 163fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 164fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 165fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 166fcf5ef2aSThomas Huth #endif 167fcf5ef2aSThomas Huth 168fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 169fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 170fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 171fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 172fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 173fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 174fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 175fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 176dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 177dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 178dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 179dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 182fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 183fcf5ef2aSThomas Huth "reserve_addr"); 184fcf5ef2aSThomas Huth 185fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 186fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 187fcf5ef2aSThomas Huth 188fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 189fcf5ef2aSThomas Huth offsetof(CPUPPCState, access_type), "access_type"); 190fcf5ef2aSThomas Huth 191fcf5ef2aSThomas Huth done_init = 1; 192fcf5ef2aSThomas Huth } 193fcf5ef2aSThomas Huth 194fcf5ef2aSThomas Huth /* internal defines */ 195fcf5ef2aSThomas Huth struct DisasContext { 196fcf5ef2aSThomas Huth struct TranslationBlock *tb; 197fcf5ef2aSThomas Huth target_ulong nip; 198fcf5ef2aSThomas Huth uint32_t opcode; 199fcf5ef2aSThomas Huth uint32_t exception; 200fcf5ef2aSThomas Huth /* Routine used to access memory */ 201fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 202fcf5ef2aSThomas Huth bool lazy_tlb_flush; 203fcf5ef2aSThomas Huth bool need_access_type; 204fcf5ef2aSThomas Huth int mem_idx; 205fcf5ef2aSThomas Huth int access_type; 206fcf5ef2aSThomas Huth /* Translation flags */ 207fcf5ef2aSThomas Huth TCGMemOp default_tcg_memop_mask; 208fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 209fcf5ef2aSThomas Huth bool sf_mode; 210fcf5ef2aSThomas Huth bool has_cfar; 211fcf5ef2aSThomas Huth #endif 212fcf5ef2aSThomas Huth bool fpu_enabled; 213fcf5ef2aSThomas Huth bool altivec_enabled; 214fcf5ef2aSThomas Huth bool vsx_enabled; 215fcf5ef2aSThomas Huth bool spe_enabled; 216fcf5ef2aSThomas Huth bool tm_enabled; 217fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 218fcf5ef2aSThomas Huth int singlestep_enabled; 219fcf5ef2aSThomas Huth uint64_t insns_flags; 220fcf5ef2aSThomas Huth uint64_t insns_flags2; 221fcf5ef2aSThomas Huth }; 222fcf5ef2aSThomas Huth 223fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 224fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 225fcf5ef2aSThomas Huth { 226fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 227fcf5ef2aSThomas Huth return ctx->le_mode; 228fcf5ef2aSThomas Huth #else 229fcf5ef2aSThomas Huth return !ctx->le_mode; 230fcf5ef2aSThomas Huth #endif 231fcf5ef2aSThomas Huth } 232fcf5ef2aSThomas Huth 233fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 234fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 235fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 236fcf5ef2aSThomas Huth #else 237fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 238fcf5ef2aSThomas Huth #endif 239fcf5ef2aSThomas Huth 240fcf5ef2aSThomas Huth struct opc_handler_t { 241fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 242fcf5ef2aSThomas Huth uint32_t inval1; 243fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 244fcf5ef2aSThomas Huth uint32_t inval2; 245fcf5ef2aSThomas Huth /* instruction type */ 246fcf5ef2aSThomas Huth uint64_t type; 247fcf5ef2aSThomas Huth /* extended instruction type */ 248fcf5ef2aSThomas Huth uint64_t type2; 249fcf5ef2aSThomas Huth /* handler */ 250fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 251fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 252fcf5ef2aSThomas Huth const char *oname; 253fcf5ef2aSThomas Huth #endif 254fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 255fcf5ef2aSThomas Huth uint64_t count; 256fcf5ef2aSThomas Huth #endif 257fcf5ef2aSThomas Huth }; 258fcf5ef2aSThomas Huth 259fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 260fcf5ef2aSThomas Huth { 261fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 262fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 263fcf5ef2aSThomas Huth ctx->access_type = access_type; 264fcf5ef2aSThomas Huth } 265fcf5ef2aSThomas Huth } 266fcf5ef2aSThomas Huth 267fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 268fcf5ef2aSThomas Huth { 269fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 270fcf5ef2aSThomas Huth nip = (uint32_t)nip; 271fcf5ef2aSThomas Huth } 272fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 273fcf5ef2aSThomas Huth } 274fcf5ef2aSThomas Huth 275fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 276fcf5ef2aSThomas Huth { 277fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 278fcf5ef2aSThomas Huth 279fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 280fcf5ef2aSThomas Huth * the faulting instruction 281fcf5ef2aSThomas Huth */ 282fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 283fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 284fcf5ef2aSThomas Huth } 285fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 286fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 287fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 288fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 289fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 290fcf5ef2aSThomas Huth ctx->exception = (excp); 291fcf5ef2aSThomas Huth } 292fcf5ef2aSThomas Huth 293fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 294fcf5ef2aSThomas Huth { 295fcf5ef2aSThomas Huth TCGv_i32 t0; 296fcf5ef2aSThomas Huth 297fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 298fcf5ef2aSThomas Huth * the faulting instruction 299fcf5ef2aSThomas Huth */ 300fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 301fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 302fcf5ef2aSThomas Huth } 303fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 304fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 305fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 306fcf5ef2aSThomas Huth ctx->exception = (excp); 307fcf5ef2aSThomas Huth } 308fcf5ef2aSThomas Huth 309fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 310fcf5ef2aSThomas Huth target_ulong nip) 311fcf5ef2aSThomas Huth { 312fcf5ef2aSThomas Huth TCGv_i32 t0; 313fcf5ef2aSThomas Huth 314fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 315fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 316fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 317fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 318fcf5ef2aSThomas Huth ctx->exception = (excp); 319fcf5ef2aSThomas Huth } 320fcf5ef2aSThomas Huth 321fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 322fcf5ef2aSThomas Huth { 323fcf5ef2aSThomas Huth TCGv_i32 t0; 324fcf5ef2aSThomas Huth 325fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 326fcf5ef2aSThomas Huth * the faulting instruction 327fcf5ef2aSThomas Huth */ 328fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 329fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 330fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 331fcf5ef2aSThomas Huth } 332fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 333fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 334fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 335fcf5ef2aSThomas Huth } 336fcf5ef2aSThomas Huth 337fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 338fcf5ef2aSThomas Huth { 339fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 340fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 341fcf5ef2aSThomas Huth } 342fcf5ef2aSThomas Huth 343fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 344fcf5ef2aSThomas Huth { 345fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 346fcf5ef2aSThomas Huth } 347fcf5ef2aSThomas Huth 348fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 351fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 352fcf5ef2aSThomas Huth } 353fcf5ef2aSThomas Huth 354fcf5ef2aSThomas Huth /* Stop translation */ 355fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 356fcf5ef2aSThomas Huth { 357fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 358fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 359fcf5ef2aSThomas Huth } 360fcf5ef2aSThomas Huth 361fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 362fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 363fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 364fcf5ef2aSThomas Huth { 365fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 366fcf5ef2aSThomas Huth } 367fcf5ef2aSThomas Huth #endif 368fcf5ef2aSThomas Huth 369fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 370fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 371fcf5ef2aSThomas Huth 372fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 373fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 374fcf5ef2aSThomas Huth 375fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 376fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 377fcf5ef2aSThomas Huth 378fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 379fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 380fcf5ef2aSThomas Huth 381fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 382fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 383fcf5ef2aSThomas Huth 384fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 385fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 386fcf5ef2aSThomas Huth 387fcf5ef2aSThomas Huth typedef struct opcode_t { 388fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 389fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 390fcf5ef2aSThomas Huth unsigned char pad[4]; 391fcf5ef2aSThomas Huth #endif 392fcf5ef2aSThomas Huth opc_handler_t handler; 393fcf5ef2aSThomas Huth const char *oname; 394fcf5ef2aSThomas Huth } opcode_t; 395fcf5ef2aSThomas Huth 396fcf5ef2aSThomas Huth /* Helpers for priv. check */ 397fcf5ef2aSThomas Huth #define GEN_PRIV \ 398fcf5ef2aSThomas Huth do { \ 399fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 400fcf5ef2aSThomas Huth } while (0) 401fcf5ef2aSThomas Huth 402fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 403fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 404fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 405fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 406fcf5ef2aSThomas Huth #else 407fcf5ef2aSThomas Huth #define CHK_HV \ 408fcf5ef2aSThomas Huth do { \ 409fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 410fcf5ef2aSThomas Huth GEN_PRIV; \ 411fcf5ef2aSThomas Huth } \ 412fcf5ef2aSThomas Huth } while (0) 413fcf5ef2aSThomas Huth #define CHK_SV \ 414fcf5ef2aSThomas Huth do { \ 415fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 416fcf5ef2aSThomas Huth GEN_PRIV; \ 417fcf5ef2aSThomas Huth } \ 418fcf5ef2aSThomas Huth } while (0) 419fcf5ef2aSThomas Huth #define CHK_HVRM \ 420fcf5ef2aSThomas Huth do { \ 421fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 422fcf5ef2aSThomas Huth GEN_PRIV; \ 423fcf5ef2aSThomas Huth } \ 424fcf5ef2aSThomas Huth } while (0) 425fcf5ef2aSThomas Huth #endif 426fcf5ef2aSThomas Huth 427fcf5ef2aSThomas Huth #define CHK_NONE 428fcf5ef2aSThomas Huth 429fcf5ef2aSThomas Huth /*****************************************************************************/ 430fcf5ef2aSThomas Huth /* PowerPC instructions table */ 431fcf5ef2aSThomas Huth 432fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 433fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 434fcf5ef2aSThomas Huth { \ 435fcf5ef2aSThomas Huth .opc1 = op1, \ 436fcf5ef2aSThomas Huth .opc2 = op2, \ 437fcf5ef2aSThomas Huth .opc3 = op3, \ 438fcf5ef2aSThomas Huth .opc4 = 0xff, \ 439fcf5ef2aSThomas Huth .handler = { \ 440fcf5ef2aSThomas Huth .inval1 = invl, \ 441fcf5ef2aSThomas Huth .type = _typ, \ 442fcf5ef2aSThomas Huth .type2 = _typ2, \ 443fcf5ef2aSThomas Huth .handler = &gen_##name, \ 444fcf5ef2aSThomas Huth .oname = stringify(name), \ 445fcf5ef2aSThomas Huth }, \ 446fcf5ef2aSThomas Huth .oname = stringify(name), \ 447fcf5ef2aSThomas Huth } 448fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 449fcf5ef2aSThomas Huth { \ 450fcf5ef2aSThomas Huth .opc1 = op1, \ 451fcf5ef2aSThomas Huth .opc2 = op2, \ 452fcf5ef2aSThomas Huth .opc3 = op3, \ 453fcf5ef2aSThomas Huth .opc4 = 0xff, \ 454fcf5ef2aSThomas Huth .handler = { \ 455fcf5ef2aSThomas Huth .inval1 = invl1, \ 456fcf5ef2aSThomas Huth .inval2 = invl2, \ 457fcf5ef2aSThomas Huth .type = _typ, \ 458fcf5ef2aSThomas Huth .type2 = _typ2, \ 459fcf5ef2aSThomas Huth .handler = &gen_##name, \ 460fcf5ef2aSThomas Huth .oname = stringify(name), \ 461fcf5ef2aSThomas Huth }, \ 462fcf5ef2aSThomas Huth .oname = stringify(name), \ 463fcf5ef2aSThomas Huth } 464fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 465fcf5ef2aSThomas Huth { \ 466fcf5ef2aSThomas Huth .opc1 = op1, \ 467fcf5ef2aSThomas Huth .opc2 = op2, \ 468fcf5ef2aSThomas Huth .opc3 = op3, \ 469fcf5ef2aSThomas Huth .opc4 = 0xff, \ 470fcf5ef2aSThomas Huth .handler = { \ 471fcf5ef2aSThomas Huth .inval1 = invl, \ 472fcf5ef2aSThomas Huth .type = _typ, \ 473fcf5ef2aSThomas Huth .type2 = _typ2, \ 474fcf5ef2aSThomas Huth .handler = &gen_##name, \ 475fcf5ef2aSThomas Huth .oname = onam, \ 476fcf5ef2aSThomas Huth }, \ 477fcf5ef2aSThomas Huth .oname = onam, \ 478fcf5ef2aSThomas Huth } 479fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 480fcf5ef2aSThomas Huth { \ 481fcf5ef2aSThomas Huth .opc1 = op1, \ 482fcf5ef2aSThomas Huth .opc2 = op2, \ 483fcf5ef2aSThomas Huth .opc3 = op3, \ 484fcf5ef2aSThomas Huth .opc4 = op4, \ 485fcf5ef2aSThomas Huth .handler = { \ 486fcf5ef2aSThomas Huth .inval1 = invl, \ 487fcf5ef2aSThomas Huth .type = _typ, \ 488fcf5ef2aSThomas Huth .type2 = _typ2, \ 489fcf5ef2aSThomas Huth .handler = &gen_##name, \ 490fcf5ef2aSThomas Huth .oname = stringify(name), \ 491fcf5ef2aSThomas Huth }, \ 492fcf5ef2aSThomas Huth .oname = stringify(name), \ 493fcf5ef2aSThomas Huth } 494fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 495fcf5ef2aSThomas Huth { \ 496fcf5ef2aSThomas Huth .opc1 = op1, \ 497fcf5ef2aSThomas Huth .opc2 = op2, \ 498fcf5ef2aSThomas Huth .opc3 = op3, \ 499fcf5ef2aSThomas Huth .opc4 = op4, \ 500fcf5ef2aSThomas Huth .handler = { \ 501fcf5ef2aSThomas Huth .inval1 = invl, \ 502fcf5ef2aSThomas Huth .type = _typ, \ 503fcf5ef2aSThomas Huth .type2 = _typ2, \ 504fcf5ef2aSThomas Huth .handler = &gen_##name, \ 505fcf5ef2aSThomas Huth .oname = onam, \ 506fcf5ef2aSThomas Huth }, \ 507fcf5ef2aSThomas Huth .oname = onam, \ 508fcf5ef2aSThomas Huth } 509fcf5ef2aSThomas Huth #else 510fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 511fcf5ef2aSThomas Huth { \ 512fcf5ef2aSThomas Huth .opc1 = op1, \ 513fcf5ef2aSThomas Huth .opc2 = op2, \ 514fcf5ef2aSThomas Huth .opc3 = op3, \ 515fcf5ef2aSThomas Huth .opc4 = 0xff, \ 516fcf5ef2aSThomas Huth .handler = { \ 517fcf5ef2aSThomas Huth .inval1 = invl, \ 518fcf5ef2aSThomas Huth .type = _typ, \ 519fcf5ef2aSThomas Huth .type2 = _typ2, \ 520fcf5ef2aSThomas Huth .handler = &gen_##name, \ 521fcf5ef2aSThomas Huth }, \ 522fcf5ef2aSThomas Huth .oname = stringify(name), \ 523fcf5ef2aSThomas Huth } 524fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 525fcf5ef2aSThomas Huth { \ 526fcf5ef2aSThomas Huth .opc1 = op1, \ 527fcf5ef2aSThomas Huth .opc2 = op2, \ 528fcf5ef2aSThomas Huth .opc3 = op3, \ 529fcf5ef2aSThomas Huth .opc4 = 0xff, \ 530fcf5ef2aSThomas Huth .handler = { \ 531fcf5ef2aSThomas Huth .inval1 = invl1, \ 532fcf5ef2aSThomas Huth .inval2 = invl2, \ 533fcf5ef2aSThomas Huth .type = _typ, \ 534fcf5ef2aSThomas Huth .type2 = _typ2, \ 535fcf5ef2aSThomas Huth .handler = &gen_##name, \ 536fcf5ef2aSThomas Huth }, \ 537fcf5ef2aSThomas Huth .oname = stringify(name), \ 538fcf5ef2aSThomas Huth } 539fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 540fcf5ef2aSThomas Huth { \ 541fcf5ef2aSThomas Huth .opc1 = op1, \ 542fcf5ef2aSThomas Huth .opc2 = op2, \ 543fcf5ef2aSThomas Huth .opc3 = op3, \ 544fcf5ef2aSThomas Huth .opc4 = 0xff, \ 545fcf5ef2aSThomas Huth .handler = { \ 546fcf5ef2aSThomas Huth .inval1 = invl, \ 547fcf5ef2aSThomas Huth .type = _typ, \ 548fcf5ef2aSThomas Huth .type2 = _typ2, \ 549fcf5ef2aSThomas Huth .handler = &gen_##name, \ 550fcf5ef2aSThomas Huth }, \ 551fcf5ef2aSThomas Huth .oname = onam, \ 552fcf5ef2aSThomas Huth } 553fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 554fcf5ef2aSThomas Huth { \ 555fcf5ef2aSThomas Huth .opc1 = op1, \ 556fcf5ef2aSThomas Huth .opc2 = op2, \ 557fcf5ef2aSThomas Huth .opc3 = op3, \ 558fcf5ef2aSThomas Huth .opc4 = op4, \ 559fcf5ef2aSThomas Huth .handler = { \ 560fcf5ef2aSThomas Huth .inval1 = invl, \ 561fcf5ef2aSThomas Huth .type = _typ, \ 562fcf5ef2aSThomas Huth .type2 = _typ2, \ 563fcf5ef2aSThomas Huth .handler = &gen_##name, \ 564fcf5ef2aSThomas Huth }, \ 565fcf5ef2aSThomas Huth .oname = stringify(name), \ 566fcf5ef2aSThomas Huth } 567fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 568fcf5ef2aSThomas Huth { \ 569fcf5ef2aSThomas Huth .opc1 = op1, \ 570fcf5ef2aSThomas Huth .opc2 = op2, \ 571fcf5ef2aSThomas Huth .opc3 = op3, \ 572fcf5ef2aSThomas Huth .opc4 = op4, \ 573fcf5ef2aSThomas Huth .handler = { \ 574fcf5ef2aSThomas Huth .inval1 = invl, \ 575fcf5ef2aSThomas Huth .type = _typ, \ 576fcf5ef2aSThomas Huth .type2 = _typ2, \ 577fcf5ef2aSThomas Huth .handler = &gen_##name, \ 578fcf5ef2aSThomas Huth }, \ 579fcf5ef2aSThomas Huth .oname = onam, \ 580fcf5ef2aSThomas Huth } 581fcf5ef2aSThomas Huth #endif 582fcf5ef2aSThomas Huth 583fcf5ef2aSThomas Huth /* SPR load/store helpers */ 584fcf5ef2aSThomas Huth static inline void gen_load_spr(TCGv t, int reg) 585fcf5ef2aSThomas Huth { 586fcf5ef2aSThomas Huth tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 587fcf5ef2aSThomas Huth } 588fcf5ef2aSThomas Huth 589fcf5ef2aSThomas Huth static inline void gen_store_spr(int reg, TCGv t) 590fcf5ef2aSThomas Huth { 591fcf5ef2aSThomas Huth tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 592fcf5ef2aSThomas Huth } 593fcf5ef2aSThomas Huth 594fcf5ef2aSThomas Huth /* Invalid instruction */ 595fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 596fcf5ef2aSThomas Huth { 597fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 598fcf5ef2aSThomas Huth } 599fcf5ef2aSThomas Huth 600fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 601fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 602fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 603fcf5ef2aSThomas Huth .type = PPC_NONE, 604fcf5ef2aSThomas Huth .type2 = PPC_NONE, 605fcf5ef2aSThomas Huth .handler = gen_invalid, 606fcf5ef2aSThomas Huth }; 607fcf5ef2aSThomas Huth 608fcf5ef2aSThomas Huth /*** Integer comparison ***/ 609fcf5ef2aSThomas Huth 610fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 611fcf5ef2aSThomas Huth { 612fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 613fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 614fcf5ef2aSThomas Huth 615fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 616fcf5ef2aSThomas Huth 617fcf5ef2aSThomas Huth tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); 618fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 619efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_LT_BIT); 620fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 621fcf5ef2aSThomas Huth 622fcf5ef2aSThomas Huth tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); 623fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 624efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_GT_BIT); 625fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 626fcf5ef2aSThomas Huth 627fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); 628fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 629efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT); 630fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 631fcf5ef2aSThomas Huth 632fcf5ef2aSThomas Huth tcg_temp_free(t0); 633fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 634fcf5ef2aSThomas Huth } 635fcf5ef2aSThomas Huth 636fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 637fcf5ef2aSThomas Huth { 638fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 639fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 640fcf5ef2aSThomas Huth tcg_temp_free(t0); 641fcf5ef2aSThomas Huth } 642fcf5ef2aSThomas Huth 643fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 644fcf5ef2aSThomas Huth { 645fcf5ef2aSThomas Huth TCGv t0, t1; 646fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 647fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 648fcf5ef2aSThomas Huth if (s) { 649fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 650fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 651fcf5ef2aSThomas Huth } else { 652fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 653fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 654fcf5ef2aSThomas Huth } 655fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 656fcf5ef2aSThomas Huth tcg_temp_free(t1); 657fcf5ef2aSThomas Huth tcg_temp_free(t0); 658fcf5ef2aSThomas Huth } 659fcf5ef2aSThomas Huth 660fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 661fcf5ef2aSThomas Huth { 662fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 663fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 664fcf5ef2aSThomas Huth tcg_temp_free(t0); 665fcf5ef2aSThomas Huth } 666fcf5ef2aSThomas Huth 667fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 668fcf5ef2aSThomas Huth { 669fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 670fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 671fcf5ef2aSThomas Huth } else { 672fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 673fcf5ef2aSThomas Huth } 674fcf5ef2aSThomas Huth } 675fcf5ef2aSThomas Huth 676fcf5ef2aSThomas Huth /* cmp */ 677fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 678fcf5ef2aSThomas Huth { 679fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 680fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 681fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 682fcf5ef2aSThomas Huth } else { 683fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 684fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 685fcf5ef2aSThomas Huth } 686fcf5ef2aSThomas Huth } 687fcf5ef2aSThomas Huth 688fcf5ef2aSThomas Huth /* cmpi */ 689fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 690fcf5ef2aSThomas Huth { 691fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 692fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 693fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 694fcf5ef2aSThomas Huth } else { 695fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 696fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 697fcf5ef2aSThomas Huth } 698fcf5ef2aSThomas Huth } 699fcf5ef2aSThomas Huth 700fcf5ef2aSThomas Huth /* cmpl */ 701fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 702fcf5ef2aSThomas Huth { 703fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 704fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 705fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 706fcf5ef2aSThomas Huth } else { 707fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 708fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 709fcf5ef2aSThomas Huth } 710fcf5ef2aSThomas Huth } 711fcf5ef2aSThomas Huth 712fcf5ef2aSThomas Huth /* cmpli */ 713fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 714fcf5ef2aSThomas Huth { 715fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 716fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 717fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 718fcf5ef2aSThomas Huth } else { 719fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 720fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 721fcf5ef2aSThomas Huth } 722fcf5ef2aSThomas Huth } 723fcf5ef2aSThomas Huth 724fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 725fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 726fcf5ef2aSThomas Huth { 727fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 728fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 729fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 730fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 731fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 732fcf5ef2aSThomas Huth 733fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 734fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 735fcf5ef2aSThomas Huth 736fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 737fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 738fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 739fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 740fcf5ef2aSThomas Huth 741fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 742fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 743fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 744fcf5ef2aSThomas Huth 745fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 746fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 747fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 748fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 749fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 750fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 751fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 752fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 753fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 754fcf5ef2aSThomas Huth } 755efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 756fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 757fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 758fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 759fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 760fcf5ef2aSThomas Huth } 761fcf5ef2aSThomas Huth 762fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 763fcf5ef2aSThomas Huth /* cmpeqb */ 764fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 765fcf5ef2aSThomas Huth { 766fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 767fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 768fcf5ef2aSThomas Huth } 769fcf5ef2aSThomas Huth #endif 770fcf5ef2aSThomas Huth 771fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 772fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 773fcf5ef2aSThomas Huth { 774fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 775fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 776fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 777fcf5ef2aSThomas Huth TCGv zr; 778fcf5ef2aSThomas Huth 779fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 780fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 781fcf5ef2aSThomas Huth 782fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 783fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 784fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 785fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 786fcf5ef2aSThomas Huth tcg_temp_free(zr); 787fcf5ef2aSThomas Huth tcg_temp_free(t0); 788fcf5ef2aSThomas Huth } 789fcf5ef2aSThomas Huth 790fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 791fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 792fcf5ef2aSThomas Huth { 793fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 794fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 795fcf5ef2aSThomas Huth } 796fcf5ef2aSThomas Huth 797fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 798fcf5ef2aSThomas Huth 799fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 800fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 801fcf5ef2aSThomas Huth { 802fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 803fcf5ef2aSThomas Huth 804fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 805fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 806fcf5ef2aSThomas Huth if (sub) { 807fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 808fcf5ef2aSThomas Huth } else { 809fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 810fcf5ef2aSThomas Huth } 811fcf5ef2aSThomas Huth tcg_temp_free(t0); 812fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 813dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 814dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 815dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 816fcf5ef2aSThomas Huth } 817dc0ad844SNikunj A Dadhania } else { 818dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 819dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 820dc0ad844SNikunj A Dadhania } 821dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1); 822dc0ad844SNikunj A Dadhania } 823fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 824fcf5ef2aSThomas Huth } 825fcf5ef2aSThomas Huth 8266b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8276b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 8286b10d008SNikunj A Dadhania int sub) 8296b10d008SNikunj A Dadhania { 8306b10d008SNikunj A Dadhania TCGv t0; 8316b10d008SNikunj A Dadhania 8326b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8336b10d008SNikunj A Dadhania return; 8346b10d008SNikunj A Dadhania } 8356b10d008SNikunj A Dadhania 8366b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 83733903d0aSNikunj A Dadhania if (sub) { 83833903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 83933903d0aSNikunj A Dadhania } else { 8406b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 84133903d0aSNikunj A Dadhania } 8426b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 8436b10d008SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); 8446b10d008SNikunj A Dadhania tcg_temp_free(t0); 8456b10d008SNikunj A Dadhania } 8466b10d008SNikunj A Dadhania 847fcf5ef2aSThomas Huth /* Common add function */ 848fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 849fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 850fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 851fcf5ef2aSThomas Huth { 852fcf5ef2aSThomas Huth TCGv t0 = ret; 853fcf5ef2aSThomas Huth 854fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 855fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 856fcf5ef2aSThomas Huth } 857fcf5ef2aSThomas Huth 858fcf5ef2aSThomas Huth if (compute_ca) { 859fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 860fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 861fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 862fcf5ef2aSThomas Huth carry into bit 32. */ 863fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 864fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 865fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 866fcf5ef2aSThomas Huth if (add_ca) { 867fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 868fcf5ef2aSThomas Huth } 869fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 870fcf5ef2aSThomas Huth tcg_temp_free(t1); 871fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ 872fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); 8736b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 8746b10d008SNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 8756b10d008SNikunj A Dadhania } 876fcf5ef2aSThomas Huth } else { 877fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 878fcf5ef2aSThomas Huth if (add_ca) { 879fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 880fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 881fcf5ef2aSThomas Huth } else { 882fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 883fcf5ef2aSThomas Huth } 8846b10d008SNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); 885fcf5ef2aSThomas Huth tcg_temp_free(zero); 886fcf5ef2aSThomas Huth } 887fcf5ef2aSThomas Huth } else { 888fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 889fcf5ef2aSThomas Huth if (add_ca) { 890fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 891fcf5ef2aSThomas Huth } 892fcf5ef2aSThomas Huth } 893fcf5ef2aSThomas Huth 894fcf5ef2aSThomas Huth if (compute_ov) { 895fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 896fcf5ef2aSThomas Huth } 897fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 898fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 899fcf5ef2aSThomas Huth } 900fcf5ef2aSThomas Huth 901fcf5ef2aSThomas Huth if (!TCGV_EQUAL(t0, ret)) { 902fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 903fcf5ef2aSThomas Huth tcg_temp_free(t0); 904fcf5ef2aSThomas Huth } 905fcf5ef2aSThomas Huth } 906fcf5ef2aSThomas Huth /* Add functions with two operands */ 907fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 908fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 909fcf5ef2aSThomas Huth { \ 910fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 911fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 912fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 913fcf5ef2aSThomas Huth } 914fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 915fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 916fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 917fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 918fcf5ef2aSThomas Huth { \ 919fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 920fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 921fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 922fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 923fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 924fcf5ef2aSThomas Huth } 925fcf5ef2aSThomas Huth 926fcf5ef2aSThomas Huth /* add add. addo addo. */ 927fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 928fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 929fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 930fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 931fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 932fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 933fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 934fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 935fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 936fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 937fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 938fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 939fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 940fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 941fcf5ef2aSThomas Huth /* addi */ 942fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 943fcf5ef2aSThomas Huth { 944fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 945fcf5ef2aSThomas Huth 946fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 947fcf5ef2aSThomas Huth /* li case */ 948fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 949fcf5ef2aSThomas Huth } else { 950fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 951fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 952fcf5ef2aSThomas Huth } 953fcf5ef2aSThomas Huth } 954fcf5ef2aSThomas Huth /* addic addic.*/ 955fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 956fcf5ef2aSThomas Huth { 957fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 958fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 959fcf5ef2aSThomas Huth c, 0, 1, 0, compute_rc0); 960fcf5ef2aSThomas Huth tcg_temp_free(c); 961fcf5ef2aSThomas Huth } 962fcf5ef2aSThomas Huth 963fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 964fcf5ef2aSThomas Huth { 965fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 966fcf5ef2aSThomas Huth } 967fcf5ef2aSThomas Huth 968fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 969fcf5ef2aSThomas Huth { 970fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 971fcf5ef2aSThomas Huth } 972fcf5ef2aSThomas Huth 973fcf5ef2aSThomas Huth /* addis */ 974fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 975fcf5ef2aSThomas Huth { 976fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 977fcf5ef2aSThomas Huth 978fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 979fcf5ef2aSThomas Huth /* lis case */ 980fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 981fcf5ef2aSThomas Huth } else { 982fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 983fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 984fcf5ef2aSThomas Huth } 985fcf5ef2aSThomas Huth } 986fcf5ef2aSThomas Huth 987fcf5ef2aSThomas Huth /* addpcis */ 988fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 989fcf5ef2aSThomas Huth { 990fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 991fcf5ef2aSThomas Huth 992fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16)); 993fcf5ef2aSThomas Huth } 994fcf5ef2aSThomas Huth 995fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 996fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 997fcf5ef2aSThomas Huth { 998fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 999fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1000fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1001fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1002fcf5ef2aSThomas Huth 1003fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1004fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1005fcf5ef2aSThomas Huth if (sign) { 1006fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1007fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1008fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1009fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1010fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1011fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1012fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1013fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1014fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1015fcf5ef2aSThomas Huth } else { 1016fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1017fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1018fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1019fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1020fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1021fcf5ef2aSThomas Huth } 1022fcf5ef2aSThomas Huth if (compute_ov) { 1023fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1024fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1025fcf5ef2aSThomas Huth } 1026fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1027fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1028fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1029fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1030fcf5ef2aSThomas Huth 1031fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1032fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1033fcf5ef2aSThomas Huth } 1034fcf5ef2aSThomas Huth /* Div functions */ 1035fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1036fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1037fcf5ef2aSThomas Huth { \ 1038fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1039fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1040fcf5ef2aSThomas Huth sign, compute_ov); \ 1041fcf5ef2aSThomas Huth } 1042fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1043fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1044fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1045fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1046fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1047fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1048fcf5ef2aSThomas Huth 1049fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1050fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1051fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1052fcf5ef2aSThomas Huth { \ 1053fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1054fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1055fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1056fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1057fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1058fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1059fcf5ef2aSThomas Huth } \ 1060fcf5ef2aSThomas Huth } 1061fcf5ef2aSThomas Huth 1062fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1063fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1064fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1065fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1066fcf5ef2aSThomas Huth 1067fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1068fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1069fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1070fcf5ef2aSThomas Huth { 1071fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1072fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1073fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1074fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1075fcf5ef2aSThomas Huth 1076fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1077fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1078fcf5ef2aSThomas Huth if (sign) { 1079fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1080fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1081fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1082fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1083fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1084fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1085fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1086fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1087fcf5ef2aSThomas Huth } else { 1088fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1089fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1090fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1091fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1092fcf5ef2aSThomas Huth } 1093fcf5ef2aSThomas Huth if (compute_ov) { 1094fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1095fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1096fcf5ef2aSThomas Huth } 1097fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1098fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1099fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1100fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1101fcf5ef2aSThomas Huth 1102fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1103fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1104fcf5ef2aSThomas Huth } 1105fcf5ef2aSThomas Huth 1106fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1107fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1108fcf5ef2aSThomas Huth { \ 1109fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1110fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1111fcf5ef2aSThomas Huth sign, compute_ov); \ 1112fcf5ef2aSThomas Huth } 1113fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1114fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1115fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1116fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1117fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1118fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1119fcf5ef2aSThomas Huth 1120fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1121fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1122fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1123fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1124fcf5ef2aSThomas Huth #endif 1125fcf5ef2aSThomas Huth 1126fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1127fcf5ef2aSThomas Huth TCGv arg2, int sign) 1128fcf5ef2aSThomas Huth { 1129fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1130fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1131fcf5ef2aSThomas Huth 1132fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1133fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1134fcf5ef2aSThomas Huth if (sign) { 1135fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1136fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1137fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1138fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1139fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1140fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1141fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1142fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1143fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1144fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1145fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1146fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1147fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1148fcf5ef2aSThomas Huth } else { 1149fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1150fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1151fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1152fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1153fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1154fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1155fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1156fcf5ef2aSThomas Huth } 1157fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1158fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1159fcf5ef2aSThomas Huth } 1160fcf5ef2aSThomas Huth 1161fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1162fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1163fcf5ef2aSThomas Huth { \ 1164fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1165fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1166fcf5ef2aSThomas Huth sign); \ 1167fcf5ef2aSThomas Huth } 1168fcf5ef2aSThomas Huth 1169fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1170fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1171fcf5ef2aSThomas Huth 1172fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1173fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1174fcf5ef2aSThomas Huth TCGv arg2, int sign) 1175fcf5ef2aSThomas Huth { 1176fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1177fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1178fcf5ef2aSThomas Huth 1179fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1180fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1181fcf5ef2aSThomas Huth if (sign) { 1182fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1183fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1184fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1185fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1186fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1187fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1188fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1189fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1190fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1191fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1192fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1193fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1194fcf5ef2aSThomas Huth } else { 1195fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1196fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1197fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1198fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1199fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1200fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1201fcf5ef2aSThomas Huth } 1202fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1203fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1204fcf5ef2aSThomas Huth } 1205fcf5ef2aSThomas Huth 1206fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1207fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1208fcf5ef2aSThomas Huth { \ 1209fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1210fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1211fcf5ef2aSThomas Huth sign); \ 1212fcf5ef2aSThomas Huth } 1213fcf5ef2aSThomas Huth 1214fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1215fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1216fcf5ef2aSThomas Huth #endif 1217fcf5ef2aSThomas Huth 1218fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1219fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1220fcf5ef2aSThomas Huth { 1221fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1222fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1223fcf5ef2aSThomas Huth 1224fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1225fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1226fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1227fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1228fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1229fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1230fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1231fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1232fcf5ef2aSThomas Huth } 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1235fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1236fcf5ef2aSThomas Huth { 1237fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1238fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1239fcf5ef2aSThomas Huth 1240fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1241fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1242fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1243fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1244fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1245fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1246fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1247fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1248fcf5ef2aSThomas Huth } 1249fcf5ef2aSThomas Huth 1250fcf5ef2aSThomas Huth /* mullw mullw. */ 1251fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1252fcf5ef2aSThomas Huth { 1253fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1254fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1255fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1256fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1257fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1258fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1259fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1260fcf5ef2aSThomas Huth tcg_temp_free(t0); 1261fcf5ef2aSThomas Huth tcg_temp_free(t1); 1262fcf5ef2aSThomas Huth #else 1263fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1264fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1265fcf5ef2aSThomas Huth #endif 1266fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1267fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1268fcf5ef2aSThomas Huth } 1269fcf5ef2aSThomas Huth 1270fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1271fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1272fcf5ef2aSThomas Huth { 1273fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1274fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1275fcf5ef2aSThomas Huth 1276fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1277fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1278fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1279fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1280fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1281fcf5ef2aSThomas Huth #else 1282fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1283fcf5ef2aSThomas Huth #endif 1284fcf5ef2aSThomas Huth 1285fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1286fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1287fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 1288*61aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 1289*61aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1290*61aa9a69SNikunj A Dadhania } 1291fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1292fcf5ef2aSThomas Huth 1293fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1294fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1295fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1296fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1297fcf5ef2aSThomas Huth } 1298fcf5ef2aSThomas Huth 1299fcf5ef2aSThomas Huth /* mulli */ 1300fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1301fcf5ef2aSThomas Huth { 1302fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1303fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1304fcf5ef2aSThomas Huth } 1305fcf5ef2aSThomas Huth 1306fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1307fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1308fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1309fcf5ef2aSThomas Huth { 1310fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1311fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1312fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1313fcf5ef2aSThomas Huth tcg_temp_free(lo); 1314fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1315fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1316fcf5ef2aSThomas Huth } 1317fcf5ef2aSThomas Huth } 1318fcf5ef2aSThomas Huth 1319fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1320fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1321fcf5ef2aSThomas Huth { 1322fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1323fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1324fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1325fcf5ef2aSThomas Huth tcg_temp_free(lo); 1326fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1327fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1328fcf5ef2aSThomas Huth } 1329fcf5ef2aSThomas Huth } 1330fcf5ef2aSThomas Huth 1331fcf5ef2aSThomas Huth /* mulld mulld. */ 1332fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1333fcf5ef2aSThomas Huth { 1334fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1335fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1336fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1337fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1338fcf5ef2aSThomas Huth } 1339fcf5ef2aSThomas Huth 1340fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1341fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1342fcf5ef2aSThomas Huth { 1343fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1344fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1345fcf5ef2aSThomas Huth 1346fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1347fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1348fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1349fcf5ef2aSThomas Huth 1350fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1351fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1352*61aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 1353*61aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1354*61aa9a69SNikunj A Dadhania } 1355fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1356fcf5ef2aSThomas Huth 1357fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1358fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1359fcf5ef2aSThomas Huth 1360fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1361fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1362fcf5ef2aSThomas Huth } 1363fcf5ef2aSThomas Huth } 1364fcf5ef2aSThomas Huth #endif 1365fcf5ef2aSThomas Huth 1366fcf5ef2aSThomas Huth /* Common subf function */ 1367fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1368fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1369fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1370fcf5ef2aSThomas Huth { 1371fcf5ef2aSThomas Huth TCGv t0 = ret; 1372fcf5ef2aSThomas Huth 1373fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1374fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1375fcf5ef2aSThomas Huth } 1376fcf5ef2aSThomas Huth 1377fcf5ef2aSThomas Huth if (compute_ca) { 1378fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1379fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1380fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 1381fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 1382fcf5ef2aSThomas Huth carry into bit 32. */ 1383fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1384fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1385fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1386fcf5ef2aSThomas Huth if (add_ca) { 1387fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1388fcf5ef2aSThomas Huth } else { 1389fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1390fcf5ef2aSThomas Huth } 1391fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1392fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1393fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1394fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1395fcf5ef2aSThomas Huth tcg_temp_free(t1); 1396fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ 1397fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); 139833903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 139933903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 140033903d0aSNikunj A Dadhania } 1401fcf5ef2aSThomas Huth } else if (add_ca) { 1402fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1403fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1404fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1405fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1406fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 140733903d0aSNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); 1408fcf5ef2aSThomas Huth tcg_temp_free(zero); 1409fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1410fcf5ef2aSThomas Huth } else { 1411fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1412fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 141333903d0aSNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); 1414fcf5ef2aSThomas Huth } 1415fcf5ef2aSThomas Huth } else if (add_ca) { 1416fcf5ef2aSThomas Huth /* Since we're ignoring carry-out, we can simplify the 1417fcf5ef2aSThomas Huth standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1418fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1419fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1420fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1421fcf5ef2aSThomas Huth } else { 1422fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1423fcf5ef2aSThomas Huth } 1424fcf5ef2aSThomas Huth 1425fcf5ef2aSThomas Huth if (compute_ov) { 1426fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1427fcf5ef2aSThomas Huth } 1428fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1429fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1430fcf5ef2aSThomas Huth } 1431fcf5ef2aSThomas Huth 1432fcf5ef2aSThomas Huth if (!TCGV_EQUAL(t0, ret)) { 1433fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1434fcf5ef2aSThomas Huth tcg_temp_free(t0); 1435fcf5ef2aSThomas Huth } 1436fcf5ef2aSThomas Huth } 1437fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1438fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1439fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1440fcf5ef2aSThomas Huth { \ 1441fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1442fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1443fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1444fcf5ef2aSThomas Huth } 1445fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1446fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1447fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1448fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1449fcf5ef2aSThomas Huth { \ 1450fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1451fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1452fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1453fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1454fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1455fcf5ef2aSThomas Huth } 1456fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1457fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1458fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1459fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1460fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1461fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1462fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1463fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1464fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1465fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1466fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1467fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1468fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1469fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1470fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1471fcf5ef2aSThomas Huth 1472fcf5ef2aSThomas Huth /* subfic */ 1473fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1474fcf5ef2aSThomas Huth { 1475fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1476fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1477fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1478fcf5ef2aSThomas Huth tcg_temp_free(c); 1479fcf5ef2aSThomas Huth } 1480fcf5ef2aSThomas Huth 1481fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1482fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1483fcf5ef2aSThomas Huth { 1484fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1485fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1486fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1487fcf5ef2aSThomas Huth tcg_temp_free(zero); 1488fcf5ef2aSThomas Huth } 1489fcf5ef2aSThomas Huth 1490fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1491fcf5ef2aSThomas Huth { 14921480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 14931480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 14941480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 14951480d71cSNikunj A Dadhania } 1496fcf5ef2aSThomas Huth } 1497fcf5ef2aSThomas Huth 1498fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1499fcf5ef2aSThomas Huth { 1500fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1501fcf5ef2aSThomas Huth } 1502fcf5ef2aSThomas Huth 1503fcf5ef2aSThomas Huth /*** Integer logical ***/ 1504fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1505fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1506fcf5ef2aSThomas Huth { \ 1507fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1508fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1509fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1510fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1511fcf5ef2aSThomas Huth } 1512fcf5ef2aSThomas Huth 1513fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1514fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1515fcf5ef2aSThomas Huth { \ 1516fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1517fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1518fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1519fcf5ef2aSThomas Huth } 1520fcf5ef2aSThomas Huth 1521fcf5ef2aSThomas Huth /* and & and. */ 1522fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1523fcf5ef2aSThomas Huth /* andc & andc. */ 1524fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1525fcf5ef2aSThomas Huth 1526fcf5ef2aSThomas Huth /* andi. */ 1527fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1528fcf5ef2aSThomas Huth { 1529fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1530fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1531fcf5ef2aSThomas Huth } 1532fcf5ef2aSThomas Huth 1533fcf5ef2aSThomas Huth /* andis. */ 1534fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1535fcf5ef2aSThomas Huth { 1536fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1537fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1538fcf5ef2aSThomas Huth } 1539fcf5ef2aSThomas Huth 1540fcf5ef2aSThomas Huth /* cntlzw */ 1541fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1542fcf5ef2aSThomas Huth { 15439b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15449b8514e5SRichard Henderson 15459b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15469b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15479b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15489b8514e5SRichard Henderson tcg_temp_free_i32(t); 15499b8514e5SRichard Henderson 1550fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1551fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1552fcf5ef2aSThomas Huth } 1553fcf5ef2aSThomas Huth 1554fcf5ef2aSThomas Huth /* cnttzw */ 1555fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1556fcf5ef2aSThomas Huth { 15579b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15589b8514e5SRichard Henderson 15599b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15609b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15619b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15629b8514e5SRichard Henderson tcg_temp_free_i32(t); 15639b8514e5SRichard Henderson 1564fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1565fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1566fcf5ef2aSThomas Huth } 1567fcf5ef2aSThomas Huth } 1568fcf5ef2aSThomas Huth 1569fcf5ef2aSThomas Huth /* eqv & eqv. */ 1570fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1571fcf5ef2aSThomas Huth /* extsb & extsb. */ 1572fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1573fcf5ef2aSThomas Huth /* extsh & extsh. */ 1574fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1575fcf5ef2aSThomas Huth /* nand & nand. */ 1576fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1577fcf5ef2aSThomas Huth /* nor & nor. */ 1578fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1579fcf5ef2aSThomas Huth 1580fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1581fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1582fcf5ef2aSThomas Huth { 1583fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1584fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1585fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1586fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1587fcf5ef2aSThomas Huth 1588fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1589fcf5ef2aSThomas Huth gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 1590fcf5ef2aSThomas Huth } 1591fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1592fcf5ef2aSThomas Huth 1593fcf5ef2aSThomas Huth /* or & or. */ 1594fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1595fcf5ef2aSThomas Huth { 1596fcf5ef2aSThomas Huth int rs, ra, rb; 1597fcf5ef2aSThomas Huth 1598fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1599fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1600fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1601fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1602fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1603fcf5ef2aSThomas Huth if (rs != rb) 1604fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1605fcf5ef2aSThomas Huth else 1606fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1607fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1608fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1609fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1610fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1611fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1612fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1613fcf5ef2aSThomas Huth int prio = 0; 1614fcf5ef2aSThomas Huth 1615fcf5ef2aSThomas Huth switch (rs) { 1616fcf5ef2aSThomas Huth case 1: 1617fcf5ef2aSThomas Huth /* Set process priority to low */ 1618fcf5ef2aSThomas Huth prio = 2; 1619fcf5ef2aSThomas Huth break; 1620fcf5ef2aSThomas Huth case 6: 1621fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1622fcf5ef2aSThomas Huth prio = 3; 1623fcf5ef2aSThomas Huth break; 1624fcf5ef2aSThomas Huth case 2: 1625fcf5ef2aSThomas Huth /* Set process priority to normal */ 1626fcf5ef2aSThomas Huth prio = 4; 1627fcf5ef2aSThomas Huth break; 1628fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1629fcf5ef2aSThomas Huth case 31: 1630fcf5ef2aSThomas Huth if (!ctx->pr) { 1631fcf5ef2aSThomas Huth /* Set process priority to very low */ 1632fcf5ef2aSThomas Huth prio = 1; 1633fcf5ef2aSThomas Huth } 1634fcf5ef2aSThomas Huth break; 1635fcf5ef2aSThomas Huth case 5: 1636fcf5ef2aSThomas Huth if (!ctx->pr) { 1637fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1638fcf5ef2aSThomas Huth prio = 5; 1639fcf5ef2aSThomas Huth } 1640fcf5ef2aSThomas Huth break; 1641fcf5ef2aSThomas Huth case 3: 1642fcf5ef2aSThomas Huth if (!ctx->pr) { 1643fcf5ef2aSThomas Huth /* Set process priority to high */ 1644fcf5ef2aSThomas Huth prio = 6; 1645fcf5ef2aSThomas Huth } 1646fcf5ef2aSThomas Huth break; 1647fcf5ef2aSThomas Huth case 7: 1648fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1649fcf5ef2aSThomas Huth /* Set process priority to very high */ 1650fcf5ef2aSThomas Huth prio = 7; 1651fcf5ef2aSThomas Huth } 1652fcf5ef2aSThomas Huth break; 1653fcf5ef2aSThomas Huth #endif 1654fcf5ef2aSThomas Huth default: 1655fcf5ef2aSThomas Huth break; 1656fcf5ef2aSThomas Huth } 1657fcf5ef2aSThomas Huth if (prio) { 1658fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1659fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1660fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1661fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1662fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1663fcf5ef2aSThomas Huth tcg_temp_free(t0); 1664fcf5ef2aSThomas Huth } 1665fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1666fcf5ef2aSThomas Huth /* Pause out of TCG otherwise spin loops with smt_low eat too much 1667fcf5ef2aSThomas Huth * CPU and the kernel hangs. This applies to all encodings other 1668fcf5ef2aSThomas Huth * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1669fcf5ef2aSThomas Huth * and all currently undefined. 1670fcf5ef2aSThomas Huth */ 1671fcf5ef2aSThomas Huth gen_pause(ctx); 1672fcf5ef2aSThomas Huth #endif 1673fcf5ef2aSThomas Huth #endif 1674fcf5ef2aSThomas Huth } 1675fcf5ef2aSThomas Huth } 1676fcf5ef2aSThomas Huth /* orc & orc. */ 1677fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1678fcf5ef2aSThomas Huth 1679fcf5ef2aSThomas Huth /* xor & xor. */ 1680fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1681fcf5ef2aSThomas Huth { 1682fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1683fcf5ef2aSThomas Huth if (rS(ctx->opcode) != rB(ctx->opcode)) 1684fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1685fcf5ef2aSThomas Huth else 1686fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1687fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1688fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1689fcf5ef2aSThomas Huth } 1690fcf5ef2aSThomas Huth 1691fcf5ef2aSThomas Huth /* ori */ 1692fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1693fcf5ef2aSThomas Huth { 1694fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1695fcf5ef2aSThomas Huth 1696fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1697fcf5ef2aSThomas Huth return; 1698fcf5ef2aSThomas Huth } 1699fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1700fcf5ef2aSThomas Huth } 1701fcf5ef2aSThomas Huth 1702fcf5ef2aSThomas Huth /* oris */ 1703fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1704fcf5ef2aSThomas Huth { 1705fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1706fcf5ef2aSThomas Huth 1707fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1708fcf5ef2aSThomas Huth /* NOP */ 1709fcf5ef2aSThomas Huth return; 1710fcf5ef2aSThomas Huth } 1711fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1712fcf5ef2aSThomas Huth } 1713fcf5ef2aSThomas Huth 1714fcf5ef2aSThomas Huth /* xori */ 1715fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1716fcf5ef2aSThomas Huth { 1717fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1718fcf5ef2aSThomas Huth 1719fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1720fcf5ef2aSThomas Huth /* NOP */ 1721fcf5ef2aSThomas Huth return; 1722fcf5ef2aSThomas Huth } 1723fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1724fcf5ef2aSThomas Huth } 1725fcf5ef2aSThomas Huth 1726fcf5ef2aSThomas Huth /* xoris */ 1727fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1728fcf5ef2aSThomas Huth { 1729fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1730fcf5ef2aSThomas Huth 1731fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1732fcf5ef2aSThomas Huth /* NOP */ 1733fcf5ef2aSThomas Huth return; 1734fcf5ef2aSThomas Huth } 1735fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1736fcf5ef2aSThomas Huth } 1737fcf5ef2aSThomas Huth 1738fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1739fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1740fcf5ef2aSThomas Huth { 1741fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1742fcf5ef2aSThomas Huth } 1743fcf5ef2aSThomas Huth 1744fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1745fcf5ef2aSThomas Huth { 174679770002SRichard Henderson #if defined(TARGET_PPC64) 1747fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 174879770002SRichard Henderson #else 174979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 175079770002SRichard Henderson #endif 1751fcf5ef2aSThomas Huth } 1752fcf5ef2aSThomas Huth 1753fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1754fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1755fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1756fcf5ef2aSThomas Huth { 175779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1758fcf5ef2aSThomas Huth } 1759fcf5ef2aSThomas Huth #endif 1760fcf5ef2aSThomas Huth 1761fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1762fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1763fcf5ef2aSThomas Huth { 1764fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1765fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1766fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1767fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1768fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1769fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1770fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1771fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1772fcf5ef2aSThomas Huth tcg_temp_free(t0); 1773fcf5ef2aSThomas Huth } 1774fcf5ef2aSThomas Huth 1775fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1776fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1777fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1778fcf5ef2aSThomas Huth { 1779fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1780fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1781fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1782fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1783fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1784fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1785fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1786fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1787fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1788fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1789fcf5ef2aSThomas Huth tcg_temp_free(t0); 1790fcf5ef2aSThomas Huth } 1791fcf5ef2aSThomas Huth #endif 1792fcf5ef2aSThomas Huth 1793fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1794fcf5ef2aSThomas Huth /* bpermd */ 1795fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1796fcf5ef2aSThomas Huth { 1797fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1798fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1799fcf5ef2aSThomas Huth } 1800fcf5ef2aSThomas Huth #endif 1801fcf5ef2aSThomas Huth 1802fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1803fcf5ef2aSThomas Huth /* extsw & extsw. */ 1804fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1805fcf5ef2aSThomas Huth 1806fcf5ef2aSThomas Huth /* cntlzd */ 1807fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1808fcf5ef2aSThomas Huth { 18099b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1810fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1811fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1812fcf5ef2aSThomas Huth } 1813fcf5ef2aSThomas Huth 1814fcf5ef2aSThomas Huth /* cnttzd */ 1815fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1816fcf5ef2aSThomas Huth { 18179b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1818fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1819fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1820fcf5ef2aSThomas Huth } 1821fcf5ef2aSThomas Huth } 1822fcf5ef2aSThomas Huth 1823fcf5ef2aSThomas Huth /* darn */ 1824fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1825fcf5ef2aSThomas Huth { 1826fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1827fcf5ef2aSThomas Huth 1828fcf5ef2aSThomas Huth if (l == 0) { 1829fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1830fcf5ef2aSThomas Huth } else if (l <= 2) { 1831fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1832fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1833fcf5ef2aSThomas Huth } else { 1834fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1835fcf5ef2aSThomas Huth } 1836fcf5ef2aSThomas Huth } 1837fcf5ef2aSThomas Huth #endif 1838fcf5ef2aSThomas Huth 1839fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1840fcf5ef2aSThomas Huth 1841fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1842fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1843fcf5ef2aSThomas Huth { 1844fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1845fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1846fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1847fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1848fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1849fcf5ef2aSThomas Huth 1850fcf5ef2aSThomas Huth if (sh == (31-me) && mb <= me) { 1851fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1852fcf5ef2aSThomas Huth } else { 1853fcf5ef2aSThomas Huth target_ulong mask; 1854fcf5ef2aSThomas Huth TCGv t1; 1855fcf5ef2aSThomas Huth 1856fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1857fcf5ef2aSThomas Huth mb += 32; 1858fcf5ef2aSThomas Huth me += 32; 1859fcf5ef2aSThomas Huth #endif 1860fcf5ef2aSThomas Huth mask = MASK(mb, me); 1861fcf5ef2aSThomas Huth 1862fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1863fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1864fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1865fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1866fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1867fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1868fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1869fcf5ef2aSThomas Huth } else { 1870fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1871fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1872fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1873fcf5ef2aSThomas Huth #else 1874fcf5ef2aSThomas Huth g_assert_not_reached(); 1875fcf5ef2aSThomas Huth #endif 1876fcf5ef2aSThomas Huth } 1877fcf5ef2aSThomas Huth 1878fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1879fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1880fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1881fcf5ef2aSThomas Huth tcg_temp_free(t1); 1882fcf5ef2aSThomas Huth } 1883fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1884fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1885fcf5ef2aSThomas Huth } 1886fcf5ef2aSThomas Huth } 1887fcf5ef2aSThomas Huth 1888fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1889fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1890fcf5ef2aSThomas Huth { 1891fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1892fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 18937b4d326fSRichard Henderson int sh = SH(ctx->opcode); 18947b4d326fSRichard Henderson int mb = MB(ctx->opcode); 18957b4d326fSRichard Henderson int me = ME(ctx->opcode); 18967b4d326fSRichard Henderson int len = me - mb + 1; 18977b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1898fcf5ef2aSThomas Huth 18997b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 19007b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 19017b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 19027b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1903fcf5ef2aSThomas Huth } else { 1904fcf5ef2aSThomas Huth target_ulong mask; 1905fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1906fcf5ef2aSThomas Huth mb += 32; 1907fcf5ef2aSThomas Huth me += 32; 1908fcf5ef2aSThomas Huth #endif 1909fcf5ef2aSThomas Huth mask = MASK(mb, me); 19107b4d326fSRichard Henderson if (sh == 0) { 19117b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 19127b4d326fSRichard Henderson } else if (mask <= 0xffffffffu) { 1913fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1914fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1915fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1916fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1917fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1918fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1919fcf5ef2aSThomas Huth } else { 1920fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1921fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1922fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1923fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1924fcf5ef2aSThomas Huth #else 1925fcf5ef2aSThomas Huth g_assert_not_reached(); 1926fcf5ef2aSThomas Huth #endif 1927fcf5ef2aSThomas Huth } 1928fcf5ef2aSThomas Huth } 1929fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1930fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1931fcf5ef2aSThomas Huth } 1932fcf5ef2aSThomas Huth } 1933fcf5ef2aSThomas Huth 1934fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1935fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1936fcf5ef2aSThomas Huth { 1937fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1938fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1939fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1940fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1941fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1942fcf5ef2aSThomas Huth target_ulong mask; 1943fcf5ef2aSThomas Huth 1944fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1945fcf5ef2aSThomas Huth mb += 32; 1946fcf5ef2aSThomas Huth me += 32; 1947fcf5ef2aSThomas Huth #endif 1948fcf5ef2aSThomas Huth mask = MASK(mb, me); 1949fcf5ef2aSThomas Huth 1950fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1951fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1952fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1953fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1954fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1955fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1956fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1957fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1958fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1959fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1960fcf5ef2aSThomas Huth } else { 1961fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1962fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1963fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1964fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1965fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1966fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1967fcf5ef2aSThomas Huth #else 1968fcf5ef2aSThomas Huth g_assert_not_reached(); 1969fcf5ef2aSThomas Huth #endif 1970fcf5ef2aSThomas Huth } 1971fcf5ef2aSThomas Huth 1972fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 1973fcf5ef2aSThomas Huth 1974fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1975fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1976fcf5ef2aSThomas Huth } 1977fcf5ef2aSThomas Huth } 1978fcf5ef2aSThomas Huth 1979fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1980fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 1981fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1982fcf5ef2aSThomas Huth { \ 1983fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 1984fcf5ef2aSThomas Huth } \ 1985fcf5ef2aSThomas Huth \ 1986fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1987fcf5ef2aSThomas Huth { \ 1988fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 1989fcf5ef2aSThomas Huth } 1990fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 1991fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1992fcf5ef2aSThomas Huth { \ 1993fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 1994fcf5ef2aSThomas Huth } \ 1995fcf5ef2aSThomas Huth \ 1996fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1997fcf5ef2aSThomas Huth { \ 1998fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 1999fcf5ef2aSThomas Huth } \ 2000fcf5ef2aSThomas Huth \ 2001fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2002fcf5ef2aSThomas Huth { \ 2003fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2004fcf5ef2aSThomas Huth } \ 2005fcf5ef2aSThomas Huth \ 2006fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2007fcf5ef2aSThomas Huth { \ 2008fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2009fcf5ef2aSThomas Huth } 2010fcf5ef2aSThomas Huth 2011fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2012fcf5ef2aSThomas Huth { 2013fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2014fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20157b4d326fSRichard Henderson int len = me - mb + 1; 20167b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2017fcf5ef2aSThomas Huth 20187b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20197b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20207b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20217b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2022fcf5ef2aSThomas Huth } else { 2023fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2024fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2025fcf5ef2aSThomas Huth } 2026fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2027fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2028fcf5ef2aSThomas Huth } 2029fcf5ef2aSThomas Huth } 2030fcf5ef2aSThomas Huth 2031fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2032fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2033fcf5ef2aSThomas Huth { 2034fcf5ef2aSThomas Huth uint32_t sh, mb; 2035fcf5ef2aSThomas Huth 2036fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2037fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2038fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2039fcf5ef2aSThomas Huth } 2040fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2041fcf5ef2aSThomas Huth 2042fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2043fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2044fcf5ef2aSThomas Huth { 2045fcf5ef2aSThomas Huth uint32_t sh, me; 2046fcf5ef2aSThomas Huth 2047fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2048fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2049fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2050fcf5ef2aSThomas Huth } 2051fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2052fcf5ef2aSThomas Huth 2053fcf5ef2aSThomas Huth /* rldic - rldic. */ 2054fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2055fcf5ef2aSThomas Huth { 2056fcf5ef2aSThomas Huth uint32_t sh, mb; 2057fcf5ef2aSThomas Huth 2058fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2059fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2060fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2061fcf5ef2aSThomas Huth } 2062fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2063fcf5ef2aSThomas Huth 2064fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2065fcf5ef2aSThomas Huth { 2066fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2067fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2068fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2069fcf5ef2aSThomas Huth TCGv t0; 2070fcf5ef2aSThomas Huth 2071fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2072fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2073fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2074fcf5ef2aSThomas Huth tcg_temp_free(t0); 2075fcf5ef2aSThomas Huth 2076fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2077fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2078fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2079fcf5ef2aSThomas Huth } 2080fcf5ef2aSThomas Huth } 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2083fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2084fcf5ef2aSThomas Huth { 2085fcf5ef2aSThomas Huth uint32_t mb; 2086fcf5ef2aSThomas Huth 2087fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2088fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2089fcf5ef2aSThomas Huth } 2090fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2091fcf5ef2aSThomas Huth 2092fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2093fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2094fcf5ef2aSThomas Huth { 2095fcf5ef2aSThomas Huth uint32_t me; 2096fcf5ef2aSThomas Huth 2097fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2098fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2099fcf5ef2aSThomas Huth } 2100fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2101fcf5ef2aSThomas Huth 2102fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2103fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2104fcf5ef2aSThomas Huth { 2105fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2106fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2107fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2108fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2109fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2110fcf5ef2aSThomas Huth 2111fcf5ef2aSThomas Huth if (mb <= me) { 2112fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2113fcf5ef2aSThomas Huth } else { 2114fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2115fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2116fcf5ef2aSThomas Huth 2117fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2118fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2119fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2120fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2121fcf5ef2aSThomas Huth tcg_temp_free(t1); 2122fcf5ef2aSThomas Huth } 2123fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2124fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2125fcf5ef2aSThomas Huth } 2126fcf5ef2aSThomas Huth } 2127fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2128fcf5ef2aSThomas Huth #endif 2129fcf5ef2aSThomas Huth 2130fcf5ef2aSThomas Huth /*** Integer shift ***/ 2131fcf5ef2aSThomas Huth 2132fcf5ef2aSThomas Huth /* slw & slw. */ 2133fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2134fcf5ef2aSThomas Huth { 2135fcf5ef2aSThomas Huth TCGv t0, t1; 2136fcf5ef2aSThomas Huth 2137fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2138fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2139fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2140fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2141fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2142fcf5ef2aSThomas Huth #else 2143fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2144fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2145fcf5ef2aSThomas Huth #endif 2146fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2147fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2148fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2149fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2150fcf5ef2aSThomas Huth tcg_temp_free(t1); 2151fcf5ef2aSThomas Huth tcg_temp_free(t0); 2152fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2153fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2154fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2155fcf5ef2aSThomas Huth } 2156fcf5ef2aSThomas Huth 2157fcf5ef2aSThomas Huth /* sraw & sraw. */ 2158fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2159fcf5ef2aSThomas Huth { 2160fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2161fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2162fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2163fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2164fcf5ef2aSThomas Huth } 2165fcf5ef2aSThomas Huth 2166fcf5ef2aSThomas Huth /* srawi & srawi. */ 2167fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2168fcf5ef2aSThomas Huth { 2169fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2170fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2171fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2172fcf5ef2aSThomas Huth if (sh == 0) { 2173fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2174fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2175fcf5ef2aSThomas Huth } else { 2176fcf5ef2aSThomas Huth TCGv t0; 2177fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2178fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2179fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2180fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2181fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2182fcf5ef2aSThomas Huth tcg_temp_free(t0); 2183fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2184fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2185fcf5ef2aSThomas Huth } 2186fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2187fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2188fcf5ef2aSThomas Huth } 2189fcf5ef2aSThomas Huth } 2190fcf5ef2aSThomas Huth 2191fcf5ef2aSThomas Huth /* srw & srw. */ 2192fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2193fcf5ef2aSThomas Huth { 2194fcf5ef2aSThomas Huth TCGv t0, t1; 2195fcf5ef2aSThomas Huth 2196fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2197fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2198fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2199fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2200fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2201fcf5ef2aSThomas Huth #else 2202fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2203fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2204fcf5ef2aSThomas Huth #endif 2205fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2206fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2207fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2208fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2209fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2210fcf5ef2aSThomas Huth tcg_temp_free(t1); 2211fcf5ef2aSThomas Huth tcg_temp_free(t0); 2212fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2213fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2214fcf5ef2aSThomas Huth } 2215fcf5ef2aSThomas Huth 2216fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2217fcf5ef2aSThomas Huth /* sld & sld. */ 2218fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2219fcf5ef2aSThomas Huth { 2220fcf5ef2aSThomas Huth TCGv t0, t1; 2221fcf5ef2aSThomas Huth 2222fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2223fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2224fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2225fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2226fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2227fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2228fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2229fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2230fcf5ef2aSThomas Huth tcg_temp_free(t1); 2231fcf5ef2aSThomas Huth tcg_temp_free(t0); 2232fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2233fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2234fcf5ef2aSThomas Huth } 2235fcf5ef2aSThomas Huth 2236fcf5ef2aSThomas Huth /* srad & srad. */ 2237fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2238fcf5ef2aSThomas Huth { 2239fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2240fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2241fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2242fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2243fcf5ef2aSThomas Huth } 2244fcf5ef2aSThomas Huth /* sradi & sradi. */ 2245fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2246fcf5ef2aSThomas Huth { 2247fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2248fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2249fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2250fcf5ef2aSThomas Huth if (sh == 0) { 2251fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2252fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2253fcf5ef2aSThomas Huth } else { 2254fcf5ef2aSThomas Huth TCGv t0; 2255fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2256fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2257fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2258fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2259fcf5ef2aSThomas Huth tcg_temp_free(t0); 2260fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2261fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2262fcf5ef2aSThomas Huth } 2263fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2264fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2265fcf5ef2aSThomas Huth } 2266fcf5ef2aSThomas Huth } 2267fcf5ef2aSThomas Huth 2268fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2269fcf5ef2aSThomas Huth { 2270fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2271fcf5ef2aSThomas Huth } 2272fcf5ef2aSThomas Huth 2273fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2274fcf5ef2aSThomas Huth { 2275fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2276fcf5ef2aSThomas Huth } 2277fcf5ef2aSThomas Huth 2278fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2279fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2280fcf5ef2aSThomas Huth { 2281fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2282fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2283fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2284fcf5ef2aSThomas Huth 2285fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2286fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2287fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2288fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2289fcf5ef2aSThomas Huth } 2290fcf5ef2aSThomas Huth } 2291fcf5ef2aSThomas Huth 2292fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2293fcf5ef2aSThomas Huth { 2294fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2295fcf5ef2aSThomas Huth } 2296fcf5ef2aSThomas Huth 2297fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2298fcf5ef2aSThomas Huth { 2299fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2300fcf5ef2aSThomas Huth } 2301fcf5ef2aSThomas Huth 2302fcf5ef2aSThomas Huth /* srd & srd. */ 2303fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2304fcf5ef2aSThomas Huth { 2305fcf5ef2aSThomas Huth TCGv t0, t1; 2306fcf5ef2aSThomas Huth 2307fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2308fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2309fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2310fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2311fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2312fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2313fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2314fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2315fcf5ef2aSThomas Huth tcg_temp_free(t1); 2316fcf5ef2aSThomas Huth tcg_temp_free(t0); 2317fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2318fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2319fcf5ef2aSThomas Huth } 2320fcf5ef2aSThomas Huth #endif 2321fcf5ef2aSThomas Huth 2322fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2323fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2324fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2325fcf5ef2aSThomas Huth target_long maskl) 2326fcf5ef2aSThomas Huth { 2327fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2328fcf5ef2aSThomas Huth 2329fcf5ef2aSThomas Huth simm &= ~maskl; 2330fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2331fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2332fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2333fcf5ef2aSThomas Huth } 2334fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2335fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2336fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2337fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2338fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2339fcf5ef2aSThomas Huth } 2340fcf5ef2aSThomas Huth } else { 2341fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2342fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2343fcf5ef2aSThomas Huth } else { 2344fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2345fcf5ef2aSThomas Huth } 2346fcf5ef2aSThomas Huth } 2347fcf5ef2aSThomas Huth } 2348fcf5ef2aSThomas Huth 2349fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2350fcf5ef2aSThomas Huth { 2351fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2352fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2353fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2354fcf5ef2aSThomas Huth } else { 2355fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2356fcf5ef2aSThomas Huth } 2357fcf5ef2aSThomas Huth } else { 2358fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2359fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2360fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2361fcf5ef2aSThomas Huth } 2362fcf5ef2aSThomas Huth } 2363fcf5ef2aSThomas Huth } 2364fcf5ef2aSThomas Huth 2365fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2366fcf5ef2aSThomas Huth { 2367fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2368fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2369fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2370fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2371fcf5ef2aSThomas Huth } else { 2372fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2373fcf5ef2aSThomas Huth } 2374fcf5ef2aSThomas Huth } 2375fcf5ef2aSThomas Huth 2376fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2377fcf5ef2aSThomas Huth target_long val) 2378fcf5ef2aSThomas Huth { 2379fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2380fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2381fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2382fcf5ef2aSThomas Huth } 2383fcf5ef2aSThomas Huth } 2384fcf5ef2aSThomas Huth 2385fcf5ef2aSThomas Huth static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) 2386fcf5ef2aSThomas Huth { 2387fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 2388fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2389fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2390fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, EA, mask); 2391fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 2392fcf5ef2aSThomas Huth t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); 2393fcf5ef2aSThomas Huth t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); 2394fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 2395fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t1, t2); 2396fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2397fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2398fcf5ef2aSThomas Huth gen_set_label(l1); 2399fcf5ef2aSThomas Huth tcg_temp_free(t0); 2400fcf5ef2aSThomas Huth } 2401fcf5ef2aSThomas Huth 2402fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2403fcf5ef2aSThomas Huth { 2404fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2405fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2406fcf5ef2aSThomas Huth } 2407fcf5ef2aSThomas Huth 2408fcf5ef2aSThomas Huth /*** Integer load ***/ 2409fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2410fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2411fcf5ef2aSThomas Huth 2412fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2413fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2414fcf5ef2aSThomas Huth TCGv val, \ 2415fcf5ef2aSThomas Huth TCGv addr) \ 2416fcf5ef2aSThomas Huth { \ 2417fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2418fcf5ef2aSThomas Huth } 2419fcf5ef2aSThomas Huth 2420fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2421fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2422fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2423fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2424fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2425fcf5ef2aSThomas Huth 2426fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2427fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2428fcf5ef2aSThomas Huth 2429fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2430fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2431fcf5ef2aSThomas Huth TCGv_i64 val, \ 2432fcf5ef2aSThomas Huth TCGv addr) \ 2433fcf5ef2aSThomas Huth { \ 2434fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2435fcf5ef2aSThomas Huth } 2436fcf5ef2aSThomas Huth 2437fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2438fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2439fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2440fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2441fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2442fcf5ef2aSThomas Huth 2443fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2444fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2445fcf5ef2aSThomas Huth #endif 2446fcf5ef2aSThomas Huth 2447fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2448fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2449fcf5ef2aSThomas Huth TCGv val, \ 2450fcf5ef2aSThomas Huth TCGv addr) \ 2451fcf5ef2aSThomas Huth { \ 2452fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2453fcf5ef2aSThomas Huth } 2454fcf5ef2aSThomas Huth 2455fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2456fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2457fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2458fcf5ef2aSThomas Huth 2459fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2460fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2461fcf5ef2aSThomas Huth 2462fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2463fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2464fcf5ef2aSThomas Huth TCGv_i64 val, \ 2465fcf5ef2aSThomas Huth TCGv addr) \ 2466fcf5ef2aSThomas Huth { \ 2467fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2468fcf5ef2aSThomas Huth } 2469fcf5ef2aSThomas Huth 2470fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2471fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2472fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2473fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2474fcf5ef2aSThomas Huth 2475fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2476fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2477fcf5ef2aSThomas Huth #endif 2478fcf5ef2aSThomas Huth 2479fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2480fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2481fcf5ef2aSThomas Huth { \ 2482fcf5ef2aSThomas Huth TCGv EA; \ 2483fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2484fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2485fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2486fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2487fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2488fcf5ef2aSThomas Huth } 2489fcf5ef2aSThomas Huth 2490fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2491fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2492fcf5ef2aSThomas Huth { \ 2493fcf5ef2aSThomas Huth TCGv EA; \ 2494fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2495fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2496fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2497fcf5ef2aSThomas Huth return; \ 2498fcf5ef2aSThomas Huth } \ 2499fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2500fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2501fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2502fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2503fcf5ef2aSThomas Huth else \ 2504fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2505fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2506fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2507fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2508fcf5ef2aSThomas Huth } 2509fcf5ef2aSThomas Huth 2510fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2511fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2512fcf5ef2aSThomas Huth { \ 2513fcf5ef2aSThomas Huth TCGv EA; \ 2514fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2515fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2516fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2517fcf5ef2aSThomas Huth return; \ 2518fcf5ef2aSThomas Huth } \ 2519fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2520fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2521fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2522fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2523fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2524fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2525fcf5ef2aSThomas Huth } 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2528fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2529fcf5ef2aSThomas Huth { \ 2530fcf5ef2aSThomas Huth TCGv EA; \ 2531fcf5ef2aSThomas Huth chk; \ 2532fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2533fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2534fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2535fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2536fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2537fcf5ef2aSThomas Huth } 2538fcf5ef2aSThomas Huth 2539fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2540fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2541fcf5ef2aSThomas Huth 2542fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2543fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2544fcf5ef2aSThomas Huth 2545fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2546fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2547fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2548fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2549fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2550fcf5ef2aSThomas Huth 2551fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2552fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2553fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2554fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2555fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2556fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2557fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2558fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2559fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2560fcf5ef2aSThomas Huth /* lwaux */ 2561fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2562fcf5ef2aSThomas Huth /* lwax */ 2563fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2564fcf5ef2aSThomas Huth /* ldux */ 2565fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2566fcf5ef2aSThomas Huth /* ldx */ 2567fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2568fcf5ef2aSThomas Huth 2569fcf5ef2aSThomas Huth /* CI load/store variants */ 2570fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2571fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2572fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2573fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2574fcf5ef2aSThomas Huth 2575fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2576fcf5ef2aSThomas Huth { 2577fcf5ef2aSThomas Huth TCGv EA; 2578fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2579fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2580fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2581fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2582fcf5ef2aSThomas Huth return; 2583fcf5ef2aSThomas Huth } 2584fcf5ef2aSThomas Huth } 2585fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2586fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2587fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2588fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2589fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2590fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2591fcf5ef2aSThomas Huth } else { 2592fcf5ef2aSThomas Huth /* ld - ldu */ 2593fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2594fcf5ef2aSThomas Huth } 2595fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2596fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2597fcf5ef2aSThomas Huth tcg_temp_free(EA); 2598fcf5ef2aSThomas Huth } 2599fcf5ef2aSThomas Huth 2600fcf5ef2aSThomas Huth /* lq */ 2601fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2602fcf5ef2aSThomas Huth { 2603fcf5ef2aSThomas Huth int ra, rd; 2604fcf5ef2aSThomas Huth TCGv EA; 2605fcf5ef2aSThomas Huth 2606fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2607fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2608fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2609fcf5ef2aSThomas Huth 2610fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2611fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2612fcf5ef2aSThomas Huth return; 2613fcf5ef2aSThomas Huth } 2614fcf5ef2aSThomas Huth 2615fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2616fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2617fcf5ef2aSThomas Huth return; 2618fcf5ef2aSThomas Huth } 2619fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2620fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2621fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2622fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2623fcf5ef2aSThomas Huth return; 2624fcf5ef2aSThomas Huth } 2625fcf5ef2aSThomas Huth 2626fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2627fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2628fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2629fcf5ef2aSThomas Huth 2630fcf5ef2aSThomas Huth /* We only need to swap high and low halves. gen_qemu_ld64_i64 does 2631fcf5ef2aSThomas Huth necessary 64-bit byteswap already. */ 2632fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 2633fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2634fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2635fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2636fcf5ef2aSThomas Huth } else { 2637fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2638fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2639fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2640fcf5ef2aSThomas Huth } 2641fcf5ef2aSThomas Huth tcg_temp_free(EA); 2642fcf5ef2aSThomas Huth } 2643fcf5ef2aSThomas Huth #endif 2644fcf5ef2aSThomas Huth 2645fcf5ef2aSThomas Huth /*** Integer store ***/ 2646fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2647fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2648fcf5ef2aSThomas Huth { \ 2649fcf5ef2aSThomas Huth TCGv EA; \ 2650fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2651fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2652fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2653fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2654fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2655fcf5ef2aSThomas Huth } 2656fcf5ef2aSThomas Huth 2657fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2658fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2659fcf5ef2aSThomas Huth { \ 2660fcf5ef2aSThomas Huth TCGv EA; \ 2661fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2662fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2663fcf5ef2aSThomas Huth return; \ 2664fcf5ef2aSThomas Huth } \ 2665fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2666fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2667fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2668fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2669fcf5ef2aSThomas Huth else \ 2670fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2671fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2672fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2673fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2674fcf5ef2aSThomas Huth } 2675fcf5ef2aSThomas Huth 2676fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2677fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2678fcf5ef2aSThomas Huth { \ 2679fcf5ef2aSThomas Huth TCGv EA; \ 2680fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2681fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2682fcf5ef2aSThomas Huth return; \ 2683fcf5ef2aSThomas Huth } \ 2684fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2685fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2686fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2687fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2688fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2689fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2690fcf5ef2aSThomas Huth } 2691fcf5ef2aSThomas Huth 2692fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2693fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2694fcf5ef2aSThomas Huth { \ 2695fcf5ef2aSThomas Huth TCGv EA; \ 2696fcf5ef2aSThomas Huth chk; \ 2697fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2698fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2699fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2700fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2701fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2702fcf5ef2aSThomas Huth } 2703fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2704fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2705fcf5ef2aSThomas Huth 2706fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2707fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2708fcf5ef2aSThomas Huth 2709fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2710fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2711fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2712fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2713fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2714fcf5ef2aSThomas Huth 2715fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2716fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2717fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2718fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2719fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2720fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2721fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2722fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2723fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2724fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2725fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2726fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2727fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2728fcf5ef2aSThomas Huth 2729fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2730fcf5ef2aSThomas Huth { 2731fcf5ef2aSThomas Huth int rs; 2732fcf5ef2aSThomas Huth TCGv EA; 2733fcf5ef2aSThomas Huth 2734fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2735fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2736fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2737fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2738fcf5ef2aSThomas Huth 2739fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2740fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2741fcf5ef2aSThomas Huth } 2742fcf5ef2aSThomas Huth 2743fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2744fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2745fcf5ef2aSThomas Huth return; 2746fcf5ef2aSThomas Huth } 2747fcf5ef2aSThomas Huth 2748fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2749fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2750fcf5ef2aSThomas Huth return; 2751fcf5ef2aSThomas Huth } 2752fcf5ef2aSThomas Huth 2753fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2754fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2755fcf5ef2aSThomas Huth return; 2756fcf5ef2aSThomas Huth } 2757fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2758fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2759fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2760fcf5ef2aSThomas Huth 2761fcf5ef2aSThomas Huth /* We only need to swap high and low halves. gen_qemu_st64_i64 does 2762fcf5ef2aSThomas Huth necessary 64-bit byteswap already. */ 2763fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 2764fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2765fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2766fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2767fcf5ef2aSThomas Huth } else { 2768fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2769fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2770fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2771fcf5ef2aSThomas Huth } 2772fcf5ef2aSThomas Huth tcg_temp_free(EA); 2773fcf5ef2aSThomas Huth } else { 2774fcf5ef2aSThomas Huth /* std / stdu*/ 2775fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2776fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2777fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2778fcf5ef2aSThomas Huth return; 2779fcf5ef2aSThomas Huth } 2780fcf5ef2aSThomas Huth } 2781fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2782fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2783fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2784fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2785fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2786fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2787fcf5ef2aSThomas Huth tcg_temp_free(EA); 2788fcf5ef2aSThomas Huth } 2789fcf5ef2aSThomas Huth } 2790fcf5ef2aSThomas Huth #endif 2791fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2792fcf5ef2aSThomas Huth 2793fcf5ef2aSThomas Huth /* lhbrx */ 2794fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2795fcf5ef2aSThomas Huth 2796fcf5ef2aSThomas Huth /* lwbrx */ 2797fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2798fcf5ef2aSThomas Huth 2799fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2800fcf5ef2aSThomas Huth /* ldbrx */ 2801fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2802fcf5ef2aSThomas Huth /* stdbrx */ 2803fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2804fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2805fcf5ef2aSThomas Huth 2806fcf5ef2aSThomas Huth /* sthbrx */ 2807fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2808fcf5ef2aSThomas Huth /* stwbrx */ 2809fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2810fcf5ef2aSThomas Huth 2811fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2812fcf5ef2aSThomas Huth 2813fcf5ef2aSThomas Huth /* lmw */ 2814fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2815fcf5ef2aSThomas Huth { 2816fcf5ef2aSThomas Huth TCGv t0; 2817fcf5ef2aSThomas Huth TCGv_i32 t1; 2818fcf5ef2aSThomas Huth 2819fcf5ef2aSThomas Huth if (ctx->le_mode) { 2820fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2821fcf5ef2aSThomas Huth return; 2822fcf5ef2aSThomas Huth } 2823fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2824fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2825fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2826fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2827fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2828fcf5ef2aSThomas Huth tcg_temp_free(t0); 2829fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2830fcf5ef2aSThomas Huth } 2831fcf5ef2aSThomas Huth 2832fcf5ef2aSThomas Huth /* stmw */ 2833fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2834fcf5ef2aSThomas Huth { 2835fcf5ef2aSThomas Huth TCGv t0; 2836fcf5ef2aSThomas Huth TCGv_i32 t1; 2837fcf5ef2aSThomas Huth 2838fcf5ef2aSThomas Huth if (ctx->le_mode) { 2839fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2840fcf5ef2aSThomas Huth return; 2841fcf5ef2aSThomas Huth } 2842fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2843fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2844fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2845fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2846fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2847fcf5ef2aSThomas Huth tcg_temp_free(t0); 2848fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth 2851fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2852fcf5ef2aSThomas Huth 2853fcf5ef2aSThomas Huth /* lswi */ 2854fcf5ef2aSThomas Huth /* PowerPC32 specification says we must generate an exception if 2855fcf5ef2aSThomas Huth * rA is in the range of registers to be loaded. 2856fcf5ef2aSThomas Huth * In an other hand, IBM says this is valid, but rA won't be loaded. 2857fcf5ef2aSThomas Huth * For now, I'll follow the spec... 2858fcf5ef2aSThomas Huth */ 2859fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2860fcf5ef2aSThomas Huth { 2861fcf5ef2aSThomas Huth TCGv t0; 2862fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2863fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2864fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2865fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2866fcf5ef2aSThomas Huth int nr; 2867fcf5ef2aSThomas Huth 2868fcf5ef2aSThomas Huth if (ctx->le_mode) { 2869fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2870fcf5ef2aSThomas Huth return; 2871fcf5ef2aSThomas Huth } 2872fcf5ef2aSThomas Huth if (nb == 0) 2873fcf5ef2aSThomas Huth nb = 32; 2874fcf5ef2aSThomas Huth nr = (nb + 3) / 4; 2875fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2876fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2877fcf5ef2aSThomas Huth return; 2878fcf5ef2aSThomas Huth } 2879fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2880fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2881fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2882fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2883fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 2884fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 2885fcf5ef2aSThomas Huth tcg_temp_free(t0); 2886fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2887fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2888fcf5ef2aSThomas Huth } 2889fcf5ef2aSThomas Huth 2890fcf5ef2aSThomas Huth /* lswx */ 2891fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 2892fcf5ef2aSThomas Huth { 2893fcf5ef2aSThomas Huth TCGv t0; 2894fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 2895fcf5ef2aSThomas Huth 2896fcf5ef2aSThomas Huth if (ctx->le_mode) { 2897fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2898fcf5ef2aSThomas Huth return; 2899fcf5ef2aSThomas Huth } 2900fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2901fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2902fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2903fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2904fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 2905fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 2906fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2907fcf5ef2aSThomas Huth tcg_temp_free(t0); 2908fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2909fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2910fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2911fcf5ef2aSThomas Huth } 2912fcf5ef2aSThomas Huth 2913fcf5ef2aSThomas Huth /* stswi */ 2914fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 2915fcf5ef2aSThomas Huth { 2916fcf5ef2aSThomas Huth TCGv t0; 2917fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2918fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2919fcf5ef2aSThomas Huth 2920fcf5ef2aSThomas Huth if (ctx->le_mode) { 2921fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2922fcf5ef2aSThomas Huth return; 2923fcf5ef2aSThomas Huth } 2924fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2925fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2926fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2927fcf5ef2aSThomas Huth if (nb == 0) 2928fcf5ef2aSThomas Huth nb = 32; 2929fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2930fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2931fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2932fcf5ef2aSThomas Huth tcg_temp_free(t0); 2933fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2934fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2935fcf5ef2aSThomas Huth } 2936fcf5ef2aSThomas Huth 2937fcf5ef2aSThomas Huth /* stswx */ 2938fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 2939fcf5ef2aSThomas Huth { 2940fcf5ef2aSThomas Huth TCGv t0; 2941fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2942fcf5ef2aSThomas Huth 2943fcf5ef2aSThomas Huth if (ctx->le_mode) { 2944fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2945fcf5ef2aSThomas Huth return; 2946fcf5ef2aSThomas Huth } 2947fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2948fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2949fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2950fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 2951fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 2952fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 2953fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2954fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2955fcf5ef2aSThomas Huth tcg_temp_free(t0); 2956fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2957fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2958fcf5ef2aSThomas Huth } 2959fcf5ef2aSThomas Huth 2960fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 2961fcf5ef2aSThomas Huth /* eieio */ 2962fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 2963fcf5ef2aSThomas Huth { 2964fcf5ef2aSThomas Huth } 2965fcf5ef2aSThomas Huth 2966fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2967fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2968fcf5ef2aSThomas Huth { 2969fcf5ef2aSThomas Huth TCGv_i32 t; 2970fcf5ef2aSThomas Huth TCGLabel *l; 2971fcf5ef2aSThomas Huth 2972fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 2973fcf5ef2aSThomas Huth return; 2974fcf5ef2aSThomas Huth } 2975fcf5ef2aSThomas Huth l = gen_new_label(); 2976fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 2977fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 2978fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 2979fcf5ef2aSThomas Huth if (global) { 2980fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 2981fcf5ef2aSThomas Huth } else { 2982fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 2983fcf5ef2aSThomas Huth } 2984fcf5ef2aSThomas Huth gen_set_label(l); 2985fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 2986fcf5ef2aSThomas Huth } 2987fcf5ef2aSThomas Huth #else 2988fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 2989fcf5ef2aSThomas Huth #endif 2990fcf5ef2aSThomas Huth 2991fcf5ef2aSThomas Huth /* isync */ 2992fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 2993fcf5ef2aSThomas Huth { 2994fcf5ef2aSThomas Huth /* 2995fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 2996fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 2997fcf5ef2aSThomas Huth */ 2998fcf5ef2aSThomas Huth if (!ctx->pr) { 2999fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3000fcf5ef2aSThomas Huth } 3001fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3002fcf5ef2aSThomas Huth } 3003fcf5ef2aSThomas Huth 3004fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3005fcf5ef2aSThomas Huth 3006fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3007fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3008fcf5ef2aSThomas Huth { \ 3009fcf5ef2aSThomas Huth TCGv t0; \ 3010fcf5ef2aSThomas Huth TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ 3011fcf5ef2aSThomas Huth int len = MEMOP_GET_SIZE(memop); \ 3012fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); \ 3013fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); \ 3014fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); \ 3015fcf5ef2aSThomas Huth if ((len) > 1) { \ 3016fcf5ef2aSThomas Huth gen_check_align(ctx, t0, (len)-1); \ 3017fcf5ef2aSThomas Huth } \ 3018fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ 3019fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, t0); \ 3020fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ 3021fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 3022fcf5ef2aSThomas Huth } 3023fcf5ef2aSThomas Huth 3024fcf5ef2aSThomas Huth /* lwarx */ 3025fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3026fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3027fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3028fcf5ef2aSThomas Huth 3029a68a6146SBalamuruhan S #define LD_ATOMIC(name, memop, tp, op, eop) \ 3030a68a6146SBalamuruhan S static void gen_##name(DisasContext *ctx) \ 3031a68a6146SBalamuruhan S { \ 3032a68a6146SBalamuruhan S int len = MEMOP_GET_SIZE(memop); \ 3033a68a6146SBalamuruhan S uint32_t gpr_FC = FC(ctx->opcode); \ 3034a68a6146SBalamuruhan S TCGv EA = tcg_temp_local_new(); \ 3035a68a6146SBalamuruhan S TCGv_##tp t0, t1; \ 3036a68a6146SBalamuruhan S \ 3037a68a6146SBalamuruhan S gen_addr_register(ctx, EA); \ 3038a68a6146SBalamuruhan S if (len > 1) { \ 3039a68a6146SBalamuruhan S gen_check_align(ctx, EA, len - 1); \ 3040a68a6146SBalamuruhan S } \ 3041a68a6146SBalamuruhan S t0 = tcg_temp_new_##tp(); \ 3042a68a6146SBalamuruhan S t1 = tcg_temp_new_##tp(); \ 3043a68a6146SBalamuruhan S tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3044a68a6146SBalamuruhan S \ 3045a68a6146SBalamuruhan S switch (gpr_FC) { \ 3046a68a6146SBalamuruhan S case 0: /* Fetch and add */ \ 3047a68a6146SBalamuruhan S tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3048a68a6146SBalamuruhan S break; \ 3049a68a6146SBalamuruhan S case 1: /* Fetch and xor */ \ 3050a68a6146SBalamuruhan S tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3051a68a6146SBalamuruhan S break; \ 3052a68a6146SBalamuruhan S case 2: /* Fetch and or */ \ 3053a68a6146SBalamuruhan S tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3054a68a6146SBalamuruhan S break; \ 3055a68a6146SBalamuruhan S case 3: /* Fetch and 'and' */ \ 3056a68a6146SBalamuruhan S tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3057a68a6146SBalamuruhan S break; \ 3058a68a6146SBalamuruhan S case 8: /* Swap */ \ 3059a68a6146SBalamuruhan S tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3060a68a6146SBalamuruhan S break; \ 3061a68a6146SBalamuruhan S case 4: /* Fetch and max unsigned */ \ 3062a68a6146SBalamuruhan S case 5: /* Fetch and max signed */ \ 3063a68a6146SBalamuruhan S case 6: /* Fetch and min unsigned */ \ 3064a68a6146SBalamuruhan S case 7: /* Fetch and min signed */ \ 3065a68a6146SBalamuruhan S case 16: /* compare and swap not equal */ \ 3066a68a6146SBalamuruhan S case 24: /* Fetch and increment bounded */ \ 3067a68a6146SBalamuruhan S case 25: /* Fetch and increment equal */ \ 3068a68a6146SBalamuruhan S case 28: /* Fetch and decrement bounded */ \ 3069a68a6146SBalamuruhan S gen_invalid(ctx); \ 3070a68a6146SBalamuruhan S break; \ 3071a68a6146SBalamuruhan S default: \ 3072a68a6146SBalamuruhan S /* invoke data storage error handler */ \ 3073a68a6146SBalamuruhan S gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3074a68a6146SBalamuruhan S } \ 3075a68a6146SBalamuruhan S tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ 3076a68a6146SBalamuruhan S tcg_temp_free_##tp(t0); \ 3077a68a6146SBalamuruhan S tcg_temp_free_##tp(t1); \ 3078a68a6146SBalamuruhan S tcg_temp_free(EA); \ 3079a68a6146SBalamuruhan S } 3080a68a6146SBalamuruhan S 3081a68a6146SBalamuruhan S LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) 3082a68a6146SBalamuruhan S #if defined(TARGET_PPC64) 3083a68a6146SBalamuruhan S LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) 3084a68a6146SBalamuruhan S #endif 3085a68a6146SBalamuruhan S 3086a3401188SBalamuruhan S #define ST_ATOMIC(name, memop, tp, op) \ 3087a3401188SBalamuruhan S static void gen_##name(DisasContext *ctx) \ 3088a3401188SBalamuruhan S { \ 3089a3401188SBalamuruhan S int len = MEMOP_GET_SIZE(memop); \ 3090a3401188SBalamuruhan S uint32_t gpr_FC = FC(ctx->opcode); \ 3091a3401188SBalamuruhan S TCGv EA = tcg_temp_local_new(); \ 3092a3401188SBalamuruhan S TCGv_##tp t0, t1; \ 3093a3401188SBalamuruhan S \ 3094a3401188SBalamuruhan S gen_addr_register(ctx, EA); \ 3095a3401188SBalamuruhan S if (len > 1) { \ 3096a3401188SBalamuruhan S gen_check_align(ctx, EA, len - 1); \ 3097a3401188SBalamuruhan S } \ 3098a3401188SBalamuruhan S t0 = tcg_temp_new_##tp(); \ 3099a3401188SBalamuruhan S t1 = tcg_temp_new_##tp(); \ 3100a3401188SBalamuruhan S tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3101a3401188SBalamuruhan S \ 3102a3401188SBalamuruhan S switch (gpr_FC) { \ 3103a3401188SBalamuruhan S case 0: /* add and Store */ \ 3104a3401188SBalamuruhan S tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3105a3401188SBalamuruhan S break; \ 3106a3401188SBalamuruhan S case 1: /* xor and Store */ \ 3107a3401188SBalamuruhan S tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3108a3401188SBalamuruhan S break; \ 3109a3401188SBalamuruhan S case 2: /* Or and Store */ \ 3110a3401188SBalamuruhan S tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3111a3401188SBalamuruhan S break; \ 3112a3401188SBalamuruhan S case 3: /* 'and' and Store */ \ 3113a3401188SBalamuruhan S tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3114a3401188SBalamuruhan S break; \ 3115a3401188SBalamuruhan S case 4: /* Store max unsigned */ \ 3116a3401188SBalamuruhan S case 5: /* Store max signed */ \ 3117a3401188SBalamuruhan S case 6: /* Store min unsigned */ \ 3118a3401188SBalamuruhan S case 7: /* Store min signed */ \ 3119a3401188SBalamuruhan S case 24: /* Store twin */ \ 3120a3401188SBalamuruhan S gen_invalid(ctx); \ 3121a3401188SBalamuruhan S break; \ 3122a3401188SBalamuruhan S default: \ 3123a3401188SBalamuruhan S /* invoke data storage error handler */ \ 3124a3401188SBalamuruhan S gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3125a3401188SBalamuruhan S } \ 3126a3401188SBalamuruhan S tcg_temp_free_##tp(t0); \ 3127a3401188SBalamuruhan S tcg_temp_free_##tp(t1); \ 3128a3401188SBalamuruhan S tcg_temp_free(EA); \ 3129a3401188SBalamuruhan S } 3130a3401188SBalamuruhan S 3131a3401188SBalamuruhan S ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) 3132a3401188SBalamuruhan S #if defined(TARGET_PPC64) 3133a3401188SBalamuruhan S ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) 3134a3401188SBalamuruhan S #endif 3135a3401188SBalamuruhan S 3136fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3137fcf5ef2aSThomas Huth static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3138fcf5ef2aSThomas Huth int reg, int memop) 3139fcf5ef2aSThomas Huth { 3140fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3141fcf5ef2aSThomas Huth 3142fcf5ef2aSThomas Huth tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); 3143fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); 3144fcf5ef2aSThomas Huth tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); 3145fcf5ef2aSThomas Huth tcg_temp_free(t0); 3146fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); 3147fcf5ef2aSThomas Huth } 3148fcf5ef2aSThomas Huth #else 3149fcf5ef2aSThomas Huth static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3150fcf5ef2aSThomas Huth int reg, int memop) 3151fcf5ef2aSThomas Huth { 3152fcf5ef2aSThomas Huth TCGLabel *l1; 3153fcf5ef2aSThomas Huth 3154fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3155fcf5ef2aSThomas Huth l1 = gen_new_label(); 3156fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3157efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3158fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop); 3159fcf5ef2aSThomas Huth gen_set_label(l1); 3160fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3161fcf5ef2aSThomas Huth } 3162fcf5ef2aSThomas Huth #endif 3163fcf5ef2aSThomas Huth 3164fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3165fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3166fcf5ef2aSThomas Huth { \ 3167fcf5ef2aSThomas Huth TCGv t0; \ 3168fcf5ef2aSThomas Huth int len = MEMOP_GET_SIZE(memop); \ 3169fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); \ 3170fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); \ 3171fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); \ 3172fcf5ef2aSThomas Huth if (len > 1) { \ 3173fcf5ef2aSThomas Huth gen_check_align(ctx, t0, (len) - 1); \ 3174fcf5ef2aSThomas Huth } \ 3175fcf5ef2aSThomas Huth gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ 3176fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 3177fcf5ef2aSThomas Huth } 3178fcf5ef2aSThomas Huth 3179fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3180fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3181fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3182fcf5ef2aSThomas Huth 3183fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3184fcf5ef2aSThomas Huth /* ldarx */ 3185fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3186fcf5ef2aSThomas Huth /* stdcx. */ 3187fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3188fcf5ef2aSThomas Huth 3189fcf5ef2aSThomas Huth /* lqarx */ 3190fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3191fcf5ef2aSThomas Huth { 3192fcf5ef2aSThomas Huth TCGv EA; 3193fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 3194fcf5ef2aSThomas Huth TCGv gpr1, gpr2; 3195fcf5ef2aSThomas Huth 3196fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3197fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3198fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3199fcf5ef2aSThomas Huth return; 3200fcf5ef2aSThomas Huth } 3201fcf5ef2aSThomas Huth 3202fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 3203fcf5ef2aSThomas Huth EA = tcg_temp_local_new(); 3204fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3205fcf5ef2aSThomas Huth gen_check_align(ctx, EA, 15); 3206fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 3207fcf5ef2aSThomas Huth gpr1 = cpu_gpr[rd+1]; 3208fcf5ef2aSThomas Huth gpr2 = cpu_gpr[rd]; 3209fcf5ef2aSThomas Huth } else { 3210fcf5ef2aSThomas Huth gpr1 = cpu_gpr[rd]; 3211fcf5ef2aSThomas Huth gpr2 = cpu_gpr[rd+1]; 3212fcf5ef2aSThomas Huth } 3213fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3214fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3215fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3216fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3217fcf5ef2aSThomas Huth 3218fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); 3219fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3220fcf5ef2aSThomas Huth tcg_temp_free(EA); 3221fcf5ef2aSThomas Huth } 3222fcf5ef2aSThomas Huth 3223fcf5ef2aSThomas Huth /* stqcx. */ 3224fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3225fcf5ef2aSThomas Huth { 3226fcf5ef2aSThomas Huth TCGv EA; 3227fcf5ef2aSThomas Huth int reg = rS(ctx->opcode); 3228fcf5ef2aSThomas Huth int len = 16; 3229fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3230fcf5ef2aSThomas Huth TCGLabel *l1; 3231fcf5ef2aSThomas Huth TCGv gpr1, gpr2; 3232fcf5ef2aSThomas Huth #endif 3233fcf5ef2aSThomas Huth 3234fcf5ef2aSThomas Huth if (unlikely((rD(ctx->opcode) & 1))) { 3235fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3236fcf5ef2aSThomas Huth return; 3237fcf5ef2aSThomas Huth } 3238fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 3239fcf5ef2aSThomas Huth EA = tcg_temp_local_new(); 3240fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3241fcf5ef2aSThomas Huth if (len > 1) { 3242fcf5ef2aSThomas Huth gen_check_align(ctx, EA, (len) - 1); 3243fcf5ef2aSThomas Huth } 3244fcf5ef2aSThomas Huth 3245fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3246fcf5ef2aSThomas Huth gen_conditional_store(ctx, EA, reg, 16); 3247fcf5ef2aSThomas Huth #else 3248fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3249fcf5ef2aSThomas Huth l1 = gen_new_label(); 3250fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3251efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3252fcf5ef2aSThomas Huth 3253fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 3254fcf5ef2aSThomas Huth gpr1 = cpu_gpr[reg + 1]; 3255fcf5ef2aSThomas Huth gpr2 = cpu_gpr[reg]; 3256fcf5ef2aSThomas Huth } else { 3257fcf5ef2aSThomas Huth gpr1 = cpu_gpr[reg]; 3258fcf5ef2aSThomas Huth gpr2 = cpu_gpr[reg + 1]; 3259fcf5ef2aSThomas Huth } 3260fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3261fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3262fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3263fcf5ef2aSThomas Huth 3264fcf5ef2aSThomas Huth gen_set_label(l1); 3265fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3266fcf5ef2aSThomas Huth #endif 3267fcf5ef2aSThomas Huth tcg_temp_free(EA); 3268fcf5ef2aSThomas Huth } 3269fcf5ef2aSThomas Huth 3270fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3271fcf5ef2aSThomas Huth 3272fcf5ef2aSThomas Huth /* sync */ 3273fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3274fcf5ef2aSThomas Huth { 3275fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3276fcf5ef2aSThomas Huth 3277fcf5ef2aSThomas Huth /* 3278fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3279fcf5ef2aSThomas Huth * 3280fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3281fcf5ef2aSThomas Huth * 3282fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3283fcf5ef2aSThomas Huth * check MSR_PR as well. 3284fcf5ef2aSThomas Huth */ 3285fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3286fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3287fcf5ef2aSThomas Huth } 3288fcf5ef2aSThomas Huth } 3289fcf5ef2aSThomas Huth 3290fcf5ef2aSThomas Huth /* wait */ 3291fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3292fcf5ef2aSThomas Huth { 3293fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3294fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3295fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3296fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3297fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3298fcf5ef2aSThomas Huth gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 3299fcf5ef2aSThomas Huth } 3300fcf5ef2aSThomas Huth 3301fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3302fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3303fcf5ef2aSThomas Huth { 3304fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3305fcf5ef2aSThomas Huth GEN_PRIV; 3306fcf5ef2aSThomas Huth #else 3307fcf5ef2aSThomas Huth TCGv_i32 t; 3308fcf5ef2aSThomas Huth 3309fcf5ef2aSThomas Huth CHK_HV; 3310fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3311fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3312fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3313fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3314fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3315fcf5ef2aSThomas Huth } 3316fcf5ef2aSThomas Huth 3317fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3318fcf5ef2aSThomas Huth { 3319fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3320fcf5ef2aSThomas Huth GEN_PRIV; 3321fcf5ef2aSThomas Huth #else 3322fcf5ef2aSThomas Huth TCGv_i32 t; 3323fcf5ef2aSThomas Huth 3324fcf5ef2aSThomas Huth CHK_HV; 3325fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3326fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3327fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3328fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3329fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3330fcf5ef2aSThomas Huth } 3331fcf5ef2aSThomas Huth 3332cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3333cdee0e72SNikunj A Dadhania { 3334cdee0e72SNikunj A Dadhania gen_nap(ctx); 3335cdee0e72SNikunj A Dadhania } 3336cdee0e72SNikunj A Dadhania 3337fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3338fcf5ef2aSThomas Huth { 3339fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3340fcf5ef2aSThomas Huth GEN_PRIV; 3341fcf5ef2aSThomas Huth #else 3342fcf5ef2aSThomas Huth TCGv_i32 t; 3343fcf5ef2aSThomas Huth 3344fcf5ef2aSThomas Huth CHK_HV; 3345fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3346fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3347fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3348fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3349fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3350fcf5ef2aSThomas Huth } 3351fcf5ef2aSThomas Huth 3352fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3353fcf5ef2aSThomas Huth { 3354fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3355fcf5ef2aSThomas Huth GEN_PRIV; 3356fcf5ef2aSThomas Huth #else 3357fcf5ef2aSThomas Huth TCGv_i32 t; 3358fcf5ef2aSThomas Huth 3359fcf5ef2aSThomas Huth CHK_HV; 3360fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3361fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3362fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3363fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3365fcf5ef2aSThomas Huth } 3366fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3367fcf5ef2aSThomas Huth 3368fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3369fcf5ef2aSThomas Huth { 3370fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3371fcf5ef2aSThomas Huth if (ctx->has_cfar) 3372fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3373fcf5ef2aSThomas Huth #endif 3374fcf5ef2aSThomas Huth } 3375fcf5ef2aSThomas Huth 3376fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3377fcf5ef2aSThomas Huth { 3378fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3379fcf5ef2aSThomas Huth return false; 3380fcf5ef2aSThomas Huth } 3381fcf5ef2aSThomas Huth 3382fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3383fcf5ef2aSThomas Huth return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3384fcf5ef2aSThomas Huth #else 3385fcf5ef2aSThomas Huth return true; 3386fcf5ef2aSThomas Huth #endif 3387fcf5ef2aSThomas Huth } 3388fcf5ef2aSThomas Huth 3389fcf5ef2aSThomas Huth /*** Branch ***/ 3390fcf5ef2aSThomas Huth static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3391fcf5ef2aSThomas Huth { 3392fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3393fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3394fcf5ef2aSThomas Huth } 3395fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3396fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3397fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 3398fcf5ef2aSThomas Huth tcg_gen_exit_tb((uintptr_t)ctx->tb + n); 3399fcf5ef2aSThomas Huth } else { 3400fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 3401fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3402fcf5ef2aSThomas Huth if ((ctx->singlestep_enabled & 3403fcf5ef2aSThomas Huth (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && 3404fcf5ef2aSThomas Huth (ctx->exception == POWERPC_EXCP_BRANCH || 3405fcf5ef2aSThomas Huth ctx->exception == POWERPC_EXCP_TRACE)) { 3406fcf5ef2aSThomas Huth gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); 3407fcf5ef2aSThomas Huth } 3408fcf5ef2aSThomas Huth if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { 3409fcf5ef2aSThomas Huth gen_debug_exception(ctx); 3410fcf5ef2aSThomas Huth } 3411fcf5ef2aSThomas Huth } 3412fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3413fcf5ef2aSThomas Huth } 3414fcf5ef2aSThomas Huth } 3415fcf5ef2aSThomas Huth 3416fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3417fcf5ef2aSThomas Huth { 3418fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3419fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3420fcf5ef2aSThomas Huth } 3421fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3422fcf5ef2aSThomas Huth } 3423fcf5ef2aSThomas Huth 3424fcf5ef2aSThomas Huth /* b ba bl bla */ 3425fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3426fcf5ef2aSThomas Huth { 3427fcf5ef2aSThomas Huth target_ulong li, target; 3428fcf5ef2aSThomas Huth 3429fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3430fcf5ef2aSThomas Huth /* sign extend LI */ 3431fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3432fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3433fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3434fcf5ef2aSThomas Huth target = ctx->nip + li - 4; 3435fcf5ef2aSThomas Huth } else { 3436fcf5ef2aSThomas Huth target = li; 3437fcf5ef2aSThomas Huth } 3438fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3439fcf5ef2aSThomas Huth gen_setlr(ctx, ctx->nip); 3440fcf5ef2aSThomas Huth } 3441fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3442fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3443fcf5ef2aSThomas Huth } 3444fcf5ef2aSThomas Huth 3445fcf5ef2aSThomas Huth #define BCOND_IM 0 3446fcf5ef2aSThomas Huth #define BCOND_LR 1 3447fcf5ef2aSThomas Huth #define BCOND_CTR 2 3448fcf5ef2aSThomas Huth #define BCOND_TAR 3 3449fcf5ef2aSThomas Huth 3450fcf5ef2aSThomas Huth static inline void gen_bcond(DisasContext *ctx, int type) 3451fcf5ef2aSThomas Huth { 3452fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3453fcf5ef2aSThomas Huth TCGLabel *l1; 3454fcf5ef2aSThomas Huth TCGv target; 3455fcf5ef2aSThomas Huth 3456fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3457fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3458fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3459fcf5ef2aSThomas Huth if (type == BCOND_CTR) 3460fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3461fcf5ef2aSThomas Huth else if (type == BCOND_TAR) 3462fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3463fcf5ef2aSThomas Huth else 3464fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3465fcf5ef2aSThomas Huth } else { 3466fcf5ef2aSThomas Huth TCGV_UNUSED(target); 3467fcf5ef2aSThomas Huth } 3468fcf5ef2aSThomas Huth if (LK(ctx->opcode)) 3469fcf5ef2aSThomas Huth gen_setlr(ctx, ctx->nip); 3470fcf5ef2aSThomas Huth l1 = gen_new_label(); 3471fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3472fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3473fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3474fcf5ef2aSThomas Huth if (unlikely(type == BCOND_CTR)) { 3475fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3476fcf5ef2aSThomas Huth return; 3477fcf5ef2aSThomas Huth } 3478fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3479fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3480fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3481fcf5ef2aSThomas Huth } else { 3482fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3483fcf5ef2aSThomas Huth } 3484fcf5ef2aSThomas Huth if (bo & 0x2) { 3485fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3486fcf5ef2aSThomas Huth } else { 3487fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3488fcf5ef2aSThomas Huth } 3489fcf5ef2aSThomas Huth tcg_temp_free(temp); 3490fcf5ef2aSThomas Huth } 3491fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3492fcf5ef2aSThomas Huth /* Test CR */ 3493fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3494fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3495fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3496fcf5ef2aSThomas Huth 3497fcf5ef2aSThomas Huth if (bo & 0x8) { 3498fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3499fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3500fcf5ef2aSThomas Huth } else { 3501fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3502fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3503fcf5ef2aSThomas Huth } 3504fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3505fcf5ef2aSThomas Huth } 3506fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3507fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3508fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3509fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3510fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, ctx->nip + li - 4); 3511fcf5ef2aSThomas Huth } else { 3512fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3513fcf5ef2aSThomas Huth } 3514fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 3515fcf5ef2aSThomas Huth gen_set_label(l1); 3516fcf5ef2aSThomas Huth gen_goto_tb(ctx, 1, ctx->nip); 3517fcf5ef2aSThomas Huth } 3518fcf5ef2aSThomas Huth } else { 3519fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3520fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3521fcf5ef2aSThomas Huth } else { 3522fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3523fcf5ef2aSThomas Huth } 3524fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3525fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 3526fcf5ef2aSThomas Huth gen_set_label(l1); 3527fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 3528fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3529fcf5ef2aSThomas Huth } 3530fcf5ef2aSThomas Huth } 3531fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3532fcf5ef2aSThomas Huth tcg_temp_free(target); 3533fcf5ef2aSThomas Huth } 3534fcf5ef2aSThomas Huth } 3535fcf5ef2aSThomas Huth 3536fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3537fcf5ef2aSThomas Huth { 3538fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3539fcf5ef2aSThomas Huth } 3540fcf5ef2aSThomas Huth 3541fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3542fcf5ef2aSThomas Huth { 3543fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3544fcf5ef2aSThomas Huth } 3545fcf5ef2aSThomas Huth 3546fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3547fcf5ef2aSThomas Huth { 3548fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3549fcf5ef2aSThomas Huth } 3550fcf5ef2aSThomas Huth 3551fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3552fcf5ef2aSThomas Huth { 3553fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3554fcf5ef2aSThomas Huth } 3555fcf5ef2aSThomas Huth 3556fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3557fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3558fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3559fcf5ef2aSThomas Huth { \ 3560fcf5ef2aSThomas Huth uint8_t bitmask; \ 3561fcf5ef2aSThomas Huth int sh; \ 3562fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3563fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3564fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3565fcf5ef2aSThomas Huth if (sh > 0) \ 3566fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3567fcf5ef2aSThomas Huth else if (sh < 0) \ 3568fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3569fcf5ef2aSThomas Huth else \ 3570fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3571fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3572fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3573fcf5ef2aSThomas Huth if (sh > 0) \ 3574fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3575fcf5ef2aSThomas Huth else if (sh < 0) \ 3576fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3577fcf5ef2aSThomas Huth else \ 3578fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3579fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3580fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3581fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3582fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3583fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3584fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3585fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3586fcf5ef2aSThomas Huth } 3587fcf5ef2aSThomas Huth 3588fcf5ef2aSThomas Huth /* crand */ 3589fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3590fcf5ef2aSThomas Huth /* crandc */ 3591fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3592fcf5ef2aSThomas Huth /* creqv */ 3593fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3594fcf5ef2aSThomas Huth /* crnand */ 3595fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3596fcf5ef2aSThomas Huth /* crnor */ 3597fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3598fcf5ef2aSThomas Huth /* cror */ 3599fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3600fcf5ef2aSThomas Huth /* crorc */ 3601fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3602fcf5ef2aSThomas Huth /* crxor */ 3603fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3604fcf5ef2aSThomas Huth 3605fcf5ef2aSThomas Huth /* mcrf */ 3606fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3607fcf5ef2aSThomas Huth { 3608fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3609fcf5ef2aSThomas Huth } 3610fcf5ef2aSThomas Huth 3611fcf5ef2aSThomas Huth /*** System linkage ***/ 3612fcf5ef2aSThomas Huth 3613fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3614fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3615fcf5ef2aSThomas Huth { 3616fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3617fcf5ef2aSThomas Huth GEN_PRIV; 3618fcf5ef2aSThomas Huth #else 3619fcf5ef2aSThomas Huth /* This instruction doesn't exist anymore on 64-bit server 3620fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3621fcf5ef2aSThomas Huth */ 3622fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_SEGMENT_64B) { 3623fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3624fcf5ef2aSThomas Huth return; 3625fcf5ef2aSThomas Huth } 3626fcf5ef2aSThomas Huth /* Restore CPU state */ 3627fcf5ef2aSThomas Huth CHK_SV; 3628fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3629fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3630fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3631fcf5ef2aSThomas Huth #endif 3632fcf5ef2aSThomas Huth } 3633fcf5ef2aSThomas Huth 3634fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3635fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 3636fcf5ef2aSThomas Huth { 3637fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3638fcf5ef2aSThomas Huth GEN_PRIV; 3639fcf5ef2aSThomas Huth #else 3640fcf5ef2aSThomas Huth /* Restore CPU state */ 3641fcf5ef2aSThomas Huth CHK_SV; 3642fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3643fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 3644fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3645fcf5ef2aSThomas Huth #endif 3646fcf5ef2aSThomas Huth } 3647fcf5ef2aSThomas Huth 3648fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 3649fcf5ef2aSThomas Huth { 3650fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3651fcf5ef2aSThomas Huth GEN_PRIV; 3652fcf5ef2aSThomas Huth #else 3653fcf5ef2aSThomas Huth /* Restore CPU state */ 3654fcf5ef2aSThomas Huth CHK_HV; 3655fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 3656fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3657fcf5ef2aSThomas Huth #endif 3658fcf5ef2aSThomas Huth } 3659fcf5ef2aSThomas Huth #endif 3660fcf5ef2aSThomas Huth 3661fcf5ef2aSThomas Huth /* sc */ 3662fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3663fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3664fcf5ef2aSThomas Huth #else 3665fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3666fcf5ef2aSThomas Huth #endif 3667fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 3668fcf5ef2aSThomas Huth { 3669fcf5ef2aSThomas Huth uint32_t lev; 3670fcf5ef2aSThomas Huth 3671fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 3672fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3673fcf5ef2aSThomas Huth } 3674fcf5ef2aSThomas Huth 3675fcf5ef2aSThomas Huth /*** Trap ***/ 3676fcf5ef2aSThomas Huth 3677fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 3678fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 3679fcf5ef2aSThomas Huth { 3680fcf5ef2aSThomas Huth /* Trap never */ 3681fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 3682fcf5ef2aSThomas Huth return true; 3683fcf5ef2aSThomas Huth } 3684fcf5ef2aSThomas Huth /* Trap always */ 3685fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 3686fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3687fcf5ef2aSThomas Huth return true; 3688fcf5ef2aSThomas Huth } 3689fcf5ef2aSThomas Huth return false; 3690fcf5ef2aSThomas Huth } 3691fcf5ef2aSThomas Huth 3692fcf5ef2aSThomas Huth /* tw */ 3693fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 3694fcf5ef2aSThomas Huth { 3695fcf5ef2aSThomas Huth TCGv_i32 t0; 3696fcf5ef2aSThomas Huth 3697fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3698fcf5ef2aSThomas Huth return; 3699fcf5ef2aSThomas Huth } 3700fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3701fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3702fcf5ef2aSThomas Huth t0); 3703fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3704fcf5ef2aSThomas Huth } 3705fcf5ef2aSThomas Huth 3706fcf5ef2aSThomas Huth /* twi */ 3707fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 3708fcf5ef2aSThomas Huth { 3709fcf5ef2aSThomas Huth TCGv t0; 3710fcf5ef2aSThomas Huth TCGv_i32 t1; 3711fcf5ef2aSThomas Huth 3712fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3713fcf5ef2aSThomas Huth return; 3714fcf5ef2aSThomas Huth } 3715fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3716fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3717fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3718fcf5ef2aSThomas Huth tcg_temp_free(t0); 3719fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3720fcf5ef2aSThomas Huth } 3721fcf5ef2aSThomas Huth 3722fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3723fcf5ef2aSThomas Huth /* td */ 3724fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 3725fcf5ef2aSThomas Huth { 3726fcf5ef2aSThomas Huth TCGv_i32 t0; 3727fcf5ef2aSThomas Huth 3728fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3729fcf5ef2aSThomas Huth return; 3730fcf5ef2aSThomas Huth } 3731fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3732fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3733fcf5ef2aSThomas Huth t0); 3734fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3735fcf5ef2aSThomas Huth } 3736fcf5ef2aSThomas Huth 3737fcf5ef2aSThomas Huth /* tdi */ 3738fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 3739fcf5ef2aSThomas Huth { 3740fcf5ef2aSThomas Huth TCGv t0; 3741fcf5ef2aSThomas Huth TCGv_i32 t1; 3742fcf5ef2aSThomas Huth 3743fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3744fcf5ef2aSThomas Huth return; 3745fcf5ef2aSThomas Huth } 3746fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3747fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3748fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3749fcf5ef2aSThomas Huth tcg_temp_free(t0); 3750fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3751fcf5ef2aSThomas Huth } 3752fcf5ef2aSThomas Huth #endif 3753fcf5ef2aSThomas Huth 3754fcf5ef2aSThomas Huth /*** Processor control ***/ 3755fcf5ef2aSThomas Huth 3756dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 3757fcf5ef2aSThomas Huth { 3758fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3759fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3760fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 3761fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 3762fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 3763fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 3764fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 3765fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 3766fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 3767fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 3768dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 3769dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 3770dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 3771dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 3772dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 3773dd09c361SNikunj A Dadhania } 3774fcf5ef2aSThomas Huth tcg_temp_free(t0); 3775fcf5ef2aSThomas Huth tcg_temp_free(t1); 3776fcf5ef2aSThomas Huth tcg_temp_free(t2); 3777fcf5ef2aSThomas Huth } 3778fcf5ef2aSThomas Huth 3779fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 3780fcf5ef2aSThomas Huth { 3781dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 3782fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 3783dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 3784dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 3785dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 3786dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 3787dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 37881bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 37891bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 37901bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 3791fcf5ef2aSThomas Huth } 3792fcf5ef2aSThomas Huth 3793fcf5ef2aSThomas Huth /* mcrxr */ 3794fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 3795fcf5ef2aSThomas Huth { 3796fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3797fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3798fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3799fcf5ef2aSThomas Huth 3800fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 3801fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 3802fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 3803fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 3804fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 3805fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 3806fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 3807fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 3808fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3809fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3810fcf5ef2aSThomas Huth 3811fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 3812fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 3813fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3814fcf5ef2aSThomas Huth } 3815fcf5ef2aSThomas Huth 3816fcf5ef2aSThomas Huth /* mfcr mfocrf */ 3817fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 3818fcf5ef2aSThomas Huth { 3819fcf5ef2aSThomas Huth uint32_t crm, crn; 3820fcf5ef2aSThomas Huth 3821fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 3822fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 3823fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 3824fcf5ef2aSThomas Huth crn = ctz32 (crm); 3825fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3826fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 3827fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 3828fcf5ef2aSThomas Huth } 3829fcf5ef2aSThomas Huth } else { 3830fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3831fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 3832fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3833fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 3834fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3835fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 3836fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3837fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 3838fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3839fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 3840fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3841fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 3842fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3843fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 3844fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3845fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 3846fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 3847fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3848fcf5ef2aSThomas Huth } 3849fcf5ef2aSThomas Huth } 3850fcf5ef2aSThomas Huth 3851fcf5ef2aSThomas Huth /* mfmsr */ 3852fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 3853fcf5ef2aSThomas Huth { 3854fcf5ef2aSThomas Huth CHK_SV; 3855fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 3856fcf5ef2aSThomas Huth } 3857fcf5ef2aSThomas Huth 3858fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 3859fcf5ef2aSThomas Huth { 3860fcf5ef2aSThomas Huth #if 0 3861fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 3862fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 3863fcf5ef2aSThomas Huth #endif 3864fcf5ef2aSThomas Huth } 3865fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 3866fcf5ef2aSThomas Huth 3867fcf5ef2aSThomas Huth /* mfspr */ 3868fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 3869fcf5ef2aSThomas Huth { 3870fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 3871fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 3872fcf5ef2aSThomas Huth 3873fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3874fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 3875fcf5ef2aSThomas Huth #else 3876fcf5ef2aSThomas Huth if (ctx->pr) { 3877fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 3878fcf5ef2aSThomas Huth } else if (ctx->hv) { 3879fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 3880fcf5ef2aSThomas Huth } else { 3881fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 3882fcf5ef2aSThomas Huth } 3883fcf5ef2aSThomas Huth #endif 3884fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 3885fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 3886fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 3887fcf5ef2aSThomas Huth } else { 3888fcf5ef2aSThomas Huth /* Privilege exception */ 3889fcf5ef2aSThomas Huth /* This is a hack to avoid warnings when running Linux: 3890fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 3891fcf5ef2aSThomas Huth * allowing userland application to read the PVR 3892fcf5ef2aSThomas Huth */ 3893fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 3894fcf5ef2aSThomas Huth fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at " 3895fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3896fcf5ef2aSThomas Huth if (qemu_log_separate()) { 3897fcf5ef2aSThomas Huth qemu_log("Trying to read privileged spr %d (0x%03x) at " 3898fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3899fcf5ef2aSThomas Huth } 3900fcf5ef2aSThomas Huth } 3901fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 3902fcf5ef2aSThomas Huth } 3903fcf5ef2aSThomas Huth } else { 3904fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 3905fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 3906fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 3907fcf5ef2aSThomas Huth /* This is a nop */ 3908fcf5ef2aSThomas Huth return; 3909fcf5ef2aSThomas Huth } 3910fcf5ef2aSThomas Huth /* Not defined */ 3911fcf5ef2aSThomas Huth fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " 3912fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3913fcf5ef2aSThomas Huth if (qemu_log_separate()) { 3914fcf5ef2aSThomas Huth qemu_log("Trying to read invalid spr %d (0x%03x) at " 3915fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3916fcf5ef2aSThomas Huth } 3917fcf5ef2aSThomas Huth 3918fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 3919fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 3920fcf5ef2aSThomas Huth */ 3921fcf5ef2aSThomas Huth if (sprn & 0x10) { 3922fcf5ef2aSThomas Huth if (ctx->pr) { 3923fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3924fcf5ef2aSThomas Huth } 3925fcf5ef2aSThomas Huth } else { 3926fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 3927fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3928fcf5ef2aSThomas Huth } 3929fcf5ef2aSThomas Huth } 3930fcf5ef2aSThomas Huth } 3931fcf5ef2aSThomas Huth } 3932fcf5ef2aSThomas Huth 3933fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 3934fcf5ef2aSThomas Huth { 3935fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 3936fcf5ef2aSThomas Huth } 3937fcf5ef2aSThomas Huth 3938fcf5ef2aSThomas Huth /* mftb */ 3939fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 3940fcf5ef2aSThomas Huth { 3941fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 3942fcf5ef2aSThomas Huth } 3943fcf5ef2aSThomas Huth 3944fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 3945fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 3946fcf5ef2aSThomas Huth { 3947fcf5ef2aSThomas Huth uint32_t crm, crn; 3948fcf5ef2aSThomas Huth 3949fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 3950fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 3951fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 3952fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3953fcf5ef2aSThomas Huth crn = ctz32 (crm); 3954fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3955fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 3956fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 3957fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3958fcf5ef2aSThomas Huth } 3959fcf5ef2aSThomas Huth } else { 3960fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3961fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3962fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 3963fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 3964fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 3965fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 3966fcf5ef2aSThomas Huth } 3967fcf5ef2aSThomas Huth } 3968fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3969fcf5ef2aSThomas Huth } 3970fcf5ef2aSThomas Huth } 3971fcf5ef2aSThomas Huth 3972fcf5ef2aSThomas Huth /* mtmsr */ 3973fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3974fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 3975fcf5ef2aSThomas Huth { 3976fcf5ef2aSThomas Huth CHK_SV; 3977fcf5ef2aSThomas Huth 3978fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3979fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 3980fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 3981fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3982fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 3983fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 3984fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 3985fcf5ef2aSThomas Huth tcg_temp_free(t0); 3986fcf5ef2aSThomas Huth } else { 3987fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 3988fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 3989fcf5ef2aSThomas Huth * directly from ppc_store_msr 3990fcf5ef2aSThomas Huth */ 3991fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 3992fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 3993fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 3994fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 3995fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3996fcf5ef2aSThomas Huth } 3997fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 3998fcf5ef2aSThomas Huth } 3999fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4000fcf5ef2aSThomas Huth 4001fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4002fcf5ef2aSThomas Huth { 4003fcf5ef2aSThomas Huth CHK_SV; 4004fcf5ef2aSThomas Huth 4005fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4006fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4007fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4008fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4009fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4010fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4011fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4012fcf5ef2aSThomas Huth tcg_temp_free(t0); 4013fcf5ef2aSThomas Huth } else { 4014fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4015fcf5ef2aSThomas Huth 4016fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4017fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4018fcf5ef2aSThomas Huth * directly from ppc_store_msr 4019fcf5ef2aSThomas Huth */ 4020fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 4021fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4022fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4023fcf5ef2aSThomas Huth #else 4024fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4025fcf5ef2aSThomas Huth #endif 4026fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4027fcf5ef2aSThomas Huth tcg_temp_free(msr); 4028fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4029fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4030fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4031fcf5ef2aSThomas Huth } 4032fcf5ef2aSThomas Huth #endif 4033fcf5ef2aSThomas Huth } 4034fcf5ef2aSThomas Huth 4035fcf5ef2aSThomas Huth /* mtspr */ 4036fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4037fcf5ef2aSThomas Huth { 4038fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4039fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4040fcf5ef2aSThomas Huth 4041fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4042fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4043fcf5ef2aSThomas Huth #else 4044fcf5ef2aSThomas Huth if (ctx->pr) { 4045fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4046fcf5ef2aSThomas Huth } else if (ctx->hv) { 4047fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4048fcf5ef2aSThomas Huth } else { 4049fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4050fcf5ef2aSThomas Huth } 4051fcf5ef2aSThomas Huth #endif 4052fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4053fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4054fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4055fcf5ef2aSThomas Huth } else { 4056fcf5ef2aSThomas Huth /* Privilege exception */ 4057fcf5ef2aSThomas Huth fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at " 4058fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4059fcf5ef2aSThomas Huth if (qemu_log_separate()) { 4060fcf5ef2aSThomas Huth qemu_log("Trying to write privileged spr %d (0x%03x) at " 4061fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4062fcf5ef2aSThomas Huth } 4063fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4064fcf5ef2aSThomas Huth } 4065fcf5ef2aSThomas Huth } else { 4066fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4067fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4068fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4069fcf5ef2aSThomas Huth /* This is a nop */ 4070fcf5ef2aSThomas Huth return; 4071fcf5ef2aSThomas Huth } 4072fcf5ef2aSThomas Huth 4073fcf5ef2aSThomas Huth /* Not defined */ 4074fcf5ef2aSThomas Huth if (qemu_log_separate()) { 4075fcf5ef2aSThomas Huth qemu_log("Trying to write invalid spr %d (0x%03x) at " 4076fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4077fcf5ef2aSThomas Huth } 4078fcf5ef2aSThomas Huth fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " 4079fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4080fcf5ef2aSThomas Huth 4081fcf5ef2aSThomas Huth 4082fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4083fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4084fcf5ef2aSThomas Huth */ 4085fcf5ef2aSThomas Huth if (sprn & 0x10) { 4086fcf5ef2aSThomas Huth if (ctx->pr) { 4087fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4088fcf5ef2aSThomas Huth } 4089fcf5ef2aSThomas Huth } else { 4090fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4091fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4092fcf5ef2aSThomas Huth } 4093fcf5ef2aSThomas Huth } 4094fcf5ef2aSThomas Huth } 4095fcf5ef2aSThomas Huth } 4096fcf5ef2aSThomas Huth 4097fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4098fcf5ef2aSThomas Huth /* setb */ 4099fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4100fcf5ef2aSThomas Huth { 4101fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4102fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4103fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4104fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4105fcf5ef2aSThomas Huth 4106fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4107fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4108fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4109fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4110fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4111fcf5ef2aSThomas Huth 4112fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4113fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4114fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4115fcf5ef2aSThomas Huth } 4116fcf5ef2aSThomas Huth #endif 4117fcf5ef2aSThomas Huth 4118fcf5ef2aSThomas Huth /*** Cache management ***/ 4119fcf5ef2aSThomas Huth 4120fcf5ef2aSThomas Huth /* dcbf */ 4121fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4122fcf5ef2aSThomas Huth { 4123fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4124fcf5ef2aSThomas Huth TCGv t0; 4125fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4126fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4127fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4128fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4129fcf5ef2aSThomas Huth tcg_temp_free(t0); 4130fcf5ef2aSThomas Huth } 4131fcf5ef2aSThomas Huth 4132fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4133fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4134fcf5ef2aSThomas Huth { 4135fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4136fcf5ef2aSThomas Huth GEN_PRIV; 4137fcf5ef2aSThomas Huth #else 4138fcf5ef2aSThomas Huth TCGv EA, val; 4139fcf5ef2aSThomas Huth 4140fcf5ef2aSThomas Huth CHK_SV; 4141fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4142fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4143fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4144fcf5ef2aSThomas Huth val = tcg_temp_new(); 4145fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4146fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4147fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4148fcf5ef2aSThomas Huth tcg_temp_free(val); 4149fcf5ef2aSThomas Huth tcg_temp_free(EA); 4150fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4151fcf5ef2aSThomas Huth } 4152fcf5ef2aSThomas Huth 4153fcf5ef2aSThomas Huth /* dcdst */ 4154fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4155fcf5ef2aSThomas Huth { 4156fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4157fcf5ef2aSThomas Huth TCGv t0; 4158fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4159fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4160fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4161fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4162fcf5ef2aSThomas Huth tcg_temp_free(t0); 4163fcf5ef2aSThomas Huth } 4164fcf5ef2aSThomas Huth 4165fcf5ef2aSThomas Huth /* dcbt */ 4166fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4167fcf5ef2aSThomas Huth { 4168fcf5ef2aSThomas Huth /* interpreted as no-op */ 4169fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4170fcf5ef2aSThomas Huth * but does not generate any exception 4171fcf5ef2aSThomas Huth */ 4172fcf5ef2aSThomas Huth } 4173fcf5ef2aSThomas Huth 4174fcf5ef2aSThomas Huth /* dcbtst */ 4175fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4176fcf5ef2aSThomas Huth { 4177fcf5ef2aSThomas Huth /* interpreted as no-op */ 4178fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4179fcf5ef2aSThomas Huth * but does not generate any exception 4180fcf5ef2aSThomas Huth */ 4181fcf5ef2aSThomas Huth } 4182fcf5ef2aSThomas Huth 4183fcf5ef2aSThomas Huth /* dcbtls */ 4184fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4185fcf5ef2aSThomas Huth { 4186fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4187fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4188fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4189fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4190fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4191fcf5ef2aSThomas Huth tcg_temp_free(t0); 4192fcf5ef2aSThomas Huth } 4193fcf5ef2aSThomas Huth 4194fcf5ef2aSThomas Huth /* dcbz */ 4195fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4196fcf5ef2aSThomas Huth { 4197fcf5ef2aSThomas Huth TCGv tcgv_addr; 4198fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4199fcf5ef2aSThomas Huth 4200fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4201fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4202fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4203fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4204fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4205fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4206fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4207fcf5ef2aSThomas Huth } 4208fcf5ef2aSThomas Huth 4209fcf5ef2aSThomas Huth /* dst / dstt */ 4210fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4211fcf5ef2aSThomas Huth { 4212fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4213fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4214fcf5ef2aSThomas Huth } else { 4215fcf5ef2aSThomas Huth /* interpreted as no-op */ 4216fcf5ef2aSThomas Huth } 4217fcf5ef2aSThomas Huth } 4218fcf5ef2aSThomas Huth 4219fcf5ef2aSThomas Huth /* dstst /dststt */ 4220fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4221fcf5ef2aSThomas Huth { 4222fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4223fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4224fcf5ef2aSThomas Huth } else { 4225fcf5ef2aSThomas Huth /* interpreted as no-op */ 4226fcf5ef2aSThomas Huth } 4227fcf5ef2aSThomas Huth 4228fcf5ef2aSThomas Huth } 4229fcf5ef2aSThomas Huth 4230fcf5ef2aSThomas Huth /* dss / dssall */ 4231fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4232fcf5ef2aSThomas Huth { 4233fcf5ef2aSThomas Huth /* interpreted as no-op */ 4234fcf5ef2aSThomas Huth } 4235fcf5ef2aSThomas Huth 4236fcf5ef2aSThomas Huth /* icbi */ 4237fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4238fcf5ef2aSThomas Huth { 4239fcf5ef2aSThomas Huth TCGv t0; 4240fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4241fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4242fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4243fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4244fcf5ef2aSThomas Huth tcg_temp_free(t0); 4245fcf5ef2aSThomas Huth } 4246fcf5ef2aSThomas Huth 4247fcf5ef2aSThomas Huth /* Optional: */ 4248fcf5ef2aSThomas Huth /* dcba */ 4249fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4250fcf5ef2aSThomas Huth { 4251fcf5ef2aSThomas Huth /* interpreted as no-op */ 4252fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a store by the MMU 4253fcf5ef2aSThomas Huth * but does not generate any exception 4254fcf5ef2aSThomas Huth */ 4255fcf5ef2aSThomas Huth } 4256fcf5ef2aSThomas Huth 4257fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4258fcf5ef2aSThomas Huth /* Supervisor only: */ 4259fcf5ef2aSThomas Huth 4260fcf5ef2aSThomas Huth /* mfsr */ 4261fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4262fcf5ef2aSThomas Huth { 4263fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4264fcf5ef2aSThomas Huth GEN_PRIV; 4265fcf5ef2aSThomas Huth #else 4266fcf5ef2aSThomas Huth TCGv t0; 4267fcf5ef2aSThomas Huth 4268fcf5ef2aSThomas Huth CHK_SV; 4269fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4270fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4271fcf5ef2aSThomas Huth tcg_temp_free(t0); 4272fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4273fcf5ef2aSThomas Huth } 4274fcf5ef2aSThomas Huth 4275fcf5ef2aSThomas Huth /* mfsrin */ 4276fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4277fcf5ef2aSThomas Huth { 4278fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4279fcf5ef2aSThomas Huth GEN_PRIV; 4280fcf5ef2aSThomas Huth #else 4281fcf5ef2aSThomas Huth TCGv t0; 4282fcf5ef2aSThomas Huth 4283fcf5ef2aSThomas Huth CHK_SV; 4284fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4285fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4286fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 4287fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4288fcf5ef2aSThomas Huth tcg_temp_free(t0); 4289fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4290fcf5ef2aSThomas Huth } 4291fcf5ef2aSThomas Huth 4292fcf5ef2aSThomas Huth /* mtsr */ 4293fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4294fcf5ef2aSThomas Huth { 4295fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4296fcf5ef2aSThomas Huth GEN_PRIV; 4297fcf5ef2aSThomas Huth #else 4298fcf5ef2aSThomas Huth TCGv t0; 4299fcf5ef2aSThomas Huth 4300fcf5ef2aSThomas Huth CHK_SV; 4301fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4302fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4303fcf5ef2aSThomas Huth tcg_temp_free(t0); 4304fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4305fcf5ef2aSThomas Huth } 4306fcf5ef2aSThomas Huth 4307fcf5ef2aSThomas Huth /* mtsrin */ 4308fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4309fcf5ef2aSThomas Huth { 4310fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4311fcf5ef2aSThomas Huth GEN_PRIV; 4312fcf5ef2aSThomas Huth #else 4313fcf5ef2aSThomas Huth TCGv t0; 4314fcf5ef2aSThomas Huth CHK_SV; 4315fcf5ef2aSThomas Huth 4316fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4317fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4318fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 4319fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4320fcf5ef2aSThomas Huth tcg_temp_free(t0); 4321fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4322fcf5ef2aSThomas Huth } 4323fcf5ef2aSThomas Huth 4324fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4325fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4326fcf5ef2aSThomas Huth 4327fcf5ef2aSThomas Huth /* mfsr */ 4328fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4329fcf5ef2aSThomas Huth { 4330fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4331fcf5ef2aSThomas Huth GEN_PRIV; 4332fcf5ef2aSThomas Huth #else 4333fcf5ef2aSThomas Huth TCGv t0; 4334fcf5ef2aSThomas Huth 4335fcf5ef2aSThomas Huth CHK_SV; 4336fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4337fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4338fcf5ef2aSThomas Huth tcg_temp_free(t0); 4339fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4340fcf5ef2aSThomas Huth } 4341fcf5ef2aSThomas Huth 4342fcf5ef2aSThomas Huth /* mfsrin */ 4343fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4344fcf5ef2aSThomas Huth { 4345fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4346fcf5ef2aSThomas Huth GEN_PRIV; 4347fcf5ef2aSThomas Huth #else 4348fcf5ef2aSThomas Huth TCGv t0; 4349fcf5ef2aSThomas Huth 4350fcf5ef2aSThomas Huth CHK_SV; 4351fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4352fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4353fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 4354fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4355fcf5ef2aSThomas Huth tcg_temp_free(t0); 4356fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4357fcf5ef2aSThomas Huth } 4358fcf5ef2aSThomas Huth 4359fcf5ef2aSThomas Huth /* mtsr */ 4360fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4361fcf5ef2aSThomas Huth { 4362fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4363fcf5ef2aSThomas Huth GEN_PRIV; 4364fcf5ef2aSThomas Huth #else 4365fcf5ef2aSThomas Huth TCGv t0; 4366fcf5ef2aSThomas Huth 4367fcf5ef2aSThomas Huth CHK_SV; 4368fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4369fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4370fcf5ef2aSThomas Huth tcg_temp_free(t0); 4371fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4372fcf5ef2aSThomas Huth } 4373fcf5ef2aSThomas Huth 4374fcf5ef2aSThomas Huth /* mtsrin */ 4375fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4376fcf5ef2aSThomas Huth { 4377fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4378fcf5ef2aSThomas Huth GEN_PRIV; 4379fcf5ef2aSThomas Huth #else 4380fcf5ef2aSThomas Huth TCGv t0; 4381fcf5ef2aSThomas Huth 4382fcf5ef2aSThomas Huth CHK_SV; 4383fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4384fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4385fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 4386fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4387fcf5ef2aSThomas Huth tcg_temp_free(t0); 4388fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4389fcf5ef2aSThomas Huth } 4390fcf5ef2aSThomas Huth 4391fcf5ef2aSThomas Huth /* slbmte */ 4392fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4393fcf5ef2aSThomas Huth { 4394fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4395fcf5ef2aSThomas Huth GEN_PRIV; 4396fcf5ef2aSThomas Huth #else 4397fcf5ef2aSThomas Huth CHK_SV; 4398fcf5ef2aSThomas Huth 4399fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4400fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4401fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4402fcf5ef2aSThomas Huth } 4403fcf5ef2aSThomas Huth 4404fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4405fcf5ef2aSThomas Huth { 4406fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4407fcf5ef2aSThomas Huth GEN_PRIV; 4408fcf5ef2aSThomas Huth #else 4409fcf5ef2aSThomas Huth CHK_SV; 4410fcf5ef2aSThomas Huth 4411fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4412fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4413fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4414fcf5ef2aSThomas Huth } 4415fcf5ef2aSThomas Huth 4416fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4417fcf5ef2aSThomas Huth { 4418fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4419fcf5ef2aSThomas Huth GEN_PRIV; 4420fcf5ef2aSThomas Huth #else 4421fcf5ef2aSThomas Huth CHK_SV; 4422fcf5ef2aSThomas Huth 4423fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4424fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4425fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4426fcf5ef2aSThomas Huth } 4427fcf5ef2aSThomas Huth 4428fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4429fcf5ef2aSThomas Huth { 4430fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4431fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4432fcf5ef2aSThomas Huth #else 4433fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4434fcf5ef2aSThomas Huth 4435fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4436fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4437fcf5ef2aSThomas Huth return; 4438fcf5ef2aSThomas Huth } 4439fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4440fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4441fcf5ef2aSThomas Huth l1 = gen_new_label(); 4442fcf5ef2aSThomas Huth l2 = gen_new_label(); 4443fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4444fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4445efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4446fcf5ef2aSThomas Huth tcg_gen_br(l2); 4447fcf5ef2aSThomas Huth gen_set_label(l1); 4448fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4449fcf5ef2aSThomas Huth gen_set_label(l2); 4450fcf5ef2aSThomas Huth #endif 4451fcf5ef2aSThomas Huth } 4452fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4453fcf5ef2aSThomas Huth 4454fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4455fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4456fcf5ef2aSThomas Huth 4457fcf5ef2aSThomas Huth /* tlbia */ 4458fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4459fcf5ef2aSThomas Huth { 4460fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4461fcf5ef2aSThomas Huth GEN_PRIV; 4462fcf5ef2aSThomas Huth #else 4463fcf5ef2aSThomas Huth CHK_HV; 4464fcf5ef2aSThomas Huth 4465fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4466fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4467fcf5ef2aSThomas Huth } 4468fcf5ef2aSThomas Huth 4469fcf5ef2aSThomas Huth /* tlbiel */ 4470fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4471fcf5ef2aSThomas Huth { 4472fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4473fcf5ef2aSThomas Huth GEN_PRIV; 4474fcf5ef2aSThomas Huth #else 4475fcf5ef2aSThomas Huth CHK_SV; 4476fcf5ef2aSThomas Huth 4477fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4478fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4479fcf5ef2aSThomas Huth } 4480fcf5ef2aSThomas Huth 4481fcf5ef2aSThomas Huth /* tlbie */ 4482fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4483fcf5ef2aSThomas Huth { 4484fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4485fcf5ef2aSThomas Huth GEN_PRIV; 4486fcf5ef2aSThomas Huth #else 4487fcf5ef2aSThomas Huth TCGv_i32 t1; 4488fcf5ef2aSThomas Huth CHK_HV; 4489fcf5ef2aSThomas Huth 4490fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4491fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4492fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4493fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4494fcf5ef2aSThomas Huth tcg_temp_free(t0); 4495fcf5ef2aSThomas Huth } else { 4496fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4497fcf5ef2aSThomas Huth } 4498fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4499fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4500fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4501fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4502fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4503fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4504fcf5ef2aSThomas Huth } 4505fcf5ef2aSThomas Huth 4506fcf5ef2aSThomas Huth /* tlbsync */ 4507fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4508fcf5ef2aSThomas Huth { 4509fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4510fcf5ef2aSThomas Huth GEN_PRIV; 4511fcf5ef2aSThomas Huth #else 4512fcf5ef2aSThomas Huth CHK_HV; 4513fcf5ef2aSThomas Huth 4514fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4515fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4516fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4517fcf5ef2aSThomas Huth } 4518fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4519fcf5ef2aSThomas Huth } 4520fcf5ef2aSThomas Huth 4521fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4522fcf5ef2aSThomas Huth /* slbia */ 4523fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 4524fcf5ef2aSThomas Huth { 4525fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4526fcf5ef2aSThomas Huth GEN_PRIV; 4527fcf5ef2aSThomas Huth #else 4528fcf5ef2aSThomas Huth CHK_SV; 4529fcf5ef2aSThomas Huth 4530fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 4531fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4532fcf5ef2aSThomas Huth } 4533fcf5ef2aSThomas Huth 4534fcf5ef2aSThomas Huth /* slbie */ 4535fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 4536fcf5ef2aSThomas Huth { 4537fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4538fcf5ef2aSThomas Huth GEN_PRIV; 4539fcf5ef2aSThomas Huth #else 4540fcf5ef2aSThomas Huth CHK_SV; 4541fcf5ef2aSThomas Huth 4542fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4543fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4544fcf5ef2aSThomas Huth } 4545a63f1dfcSNikunj A Dadhania 4546a63f1dfcSNikunj A Dadhania /* slbieg */ 4547a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 4548a63f1dfcSNikunj A Dadhania { 4549a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 4550a63f1dfcSNikunj A Dadhania GEN_PRIV; 4551a63f1dfcSNikunj A Dadhania #else 4552a63f1dfcSNikunj A Dadhania CHK_SV; 4553a63f1dfcSNikunj A Dadhania 4554a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4555a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 4556a63f1dfcSNikunj A Dadhania } 4557a63f1dfcSNikunj A Dadhania 455862d897caSNikunj A Dadhania /* slbsync */ 455962d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 456062d897caSNikunj A Dadhania { 456162d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 456262d897caSNikunj A Dadhania GEN_PRIV; 456362d897caSNikunj A Dadhania #else 456462d897caSNikunj A Dadhania CHK_SV; 456562d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 456662d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 456762d897caSNikunj A Dadhania } 456862d897caSNikunj A Dadhania 4569fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4570fcf5ef2aSThomas Huth 4571fcf5ef2aSThomas Huth /*** External control ***/ 4572fcf5ef2aSThomas Huth /* Optional: */ 4573fcf5ef2aSThomas Huth 4574fcf5ef2aSThomas Huth /* eciwx */ 4575fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 4576fcf5ef2aSThomas Huth { 4577fcf5ef2aSThomas Huth TCGv t0; 4578fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4579fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4580fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4581fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4582fcf5ef2aSThomas Huth gen_check_align(ctx, t0, 0x03); 4583fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4584fcf5ef2aSThomas Huth tcg_temp_free(t0); 4585fcf5ef2aSThomas Huth } 4586fcf5ef2aSThomas Huth 4587fcf5ef2aSThomas Huth /* ecowx */ 4588fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 4589fcf5ef2aSThomas Huth { 4590fcf5ef2aSThomas Huth TCGv t0; 4591fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4592fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4593fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4594fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4595fcf5ef2aSThomas Huth gen_check_align(ctx, t0, 0x03); 4596fcf5ef2aSThomas Huth gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4597fcf5ef2aSThomas Huth tcg_temp_free(t0); 4598fcf5ef2aSThomas Huth } 4599fcf5ef2aSThomas Huth 4600fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 4601fcf5ef2aSThomas Huth 4602fcf5ef2aSThomas Huth /* abs - abs. */ 4603fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 4604fcf5ef2aSThomas Huth { 4605fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4606fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4607fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4608fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4609fcf5ef2aSThomas Huth tcg_gen_br(l2); 4610fcf5ef2aSThomas Huth gen_set_label(l1); 4611fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4612fcf5ef2aSThomas Huth gen_set_label(l2); 4613fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4614fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4615fcf5ef2aSThomas Huth } 4616fcf5ef2aSThomas Huth 4617fcf5ef2aSThomas Huth /* abso - abso. */ 4618fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 4619fcf5ef2aSThomas Huth { 4620fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4621fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4622fcf5ef2aSThomas Huth TCGLabel *l3 = gen_new_label(); 4623fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4624fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4625fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4626fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4627fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4628fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4629fcf5ef2aSThomas Huth tcg_gen_br(l2); 4630fcf5ef2aSThomas Huth gen_set_label(l1); 4631fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4632fcf5ef2aSThomas Huth tcg_gen_br(l3); 4633fcf5ef2aSThomas Huth gen_set_label(l2); 4634fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4635fcf5ef2aSThomas Huth gen_set_label(l3); 4636fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4637fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4638fcf5ef2aSThomas Huth } 4639fcf5ef2aSThomas Huth 4640fcf5ef2aSThomas Huth /* clcs */ 4641fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 4642fcf5ef2aSThomas Huth { 4643fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4644fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4645fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4646fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 4647fcf5ef2aSThomas Huth } 4648fcf5ef2aSThomas Huth 4649fcf5ef2aSThomas Huth /* div - div. */ 4650fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 4651fcf5ef2aSThomas Huth { 4652fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4653fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4654fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4655fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4656fcf5ef2aSThomas Huth } 4657fcf5ef2aSThomas Huth 4658fcf5ef2aSThomas Huth /* divo - divo. */ 4659fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 4660fcf5ef2aSThomas Huth { 4661fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4662fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4663fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4664fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4665fcf5ef2aSThomas Huth } 4666fcf5ef2aSThomas Huth 4667fcf5ef2aSThomas Huth /* divs - divs. */ 4668fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 4669fcf5ef2aSThomas Huth { 4670fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4671fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4672fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4673fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4674fcf5ef2aSThomas Huth } 4675fcf5ef2aSThomas Huth 4676fcf5ef2aSThomas Huth /* divso - divso. */ 4677fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 4678fcf5ef2aSThomas Huth { 4679fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4680fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4681fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4682fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4683fcf5ef2aSThomas Huth } 4684fcf5ef2aSThomas Huth 4685fcf5ef2aSThomas Huth /* doz - doz. */ 4686fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 4687fcf5ef2aSThomas Huth { 4688fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4689fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4690fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4691fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4692fcf5ef2aSThomas Huth tcg_gen_br(l2); 4693fcf5ef2aSThomas Huth gen_set_label(l1); 4694fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4695fcf5ef2aSThomas Huth gen_set_label(l2); 4696fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4697fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4698fcf5ef2aSThomas Huth } 4699fcf5ef2aSThomas Huth 4700fcf5ef2aSThomas Huth /* dozo - dozo. */ 4701fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 4702fcf5ef2aSThomas Huth { 4703fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4704fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4705fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4706fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4707fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4708fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4709fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4710fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4711fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4712fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4713fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4714fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 4715fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4716fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4717fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4718fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4719fcf5ef2aSThomas Huth tcg_gen_br(l2); 4720fcf5ef2aSThomas Huth gen_set_label(l1); 4721fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4722fcf5ef2aSThomas Huth gen_set_label(l2); 4723fcf5ef2aSThomas Huth tcg_temp_free(t0); 4724fcf5ef2aSThomas Huth tcg_temp_free(t1); 4725fcf5ef2aSThomas Huth tcg_temp_free(t2); 4726fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4727fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4728fcf5ef2aSThomas Huth } 4729fcf5ef2aSThomas Huth 4730fcf5ef2aSThomas Huth /* dozi */ 4731fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 4732fcf5ef2aSThomas Huth { 4733fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 4734fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4735fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4736fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 4737fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 4738fcf5ef2aSThomas Huth tcg_gen_br(l2); 4739fcf5ef2aSThomas Huth gen_set_label(l1); 4740fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4741fcf5ef2aSThomas Huth gen_set_label(l2); 4742fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4743fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4744fcf5ef2aSThomas Huth } 4745fcf5ef2aSThomas Huth 4746fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 4747fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 4748fcf5ef2aSThomas Huth { 4749fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4750fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 4751fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 4752fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 4753fcf5ef2aSThomas Huth 4754fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4755fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 4756fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4757fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4758fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4759fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 4760fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 4761fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4762fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 4763fcf5ef2aSThomas Huth tcg_temp_free(t0); 4764fcf5ef2aSThomas Huth } 4765fcf5ef2aSThomas Huth 4766fcf5ef2aSThomas Huth /* maskg - maskg. */ 4767fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 4768fcf5ef2aSThomas Huth { 4769fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4770fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4771fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4772fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4773fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 4774fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 4775fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4776fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 4777fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 4778fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 4779fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 4780fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 4781fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4782fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4783fcf5ef2aSThomas Huth gen_set_label(l1); 4784fcf5ef2aSThomas Huth tcg_temp_free(t0); 4785fcf5ef2aSThomas Huth tcg_temp_free(t1); 4786fcf5ef2aSThomas Huth tcg_temp_free(t2); 4787fcf5ef2aSThomas Huth tcg_temp_free(t3); 4788fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4789fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4790fcf5ef2aSThomas Huth } 4791fcf5ef2aSThomas Huth 4792fcf5ef2aSThomas Huth /* maskir - maskir. */ 4793fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 4794fcf5ef2aSThomas Huth { 4795fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4796fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4797fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4798fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4799fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4800fcf5ef2aSThomas Huth tcg_temp_free(t0); 4801fcf5ef2aSThomas Huth tcg_temp_free(t1); 4802fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4803fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4804fcf5ef2aSThomas Huth } 4805fcf5ef2aSThomas Huth 4806fcf5ef2aSThomas Huth /* mul - mul. */ 4807fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 4808fcf5ef2aSThomas Huth { 4809fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 4810fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 4811fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4812fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4813fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4814fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 4815fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 4816fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 4817fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 4818fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4819fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 4820fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 4821fcf5ef2aSThomas Huth tcg_temp_free(t2); 4822fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4823fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4824fcf5ef2aSThomas Huth } 4825fcf5ef2aSThomas Huth 4826fcf5ef2aSThomas Huth /* mulo - mulo. */ 4827fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 4828fcf5ef2aSThomas Huth { 4829fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4830fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 4831fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 4832fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4833fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4834fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4835fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4836fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4837fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 4838fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 4839fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 4840fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 4841fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4842fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 4843fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 4844fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4845fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4846fcf5ef2aSThomas Huth gen_set_label(l1); 4847fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 4848fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 4849fcf5ef2aSThomas Huth tcg_temp_free(t2); 4850fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4851fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4852fcf5ef2aSThomas Huth } 4853fcf5ef2aSThomas Huth 4854fcf5ef2aSThomas Huth /* nabs - nabs. */ 4855fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 4856fcf5ef2aSThomas Huth { 4857fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4858fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4859fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4860fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4861fcf5ef2aSThomas Huth tcg_gen_br(l2); 4862fcf5ef2aSThomas Huth gen_set_label(l1); 4863fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4864fcf5ef2aSThomas Huth gen_set_label(l2); 4865fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4866fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4867fcf5ef2aSThomas Huth } 4868fcf5ef2aSThomas Huth 4869fcf5ef2aSThomas Huth /* nabso - nabso. */ 4870fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 4871fcf5ef2aSThomas Huth { 4872fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4873fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4874fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4875fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4876fcf5ef2aSThomas Huth tcg_gen_br(l2); 4877fcf5ef2aSThomas Huth gen_set_label(l1); 4878fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4879fcf5ef2aSThomas Huth gen_set_label(l2); 4880fcf5ef2aSThomas Huth /* nabs never overflows */ 4881fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4882fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4883fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4884fcf5ef2aSThomas Huth } 4885fcf5ef2aSThomas Huth 4886fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 4887fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 4888fcf5ef2aSThomas Huth { 4889fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 4890fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 4891fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4892fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4893fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4894fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 4895fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 4896fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 4897fcf5ef2aSThomas Huth tcg_temp_free(t0); 4898fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4899fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4900fcf5ef2aSThomas Huth } 4901fcf5ef2aSThomas Huth 4902fcf5ef2aSThomas Huth /* rrib - rrib. */ 4903fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 4904fcf5ef2aSThomas Huth { 4905fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4906fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4907fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4908fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 4909fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 4910fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4911fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 4912fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 4913fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4914fcf5ef2aSThomas Huth tcg_temp_free(t0); 4915fcf5ef2aSThomas Huth tcg_temp_free(t1); 4916fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4917fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4918fcf5ef2aSThomas Huth } 4919fcf5ef2aSThomas Huth 4920fcf5ef2aSThomas Huth /* sle - sle. */ 4921fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 4922fcf5ef2aSThomas Huth { 4923fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4924fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4925fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4926fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4927fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 4928fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4929fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 4930fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4931fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 4932fcf5ef2aSThomas Huth tcg_temp_free(t0); 4933fcf5ef2aSThomas Huth tcg_temp_free(t1); 4934fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4935fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4936fcf5ef2aSThomas Huth } 4937fcf5ef2aSThomas Huth 4938fcf5ef2aSThomas Huth /* sleq - sleq. */ 4939fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 4940fcf5ef2aSThomas Huth { 4941fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4942fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4943fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4944fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4945fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 4946fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 4947fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4948fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 4949fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 4950fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 4951fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 4952fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4953fcf5ef2aSThomas Huth tcg_temp_free(t0); 4954fcf5ef2aSThomas Huth tcg_temp_free(t1); 4955fcf5ef2aSThomas Huth tcg_temp_free(t2); 4956fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4957fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4958fcf5ef2aSThomas Huth } 4959fcf5ef2aSThomas Huth 4960fcf5ef2aSThomas Huth /* sliq - sliq. */ 4961fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 4962fcf5ef2aSThomas Huth { 4963fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 4964fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4965fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4966fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 4967fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 4968fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 4969fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4970fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 4971fcf5ef2aSThomas Huth tcg_temp_free(t0); 4972fcf5ef2aSThomas Huth tcg_temp_free(t1); 4973fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4974fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4975fcf5ef2aSThomas Huth } 4976fcf5ef2aSThomas Huth 4977fcf5ef2aSThomas Huth /* slliq - slliq. */ 4978fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 4979fcf5ef2aSThomas Huth { 4980fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 4981fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4982fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4983fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 4984fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 4985fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 4986fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 4987fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 4988fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4989fcf5ef2aSThomas Huth tcg_temp_free(t0); 4990fcf5ef2aSThomas Huth tcg_temp_free(t1); 4991fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4992fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4993fcf5ef2aSThomas Huth } 4994fcf5ef2aSThomas Huth 4995fcf5ef2aSThomas Huth /* sllq - sllq. */ 4996fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 4997fcf5ef2aSThomas Huth { 4998fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4999fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5000fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5001fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5002fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5003fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5004fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5005fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5006fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5007fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5008fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5009fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5010fcf5ef2aSThomas Huth tcg_gen_br(l2); 5011fcf5ef2aSThomas Huth gen_set_label(l1); 5012fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5013fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5014fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5015fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5016fcf5ef2aSThomas Huth gen_set_label(l2); 5017fcf5ef2aSThomas Huth tcg_temp_free(t0); 5018fcf5ef2aSThomas Huth tcg_temp_free(t1); 5019fcf5ef2aSThomas Huth tcg_temp_free(t2); 5020fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5021fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5022fcf5ef2aSThomas Huth } 5023fcf5ef2aSThomas Huth 5024fcf5ef2aSThomas Huth /* slq - slq. */ 5025fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5026fcf5ef2aSThomas Huth { 5027fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5028fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5029fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5030fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5031fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5032fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5033fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5034fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5035fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5036fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5037fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5038fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5039fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5040fcf5ef2aSThomas Huth gen_set_label(l1); 5041fcf5ef2aSThomas Huth tcg_temp_free(t0); 5042fcf5ef2aSThomas Huth tcg_temp_free(t1); 5043fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5044fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5045fcf5ef2aSThomas Huth } 5046fcf5ef2aSThomas Huth 5047fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5048fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5049fcf5ef2aSThomas Huth { 5050fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5051fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5052fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5053fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5054fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5055fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5056fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5057fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5058fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5059fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5060fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5061fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5062fcf5ef2aSThomas Huth gen_set_label(l1); 5063fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5064fcf5ef2aSThomas Huth tcg_temp_free(t0); 5065fcf5ef2aSThomas Huth tcg_temp_free(t1); 5066fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5067fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5068fcf5ef2aSThomas Huth } 5069fcf5ef2aSThomas Huth 5070fcf5ef2aSThomas Huth /* sraq - sraq. */ 5071fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5072fcf5ef2aSThomas Huth { 5073fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5074fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5075fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5076fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5077fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5078fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5079fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5080fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5081fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5082fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5083fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5084fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5085fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5086fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5087fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5088fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5089fcf5ef2aSThomas Huth gen_set_label(l1); 5090fcf5ef2aSThomas Huth tcg_temp_free(t0); 5091fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5092fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5093fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5094fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5095fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5096fcf5ef2aSThomas Huth gen_set_label(l2); 5097fcf5ef2aSThomas Huth tcg_temp_free(t1); 5098fcf5ef2aSThomas Huth tcg_temp_free(t2); 5099fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5100fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5101fcf5ef2aSThomas Huth } 5102fcf5ef2aSThomas Huth 5103fcf5ef2aSThomas Huth /* sre - sre. */ 5104fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5105fcf5ef2aSThomas Huth { 5106fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5107fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5108fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5109fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5110fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5111fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5112fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5113fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5114fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5115fcf5ef2aSThomas Huth tcg_temp_free(t0); 5116fcf5ef2aSThomas Huth tcg_temp_free(t1); 5117fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5118fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5119fcf5ef2aSThomas Huth } 5120fcf5ef2aSThomas Huth 5121fcf5ef2aSThomas Huth /* srea - srea. */ 5122fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5123fcf5ef2aSThomas Huth { 5124fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5125fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5126fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5127fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5128fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5129fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5130fcf5ef2aSThomas Huth tcg_temp_free(t0); 5131fcf5ef2aSThomas Huth tcg_temp_free(t1); 5132fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5133fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5134fcf5ef2aSThomas Huth } 5135fcf5ef2aSThomas Huth 5136fcf5ef2aSThomas Huth /* sreq */ 5137fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5138fcf5ef2aSThomas Huth { 5139fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5140fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5141fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5142fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5143fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5144fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5145fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5146fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5147fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5148fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5149fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5150fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5151fcf5ef2aSThomas Huth tcg_temp_free(t0); 5152fcf5ef2aSThomas Huth tcg_temp_free(t1); 5153fcf5ef2aSThomas Huth tcg_temp_free(t2); 5154fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5155fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5156fcf5ef2aSThomas Huth } 5157fcf5ef2aSThomas Huth 5158fcf5ef2aSThomas Huth /* sriq */ 5159fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5160fcf5ef2aSThomas Huth { 5161fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5162fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5163fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5164fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5165fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5166fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5167fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5168fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5169fcf5ef2aSThomas Huth tcg_temp_free(t0); 5170fcf5ef2aSThomas Huth tcg_temp_free(t1); 5171fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5172fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5173fcf5ef2aSThomas Huth } 5174fcf5ef2aSThomas Huth 5175fcf5ef2aSThomas Huth /* srliq */ 5176fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5177fcf5ef2aSThomas Huth { 5178fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5179fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5180fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5181fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5182fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5183fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5184fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5185fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5186fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5187fcf5ef2aSThomas Huth tcg_temp_free(t0); 5188fcf5ef2aSThomas Huth tcg_temp_free(t1); 5189fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5190fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5191fcf5ef2aSThomas Huth } 5192fcf5ef2aSThomas Huth 5193fcf5ef2aSThomas Huth /* srlq */ 5194fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5195fcf5ef2aSThomas Huth { 5196fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5197fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5198fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5199fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5200fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5201fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5202fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5203fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5204fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5205fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5206fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5207fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5208fcf5ef2aSThomas Huth tcg_gen_br(l2); 5209fcf5ef2aSThomas Huth gen_set_label(l1); 5210fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5211fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5212fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5213fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5214fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5215fcf5ef2aSThomas Huth gen_set_label(l2); 5216fcf5ef2aSThomas Huth tcg_temp_free(t0); 5217fcf5ef2aSThomas Huth tcg_temp_free(t1); 5218fcf5ef2aSThomas Huth tcg_temp_free(t2); 5219fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5220fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5221fcf5ef2aSThomas Huth } 5222fcf5ef2aSThomas Huth 5223fcf5ef2aSThomas Huth /* srq */ 5224fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5225fcf5ef2aSThomas Huth { 5226fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5227fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5228fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5229fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5230fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5231fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5232fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5233fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5234fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5235fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5236fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5237fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5238fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5239fcf5ef2aSThomas Huth gen_set_label(l1); 5240fcf5ef2aSThomas Huth tcg_temp_free(t0); 5241fcf5ef2aSThomas Huth tcg_temp_free(t1); 5242fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5243fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5244fcf5ef2aSThomas Huth } 5245fcf5ef2aSThomas Huth 5246fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5247fcf5ef2aSThomas Huth 5248fcf5ef2aSThomas Huth /* dsa */ 5249fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5250fcf5ef2aSThomas Huth { 5251fcf5ef2aSThomas Huth /* XXX: TODO */ 5252fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5253fcf5ef2aSThomas Huth } 5254fcf5ef2aSThomas Huth 5255fcf5ef2aSThomas Huth /* esa */ 5256fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5257fcf5ef2aSThomas Huth { 5258fcf5ef2aSThomas Huth /* XXX: TODO */ 5259fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5260fcf5ef2aSThomas Huth } 5261fcf5ef2aSThomas Huth 5262fcf5ef2aSThomas Huth /* mfrom */ 5263fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5264fcf5ef2aSThomas Huth { 5265fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5266fcf5ef2aSThomas Huth GEN_PRIV; 5267fcf5ef2aSThomas Huth #else 5268fcf5ef2aSThomas Huth CHK_SV; 5269fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5270fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5271fcf5ef2aSThomas Huth } 5272fcf5ef2aSThomas Huth 5273fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5274fcf5ef2aSThomas Huth 5275fcf5ef2aSThomas Huth /* tlbld */ 5276fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5277fcf5ef2aSThomas Huth { 5278fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5279fcf5ef2aSThomas Huth GEN_PRIV; 5280fcf5ef2aSThomas Huth #else 5281fcf5ef2aSThomas Huth CHK_SV; 5282fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5283fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5284fcf5ef2aSThomas Huth } 5285fcf5ef2aSThomas Huth 5286fcf5ef2aSThomas Huth /* tlbli */ 5287fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5288fcf5ef2aSThomas Huth { 5289fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5290fcf5ef2aSThomas Huth GEN_PRIV; 5291fcf5ef2aSThomas Huth #else 5292fcf5ef2aSThomas Huth CHK_SV; 5293fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5294fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5295fcf5ef2aSThomas Huth } 5296fcf5ef2aSThomas Huth 5297fcf5ef2aSThomas Huth /* 74xx TLB management */ 5298fcf5ef2aSThomas Huth 5299fcf5ef2aSThomas Huth /* tlbld */ 5300fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5301fcf5ef2aSThomas Huth { 5302fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5303fcf5ef2aSThomas Huth GEN_PRIV; 5304fcf5ef2aSThomas Huth #else 5305fcf5ef2aSThomas Huth CHK_SV; 5306fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5307fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5308fcf5ef2aSThomas Huth } 5309fcf5ef2aSThomas Huth 5310fcf5ef2aSThomas Huth /* tlbli */ 5311fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5312fcf5ef2aSThomas Huth { 5313fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5314fcf5ef2aSThomas Huth GEN_PRIV; 5315fcf5ef2aSThomas Huth #else 5316fcf5ef2aSThomas Huth CHK_SV; 5317fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5318fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5319fcf5ef2aSThomas Huth } 5320fcf5ef2aSThomas Huth 5321fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5322fcf5ef2aSThomas Huth 5323fcf5ef2aSThomas Huth /* clf */ 5324fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5325fcf5ef2aSThomas Huth { 5326fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5327fcf5ef2aSThomas Huth } 5328fcf5ef2aSThomas Huth 5329fcf5ef2aSThomas Huth /* cli */ 5330fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5331fcf5ef2aSThomas Huth { 5332fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5333fcf5ef2aSThomas Huth GEN_PRIV; 5334fcf5ef2aSThomas Huth #else 5335fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5336fcf5ef2aSThomas Huth CHK_SV; 5337fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5338fcf5ef2aSThomas Huth } 5339fcf5ef2aSThomas Huth 5340fcf5ef2aSThomas Huth /* dclst */ 5341fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5342fcf5ef2aSThomas Huth { 5343fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5344fcf5ef2aSThomas Huth } 5345fcf5ef2aSThomas Huth 5346fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5347fcf5ef2aSThomas Huth { 5348fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5349fcf5ef2aSThomas Huth GEN_PRIV; 5350fcf5ef2aSThomas Huth #else 5351fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5352fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5353fcf5ef2aSThomas Huth TCGv t0; 5354fcf5ef2aSThomas Huth 5355fcf5ef2aSThomas Huth CHK_SV; 5356fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5357fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5358fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, t0, 28); 5359fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, 0xF); 5360fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5361fcf5ef2aSThomas Huth tcg_temp_free(t0); 5362fcf5ef2aSThomas Huth if (ra != 0 && ra != rd) 5363fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5365fcf5ef2aSThomas Huth } 5366fcf5ef2aSThomas Huth 5367fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5368fcf5ef2aSThomas Huth { 5369fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5370fcf5ef2aSThomas Huth GEN_PRIV; 5371fcf5ef2aSThomas Huth #else 5372fcf5ef2aSThomas Huth TCGv t0; 5373fcf5ef2aSThomas Huth 5374fcf5ef2aSThomas Huth CHK_SV; 5375fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5376fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5377fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5378fcf5ef2aSThomas Huth tcg_temp_free(t0); 5379fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5380fcf5ef2aSThomas Huth } 5381fcf5ef2aSThomas Huth 5382fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5383fcf5ef2aSThomas Huth { 5384fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5385fcf5ef2aSThomas Huth GEN_PRIV; 5386fcf5ef2aSThomas Huth #else 5387fcf5ef2aSThomas Huth CHK_SV; 5388fcf5ef2aSThomas Huth 5389fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5390fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5391fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5392fcf5ef2aSThomas Huth } 5393fcf5ef2aSThomas Huth 5394fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5395fcf5ef2aSThomas Huth 5396fcf5ef2aSThomas Huth /* BookE specific instructions */ 5397fcf5ef2aSThomas Huth 5398fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5399fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5400fcf5ef2aSThomas Huth { 5401fcf5ef2aSThomas Huth /* XXX: TODO */ 5402fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5403fcf5ef2aSThomas Huth } 5404fcf5ef2aSThomas Huth 5405fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5406fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5407fcf5ef2aSThomas Huth { 5408fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5409fcf5ef2aSThomas Huth GEN_PRIV; 5410fcf5ef2aSThomas Huth #else 5411fcf5ef2aSThomas Huth TCGv t0; 5412fcf5ef2aSThomas Huth 5413fcf5ef2aSThomas Huth CHK_SV; 5414fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5415fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5416fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5417fcf5ef2aSThomas Huth tcg_temp_free(t0); 5418fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5419fcf5ef2aSThomas Huth } 5420fcf5ef2aSThomas Huth 5421fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5422fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5423fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5424fcf5ef2aSThomas Huth { 5425fcf5ef2aSThomas Huth TCGv t0, t1; 5426fcf5ef2aSThomas Huth 5427fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5428fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5429fcf5ef2aSThomas Huth 5430fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5431fcf5ef2aSThomas Huth case 0x05: 5432fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5433fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5434fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5435fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5436fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5437fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5438fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5439fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5440fcf5ef2aSThomas Huth break; 5441fcf5ef2aSThomas Huth case 0x04: 5442fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5443fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5444fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5445fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5446fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5447fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5448fcf5ef2aSThomas Huth break; 5449fcf5ef2aSThomas Huth case 0x01: 5450fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5451fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5452fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5453fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5454fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5455fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5456fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5457fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5458fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5459fcf5ef2aSThomas Huth break; 5460fcf5ef2aSThomas Huth case 0x00: 5461fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5462fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5463fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5464fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5465fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5466fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5467fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5468fcf5ef2aSThomas Huth break; 5469fcf5ef2aSThomas Huth case 0x0D: 5470fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5471fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5472fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5473fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5474fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5475fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5476fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5477fcf5ef2aSThomas Huth break; 5478fcf5ef2aSThomas Huth case 0x0C: 5479fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5480fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5481fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5482fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5483fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5484fcf5ef2aSThomas Huth break; 5485fcf5ef2aSThomas Huth } 5486fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5487fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5488fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5489fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5490fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5491fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5492fcf5ef2aSThomas Huth } else { 5493fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5494fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5495fcf5ef2aSThomas Huth } 5496fcf5ef2aSThomas Huth 5497fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5498fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5499fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5500fcf5ef2aSThomas Huth 5501fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5502fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5503fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5504fcf5ef2aSThomas Huth } 5505fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5506fcf5ef2aSThomas Huth /* Signed */ 5507fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5508fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5509fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5510fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5511fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5512fcf5ef2aSThomas Huth /* Saturate */ 5513fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5514fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5515fcf5ef2aSThomas Huth } 5516fcf5ef2aSThomas Huth } else { 5517fcf5ef2aSThomas Huth /* Unsigned */ 5518fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5519fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5520fcf5ef2aSThomas Huth /* Saturate */ 5521fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5522fcf5ef2aSThomas Huth } 5523fcf5ef2aSThomas Huth } 5524fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5525fcf5ef2aSThomas Huth /* Check overflow */ 5526fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5527fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5528fcf5ef2aSThomas Huth } 5529fcf5ef2aSThomas Huth gen_set_label(l1); 5530fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5531fcf5ef2aSThomas Huth } 5532fcf5ef2aSThomas Huth } else { 5533fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5534fcf5ef2aSThomas Huth } 5535fcf5ef2aSThomas Huth tcg_temp_free(t0); 5536fcf5ef2aSThomas Huth tcg_temp_free(t1); 5537fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5538fcf5ef2aSThomas Huth /* Update Rc0 */ 5539fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5540fcf5ef2aSThomas Huth } 5541fcf5ef2aSThomas Huth } 5542fcf5ef2aSThomas Huth 5543fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5544fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5545fcf5ef2aSThomas Huth { \ 5546fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5547fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5548fcf5ef2aSThomas Huth } 5549fcf5ef2aSThomas Huth 5550fcf5ef2aSThomas Huth /* macchw - macchw. */ 5551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5552fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5554fcf5ef2aSThomas Huth /* macchws - macchws. */ 5555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5556fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5558fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5560fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5562fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5564fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5566fcf5ef2aSThomas Huth /* machhw - machhw. */ 5567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5568fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5570fcf5ef2aSThomas Huth /* machhws - machhws. */ 5571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5572fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5574fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5576fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5578fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5580fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5582fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5583fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5584fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5585fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5586fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5587fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5588fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5589fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5590fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5591fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5592fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5593fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5594fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5595fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5596fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5597fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5598fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5599fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5600fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5601fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5602fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5603fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5604fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5605fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5606fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5607fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5608fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5609fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5610fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5611fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5612fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5613fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5614fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5615fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5616fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5617fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5618fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5619fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5620fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5621fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5622fcf5ef2aSThomas Huth 5623fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5624fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5625fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5626fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5627fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5628fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5629fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5630fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5631fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5632fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5633fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5634fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5635fcf5ef2aSThomas Huth 5636fcf5ef2aSThomas Huth /* mfdcr */ 5637fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5638fcf5ef2aSThomas Huth { 5639fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5640fcf5ef2aSThomas Huth GEN_PRIV; 5641fcf5ef2aSThomas Huth #else 5642fcf5ef2aSThomas Huth TCGv dcrn; 5643fcf5ef2aSThomas Huth 5644fcf5ef2aSThomas Huth CHK_SV; 5645fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5646fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5647fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5648fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5649fcf5ef2aSThomas Huth } 5650fcf5ef2aSThomas Huth 5651fcf5ef2aSThomas Huth /* mtdcr */ 5652fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5653fcf5ef2aSThomas Huth { 5654fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5655fcf5ef2aSThomas Huth GEN_PRIV; 5656fcf5ef2aSThomas Huth #else 5657fcf5ef2aSThomas Huth TCGv dcrn; 5658fcf5ef2aSThomas Huth 5659fcf5ef2aSThomas Huth CHK_SV; 5660fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5661fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5662fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5663fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5664fcf5ef2aSThomas Huth } 5665fcf5ef2aSThomas Huth 5666fcf5ef2aSThomas Huth /* mfdcrx */ 5667fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5668fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5669fcf5ef2aSThomas Huth { 5670fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5671fcf5ef2aSThomas Huth GEN_PRIV; 5672fcf5ef2aSThomas Huth #else 5673fcf5ef2aSThomas Huth CHK_SV; 5674fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5675fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5676fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5677fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5678fcf5ef2aSThomas Huth } 5679fcf5ef2aSThomas Huth 5680fcf5ef2aSThomas Huth /* mtdcrx */ 5681fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5682fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5683fcf5ef2aSThomas Huth { 5684fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5685fcf5ef2aSThomas Huth GEN_PRIV; 5686fcf5ef2aSThomas Huth #else 5687fcf5ef2aSThomas Huth CHK_SV; 5688fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5689fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5690fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5691fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5692fcf5ef2aSThomas Huth } 5693fcf5ef2aSThomas Huth 5694fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 5695fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 5696fcf5ef2aSThomas Huth { 5697fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5698fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5699fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5700fcf5ef2aSThomas Huth } 5701fcf5ef2aSThomas Huth 5702fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 5703fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 5704fcf5ef2aSThomas Huth { 5705fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5706fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5707fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5708fcf5ef2aSThomas Huth } 5709fcf5ef2aSThomas Huth 5710fcf5ef2aSThomas Huth /* dccci */ 5711fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5712fcf5ef2aSThomas Huth { 5713fcf5ef2aSThomas Huth CHK_SV; 5714fcf5ef2aSThomas Huth /* interpreted as no-op */ 5715fcf5ef2aSThomas Huth } 5716fcf5ef2aSThomas Huth 5717fcf5ef2aSThomas Huth /* dcread */ 5718fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5719fcf5ef2aSThomas Huth { 5720fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5721fcf5ef2aSThomas Huth GEN_PRIV; 5722fcf5ef2aSThomas Huth #else 5723fcf5ef2aSThomas Huth TCGv EA, val; 5724fcf5ef2aSThomas Huth 5725fcf5ef2aSThomas Huth CHK_SV; 5726fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5727fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5728fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5729fcf5ef2aSThomas Huth val = tcg_temp_new(); 5730fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5731fcf5ef2aSThomas Huth tcg_temp_free(val); 5732fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5733fcf5ef2aSThomas Huth tcg_temp_free(EA); 5734fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5735fcf5ef2aSThomas Huth } 5736fcf5ef2aSThomas Huth 5737fcf5ef2aSThomas Huth /* icbt */ 5738fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5739fcf5ef2aSThomas Huth { 5740fcf5ef2aSThomas Huth /* interpreted as no-op */ 5741fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 5742fcf5ef2aSThomas Huth * but does not generate any exception 5743fcf5ef2aSThomas Huth */ 5744fcf5ef2aSThomas Huth } 5745fcf5ef2aSThomas Huth 5746fcf5ef2aSThomas Huth /* iccci */ 5747fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5748fcf5ef2aSThomas Huth { 5749fcf5ef2aSThomas Huth CHK_SV; 5750fcf5ef2aSThomas Huth /* interpreted as no-op */ 5751fcf5ef2aSThomas Huth } 5752fcf5ef2aSThomas Huth 5753fcf5ef2aSThomas Huth /* icread */ 5754fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5755fcf5ef2aSThomas Huth { 5756fcf5ef2aSThomas Huth CHK_SV; 5757fcf5ef2aSThomas Huth /* interpreted as no-op */ 5758fcf5ef2aSThomas Huth } 5759fcf5ef2aSThomas Huth 5760fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5761fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5762fcf5ef2aSThomas Huth { 5763fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5764fcf5ef2aSThomas Huth GEN_PRIV; 5765fcf5ef2aSThomas Huth #else 5766fcf5ef2aSThomas Huth CHK_SV; 5767fcf5ef2aSThomas Huth /* Restore CPU state */ 5768fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 5769fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5770fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5771fcf5ef2aSThomas Huth } 5772fcf5ef2aSThomas Huth 5773fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5774fcf5ef2aSThomas Huth { 5775fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5776fcf5ef2aSThomas Huth GEN_PRIV; 5777fcf5ef2aSThomas Huth #else 5778fcf5ef2aSThomas Huth CHK_SV; 5779fcf5ef2aSThomas Huth /* Restore CPU state */ 5780fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 5781fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5782fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5783fcf5ef2aSThomas Huth } 5784fcf5ef2aSThomas Huth 5785fcf5ef2aSThomas Huth /* BookE specific */ 5786fcf5ef2aSThomas Huth 5787fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5788fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5789fcf5ef2aSThomas Huth { 5790fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5791fcf5ef2aSThomas Huth GEN_PRIV; 5792fcf5ef2aSThomas Huth #else 5793fcf5ef2aSThomas Huth CHK_SV; 5794fcf5ef2aSThomas Huth /* Restore CPU state */ 5795fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 5796fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5797fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5798fcf5ef2aSThomas Huth } 5799fcf5ef2aSThomas Huth 5800fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5801fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5802fcf5ef2aSThomas Huth { 5803fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5804fcf5ef2aSThomas Huth GEN_PRIV; 5805fcf5ef2aSThomas Huth #else 5806fcf5ef2aSThomas Huth CHK_SV; 5807fcf5ef2aSThomas Huth /* Restore CPU state */ 5808fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 5809fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5810fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5811fcf5ef2aSThomas Huth } 5812fcf5ef2aSThomas Huth 5813fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5814fcf5ef2aSThomas Huth 5815fcf5ef2aSThomas Huth /* tlbre */ 5816fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5817fcf5ef2aSThomas Huth { 5818fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5819fcf5ef2aSThomas Huth GEN_PRIV; 5820fcf5ef2aSThomas Huth #else 5821fcf5ef2aSThomas Huth CHK_SV; 5822fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5823fcf5ef2aSThomas Huth case 0: 5824fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5825fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5826fcf5ef2aSThomas Huth break; 5827fcf5ef2aSThomas Huth case 1: 5828fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5829fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5830fcf5ef2aSThomas Huth break; 5831fcf5ef2aSThomas Huth default: 5832fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5833fcf5ef2aSThomas Huth break; 5834fcf5ef2aSThomas Huth } 5835fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5836fcf5ef2aSThomas Huth } 5837fcf5ef2aSThomas Huth 5838fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5839fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5840fcf5ef2aSThomas Huth { 5841fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5842fcf5ef2aSThomas Huth GEN_PRIV; 5843fcf5ef2aSThomas Huth #else 5844fcf5ef2aSThomas Huth TCGv t0; 5845fcf5ef2aSThomas Huth 5846fcf5ef2aSThomas Huth CHK_SV; 5847fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5848fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5849fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5850fcf5ef2aSThomas Huth tcg_temp_free(t0); 5851fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5852fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5853fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5854fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5855fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5856fcf5ef2aSThomas Huth gen_set_label(l1); 5857fcf5ef2aSThomas Huth } 5858fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5859fcf5ef2aSThomas Huth } 5860fcf5ef2aSThomas Huth 5861fcf5ef2aSThomas Huth /* tlbwe */ 5862fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5863fcf5ef2aSThomas Huth { 5864fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5865fcf5ef2aSThomas Huth GEN_PRIV; 5866fcf5ef2aSThomas Huth #else 5867fcf5ef2aSThomas Huth CHK_SV; 5868fcf5ef2aSThomas Huth 5869fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5870fcf5ef2aSThomas Huth case 0: 5871fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5872fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5873fcf5ef2aSThomas Huth break; 5874fcf5ef2aSThomas Huth case 1: 5875fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5876fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5877fcf5ef2aSThomas Huth break; 5878fcf5ef2aSThomas Huth default: 5879fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5880fcf5ef2aSThomas Huth break; 5881fcf5ef2aSThomas Huth } 5882fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5883fcf5ef2aSThomas Huth } 5884fcf5ef2aSThomas Huth 5885fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5886fcf5ef2aSThomas Huth 5887fcf5ef2aSThomas Huth /* tlbre */ 5888fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5889fcf5ef2aSThomas Huth { 5890fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5891fcf5ef2aSThomas Huth GEN_PRIV; 5892fcf5ef2aSThomas Huth #else 5893fcf5ef2aSThomas Huth CHK_SV; 5894fcf5ef2aSThomas Huth 5895fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5896fcf5ef2aSThomas Huth case 0: 5897fcf5ef2aSThomas Huth case 1: 5898fcf5ef2aSThomas Huth case 2: 5899fcf5ef2aSThomas Huth { 5900fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5901fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5902fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5903fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5904fcf5ef2aSThomas Huth } 5905fcf5ef2aSThomas Huth break; 5906fcf5ef2aSThomas Huth default: 5907fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5908fcf5ef2aSThomas Huth break; 5909fcf5ef2aSThomas Huth } 5910fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5911fcf5ef2aSThomas Huth } 5912fcf5ef2aSThomas Huth 5913fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5914fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5915fcf5ef2aSThomas Huth { 5916fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5917fcf5ef2aSThomas Huth GEN_PRIV; 5918fcf5ef2aSThomas Huth #else 5919fcf5ef2aSThomas Huth TCGv t0; 5920fcf5ef2aSThomas Huth 5921fcf5ef2aSThomas Huth CHK_SV; 5922fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5923fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5924fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5925fcf5ef2aSThomas Huth tcg_temp_free(t0); 5926fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5927fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5928fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5929fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5930fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5931fcf5ef2aSThomas Huth gen_set_label(l1); 5932fcf5ef2aSThomas Huth } 5933fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5934fcf5ef2aSThomas Huth } 5935fcf5ef2aSThomas Huth 5936fcf5ef2aSThomas Huth /* tlbwe */ 5937fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5938fcf5ef2aSThomas Huth { 5939fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5940fcf5ef2aSThomas Huth GEN_PRIV; 5941fcf5ef2aSThomas Huth #else 5942fcf5ef2aSThomas Huth CHK_SV; 5943fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5944fcf5ef2aSThomas Huth case 0: 5945fcf5ef2aSThomas Huth case 1: 5946fcf5ef2aSThomas Huth case 2: 5947fcf5ef2aSThomas Huth { 5948fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5949fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5950fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5951fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5952fcf5ef2aSThomas Huth } 5953fcf5ef2aSThomas Huth break; 5954fcf5ef2aSThomas Huth default: 5955fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5956fcf5ef2aSThomas Huth break; 5957fcf5ef2aSThomas Huth } 5958fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5959fcf5ef2aSThomas Huth } 5960fcf5ef2aSThomas Huth 5961fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5962fcf5ef2aSThomas Huth 5963fcf5ef2aSThomas Huth /* tlbre */ 5964fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5965fcf5ef2aSThomas Huth { 5966fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5967fcf5ef2aSThomas Huth GEN_PRIV; 5968fcf5ef2aSThomas Huth #else 5969fcf5ef2aSThomas Huth CHK_SV; 5970fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5971fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5972fcf5ef2aSThomas Huth } 5973fcf5ef2aSThomas Huth 5974fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5975fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5976fcf5ef2aSThomas Huth { 5977fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5978fcf5ef2aSThomas Huth GEN_PRIV; 5979fcf5ef2aSThomas Huth #else 5980fcf5ef2aSThomas Huth TCGv t0; 5981fcf5ef2aSThomas Huth 5982fcf5ef2aSThomas Huth CHK_SV; 5983fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5984fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5985fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 5986fcf5ef2aSThomas Huth } else { 5987fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 5988fcf5ef2aSThomas Huth } 5989fcf5ef2aSThomas Huth 5990fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 5991fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5992fcf5ef2aSThomas Huth tcg_temp_free(t0); 5993fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5994fcf5ef2aSThomas Huth } 5995fcf5ef2aSThomas Huth 5996fcf5ef2aSThomas Huth /* tlbwe */ 5997fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5998fcf5ef2aSThomas Huth { 5999fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6000fcf5ef2aSThomas Huth GEN_PRIV; 6001fcf5ef2aSThomas Huth #else 6002fcf5ef2aSThomas Huth CHK_SV; 6003fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6004fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6005fcf5ef2aSThomas Huth } 6006fcf5ef2aSThomas Huth 6007fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6008fcf5ef2aSThomas Huth { 6009fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6010fcf5ef2aSThomas Huth GEN_PRIV; 6011fcf5ef2aSThomas Huth #else 6012fcf5ef2aSThomas Huth TCGv t0; 6013fcf5ef2aSThomas Huth 6014fcf5ef2aSThomas Huth CHK_SV; 6015fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6016fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6017fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6018fcf5ef2aSThomas Huth tcg_temp_free(t0); 6019fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6020fcf5ef2aSThomas Huth } 6021fcf5ef2aSThomas Huth 6022fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6023fcf5ef2aSThomas Huth { 6024fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6025fcf5ef2aSThomas Huth GEN_PRIV; 6026fcf5ef2aSThomas Huth #else 6027fcf5ef2aSThomas Huth TCGv t0; 6028fcf5ef2aSThomas Huth 6029fcf5ef2aSThomas Huth CHK_SV; 6030fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6031fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6032fcf5ef2aSThomas Huth 6033fcf5ef2aSThomas Huth switch((ctx->opcode >> 21) & 0x3) { 6034fcf5ef2aSThomas Huth case 0: 6035fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6036fcf5ef2aSThomas Huth break; 6037fcf5ef2aSThomas Huth case 1: 6038fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6039fcf5ef2aSThomas Huth break; 6040fcf5ef2aSThomas Huth case 3: 6041fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6042fcf5ef2aSThomas Huth break; 6043fcf5ef2aSThomas Huth default: 6044fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6045fcf5ef2aSThomas Huth break; 6046fcf5ef2aSThomas Huth } 6047fcf5ef2aSThomas Huth 6048fcf5ef2aSThomas Huth tcg_temp_free(t0); 6049fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6050fcf5ef2aSThomas Huth } 6051fcf5ef2aSThomas Huth 6052fcf5ef2aSThomas Huth 6053fcf5ef2aSThomas Huth /* wrtee */ 6054fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6055fcf5ef2aSThomas Huth { 6056fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6057fcf5ef2aSThomas Huth GEN_PRIV; 6058fcf5ef2aSThomas Huth #else 6059fcf5ef2aSThomas Huth TCGv t0; 6060fcf5ef2aSThomas Huth 6061fcf5ef2aSThomas Huth CHK_SV; 6062fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6063fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6064fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6065fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6066fcf5ef2aSThomas Huth tcg_temp_free(t0); 6067fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception 6068fcf5ef2aSThomas Huth * if we just set msr_ee to 1 6069fcf5ef2aSThomas Huth */ 6070fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6071fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6072fcf5ef2aSThomas Huth } 6073fcf5ef2aSThomas Huth 6074fcf5ef2aSThomas Huth /* wrteei */ 6075fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6076fcf5ef2aSThomas Huth { 6077fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6078fcf5ef2aSThomas Huth GEN_PRIV; 6079fcf5ef2aSThomas Huth #else 6080fcf5ef2aSThomas Huth CHK_SV; 6081fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6082fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6083fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6084fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6085fcf5ef2aSThomas Huth } else { 6086fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6087fcf5ef2aSThomas Huth } 6088fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6089fcf5ef2aSThomas Huth } 6090fcf5ef2aSThomas Huth 6091fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6092fcf5ef2aSThomas Huth 6093fcf5ef2aSThomas Huth /* dlmzb */ 6094fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6095fcf5ef2aSThomas Huth { 6096fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6097fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6098fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6099fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6100fcf5ef2aSThomas Huth } 6101fcf5ef2aSThomas Huth 6102fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6103fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6104fcf5ef2aSThomas Huth { 6105fcf5ef2aSThomas Huth /* interpreted as no-op */ 6106fcf5ef2aSThomas Huth } 6107fcf5ef2aSThomas Huth 6108fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6109fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6110fcf5ef2aSThomas Huth { 6111fcf5ef2aSThomas Huth /* interpreted as no-op */ 6112fcf5ef2aSThomas Huth } 6113fcf5ef2aSThomas Huth 6114fcf5ef2aSThomas Huth /* icbt */ 6115fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6116fcf5ef2aSThomas Huth { 6117fcf5ef2aSThomas Huth /* interpreted as no-op */ 6118fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6119fcf5ef2aSThomas Huth * but does not generate any exception 6120fcf5ef2aSThomas Huth */ 6121fcf5ef2aSThomas Huth } 6122fcf5ef2aSThomas Huth 6123fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6124fcf5ef2aSThomas Huth 6125fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6126fcf5ef2aSThomas Huth { 6127fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6128fcf5ef2aSThomas Huth GEN_PRIV; 6129fcf5ef2aSThomas Huth #else 6130fcf5ef2aSThomas Huth CHK_SV; 6131fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6132fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6133fcf5ef2aSThomas Huth } 6134fcf5ef2aSThomas Huth 6135fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6136fcf5ef2aSThomas Huth { 6137fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6138fcf5ef2aSThomas Huth GEN_PRIV; 6139fcf5ef2aSThomas Huth #else 6140fcf5ef2aSThomas Huth CHK_SV; 6141fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6142fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6143fcf5ef2aSThomas Huth } 6144fcf5ef2aSThomas Huth 6145fcf5ef2aSThomas Huth 6146fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6147fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6148fcf5ef2aSThomas Huth { 6149fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6150fcf5ef2aSThomas Huth 6151fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6152fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6153fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6154fcf5ef2aSThomas Huth } 6155fcf5ef2aSThomas Huth 6156fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6157fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6158fcf5ef2aSThomas Huth { 6159fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6160fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6161fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6162fcf5ef2aSThomas Huth 6163fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6164fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6165fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6166fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6167fcf5ef2aSThomas Huth } else { 6168fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6169fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6170fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6171fcf5ef2aSThomas Huth } 6172fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6173fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6174fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6175fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6176fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6177fcf5ef2aSThomas Huth } 6178fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6179fcf5ef2aSThomas Huth 6180fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6181fcf5ef2aSThomas Huth { 6182fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6183fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6184fcf5ef2aSThomas Huth return; 6185fcf5ef2aSThomas Huth } 6186fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6187fcf5ef2aSThomas Huth } 6188fcf5ef2aSThomas Huth 6189fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6190fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6191fcf5ef2aSThomas Huth { \ 6192fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6193fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6194fcf5ef2aSThomas Huth return; \ 6195fcf5ef2aSThomas Huth } \ 6196fcf5ef2aSThomas Huth /* Because tbegin always fails in QEMU, these user \ 6197fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6198fcf5ef2aSThomas Huth * \ 6199fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6200fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6201fcf5ef2aSThomas Huth */ \ 6202fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6203fcf5ef2aSThomas Huth } 6204fcf5ef2aSThomas Huth 6205fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6206fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6207fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6208fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6209fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6210fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6211fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6212b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6213b8b4576eSSuraj Jitindar Singh { 6214b8b4576eSSuraj Jitindar Singh // Do Nothing 6215b8b4576eSSuraj Jitindar Singh } 6216fcf5ef2aSThomas Huth 621780b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 621880b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 621980b8c1eeSNikunj A Dadhania { \ 622080b8c1eeSNikunj A Dadhania /* Generate invalid exception until \ 622180b8c1eeSNikunj A Dadhania * we have an implementation of the copy \ 622280b8c1eeSNikunj A Dadhania * paste facility \ 622380b8c1eeSNikunj A Dadhania */ \ 622480b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 622580b8c1eeSNikunj A Dadhania } 622680b8c1eeSNikunj A Dadhania 622780b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 622880b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 622980b8c1eeSNikunj A Dadhania 6230fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6231fcf5ef2aSThomas Huth { 6232fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6233fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6234fcf5ef2aSThomas Huth return; 6235fcf5ef2aSThomas Huth } 6236fcf5ef2aSThomas Huth /* Because tbegin always fails, the tcheck implementation 6237fcf5ef2aSThomas Huth * is simple: 6238fcf5ef2aSThomas Huth * 6239fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6240fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6241fcf5ef2aSThomas Huth */ 6242fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6243fcf5ef2aSThomas Huth } 6244fcf5ef2aSThomas Huth 6245fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6246fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6247fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6248fcf5ef2aSThomas Huth { \ 6249fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6250fcf5ef2aSThomas Huth } 6251fcf5ef2aSThomas Huth 6252fcf5ef2aSThomas Huth #else 6253fcf5ef2aSThomas Huth 6254fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6255fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6256fcf5ef2aSThomas Huth { \ 6257fcf5ef2aSThomas Huth CHK_SV; \ 6258fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6259fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6260fcf5ef2aSThomas Huth return; \ 6261fcf5ef2aSThomas Huth } \ 6262fcf5ef2aSThomas Huth /* Because tbegin always fails, the implementation is \ 6263fcf5ef2aSThomas Huth * simple: \ 6264fcf5ef2aSThomas Huth * \ 6265fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6266fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6267fcf5ef2aSThomas Huth */ \ 6268fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6269fcf5ef2aSThomas Huth } 6270fcf5ef2aSThomas Huth 6271fcf5ef2aSThomas Huth #endif 6272fcf5ef2aSThomas Huth 6273fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6274fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6275fcf5ef2aSThomas Huth 6276fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6277fcf5ef2aSThomas Huth 6278fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6279fcf5ef2aSThomas Huth 6280fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6281fcf5ef2aSThomas Huth 6282fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6283fcf5ef2aSThomas Huth 6284fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6285fcf5ef2aSThomas Huth 62865cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 62875cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 62885cb091a4SNikunj A Dadhania { 62895cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 62905cb091a4SNikunj A Dadhania case 0: /* lfdp */ 62915cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 62925cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 62935cb091a4SNikunj A Dadhania } 62945cb091a4SNikunj A Dadhania break; 62955cb091a4SNikunj A Dadhania case 2: /* lxsd */ 62965cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 62975cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 62985cb091a4SNikunj A Dadhania } 62995cb091a4SNikunj A Dadhania break; 63005cb091a4SNikunj A Dadhania case 3: /* lxssp */ 63015cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 63025cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 63035cb091a4SNikunj A Dadhania } 63045cb091a4SNikunj A Dadhania break; 63055cb091a4SNikunj A Dadhania } 63065cb091a4SNikunj A Dadhania return gen_invalid(ctx); 63075cb091a4SNikunj A Dadhania } 63085cb091a4SNikunj A Dadhania 6309d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6310e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6311e3001664SNikunj A Dadhania { 6312e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6313e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6314e3001664SNikunj A Dadhania case 1: /* lxv */ 6315d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6316d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6317d59ba583SNikunj A Dadhania } 6318e3001664SNikunj A Dadhania break; 6319e3001664SNikunj A Dadhania case 5: /* stxv */ 6320d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6321d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6322d59ba583SNikunj A Dadhania } 6323e3001664SNikunj A Dadhania break; 6324e3001664SNikunj A Dadhania } 6325e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6326e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6327e3001664SNikunj A Dadhania case 0: /* stfdp */ 6328e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6329e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6330e3001664SNikunj A Dadhania } 6331e3001664SNikunj A Dadhania break; 6332e3001664SNikunj A Dadhania case 2: /* stxsd */ 6333e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6334e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6335e3001664SNikunj A Dadhania } 6336e3001664SNikunj A Dadhania break; 6337e3001664SNikunj A Dadhania case 3: /* stxssp */ 6338e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6339e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6340e3001664SNikunj A Dadhania } 6341e3001664SNikunj A Dadhania break; 6342e3001664SNikunj A Dadhania } 6343e3001664SNikunj A Dadhania } 6344e3001664SNikunj A Dadhania return gen_invalid(ctx); 6345e3001664SNikunj A Dadhania } 6346e3001664SNikunj A Dadhania 6347fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6348fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6349fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6350fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6351fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6352fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6353fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6354fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6355fcf5ef2aSThomas Huth #endif 6356fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6357fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6358fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6359fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6360fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6361fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6362fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6363fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6364fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6365fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6366fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6367fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6368fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6369fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6370fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6371fcf5ef2aSThomas Huth #endif 6372fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6373fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6374fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6375fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6376fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6377fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6378fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 637980b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6380b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 638180b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6382fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6383fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6384fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6385fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6386fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6387fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6388fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6389fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6390fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6391fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6392fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6393fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6394fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6395fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6396fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6397fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6398fcf5ef2aSThomas Huth #endif 6399fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6400fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6401fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6402fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6403fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6404fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6405fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6406fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6407fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6408fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6409fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6410fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6411fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6412fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6413fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6414fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6415fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6416fcf5ef2aSThomas Huth #endif 6417fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6418fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6419fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6420fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6421fcf5ef2aSThomas Huth #endif 64225cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 64235cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6424d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6425e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6426fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6427fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6428fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6429fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6430fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6431fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6432fcf5ef2aSThomas Huth GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), 6433fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6434fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6435fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6436fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6437a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6438a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6439fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6440fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6441fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6442fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6443a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6444a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6445fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6446fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6447fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6448fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6449fcf5ef2aSThomas Huth #endif 6450fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6451fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6452c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6453fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6454fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6455fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6456fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6457fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6458fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6459fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6460fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6461fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6462cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6463fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6464fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6465fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6466fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6467fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6468fcf5ef2aSThomas Huth #endif 6469fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6470fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6471fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6472fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6473fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6474fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6475fcf5ef2aSThomas Huth #endif 6476fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6477fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6478fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6479fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6480fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6481fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6482fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6483fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6484fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6485fcf5ef2aSThomas Huth #endif 6486fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6487fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6488fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6489fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6490fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6491fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6492fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6493fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6494fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6495fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6496fcf5ef2aSThomas Huth GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), 6497fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6498fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6499fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6500fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6501fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6502fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6503fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6504fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6505fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6506fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6507fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6508fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6509fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6510fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6511fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6512fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6513fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6514fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6515fcf5ef2aSThomas Huth #endif 6516fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6517fcf5ef2aSThomas Huth /* XXX Those instructions will need to be handled differently for 6518fcf5ef2aSThomas Huth * different ISA versions */ 6519fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6520fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6521fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6522fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6523fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6524fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6525a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 652662d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6527fcf5ef2aSThomas Huth #endif 6528fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6529fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6530fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6531fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6532fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6533fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6534fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6535fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6536fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6537fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6538fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6539fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6540fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6541fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6542fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6543fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6544fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6545fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6546fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6547fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6548fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6549fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6550fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6551fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6552fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6553fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6554fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6555fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6556fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6557fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6558fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6559fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6560fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6561fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6562fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6563fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6564fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6565fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6566fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6567fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6568fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6569fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6570fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6571fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6572fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6573fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6574fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6575fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6576fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6577fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6578fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6579fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6580fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6581fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6582fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6583fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6584fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6585fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6586fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6587fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6588fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6589fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6590fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6591fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6592fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6593fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6594fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6595fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6596fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6597fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6598fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6599fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6600fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6601fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6602fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6603fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6604fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6605fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6606fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6607fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6608fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6609fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6610fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6611fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6612fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6613fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6614fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6615fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6616fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6617fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6618fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6619fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6620fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6621fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6622fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6623fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6624fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6625fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6626fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6627fcf5ef2aSThomas Huth GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6628fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6629fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6630fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6631fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6632fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6633fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6634fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6635fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6636fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6637fcf5ef2aSThomas Huth PPC2_ISA300), 6638fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6639fcf5ef2aSThomas Huth #endif 6640fcf5ef2aSThomas Huth 6641fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6642fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6643fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6644fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6645fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6646fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6647fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6648fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6649fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6650fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6651fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6652fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6653fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6654fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6655fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6656fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6657fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6658fcf5ef2aSThomas Huth 6659fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6660fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6661fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6662fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6663fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6664fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6665fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6666fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6667fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6668fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6669fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6670fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6671fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6672fcf5ef2aSThomas Huth 6673fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6674fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6675fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6676fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6677fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6678fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6679fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6680fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6681fcf5ef2aSThomas Huth 6682fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6683fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6684fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6685fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6686fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6687fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6688fcf5ef2aSThomas Huth 6689fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6690fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6691fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6692fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6693fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6694fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6695fcf5ef2aSThomas Huth #endif 6696fcf5ef2aSThomas Huth 6697fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6698fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6699fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6700fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6701fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6702fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6703fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6704fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6705fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6706fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6707fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6708fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6709fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6710fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6711fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6712fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6713fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6714fcf5ef2aSThomas Huth 6715fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6716fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6717fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6718fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6719fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6720fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6721fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6722fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6723fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6724fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6725fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6726fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6727fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6728fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6729fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6730fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6731fcf5ef2aSThomas Huth #endif 6732fcf5ef2aSThomas Huth 6733fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6734fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6735fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6736fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6737fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6738fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6739fcf5ef2aSThomas Huth PPC_64B) 6740fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6741fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6742fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6743fcf5ef2aSThomas Huth PPC_64B), \ 6744fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6745fcf5ef2aSThomas Huth PPC_64B), \ 6746fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6747fcf5ef2aSThomas Huth PPC_64B) 6748fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6749fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6750fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6751fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6752fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6753fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6754fcf5ef2aSThomas Huth #endif 6755fcf5ef2aSThomas Huth 6756fcf5ef2aSThomas Huth #undef GEN_LD 6757fcf5ef2aSThomas Huth #undef GEN_LDU 6758fcf5ef2aSThomas Huth #undef GEN_LDUX 6759fcf5ef2aSThomas Huth #undef GEN_LDX_E 6760fcf5ef2aSThomas Huth #undef GEN_LDS 6761fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 6762fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6763fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 6764fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 6765fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 6766fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6767fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6768fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6769fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 6770fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 6771fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 6772fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 6773fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 6774fcf5ef2aSThomas Huth 6775fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 6776fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 6777fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 6778fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 6779fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6780fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 6781fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 6782fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 6783fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 6784fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6785fcf5ef2aSThomas Huth 6786fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6787fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6788fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6789fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6790fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6791fcf5ef2aSThomas Huth #endif 6792fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6793fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6794fcf5ef2aSThomas Huth 6795fcf5ef2aSThomas Huth #undef GEN_ST 6796fcf5ef2aSThomas Huth #undef GEN_STU 6797fcf5ef2aSThomas Huth #undef GEN_STUX 6798fcf5ef2aSThomas Huth #undef GEN_STX_E 6799fcf5ef2aSThomas Huth #undef GEN_STS 6800fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 6801fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6802fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 6803fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 6804fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 6805fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6806fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6807fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6808fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 6809fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 6810fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 6811fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 6812fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 6813fcf5ef2aSThomas Huth 6814fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 6815fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 6816fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 6817fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6818fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 6819fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 6820fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6821fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6822fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6823fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6824fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6825fcf5ef2aSThomas Huth #endif 6826fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6827fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6828fcf5ef2aSThomas Huth 6829fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6830fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6831fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6832fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6833fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6834fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6835fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6836fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6837fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6838fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6839fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6840fcf5ef2aSThomas Huth 6841fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6842fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6843fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6844fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6845fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6846fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6847fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6848fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6849fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6850fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6851fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6852fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6853fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6854fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6855fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6856fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6857fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6858fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6859fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6860fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6861fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6862fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6863fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6864fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6865fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6866fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6867fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6868fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6869fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6870fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6871fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6872fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6873fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6874fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6875fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6876fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6877fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6878fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6879fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6880fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6881fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6882fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6883fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6884fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6885fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6886fcf5ef2aSThomas Huth 6887fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6888fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6889fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6890fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6891fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6892fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6893fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6894fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6895fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6896fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6897fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6898fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6899fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6900fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6901fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6902fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6903fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6904fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6905fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6906fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6907fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6908fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6909fcf5ef2aSThomas Huth 6910fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 6911fcf5ef2aSThomas Huth 6912fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 6913fcf5ef2aSThomas Huth 6914fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 6915fcf5ef2aSThomas Huth 6916fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 6917fcf5ef2aSThomas Huth 6918fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 6919fcf5ef2aSThomas Huth }; 6920fcf5ef2aSThomas Huth 6921fcf5ef2aSThomas Huth #include "helper_regs.h" 6922fcf5ef2aSThomas Huth #include "translate_init.c" 6923fcf5ef2aSThomas Huth 6924fcf5ef2aSThomas Huth /*****************************************************************************/ 6925fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 6926fcf5ef2aSThomas Huth void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 6927fcf5ef2aSThomas Huth int flags) 6928fcf5ef2aSThomas Huth { 6929fcf5ef2aSThomas Huth #define RGPL 4 6930fcf5ef2aSThomas Huth #define RFPL 4 6931fcf5ef2aSThomas Huth 6932fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 6933fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 6934fcf5ef2aSThomas Huth int i; 6935fcf5ef2aSThomas Huth 6936fcf5ef2aSThomas Huth cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 6937fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 6938fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 6939fcf5ef2aSThomas Huth cs->cpu_index); 6940fcf5ef2aSThomas Huth cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 6941fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 6942fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 6943fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 6944fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 6945fcf5ef2aSThomas Huth cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 6946fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 6947fcf5ef2aSThomas Huth " DECR %08" PRIu32 6948fcf5ef2aSThomas Huth #endif 6949fcf5ef2aSThomas Huth "\n", 6950fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 6951fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 6952fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 6953fcf5ef2aSThomas Huth #endif 6954fcf5ef2aSThomas Huth ); 6955fcf5ef2aSThomas Huth #endif 6956fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 6957fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == 0) 6958fcf5ef2aSThomas Huth cpu_fprintf(f, "GPR%02d", i); 6959fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 6960fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == (RGPL - 1)) 6961fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 6962fcf5ef2aSThomas Huth } 6963fcf5ef2aSThomas Huth cpu_fprintf(f, "CR "); 6964fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 6965fcf5ef2aSThomas Huth cpu_fprintf(f, "%01x", env->crf[i]); 6966fcf5ef2aSThomas Huth cpu_fprintf(f, " ["); 6967fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 6968fcf5ef2aSThomas Huth char a = '-'; 6969fcf5ef2aSThomas Huth if (env->crf[i] & 0x08) 6970fcf5ef2aSThomas Huth a = 'L'; 6971fcf5ef2aSThomas Huth else if (env->crf[i] & 0x04) 6972fcf5ef2aSThomas Huth a = 'G'; 6973fcf5ef2aSThomas Huth else if (env->crf[i] & 0x02) 6974fcf5ef2aSThomas Huth a = 'E'; 6975fcf5ef2aSThomas Huth cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 6976fcf5ef2aSThomas Huth } 6977fcf5ef2aSThomas Huth cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 6978fcf5ef2aSThomas Huth env->reserve_addr); 6979fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 6980fcf5ef2aSThomas Huth if ((i & (RFPL - 1)) == 0) 6981fcf5ef2aSThomas Huth cpu_fprintf(f, "FPR%02d", i); 6982fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 6983fcf5ef2aSThomas Huth if ((i & (RFPL - 1)) == (RFPL - 1)) 6984fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 6985fcf5ef2aSThomas Huth } 6986fcf5ef2aSThomas Huth cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 6987fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 6988fcf5ef2aSThomas Huth cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 6989fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 6990fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 6991fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 6992fcf5ef2aSThomas Huth 6993fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 6994fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 6995fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 6996fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 6997fcf5ef2aSThomas Huth 6998fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 6999fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7000fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7001fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7002fcf5ef2aSThomas Huth 7003fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7004fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7005fcf5ef2aSThomas Huth env->excp_model == POWERPC_EXCP_POWER8) { 7006fcf5ef2aSThomas Huth cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7007fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7008fcf5ef2aSThomas Huth } 7009fcf5ef2aSThomas Huth #endif 7010fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 7011fcf5ef2aSThomas Huth cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7012fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7013fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7014fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7015fcf5ef2aSThomas Huth 7016fcf5ef2aSThomas Huth cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7017fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7018fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7019fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7020fcf5ef2aSThomas Huth 7021fcf5ef2aSThomas Huth cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7022fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7023fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7024fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7025fcf5ef2aSThomas Huth 7026fcf5ef2aSThomas Huth cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7027fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7028fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7029fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7030fcf5ef2aSThomas Huth 7031fcf5ef2aSThomas Huth /* FSL-specific */ 7032fcf5ef2aSThomas Huth cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7033fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7034fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7035fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7036fcf5ef2aSThomas Huth 7037fcf5ef2aSThomas Huth /* 7038fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7039fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7040fcf5ef2aSThomas Huth */ 7041fcf5ef2aSThomas Huth } 7042fcf5ef2aSThomas Huth 7043fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7044fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 7045fcf5ef2aSThomas Huth cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7046fcf5ef2aSThomas Huth } 7047fcf5ef2aSThomas Huth #endif 7048fcf5ef2aSThomas Huth 7049d801a61eSSuraj Jitindar Singh if (env->spr_cb[SPR_LPCR].name) 7050d801a61eSSuraj Jitindar Singh cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7051d801a61eSSuraj Jitindar Singh 7052fcf5ef2aSThomas Huth switch (env->mmu_model) { 7053fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7054fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7055fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7056fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7057fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7058fcf5ef2aSThomas Huth case POWERPC_MMU_64B: 7059fcf5ef2aSThomas Huth case POWERPC_MMU_2_03: 7060fcf5ef2aSThomas Huth case POWERPC_MMU_2_06: 7061fcf5ef2aSThomas Huth case POWERPC_MMU_2_06a: 7062fcf5ef2aSThomas Huth case POWERPC_MMU_2_07: 7063fcf5ef2aSThomas Huth case POWERPC_MMU_2_07a: 7064fcf5ef2aSThomas Huth #endif 7065fcf5ef2aSThomas Huth cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx 7066fcf5ef2aSThomas Huth " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], 7067fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7068fcf5ef2aSThomas Huth break; 7069fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 7070fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7071fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7072fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7073fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7074fcf5ef2aSThomas Huth 7075fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7076fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7077fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7078fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7079fcf5ef2aSThomas Huth 7080fcf5ef2aSThomas Huth cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7081fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7082fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7083fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7084fcf5ef2aSThomas Huth break; 7085fcf5ef2aSThomas Huth default: 7086fcf5ef2aSThomas Huth break; 7087fcf5ef2aSThomas Huth } 7088fcf5ef2aSThomas Huth #endif 7089fcf5ef2aSThomas Huth 7090fcf5ef2aSThomas Huth #undef RGPL 7091fcf5ef2aSThomas Huth #undef RFPL 7092fcf5ef2aSThomas Huth } 7093fcf5ef2aSThomas Huth 7094fcf5ef2aSThomas Huth void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7095fcf5ef2aSThomas Huth fprintf_function cpu_fprintf, int flags) 7096fcf5ef2aSThomas Huth { 7097fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7098fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7099fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7100fcf5ef2aSThomas Huth int op1, op2, op3; 7101fcf5ef2aSThomas Huth 7102fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7103fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7104fcf5ef2aSThomas Huth handler = t1[op1]; 7105fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7106fcf5ef2aSThomas Huth t2 = ind_table(handler); 7107fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7108fcf5ef2aSThomas Huth handler = t2[op2]; 7109fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7110fcf5ef2aSThomas Huth t3 = ind_table(handler); 7111fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7112fcf5ef2aSThomas Huth handler = t3[op3]; 7113fcf5ef2aSThomas Huth if (handler->count == 0) 7114fcf5ef2aSThomas Huth continue; 7115fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7116fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7117fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7118fcf5ef2aSThomas Huth handler->oname, 7119fcf5ef2aSThomas Huth handler->count, handler->count); 7120fcf5ef2aSThomas Huth } 7121fcf5ef2aSThomas Huth } else { 7122fcf5ef2aSThomas Huth if (handler->count == 0) 7123fcf5ef2aSThomas Huth continue; 7124fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7125fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7126fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7127fcf5ef2aSThomas Huth handler->count, handler->count); 7128fcf5ef2aSThomas Huth } 7129fcf5ef2aSThomas Huth } 7130fcf5ef2aSThomas Huth } else { 7131fcf5ef2aSThomas Huth if (handler->count == 0) 7132fcf5ef2aSThomas Huth continue; 7133fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7134fcf5ef2aSThomas Huth " %" PRId64 "\n", 7135fcf5ef2aSThomas Huth op1, op1, handler->oname, 7136fcf5ef2aSThomas Huth handler->count, handler->count); 7137fcf5ef2aSThomas Huth } 7138fcf5ef2aSThomas Huth } 7139fcf5ef2aSThomas Huth #endif 7140fcf5ef2aSThomas Huth } 7141fcf5ef2aSThomas Huth 7142fcf5ef2aSThomas Huth /*****************************************************************************/ 7143fcf5ef2aSThomas Huth void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) 7144fcf5ef2aSThomas Huth { 7145fcf5ef2aSThomas Huth PowerPCCPU *cpu = ppc_env_get_cpu(env); 7146fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 7147fcf5ef2aSThomas Huth DisasContext ctx, *ctxp = &ctx; 7148fcf5ef2aSThomas Huth opc_handler_t **table, *handler; 7149fcf5ef2aSThomas Huth target_ulong pc_start; 7150fcf5ef2aSThomas Huth int num_insns; 7151fcf5ef2aSThomas Huth int max_insns; 7152fcf5ef2aSThomas Huth 7153fcf5ef2aSThomas Huth pc_start = tb->pc; 7154fcf5ef2aSThomas Huth ctx.nip = pc_start; 7155fcf5ef2aSThomas Huth ctx.tb = tb; 7156fcf5ef2aSThomas Huth ctx.exception = POWERPC_EXCP_NONE; 7157fcf5ef2aSThomas Huth ctx.spr_cb = env->spr_cb; 7158fcf5ef2aSThomas Huth ctx.pr = msr_pr; 7159fcf5ef2aSThomas Huth ctx.mem_idx = env->dmmu_idx; 7160fcf5ef2aSThomas Huth ctx.dr = msr_dr; 7161fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7162fcf5ef2aSThomas Huth ctx.hv = msr_hv || !env->has_hv_mode; 7163fcf5ef2aSThomas Huth #endif 7164fcf5ef2aSThomas Huth ctx.insns_flags = env->insns_flags; 7165fcf5ef2aSThomas Huth ctx.insns_flags2 = env->insns_flags2; 7166fcf5ef2aSThomas Huth ctx.access_type = -1; 7167fcf5ef2aSThomas Huth ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7168fcf5ef2aSThomas Huth ctx.le_mode = !!(env->hflags & (1 << MSR_LE)); 7169fcf5ef2aSThomas Huth ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; 7170fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7171fcf5ef2aSThomas Huth ctx.sf_mode = msr_is_64bit(env, env->msr); 7172fcf5ef2aSThomas Huth ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7173fcf5ef2aSThomas Huth #endif 7174fcf5ef2aSThomas Huth if (env->mmu_model == POWERPC_MMU_32B || 7175fcf5ef2aSThomas Huth env->mmu_model == POWERPC_MMU_601 || 7176fcf5ef2aSThomas Huth (env->mmu_model & POWERPC_MMU_64B)) 7177fcf5ef2aSThomas Huth ctx.lazy_tlb_flush = true; 7178fcf5ef2aSThomas Huth 7179fcf5ef2aSThomas Huth ctx.fpu_enabled = !!msr_fp; 7180fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7181fcf5ef2aSThomas Huth ctx.spe_enabled = !!msr_spe; 7182fcf5ef2aSThomas Huth else 7183fcf5ef2aSThomas Huth ctx.spe_enabled = false; 7184fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7185fcf5ef2aSThomas Huth ctx.altivec_enabled = !!msr_vr; 7186fcf5ef2aSThomas Huth else 7187fcf5ef2aSThomas Huth ctx.altivec_enabled = false; 7188fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7189fcf5ef2aSThomas Huth ctx.vsx_enabled = !!msr_vsx; 7190fcf5ef2aSThomas Huth } else { 7191fcf5ef2aSThomas Huth ctx.vsx_enabled = false; 7192fcf5ef2aSThomas Huth } 7193fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7194fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7195fcf5ef2aSThomas Huth ctx.tm_enabled = !!msr_tm; 7196fcf5ef2aSThomas Huth } else { 7197fcf5ef2aSThomas Huth ctx.tm_enabled = false; 7198fcf5ef2aSThomas Huth } 7199fcf5ef2aSThomas Huth #endif 7200fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7201fcf5ef2aSThomas Huth ctx.singlestep_enabled = CPU_SINGLE_STEP; 7202fcf5ef2aSThomas Huth else 7203fcf5ef2aSThomas Huth ctx.singlestep_enabled = 0; 7204fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7205fcf5ef2aSThomas Huth ctx.singlestep_enabled |= CPU_BRANCH_STEP; 7206fcf5ef2aSThomas Huth if (unlikely(cs->singlestep_enabled)) { 7207fcf5ef2aSThomas Huth ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7208fcf5ef2aSThomas Huth } 7209fcf5ef2aSThomas Huth #if defined (DO_SINGLE_STEP) && 0 7210fcf5ef2aSThomas Huth /* Single step trace mode */ 7211fcf5ef2aSThomas Huth msr_se = 1; 7212fcf5ef2aSThomas Huth #endif 7213fcf5ef2aSThomas Huth num_insns = 0; 7214fcf5ef2aSThomas Huth max_insns = tb->cflags & CF_COUNT_MASK; 7215fcf5ef2aSThomas Huth if (max_insns == 0) { 7216fcf5ef2aSThomas Huth max_insns = CF_COUNT_MASK; 7217fcf5ef2aSThomas Huth } 7218fcf5ef2aSThomas Huth if (max_insns > TCG_MAX_INSNS) { 7219fcf5ef2aSThomas Huth max_insns = TCG_MAX_INSNS; 7220fcf5ef2aSThomas Huth } 7221fcf5ef2aSThomas Huth 7222fcf5ef2aSThomas Huth gen_tb_start(tb); 7223fcf5ef2aSThomas Huth tcg_clear_temp_count(); 7224fcf5ef2aSThomas Huth /* Set env in case of segfault during code fetch */ 7225fcf5ef2aSThomas Huth while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) { 7226fcf5ef2aSThomas Huth tcg_gen_insn_start(ctx.nip); 7227fcf5ef2aSThomas Huth num_insns++; 7228fcf5ef2aSThomas Huth 7229fcf5ef2aSThomas Huth if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { 7230fcf5ef2aSThomas Huth gen_debug_exception(ctxp); 7231fcf5ef2aSThomas Huth /* The address covered by the breakpoint must be included in 7232fcf5ef2aSThomas Huth [tb->pc, tb->pc + tb->size) in order to for it to be 7233fcf5ef2aSThomas Huth properly cleared -- thus we increment the PC here so that 7234fcf5ef2aSThomas Huth the logic setting tb->size below does the right thing. */ 7235fcf5ef2aSThomas Huth ctx.nip += 4; 7236fcf5ef2aSThomas Huth break; 7237fcf5ef2aSThomas Huth } 7238fcf5ef2aSThomas Huth 7239fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7240fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7241fcf5ef2aSThomas Huth ctx.nip, ctx.mem_idx, (int)msr_ir); 7242fcf5ef2aSThomas Huth if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) 7243fcf5ef2aSThomas Huth gen_io_start(); 7244fcf5ef2aSThomas Huth if (unlikely(need_byteswap(&ctx))) { 7245fcf5ef2aSThomas Huth ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); 7246fcf5ef2aSThomas Huth } else { 7247fcf5ef2aSThomas Huth ctx.opcode = cpu_ldl_code(env, ctx.nip); 7248fcf5ef2aSThomas Huth } 7249fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7250fcf5ef2aSThomas Huth ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), 7251fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7252fcf5ef2aSThomas Huth ctx.le_mode ? "little" : "big"); 7253fcf5ef2aSThomas Huth ctx.nip += 4; 7254fcf5ef2aSThomas Huth table = env->opcodes; 7255fcf5ef2aSThomas Huth handler = table[opc1(ctx.opcode)]; 7256fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7257fcf5ef2aSThomas Huth table = ind_table(handler); 7258fcf5ef2aSThomas Huth handler = table[opc2(ctx.opcode)]; 7259fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7260fcf5ef2aSThomas Huth table = ind_table(handler); 7261fcf5ef2aSThomas Huth handler = table[opc3(ctx.opcode)]; 7262fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7263fcf5ef2aSThomas Huth table = ind_table(handler); 7264fcf5ef2aSThomas Huth handler = table[opc4(ctx.opcode)]; 7265fcf5ef2aSThomas Huth } 7266fcf5ef2aSThomas Huth } 7267fcf5ef2aSThomas Huth } 7268fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7269fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7270fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7271fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7272fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7273fcf5ef2aSThomas Huth opc1(ctx.opcode), opc2(ctx.opcode), 7274fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7275fcf5ef2aSThomas Huth ctx.opcode, ctx.nip - 4, (int)msr_ir); 7276fcf5ef2aSThomas Huth } else { 7277fcf5ef2aSThomas Huth uint32_t inval; 7278fcf5ef2aSThomas Huth 7279fcf5ef2aSThomas Huth if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { 7280fcf5ef2aSThomas Huth inval = handler->inval2; 7281fcf5ef2aSThomas Huth } else { 7282fcf5ef2aSThomas Huth inval = handler->inval1; 7283fcf5ef2aSThomas Huth } 7284fcf5ef2aSThomas Huth 7285fcf5ef2aSThomas Huth if (unlikely((ctx.opcode & inval) != 0)) { 7286fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7287fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7288fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", ctx.opcode & inval, 7289fcf5ef2aSThomas Huth opc1(ctx.opcode), opc2(ctx.opcode), 7290fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7291fcf5ef2aSThomas Huth ctx.opcode, ctx.nip - 4); 7292fcf5ef2aSThomas Huth gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); 7293fcf5ef2aSThomas Huth break; 7294fcf5ef2aSThomas Huth } 7295fcf5ef2aSThomas Huth } 7296fcf5ef2aSThomas Huth (*(handler->handler))(&ctx); 7297fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7298fcf5ef2aSThomas Huth handler->count++; 7299fcf5ef2aSThomas Huth #endif 7300fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7301fcf5ef2aSThomas Huth if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && 7302fcf5ef2aSThomas Huth (ctx.nip <= 0x100 || ctx.nip > 0xF00) && 7303fcf5ef2aSThomas Huth ctx.exception != POWERPC_SYSCALL && 7304fcf5ef2aSThomas Huth ctx.exception != POWERPC_EXCP_TRAP && 7305fcf5ef2aSThomas Huth ctx.exception != POWERPC_EXCP_BRANCH)) { 7306fcf5ef2aSThomas Huth gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); 7307fcf5ef2aSThomas Huth } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || 7308fcf5ef2aSThomas Huth (cs->singlestep_enabled) || 7309fcf5ef2aSThomas Huth singlestep || 7310fcf5ef2aSThomas Huth num_insns >= max_insns)) { 7311fcf5ef2aSThomas Huth /* if we reach a page boundary or are single stepping, stop 7312fcf5ef2aSThomas Huth * generation 7313fcf5ef2aSThomas Huth */ 7314fcf5ef2aSThomas Huth break; 7315fcf5ef2aSThomas Huth } 7316fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7317fcf5ef2aSThomas Huth fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " 7318fcf5ef2aSThomas Huth "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), 7319fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); 7320fcf5ef2aSThomas Huth exit(1); 7321fcf5ef2aSThomas Huth } 7322fcf5ef2aSThomas Huth } 7323fcf5ef2aSThomas Huth if (tb->cflags & CF_LAST_IO) 7324fcf5ef2aSThomas Huth gen_io_end(); 7325fcf5ef2aSThomas Huth if (ctx.exception == POWERPC_EXCP_NONE) { 7326fcf5ef2aSThomas Huth gen_goto_tb(&ctx, 0, ctx.nip); 7327fcf5ef2aSThomas Huth } else if (ctx.exception != POWERPC_EXCP_BRANCH) { 7328fcf5ef2aSThomas Huth if (unlikely(cs->singlestep_enabled)) { 7329fcf5ef2aSThomas Huth gen_debug_exception(ctxp); 7330fcf5ef2aSThomas Huth } 7331fcf5ef2aSThomas Huth /* Generate the return instruction */ 7332fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 7333fcf5ef2aSThomas Huth } 7334fcf5ef2aSThomas Huth gen_tb_end(tb, num_insns); 7335fcf5ef2aSThomas Huth 7336fcf5ef2aSThomas Huth tb->size = ctx.nip - pc_start; 7337fcf5ef2aSThomas Huth tb->icount = num_insns; 7338fcf5ef2aSThomas Huth 7339fcf5ef2aSThomas Huth #if defined(DEBUG_DISAS) 7340fcf5ef2aSThomas Huth if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 7341fcf5ef2aSThomas Huth && qemu_log_in_addr_range(pc_start)) { 7342fcf5ef2aSThomas Huth int flags; 7343fcf5ef2aSThomas Huth flags = env->bfd_mach; 7344fcf5ef2aSThomas Huth flags |= ctx.le_mode << 16; 7345fcf5ef2aSThomas Huth qemu_log_lock(); 7346fcf5ef2aSThomas Huth qemu_log("IN: %s\n", lookup_symbol(pc_start)); 7347fcf5ef2aSThomas Huth log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); 7348fcf5ef2aSThomas Huth qemu_log("\n"); 7349fcf5ef2aSThomas Huth qemu_log_unlock(); 7350fcf5ef2aSThomas Huth } 7351fcf5ef2aSThomas Huth #endif 7352fcf5ef2aSThomas Huth } 7353fcf5ef2aSThomas Huth 7354fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7355fcf5ef2aSThomas Huth target_ulong *data) 7356fcf5ef2aSThomas Huth { 7357fcf5ef2aSThomas Huth env->nip = data[0]; 7358fcf5ef2aSThomas Huth } 7359