1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26fcf5ef2aSThomas Huth #include "tcg-op.h" 27fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #include "trace-tcg.h" 34b6bac4bcSEmilio G. Cota #include "exec/translator.h" 35fcf5ef2aSThomas Huth #include "exec/log.h" 36f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 37fcf5ef2aSThomas Huth 38fcf5ef2aSThomas Huth 39fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 40fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 41fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 44fcf5ef2aSThomas Huth //#define PPC_DEBUG_DISAS 45fcf5ef2aSThomas Huth //#define DO_PPC_STATISTICS 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 48fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 49fcf5ef2aSThomas Huth #else 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 51fcf5ef2aSThomas Huth #endif 52fcf5ef2aSThomas Huth /*****************************************************************************/ 53fcf5ef2aSThomas Huth /* Code translation helpers */ 54fcf5ef2aSThomas Huth 55fcf5ef2aSThomas Huth /* global register indexes */ 56fcf5ef2aSThomas Huth static char cpu_reg_names[10*3 + 22*4 /* GPR */ 57fcf5ef2aSThomas Huth + 10*4 + 22*5 /* SPE GPRh */ 58fcf5ef2aSThomas Huth + 10*4 + 22*5 /* FPR */ 59fcf5ef2aSThomas Huth + 2*(10*6 + 22*7) /* AVRh, AVRl */ 60fcf5ef2aSThomas Huth + 10*5 + 22*6 /* VSR */ 61fcf5ef2aSThomas Huth + 8*5 /* CRF */]; 62fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 63fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 64fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[32]; 65fcf5ef2aSThomas Huth static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 66fcf5ef2aSThomas Huth static TCGv_i64 cpu_vsr[32]; 67fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 68fcf5ef2aSThomas Huth static TCGv cpu_nip; 69fcf5ef2aSThomas Huth static TCGv cpu_msr; 70fcf5ef2aSThomas Huth static TCGv cpu_ctr; 71fcf5ef2aSThomas Huth static TCGv cpu_lr; 72fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 73fcf5ef2aSThomas Huth static TCGv cpu_cfar; 74fcf5ef2aSThomas Huth #endif 75dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 76fcf5ef2aSThomas Huth static TCGv cpu_reserve; 77253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 78fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 79fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 82fcf5ef2aSThomas Huth 83fcf5ef2aSThomas Huth void ppc_translate_init(void) 84fcf5ef2aSThomas Huth { 85fcf5ef2aSThomas Huth int i; 86fcf5ef2aSThomas Huth char* p; 87fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 88fcf5ef2aSThomas Huth 89fcf5ef2aSThomas Huth p = cpu_reg_names; 90fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 91fcf5ef2aSThomas Huth 92fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 93fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 94fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 95fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 96fcf5ef2aSThomas Huth p += 5; 97fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 98fcf5ef2aSThomas Huth } 99fcf5ef2aSThomas Huth 100fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 101fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 102fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 103fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 104fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 106fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 107fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 108fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 109fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "fp%d", i); 113fcf5ef2aSThomas Huth cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 114fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpr[i]), p); 115fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 116fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dH", i); 119fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 120fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 122fcf5ef2aSThomas Huth #else 123fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 124fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 125fcf5ef2aSThomas Huth #endif 126fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 127fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dL", i); 130fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 131fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 133fcf5ef2aSThomas Huth #else 134fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 135fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 136fcf5ef2aSThomas Huth #endif 137fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 138fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 139fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "vsr%d", i); 140fcf5ef2aSThomas Huth cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 141fcf5ef2aSThomas Huth offsetof(CPUPPCState, vsr[i]), p); 142fcf5ef2aSThomas Huth p += (i < 10) ? 5 : 6; 143fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 5 : 6; 144fcf5ef2aSThomas Huth } 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 150fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 153fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 154fcf5ef2aSThomas Huth 155fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 156fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 159fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 160fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 161fcf5ef2aSThomas Huth #endif 162fcf5ef2aSThomas Huth 163fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 164fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 165fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 166fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 167fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 168fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 169fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 170fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 171dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 172dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 173dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 174dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 175fcf5ef2aSThomas Huth 176fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 177fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 178fcf5ef2aSThomas Huth "reserve_addr"); 179253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 180253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 181253ce7b2SNikunj A Dadhania "reserve_val"); 182fcf5ef2aSThomas Huth 183fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 184fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 185fcf5ef2aSThomas Huth 186fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 187fcf5ef2aSThomas Huth offsetof(CPUPPCState, access_type), "access_type"); 188fcf5ef2aSThomas Huth } 189fcf5ef2aSThomas Huth 190fcf5ef2aSThomas Huth /* internal defines */ 191fcf5ef2aSThomas Huth struct DisasContext { 192b6bac4bcSEmilio G. Cota DisasContextBase base; 193fcf5ef2aSThomas Huth uint32_t opcode; 194fcf5ef2aSThomas Huth uint32_t exception; 195fcf5ef2aSThomas Huth /* Routine used to access memory */ 196fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 197fcf5ef2aSThomas Huth bool lazy_tlb_flush; 198fcf5ef2aSThomas Huth bool need_access_type; 199fcf5ef2aSThomas Huth int mem_idx; 200fcf5ef2aSThomas Huth int access_type; 201fcf5ef2aSThomas Huth /* Translation flags */ 202fcf5ef2aSThomas Huth TCGMemOp default_tcg_memop_mask; 203fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 204fcf5ef2aSThomas Huth bool sf_mode; 205fcf5ef2aSThomas Huth bool has_cfar; 206fcf5ef2aSThomas Huth #endif 207fcf5ef2aSThomas Huth bool fpu_enabled; 208fcf5ef2aSThomas Huth bool altivec_enabled; 209fcf5ef2aSThomas Huth bool vsx_enabled; 210fcf5ef2aSThomas Huth bool spe_enabled; 211fcf5ef2aSThomas Huth bool tm_enabled; 212c6fd28fdSSuraj Jitindar Singh bool gtse; 213fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 214fcf5ef2aSThomas Huth int singlestep_enabled; 2150e3bf489SRoman Kapl uint32_t flags; 216fcf5ef2aSThomas Huth uint64_t insns_flags; 217fcf5ef2aSThomas Huth uint64_t insns_flags2; 218fcf5ef2aSThomas Huth }; 219fcf5ef2aSThomas Huth 220fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 221fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 222fcf5ef2aSThomas Huth { 223fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 224fcf5ef2aSThomas Huth return ctx->le_mode; 225fcf5ef2aSThomas Huth #else 226fcf5ef2aSThomas Huth return !ctx->le_mode; 227fcf5ef2aSThomas Huth #endif 228fcf5ef2aSThomas Huth } 229fcf5ef2aSThomas Huth 230fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 231fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 232fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 233fcf5ef2aSThomas Huth #else 234fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 235fcf5ef2aSThomas Huth #endif 236fcf5ef2aSThomas Huth 237fcf5ef2aSThomas Huth struct opc_handler_t { 238fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 239fcf5ef2aSThomas Huth uint32_t inval1; 240fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 241fcf5ef2aSThomas Huth uint32_t inval2; 242fcf5ef2aSThomas Huth /* instruction type */ 243fcf5ef2aSThomas Huth uint64_t type; 244fcf5ef2aSThomas Huth /* extended instruction type */ 245fcf5ef2aSThomas Huth uint64_t type2; 246fcf5ef2aSThomas Huth /* handler */ 247fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 248fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 249fcf5ef2aSThomas Huth const char *oname; 250fcf5ef2aSThomas Huth #endif 251fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 252fcf5ef2aSThomas Huth uint64_t count; 253fcf5ef2aSThomas Huth #endif 254fcf5ef2aSThomas Huth }; 255fcf5ef2aSThomas Huth 2560e3bf489SRoman Kapl /* SPR load/store helpers */ 2570e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2580e3bf489SRoman Kapl { 2590e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2600e3bf489SRoman Kapl } 2610e3bf489SRoman Kapl 2620e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2630e3bf489SRoman Kapl { 2640e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2650e3bf489SRoman Kapl } 2660e3bf489SRoman Kapl 267fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 268fcf5ef2aSThomas Huth { 269fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 270fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 271fcf5ef2aSThomas Huth ctx->access_type = access_type; 272fcf5ef2aSThomas Huth } 273fcf5ef2aSThomas Huth } 274fcf5ef2aSThomas Huth 275fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 276fcf5ef2aSThomas Huth { 277fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 278fcf5ef2aSThomas Huth nip = (uint32_t)nip; 279fcf5ef2aSThomas Huth } 280fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 281fcf5ef2aSThomas Huth } 282fcf5ef2aSThomas Huth 283fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 284fcf5ef2aSThomas Huth { 285fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 288fcf5ef2aSThomas Huth * the faulting instruction 289fcf5ef2aSThomas Huth */ 290fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 291b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 292fcf5ef2aSThomas Huth } 293fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 294fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 295fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 296fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 297fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 298fcf5ef2aSThomas Huth ctx->exception = (excp); 299fcf5ef2aSThomas Huth } 300fcf5ef2aSThomas Huth 301fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 302fcf5ef2aSThomas Huth { 303fcf5ef2aSThomas Huth TCGv_i32 t0; 304fcf5ef2aSThomas Huth 305fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 306fcf5ef2aSThomas Huth * the faulting instruction 307fcf5ef2aSThomas Huth */ 308fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 309b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 310fcf5ef2aSThomas Huth } 311fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 312fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 313fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 314fcf5ef2aSThomas Huth ctx->exception = (excp); 315fcf5ef2aSThomas Huth } 316fcf5ef2aSThomas Huth 317fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 318fcf5ef2aSThomas Huth target_ulong nip) 319fcf5ef2aSThomas Huth { 320fcf5ef2aSThomas Huth TCGv_i32 t0; 321fcf5ef2aSThomas Huth 322fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 323fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 324fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 325fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 326fcf5ef2aSThomas Huth ctx->exception = (excp); 327fcf5ef2aSThomas Huth } 328fcf5ef2aSThomas Huth 3290e3bf489SRoman Kapl /* Translates the EXCP_TRACE/BRANCH exceptions used on most PowerPCs to 3300e3bf489SRoman Kapl * EXCP_DEBUG, if we are running on cores using the debug enable bit (e.g. 3310e3bf489SRoman Kapl * BookE). 3320e3bf489SRoman Kapl */ 3330e3bf489SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx, uint32_t excp) 3340e3bf489SRoman Kapl { 3350e3bf489SRoman Kapl if ((ctx->singlestep_enabled & CPU_SINGLE_STEP) 3360e3bf489SRoman Kapl && (excp == POWERPC_EXCP_BRANCH)) { 3370e3bf489SRoman Kapl /* Trace excpt. has priority */ 3380e3bf489SRoman Kapl excp = POWERPC_EXCP_TRACE; 3390e3bf489SRoman Kapl } 3400e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3410e3bf489SRoman Kapl target_ulong dbsr = 0; 3420e3bf489SRoman Kapl switch (excp) { 3430e3bf489SRoman Kapl case POWERPC_EXCP_TRACE: 3440e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 3450e3bf489SRoman Kapl break; 3460e3bf489SRoman Kapl case POWERPC_EXCP_BRANCH: 3470e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3480e3bf489SRoman Kapl break; 3490e3bf489SRoman Kapl } 3500e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3510e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3520e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3530e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3540e3bf489SRoman Kapl tcg_temp_free(t0); 3550e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3560e3bf489SRoman Kapl } else { 3570e3bf489SRoman Kapl return excp; 3580e3bf489SRoman Kapl } 3590e3bf489SRoman Kapl } 3600e3bf489SRoman Kapl 361fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 362fcf5ef2aSThomas Huth { 363fcf5ef2aSThomas Huth TCGv_i32 t0; 364fcf5ef2aSThomas Huth 365fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 366fcf5ef2aSThomas Huth * the faulting instruction 367fcf5ef2aSThomas Huth */ 368fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 369fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 370b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 371fcf5ef2aSThomas Huth } 372fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 373fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 374fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 375fcf5ef2aSThomas Huth } 376fcf5ef2aSThomas Huth 377fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 378fcf5ef2aSThomas Huth { 379fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 380fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 381fcf5ef2aSThomas Huth } 382fcf5ef2aSThomas Huth 383fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 384fcf5ef2aSThomas Huth { 385fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 386fcf5ef2aSThomas Huth } 387fcf5ef2aSThomas Huth 388fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 389fcf5ef2aSThomas Huth { 390fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 391fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 392fcf5ef2aSThomas Huth } 393fcf5ef2aSThomas Huth 394fcf5ef2aSThomas Huth /* Stop translation */ 395fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 396fcf5ef2aSThomas Huth { 397b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 398fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 399fcf5ef2aSThomas Huth } 400fcf5ef2aSThomas Huth 401fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 402fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 403fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 404fcf5ef2aSThomas Huth { 405fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 406fcf5ef2aSThomas Huth } 407fcf5ef2aSThomas Huth #endif 408fcf5ef2aSThomas Huth 409fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 410fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 411fcf5ef2aSThomas Huth 412fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 413fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 414fcf5ef2aSThomas Huth 415fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 416fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 417fcf5ef2aSThomas Huth 418fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 419fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 420fcf5ef2aSThomas Huth 421fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 422fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 423fcf5ef2aSThomas Huth 424fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 425fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 426fcf5ef2aSThomas Huth 427fcf5ef2aSThomas Huth typedef struct opcode_t { 428fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 429fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 430fcf5ef2aSThomas Huth unsigned char pad[4]; 431fcf5ef2aSThomas Huth #endif 432fcf5ef2aSThomas Huth opc_handler_t handler; 433fcf5ef2aSThomas Huth const char *oname; 434fcf5ef2aSThomas Huth } opcode_t; 435fcf5ef2aSThomas Huth 436fcf5ef2aSThomas Huth /* Helpers for priv. check */ 437fcf5ef2aSThomas Huth #define GEN_PRIV \ 438fcf5ef2aSThomas Huth do { \ 439fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 440fcf5ef2aSThomas Huth } while (0) 441fcf5ef2aSThomas Huth 442fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 443fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 444fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 445fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 446fcf5ef2aSThomas Huth #else 447fcf5ef2aSThomas Huth #define CHK_HV \ 448fcf5ef2aSThomas Huth do { \ 449fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 450fcf5ef2aSThomas Huth GEN_PRIV; \ 451fcf5ef2aSThomas Huth } \ 452fcf5ef2aSThomas Huth } while (0) 453fcf5ef2aSThomas Huth #define CHK_SV \ 454fcf5ef2aSThomas Huth do { \ 455fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 456fcf5ef2aSThomas Huth GEN_PRIV; \ 457fcf5ef2aSThomas Huth } \ 458fcf5ef2aSThomas Huth } while (0) 459fcf5ef2aSThomas Huth #define CHK_HVRM \ 460fcf5ef2aSThomas Huth do { \ 461fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 462fcf5ef2aSThomas Huth GEN_PRIV; \ 463fcf5ef2aSThomas Huth } \ 464fcf5ef2aSThomas Huth } while (0) 465fcf5ef2aSThomas Huth #endif 466fcf5ef2aSThomas Huth 467fcf5ef2aSThomas Huth #define CHK_NONE 468fcf5ef2aSThomas Huth 469fcf5ef2aSThomas Huth /*****************************************************************************/ 470fcf5ef2aSThomas Huth /* PowerPC instructions table */ 471fcf5ef2aSThomas Huth 472fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 473fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 474fcf5ef2aSThomas Huth { \ 475fcf5ef2aSThomas Huth .opc1 = op1, \ 476fcf5ef2aSThomas Huth .opc2 = op2, \ 477fcf5ef2aSThomas Huth .opc3 = op3, \ 478fcf5ef2aSThomas Huth .opc4 = 0xff, \ 479fcf5ef2aSThomas Huth .handler = { \ 480fcf5ef2aSThomas Huth .inval1 = invl, \ 481fcf5ef2aSThomas Huth .type = _typ, \ 482fcf5ef2aSThomas Huth .type2 = _typ2, \ 483fcf5ef2aSThomas Huth .handler = &gen_##name, \ 484fcf5ef2aSThomas Huth .oname = stringify(name), \ 485fcf5ef2aSThomas Huth }, \ 486fcf5ef2aSThomas Huth .oname = stringify(name), \ 487fcf5ef2aSThomas Huth } 488fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 489fcf5ef2aSThomas Huth { \ 490fcf5ef2aSThomas Huth .opc1 = op1, \ 491fcf5ef2aSThomas Huth .opc2 = op2, \ 492fcf5ef2aSThomas Huth .opc3 = op3, \ 493fcf5ef2aSThomas Huth .opc4 = 0xff, \ 494fcf5ef2aSThomas Huth .handler = { \ 495fcf5ef2aSThomas Huth .inval1 = invl1, \ 496fcf5ef2aSThomas Huth .inval2 = invl2, \ 497fcf5ef2aSThomas Huth .type = _typ, \ 498fcf5ef2aSThomas Huth .type2 = _typ2, \ 499fcf5ef2aSThomas Huth .handler = &gen_##name, \ 500fcf5ef2aSThomas Huth .oname = stringify(name), \ 501fcf5ef2aSThomas Huth }, \ 502fcf5ef2aSThomas Huth .oname = stringify(name), \ 503fcf5ef2aSThomas Huth } 504fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 505fcf5ef2aSThomas Huth { \ 506fcf5ef2aSThomas Huth .opc1 = op1, \ 507fcf5ef2aSThomas Huth .opc2 = op2, \ 508fcf5ef2aSThomas Huth .opc3 = op3, \ 509fcf5ef2aSThomas Huth .opc4 = 0xff, \ 510fcf5ef2aSThomas Huth .handler = { \ 511fcf5ef2aSThomas Huth .inval1 = invl, \ 512fcf5ef2aSThomas Huth .type = _typ, \ 513fcf5ef2aSThomas Huth .type2 = _typ2, \ 514fcf5ef2aSThomas Huth .handler = &gen_##name, \ 515fcf5ef2aSThomas Huth .oname = onam, \ 516fcf5ef2aSThomas Huth }, \ 517fcf5ef2aSThomas Huth .oname = onam, \ 518fcf5ef2aSThomas Huth } 519fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 520fcf5ef2aSThomas Huth { \ 521fcf5ef2aSThomas Huth .opc1 = op1, \ 522fcf5ef2aSThomas Huth .opc2 = op2, \ 523fcf5ef2aSThomas Huth .opc3 = op3, \ 524fcf5ef2aSThomas Huth .opc4 = op4, \ 525fcf5ef2aSThomas Huth .handler = { \ 526fcf5ef2aSThomas Huth .inval1 = invl, \ 527fcf5ef2aSThomas Huth .type = _typ, \ 528fcf5ef2aSThomas Huth .type2 = _typ2, \ 529fcf5ef2aSThomas Huth .handler = &gen_##name, \ 530fcf5ef2aSThomas Huth .oname = stringify(name), \ 531fcf5ef2aSThomas Huth }, \ 532fcf5ef2aSThomas Huth .oname = stringify(name), \ 533fcf5ef2aSThomas Huth } 534fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 535fcf5ef2aSThomas Huth { \ 536fcf5ef2aSThomas Huth .opc1 = op1, \ 537fcf5ef2aSThomas Huth .opc2 = op2, \ 538fcf5ef2aSThomas Huth .opc3 = op3, \ 539fcf5ef2aSThomas Huth .opc4 = op4, \ 540fcf5ef2aSThomas Huth .handler = { \ 541fcf5ef2aSThomas Huth .inval1 = invl, \ 542fcf5ef2aSThomas Huth .type = _typ, \ 543fcf5ef2aSThomas Huth .type2 = _typ2, \ 544fcf5ef2aSThomas Huth .handler = &gen_##name, \ 545fcf5ef2aSThomas Huth .oname = onam, \ 546fcf5ef2aSThomas Huth }, \ 547fcf5ef2aSThomas Huth .oname = onam, \ 548fcf5ef2aSThomas Huth } 549fcf5ef2aSThomas Huth #else 550fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 551fcf5ef2aSThomas Huth { \ 552fcf5ef2aSThomas Huth .opc1 = op1, \ 553fcf5ef2aSThomas Huth .opc2 = op2, \ 554fcf5ef2aSThomas Huth .opc3 = op3, \ 555fcf5ef2aSThomas Huth .opc4 = 0xff, \ 556fcf5ef2aSThomas Huth .handler = { \ 557fcf5ef2aSThomas Huth .inval1 = invl, \ 558fcf5ef2aSThomas Huth .type = _typ, \ 559fcf5ef2aSThomas Huth .type2 = _typ2, \ 560fcf5ef2aSThomas Huth .handler = &gen_##name, \ 561fcf5ef2aSThomas Huth }, \ 562fcf5ef2aSThomas Huth .oname = stringify(name), \ 563fcf5ef2aSThomas Huth } 564fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 565fcf5ef2aSThomas Huth { \ 566fcf5ef2aSThomas Huth .opc1 = op1, \ 567fcf5ef2aSThomas Huth .opc2 = op2, \ 568fcf5ef2aSThomas Huth .opc3 = op3, \ 569fcf5ef2aSThomas Huth .opc4 = 0xff, \ 570fcf5ef2aSThomas Huth .handler = { \ 571fcf5ef2aSThomas Huth .inval1 = invl1, \ 572fcf5ef2aSThomas Huth .inval2 = invl2, \ 573fcf5ef2aSThomas Huth .type = _typ, \ 574fcf5ef2aSThomas Huth .type2 = _typ2, \ 575fcf5ef2aSThomas Huth .handler = &gen_##name, \ 576fcf5ef2aSThomas Huth }, \ 577fcf5ef2aSThomas Huth .oname = stringify(name), \ 578fcf5ef2aSThomas Huth } 579fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 580fcf5ef2aSThomas Huth { \ 581fcf5ef2aSThomas Huth .opc1 = op1, \ 582fcf5ef2aSThomas Huth .opc2 = op2, \ 583fcf5ef2aSThomas Huth .opc3 = op3, \ 584fcf5ef2aSThomas Huth .opc4 = 0xff, \ 585fcf5ef2aSThomas Huth .handler = { \ 586fcf5ef2aSThomas Huth .inval1 = invl, \ 587fcf5ef2aSThomas Huth .type = _typ, \ 588fcf5ef2aSThomas Huth .type2 = _typ2, \ 589fcf5ef2aSThomas Huth .handler = &gen_##name, \ 590fcf5ef2aSThomas Huth }, \ 591fcf5ef2aSThomas Huth .oname = onam, \ 592fcf5ef2aSThomas Huth } 593fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 594fcf5ef2aSThomas Huth { \ 595fcf5ef2aSThomas Huth .opc1 = op1, \ 596fcf5ef2aSThomas Huth .opc2 = op2, \ 597fcf5ef2aSThomas Huth .opc3 = op3, \ 598fcf5ef2aSThomas Huth .opc4 = op4, \ 599fcf5ef2aSThomas Huth .handler = { \ 600fcf5ef2aSThomas Huth .inval1 = invl, \ 601fcf5ef2aSThomas Huth .type = _typ, \ 602fcf5ef2aSThomas Huth .type2 = _typ2, \ 603fcf5ef2aSThomas Huth .handler = &gen_##name, \ 604fcf5ef2aSThomas Huth }, \ 605fcf5ef2aSThomas Huth .oname = stringify(name), \ 606fcf5ef2aSThomas Huth } 607fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 608fcf5ef2aSThomas Huth { \ 609fcf5ef2aSThomas Huth .opc1 = op1, \ 610fcf5ef2aSThomas Huth .opc2 = op2, \ 611fcf5ef2aSThomas Huth .opc3 = op3, \ 612fcf5ef2aSThomas Huth .opc4 = op4, \ 613fcf5ef2aSThomas Huth .handler = { \ 614fcf5ef2aSThomas Huth .inval1 = invl, \ 615fcf5ef2aSThomas Huth .type = _typ, \ 616fcf5ef2aSThomas Huth .type2 = _typ2, \ 617fcf5ef2aSThomas Huth .handler = &gen_##name, \ 618fcf5ef2aSThomas Huth }, \ 619fcf5ef2aSThomas Huth .oname = onam, \ 620fcf5ef2aSThomas Huth } 621fcf5ef2aSThomas Huth #endif 622fcf5ef2aSThomas Huth 623fcf5ef2aSThomas Huth /* Invalid instruction */ 624fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 625fcf5ef2aSThomas Huth { 626fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 627fcf5ef2aSThomas Huth } 628fcf5ef2aSThomas Huth 629fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 630fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 631fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 632fcf5ef2aSThomas Huth .type = PPC_NONE, 633fcf5ef2aSThomas Huth .type2 = PPC_NONE, 634fcf5ef2aSThomas Huth .handler = gen_invalid, 635fcf5ef2aSThomas Huth }; 636fcf5ef2aSThomas Huth 637fcf5ef2aSThomas Huth /*** Integer comparison ***/ 638fcf5ef2aSThomas Huth 639fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 640fcf5ef2aSThomas Huth { 641fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 642b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 643b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 644fcf5ef2aSThomas Huth 645b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 646b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 647b62b3686Spbonzini@redhat.com tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0); 648b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 649b62b3686Spbonzini@redhat.com tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0); 650b62b3686Spbonzini@redhat.com 651b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 652fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 653b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 654fcf5ef2aSThomas Huth 655fcf5ef2aSThomas Huth tcg_temp_free(t0); 656b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 657b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 658fcf5ef2aSThomas Huth } 659fcf5ef2aSThomas Huth 660fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 661fcf5ef2aSThomas Huth { 662fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 663fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 664fcf5ef2aSThomas Huth tcg_temp_free(t0); 665fcf5ef2aSThomas Huth } 666fcf5ef2aSThomas Huth 667fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 668fcf5ef2aSThomas Huth { 669fcf5ef2aSThomas Huth TCGv t0, t1; 670fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 671fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 672fcf5ef2aSThomas Huth if (s) { 673fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 674fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 675fcf5ef2aSThomas Huth } else { 676fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 677fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 678fcf5ef2aSThomas Huth } 679fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 680fcf5ef2aSThomas Huth tcg_temp_free(t1); 681fcf5ef2aSThomas Huth tcg_temp_free(t0); 682fcf5ef2aSThomas Huth } 683fcf5ef2aSThomas Huth 684fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 685fcf5ef2aSThomas Huth { 686fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 687fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 688fcf5ef2aSThomas Huth tcg_temp_free(t0); 689fcf5ef2aSThomas Huth } 690fcf5ef2aSThomas Huth 691fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 692fcf5ef2aSThomas Huth { 693fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 694fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 695fcf5ef2aSThomas Huth } else { 696fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 697fcf5ef2aSThomas Huth } 698fcf5ef2aSThomas Huth } 699fcf5ef2aSThomas Huth 700fcf5ef2aSThomas Huth /* cmp */ 701fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 702fcf5ef2aSThomas Huth { 703fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 704fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 705fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 706fcf5ef2aSThomas Huth } else { 707fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 708fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 709fcf5ef2aSThomas Huth } 710fcf5ef2aSThomas Huth } 711fcf5ef2aSThomas Huth 712fcf5ef2aSThomas Huth /* cmpi */ 713fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 714fcf5ef2aSThomas Huth { 715fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 716fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 717fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 718fcf5ef2aSThomas Huth } else { 719fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 720fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 721fcf5ef2aSThomas Huth } 722fcf5ef2aSThomas Huth } 723fcf5ef2aSThomas Huth 724fcf5ef2aSThomas Huth /* cmpl */ 725fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 726fcf5ef2aSThomas Huth { 727fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 728fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 729fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 730fcf5ef2aSThomas Huth } else { 731fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 732fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 733fcf5ef2aSThomas Huth } 734fcf5ef2aSThomas Huth } 735fcf5ef2aSThomas Huth 736fcf5ef2aSThomas Huth /* cmpli */ 737fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 738fcf5ef2aSThomas Huth { 739fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 740fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 741fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 742fcf5ef2aSThomas Huth } else { 743fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 744fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 745fcf5ef2aSThomas Huth } 746fcf5ef2aSThomas Huth } 747fcf5ef2aSThomas Huth 748fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 749fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 750fcf5ef2aSThomas Huth { 751fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 752fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 753fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 754fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 755fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 756fcf5ef2aSThomas Huth 757fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 758fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 759fcf5ef2aSThomas Huth 760fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 761fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 762fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 763fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 764fcf5ef2aSThomas Huth 765fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 766fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 767fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 768fcf5ef2aSThomas Huth 769fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 770fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 771fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 772fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 773fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 774fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 775fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 776fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 777fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 778fcf5ef2aSThomas Huth } 779efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 780fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 781fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 782fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 783fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 784fcf5ef2aSThomas Huth } 785fcf5ef2aSThomas Huth 786fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 787fcf5ef2aSThomas Huth /* cmpeqb */ 788fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 789fcf5ef2aSThomas Huth { 790fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 791fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 792fcf5ef2aSThomas Huth } 793fcf5ef2aSThomas Huth #endif 794fcf5ef2aSThomas Huth 795fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 796fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 797fcf5ef2aSThomas Huth { 798fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 799fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 800fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 801fcf5ef2aSThomas Huth TCGv zr; 802fcf5ef2aSThomas Huth 803fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 804fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 805fcf5ef2aSThomas Huth 806fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 807fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 808fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 809fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 810fcf5ef2aSThomas Huth tcg_temp_free(zr); 811fcf5ef2aSThomas Huth tcg_temp_free(t0); 812fcf5ef2aSThomas Huth } 813fcf5ef2aSThomas Huth 814fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 815fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 816fcf5ef2aSThomas Huth { 817fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 818fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 819fcf5ef2aSThomas Huth } 820fcf5ef2aSThomas Huth 821fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 822fcf5ef2aSThomas Huth 823fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 824fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 825fcf5ef2aSThomas Huth { 826fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 827fcf5ef2aSThomas Huth 828fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 829fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 830fcf5ef2aSThomas Huth if (sub) { 831fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 832fcf5ef2aSThomas Huth } else { 833fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 834fcf5ef2aSThomas Huth } 835fcf5ef2aSThomas Huth tcg_temp_free(t0); 836fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 837dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 838dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 839dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 840fcf5ef2aSThomas Huth } 841dc0ad844SNikunj A Dadhania } else { 842dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 843dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 844dc0ad844SNikunj A Dadhania } 84538a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 846dc0ad844SNikunj A Dadhania } 847fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 848fcf5ef2aSThomas Huth } 849fcf5ef2aSThomas Huth 8506b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8516b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 852*4c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 8536b10d008SNikunj A Dadhania { 8546b10d008SNikunj A Dadhania TCGv t0; 8556b10d008SNikunj A Dadhania 8566b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8576b10d008SNikunj A Dadhania return; 8586b10d008SNikunj A Dadhania } 8596b10d008SNikunj A Dadhania 8606b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 86133903d0aSNikunj A Dadhania if (sub) { 86233903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 86333903d0aSNikunj A Dadhania } else { 8646b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 86533903d0aSNikunj A Dadhania } 8666b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 867*4c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 8686b10d008SNikunj A Dadhania tcg_temp_free(t0); 8696b10d008SNikunj A Dadhania } 8706b10d008SNikunj A Dadhania 871fcf5ef2aSThomas Huth /* Common add function */ 872fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 873*4c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 874*4c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 875fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 876fcf5ef2aSThomas Huth { 877fcf5ef2aSThomas Huth TCGv t0 = ret; 878fcf5ef2aSThomas Huth 879fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 880fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 881fcf5ef2aSThomas Huth } 882fcf5ef2aSThomas Huth 883fcf5ef2aSThomas Huth if (compute_ca) { 884fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 885fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 886fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 887fcf5ef2aSThomas Huth carry into bit 32. */ 888fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 889fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 890fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 891fcf5ef2aSThomas Huth if (add_ca) { 892*4c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 893fcf5ef2aSThomas Huth } 894*4c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 895fcf5ef2aSThomas Huth tcg_temp_free(t1); 896*4c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 8976b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 898*4c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 8996b10d008SNikunj A Dadhania } 900fcf5ef2aSThomas Huth } else { 901fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 902fcf5ef2aSThomas Huth if (add_ca) { 903*4c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 904*4c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 905fcf5ef2aSThomas Huth } else { 906*4c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 907fcf5ef2aSThomas Huth } 908*4c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 909fcf5ef2aSThomas Huth tcg_temp_free(zero); 910fcf5ef2aSThomas Huth } 911fcf5ef2aSThomas Huth } else { 912fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 913fcf5ef2aSThomas Huth if (add_ca) { 914*4c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 915fcf5ef2aSThomas Huth } 916fcf5ef2aSThomas Huth } 917fcf5ef2aSThomas Huth 918fcf5ef2aSThomas Huth if (compute_ov) { 919fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 920fcf5ef2aSThomas Huth } 921fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 922fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 923fcf5ef2aSThomas Huth } 924fcf5ef2aSThomas Huth 92511f4e8f8SRichard Henderson if (t0 != ret) { 926fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 927fcf5ef2aSThomas Huth tcg_temp_free(t0); 928fcf5ef2aSThomas Huth } 929fcf5ef2aSThomas Huth } 930fcf5ef2aSThomas Huth /* Add functions with two operands */ 931*4c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 932fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 933fcf5ef2aSThomas Huth { \ 934fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 935fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 936*4c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 937fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 938fcf5ef2aSThomas Huth } 939fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 940*4c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 941fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 942fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 943fcf5ef2aSThomas Huth { \ 944fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 945fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 946fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 947*4c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 948fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 949fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 950fcf5ef2aSThomas Huth } 951fcf5ef2aSThomas Huth 952fcf5ef2aSThomas Huth /* add add. addo addo. */ 953*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 954*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 955fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 956*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 957*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 958fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 959*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 960*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 961fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 962*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 963*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 964*4c5920afSSuraj Jitindar Singh /* addex */ 965*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 966fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 967*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 968*4c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 969fcf5ef2aSThomas Huth /* addi */ 970fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 971fcf5ef2aSThomas Huth { 972fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 973fcf5ef2aSThomas Huth 974fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 975fcf5ef2aSThomas Huth /* li case */ 976fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 977fcf5ef2aSThomas Huth } else { 978fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 979fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 980fcf5ef2aSThomas Huth } 981fcf5ef2aSThomas Huth } 982fcf5ef2aSThomas Huth /* addic addic.*/ 983fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 984fcf5ef2aSThomas Huth { 985fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 986fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 987*4c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 988fcf5ef2aSThomas Huth tcg_temp_free(c); 989fcf5ef2aSThomas Huth } 990fcf5ef2aSThomas Huth 991fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 992fcf5ef2aSThomas Huth { 993fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 994fcf5ef2aSThomas Huth } 995fcf5ef2aSThomas Huth 996fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 997fcf5ef2aSThomas Huth { 998fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 999fcf5ef2aSThomas Huth } 1000fcf5ef2aSThomas Huth 1001fcf5ef2aSThomas Huth /* addis */ 1002fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 1003fcf5ef2aSThomas Huth { 1004fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1005fcf5ef2aSThomas Huth 1006fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1007fcf5ef2aSThomas Huth /* lis case */ 1008fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 1009fcf5ef2aSThomas Huth } else { 1010fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1011fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 1012fcf5ef2aSThomas Huth } 1013fcf5ef2aSThomas Huth } 1014fcf5ef2aSThomas Huth 1015fcf5ef2aSThomas Huth /* addpcis */ 1016fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 1017fcf5ef2aSThomas Huth { 1018fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 1019fcf5ef2aSThomas Huth 1020b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 1021fcf5ef2aSThomas Huth } 1022fcf5ef2aSThomas Huth 1023fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1024fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1025fcf5ef2aSThomas Huth { 1026fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1027fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1028fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1029fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1030fcf5ef2aSThomas Huth 1031fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1032fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1033fcf5ef2aSThomas Huth if (sign) { 1034fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1035fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1036fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1037fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1038fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1039fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1040fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1041fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1042fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1043fcf5ef2aSThomas Huth } else { 1044fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1045fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1046fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1047fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1048fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1049fcf5ef2aSThomas Huth } 1050fcf5ef2aSThomas Huth if (compute_ov) { 1051fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1052c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1053c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1054c44027ffSNikunj A Dadhania } 1055fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1056fcf5ef2aSThomas Huth } 1057fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1058fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1059fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1060fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1061fcf5ef2aSThomas Huth 1062fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1063fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1064fcf5ef2aSThomas Huth } 1065fcf5ef2aSThomas Huth /* Div functions */ 1066fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1067fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1068fcf5ef2aSThomas Huth { \ 1069fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1070fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1071fcf5ef2aSThomas Huth sign, compute_ov); \ 1072fcf5ef2aSThomas Huth } 1073fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1074fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1075fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1076fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1077fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1078fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1079fcf5ef2aSThomas Huth 1080fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1081fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1082fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1083fcf5ef2aSThomas Huth { \ 1084fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1085fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1086fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1087fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1088fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1089fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1090fcf5ef2aSThomas Huth } \ 1091fcf5ef2aSThomas Huth } 1092fcf5ef2aSThomas Huth 1093fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1094fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1095fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1096fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1097fcf5ef2aSThomas Huth 1098fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1099fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1100fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1101fcf5ef2aSThomas Huth { 1102fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1103fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1104fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1105fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1106fcf5ef2aSThomas Huth 1107fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1108fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1109fcf5ef2aSThomas Huth if (sign) { 1110fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1111fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1112fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1113fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1114fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1115fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1116fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1117fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1118fcf5ef2aSThomas Huth } else { 1119fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1120fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1121fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1122fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1123fcf5ef2aSThomas Huth } 1124fcf5ef2aSThomas Huth if (compute_ov) { 1125fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1126c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1127c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1128c44027ffSNikunj A Dadhania } 1129fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1130fcf5ef2aSThomas Huth } 1131fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1132fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1133fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1134fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1135fcf5ef2aSThomas Huth 1136fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1137fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1138fcf5ef2aSThomas Huth } 1139fcf5ef2aSThomas Huth 1140fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1141fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1142fcf5ef2aSThomas Huth { \ 1143fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1144fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1145fcf5ef2aSThomas Huth sign, compute_ov); \ 1146fcf5ef2aSThomas Huth } 1147c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1148fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1149fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1150c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1151fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1152fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1153fcf5ef2aSThomas Huth 1154fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1155fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1156fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1157fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1158fcf5ef2aSThomas Huth #endif 1159fcf5ef2aSThomas Huth 1160fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1161fcf5ef2aSThomas Huth TCGv arg2, int sign) 1162fcf5ef2aSThomas Huth { 1163fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1164fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1165fcf5ef2aSThomas Huth 1166fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1167fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1168fcf5ef2aSThomas Huth if (sign) { 1169fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1170fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1171fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1172fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1173fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1174fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1175fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1176fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1177fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1178fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1179fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1180fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1181fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1182fcf5ef2aSThomas Huth } else { 1183fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1184fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1185fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1186fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1187fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1188fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1189fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1190fcf5ef2aSThomas Huth } 1191fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1192fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1193fcf5ef2aSThomas Huth } 1194fcf5ef2aSThomas Huth 1195fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1196fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1197fcf5ef2aSThomas Huth { \ 1198fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1199fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1200fcf5ef2aSThomas Huth sign); \ 1201fcf5ef2aSThomas Huth } 1202fcf5ef2aSThomas Huth 1203fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1204fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1205fcf5ef2aSThomas Huth 1206fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1207fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1208fcf5ef2aSThomas Huth TCGv arg2, int sign) 1209fcf5ef2aSThomas Huth { 1210fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1211fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1212fcf5ef2aSThomas Huth 1213fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1214fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1215fcf5ef2aSThomas Huth if (sign) { 1216fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1217fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1218fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1219fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1220fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1221fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1222fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1223fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1224fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1225fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1226fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1227fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1228fcf5ef2aSThomas Huth } else { 1229fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1230fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1231fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1232fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1233fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1234fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1235fcf5ef2aSThomas Huth } 1236fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1237fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1238fcf5ef2aSThomas Huth } 1239fcf5ef2aSThomas Huth 1240fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1241fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1242fcf5ef2aSThomas Huth { \ 1243fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1244fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1245fcf5ef2aSThomas Huth sign); \ 1246fcf5ef2aSThomas Huth } 1247fcf5ef2aSThomas Huth 1248fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1249fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1250fcf5ef2aSThomas Huth #endif 1251fcf5ef2aSThomas Huth 1252fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1253fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1254fcf5ef2aSThomas Huth { 1255fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1256fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1257fcf5ef2aSThomas Huth 1258fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1259fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1260fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1261fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1262fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1263fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1264fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1265fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1266fcf5ef2aSThomas Huth } 1267fcf5ef2aSThomas Huth 1268fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1269fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1270fcf5ef2aSThomas Huth { 1271fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1272fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1273fcf5ef2aSThomas Huth 1274fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1275fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1276fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1277fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1278fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1279fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1280fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1281fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1282fcf5ef2aSThomas Huth } 1283fcf5ef2aSThomas Huth 1284fcf5ef2aSThomas Huth /* mullw mullw. */ 1285fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1286fcf5ef2aSThomas Huth { 1287fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1288fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1289fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1290fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1291fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1292fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1293fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1294fcf5ef2aSThomas Huth tcg_temp_free(t0); 1295fcf5ef2aSThomas Huth tcg_temp_free(t1); 1296fcf5ef2aSThomas Huth #else 1297fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1298fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1299fcf5ef2aSThomas Huth #endif 1300fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1301fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1302fcf5ef2aSThomas Huth } 1303fcf5ef2aSThomas Huth 1304fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1305fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1306fcf5ef2aSThomas Huth { 1307fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1308fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1309fcf5ef2aSThomas Huth 1310fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1311fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1312fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1313fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1314fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1315fcf5ef2aSThomas Huth #else 1316fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1317fcf5ef2aSThomas Huth #endif 1318fcf5ef2aSThomas Huth 1319fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1320fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1321fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 132261aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 132361aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 132461aa9a69SNikunj A Dadhania } 1325fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1326fcf5ef2aSThomas Huth 1327fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1328fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1329fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1330fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1331fcf5ef2aSThomas Huth } 1332fcf5ef2aSThomas Huth 1333fcf5ef2aSThomas Huth /* mulli */ 1334fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1335fcf5ef2aSThomas Huth { 1336fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1337fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1338fcf5ef2aSThomas Huth } 1339fcf5ef2aSThomas Huth 1340fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1341fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1342fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1343fcf5ef2aSThomas Huth { 1344fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1345fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1346fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1347fcf5ef2aSThomas Huth tcg_temp_free(lo); 1348fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1349fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1350fcf5ef2aSThomas Huth } 1351fcf5ef2aSThomas Huth } 1352fcf5ef2aSThomas Huth 1353fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1354fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1355fcf5ef2aSThomas Huth { 1356fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1357fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1358fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1359fcf5ef2aSThomas Huth tcg_temp_free(lo); 1360fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1361fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1362fcf5ef2aSThomas Huth } 1363fcf5ef2aSThomas Huth } 1364fcf5ef2aSThomas Huth 1365fcf5ef2aSThomas Huth /* mulld mulld. */ 1366fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1367fcf5ef2aSThomas Huth { 1368fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1369fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1370fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1371fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1372fcf5ef2aSThomas Huth } 1373fcf5ef2aSThomas Huth 1374fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1375fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1376fcf5ef2aSThomas Huth { 1377fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1378fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1379fcf5ef2aSThomas Huth 1380fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1381fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1382fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1383fcf5ef2aSThomas Huth 1384fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1385fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 138661aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 138761aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 138861aa9a69SNikunj A Dadhania } 1389fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1390fcf5ef2aSThomas Huth 1391fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1392fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1393fcf5ef2aSThomas Huth 1394fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1395fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1396fcf5ef2aSThomas Huth } 1397fcf5ef2aSThomas Huth } 1398fcf5ef2aSThomas Huth #endif 1399fcf5ef2aSThomas Huth 1400fcf5ef2aSThomas Huth /* Common subf function */ 1401fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1402fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1403fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1404fcf5ef2aSThomas Huth { 1405fcf5ef2aSThomas Huth TCGv t0 = ret; 1406fcf5ef2aSThomas Huth 1407fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1408fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1409fcf5ef2aSThomas Huth } 1410fcf5ef2aSThomas Huth 1411fcf5ef2aSThomas Huth if (compute_ca) { 1412fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1413fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1414fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 1415fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 1416fcf5ef2aSThomas Huth carry into bit 32. */ 1417fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1418fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1419fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1420fcf5ef2aSThomas Huth if (add_ca) { 1421fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1422fcf5ef2aSThomas Huth } else { 1423fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1424fcf5ef2aSThomas Huth } 1425fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1426fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1427fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1428fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1429fcf5ef2aSThomas Huth tcg_temp_free(t1); 1430e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 143133903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 143233903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 143333903d0aSNikunj A Dadhania } 1434fcf5ef2aSThomas Huth } else if (add_ca) { 1435fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1436fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1437fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1438fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1439fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1440*4c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1441fcf5ef2aSThomas Huth tcg_temp_free(zero); 1442fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1443fcf5ef2aSThomas Huth } else { 1444fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1445fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1446*4c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1447fcf5ef2aSThomas Huth } 1448fcf5ef2aSThomas Huth } else if (add_ca) { 1449fcf5ef2aSThomas Huth /* Since we're ignoring carry-out, we can simplify the 1450fcf5ef2aSThomas Huth standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1451fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1452fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1453fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1454fcf5ef2aSThomas Huth } else { 1455fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1456fcf5ef2aSThomas Huth } 1457fcf5ef2aSThomas Huth 1458fcf5ef2aSThomas Huth if (compute_ov) { 1459fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1460fcf5ef2aSThomas Huth } 1461fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1462fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1463fcf5ef2aSThomas Huth } 1464fcf5ef2aSThomas Huth 146511f4e8f8SRichard Henderson if (t0 != ret) { 1466fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1467fcf5ef2aSThomas Huth tcg_temp_free(t0); 1468fcf5ef2aSThomas Huth } 1469fcf5ef2aSThomas Huth } 1470fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1471fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1472fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1473fcf5ef2aSThomas Huth { \ 1474fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1475fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1476fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1477fcf5ef2aSThomas Huth } 1478fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1479fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1480fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1481fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1482fcf5ef2aSThomas Huth { \ 1483fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1484fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1485fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1486fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1487fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1488fcf5ef2aSThomas Huth } 1489fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1490fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1491fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1492fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1493fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1494fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1495fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1496fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1497fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1498fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1499fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1500fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1501fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1502fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1503fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1504fcf5ef2aSThomas Huth 1505fcf5ef2aSThomas Huth /* subfic */ 1506fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1507fcf5ef2aSThomas Huth { 1508fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1509fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1510fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1511fcf5ef2aSThomas Huth tcg_temp_free(c); 1512fcf5ef2aSThomas Huth } 1513fcf5ef2aSThomas Huth 1514fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1515fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1516fcf5ef2aSThomas Huth { 1517fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1518fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1519fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1520fcf5ef2aSThomas Huth tcg_temp_free(zero); 1521fcf5ef2aSThomas Huth } 1522fcf5ef2aSThomas Huth 1523fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1524fcf5ef2aSThomas Huth { 15251480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 15261480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 15271480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 15281480d71cSNikunj A Dadhania } 1529fcf5ef2aSThomas Huth } 1530fcf5ef2aSThomas Huth 1531fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1532fcf5ef2aSThomas Huth { 1533fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1534fcf5ef2aSThomas Huth } 1535fcf5ef2aSThomas Huth 1536fcf5ef2aSThomas Huth /*** Integer logical ***/ 1537fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1538fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1539fcf5ef2aSThomas Huth { \ 1540fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1541fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1542fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1543fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1544fcf5ef2aSThomas Huth } 1545fcf5ef2aSThomas Huth 1546fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1547fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1548fcf5ef2aSThomas Huth { \ 1549fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1550fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1551fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1552fcf5ef2aSThomas Huth } 1553fcf5ef2aSThomas Huth 1554fcf5ef2aSThomas Huth /* and & and. */ 1555fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1556fcf5ef2aSThomas Huth /* andc & andc. */ 1557fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1558fcf5ef2aSThomas Huth 1559fcf5ef2aSThomas Huth /* andi. */ 1560fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1561fcf5ef2aSThomas Huth { 1562fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1563fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1564fcf5ef2aSThomas Huth } 1565fcf5ef2aSThomas Huth 1566fcf5ef2aSThomas Huth /* andis. */ 1567fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1568fcf5ef2aSThomas Huth { 1569fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1570fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1571fcf5ef2aSThomas Huth } 1572fcf5ef2aSThomas Huth 1573fcf5ef2aSThomas Huth /* cntlzw */ 1574fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1575fcf5ef2aSThomas Huth { 15769b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15779b8514e5SRichard Henderson 15789b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15799b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15809b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15819b8514e5SRichard Henderson tcg_temp_free_i32(t); 15829b8514e5SRichard Henderson 1583fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1584fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1585fcf5ef2aSThomas Huth } 1586fcf5ef2aSThomas Huth 1587fcf5ef2aSThomas Huth /* cnttzw */ 1588fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1589fcf5ef2aSThomas Huth { 15909b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15919b8514e5SRichard Henderson 15929b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15939b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15949b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15959b8514e5SRichard Henderson tcg_temp_free_i32(t); 15969b8514e5SRichard Henderson 1597fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1598fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1599fcf5ef2aSThomas Huth } 1600fcf5ef2aSThomas Huth } 1601fcf5ef2aSThomas Huth 1602fcf5ef2aSThomas Huth /* eqv & eqv. */ 1603fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1604fcf5ef2aSThomas Huth /* extsb & extsb. */ 1605fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1606fcf5ef2aSThomas Huth /* extsh & extsh. */ 1607fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1608fcf5ef2aSThomas Huth /* nand & nand. */ 1609fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1610fcf5ef2aSThomas Huth /* nor & nor. */ 1611fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1612fcf5ef2aSThomas Huth 1613fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1614fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1615fcf5ef2aSThomas Huth { 1616fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1617fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1618fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1619fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1620fcf5ef2aSThomas Huth 1621fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1622b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1623fcf5ef2aSThomas Huth } 1624fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1625fcf5ef2aSThomas Huth 1626fcf5ef2aSThomas Huth /* or & or. */ 1627fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1628fcf5ef2aSThomas Huth { 1629fcf5ef2aSThomas Huth int rs, ra, rb; 1630fcf5ef2aSThomas Huth 1631fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1632fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1633fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1634fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1635fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1636fcf5ef2aSThomas Huth if (rs != rb) 1637fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1638fcf5ef2aSThomas Huth else 1639fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1640fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1641fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1642fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1643fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1644fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1645fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1646fcf5ef2aSThomas Huth int prio = 0; 1647fcf5ef2aSThomas Huth 1648fcf5ef2aSThomas Huth switch (rs) { 1649fcf5ef2aSThomas Huth case 1: 1650fcf5ef2aSThomas Huth /* Set process priority to low */ 1651fcf5ef2aSThomas Huth prio = 2; 1652fcf5ef2aSThomas Huth break; 1653fcf5ef2aSThomas Huth case 6: 1654fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1655fcf5ef2aSThomas Huth prio = 3; 1656fcf5ef2aSThomas Huth break; 1657fcf5ef2aSThomas Huth case 2: 1658fcf5ef2aSThomas Huth /* Set process priority to normal */ 1659fcf5ef2aSThomas Huth prio = 4; 1660fcf5ef2aSThomas Huth break; 1661fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1662fcf5ef2aSThomas Huth case 31: 1663fcf5ef2aSThomas Huth if (!ctx->pr) { 1664fcf5ef2aSThomas Huth /* Set process priority to very low */ 1665fcf5ef2aSThomas Huth prio = 1; 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth break; 1668fcf5ef2aSThomas Huth case 5: 1669fcf5ef2aSThomas Huth if (!ctx->pr) { 1670fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1671fcf5ef2aSThomas Huth prio = 5; 1672fcf5ef2aSThomas Huth } 1673fcf5ef2aSThomas Huth break; 1674fcf5ef2aSThomas Huth case 3: 1675fcf5ef2aSThomas Huth if (!ctx->pr) { 1676fcf5ef2aSThomas Huth /* Set process priority to high */ 1677fcf5ef2aSThomas Huth prio = 6; 1678fcf5ef2aSThomas Huth } 1679fcf5ef2aSThomas Huth break; 1680fcf5ef2aSThomas Huth case 7: 1681fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1682fcf5ef2aSThomas Huth /* Set process priority to very high */ 1683fcf5ef2aSThomas Huth prio = 7; 1684fcf5ef2aSThomas Huth } 1685fcf5ef2aSThomas Huth break; 1686fcf5ef2aSThomas Huth #endif 1687fcf5ef2aSThomas Huth default: 1688fcf5ef2aSThomas Huth break; 1689fcf5ef2aSThomas Huth } 1690fcf5ef2aSThomas Huth if (prio) { 1691fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1692fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1693fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1694fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1695fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1696fcf5ef2aSThomas Huth tcg_temp_free(t0); 1697fcf5ef2aSThomas Huth } 1698fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1699fcf5ef2aSThomas Huth /* Pause out of TCG otherwise spin loops with smt_low eat too much 1700fcf5ef2aSThomas Huth * CPU and the kernel hangs. This applies to all encodings other 1701fcf5ef2aSThomas Huth * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1702fcf5ef2aSThomas Huth * and all currently undefined. 1703fcf5ef2aSThomas Huth */ 1704fcf5ef2aSThomas Huth gen_pause(ctx); 1705fcf5ef2aSThomas Huth #endif 1706fcf5ef2aSThomas Huth #endif 1707fcf5ef2aSThomas Huth } 1708fcf5ef2aSThomas Huth } 1709fcf5ef2aSThomas Huth /* orc & orc. */ 1710fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1711fcf5ef2aSThomas Huth 1712fcf5ef2aSThomas Huth /* xor & xor. */ 1713fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1714fcf5ef2aSThomas Huth { 1715fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1716fcf5ef2aSThomas Huth if (rS(ctx->opcode) != rB(ctx->opcode)) 1717fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1718fcf5ef2aSThomas Huth else 1719fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1720fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1721fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1722fcf5ef2aSThomas Huth } 1723fcf5ef2aSThomas Huth 1724fcf5ef2aSThomas Huth /* ori */ 1725fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1726fcf5ef2aSThomas Huth { 1727fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1728fcf5ef2aSThomas Huth 1729fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1730fcf5ef2aSThomas Huth return; 1731fcf5ef2aSThomas Huth } 1732fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1733fcf5ef2aSThomas Huth } 1734fcf5ef2aSThomas Huth 1735fcf5ef2aSThomas Huth /* oris */ 1736fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1737fcf5ef2aSThomas Huth { 1738fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1739fcf5ef2aSThomas Huth 1740fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1741fcf5ef2aSThomas Huth /* NOP */ 1742fcf5ef2aSThomas Huth return; 1743fcf5ef2aSThomas Huth } 1744fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1745fcf5ef2aSThomas Huth } 1746fcf5ef2aSThomas Huth 1747fcf5ef2aSThomas Huth /* xori */ 1748fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1749fcf5ef2aSThomas Huth { 1750fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1751fcf5ef2aSThomas Huth 1752fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1753fcf5ef2aSThomas Huth /* NOP */ 1754fcf5ef2aSThomas Huth return; 1755fcf5ef2aSThomas Huth } 1756fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1757fcf5ef2aSThomas Huth } 1758fcf5ef2aSThomas Huth 1759fcf5ef2aSThomas Huth /* xoris */ 1760fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1761fcf5ef2aSThomas Huth { 1762fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1763fcf5ef2aSThomas Huth 1764fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1765fcf5ef2aSThomas Huth /* NOP */ 1766fcf5ef2aSThomas Huth return; 1767fcf5ef2aSThomas Huth } 1768fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1769fcf5ef2aSThomas Huth } 1770fcf5ef2aSThomas Huth 1771fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1772fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1773fcf5ef2aSThomas Huth { 1774fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1775fcf5ef2aSThomas Huth } 1776fcf5ef2aSThomas Huth 1777fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1778fcf5ef2aSThomas Huth { 177979770002SRichard Henderson #if defined(TARGET_PPC64) 1780fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 178179770002SRichard Henderson #else 178279770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 178379770002SRichard Henderson #endif 1784fcf5ef2aSThomas Huth } 1785fcf5ef2aSThomas Huth 1786fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1787fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1788fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1789fcf5ef2aSThomas Huth { 179079770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1791fcf5ef2aSThomas Huth } 1792fcf5ef2aSThomas Huth #endif 1793fcf5ef2aSThomas Huth 1794fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1795fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1796fcf5ef2aSThomas Huth { 1797fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1798fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1799fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1800fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1801fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1802fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1803fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1804fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1805fcf5ef2aSThomas Huth tcg_temp_free(t0); 1806fcf5ef2aSThomas Huth } 1807fcf5ef2aSThomas Huth 1808fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1809fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1810fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1811fcf5ef2aSThomas Huth { 1812fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1813fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1814fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1815fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1816fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1817fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1818fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1819fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1820fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1821fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1822fcf5ef2aSThomas Huth tcg_temp_free(t0); 1823fcf5ef2aSThomas Huth } 1824fcf5ef2aSThomas Huth #endif 1825fcf5ef2aSThomas Huth 1826fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1827fcf5ef2aSThomas Huth /* bpermd */ 1828fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1829fcf5ef2aSThomas Huth { 1830fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1831fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1832fcf5ef2aSThomas Huth } 1833fcf5ef2aSThomas Huth #endif 1834fcf5ef2aSThomas Huth 1835fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1836fcf5ef2aSThomas Huth /* extsw & extsw. */ 1837fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1838fcf5ef2aSThomas Huth 1839fcf5ef2aSThomas Huth /* cntlzd */ 1840fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1841fcf5ef2aSThomas Huth { 18429b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1843fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1844fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1845fcf5ef2aSThomas Huth } 1846fcf5ef2aSThomas Huth 1847fcf5ef2aSThomas Huth /* cnttzd */ 1848fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1849fcf5ef2aSThomas Huth { 18509b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1851fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1852fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1853fcf5ef2aSThomas Huth } 1854fcf5ef2aSThomas Huth } 1855fcf5ef2aSThomas Huth 1856fcf5ef2aSThomas Huth /* darn */ 1857fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1858fcf5ef2aSThomas Huth { 1859fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1860fcf5ef2aSThomas Huth 1861fcf5ef2aSThomas Huth if (l == 0) { 1862fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1863fcf5ef2aSThomas Huth } else if (l <= 2) { 1864fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1865fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1866fcf5ef2aSThomas Huth } else { 1867fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1868fcf5ef2aSThomas Huth } 1869fcf5ef2aSThomas Huth } 1870fcf5ef2aSThomas Huth #endif 1871fcf5ef2aSThomas Huth 1872fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1873fcf5ef2aSThomas Huth 1874fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1875fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1876fcf5ef2aSThomas Huth { 1877fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1878fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1879fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1880fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1881fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1882fcf5ef2aSThomas Huth 1883fcf5ef2aSThomas Huth if (sh == (31-me) && mb <= me) { 1884fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1885fcf5ef2aSThomas Huth } else { 1886fcf5ef2aSThomas Huth target_ulong mask; 1887fcf5ef2aSThomas Huth TCGv t1; 1888fcf5ef2aSThomas Huth 1889fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1890fcf5ef2aSThomas Huth mb += 32; 1891fcf5ef2aSThomas Huth me += 32; 1892fcf5ef2aSThomas Huth #endif 1893fcf5ef2aSThomas Huth mask = MASK(mb, me); 1894fcf5ef2aSThomas Huth 1895fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1896fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1897fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1898fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1899fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1900fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1901fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1902fcf5ef2aSThomas Huth } else { 1903fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1904fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1905fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1906fcf5ef2aSThomas Huth #else 1907fcf5ef2aSThomas Huth g_assert_not_reached(); 1908fcf5ef2aSThomas Huth #endif 1909fcf5ef2aSThomas Huth } 1910fcf5ef2aSThomas Huth 1911fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1912fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1913fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1914fcf5ef2aSThomas Huth tcg_temp_free(t1); 1915fcf5ef2aSThomas Huth } 1916fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1917fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1918fcf5ef2aSThomas Huth } 1919fcf5ef2aSThomas Huth } 1920fcf5ef2aSThomas Huth 1921fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1922fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1923fcf5ef2aSThomas Huth { 1924fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1925fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 19267b4d326fSRichard Henderson int sh = SH(ctx->opcode); 19277b4d326fSRichard Henderson int mb = MB(ctx->opcode); 19287b4d326fSRichard Henderson int me = ME(ctx->opcode); 19297b4d326fSRichard Henderson int len = me - mb + 1; 19307b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1931fcf5ef2aSThomas Huth 19327b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 19337b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 19347b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 19357b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1936fcf5ef2aSThomas Huth } else { 1937fcf5ef2aSThomas Huth target_ulong mask; 1938fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1939fcf5ef2aSThomas Huth mb += 32; 1940fcf5ef2aSThomas Huth me += 32; 1941fcf5ef2aSThomas Huth #endif 1942fcf5ef2aSThomas Huth mask = MASK(mb, me); 19437b4d326fSRichard Henderson if (sh == 0) { 19447b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 19457b4d326fSRichard Henderson } else if (mask <= 0xffffffffu) { 1946fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1947fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1948fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1949fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1950fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1951fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1952fcf5ef2aSThomas Huth } else { 1953fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1954fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1955fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1956fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1957fcf5ef2aSThomas Huth #else 1958fcf5ef2aSThomas Huth g_assert_not_reached(); 1959fcf5ef2aSThomas Huth #endif 1960fcf5ef2aSThomas Huth } 1961fcf5ef2aSThomas Huth } 1962fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1963fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1964fcf5ef2aSThomas Huth } 1965fcf5ef2aSThomas Huth } 1966fcf5ef2aSThomas Huth 1967fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1968fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1969fcf5ef2aSThomas Huth { 1970fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1971fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1972fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1973fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1974fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1975fcf5ef2aSThomas Huth target_ulong mask; 1976fcf5ef2aSThomas Huth 1977fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1978fcf5ef2aSThomas Huth mb += 32; 1979fcf5ef2aSThomas Huth me += 32; 1980fcf5ef2aSThomas Huth #endif 1981fcf5ef2aSThomas Huth mask = MASK(mb, me); 1982fcf5ef2aSThomas Huth 1983fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1984fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1985fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1986fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1987fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1988fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1989fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1990fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1991fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1992fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1993fcf5ef2aSThomas Huth } else { 1994fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1995fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1996fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1997fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1998fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1999fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2000fcf5ef2aSThomas Huth #else 2001fcf5ef2aSThomas Huth g_assert_not_reached(); 2002fcf5ef2aSThomas Huth #endif 2003fcf5ef2aSThomas Huth } 2004fcf5ef2aSThomas Huth 2005fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2006fcf5ef2aSThomas Huth 2007fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2008fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2009fcf5ef2aSThomas Huth } 2010fcf5ef2aSThomas Huth } 2011fcf5ef2aSThomas Huth 2012fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2013fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2014fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2015fcf5ef2aSThomas Huth { \ 2016fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2017fcf5ef2aSThomas Huth } \ 2018fcf5ef2aSThomas Huth \ 2019fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2020fcf5ef2aSThomas Huth { \ 2021fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2022fcf5ef2aSThomas Huth } 2023fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2024fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2025fcf5ef2aSThomas Huth { \ 2026fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2027fcf5ef2aSThomas Huth } \ 2028fcf5ef2aSThomas Huth \ 2029fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2030fcf5ef2aSThomas Huth { \ 2031fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2032fcf5ef2aSThomas Huth } \ 2033fcf5ef2aSThomas Huth \ 2034fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2035fcf5ef2aSThomas Huth { \ 2036fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2037fcf5ef2aSThomas Huth } \ 2038fcf5ef2aSThomas Huth \ 2039fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2040fcf5ef2aSThomas Huth { \ 2041fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2042fcf5ef2aSThomas Huth } 2043fcf5ef2aSThomas Huth 2044fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2045fcf5ef2aSThomas Huth { 2046fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2047fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20487b4d326fSRichard Henderson int len = me - mb + 1; 20497b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2050fcf5ef2aSThomas Huth 20517b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20527b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20537b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20547b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2055fcf5ef2aSThomas Huth } else { 2056fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2057fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2058fcf5ef2aSThomas Huth } 2059fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2060fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2061fcf5ef2aSThomas Huth } 2062fcf5ef2aSThomas Huth } 2063fcf5ef2aSThomas Huth 2064fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2065fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2066fcf5ef2aSThomas Huth { 2067fcf5ef2aSThomas Huth uint32_t sh, mb; 2068fcf5ef2aSThomas Huth 2069fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2070fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2071fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2072fcf5ef2aSThomas Huth } 2073fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2074fcf5ef2aSThomas Huth 2075fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2076fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2077fcf5ef2aSThomas Huth { 2078fcf5ef2aSThomas Huth uint32_t sh, me; 2079fcf5ef2aSThomas Huth 2080fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2081fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2082fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2083fcf5ef2aSThomas Huth } 2084fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2085fcf5ef2aSThomas Huth 2086fcf5ef2aSThomas Huth /* rldic - rldic. */ 2087fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2088fcf5ef2aSThomas Huth { 2089fcf5ef2aSThomas Huth uint32_t sh, mb; 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2092fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2093fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2094fcf5ef2aSThomas Huth } 2095fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2096fcf5ef2aSThomas Huth 2097fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2098fcf5ef2aSThomas Huth { 2099fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2100fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2101fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2102fcf5ef2aSThomas Huth TCGv t0; 2103fcf5ef2aSThomas Huth 2104fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2105fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2106fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2107fcf5ef2aSThomas Huth tcg_temp_free(t0); 2108fcf5ef2aSThomas Huth 2109fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2110fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2111fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2112fcf5ef2aSThomas Huth } 2113fcf5ef2aSThomas Huth } 2114fcf5ef2aSThomas Huth 2115fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2116fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2117fcf5ef2aSThomas Huth { 2118fcf5ef2aSThomas Huth uint32_t mb; 2119fcf5ef2aSThomas Huth 2120fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2121fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2122fcf5ef2aSThomas Huth } 2123fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2124fcf5ef2aSThomas Huth 2125fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2126fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2127fcf5ef2aSThomas Huth { 2128fcf5ef2aSThomas Huth uint32_t me; 2129fcf5ef2aSThomas Huth 2130fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2131fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2132fcf5ef2aSThomas Huth } 2133fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2134fcf5ef2aSThomas Huth 2135fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2136fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2137fcf5ef2aSThomas Huth { 2138fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2139fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2140fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2141fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2142fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2143fcf5ef2aSThomas Huth 2144fcf5ef2aSThomas Huth if (mb <= me) { 2145fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2146fcf5ef2aSThomas Huth } else { 2147fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2148fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2149fcf5ef2aSThomas Huth 2150fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2151fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2152fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2153fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2154fcf5ef2aSThomas Huth tcg_temp_free(t1); 2155fcf5ef2aSThomas Huth } 2156fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2157fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2158fcf5ef2aSThomas Huth } 2159fcf5ef2aSThomas Huth } 2160fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2161fcf5ef2aSThomas Huth #endif 2162fcf5ef2aSThomas Huth 2163fcf5ef2aSThomas Huth /*** Integer shift ***/ 2164fcf5ef2aSThomas Huth 2165fcf5ef2aSThomas Huth /* slw & slw. */ 2166fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2167fcf5ef2aSThomas Huth { 2168fcf5ef2aSThomas Huth TCGv t0, t1; 2169fcf5ef2aSThomas Huth 2170fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2171fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2172fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2173fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2174fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2175fcf5ef2aSThomas Huth #else 2176fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2177fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2178fcf5ef2aSThomas Huth #endif 2179fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2180fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2181fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2182fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2183fcf5ef2aSThomas Huth tcg_temp_free(t1); 2184fcf5ef2aSThomas Huth tcg_temp_free(t0); 2185fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2186fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2187fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2188fcf5ef2aSThomas Huth } 2189fcf5ef2aSThomas Huth 2190fcf5ef2aSThomas Huth /* sraw & sraw. */ 2191fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2192fcf5ef2aSThomas Huth { 2193fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2194fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2195fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2196fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2197fcf5ef2aSThomas Huth } 2198fcf5ef2aSThomas Huth 2199fcf5ef2aSThomas Huth /* srawi & srawi. */ 2200fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2201fcf5ef2aSThomas Huth { 2202fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2203fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2204fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2205fcf5ef2aSThomas Huth if (sh == 0) { 2206fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2207fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2208af1c259fSSandipan Das if (is_isa300(ctx)) { 2209af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2210af1c259fSSandipan Das } 2211fcf5ef2aSThomas Huth } else { 2212fcf5ef2aSThomas Huth TCGv t0; 2213fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2214fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2215fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2216fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2217fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2218fcf5ef2aSThomas Huth tcg_temp_free(t0); 2219fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2220af1c259fSSandipan Das if (is_isa300(ctx)) { 2221af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2222af1c259fSSandipan Das } 2223fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2224fcf5ef2aSThomas Huth } 2225fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2226fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2227fcf5ef2aSThomas Huth } 2228fcf5ef2aSThomas Huth } 2229fcf5ef2aSThomas Huth 2230fcf5ef2aSThomas Huth /* srw & srw. */ 2231fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2232fcf5ef2aSThomas Huth { 2233fcf5ef2aSThomas Huth TCGv t0, t1; 2234fcf5ef2aSThomas Huth 2235fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2236fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2237fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2238fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2239fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2240fcf5ef2aSThomas Huth #else 2241fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2242fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2243fcf5ef2aSThomas Huth #endif 2244fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2245fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2246fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2247fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2248fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2249fcf5ef2aSThomas Huth tcg_temp_free(t1); 2250fcf5ef2aSThomas Huth tcg_temp_free(t0); 2251fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2252fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2253fcf5ef2aSThomas Huth } 2254fcf5ef2aSThomas Huth 2255fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2256fcf5ef2aSThomas Huth /* sld & sld. */ 2257fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2258fcf5ef2aSThomas Huth { 2259fcf5ef2aSThomas Huth TCGv t0, t1; 2260fcf5ef2aSThomas Huth 2261fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2262fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2263fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2264fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2265fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2266fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2267fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2268fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2269fcf5ef2aSThomas Huth tcg_temp_free(t1); 2270fcf5ef2aSThomas Huth tcg_temp_free(t0); 2271fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2272fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2273fcf5ef2aSThomas Huth } 2274fcf5ef2aSThomas Huth 2275fcf5ef2aSThomas Huth /* srad & srad. */ 2276fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2277fcf5ef2aSThomas Huth { 2278fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2279fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2280fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2281fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2282fcf5ef2aSThomas Huth } 2283fcf5ef2aSThomas Huth /* sradi & sradi. */ 2284fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2285fcf5ef2aSThomas Huth { 2286fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2287fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2288fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2289fcf5ef2aSThomas Huth if (sh == 0) { 2290fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2291fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2292af1c259fSSandipan Das if (is_isa300(ctx)) { 2293af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2294af1c259fSSandipan Das } 2295fcf5ef2aSThomas Huth } else { 2296fcf5ef2aSThomas Huth TCGv t0; 2297fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2298fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2299fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2300fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2301fcf5ef2aSThomas Huth tcg_temp_free(t0); 2302fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2303af1c259fSSandipan Das if (is_isa300(ctx)) { 2304af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2305af1c259fSSandipan Das } 2306fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2307fcf5ef2aSThomas Huth } 2308fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2309fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2310fcf5ef2aSThomas Huth } 2311fcf5ef2aSThomas Huth } 2312fcf5ef2aSThomas Huth 2313fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2314fcf5ef2aSThomas Huth { 2315fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2316fcf5ef2aSThomas Huth } 2317fcf5ef2aSThomas Huth 2318fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2319fcf5ef2aSThomas Huth { 2320fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2321fcf5ef2aSThomas Huth } 2322fcf5ef2aSThomas Huth 2323fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2324fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2325fcf5ef2aSThomas Huth { 2326fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2327fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2328fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2329fcf5ef2aSThomas Huth 2330fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2331fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2332fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2333fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2334fcf5ef2aSThomas Huth } 2335fcf5ef2aSThomas Huth } 2336fcf5ef2aSThomas Huth 2337fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2338fcf5ef2aSThomas Huth { 2339fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2340fcf5ef2aSThomas Huth } 2341fcf5ef2aSThomas Huth 2342fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2343fcf5ef2aSThomas Huth { 2344fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2345fcf5ef2aSThomas Huth } 2346fcf5ef2aSThomas Huth 2347fcf5ef2aSThomas Huth /* srd & srd. */ 2348fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2349fcf5ef2aSThomas Huth { 2350fcf5ef2aSThomas Huth TCGv t0, t1; 2351fcf5ef2aSThomas Huth 2352fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2353fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2354fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2355fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2356fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2357fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2358fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2359fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2360fcf5ef2aSThomas Huth tcg_temp_free(t1); 2361fcf5ef2aSThomas Huth tcg_temp_free(t0); 2362fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2363fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2364fcf5ef2aSThomas Huth } 2365fcf5ef2aSThomas Huth #endif 2366fcf5ef2aSThomas Huth 2367fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2368fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2369fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2370fcf5ef2aSThomas Huth target_long maskl) 2371fcf5ef2aSThomas Huth { 2372fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2373fcf5ef2aSThomas Huth 2374fcf5ef2aSThomas Huth simm &= ~maskl; 2375fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2376fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2377fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2378fcf5ef2aSThomas Huth } 2379fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2380fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2381fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2382fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2383fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth } else { 2386fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2387fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2388fcf5ef2aSThomas Huth } else { 2389fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2390fcf5ef2aSThomas Huth } 2391fcf5ef2aSThomas Huth } 2392fcf5ef2aSThomas Huth } 2393fcf5ef2aSThomas Huth 2394fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2395fcf5ef2aSThomas Huth { 2396fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2397fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2398fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2399fcf5ef2aSThomas Huth } else { 2400fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2401fcf5ef2aSThomas Huth } 2402fcf5ef2aSThomas Huth } else { 2403fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2404fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2405fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2406fcf5ef2aSThomas Huth } 2407fcf5ef2aSThomas Huth } 2408fcf5ef2aSThomas Huth } 2409fcf5ef2aSThomas Huth 2410fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2411fcf5ef2aSThomas Huth { 2412fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2413fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2414fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2415fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2416fcf5ef2aSThomas Huth } else { 2417fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2418fcf5ef2aSThomas Huth } 2419fcf5ef2aSThomas Huth } 2420fcf5ef2aSThomas Huth 2421fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2422fcf5ef2aSThomas Huth target_long val) 2423fcf5ef2aSThomas Huth { 2424fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2425fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2426fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2427fcf5ef2aSThomas Huth } 2428fcf5ef2aSThomas Huth } 2429fcf5ef2aSThomas Huth 2430fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2431fcf5ef2aSThomas Huth { 2432fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2433fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2434fcf5ef2aSThomas Huth } 2435fcf5ef2aSThomas Huth 2436fcf5ef2aSThomas Huth /*** Integer load ***/ 2437fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2438fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2439fcf5ef2aSThomas Huth 2440fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2441fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2442fcf5ef2aSThomas Huth TCGv val, \ 2443fcf5ef2aSThomas Huth TCGv addr) \ 2444fcf5ef2aSThomas Huth { \ 2445fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2446fcf5ef2aSThomas Huth } 2447fcf5ef2aSThomas Huth 2448fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2449fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2450fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2451fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2452fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2453fcf5ef2aSThomas Huth 2454fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2455fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2456fcf5ef2aSThomas Huth 2457fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2458fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2459fcf5ef2aSThomas Huth TCGv_i64 val, \ 2460fcf5ef2aSThomas Huth TCGv addr) \ 2461fcf5ef2aSThomas Huth { \ 2462fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2463fcf5ef2aSThomas Huth } 2464fcf5ef2aSThomas Huth 2465fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2466fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2467fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2468fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2469fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2470fcf5ef2aSThomas Huth 2471fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2472fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2473fcf5ef2aSThomas Huth #endif 2474fcf5ef2aSThomas Huth 2475fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2476fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2477fcf5ef2aSThomas Huth TCGv val, \ 2478fcf5ef2aSThomas Huth TCGv addr) \ 2479fcf5ef2aSThomas Huth { \ 2480fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2481fcf5ef2aSThomas Huth } 2482fcf5ef2aSThomas Huth 2483fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2484fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2485fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2486fcf5ef2aSThomas Huth 2487fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2488fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2489fcf5ef2aSThomas Huth 2490fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2491fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2492fcf5ef2aSThomas Huth TCGv_i64 val, \ 2493fcf5ef2aSThomas Huth TCGv addr) \ 2494fcf5ef2aSThomas Huth { \ 2495fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2496fcf5ef2aSThomas Huth } 2497fcf5ef2aSThomas Huth 2498fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2499fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2500fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2501fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2502fcf5ef2aSThomas Huth 2503fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2504fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2505fcf5ef2aSThomas Huth #endif 2506fcf5ef2aSThomas Huth 2507fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2508fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2509fcf5ef2aSThomas Huth { \ 2510fcf5ef2aSThomas Huth TCGv EA; \ 2511fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2512fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2513fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2514fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2515fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2516fcf5ef2aSThomas Huth } 2517fcf5ef2aSThomas Huth 2518fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2519fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2520fcf5ef2aSThomas Huth { \ 2521fcf5ef2aSThomas Huth TCGv EA; \ 2522fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2523fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2524fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2525fcf5ef2aSThomas Huth return; \ 2526fcf5ef2aSThomas Huth } \ 2527fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2528fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2529fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2530fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2531fcf5ef2aSThomas Huth else \ 2532fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2533fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2534fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2535fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2536fcf5ef2aSThomas Huth } 2537fcf5ef2aSThomas Huth 2538fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2539fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2540fcf5ef2aSThomas Huth { \ 2541fcf5ef2aSThomas Huth TCGv EA; \ 2542fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2543fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2544fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2545fcf5ef2aSThomas Huth return; \ 2546fcf5ef2aSThomas Huth } \ 2547fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2548fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2549fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2550fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2551fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2552fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2553fcf5ef2aSThomas Huth } 2554fcf5ef2aSThomas Huth 2555fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2556fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2557fcf5ef2aSThomas Huth { \ 2558fcf5ef2aSThomas Huth TCGv EA; \ 2559fcf5ef2aSThomas Huth chk; \ 2560fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2561fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2562fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2563fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2564fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2565fcf5ef2aSThomas Huth } 2566fcf5ef2aSThomas Huth 2567fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2568fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2569fcf5ef2aSThomas Huth 2570fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2571fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2572fcf5ef2aSThomas Huth 2573fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2574fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2575fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2576fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2577fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2578fcf5ef2aSThomas Huth 2579fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2580fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2581fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2582fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2583fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2584fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2585fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2586fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 258750728199SRoman Kapl 258850728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 258950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 259050728199SRoman Kapl { \ 259150728199SRoman Kapl TCGv EA; \ 259250728199SRoman Kapl CHK_SV; \ 259350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 259450728199SRoman Kapl EA = tcg_temp_new(); \ 259550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 259650728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 259750728199SRoman Kapl tcg_temp_free(EA); \ 259850728199SRoman Kapl } 259950728199SRoman Kapl 260050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 260150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 260250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 260350728199SRoman Kapl #if defined(TARGET_PPC64) 260450728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 260550728199SRoman Kapl #endif 260650728199SRoman Kapl 2607fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2608fcf5ef2aSThomas Huth /* lwaux */ 2609fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2610fcf5ef2aSThomas Huth /* lwax */ 2611fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2612fcf5ef2aSThomas Huth /* ldux */ 2613fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2614fcf5ef2aSThomas Huth /* ldx */ 2615fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2616fcf5ef2aSThomas Huth 2617fcf5ef2aSThomas Huth /* CI load/store variants */ 2618fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2619fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2620fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2621fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2622fcf5ef2aSThomas Huth 2623fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2624fcf5ef2aSThomas Huth { 2625fcf5ef2aSThomas Huth TCGv EA; 2626fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2627fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2628fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2629fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2630fcf5ef2aSThomas Huth return; 2631fcf5ef2aSThomas Huth } 2632fcf5ef2aSThomas Huth } 2633fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2634fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2635fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2636fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2637fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2638fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2639fcf5ef2aSThomas Huth } else { 2640fcf5ef2aSThomas Huth /* ld - ldu */ 2641fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2642fcf5ef2aSThomas Huth } 2643fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2644fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2645fcf5ef2aSThomas Huth tcg_temp_free(EA); 2646fcf5ef2aSThomas Huth } 2647fcf5ef2aSThomas Huth 2648fcf5ef2aSThomas Huth /* lq */ 2649fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2650fcf5ef2aSThomas Huth { 2651fcf5ef2aSThomas Huth int ra, rd; 265294bf2658SRichard Henderson TCGv EA, hi, lo; 2653fcf5ef2aSThomas Huth 2654fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2655fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2656fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2657fcf5ef2aSThomas Huth 2658fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2659fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2660fcf5ef2aSThomas Huth return; 2661fcf5ef2aSThomas Huth } 2662fcf5ef2aSThomas Huth 2663fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2664fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2665fcf5ef2aSThomas Huth return; 2666fcf5ef2aSThomas Huth } 2667fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2668fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2669fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2670fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2671fcf5ef2aSThomas Huth return; 2672fcf5ef2aSThomas Huth } 2673fcf5ef2aSThomas Huth 2674fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2675fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2676fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2677fcf5ef2aSThomas Huth 267894bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 267994bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 268094bf2658SRichard Henderson hi = cpu_gpr[rd]; 268194bf2658SRichard Henderson 268294bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2683f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 268494bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 268594bf2658SRichard Henderson if (ctx->le_mode) { 268694bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 268794bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2688fcf5ef2aSThomas Huth } else { 268994bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 269094bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 269194bf2658SRichard Henderson } 269294bf2658SRichard Henderson tcg_temp_free_i32(oi); 269394bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2694f34ec0f6SRichard Henderson } else { 269594bf2658SRichard Henderson /* Restart with exclusive lock. */ 269694bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 269794bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2698f34ec0f6SRichard Henderson } 269994bf2658SRichard Henderson } else if (ctx->le_mode) { 270094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2701fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 270294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 270394bf2658SRichard Henderson } else { 270494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 270594bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 270694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2707fcf5ef2aSThomas Huth } 2708fcf5ef2aSThomas Huth tcg_temp_free(EA); 2709fcf5ef2aSThomas Huth } 2710fcf5ef2aSThomas Huth #endif 2711fcf5ef2aSThomas Huth 2712fcf5ef2aSThomas Huth /*** Integer store ***/ 2713fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2714fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2715fcf5ef2aSThomas Huth { \ 2716fcf5ef2aSThomas Huth TCGv EA; \ 2717fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2718fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2719fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2720fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2721fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2722fcf5ef2aSThomas Huth } 2723fcf5ef2aSThomas Huth 2724fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2725fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2726fcf5ef2aSThomas Huth { \ 2727fcf5ef2aSThomas Huth TCGv EA; \ 2728fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2729fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2730fcf5ef2aSThomas Huth return; \ 2731fcf5ef2aSThomas Huth } \ 2732fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2733fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2734fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2735fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2736fcf5ef2aSThomas Huth else \ 2737fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2738fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2739fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2740fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2741fcf5ef2aSThomas Huth } 2742fcf5ef2aSThomas Huth 2743fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2744fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2745fcf5ef2aSThomas Huth { \ 2746fcf5ef2aSThomas Huth TCGv EA; \ 2747fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2748fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2749fcf5ef2aSThomas Huth return; \ 2750fcf5ef2aSThomas Huth } \ 2751fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2752fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2753fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2754fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2755fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2756fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2757fcf5ef2aSThomas Huth } 2758fcf5ef2aSThomas Huth 2759fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2760fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2761fcf5ef2aSThomas Huth { \ 2762fcf5ef2aSThomas Huth TCGv EA; \ 2763fcf5ef2aSThomas Huth chk; \ 2764fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2765fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2766fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2767fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2768fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2769fcf5ef2aSThomas Huth } 2770fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2771fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2772fcf5ef2aSThomas Huth 2773fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2774fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2775fcf5ef2aSThomas Huth 2776fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2777fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2778fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2779fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2780fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2781fcf5ef2aSThomas Huth 2782fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2783fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2784fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2785fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2786fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2787fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 278850728199SRoman Kapl 278950728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 279050728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 279150728199SRoman Kapl { \ 279250728199SRoman Kapl TCGv EA; \ 279350728199SRoman Kapl CHK_SV; \ 279450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 279550728199SRoman Kapl EA = tcg_temp_new(); \ 279650728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 279750728199SRoman Kapl tcg_gen_qemu_st_tl( \ 279850728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 279950728199SRoman Kapl tcg_temp_free(EA); \ 280050728199SRoman Kapl } 280150728199SRoman Kapl 280250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 280350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 280450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 280550728199SRoman Kapl #if defined(TARGET_PPC64) 280650728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 280750728199SRoman Kapl #endif 280850728199SRoman Kapl 2809fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2810fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2811fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2812fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2813fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2814fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2815fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2816fcf5ef2aSThomas Huth 2817fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2818fcf5ef2aSThomas Huth { 2819fcf5ef2aSThomas Huth int rs; 2820fcf5ef2aSThomas Huth TCGv EA; 2821fcf5ef2aSThomas Huth 2822fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2823fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2824fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2825fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2826f89ced5fSRichard Henderson TCGv hi, lo; 2827fcf5ef2aSThomas Huth 2828fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2829fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2830fcf5ef2aSThomas Huth } 2831fcf5ef2aSThomas Huth 2832fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2833fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2834fcf5ef2aSThomas Huth return; 2835fcf5ef2aSThomas Huth } 2836fcf5ef2aSThomas Huth 2837fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2838fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2839fcf5ef2aSThomas Huth return; 2840fcf5ef2aSThomas Huth } 2841fcf5ef2aSThomas Huth 2842fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2843fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2844fcf5ef2aSThomas Huth return; 2845fcf5ef2aSThomas Huth } 2846fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2847fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2848fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2849fcf5ef2aSThomas Huth 2850f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 2851f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 2852f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 2853f89ced5fSRichard Henderson 2854f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2855f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 2856f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 2857f89ced5fSRichard Henderson if (ctx->le_mode) { 2858f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2859f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2860fcf5ef2aSThomas Huth } else { 2861f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2862f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2863f89ced5fSRichard Henderson } 2864f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 2865f34ec0f6SRichard Henderson } else { 2866f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 2867f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 2868f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2869f34ec0f6SRichard Henderson } 2870f89ced5fSRichard Henderson } else if (ctx->le_mode) { 2871f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2872fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2873f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2874f89ced5fSRichard Henderson } else { 2875f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2876f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 2877f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2878fcf5ef2aSThomas Huth } 2879fcf5ef2aSThomas Huth tcg_temp_free(EA); 2880fcf5ef2aSThomas Huth } else { 2881fcf5ef2aSThomas Huth /* std / stdu */ 2882fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2883fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2884fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2885fcf5ef2aSThomas Huth return; 2886fcf5ef2aSThomas Huth } 2887fcf5ef2aSThomas Huth } 2888fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2889fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2890fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2891fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2892fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2893fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2894fcf5ef2aSThomas Huth tcg_temp_free(EA); 2895fcf5ef2aSThomas Huth } 2896fcf5ef2aSThomas Huth } 2897fcf5ef2aSThomas Huth #endif 2898fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2899fcf5ef2aSThomas Huth 2900fcf5ef2aSThomas Huth /* lhbrx */ 2901fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2902fcf5ef2aSThomas Huth 2903fcf5ef2aSThomas Huth /* lwbrx */ 2904fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2905fcf5ef2aSThomas Huth 2906fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2907fcf5ef2aSThomas Huth /* ldbrx */ 2908fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2909fcf5ef2aSThomas Huth /* stdbrx */ 2910fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2911fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2912fcf5ef2aSThomas Huth 2913fcf5ef2aSThomas Huth /* sthbrx */ 2914fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2915fcf5ef2aSThomas Huth /* stwbrx */ 2916fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2917fcf5ef2aSThomas Huth 2918fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2919fcf5ef2aSThomas Huth 2920fcf5ef2aSThomas Huth /* lmw */ 2921fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2922fcf5ef2aSThomas Huth { 2923fcf5ef2aSThomas Huth TCGv t0; 2924fcf5ef2aSThomas Huth TCGv_i32 t1; 2925fcf5ef2aSThomas Huth 2926fcf5ef2aSThomas Huth if (ctx->le_mode) { 2927fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2928fcf5ef2aSThomas Huth return; 2929fcf5ef2aSThomas Huth } 2930fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2931fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2932fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2933fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2934fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2935fcf5ef2aSThomas Huth tcg_temp_free(t0); 2936fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2937fcf5ef2aSThomas Huth } 2938fcf5ef2aSThomas Huth 2939fcf5ef2aSThomas Huth /* stmw */ 2940fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2941fcf5ef2aSThomas Huth { 2942fcf5ef2aSThomas Huth TCGv t0; 2943fcf5ef2aSThomas Huth TCGv_i32 t1; 2944fcf5ef2aSThomas Huth 2945fcf5ef2aSThomas Huth if (ctx->le_mode) { 2946fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2947fcf5ef2aSThomas Huth return; 2948fcf5ef2aSThomas Huth } 2949fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2950fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2951fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2952fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2953fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2954fcf5ef2aSThomas Huth tcg_temp_free(t0); 2955fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2956fcf5ef2aSThomas Huth } 2957fcf5ef2aSThomas Huth 2958fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2959fcf5ef2aSThomas Huth 2960fcf5ef2aSThomas Huth /* lswi */ 2961fcf5ef2aSThomas Huth /* PowerPC32 specification says we must generate an exception if 2962fcf5ef2aSThomas Huth * rA is in the range of registers to be loaded. 2963fcf5ef2aSThomas Huth * In an other hand, IBM says this is valid, but rA won't be loaded. 2964fcf5ef2aSThomas Huth * For now, I'll follow the spec... 2965fcf5ef2aSThomas Huth */ 2966fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2967fcf5ef2aSThomas Huth { 2968fcf5ef2aSThomas Huth TCGv t0; 2969fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2970fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2971fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2972fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2973fcf5ef2aSThomas Huth int nr; 2974fcf5ef2aSThomas Huth 2975fcf5ef2aSThomas Huth if (ctx->le_mode) { 2976fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2977fcf5ef2aSThomas Huth return; 2978fcf5ef2aSThomas Huth } 2979fcf5ef2aSThomas Huth if (nb == 0) 2980fcf5ef2aSThomas Huth nb = 32; 2981f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 2982fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2983fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2984fcf5ef2aSThomas Huth return; 2985fcf5ef2aSThomas Huth } 2986fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2987fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2988fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2989fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2990fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 2991fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 2992fcf5ef2aSThomas Huth tcg_temp_free(t0); 2993fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2994fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2995fcf5ef2aSThomas Huth } 2996fcf5ef2aSThomas Huth 2997fcf5ef2aSThomas Huth /* lswx */ 2998fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 2999fcf5ef2aSThomas Huth { 3000fcf5ef2aSThomas Huth TCGv t0; 3001fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3002fcf5ef2aSThomas Huth 3003fcf5ef2aSThomas Huth if (ctx->le_mode) { 3004fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3005fcf5ef2aSThomas Huth return; 3006fcf5ef2aSThomas Huth } 3007fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3008fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3009fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3010fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3011fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3012fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3013fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3014fcf5ef2aSThomas Huth tcg_temp_free(t0); 3015fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3016fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3017fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3018fcf5ef2aSThomas Huth } 3019fcf5ef2aSThomas Huth 3020fcf5ef2aSThomas Huth /* stswi */ 3021fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3022fcf5ef2aSThomas Huth { 3023fcf5ef2aSThomas Huth TCGv t0; 3024fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3025fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3026fcf5ef2aSThomas Huth 3027fcf5ef2aSThomas Huth if (ctx->le_mode) { 3028fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3029fcf5ef2aSThomas Huth return; 3030fcf5ef2aSThomas Huth } 3031fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3032fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3033fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3034fcf5ef2aSThomas Huth if (nb == 0) 3035fcf5ef2aSThomas Huth nb = 32; 3036fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3037fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3038fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3039fcf5ef2aSThomas Huth tcg_temp_free(t0); 3040fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3041fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3042fcf5ef2aSThomas Huth } 3043fcf5ef2aSThomas Huth 3044fcf5ef2aSThomas Huth /* stswx */ 3045fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3046fcf5ef2aSThomas Huth { 3047fcf5ef2aSThomas Huth TCGv t0; 3048fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3049fcf5ef2aSThomas Huth 3050fcf5ef2aSThomas Huth if (ctx->le_mode) { 3051fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3052fcf5ef2aSThomas Huth return; 3053fcf5ef2aSThomas Huth } 3054fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3055fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3056fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3057fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3058fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3059fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3060fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3061fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3062fcf5ef2aSThomas Huth tcg_temp_free(t0); 3063fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3064fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3065fcf5ef2aSThomas Huth } 3066fcf5ef2aSThomas Huth 3067fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3068fcf5ef2aSThomas Huth /* eieio */ 3069fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3070fcf5ef2aSThomas Huth { 3071c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3072c8fd8373SCédric Le Goater 3073c8fd8373SCédric Le Goater /* 3074c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3075c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3076c8fd8373SCédric Le Goater */ 3077c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3078c8fd8373SCédric Le Goater /* 3079c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3080c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3081c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3082c8fd8373SCédric Le Goater * complain to the user. 3083c8fd8373SCédric Le Goater */ 3084c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3085c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3086c8fd8373SCédric Le Goater TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3087c8fd8373SCédric Le Goater } else { 3088c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3089c8fd8373SCédric Le Goater } 3090c8fd8373SCédric Le Goater } 3091c8fd8373SCédric Le Goater 3092c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3093fcf5ef2aSThomas Huth } 3094fcf5ef2aSThomas Huth 3095fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3096fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3097fcf5ef2aSThomas Huth { 3098fcf5ef2aSThomas Huth TCGv_i32 t; 3099fcf5ef2aSThomas Huth TCGLabel *l; 3100fcf5ef2aSThomas Huth 3101fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3102fcf5ef2aSThomas Huth return; 3103fcf5ef2aSThomas Huth } 3104fcf5ef2aSThomas Huth l = gen_new_label(); 3105fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3106fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3107fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3108fcf5ef2aSThomas Huth if (global) { 3109fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3110fcf5ef2aSThomas Huth } else { 3111fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3112fcf5ef2aSThomas Huth } 3113fcf5ef2aSThomas Huth gen_set_label(l); 3114fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3115fcf5ef2aSThomas Huth } 3116fcf5ef2aSThomas Huth #else 3117fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3118fcf5ef2aSThomas Huth #endif 3119fcf5ef2aSThomas Huth 3120fcf5ef2aSThomas Huth /* isync */ 3121fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3122fcf5ef2aSThomas Huth { 3123fcf5ef2aSThomas Huth /* 3124fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3125fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3126fcf5ef2aSThomas Huth */ 3127fcf5ef2aSThomas Huth if (!ctx->pr) { 3128fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3129fcf5ef2aSThomas Huth } 31304771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3131fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3132fcf5ef2aSThomas Huth } 3133fcf5ef2aSThomas Huth 3134fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3135fcf5ef2aSThomas Huth 31362a4e6c1bSRichard Henderson static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) 31372a4e6c1bSRichard Henderson { 31382a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 31392a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 31402a4e6c1bSRichard Henderson 31412a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 31422a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 31432a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 31442a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 31452a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 31462a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 31472a4e6c1bSRichard Henderson tcg_temp_free(t0); 31482a4e6c1bSRichard Henderson } 31492a4e6c1bSRichard Henderson 3150fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3151fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3152fcf5ef2aSThomas Huth { \ 31532a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3154fcf5ef2aSThomas Huth } 3155fcf5ef2aSThomas Huth 3156fcf5ef2aSThomas Huth /* lwarx */ 3157fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3158fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3159fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3160fcf5ef2aSThomas Huth 316120923c1dSRichard Henderson static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, 316220923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 316320923c1dSRichard Henderson { 316420923c1dSRichard Henderson TCGv t = tcg_temp_new(); 316520923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 316620923c1dSRichard Henderson TCGv u = tcg_temp_new(); 316720923c1dSRichard Henderson 316820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 316920923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 317020923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 317120923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 317220923c1dSRichard Henderson 317320923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 317420923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 317520923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 317620923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 317720923c1dSRichard Henderson 317820923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 317920923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 318020923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 318120923c1dSRichard Henderson 318220923c1dSRichard Henderson tcg_temp_free(t); 318320923c1dSRichard Henderson tcg_temp_free(t2); 318420923c1dSRichard Henderson tcg_temp_free(u); 318520923c1dSRichard Henderson } 318620923c1dSRichard Henderson 318720ba8504SRichard Henderson static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) 318820ba8504SRichard Henderson { 318920ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 319020ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 319120923c1dSRichard Henderson int rt = rD(ctx->opcode); 319220923c1dSRichard Henderson bool need_serial; 319320ba8504SRichard Henderson TCGv src, dst; 319420ba8504SRichard Henderson 319520ba8504SRichard Henderson gen_addr_register(ctx, EA); 319620923c1dSRichard Henderson dst = cpu_gpr[rt]; 319720923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 319820ba8504SRichard Henderson 319920923c1dSRichard Henderson need_serial = false; 320020ba8504SRichard Henderson memop |= MO_ALIGN; 320120ba8504SRichard Henderson switch (gpr_FC) { 320220ba8504SRichard Henderson case 0: /* Fetch and add */ 320320ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 320420ba8504SRichard Henderson break; 320520ba8504SRichard Henderson case 1: /* Fetch and xor */ 320620ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 320720ba8504SRichard Henderson break; 320820ba8504SRichard Henderson case 2: /* Fetch and or */ 320920ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 321020ba8504SRichard Henderson break; 321120ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 321220ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 321320ba8504SRichard Henderson break; 3214b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3215b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3216b8ce0f86SRichard Henderson break; 3217b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3218b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3219b8ce0f86SRichard Henderson break; 3220b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3221b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3222b8ce0f86SRichard Henderson break; 3223b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3224b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3225b8ce0f86SRichard Henderson break; 322620ba8504SRichard Henderson case 8: /* Swap */ 322720ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 322820ba8504SRichard Henderson break; 322920923c1dSRichard Henderson 323020923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 323120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 323220923c1dSRichard Henderson need_serial = true; 323320923c1dSRichard Henderson } else { 323420923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 323520923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 323620923c1dSRichard Henderson 323720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 323820923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 323920923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 324020923c1dSRichard Henderson } else { 324120923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 324220923c1dSRichard Henderson } 324320923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 324420923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 324520923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 324620923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 324720923c1dSRichard Henderson 324820923c1dSRichard Henderson tcg_temp_free(t0); 324920923c1dSRichard Henderson tcg_temp_free(t1); 325020923c1dSRichard Henderson } 325120ba8504SRichard Henderson break; 325220923c1dSRichard Henderson 325320923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 325420923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 325520923c1dSRichard Henderson need_serial = true; 325620923c1dSRichard Henderson } else { 325720923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 325820923c1dSRichard Henderson } 325920923c1dSRichard Henderson break; 326020923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 326120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 326220923c1dSRichard Henderson need_serial = true; 326320923c1dSRichard Henderson } else { 326420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 326520923c1dSRichard Henderson } 326620923c1dSRichard Henderson break; 326720923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 326820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 326920923c1dSRichard Henderson need_serial = true; 327020923c1dSRichard Henderson } else { 327120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 327220923c1dSRichard Henderson } 327320923c1dSRichard Henderson break; 327420923c1dSRichard Henderson 327520ba8504SRichard Henderson default: 327620ba8504SRichard Henderson /* invoke data storage error handler */ 327720ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 327820ba8504SRichard Henderson } 327920ba8504SRichard Henderson tcg_temp_free(EA); 328020923c1dSRichard Henderson 328120923c1dSRichard Henderson if (need_serial) { 328220923c1dSRichard Henderson /* Restart with exclusive lock. */ 328320923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 328420923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 328520923c1dSRichard Henderson } 3286a68a6146SBalamuruhan S } 3287a68a6146SBalamuruhan S 328820ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 328920ba8504SRichard Henderson { 329020ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 329120ba8504SRichard Henderson } 329220ba8504SRichard Henderson 329320ba8504SRichard Henderson #ifdef TARGET_PPC64 329420ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 329520ba8504SRichard Henderson { 329620ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 329720ba8504SRichard Henderson } 3298a68a6146SBalamuruhan S #endif 3299a68a6146SBalamuruhan S 33009deb041cSRichard Henderson static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) 33019deb041cSRichard Henderson { 33029deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 33039deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 33049deb041cSRichard Henderson TCGv src, discard; 33059deb041cSRichard Henderson 33069deb041cSRichard Henderson gen_addr_register(ctx, EA); 33079deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 33089deb041cSRichard Henderson discard = tcg_temp_new(); 33099deb041cSRichard Henderson 33109deb041cSRichard Henderson memop |= MO_ALIGN; 33119deb041cSRichard Henderson switch (gpr_FC) { 33129deb041cSRichard Henderson case 0: /* add and Store */ 33139deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33149deb041cSRichard Henderson break; 33159deb041cSRichard Henderson case 1: /* xor and Store */ 33169deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33179deb041cSRichard Henderson break; 33189deb041cSRichard Henderson case 2: /* Or and Store */ 33199deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33209deb041cSRichard Henderson break; 33219deb041cSRichard Henderson case 3: /* 'and' and Store */ 33229deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33239deb041cSRichard Henderson break; 33249deb041cSRichard Henderson case 4: /* Store max unsigned */ 3325b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3326b8ce0f86SRichard Henderson break; 33279deb041cSRichard Henderson case 5: /* Store max signed */ 3328b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3329b8ce0f86SRichard Henderson break; 33309deb041cSRichard Henderson case 6: /* Store min unsigned */ 3331b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3332b8ce0f86SRichard Henderson break; 33339deb041cSRichard Henderson case 7: /* Store min signed */ 3334b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3335b8ce0f86SRichard Henderson break; 33369deb041cSRichard Henderson case 24: /* Store twin */ 33377fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 33387fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 33397fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 33407fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 33417fbc2b20SRichard Henderson } else { 33427fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 33437fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 33447fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 33457fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 33467fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 33477fbc2b20SRichard Henderson 33487fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 33497fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 33507fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 33517fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 33527fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 33537fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 33547fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 33557fbc2b20SRichard Henderson 33567fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 33577fbc2b20SRichard Henderson tcg_temp_free(s2); 33587fbc2b20SRichard Henderson tcg_temp_free(s); 33597fbc2b20SRichard Henderson tcg_temp_free(t2); 33607fbc2b20SRichard Henderson tcg_temp_free(t); 33617fbc2b20SRichard Henderson } 33629deb041cSRichard Henderson break; 33639deb041cSRichard Henderson default: 33649deb041cSRichard Henderson /* invoke data storage error handler */ 33659deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 33669deb041cSRichard Henderson } 33679deb041cSRichard Henderson tcg_temp_free(discard); 33689deb041cSRichard Henderson tcg_temp_free(EA); 3369a3401188SBalamuruhan S } 3370a3401188SBalamuruhan S 33719deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 33729deb041cSRichard Henderson { 33739deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 33749deb041cSRichard Henderson } 33759deb041cSRichard Henderson 33769deb041cSRichard Henderson #ifdef TARGET_PPC64 33779deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 33789deb041cSRichard Henderson { 33799deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 33809deb041cSRichard Henderson } 3381a3401188SBalamuruhan S #endif 3382a3401188SBalamuruhan S 3383d8b86898SRichard Henderson static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) 3384fcf5ef2aSThomas Huth { 3385253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3386253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3387d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3388d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3389fcf5ef2aSThomas Huth 3390d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3391d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3392d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3393d8b86898SRichard Henderson tcg_temp_free(t0); 3394253ce7b2SNikunj A Dadhania 3395253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3396253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3397253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3398253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3399253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3400253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3401253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3402253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3403253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3404253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3405253ce7b2SNikunj A Dadhania 3406fcf5ef2aSThomas Huth gen_set_label(l1); 34074771df23SNikunj A Dadhania 34084771df23SNikunj A Dadhania /* Address mismatch implies failure. But we still need to provide the 34094771df23SNikunj A Dadhania memory barrier semantics of the instruction. */ 34104771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3411253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3412253ce7b2SNikunj A Dadhania 3413253ce7b2SNikunj A Dadhania gen_set_label(l2); 3414fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3415fcf5ef2aSThomas Huth } 3416fcf5ef2aSThomas Huth 3417fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3418fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3419fcf5ef2aSThomas Huth { \ 3420d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3421fcf5ef2aSThomas Huth } 3422fcf5ef2aSThomas Huth 3423fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3424fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3425fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3426fcf5ef2aSThomas Huth 3427fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3428fcf5ef2aSThomas Huth /* ldarx */ 3429fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3430fcf5ef2aSThomas Huth /* stdcx. */ 3431fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3432fcf5ef2aSThomas Huth 3433fcf5ef2aSThomas Huth /* lqarx */ 3434fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3435fcf5ef2aSThomas Huth { 3436fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 343794bf2658SRichard Henderson TCGv EA, hi, lo; 3438fcf5ef2aSThomas Huth 3439fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3440fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3441fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3442fcf5ef2aSThomas Huth return; 3443fcf5ef2aSThomas Huth } 3444fcf5ef2aSThomas Huth 3445fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 344694bf2658SRichard Henderson EA = tcg_temp_new(); 3447fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 344894bf2658SRichard Henderson 344994bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 345094bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 345194bf2658SRichard Henderson hi = cpu_gpr[rd]; 345294bf2658SRichard Henderson 345394bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3454f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 345594bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 345694bf2658SRichard Henderson if (ctx->le_mode) { 345794bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 345894bf2658SRichard Henderson ctx->mem_idx)); 345994bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3460fcf5ef2aSThomas Huth } else { 346194bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 346294bf2658SRichard Henderson ctx->mem_idx)); 346394bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3464fcf5ef2aSThomas Huth } 346594bf2658SRichard Henderson tcg_temp_free_i32(oi); 346694bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3467f34ec0f6SRichard Henderson } else { 346894bf2658SRichard Henderson /* Restart with exclusive lock. */ 346994bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 347094bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 347194bf2658SRichard Henderson tcg_temp_free(EA); 347294bf2658SRichard Henderson return; 3473f34ec0f6SRichard Henderson } 347494bf2658SRichard Henderson } else if (ctx->le_mode) { 347594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3476fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3477fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 347894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 347994bf2658SRichard Henderson } else { 348094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 348194bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 348294bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 348394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 348494bf2658SRichard Henderson } 3485fcf5ef2aSThomas Huth tcg_temp_free(EA); 348694bf2658SRichard Henderson 348794bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 348894bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3489fcf5ef2aSThomas Huth } 3490fcf5ef2aSThomas Huth 3491fcf5ef2aSThomas Huth /* stqcx. */ 3492fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3493fcf5ef2aSThomas Huth { 34944a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 34954a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3496fcf5ef2aSThomas Huth 34974a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3498fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3499fcf5ef2aSThomas Huth return; 3500fcf5ef2aSThomas Huth } 35014a9b3c5dSRichard Henderson 3502fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 35034a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3504fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3505fcf5ef2aSThomas Huth 35064a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 35074a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 35084a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3509fcf5ef2aSThomas Huth 35104a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3511f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 35124a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 35134a9b3c5dSRichard Henderson if (ctx->le_mode) { 3514f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3515f34ec0f6SRichard Henderson EA, lo, hi, oi); 3516fcf5ef2aSThomas Huth } else { 3517f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3518f34ec0f6SRichard Henderson EA, lo, hi, oi); 3519fcf5ef2aSThomas Huth } 3520f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 3521f34ec0f6SRichard Henderson } else { 35224a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 35234a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 35244a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3525f34ec0f6SRichard Henderson } 3526fcf5ef2aSThomas Huth tcg_temp_free(EA); 35274a9b3c5dSRichard Henderson } else { 35284a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 35294a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 35304a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 35314a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 3532fcf5ef2aSThomas Huth 35334a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 35344a9b3c5dSRichard Henderson tcg_temp_free(EA); 35354a9b3c5dSRichard Henderson 35364a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 35374a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35384a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 35394a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 35404a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35414a9b3c5dSRichard Henderson 35424a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35434a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 35444a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35454a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 35464a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 35474a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35484a9b3c5dSRichard Henderson 35494a9b3c5dSRichard Henderson /* Success */ 35504a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 35514a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35524a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 35534a9b3c5dSRichard Henderson 35544a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35554a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 35564a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 35574a9b3c5dSRichard Henderson 35584a9b3c5dSRichard Henderson gen_set_label(lab_fail); 35594a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35604a9b3c5dSRichard Henderson 35614a9b3c5dSRichard Henderson gen_set_label(lab_over); 35624a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 35634a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 35644a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 35654a9b3c5dSRichard Henderson } 35664a9b3c5dSRichard Henderson } 3567fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3568fcf5ef2aSThomas Huth 3569fcf5ef2aSThomas Huth /* sync */ 3570fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3571fcf5ef2aSThomas Huth { 3572fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3573fcf5ef2aSThomas Huth 3574fcf5ef2aSThomas Huth /* 3575fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3576fcf5ef2aSThomas Huth * 3577fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3578fcf5ef2aSThomas Huth * 3579fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3580fcf5ef2aSThomas Huth * check MSR_PR as well. 3581fcf5ef2aSThomas Huth */ 3582fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3583fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3584fcf5ef2aSThomas Huth } 35854771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3586fcf5ef2aSThomas Huth } 3587fcf5ef2aSThomas Huth 3588fcf5ef2aSThomas Huth /* wait */ 3589fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3590fcf5ef2aSThomas Huth { 3591fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3592fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3593fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3594fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3595fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3596b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3597fcf5ef2aSThomas Huth } 3598fcf5ef2aSThomas Huth 3599fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3600fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3601fcf5ef2aSThomas Huth { 3602fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3603fcf5ef2aSThomas Huth GEN_PRIV; 3604fcf5ef2aSThomas Huth #else 3605fcf5ef2aSThomas Huth TCGv_i32 t; 3606fcf5ef2aSThomas Huth 3607fcf5ef2aSThomas Huth CHK_HV; 3608fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3609fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3610fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3611fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3612fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3613fcf5ef2aSThomas Huth } 3614fcf5ef2aSThomas Huth 3615fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3616fcf5ef2aSThomas Huth { 3617fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3618fcf5ef2aSThomas Huth GEN_PRIV; 3619fcf5ef2aSThomas Huth #else 3620fcf5ef2aSThomas Huth TCGv_i32 t; 3621fcf5ef2aSThomas Huth 3622fcf5ef2aSThomas Huth CHK_HV; 3623fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3624fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3625fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3626fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3627fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3628fcf5ef2aSThomas Huth } 3629fcf5ef2aSThomas Huth 3630cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3631cdee0e72SNikunj A Dadhania { 3632cdee0e72SNikunj A Dadhania gen_nap(ctx); 3633cdee0e72SNikunj A Dadhania } 3634cdee0e72SNikunj A Dadhania 3635fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3636fcf5ef2aSThomas Huth { 3637fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3638fcf5ef2aSThomas Huth GEN_PRIV; 3639fcf5ef2aSThomas Huth #else 3640fcf5ef2aSThomas Huth TCGv_i32 t; 3641fcf5ef2aSThomas Huth 3642fcf5ef2aSThomas Huth CHK_HV; 3643fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3644fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3645fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3646fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3647fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3648fcf5ef2aSThomas Huth } 3649fcf5ef2aSThomas Huth 3650fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3651fcf5ef2aSThomas Huth { 3652fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3653fcf5ef2aSThomas Huth GEN_PRIV; 3654fcf5ef2aSThomas Huth #else 3655fcf5ef2aSThomas Huth TCGv_i32 t; 3656fcf5ef2aSThomas Huth 3657fcf5ef2aSThomas Huth CHK_HV; 3658fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3659fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3660fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3661fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3662fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3663fcf5ef2aSThomas Huth } 3664fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3665fcf5ef2aSThomas Huth 3666fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3667fcf5ef2aSThomas Huth { 3668fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3669fcf5ef2aSThomas Huth if (ctx->has_cfar) 3670fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3671fcf5ef2aSThomas Huth #endif 3672fcf5ef2aSThomas Huth } 3673fcf5ef2aSThomas Huth 3674fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3675fcf5ef2aSThomas Huth { 3676fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3677fcf5ef2aSThomas Huth return false; 3678fcf5ef2aSThomas Huth } 3679fcf5ef2aSThomas Huth 3680fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3681b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3682fcf5ef2aSThomas Huth #else 3683fcf5ef2aSThomas Huth return true; 3684fcf5ef2aSThomas Huth #endif 3685fcf5ef2aSThomas Huth } 3686fcf5ef2aSThomas Huth 36870e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 36880e3bf489SRoman Kapl { 36890e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 36900e3bf489SRoman Kapl if (unlikely(sse)) { 36910e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 36920e3bf489SRoman Kapl gen_debug_exception(ctx); 36930e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 36940e3bf489SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_BRANCH); 36950e3bf489SRoman Kapl if (excp != POWERPC_EXCP_NONE) { 36960e3bf489SRoman Kapl gen_exception(ctx, excp); 36970e3bf489SRoman Kapl } 36980e3bf489SRoman Kapl } 36990e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 37000e3bf489SRoman Kapl } else { 37010e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 37020e3bf489SRoman Kapl } 37030e3bf489SRoman Kapl } 37040e3bf489SRoman Kapl 3705fcf5ef2aSThomas Huth /*** Branch ***/ 3706c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3707fcf5ef2aSThomas Huth { 3708fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3709fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3710fcf5ef2aSThomas Huth } 3711fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3712fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3713fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 371407ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 3715fcf5ef2aSThomas Huth } else { 3716fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 37170e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3718fcf5ef2aSThomas Huth } 3719fcf5ef2aSThomas Huth } 3720fcf5ef2aSThomas Huth 3721fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3722fcf5ef2aSThomas Huth { 3723fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3724fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3725fcf5ef2aSThomas Huth } 3726fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3727fcf5ef2aSThomas Huth } 3728fcf5ef2aSThomas Huth 3729fcf5ef2aSThomas Huth /* b ba bl bla */ 3730fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3731fcf5ef2aSThomas Huth { 3732fcf5ef2aSThomas Huth target_ulong li, target; 3733fcf5ef2aSThomas Huth 3734fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3735fcf5ef2aSThomas Huth /* sign extend LI */ 3736fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3737fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3738fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3739b6bac4bcSEmilio G. Cota target = ctx->base.pc_next + li - 4; 3740fcf5ef2aSThomas Huth } else { 3741fcf5ef2aSThomas Huth target = li; 3742fcf5ef2aSThomas Huth } 3743fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3744b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3745fcf5ef2aSThomas Huth } 3746b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3747fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3748fcf5ef2aSThomas Huth } 3749fcf5ef2aSThomas Huth 3750fcf5ef2aSThomas Huth #define BCOND_IM 0 3751fcf5ef2aSThomas Huth #define BCOND_LR 1 3752fcf5ef2aSThomas Huth #define BCOND_CTR 2 3753fcf5ef2aSThomas Huth #define BCOND_TAR 3 3754fcf5ef2aSThomas Huth 3755c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 3756fcf5ef2aSThomas Huth { 3757fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3758fcf5ef2aSThomas Huth TCGLabel *l1; 3759fcf5ef2aSThomas Huth TCGv target; 3760fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 37610e3bf489SRoman Kapl 3762fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3763fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3764fcf5ef2aSThomas Huth if (type == BCOND_CTR) 3765fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3766fcf5ef2aSThomas Huth else if (type == BCOND_TAR) 3767fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3768fcf5ef2aSThomas Huth else 3769fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3770fcf5ef2aSThomas Huth } else { 3771f764718dSRichard Henderson target = NULL; 3772fcf5ef2aSThomas Huth } 3773fcf5ef2aSThomas Huth if (LK(ctx->opcode)) 3774b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3775fcf5ef2aSThomas Huth l1 = gen_new_label(); 3776fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3777fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3778fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3779fcf5ef2aSThomas Huth if (unlikely(type == BCOND_CTR)) { 3780fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3781fcf5ef2aSThomas Huth return; 3782fcf5ef2aSThomas Huth } 3783fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3784fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3785fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3786fcf5ef2aSThomas Huth } else { 3787fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3788fcf5ef2aSThomas Huth } 3789fcf5ef2aSThomas Huth if (bo & 0x2) { 3790fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3791fcf5ef2aSThomas Huth } else { 3792fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3793fcf5ef2aSThomas Huth } 3794fcf5ef2aSThomas Huth tcg_temp_free(temp); 3795fcf5ef2aSThomas Huth } 3796fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3797fcf5ef2aSThomas Huth /* Test CR */ 3798fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3799fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3800fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3801fcf5ef2aSThomas Huth 3802fcf5ef2aSThomas Huth if (bo & 0x8) { 3803fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3804fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3805fcf5ef2aSThomas Huth } else { 3806fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3807fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3808fcf5ef2aSThomas Huth } 3809fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3810fcf5ef2aSThomas Huth } 3811b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3812fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3813fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3814fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3815b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3816fcf5ef2aSThomas Huth } else { 3817fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3818fcf5ef2aSThomas Huth } 3819fcf5ef2aSThomas Huth } else { 3820fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3821fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3822fcf5ef2aSThomas Huth } else { 3823fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3824fcf5ef2aSThomas Huth } 38250e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3826c4a2e3a9SRichard Henderson tcg_temp_free(target); 3827c4a2e3a9SRichard Henderson } 3828fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 38290e3bf489SRoman Kapl /* fallthrough case */ 3830fcf5ef2aSThomas Huth gen_set_label(l1); 3831b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 3832fcf5ef2aSThomas Huth } 3833fcf5ef2aSThomas Huth } 3834fcf5ef2aSThomas Huth 3835fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3836fcf5ef2aSThomas Huth { 3837fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3838fcf5ef2aSThomas Huth } 3839fcf5ef2aSThomas Huth 3840fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3841fcf5ef2aSThomas Huth { 3842fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3843fcf5ef2aSThomas Huth } 3844fcf5ef2aSThomas Huth 3845fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3846fcf5ef2aSThomas Huth { 3847fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3848fcf5ef2aSThomas Huth } 3849fcf5ef2aSThomas Huth 3850fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3851fcf5ef2aSThomas Huth { 3852fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3853fcf5ef2aSThomas Huth } 3854fcf5ef2aSThomas Huth 3855fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3856fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3857fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3858fcf5ef2aSThomas Huth { \ 3859fcf5ef2aSThomas Huth uint8_t bitmask; \ 3860fcf5ef2aSThomas Huth int sh; \ 3861fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3862fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3863fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3864fcf5ef2aSThomas Huth if (sh > 0) \ 3865fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3866fcf5ef2aSThomas Huth else if (sh < 0) \ 3867fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3868fcf5ef2aSThomas Huth else \ 3869fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3870fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3871fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3872fcf5ef2aSThomas Huth if (sh > 0) \ 3873fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3874fcf5ef2aSThomas Huth else if (sh < 0) \ 3875fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3876fcf5ef2aSThomas Huth else \ 3877fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3878fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3879fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3880fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3881fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3882fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3883fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3884fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3885fcf5ef2aSThomas Huth } 3886fcf5ef2aSThomas Huth 3887fcf5ef2aSThomas Huth /* crand */ 3888fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3889fcf5ef2aSThomas Huth /* crandc */ 3890fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3891fcf5ef2aSThomas Huth /* creqv */ 3892fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3893fcf5ef2aSThomas Huth /* crnand */ 3894fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3895fcf5ef2aSThomas Huth /* crnor */ 3896fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3897fcf5ef2aSThomas Huth /* cror */ 3898fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3899fcf5ef2aSThomas Huth /* crorc */ 3900fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3901fcf5ef2aSThomas Huth /* crxor */ 3902fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3903fcf5ef2aSThomas Huth 3904fcf5ef2aSThomas Huth /* mcrf */ 3905fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3906fcf5ef2aSThomas Huth { 3907fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3908fcf5ef2aSThomas Huth } 3909fcf5ef2aSThomas Huth 3910fcf5ef2aSThomas Huth /*** System linkage ***/ 3911fcf5ef2aSThomas Huth 3912fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3913fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3914fcf5ef2aSThomas Huth { 3915fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3916fcf5ef2aSThomas Huth GEN_PRIV; 3917fcf5ef2aSThomas Huth #else 3918fcf5ef2aSThomas Huth /* This instruction doesn't exist anymore on 64-bit server 3919fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3920fcf5ef2aSThomas Huth */ 3921fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_SEGMENT_64B) { 3922fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3923fcf5ef2aSThomas Huth return; 3924fcf5ef2aSThomas Huth } 3925fcf5ef2aSThomas Huth /* Restore CPU state */ 3926fcf5ef2aSThomas Huth CHK_SV; 3927a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3928a59d628fSMaria Klimushenkova gen_io_start(); 3929a59d628fSMaria Klimushenkova } 3930b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3931fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3932fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3933a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3934a59d628fSMaria Klimushenkova gen_io_end(); 3935a59d628fSMaria Klimushenkova } 3936fcf5ef2aSThomas Huth #endif 3937fcf5ef2aSThomas Huth } 3938fcf5ef2aSThomas Huth 3939fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3940fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 3941fcf5ef2aSThomas Huth { 3942fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3943fcf5ef2aSThomas Huth GEN_PRIV; 3944fcf5ef2aSThomas Huth #else 3945fcf5ef2aSThomas Huth /* Restore CPU state */ 3946fcf5ef2aSThomas Huth CHK_SV; 3947a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3948a59d628fSMaria Klimushenkova gen_io_start(); 3949a59d628fSMaria Klimushenkova } 3950b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3951fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 3952fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3953a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3954a59d628fSMaria Klimushenkova gen_io_end(); 3955a59d628fSMaria Klimushenkova } 3956fcf5ef2aSThomas Huth #endif 3957fcf5ef2aSThomas Huth } 3958fcf5ef2aSThomas Huth 3959fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 3960fcf5ef2aSThomas Huth { 3961fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3962fcf5ef2aSThomas Huth GEN_PRIV; 3963fcf5ef2aSThomas Huth #else 3964fcf5ef2aSThomas Huth /* Restore CPU state */ 3965fcf5ef2aSThomas Huth CHK_HV; 3966fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 3967fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3968fcf5ef2aSThomas Huth #endif 3969fcf5ef2aSThomas Huth } 3970fcf5ef2aSThomas Huth #endif 3971fcf5ef2aSThomas Huth 3972fcf5ef2aSThomas Huth /* sc */ 3973fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3974fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3975fcf5ef2aSThomas Huth #else 3976fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3977fcf5ef2aSThomas Huth #endif 3978fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 3979fcf5ef2aSThomas Huth { 3980fcf5ef2aSThomas Huth uint32_t lev; 3981fcf5ef2aSThomas Huth 3982fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 3983fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3984fcf5ef2aSThomas Huth } 3985fcf5ef2aSThomas Huth 3986fcf5ef2aSThomas Huth /*** Trap ***/ 3987fcf5ef2aSThomas Huth 3988fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 3989fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 3990fcf5ef2aSThomas Huth { 3991fcf5ef2aSThomas Huth /* Trap never */ 3992fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 3993fcf5ef2aSThomas Huth return true; 3994fcf5ef2aSThomas Huth } 3995fcf5ef2aSThomas Huth /* Trap always */ 3996fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 3997fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3998fcf5ef2aSThomas Huth return true; 3999fcf5ef2aSThomas Huth } 4000fcf5ef2aSThomas Huth return false; 4001fcf5ef2aSThomas Huth } 4002fcf5ef2aSThomas Huth 4003fcf5ef2aSThomas Huth /* tw */ 4004fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4005fcf5ef2aSThomas Huth { 4006fcf5ef2aSThomas Huth TCGv_i32 t0; 4007fcf5ef2aSThomas Huth 4008fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4009fcf5ef2aSThomas Huth return; 4010fcf5ef2aSThomas Huth } 4011fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4012fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4013fcf5ef2aSThomas Huth t0); 4014fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4015fcf5ef2aSThomas Huth } 4016fcf5ef2aSThomas Huth 4017fcf5ef2aSThomas Huth /* twi */ 4018fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4019fcf5ef2aSThomas Huth { 4020fcf5ef2aSThomas Huth TCGv t0; 4021fcf5ef2aSThomas Huth TCGv_i32 t1; 4022fcf5ef2aSThomas Huth 4023fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4024fcf5ef2aSThomas Huth return; 4025fcf5ef2aSThomas Huth } 4026fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4027fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4028fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4029fcf5ef2aSThomas Huth tcg_temp_free(t0); 4030fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4031fcf5ef2aSThomas Huth } 4032fcf5ef2aSThomas Huth 4033fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4034fcf5ef2aSThomas Huth /* td */ 4035fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4036fcf5ef2aSThomas Huth { 4037fcf5ef2aSThomas Huth TCGv_i32 t0; 4038fcf5ef2aSThomas Huth 4039fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4040fcf5ef2aSThomas Huth return; 4041fcf5ef2aSThomas Huth } 4042fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4043fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4044fcf5ef2aSThomas Huth t0); 4045fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4046fcf5ef2aSThomas Huth } 4047fcf5ef2aSThomas Huth 4048fcf5ef2aSThomas Huth /* tdi */ 4049fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4050fcf5ef2aSThomas Huth { 4051fcf5ef2aSThomas Huth TCGv t0; 4052fcf5ef2aSThomas Huth TCGv_i32 t1; 4053fcf5ef2aSThomas Huth 4054fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4055fcf5ef2aSThomas Huth return; 4056fcf5ef2aSThomas Huth } 4057fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4058fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4059fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4060fcf5ef2aSThomas Huth tcg_temp_free(t0); 4061fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4062fcf5ef2aSThomas Huth } 4063fcf5ef2aSThomas Huth #endif 4064fcf5ef2aSThomas Huth 4065fcf5ef2aSThomas Huth /*** Processor control ***/ 4066fcf5ef2aSThomas Huth 4067dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 4068fcf5ef2aSThomas Huth { 4069fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4070fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4071fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4072fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 4073fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4074fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4075fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4076fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 4077fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 4078fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 4079dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 4080dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4081dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4082dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4083dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4084dd09c361SNikunj A Dadhania } 4085fcf5ef2aSThomas Huth tcg_temp_free(t0); 4086fcf5ef2aSThomas Huth tcg_temp_free(t1); 4087fcf5ef2aSThomas Huth tcg_temp_free(t2); 4088fcf5ef2aSThomas Huth } 4089fcf5ef2aSThomas Huth 4090fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 4091fcf5ef2aSThomas Huth { 4092dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 4093fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 4094dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 4095dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 4096dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 4097dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4098dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 40991bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 41001bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 41011bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4102fcf5ef2aSThomas Huth } 4103fcf5ef2aSThomas Huth 4104fcf5ef2aSThomas Huth /* mcrxr */ 4105fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4106fcf5ef2aSThomas Huth { 4107fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4108fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4109fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4110fcf5ef2aSThomas Huth 4111fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4112fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4113fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4114fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4115fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4116fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4117fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4118fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4119fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4120fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4121fcf5ef2aSThomas Huth 4122fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4123fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4124fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4125fcf5ef2aSThomas Huth } 4126fcf5ef2aSThomas Huth 4127b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4128b63d0434SNikunj A Dadhania /* mcrxrx */ 4129b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4130b63d0434SNikunj A Dadhania { 4131b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4132b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4133b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4134b63d0434SNikunj A Dadhania 4135b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4136b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4137b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4138b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4139b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4140b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4141b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4142b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4143b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4144b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4145b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4146b63d0434SNikunj A Dadhania } 4147b63d0434SNikunj A Dadhania #endif 4148b63d0434SNikunj A Dadhania 4149fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4150fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4151fcf5ef2aSThomas Huth { 4152fcf5ef2aSThomas Huth uint32_t crm, crn; 4153fcf5ef2aSThomas Huth 4154fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4155fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4156fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4157fcf5ef2aSThomas Huth crn = ctz32 (crm); 4158fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4159fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4160fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4161fcf5ef2aSThomas Huth } 4162fcf5ef2aSThomas Huth } else { 4163fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4164fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4165fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4166fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4167fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4168fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4169fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4170fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4171fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4172fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4173fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4174fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4175fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4176fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4177fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4178fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4179fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4180fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4181fcf5ef2aSThomas Huth } 4182fcf5ef2aSThomas Huth } 4183fcf5ef2aSThomas Huth 4184fcf5ef2aSThomas Huth /* mfmsr */ 4185fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4186fcf5ef2aSThomas Huth { 4187fcf5ef2aSThomas Huth CHK_SV; 4188fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4189fcf5ef2aSThomas Huth } 4190fcf5ef2aSThomas Huth 4191fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4192fcf5ef2aSThomas Huth { 4193fcf5ef2aSThomas Huth #if 0 4194fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4195fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 4196fcf5ef2aSThomas Huth #endif 4197fcf5ef2aSThomas Huth } 4198fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 4199fcf5ef2aSThomas Huth 4200fcf5ef2aSThomas Huth /* mfspr */ 4201fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4202fcf5ef2aSThomas Huth { 4203fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4204fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4205fcf5ef2aSThomas Huth 4206fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4207fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4208fcf5ef2aSThomas Huth #else 4209fcf5ef2aSThomas Huth if (ctx->pr) { 4210fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4211fcf5ef2aSThomas Huth } else if (ctx->hv) { 4212fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4213fcf5ef2aSThomas Huth } else { 4214fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4215fcf5ef2aSThomas Huth } 4216fcf5ef2aSThomas Huth #endif 4217fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4218fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4219fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4220fcf5ef2aSThomas Huth } else { 4221fcf5ef2aSThomas Huth /* Privilege exception */ 4222fcf5ef2aSThomas Huth /* This is a hack to avoid warnings when running Linux: 4223fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4224fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4225fcf5ef2aSThomas Huth */ 4226fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 422731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 422831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4229b6bac4bcSEmilio G. Cota ctx->base.pc_next - 4); 4230fcf5ef2aSThomas Huth } 4231fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4232fcf5ef2aSThomas Huth } 4233fcf5ef2aSThomas Huth } else { 4234fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4235fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4236fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4237fcf5ef2aSThomas Huth /* This is a nop */ 4238fcf5ef2aSThomas Huth return; 4239fcf5ef2aSThomas Huth } 4240fcf5ef2aSThomas Huth /* Not defined */ 424131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 424231085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 4243b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4244fcf5ef2aSThomas Huth 4245fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4246fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4247fcf5ef2aSThomas Huth */ 4248fcf5ef2aSThomas Huth if (sprn & 0x10) { 4249fcf5ef2aSThomas Huth if (ctx->pr) { 4250fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4251fcf5ef2aSThomas Huth } 4252fcf5ef2aSThomas Huth } else { 4253fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4254fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4255fcf5ef2aSThomas Huth } 4256fcf5ef2aSThomas Huth } 4257fcf5ef2aSThomas Huth } 4258fcf5ef2aSThomas Huth } 4259fcf5ef2aSThomas Huth 4260fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4261fcf5ef2aSThomas Huth { 4262fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4263fcf5ef2aSThomas Huth } 4264fcf5ef2aSThomas Huth 4265fcf5ef2aSThomas Huth /* mftb */ 4266fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4267fcf5ef2aSThomas Huth { 4268fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4269fcf5ef2aSThomas Huth } 4270fcf5ef2aSThomas Huth 4271fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4272fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4273fcf5ef2aSThomas Huth { 4274fcf5ef2aSThomas Huth uint32_t crm, crn; 4275fcf5ef2aSThomas Huth 4276fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4277fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4278fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4279fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4280fcf5ef2aSThomas Huth crn = ctz32 (crm); 4281fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4282fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4283fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4284fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4285fcf5ef2aSThomas Huth } 4286fcf5ef2aSThomas Huth } else { 4287fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4288fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4289fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4290fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4291fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4292fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4293fcf5ef2aSThomas Huth } 4294fcf5ef2aSThomas Huth } 4295fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4296fcf5ef2aSThomas Huth } 4297fcf5ef2aSThomas Huth } 4298fcf5ef2aSThomas Huth 4299fcf5ef2aSThomas Huth /* mtmsr */ 4300fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4301fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4302fcf5ef2aSThomas Huth { 4303fcf5ef2aSThomas Huth CHK_SV; 4304fcf5ef2aSThomas Huth 4305fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4306fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4307fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4308fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4309fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4310fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4311fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4312fcf5ef2aSThomas Huth tcg_temp_free(t0); 4313fcf5ef2aSThomas Huth } else { 4314fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4315fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4316fcf5ef2aSThomas Huth * directly from ppc_store_msr 4317fcf5ef2aSThomas Huth */ 4318b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4319b8edea50SPavel Dovgalyuk gen_io_start(); 4320b8edea50SPavel Dovgalyuk } 4321b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4322fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4323fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4324fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4325fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4326b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4327b8edea50SPavel Dovgalyuk gen_io_end(); 4328b8edea50SPavel Dovgalyuk } 4329fcf5ef2aSThomas Huth } 4330fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4331fcf5ef2aSThomas Huth } 4332fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4333fcf5ef2aSThomas Huth 4334fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4335fcf5ef2aSThomas Huth { 4336fcf5ef2aSThomas Huth CHK_SV; 4337fcf5ef2aSThomas Huth 4338fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4339fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4340fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4341fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4342fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4343fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4344fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4345fcf5ef2aSThomas Huth tcg_temp_free(t0); 4346fcf5ef2aSThomas Huth } else { 4347fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4348fcf5ef2aSThomas Huth 4349fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4350fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4351fcf5ef2aSThomas Huth * directly from ppc_store_msr 4352fcf5ef2aSThomas Huth */ 4353b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4354b8edea50SPavel Dovgalyuk gen_io_start(); 4355b8edea50SPavel Dovgalyuk } 4356b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4357fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4358fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4359fcf5ef2aSThomas Huth #else 4360fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4361fcf5ef2aSThomas Huth #endif 4362fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4363b8edea50SPavel Dovgalyuk if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4364b8edea50SPavel Dovgalyuk gen_io_end(); 4365b8edea50SPavel Dovgalyuk } 4366fcf5ef2aSThomas Huth tcg_temp_free(msr); 4367fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4368fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4369fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4370fcf5ef2aSThomas Huth } 4371fcf5ef2aSThomas Huth #endif 4372fcf5ef2aSThomas Huth } 4373fcf5ef2aSThomas Huth 4374fcf5ef2aSThomas Huth /* mtspr */ 4375fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4376fcf5ef2aSThomas Huth { 4377fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4378fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4379fcf5ef2aSThomas Huth 4380fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4381fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4382fcf5ef2aSThomas Huth #else 4383fcf5ef2aSThomas Huth if (ctx->pr) { 4384fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4385fcf5ef2aSThomas Huth } else if (ctx->hv) { 4386fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4387fcf5ef2aSThomas Huth } else { 4388fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4389fcf5ef2aSThomas Huth } 4390fcf5ef2aSThomas Huth #endif 4391fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4392fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4393fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4394fcf5ef2aSThomas Huth } else { 4395fcf5ef2aSThomas Huth /* Privilege exception */ 439631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 439731085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 439831085338SThomas Huth ctx->base.pc_next - 4); 4399fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4400fcf5ef2aSThomas Huth } 4401fcf5ef2aSThomas Huth } else { 4402fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4403fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4404fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4405fcf5ef2aSThomas Huth /* This is a nop */ 4406fcf5ef2aSThomas Huth return; 4407fcf5ef2aSThomas Huth } 4408fcf5ef2aSThomas Huth 4409fcf5ef2aSThomas Huth /* Not defined */ 441031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 441131085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 4412b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4413fcf5ef2aSThomas Huth 4414fcf5ef2aSThomas Huth 4415fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4416fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4417fcf5ef2aSThomas Huth */ 4418fcf5ef2aSThomas Huth if (sprn & 0x10) { 4419fcf5ef2aSThomas Huth if (ctx->pr) { 4420fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4421fcf5ef2aSThomas Huth } 4422fcf5ef2aSThomas Huth } else { 4423fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4424fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4425fcf5ef2aSThomas Huth } 4426fcf5ef2aSThomas Huth } 4427fcf5ef2aSThomas Huth } 4428fcf5ef2aSThomas Huth } 4429fcf5ef2aSThomas Huth 4430fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4431fcf5ef2aSThomas Huth /* setb */ 4432fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4433fcf5ef2aSThomas Huth { 4434fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4435fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4436fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4437fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4438fcf5ef2aSThomas Huth 4439fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4440fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4441fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4442fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4443fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4444fcf5ef2aSThomas Huth 4445fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4446fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4447fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4448fcf5ef2aSThomas Huth } 4449fcf5ef2aSThomas Huth #endif 4450fcf5ef2aSThomas Huth 4451fcf5ef2aSThomas Huth /*** Cache management ***/ 4452fcf5ef2aSThomas Huth 4453fcf5ef2aSThomas Huth /* dcbf */ 4454fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4455fcf5ef2aSThomas Huth { 4456fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4457fcf5ef2aSThomas Huth TCGv t0; 4458fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4459fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4460fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4461fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4462fcf5ef2aSThomas Huth tcg_temp_free(t0); 4463fcf5ef2aSThomas Huth } 4464fcf5ef2aSThomas Huth 446550728199SRoman Kapl /* dcbfep (external PID dcbf) */ 446650728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 446750728199SRoman Kapl { 446850728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 446950728199SRoman Kapl TCGv t0; 447050728199SRoman Kapl CHK_SV; 447150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 447250728199SRoman Kapl t0 = tcg_temp_new(); 447350728199SRoman Kapl gen_addr_reg_index(ctx, t0); 447450728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 447550728199SRoman Kapl tcg_temp_free(t0); 447650728199SRoman Kapl } 447750728199SRoman Kapl 4478fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4479fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4480fcf5ef2aSThomas Huth { 4481fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4482fcf5ef2aSThomas Huth GEN_PRIV; 4483fcf5ef2aSThomas Huth #else 4484fcf5ef2aSThomas Huth TCGv EA, val; 4485fcf5ef2aSThomas Huth 4486fcf5ef2aSThomas Huth CHK_SV; 4487fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4488fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4489fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4490fcf5ef2aSThomas Huth val = tcg_temp_new(); 4491fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4492fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4493fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4494fcf5ef2aSThomas Huth tcg_temp_free(val); 4495fcf5ef2aSThomas Huth tcg_temp_free(EA); 4496fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4497fcf5ef2aSThomas Huth } 4498fcf5ef2aSThomas Huth 4499fcf5ef2aSThomas Huth /* dcdst */ 4500fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4501fcf5ef2aSThomas Huth { 4502fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4503fcf5ef2aSThomas Huth TCGv t0; 4504fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4505fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4506fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4507fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4508fcf5ef2aSThomas Huth tcg_temp_free(t0); 4509fcf5ef2aSThomas Huth } 4510fcf5ef2aSThomas Huth 451150728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 451250728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 451350728199SRoman Kapl { 451450728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 451550728199SRoman Kapl TCGv t0; 451650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 451750728199SRoman Kapl t0 = tcg_temp_new(); 451850728199SRoman Kapl gen_addr_reg_index(ctx, t0); 451950728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 452050728199SRoman Kapl tcg_temp_free(t0); 452150728199SRoman Kapl } 452250728199SRoman Kapl 4523fcf5ef2aSThomas Huth /* dcbt */ 4524fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4525fcf5ef2aSThomas Huth { 4526fcf5ef2aSThomas Huth /* interpreted as no-op */ 4527fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4528fcf5ef2aSThomas Huth * but does not generate any exception 4529fcf5ef2aSThomas Huth */ 4530fcf5ef2aSThomas Huth } 4531fcf5ef2aSThomas Huth 453250728199SRoman Kapl /* dcbtep */ 453350728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 453450728199SRoman Kapl { 453550728199SRoman Kapl /* interpreted as no-op */ 453650728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU 453750728199SRoman Kapl * but does not generate any exception 453850728199SRoman Kapl */ 453950728199SRoman Kapl } 454050728199SRoman Kapl 4541fcf5ef2aSThomas Huth /* dcbtst */ 4542fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4543fcf5ef2aSThomas Huth { 4544fcf5ef2aSThomas Huth /* interpreted as no-op */ 4545fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4546fcf5ef2aSThomas Huth * but does not generate any exception 4547fcf5ef2aSThomas Huth */ 4548fcf5ef2aSThomas Huth } 4549fcf5ef2aSThomas Huth 455050728199SRoman Kapl /* dcbtstep */ 455150728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 455250728199SRoman Kapl { 455350728199SRoman Kapl /* interpreted as no-op */ 455450728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU 455550728199SRoman Kapl * but does not generate any exception 455650728199SRoman Kapl */ 455750728199SRoman Kapl } 455850728199SRoman Kapl 4559fcf5ef2aSThomas Huth /* dcbtls */ 4560fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4561fcf5ef2aSThomas Huth { 4562fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4563fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4564fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4565fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4566fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4567fcf5ef2aSThomas Huth tcg_temp_free(t0); 4568fcf5ef2aSThomas Huth } 4569fcf5ef2aSThomas Huth 4570fcf5ef2aSThomas Huth /* dcbz */ 4571fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4572fcf5ef2aSThomas Huth { 4573fcf5ef2aSThomas Huth TCGv tcgv_addr; 4574fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4575fcf5ef2aSThomas Huth 4576fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4577fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4578fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4579fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4580fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4581fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4582fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4583fcf5ef2aSThomas Huth } 4584fcf5ef2aSThomas Huth 458550728199SRoman Kapl /* dcbzep */ 458650728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 458750728199SRoman Kapl { 458850728199SRoman Kapl TCGv tcgv_addr; 458950728199SRoman Kapl TCGv_i32 tcgv_op; 459050728199SRoman Kapl 459150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 459250728199SRoman Kapl tcgv_addr = tcg_temp_new(); 459350728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 459450728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 459550728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 459650728199SRoman Kapl tcg_temp_free(tcgv_addr); 459750728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 459850728199SRoman Kapl } 459950728199SRoman Kapl 4600fcf5ef2aSThomas Huth /* dst / dstt */ 4601fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4602fcf5ef2aSThomas Huth { 4603fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4604fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4605fcf5ef2aSThomas Huth } else { 4606fcf5ef2aSThomas Huth /* interpreted as no-op */ 4607fcf5ef2aSThomas Huth } 4608fcf5ef2aSThomas Huth } 4609fcf5ef2aSThomas Huth 4610fcf5ef2aSThomas Huth /* dstst /dststt */ 4611fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4612fcf5ef2aSThomas Huth { 4613fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4614fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4615fcf5ef2aSThomas Huth } else { 4616fcf5ef2aSThomas Huth /* interpreted as no-op */ 4617fcf5ef2aSThomas Huth } 4618fcf5ef2aSThomas Huth 4619fcf5ef2aSThomas Huth } 4620fcf5ef2aSThomas Huth 4621fcf5ef2aSThomas Huth /* dss / dssall */ 4622fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4623fcf5ef2aSThomas Huth { 4624fcf5ef2aSThomas Huth /* interpreted as no-op */ 4625fcf5ef2aSThomas Huth } 4626fcf5ef2aSThomas Huth 4627fcf5ef2aSThomas Huth /* icbi */ 4628fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4629fcf5ef2aSThomas Huth { 4630fcf5ef2aSThomas Huth TCGv t0; 4631fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4632fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4633fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4634fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4635fcf5ef2aSThomas Huth tcg_temp_free(t0); 4636fcf5ef2aSThomas Huth } 4637fcf5ef2aSThomas Huth 463850728199SRoman Kapl /* icbiep */ 463950728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 464050728199SRoman Kapl { 464150728199SRoman Kapl TCGv t0; 464250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 464350728199SRoman Kapl t0 = tcg_temp_new(); 464450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 464550728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 464650728199SRoman Kapl tcg_temp_free(t0); 464750728199SRoman Kapl } 464850728199SRoman Kapl 4649fcf5ef2aSThomas Huth /* Optional: */ 4650fcf5ef2aSThomas Huth /* dcba */ 4651fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4652fcf5ef2aSThomas Huth { 4653fcf5ef2aSThomas Huth /* interpreted as no-op */ 4654fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a store by the MMU 4655fcf5ef2aSThomas Huth * but does not generate any exception 4656fcf5ef2aSThomas Huth */ 4657fcf5ef2aSThomas Huth } 4658fcf5ef2aSThomas Huth 4659fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4660fcf5ef2aSThomas Huth /* Supervisor only: */ 4661fcf5ef2aSThomas Huth 4662fcf5ef2aSThomas Huth /* mfsr */ 4663fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4664fcf5ef2aSThomas Huth { 4665fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4666fcf5ef2aSThomas Huth GEN_PRIV; 4667fcf5ef2aSThomas Huth #else 4668fcf5ef2aSThomas Huth TCGv t0; 4669fcf5ef2aSThomas Huth 4670fcf5ef2aSThomas Huth CHK_SV; 4671fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4672fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4673fcf5ef2aSThomas Huth tcg_temp_free(t0); 4674fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4675fcf5ef2aSThomas Huth } 4676fcf5ef2aSThomas Huth 4677fcf5ef2aSThomas Huth /* mfsrin */ 4678fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4679fcf5ef2aSThomas Huth { 4680fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4681fcf5ef2aSThomas Huth GEN_PRIV; 4682fcf5ef2aSThomas Huth #else 4683fcf5ef2aSThomas Huth TCGv t0; 4684fcf5ef2aSThomas Huth 4685fcf5ef2aSThomas Huth CHK_SV; 4686fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4687e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4688fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4689fcf5ef2aSThomas Huth tcg_temp_free(t0); 4690fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4691fcf5ef2aSThomas Huth } 4692fcf5ef2aSThomas Huth 4693fcf5ef2aSThomas Huth /* mtsr */ 4694fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4695fcf5ef2aSThomas Huth { 4696fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4697fcf5ef2aSThomas Huth GEN_PRIV; 4698fcf5ef2aSThomas Huth #else 4699fcf5ef2aSThomas Huth TCGv t0; 4700fcf5ef2aSThomas Huth 4701fcf5ef2aSThomas Huth CHK_SV; 4702fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4703fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4704fcf5ef2aSThomas Huth tcg_temp_free(t0); 4705fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4706fcf5ef2aSThomas Huth } 4707fcf5ef2aSThomas Huth 4708fcf5ef2aSThomas Huth /* mtsrin */ 4709fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4710fcf5ef2aSThomas Huth { 4711fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4712fcf5ef2aSThomas Huth GEN_PRIV; 4713fcf5ef2aSThomas Huth #else 4714fcf5ef2aSThomas Huth TCGv t0; 4715fcf5ef2aSThomas Huth CHK_SV; 4716fcf5ef2aSThomas Huth 4717fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4718e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4719fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4720fcf5ef2aSThomas Huth tcg_temp_free(t0); 4721fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4722fcf5ef2aSThomas Huth } 4723fcf5ef2aSThomas Huth 4724fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4725fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4726fcf5ef2aSThomas Huth 4727fcf5ef2aSThomas Huth /* mfsr */ 4728fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4729fcf5ef2aSThomas Huth { 4730fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4731fcf5ef2aSThomas Huth GEN_PRIV; 4732fcf5ef2aSThomas Huth #else 4733fcf5ef2aSThomas Huth TCGv t0; 4734fcf5ef2aSThomas Huth 4735fcf5ef2aSThomas Huth CHK_SV; 4736fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4737fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4738fcf5ef2aSThomas Huth tcg_temp_free(t0); 4739fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4740fcf5ef2aSThomas Huth } 4741fcf5ef2aSThomas Huth 4742fcf5ef2aSThomas Huth /* mfsrin */ 4743fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4744fcf5ef2aSThomas Huth { 4745fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4746fcf5ef2aSThomas Huth GEN_PRIV; 4747fcf5ef2aSThomas Huth #else 4748fcf5ef2aSThomas Huth TCGv t0; 4749fcf5ef2aSThomas Huth 4750fcf5ef2aSThomas Huth CHK_SV; 4751fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4752e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4753fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4754fcf5ef2aSThomas Huth tcg_temp_free(t0); 4755fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4756fcf5ef2aSThomas Huth } 4757fcf5ef2aSThomas Huth 4758fcf5ef2aSThomas Huth /* mtsr */ 4759fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4760fcf5ef2aSThomas Huth { 4761fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4762fcf5ef2aSThomas Huth GEN_PRIV; 4763fcf5ef2aSThomas Huth #else 4764fcf5ef2aSThomas Huth TCGv t0; 4765fcf5ef2aSThomas Huth 4766fcf5ef2aSThomas Huth CHK_SV; 4767fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4768fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4769fcf5ef2aSThomas Huth tcg_temp_free(t0); 4770fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4771fcf5ef2aSThomas Huth } 4772fcf5ef2aSThomas Huth 4773fcf5ef2aSThomas Huth /* mtsrin */ 4774fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4775fcf5ef2aSThomas Huth { 4776fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4777fcf5ef2aSThomas Huth GEN_PRIV; 4778fcf5ef2aSThomas Huth #else 4779fcf5ef2aSThomas Huth TCGv t0; 4780fcf5ef2aSThomas Huth 4781fcf5ef2aSThomas Huth CHK_SV; 4782fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4783e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4784fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4785fcf5ef2aSThomas Huth tcg_temp_free(t0); 4786fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4787fcf5ef2aSThomas Huth } 4788fcf5ef2aSThomas Huth 4789fcf5ef2aSThomas Huth /* slbmte */ 4790fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4791fcf5ef2aSThomas Huth { 4792fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4793fcf5ef2aSThomas Huth GEN_PRIV; 4794fcf5ef2aSThomas Huth #else 4795fcf5ef2aSThomas Huth CHK_SV; 4796fcf5ef2aSThomas Huth 4797fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4798fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4799fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4800fcf5ef2aSThomas Huth } 4801fcf5ef2aSThomas Huth 4802fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4803fcf5ef2aSThomas Huth { 4804fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4805fcf5ef2aSThomas Huth GEN_PRIV; 4806fcf5ef2aSThomas Huth #else 4807fcf5ef2aSThomas Huth CHK_SV; 4808fcf5ef2aSThomas Huth 4809fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4810fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4811fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4812fcf5ef2aSThomas Huth } 4813fcf5ef2aSThomas Huth 4814fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4815fcf5ef2aSThomas Huth { 4816fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4817fcf5ef2aSThomas Huth GEN_PRIV; 4818fcf5ef2aSThomas Huth #else 4819fcf5ef2aSThomas Huth CHK_SV; 4820fcf5ef2aSThomas Huth 4821fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4822fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4823fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4824fcf5ef2aSThomas Huth } 4825fcf5ef2aSThomas Huth 4826fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4827fcf5ef2aSThomas Huth { 4828fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4829fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4830fcf5ef2aSThomas Huth #else 4831fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4832fcf5ef2aSThomas Huth 4833fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4834fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4835fcf5ef2aSThomas Huth return; 4836fcf5ef2aSThomas Huth } 4837fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4838fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4839fcf5ef2aSThomas Huth l1 = gen_new_label(); 4840fcf5ef2aSThomas Huth l2 = gen_new_label(); 4841fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4842fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4843efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4844fcf5ef2aSThomas Huth tcg_gen_br(l2); 4845fcf5ef2aSThomas Huth gen_set_label(l1); 4846fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4847fcf5ef2aSThomas Huth gen_set_label(l2); 4848fcf5ef2aSThomas Huth #endif 4849fcf5ef2aSThomas Huth } 4850fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4851fcf5ef2aSThomas Huth 4852fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4853fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4854fcf5ef2aSThomas Huth 4855fcf5ef2aSThomas Huth /* tlbia */ 4856fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4857fcf5ef2aSThomas Huth { 4858fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4859fcf5ef2aSThomas Huth GEN_PRIV; 4860fcf5ef2aSThomas Huth #else 4861fcf5ef2aSThomas Huth CHK_HV; 4862fcf5ef2aSThomas Huth 4863fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4864fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4865fcf5ef2aSThomas Huth } 4866fcf5ef2aSThomas Huth 4867fcf5ef2aSThomas Huth /* tlbiel */ 4868fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4869fcf5ef2aSThomas Huth { 4870fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4871fcf5ef2aSThomas Huth GEN_PRIV; 4872fcf5ef2aSThomas Huth #else 4873fcf5ef2aSThomas Huth CHK_SV; 4874fcf5ef2aSThomas Huth 4875fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4876fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4877fcf5ef2aSThomas Huth } 4878fcf5ef2aSThomas Huth 4879fcf5ef2aSThomas Huth /* tlbie */ 4880fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4881fcf5ef2aSThomas Huth { 4882fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4883fcf5ef2aSThomas Huth GEN_PRIV; 4884fcf5ef2aSThomas Huth #else 4885fcf5ef2aSThomas Huth TCGv_i32 t1; 4886c6fd28fdSSuraj Jitindar Singh 4887c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 488891c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4889c6fd28fdSSuraj Jitindar Singh } else { 4890c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 4891c6fd28fdSSuraj Jitindar Singh } 4892fcf5ef2aSThomas Huth 4893fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4894fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4895fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4896fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4897fcf5ef2aSThomas Huth tcg_temp_free(t0); 4898fcf5ef2aSThomas Huth } else { 4899fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4900fcf5ef2aSThomas Huth } 4901fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4902fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4903fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4904fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4905fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4906fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4907fcf5ef2aSThomas Huth } 4908fcf5ef2aSThomas Huth 4909fcf5ef2aSThomas Huth /* tlbsync */ 4910fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4911fcf5ef2aSThomas Huth { 4912fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4913fcf5ef2aSThomas Huth GEN_PRIV; 4914fcf5ef2aSThomas Huth #else 491591c60f12SCédric Le Goater 491691c60f12SCédric Le Goater if (ctx->gtse) { 491791c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 491891c60f12SCédric Le Goater } else { 491991c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 492091c60f12SCédric Le Goater } 4921fcf5ef2aSThomas Huth 4922fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4923fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4924fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4925fcf5ef2aSThomas Huth } 4926fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4927fcf5ef2aSThomas Huth } 4928fcf5ef2aSThomas Huth 4929fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4930fcf5ef2aSThomas Huth /* slbia */ 4931fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 4932fcf5ef2aSThomas Huth { 4933fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4934fcf5ef2aSThomas Huth GEN_PRIV; 4935fcf5ef2aSThomas Huth #else 4936fcf5ef2aSThomas Huth CHK_SV; 4937fcf5ef2aSThomas Huth 4938fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 4939fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4940fcf5ef2aSThomas Huth } 4941fcf5ef2aSThomas Huth 4942fcf5ef2aSThomas Huth /* slbie */ 4943fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 4944fcf5ef2aSThomas Huth { 4945fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4946fcf5ef2aSThomas Huth GEN_PRIV; 4947fcf5ef2aSThomas Huth #else 4948fcf5ef2aSThomas Huth CHK_SV; 4949fcf5ef2aSThomas Huth 4950fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4951fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4952fcf5ef2aSThomas Huth } 4953a63f1dfcSNikunj A Dadhania 4954a63f1dfcSNikunj A Dadhania /* slbieg */ 4955a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 4956a63f1dfcSNikunj A Dadhania { 4957a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 4958a63f1dfcSNikunj A Dadhania GEN_PRIV; 4959a63f1dfcSNikunj A Dadhania #else 4960a63f1dfcSNikunj A Dadhania CHK_SV; 4961a63f1dfcSNikunj A Dadhania 4962a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4963a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 4964a63f1dfcSNikunj A Dadhania } 4965a63f1dfcSNikunj A Dadhania 496662d897caSNikunj A Dadhania /* slbsync */ 496762d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 496862d897caSNikunj A Dadhania { 496962d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 497062d897caSNikunj A Dadhania GEN_PRIV; 497162d897caSNikunj A Dadhania #else 497262d897caSNikunj A Dadhania CHK_SV; 497362d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 497462d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 497562d897caSNikunj A Dadhania } 497662d897caSNikunj A Dadhania 4977fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4978fcf5ef2aSThomas Huth 4979fcf5ef2aSThomas Huth /*** External control ***/ 4980fcf5ef2aSThomas Huth /* Optional: */ 4981fcf5ef2aSThomas Huth 4982fcf5ef2aSThomas Huth /* eciwx */ 4983fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 4984fcf5ef2aSThomas Huth { 4985fcf5ef2aSThomas Huth TCGv t0; 4986fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4987fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4988fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4989fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4990c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4991c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 4992fcf5ef2aSThomas Huth tcg_temp_free(t0); 4993fcf5ef2aSThomas Huth } 4994fcf5ef2aSThomas Huth 4995fcf5ef2aSThomas Huth /* ecowx */ 4996fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 4997fcf5ef2aSThomas Huth { 4998fcf5ef2aSThomas Huth TCGv t0; 4999fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5000fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5001fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5002fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5003c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5004c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5005fcf5ef2aSThomas Huth tcg_temp_free(t0); 5006fcf5ef2aSThomas Huth } 5007fcf5ef2aSThomas Huth 5008fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5009fcf5ef2aSThomas Huth 5010fcf5ef2aSThomas Huth /* abs - abs. */ 5011fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5012fcf5ef2aSThomas Huth { 5013fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5014fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5015fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 5016fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5017fcf5ef2aSThomas Huth tcg_gen_br(l2); 5018fcf5ef2aSThomas Huth gen_set_label(l1); 5019fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5020fcf5ef2aSThomas Huth gen_set_label(l2); 5021fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5022fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5023fcf5ef2aSThomas Huth } 5024fcf5ef2aSThomas Huth 5025fcf5ef2aSThomas Huth /* abso - abso. */ 5026fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5027fcf5ef2aSThomas Huth { 5028fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5029fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5030fcf5ef2aSThomas Huth TCGLabel *l3 = gen_new_label(); 5031fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5032fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5033fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 5034fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 5035fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5036fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5037fcf5ef2aSThomas Huth tcg_gen_br(l2); 5038fcf5ef2aSThomas Huth gen_set_label(l1); 5039fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5040fcf5ef2aSThomas Huth tcg_gen_br(l3); 5041fcf5ef2aSThomas Huth gen_set_label(l2); 5042fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5043fcf5ef2aSThomas Huth gen_set_label(l3); 5044fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5045fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5046fcf5ef2aSThomas Huth } 5047fcf5ef2aSThomas Huth 5048fcf5ef2aSThomas Huth /* clcs */ 5049fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5050fcf5ef2aSThomas Huth { 5051fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5052fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5053fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5054fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5055fcf5ef2aSThomas Huth } 5056fcf5ef2aSThomas Huth 5057fcf5ef2aSThomas Huth /* div - div. */ 5058fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5059fcf5ef2aSThomas Huth { 5060fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5061fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5062fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5063fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5064fcf5ef2aSThomas Huth } 5065fcf5ef2aSThomas Huth 5066fcf5ef2aSThomas Huth /* divo - divo. */ 5067fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5068fcf5ef2aSThomas Huth { 5069fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5070fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5071fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5072fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5073fcf5ef2aSThomas Huth } 5074fcf5ef2aSThomas Huth 5075fcf5ef2aSThomas Huth /* divs - divs. */ 5076fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5077fcf5ef2aSThomas Huth { 5078fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5079fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5080fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5081fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5082fcf5ef2aSThomas Huth } 5083fcf5ef2aSThomas Huth 5084fcf5ef2aSThomas Huth /* divso - divso. */ 5085fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5086fcf5ef2aSThomas Huth { 5087fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5088fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5089fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5090fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5091fcf5ef2aSThomas Huth } 5092fcf5ef2aSThomas Huth 5093fcf5ef2aSThomas Huth /* doz - doz. */ 5094fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5095fcf5ef2aSThomas Huth { 5096fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5097fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5098fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 5099fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5100fcf5ef2aSThomas Huth tcg_gen_br(l2); 5101fcf5ef2aSThomas Huth gen_set_label(l1); 5102fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5103fcf5ef2aSThomas Huth gen_set_label(l2); 5104fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5105fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5106fcf5ef2aSThomas Huth } 5107fcf5ef2aSThomas Huth 5108fcf5ef2aSThomas Huth /* dozo - dozo. */ 5109fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5110fcf5ef2aSThomas Huth { 5111fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5112fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5113fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5114fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5115fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5116fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5117fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5118fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 5119fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5120fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5121fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5122fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5123fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5124fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5125fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5126fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5127fcf5ef2aSThomas Huth tcg_gen_br(l2); 5128fcf5ef2aSThomas Huth gen_set_label(l1); 5129fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5130fcf5ef2aSThomas Huth gen_set_label(l2); 5131fcf5ef2aSThomas Huth tcg_temp_free(t0); 5132fcf5ef2aSThomas Huth tcg_temp_free(t1); 5133fcf5ef2aSThomas Huth tcg_temp_free(t2); 5134fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5135fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5136fcf5ef2aSThomas Huth } 5137fcf5ef2aSThomas Huth 5138fcf5ef2aSThomas Huth /* dozi */ 5139fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5140fcf5ef2aSThomas Huth { 5141fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5142fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5143fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5144fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5145fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5146fcf5ef2aSThomas Huth tcg_gen_br(l2); 5147fcf5ef2aSThomas Huth gen_set_label(l1); 5148fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5149fcf5ef2aSThomas Huth gen_set_label(l2); 5150fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5151fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5152fcf5ef2aSThomas Huth } 5153fcf5ef2aSThomas Huth 5154fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5155fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5156fcf5ef2aSThomas Huth { 5157fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5158fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5159fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5160fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5161fcf5ef2aSThomas Huth 5162fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5163fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5164fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5165fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5166fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5167fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5168fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5169fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5170fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5171fcf5ef2aSThomas Huth tcg_temp_free(t0); 5172fcf5ef2aSThomas Huth } 5173fcf5ef2aSThomas Huth 5174fcf5ef2aSThomas Huth /* maskg - maskg. */ 5175fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5176fcf5ef2aSThomas Huth { 5177fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5178fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5179fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5180fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5181fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5182fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5183fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5184fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5185fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5186fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5187fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5188fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5189fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5190fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5191fcf5ef2aSThomas Huth gen_set_label(l1); 5192fcf5ef2aSThomas Huth tcg_temp_free(t0); 5193fcf5ef2aSThomas Huth tcg_temp_free(t1); 5194fcf5ef2aSThomas Huth tcg_temp_free(t2); 5195fcf5ef2aSThomas Huth tcg_temp_free(t3); 5196fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5197fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5198fcf5ef2aSThomas Huth } 5199fcf5ef2aSThomas Huth 5200fcf5ef2aSThomas Huth /* maskir - maskir. */ 5201fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5202fcf5ef2aSThomas Huth { 5203fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5204fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5205fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5206fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5207fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5208fcf5ef2aSThomas Huth tcg_temp_free(t0); 5209fcf5ef2aSThomas Huth tcg_temp_free(t1); 5210fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5211fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5212fcf5ef2aSThomas Huth } 5213fcf5ef2aSThomas Huth 5214fcf5ef2aSThomas Huth /* mul - mul. */ 5215fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5216fcf5ef2aSThomas Huth { 5217fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5218fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5219fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5220fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5221fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5222fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5223fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5224fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5225fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5226fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5227fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5228fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5229fcf5ef2aSThomas Huth tcg_temp_free(t2); 5230fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5231fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5232fcf5ef2aSThomas Huth } 5233fcf5ef2aSThomas Huth 5234fcf5ef2aSThomas Huth /* mulo - mulo. */ 5235fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5236fcf5ef2aSThomas Huth { 5237fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5238fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5239fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5240fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5241fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5242fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5243fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5244fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5245fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5246fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5247fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5248fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5249fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5250fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5251fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5252fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5253fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5254fcf5ef2aSThomas Huth gen_set_label(l1); 5255fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5256fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5257fcf5ef2aSThomas Huth tcg_temp_free(t2); 5258fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5259fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5260fcf5ef2aSThomas Huth } 5261fcf5ef2aSThomas Huth 5262fcf5ef2aSThomas Huth /* nabs - nabs. */ 5263fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5264fcf5ef2aSThomas Huth { 5265fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5266fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5267fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 5268fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5269fcf5ef2aSThomas Huth tcg_gen_br(l2); 5270fcf5ef2aSThomas Huth gen_set_label(l1); 5271fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5272fcf5ef2aSThomas Huth gen_set_label(l2); 5273fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5274fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5275fcf5ef2aSThomas Huth } 5276fcf5ef2aSThomas Huth 5277fcf5ef2aSThomas Huth /* nabso - nabso. */ 5278fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5279fcf5ef2aSThomas Huth { 5280fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5281fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5282fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 5283fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5284fcf5ef2aSThomas Huth tcg_gen_br(l2); 5285fcf5ef2aSThomas Huth gen_set_label(l1); 5286fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5287fcf5ef2aSThomas Huth gen_set_label(l2); 5288fcf5ef2aSThomas Huth /* nabs never overflows */ 5289fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5290fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5291fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5292fcf5ef2aSThomas Huth } 5293fcf5ef2aSThomas Huth 5294fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5295fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5296fcf5ef2aSThomas Huth { 5297fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5298fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5299fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5300fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5301fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5302fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5303fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 5304fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5305fcf5ef2aSThomas Huth tcg_temp_free(t0); 5306fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5307fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5308fcf5ef2aSThomas Huth } 5309fcf5ef2aSThomas Huth 5310fcf5ef2aSThomas Huth /* rrib - rrib. */ 5311fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5312fcf5ef2aSThomas Huth { 5313fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5314fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5315fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5316fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5317fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5318fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5319fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5320fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5321fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5322fcf5ef2aSThomas Huth tcg_temp_free(t0); 5323fcf5ef2aSThomas Huth tcg_temp_free(t1); 5324fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5325fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5326fcf5ef2aSThomas Huth } 5327fcf5ef2aSThomas Huth 5328fcf5ef2aSThomas Huth /* sle - sle. */ 5329fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5330fcf5ef2aSThomas Huth { 5331fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5332fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5333fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5334fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5335fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5336fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5337fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5338fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5339fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5340fcf5ef2aSThomas Huth tcg_temp_free(t0); 5341fcf5ef2aSThomas Huth tcg_temp_free(t1); 5342fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5343fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5344fcf5ef2aSThomas Huth } 5345fcf5ef2aSThomas Huth 5346fcf5ef2aSThomas Huth /* sleq - sleq. */ 5347fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5348fcf5ef2aSThomas Huth { 5349fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5350fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5351fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5352fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5353fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5354fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5355fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5356fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5357fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5358fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5359fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5360fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5361fcf5ef2aSThomas Huth tcg_temp_free(t0); 5362fcf5ef2aSThomas Huth tcg_temp_free(t1); 5363fcf5ef2aSThomas Huth tcg_temp_free(t2); 5364fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5365fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5366fcf5ef2aSThomas Huth } 5367fcf5ef2aSThomas Huth 5368fcf5ef2aSThomas Huth /* sliq - sliq. */ 5369fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5370fcf5ef2aSThomas Huth { 5371fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5372fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5373fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5374fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5375fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5376fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5377fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5378fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5379fcf5ef2aSThomas Huth tcg_temp_free(t0); 5380fcf5ef2aSThomas Huth tcg_temp_free(t1); 5381fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5382fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5383fcf5ef2aSThomas Huth } 5384fcf5ef2aSThomas Huth 5385fcf5ef2aSThomas Huth /* slliq - slliq. */ 5386fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5387fcf5ef2aSThomas Huth { 5388fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5389fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5390fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5391fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5392fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5393fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5394fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5395fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5396fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5397fcf5ef2aSThomas Huth tcg_temp_free(t0); 5398fcf5ef2aSThomas Huth tcg_temp_free(t1); 5399fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5400fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5401fcf5ef2aSThomas Huth } 5402fcf5ef2aSThomas Huth 5403fcf5ef2aSThomas Huth /* sllq - sllq. */ 5404fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5405fcf5ef2aSThomas Huth { 5406fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5407fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5408fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5409fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5410fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5411fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5412fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5413fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5414fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5415fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5416fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5417fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5418fcf5ef2aSThomas Huth tcg_gen_br(l2); 5419fcf5ef2aSThomas Huth gen_set_label(l1); 5420fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5421fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5422fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5423fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5424fcf5ef2aSThomas Huth gen_set_label(l2); 5425fcf5ef2aSThomas Huth tcg_temp_free(t0); 5426fcf5ef2aSThomas Huth tcg_temp_free(t1); 5427fcf5ef2aSThomas Huth tcg_temp_free(t2); 5428fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5429fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5430fcf5ef2aSThomas Huth } 5431fcf5ef2aSThomas Huth 5432fcf5ef2aSThomas Huth /* slq - slq. */ 5433fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5434fcf5ef2aSThomas Huth { 5435fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5436fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5437fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5438fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5439fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5440fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5441fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5442fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5443fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5444fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5445fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5446fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5447fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5448fcf5ef2aSThomas Huth gen_set_label(l1); 5449fcf5ef2aSThomas Huth tcg_temp_free(t0); 5450fcf5ef2aSThomas Huth tcg_temp_free(t1); 5451fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5452fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5453fcf5ef2aSThomas Huth } 5454fcf5ef2aSThomas Huth 5455fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5456fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5457fcf5ef2aSThomas Huth { 5458fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5459fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5460fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5461fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5462fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5463fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5464fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5465fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5466fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5467fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5468fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5469fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5470fcf5ef2aSThomas Huth gen_set_label(l1); 5471fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5472fcf5ef2aSThomas Huth tcg_temp_free(t0); 5473fcf5ef2aSThomas Huth tcg_temp_free(t1); 5474fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5475fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5476fcf5ef2aSThomas Huth } 5477fcf5ef2aSThomas Huth 5478fcf5ef2aSThomas Huth /* sraq - sraq. */ 5479fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5480fcf5ef2aSThomas Huth { 5481fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5482fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5483fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5484fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5485fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5486fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5487fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5488fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5489fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5490fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5491fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5492fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5493fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5494fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5495fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5496fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5497fcf5ef2aSThomas Huth gen_set_label(l1); 5498fcf5ef2aSThomas Huth tcg_temp_free(t0); 5499fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5500fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5501fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5502fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5503fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5504fcf5ef2aSThomas Huth gen_set_label(l2); 5505fcf5ef2aSThomas Huth tcg_temp_free(t1); 5506fcf5ef2aSThomas Huth tcg_temp_free(t2); 5507fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5508fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5509fcf5ef2aSThomas Huth } 5510fcf5ef2aSThomas Huth 5511fcf5ef2aSThomas Huth /* sre - sre. */ 5512fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5513fcf5ef2aSThomas Huth { 5514fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5515fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5516fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5517fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5518fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5519fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5520fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5521fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5522fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5523fcf5ef2aSThomas Huth tcg_temp_free(t0); 5524fcf5ef2aSThomas Huth tcg_temp_free(t1); 5525fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5526fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5527fcf5ef2aSThomas Huth } 5528fcf5ef2aSThomas Huth 5529fcf5ef2aSThomas Huth /* srea - srea. */ 5530fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5531fcf5ef2aSThomas Huth { 5532fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5533fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5534fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5535fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5536fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5537fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5538fcf5ef2aSThomas Huth tcg_temp_free(t0); 5539fcf5ef2aSThomas Huth tcg_temp_free(t1); 5540fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5541fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5542fcf5ef2aSThomas Huth } 5543fcf5ef2aSThomas Huth 5544fcf5ef2aSThomas Huth /* sreq */ 5545fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5546fcf5ef2aSThomas Huth { 5547fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5548fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5549fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5550fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5551fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5552fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5553fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5554fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5555fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5556fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5557fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5558fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5559fcf5ef2aSThomas Huth tcg_temp_free(t0); 5560fcf5ef2aSThomas Huth tcg_temp_free(t1); 5561fcf5ef2aSThomas Huth tcg_temp_free(t2); 5562fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5563fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5564fcf5ef2aSThomas Huth } 5565fcf5ef2aSThomas Huth 5566fcf5ef2aSThomas Huth /* sriq */ 5567fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5568fcf5ef2aSThomas Huth { 5569fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5570fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5571fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5572fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5573fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5574fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5575fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5576fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5577fcf5ef2aSThomas Huth tcg_temp_free(t0); 5578fcf5ef2aSThomas Huth tcg_temp_free(t1); 5579fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5580fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5581fcf5ef2aSThomas Huth } 5582fcf5ef2aSThomas Huth 5583fcf5ef2aSThomas Huth /* srliq */ 5584fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5585fcf5ef2aSThomas Huth { 5586fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5587fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5588fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5589fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5590fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5591fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5592fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5593fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5594fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5595fcf5ef2aSThomas Huth tcg_temp_free(t0); 5596fcf5ef2aSThomas Huth tcg_temp_free(t1); 5597fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5598fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5599fcf5ef2aSThomas Huth } 5600fcf5ef2aSThomas Huth 5601fcf5ef2aSThomas Huth /* srlq */ 5602fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5603fcf5ef2aSThomas Huth { 5604fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5605fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5606fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5607fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5608fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5609fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5610fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5611fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5612fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5613fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5614fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5615fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5616fcf5ef2aSThomas Huth tcg_gen_br(l2); 5617fcf5ef2aSThomas Huth gen_set_label(l1); 5618fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5619fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5620fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5621fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5622fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5623fcf5ef2aSThomas Huth gen_set_label(l2); 5624fcf5ef2aSThomas Huth tcg_temp_free(t0); 5625fcf5ef2aSThomas Huth tcg_temp_free(t1); 5626fcf5ef2aSThomas Huth tcg_temp_free(t2); 5627fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5628fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5629fcf5ef2aSThomas Huth } 5630fcf5ef2aSThomas Huth 5631fcf5ef2aSThomas Huth /* srq */ 5632fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5633fcf5ef2aSThomas Huth { 5634fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5635fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5636fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5637fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5638fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5639fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5640fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5641fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5642fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5643fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5644fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5645fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5646fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5647fcf5ef2aSThomas Huth gen_set_label(l1); 5648fcf5ef2aSThomas Huth tcg_temp_free(t0); 5649fcf5ef2aSThomas Huth tcg_temp_free(t1); 5650fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5651fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5652fcf5ef2aSThomas Huth } 5653fcf5ef2aSThomas Huth 5654fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5655fcf5ef2aSThomas Huth 5656fcf5ef2aSThomas Huth /* dsa */ 5657fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5658fcf5ef2aSThomas Huth { 5659fcf5ef2aSThomas Huth /* XXX: TODO */ 5660fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5661fcf5ef2aSThomas Huth } 5662fcf5ef2aSThomas Huth 5663fcf5ef2aSThomas Huth /* esa */ 5664fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5665fcf5ef2aSThomas Huth { 5666fcf5ef2aSThomas Huth /* XXX: TODO */ 5667fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5668fcf5ef2aSThomas Huth } 5669fcf5ef2aSThomas Huth 5670fcf5ef2aSThomas Huth /* mfrom */ 5671fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5672fcf5ef2aSThomas Huth { 5673fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5674fcf5ef2aSThomas Huth GEN_PRIV; 5675fcf5ef2aSThomas Huth #else 5676fcf5ef2aSThomas Huth CHK_SV; 5677fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5678fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5679fcf5ef2aSThomas Huth } 5680fcf5ef2aSThomas Huth 5681fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5682fcf5ef2aSThomas Huth 5683fcf5ef2aSThomas Huth /* tlbld */ 5684fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5685fcf5ef2aSThomas Huth { 5686fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5687fcf5ef2aSThomas Huth GEN_PRIV; 5688fcf5ef2aSThomas Huth #else 5689fcf5ef2aSThomas Huth CHK_SV; 5690fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5691fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5692fcf5ef2aSThomas Huth } 5693fcf5ef2aSThomas Huth 5694fcf5ef2aSThomas Huth /* tlbli */ 5695fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5696fcf5ef2aSThomas Huth { 5697fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5698fcf5ef2aSThomas Huth GEN_PRIV; 5699fcf5ef2aSThomas Huth #else 5700fcf5ef2aSThomas Huth CHK_SV; 5701fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5702fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5703fcf5ef2aSThomas Huth } 5704fcf5ef2aSThomas Huth 5705fcf5ef2aSThomas Huth /* 74xx TLB management */ 5706fcf5ef2aSThomas Huth 5707fcf5ef2aSThomas Huth /* tlbld */ 5708fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5709fcf5ef2aSThomas Huth { 5710fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5711fcf5ef2aSThomas Huth GEN_PRIV; 5712fcf5ef2aSThomas Huth #else 5713fcf5ef2aSThomas Huth CHK_SV; 5714fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5715fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5716fcf5ef2aSThomas Huth } 5717fcf5ef2aSThomas Huth 5718fcf5ef2aSThomas Huth /* tlbli */ 5719fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5720fcf5ef2aSThomas Huth { 5721fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5722fcf5ef2aSThomas Huth GEN_PRIV; 5723fcf5ef2aSThomas Huth #else 5724fcf5ef2aSThomas Huth CHK_SV; 5725fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5726fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5727fcf5ef2aSThomas Huth } 5728fcf5ef2aSThomas Huth 5729fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5730fcf5ef2aSThomas Huth 5731fcf5ef2aSThomas Huth /* clf */ 5732fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5733fcf5ef2aSThomas Huth { 5734fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5735fcf5ef2aSThomas Huth } 5736fcf5ef2aSThomas Huth 5737fcf5ef2aSThomas Huth /* cli */ 5738fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5739fcf5ef2aSThomas Huth { 5740fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5741fcf5ef2aSThomas Huth GEN_PRIV; 5742fcf5ef2aSThomas Huth #else 5743fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5744fcf5ef2aSThomas Huth CHK_SV; 5745fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5746fcf5ef2aSThomas Huth } 5747fcf5ef2aSThomas Huth 5748fcf5ef2aSThomas Huth /* dclst */ 5749fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5750fcf5ef2aSThomas Huth { 5751fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5752fcf5ef2aSThomas Huth } 5753fcf5ef2aSThomas Huth 5754fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5755fcf5ef2aSThomas Huth { 5756fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5757fcf5ef2aSThomas Huth GEN_PRIV; 5758fcf5ef2aSThomas Huth #else 5759fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5760fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5761fcf5ef2aSThomas Huth TCGv t0; 5762fcf5ef2aSThomas Huth 5763fcf5ef2aSThomas Huth CHK_SV; 5764fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5765fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5766e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 5767fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5768fcf5ef2aSThomas Huth tcg_temp_free(t0); 5769fcf5ef2aSThomas Huth if (ra != 0 && ra != rd) 5770fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5771fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5772fcf5ef2aSThomas Huth } 5773fcf5ef2aSThomas Huth 5774fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5775fcf5ef2aSThomas Huth { 5776fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5777fcf5ef2aSThomas Huth GEN_PRIV; 5778fcf5ef2aSThomas Huth #else 5779fcf5ef2aSThomas Huth TCGv t0; 5780fcf5ef2aSThomas Huth 5781fcf5ef2aSThomas Huth CHK_SV; 5782fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5783fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5784fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5785fcf5ef2aSThomas Huth tcg_temp_free(t0); 5786fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5787fcf5ef2aSThomas Huth } 5788fcf5ef2aSThomas Huth 5789fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5790fcf5ef2aSThomas Huth { 5791fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5792fcf5ef2aSThomas Huth GEN_PRIV; 5793fcf5ef2aSThomas Huth #else 5794fcf5ef2aSThomas Huth CHK_SV; 5795fcf5ef2aSThomas Huth 5796fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5797fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5798fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5799fcf5ef2aSThomas Huth } 5800fcf5ef2aSThomas Huth 5801fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5802fcf5ef2aSThomas Huth 5803fcf5ef2aSThomas Huth /* BookE specific instructions */ 5804fcf5ef2aSThomas Huth 5805fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5806fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5807fcf5ef2aSThomas Huth { 5808fcf5ef2aSThomas Huth /* XXX: TODO */ 5809fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5810fcf5ef2aSThomas Huth } 5811fcf5ef2aSThomas Huth 5812fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5813fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5814fcf5ef2aSThomas Huth { 5815fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5816fcf5ef2aSThomas Huth GEN_PRIV; 5817fcf5ef2aSThomas Huth #else 5818fcf5ef2aSThomas Huth TCGv t0; 5819fcf5ef2aSThomas Huth 5820fcf5ef2aSThomas Huth CHK_SV; 5821fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5822fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5823fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5824fcf5ef2aSThomas Huth tcg_temp_free(t0); 5825fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5826fcf5ef2aSThomas Huth } 5827fcf5ef2aSThomas Huth 5828fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5829fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5830fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5831fcf5ef2aSThomas Huth { 5832fcf5ef2aSThomas Huth TCGv t0, t1; 5833fcf5ef2aSThomas Huth 5834fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5835fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5836fcf5ef2aSThomas Huth 5837fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5838fcf5ef2aSThomas Huth case 0x05: 5839fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5840fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5841fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5842fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5843fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5844fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5845fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5846fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5847fcf5ef2aSThomas Huth break; 5848fcf5ef2aSThomas Huth case 0x04: 5849fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5850fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5851fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5852fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5853fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5854fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5855fcf5ef2aSThomas Huth break; 5856fcf5ef2aSThomas Huth case 0x01: 5857fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5858fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5859fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5860fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5861fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5862fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5863fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5864fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5865fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5866fcf5ef2aSThomas Huth break; 5867fcf5ef2aSThomas Huth case 0x00: 5868fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5869fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5870fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5871fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5872fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5873fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5874fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5875fcf5ef2aSThomas Huth break; 5876fcf5ef2aSThomas Huth case 0x0D: 5877fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5878fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5879fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5880fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5881fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5882fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5883fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5884fcf5ef2aSThomas Huth break; 5885fcf5ef2aSThomas Huth case 0x0C: 5886fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5887fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5888fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5889fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5890fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5891fcf5ef2aSThomas Huth break; 5892fcf5ef2aSThomas Huth } 5893fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5894fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5895fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5896fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5897fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5898fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5899fcf5ef2aSThomas Huth } else { 5900fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5901fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5902fcf5ef2aSThomas Huth } 5903fcf5ef2aSThomas Huth 5904fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5905fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5906fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5907fcf5ef2aSThomas Huth 5908fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5909fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5910fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5911fcf5ef2aSThomas Huth } 5912fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5913fcf5ef2aSThomas Huth /* Signed */ 5914fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5915fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5916fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5917fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5918fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5919fcf5ef2aSThomas Huth /* Saturate */ 5920fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5921fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5922fcf5ef2aSThomas Huth } 5923fcf5ef2aSThomas Huth } else { 5924fcf5ef2aSThomas Huth /* Unsigned */ 5925fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5926fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5927fcf5ef2aSThomas Huth /* Saturate */ 5928fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5929fcf5ef2aSThomas Huth } 5930fcf5ef2aSThomas Huth } 5931fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5932fcf5ef2aSThomas Huth /* Check overflow */ 5933fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5934fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5935fcf5ef2aSThomas Huth } 5936fcf5ef2aSThomas Huth gen_set_label(l1); 5937fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5938fcf5ef2aSThomas Huth } 5939fcf5ef2aSThomas Huth } else { 5940fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5941fcf5ef2aSThomas Huth } 5942fcf5ef2aSThomas Huth tcg_temp_free(t0); 5943fcf5ef2aSThomas Huth tcg_temp_free(t1); 5944fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5945fcf5ef2aSThomas Huth /* Update Rc0 */ 5946fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5947fcf5ef2aSThomas Huth } 5948fcf5ef2aSThomas Huth } 5949fcf5ef2aSThomas Huth 5950fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5951fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5952fcf5ef2aSThomas Huth { \ 5953fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5954fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5955fcf5ef2aSThomas Huth } 5956fcf5ef2aSThomas Huth 5957fcf5ef2aSThomas Huth /* macchw - macchw. */ 5958fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5959fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5960fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5961fcf5ef2aSThomas Huth /* macchws - macchws. */ 5962fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5963fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5964fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5965fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5966fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5967fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5968fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5969fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5970fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5971fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5972fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5973fcf5ef2aSThomas Huth /* machhw - machhw. */ 5974fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5975fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5976fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5977fcf5ef2aSThomas Huth /* machhws - machhws. */ 5978fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5979fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5980fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5981fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5982fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5983fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5984fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5985fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5986fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5987fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5988fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5989fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5990fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5991fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5992fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5993fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5994fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5995fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5996fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5997fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5998fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5999fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6000fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6001fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6002fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6003fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6004fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6005fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6006fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6007fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6008fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6009fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6010fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6011fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6012fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6013fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6014fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6015fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6016fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6017fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6018fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6019fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6020fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6021fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6022fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6023fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6024fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6025fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6026fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6027fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6028fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6029fcf5ef2aSThomas Huth 6030fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6031fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6032fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6033fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6034fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6035fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6036fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6037fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6038fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6039fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6040fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6041fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6042fcf5ef2aSThomas Huth 6043fcf5ef2aSThomas Huth /* mfdcr */ 6044fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6045fcf5ef2aSThomas Huth { 6046fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6047fcf5ef2aSThomas Huth GEN_PRIV; 6048fcf5ef2aSThomas Huth #else 6049fcf5ef2aSThomas Huth TCGv dcrn; 6050fcf5ef2aSThomas Huth 6051fcf5ef2aSThomas Huth CHK_SV; 6052fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6053fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6054fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6055fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6056fcf5ef2aSThomas Huth } 6057fcf5ef2aSThomas Huth 6058fcf5ef2aSThomas Huth /* mtdcr */ 6059fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6060fcf5ef2aSThomas Huth { 6061fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6062fcf5ef2aSThomas Huth GEN_PRIV; 6063fcf5ef2aSThomas Huth #else 6064fcf5ef2aSThomas Huth TCGv dcrn; 6065fcf5ef2aSThomas Huth 6066fcf5ef2aSThomas Huth CHK_SV; 6067fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6068fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6069fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6070fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6071fcf5ef2aSThomas Huth } 6072fcf5ef2aSThomas Huth 6073fcf5ef2aSThomas Huth /* mfdcrx */ 6074fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6075fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6076fcf5ef2aSThomas Huth { 6077fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6078fcf5ef2aSThomas Huth GEN_PRIV; 6079fcf5ef2aSThomas Huth #else 6080fcf5ef2aSThomas Huth CHK_SV; 6081fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6082fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6083fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6084fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6085fcf5ef2aSThomas Huth } 6086fcf5ef2aSThomas Huth 6087fcf5ef2aSThomas Huth /* mtdcrx */ 6088fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6089fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6090fcf5ef2aSThomas Huth { 6091fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6092fcf5ef2aSThomas Huth GEN_PRIV; 6093fcf5ef2aSThomas Huth #else 6094fcf5ef2aSThomas Huth CHK_SV; 6095fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6096fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6097fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6098fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6099fcf5ef2aSThomas Huth } 6100fcf5ef2aSThomas Huth 6101fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6102fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6103fcf5ef2aSThomas Huth { 6104fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6105fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6106fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6107fcf5ef2aSThomas Huth } 6108fcf5ef2aSThomas Huth 6109fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6110fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6111fcf5ef2aSThomas Huth { 6112fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6113fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6114fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6115fcf5ef2aSThomas Huth } 6116fcf5ef2aSThomas Huth 6117fcf5ef2aSThomas Huth /* dccci */ 6118fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6119fcf5ef2aSThomas Huth { 6120fcf5ef2aSThomas Huth CHK_SV; 6121fcf5ef2aSThomas Huth /* interpreted as no-op */ 6122fcf5ef2aSThomas Huth } 6123fcf5ef2aSThomas Huth 6124fcf5ef2aSThomas Huth /* dcread */ 6125fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6126fcf5ef2aSThomas Huth { 6127fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6128fcf5ef2aSThomas Huth GEN_PRIV; 6129fcf5ef2aSThomas Huth #else 6130fcf5ef2aSThomas Huth TCGv EA, val; 6131fcf5ef2aSThomas Huth 6132fcf5ef2aSThomas Huth CHK_SV; 6133fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6134fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6135fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6136fcf5ef2aSThomas Huth val = tcg_temp_new(); 6137fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6138fcf5ef2aSThomas Huth tcg_temp_free(val); 6139fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6140fcf5ef2aSThomas Huth tcg_temp_free(EA); 6141fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6142fcf5ef2aSThomas Huth } 6143fcf5ef2aSThomas Huth 6144fcf5ef2aSThomas Huth /* icbt */ 6145fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6146fcf5ef2aSThomas Huth { 6147fcf5ef2aSThomas Huth /* interpreted as no-op */ 6148fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6149fcf5ef2aSThomas Huth * but does not generate any exception 6150fcf5ef2aSThomas Huth */ 6151fcf5ef2aSThomas Huth } 6152fcf5ef2aSThomas Huth 6153fcf5ef2aSThomas Huth /* iccci */ 6154fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6155fcf5ef2aSThomas Huth { 6156fcf5ef2aSThomas Huth CHK_SV; 6157fcf5ef2aSThomas Huth /* interpreted as no-op */ 6158fcf5ef2aSThomas Huth } 6159fcf5ef2aSThomas Huth 6160fcf5ef2aSThomas Huth /* icread */ 6161fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6162fcf5ef2aSThomas Huth { 6163fcf5ef2aSThomas Huth CHK_SV; 6164fcf5ef2aSThomas Huth /* interpreted as no-op */ 6165fcf5ef2aSThomas Huth } 6166fcf5ef2aSThomas Huth 6167fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6168fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6169fcf5ef2aSThomas Huth { 6170fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6171fcf5ef2aSThomas Huth GEN_PRIV; 6172fcf5ef2aSThomas Huth #else 6173fcf5ef2aSThomas Huth CHK_SV; 6174fcf5ef2aSThomas Huth /* Restore CPU state */ 6175fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 6176fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6177fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6178fcf5ef2aSThomas Huth } 6179fcf5ef2aSThomas Huth 6180fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6181fcf5ef2aSThomas Huth { 6182fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6183fcf5ef2aSThomas Huth GEN_PRIV; 6184fcf5ef2aSThomas Huth #else 6185fcf5ef2aSThomas Huth CHK_SV; 6186fcf5ef2aSThomas Huth /* Restore CPU state */ 6187fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 6188fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6189fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6190fcf5ef2aSThomas Huth } 6191fcf5ef2aSThomas Huth 6192fcf5ef2aSThomas Huth /* BookE specific */ 6193fcf5ef2aSThomas Huth 6194fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6195fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6196fcf5ef2aSThomas Huth { 6197fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6198fcf5ef2aSThomas Huth GEN_PRIV; 6199fcf5ef2aSThomas Huth #else 6200fcf5ef2aSThomas Huth CHK_SV; 6201fcf5ef2aSThomas Huth /* Restore CPU state */ 6202fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 6203fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6204fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6205fcf5ef2aSThomas Huth } 6206fcf5ef2aSThomas Huth 6207fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6208fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6209fcf5ef2aSThomas Huth { 6210fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6211fcf5ef2aSThomas Huth GEN_PRIV; 6212fcf5ef2aSThomas Huth #else 6213fcf5ef2aSThomas Huth CHK_SV; 6214fcf5ef2aSThomas Huth /* Restore CPU state */ 6215fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 6216fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6217fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6218fcf5ef2aSThomas Huth } 6219fcf5ef2aSThomas Huth 6220fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6221fcf5ef2aSThomas Huth 6222fcf5ef2aSThomas Huth /* tlbre */ 6223fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6224fcf5ef2aSThomas Huth { 6225fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6226fcf5ef2aSThomas Huth GEN_PRIV; 6227fcf5ef2aSThomas Huth #else 6228fcf5ef2aSThomas Huth CHK_SV; 6229fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6230fcf5ef2aSThomas Huth case 0: 6231fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6232fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6233fcf5ef2aSThomas Huth break; 6234fcf5ef2aSThomas Huth case 1: 6235fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6236fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6237fcf5ef2aSThomas Huth break; 6238fcf5ef2aSThomas Huth default: 6239fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6240fcf5ef2aSThomas Huth break; 6241fcf5ef2aSThomas Huth } 6242fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6243fcf5ef2aSThomas Huth } 6244fcf5ef2aSThomas Huth 6245fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6246fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6247fcf5ef2aSThomas Huth { 6248fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6249fcf5ef2aSThomas Huth GEN_PRIV; 6250fcf5ef2aSThomas Huth #else 6251fcf5ef2aSThomas Huth TCGv t0; 6252fcf5ef2aSThomas Huth 6253fcf5ef2aSThomas Huth CHK_SV; 6254fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6255fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6256fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6257fcf5ef2aSThomas Huth tcg_temp_free(t0); 6258fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6259fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6260fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6261fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6262fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6263fcf5ef2aSThomas Huth gen_set_label(l1); 6264fcf5ef2aSThomas Huth } 6265fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6266fcf5ef2aSThomas Huth } 6267fcf5ef2aSThomas Huth 6268fcf5ef2aSThomas Huth /* tlbwe */ 6269fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6270fcf5ef2aSThomas Huth { 6271fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6272fcf5ef2aSThomas Huth GEN_PRIV; 6273fcf5ef2aSThomas Huth #else 6274fcf5ef2aSThomas Huth CHK_SV; 6275fcf5ef2aSThomas Huth 6276fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6277fcf5ef2aSThomas Huth case 0: 6278fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6279fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6280fcf5ef2aSThomas Huth break; 6281fcf5ef2aSThomas Huth case 1: 6282fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6283fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6284fcf5ef2aSThomas Huth break; 6285fcf5ef2aSThomas Huth default: 6286fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6287fcf5ef2aSThomas Huth break; 6288fcf5ef2aSThomas Huth } 6289fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6290fcf5ef2aSThomas Huth } 6291fcf5ef2aSThomas Huth 6292fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6293fcf5ef2aSThomas Huth 6294fcf5ef2aSThomas Huth /* tlbre */ 6295fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6296fcf5ef2aSThomas Huth { 6297fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6298fcf5ef2aSThomas Huth GEN_PRIV; 6299fcf5ef2aSThomas Huth #else 6300fcf5ef2aSThomas Huth CHK_SV; 6301fcf5ef2aSThomas Huth 6302fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6303fcf5ef2aSThomas Huth case 0: 6304fcf5ef2aSThomas Huth case 1: 6305fcf5ef2aSThomas Huth case 2: 6306fcf5ef2aSThomas Huth { 6307fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6308fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6309fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6310fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6311fcf5ef2aSThomas Huth } 6312fcf5ef2aSThomas Huth break; 6313fcf5ef2aSThomas Huth default: 6314fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6315fcf5ef2aSThomas Huth break; 6316fcf5ef2aSThomas Huth } 6317fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6318fcf5ef2aSThomas Huth } 6319fcf5ef2aSThomas Huth 6320fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6321fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6322fcf5ef2aSThomas Huth { 6323fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6324fcf5ef2aSThomas Huth GEN_PRIV; 6325fcf5ef2aSThomas Huth #else 6326fcf5ef2aSThomas Huth TCGv t0; 6327fcf5ef2aSThomas Huth 6328fcf5ef2aSThomas Huth CHK_SV; 6329fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6330fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6331fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6332fcf5ef2aSThomas Huth tcg_temp_free(t0); 6333fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6334fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6335fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6336fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6337fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6338fcf5ef2aSThomas Huth gen_set_label(l1); 6339fcf5ef2aSThomas Huth } 6340fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6341fcf5ef2aSThomas Huth } 6342fcf5ef2aSThomas Huth 6343fcf5ef2aSThomas Huth /* tlbwe */ 6344fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6345fcf5ef2aSThomas Huth { 6346fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6347fcf5ef2aSThomas Huth GEN_PRIV; 6348fcf5ef2aSThomas Huth #else 6349fcf5ef2aSThomas Huth CHK_SV; 6350fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6351fcf5ef2aSThomas Huth case 0: 6352fcf5ef2aSThomas Huth case 1: 6353fcf5ef2aSThomas Huth case 2: 6354fcf5ef2aSThomas Huth { 6355fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6356fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6357fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6358fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6359fcf5ef2aSThomas Huth } 6360fcf5ef2aSThomas Huth break; 6361fcf5ef2aSThomas Huth default: 6362fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6363fcf5ef2aSThomas Huth break; 6364fcf5ef2aSThomas Huth } 6365fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6366fcf5ef2aSThomas Huth } 6367fcf5ef2aSThomas Huth 6368fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6369fcf5ef2aSThomas Huth 6370fcf5ef2aSThomas Huth /* tlbre */ 6371fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6372fcf5ef2aSThomas Huth { 6373fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6374fcf5ef2aSThomas Huth GEN_PRIV; 6375fcf5ef2aSThomas Huth #else 6376fcf5ef2aSThomas Huth CHK_SV; 6377fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6378fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6379fcf5ef2aSThomas Huth } 6380fcf5ef2aSThomas Huth 6381fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6382fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6383fcf5ef2aSThomas Huth { 6384fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6385fcf5ef2aSThomas Huth GEN_PRIV; 6386fcf5ef2aSThomas Huth #else 6387fcf5ef2aSThomas Huth TCGv t0; 6388fcf5ef2aSThomas Huth 6389fcf5ef2aSThomas Huth CHK_SV; 6390fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6391fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6392fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6393fcf5ef2aSThomas Huth } else { 6394fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6395fcf5ef2aSThomas Huth } 6396fcf5ef2aSThomas Huth 6397fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6398fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6399fcf5ef2aSThomas Huth tcg_temp_free(t0); 6400fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6401fcf5ef2aSThomas Huth } 6402fcf5ef2aSThomas Huth 6403fcf5ef2aSThomas Huth /* tlbwe */ 6404fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6405fcf5ef2aSThomas Huth { 6406fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6407fcf5ef2aSThomas Huth GEN_PRIV; 6408fcf5ef2aSThomas Huth #else 6409fcf5ef2aSThomas Huth CHK_SV; 6410fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6411fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6412fcf5ef2aSThomas Huth } 6413fcf5ef2aSThomas Huth 6414fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6415fcf5ef2aSThomas Huth { 6416fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6417fcf5ef2aSThomas Huth GEN_PRIV; 6418fcf5ef2aSThomas Huth #else 6419fcf5ef2aSThomas Huth TCGv t0; 6420fcf5ef2aSThomas Huth 6421fcf5ef2aSThomas Huth CHK_SV; 6422fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6423fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6424fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6425fcf5ef2aSThomas Huth tcg_temp_free(t0); 6426fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6427fcf5ef2aSThomas Huth } 6428fcf5ef2aSThomas Huth 6429fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6430fcf5ef2aSThomas Huth { 6431fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6432fcf5ef2aSThomas Huth GEN_PRIV; 6433fcf5ef2aSThomas Huth #else 6434fcf5ef2aSThomas Huth TCGv t0; 6435fcf5ef2aSThomas Huth 6436fcf5ef2aSThomas Huth CHK_SV; 6437fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6438fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6439fcf5ef2aSThomas Huth 6440fcf5ef2aSThomas Huth switch((ctx->opcode >> 21) & 0x3) { 6441fcf5ef2aSThomas Huth case 0: 6442fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6443fcf5ef2aSThomas Huth break; 6444fcf5ef2aSThomas Huth case 1: 6445fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6446fcf5ef2aSThomas Huth break; 6447fcf5ef2aSThomas Huth case 3: 6448fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6449fcf5ef2aSThomas Huth break; 6450fcf5ef2aSThomas Huth default: 6451fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6452fcf5ef2aSThomas Huth break; 6453fcf5ef2aSThomas Huth } 6454fcf5ef2aSThomas Huth 6455fcf5ef2aSThomas Huth tcg_temp_free(t0); 6456fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6457fcf5ef2aSThomas Huth } 6458fcf5ef2aSThomas Huth 6459fcf5ef2aSThomas Huth 6460fcf5ef2aSThomas Huth /* wrtee */ 6461fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6462fcf5ef2aSThomas Huth { 6463fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6464fcf5ef2aSThomas Huth GEN_PRIV; 6465fcf5ef2aSThomas Huth #else 6466fcf5ef2aSThomas Huth TCGv t0; 6467fcf5ef2aSThomas Huth 6468fcf5ef2aSThomas Huth CHK_SV; 6469fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6470fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6471fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6472fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6473fcf5ef2aSThomas Huth tcg_temp_free(t0); 6474fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception 6475fcf5ef2aSThomas Huth * if we just set msr_ee to 1 6476fcf5ef2aSThomas Huth */ 6477fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6478fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6479fcf5ef2aSThomas Huth } 6480fcf5ef2aSThomas Huth 6481fcf5ef2aSThomas Huth /* wrteei */ 6482fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6483fcf5ef2aSThomas Huth { 6484fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6485fcf5ef2aSThomas Huth GEN_PRIV; 6486fcf5ef2aSThomas Huth #else 6487fcf5ef2aSThomas Huth CHK_SV; 6488fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6489fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6490fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6491fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6492fcf5ef2aSThomas Huth } else { 6493fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6494fcf5ef2aSThomas Huth } 6495fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6496fcf5ef2aSThomas Huth } 6497fcf5ef2aSThomas Huth 6498fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6499fcf5ef2aSThomas Huth 6500fcf5ef2aSThomas Huth /* dlmzb */ 6501fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6502fcf5ef2aSThomas Huth { 6503fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6504fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6505fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6506fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6507fcf5ef2aSThomas Huth } 6508fcf5ef2aSThomas Huth 6509fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6510fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6511fcf5ef2aSThomas Huth { 6512fcf5ef2aSThomas Huth /* interpreted as no-op */ 6513fcf5ef2aSThomas Huth } 6514fcf5ef2aSThomas Huth 6515fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6516fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6517fcf5ef2aSThomas Huth { 6518fcf5ef2aSThomas Huth /* interpreted as no-op */ 6519fcf5ef2aSThomas Huth } 6520fcf5ef2aSThomas Huth 6521fcf5ef2aSThomas Huth /* icbt */ 6522fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6523fcf5ef2aSThomas Huth { 6524fcf5ef2aSThomas Huth /* interpreted as no-op */ 6525fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6526fcf5ef2aSThomas Huth * but does not generate any exception 6527fcf5ef2aSThomas Huth */ 6528fcf5ef2aSThomas Huth } 6529fcf5ef2aSThomas Huth 6530fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6531fcf5ef2aSThomas Huth 6532fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6533fcf5ef2aSThomas Huth { 6534fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6535fcf5ef2aSThomas Huth GEN_PRIV; 6536fcf5ef2aSThomas Huth #else 6537ebca5e6dSCédric Le Goater CHK_HV; 65387af1e7b0SCédric Le Goater /* 64-bit server processors compliant with arch 2.x */ 65397af1e7b0SCédric Le Goater if (ctx->insns_flags & PPC_SEGMENT_64B) { 65407af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 65417af1e7b0SCédric Le Goater } else { 6542fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 65437af1e7b0SCédric Le Goater } 6544fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6545fcf5ef2aSThomas Huth } 6546fcf5ef2aSThomas Huth 6547fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6548fcf5ef2aSThomas Huth { 6549fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6550fcf5ef2aSThomas Huth GEN_PRIV; 6551fcf5ef2aSThomas Huth #else 6552ebca5e6dSCédric Le Goater CHK_HV; 65537af1e7b0SCédric Le Goater /* 64-bit server processors compliant with arch 2.x */ 65547af1e7b0SCédric Le Goater if (ctx->insns_flags & PPC_SEGMENT_64B) { 65557af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 65567af1e7b0SCédric Le Goater } else { 6557fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 65587af1e7b0SCédric Le Goater } 6559fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6560fcf5ef2aSThomas Huth } 6561fcf5ef2aSThomas Huth 65627af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 65637af1e7b0SCédric Le Goater { 65647af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 65657af1e7b0SCédric Le Goater GEN_PRIV; 65667af1e7b0SCédric Le Goater #else 65677af1e7b0SCédric Le Goater CHK_HV; 65687af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 65697af1e7b0SCédric Le Goater /* interpreted as no-op */ 65707af1e7b0SCédric Le Goater } 6571fcf5ef2aSThomas Huth 6572fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6573fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6574fcf5ef2aSThomas Huth { 6575fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6576fcf5ef2aSThomas Huth 6577fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6578fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6579fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6580fcf5ef2aSThomas Huth } 6581fcf5ef2aSThomas Huth 6582fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6583fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6584fcf5ef2aSThomas Huth { 6585fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6586fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6587fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6588fcf5ef2aSThomas Huth 6589fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6590fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6591fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6592fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6593fcf5ef2aSThomas Huth } else { 6594fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6595fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6596fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6597fcf5ef2aSThomas Huth } 6598fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6599fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6600fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6601fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6602fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6603fcf5ef2aSThomas Huth } 6604fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6605fcf5ef2aSThomas Huth 6606fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6607fcf5ef2aSThomas Huth { 6608fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6609fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6610fcf5ef2aSThomas Huth return; 6611fcf5ef2aSThomas Huth } 6612fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6613fcf5ef2aSThomas Huth } 6614fcf5ef2aSThomas Huth 6615fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6616fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6617fcf5ef2aSThomas Huth { \ 6618fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6619fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6620fcf5ef2aSThomas Huth return; \ 6621fcf5ef2aSThomas Huth } \ 6622fcf5ef2aSThomas Huth /* Because tbegin always fails in QEMU, these user \ 6623fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6624fcf5ef2aSThomas Huth * \ 6625fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6626fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6627fcf5ef2aSThomas Huth */ \ 6628fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6629fcf5ef2aSThomas Huth } 6630fcf5ef2aSThomas Huth 6631fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6632fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6633fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6634fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6635fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6636fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6637fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6638b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6639b8b4576eSSuraj Jitindar Singh { 6640b8b4576eSSuraj Jitindar Singh // Do Nothing 6641b8b4576eSSuraj Jitindar Singh } 6642fcf5ef2aSThomas Huth 664380b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 664480b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 664580b8c1eeSNikunj A Dadhania { \ 664680b8c1eeSNikunj A Dadhania /* Generate invalid exception until \ 664780b8c1eeSNikunj A Dadhania * we have an implementation of the copy \ 664880b8c1eeSNikunj A Dadhania * paste facility \ 664980b8c1eeSNikunj A Dadhania */ \ 665080b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 665180b8c1eeSNikunj A Dadhania } 665280b8c1eeSNikunj A Dadhania 665380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 665480b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 665580b8c1eeSNikunj A Dadhania 6656fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6657fcf5ef2aSThomas Huth { 6658fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6659fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6660fcf5ef2aSThomas Huth return; 6661fcf5ef2aSThomas Huth } 6662fcf5ef2aSThomas Huth /* Because tbegin always fails, the tcheck implementation 6663fcf5ef2aSThomas Huth * is simple: 6664fcf5ef2aSThomas Huth * 6665fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6666fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6667fcf5ef2aSThomas Huth */ 6668fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6669fcf5ef2aSThomas Huth } 6670fcf5ef2aSThomas Huth 6671fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6672fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6673fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6674fcf5ef2aSThomas Huth { \ 6675fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6676fcf5ef2aSThomas Huth } 6677fcf5ef2aSThomas Huth 6678fcf5ef2aSThomas Huth #else 6679fcf5ef2aSThomas Huth 6680fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6681fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6682fcf5ef2aSThomas Huth { \ 6683fcf5ef2aSThomas Huth CHK_SV; \ 6684fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6685fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6686fcf5ef2aSThomas Huth return; \ 6687fcf5ef2aSThomas Huth } \ 6688fcf5ef2aSThomas Huth /* Because tbegin always fails, the implementation is \ 6689fcf5ef2aSThomas Huth * simple: \ 6690fcf5ef2aSThomas Huth * \ 6691fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6692fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6693fcf5ef2aSThomas Huth */ \ 6694fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6695fcf5ef2aSThomas Huth } 6696fcf5ef2aSThomas Huth 6697fcf5ef2aSThomas Huth #endif 6698fcf5ef2aSThomas Huth 6699fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6700fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6701fcf5ef2aSThomas Huth 6702fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6703fcf5ef2aSThomas Huth 6704fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6705fcf5ef2aSThomas Huth 6706fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6707fcf5ef2aSThomas Huth 6708fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6709fcf5ef2aSThomas Huth 6710fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6711fcf5ef2aSThomas Huth 67125cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 67135cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 67145cb091a4SNikunj A Dadhania { 67155cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 67165cb091a4SNikunj A Dadhania case 0: /* lfdp */ 67175cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 67185cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 67195cb091a4SNikunj A Dadhania } 67205cb091a4SNikunj A Dadhania break; 67215cb091a4SNikunj A Dadhania case 2: /* lxsd */ 67225cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 67235cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 67245cb091a4SNikunj A Dadhania } 67255cb091a4SNikunj A Dadhania break; 67265cb091a4SNikunj A Dadhania case 3: /* lxssp */ 67275cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 67285cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 67295cb091a4SNikunj A Dadhania } 67305cb091a4SNikunj A Dadhania break; 67315cb091a4SNikunj A Dadhania } 67325cb091a4SNikunj A Dadhania return gen_invalid(ctx); 67335cb091a4SNikunj A Dadhania } 67345cb091a4SNikunj A Dadhania 6735d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6736e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6737e3001664SNikunj A Dadhania { 6738e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6739e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6740e3001664SNikunj A Dadhania case 1: /* lxv */ 6741d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6742d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6743d59ba583SNikunj A Dadhania } 6744e3001664SNikunj A Dadhania break; 6745e3001664SNikunj A Dadhania case 5: /* stxv */ 6746d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6747d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6748d59ba583SNikunj A Dadhania } 6749e3001664SNikunj A Dadhania break; 6750e3001664SNikunj A Dadhania } 6751e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6752e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6753e3001664SNikunj A Dadhania case 0: /* stfdp */ 6754e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6755e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6756e3001664SNikunj A Dadhania } 6757e3001664SNikunj A Dadhania break; 6758e3001664SNikunj A Dadhania case 2: /* stxsd */ 6759e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6760e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6761e3001664SNikunj A Dadhania } 6762e3001664SNikunj A Dadhania break; 6763e3001664SNikunj A Dadhania case 3: /* stxssp */ 6764e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6765e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6766e3001664SNikunj A Dadhania } 6767e3001664SNikunj A Dadhania break; 6768e3001664SNikunj A Dadhania } 6769e3001664SNikunj A Dadhania } 6770e3001664SNikunj A Dadhania return gen_invalid(ctx); 6771e3001664SNikunj A Dadhania } 6772e3001664SNikunj A Dadhania 6773fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6774fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6775fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6776fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6777fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6778fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6779fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6780fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6781fcf5ef2aSThomas Huth #endif 6782fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6783fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6784fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6785fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6786fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6787fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6788fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6789fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6790fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6791fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6792fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6793fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6794fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6795fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6796fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6797fcf5ef2aSThomas Huth #endif 6798fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6799fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6800fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6801fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6802fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6803fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6804fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 680580b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6806b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 680780b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6808fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6809fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6810fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6811fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6812fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6813fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6814fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6815fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6816fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6817fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6818fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6819fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6820fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6821fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6822fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6823fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6824fcf5ef2aSThomas Huth #endif 6825fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6826fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6827fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6828fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6829fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6830fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6831fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6832fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6833fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6834fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6835fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6836fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6837fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6838fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6839fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6840fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6841fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6842fcf5ef2aSThomas Huth #endif 6843fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6844fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6845fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6846fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6847fcf5ef2aSThomas Huth #endif 68485cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 68495cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6850d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6851e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6852fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6853fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6854fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6855fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6856fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6857fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6858c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6859fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6860fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6861fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6862fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6863a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6864a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6865fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6866fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6867fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6868fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6869a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6870a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6871fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6872fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6873fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6874fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6875fcf5ef2aSThomas Huth #endif 6876fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6877fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6878c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6879fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6880fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6881fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6882fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6883fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6884fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6885fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6886fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6887fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6888cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6889fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6890fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6891fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6892fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6893fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6894fcf5ef2aSThomas Huth #endif 6895fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6896fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6897fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6898fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6899fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6900fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6901fcf5ef2aSThomas Huth #endif 6902fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6903fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6904fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6905fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6906fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6907fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6908fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6909fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6910fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6911b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6912fcf5ef2aSThomas Huth #endif 6913fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6914fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6915fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 691650728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6917fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6918fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 691950728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6920fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 692150728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6922fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 692350728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6924fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6925fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 692650728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6927fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 692899d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6929fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6930fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 693150728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6932fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6933fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6934fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6935fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6936fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6937fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6938fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6939fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6940fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6941fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6942fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6943fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6944fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6945fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6946fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6947fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6948fcf5ef2aSThomas Huth #endif 6949fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6950fcf5ef2aSThomas Huth /* XXX Those instructions will need to be handled differently for 6951fcf5ef2aSThomas Huth * different ISA versions */ 6952fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6953fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6954c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 6955c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 6956fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6957fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6958fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6959fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6960a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 696162d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6962fcf5ef2aSThomas Huth #endif 6963fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6964fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6965fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6966fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6967fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6968fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6969fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6970fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6971fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6972fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6973fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6974fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6975fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6976fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6977fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6978fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6979fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6980fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6981fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6982fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6983fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6984fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6985fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6986fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6987fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6988fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6989fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6990fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6991fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6992fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6993fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6994fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6995fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6996fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6997fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6998fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6999fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7000fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7001fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7002fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7003fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7004fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7005fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7006fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7007fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7008fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7009fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7010fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7011fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7012fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7013fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7014fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7015fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7016fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7017fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7018fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7019fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7020fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7021fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7022fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7023fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7024fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7025fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7026fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7027fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7028fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7029fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7030fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7031fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7032fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7033fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7034fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7035fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7036fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7037fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7038fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7039fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7040fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7041fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7042fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7043fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7044fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7045fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7046fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7047fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7048fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7049fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7050fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7051fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7052fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7053fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7054fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7055fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7056fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 70577af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 70587af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7059fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7060fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7061fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7062fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7063fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 7064fcf5ef2aSThomas Huth GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 7065fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7066fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 70670c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 70680c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7069fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7070fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7071fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7072fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7073fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7074fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7075fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7076fcf5ef2aSThomas Huth PPC2_ISA300), 7077fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7078fcf5ef2aSThomas Huth #endif 7079fcf5ef2aSThomas Huth 7080fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7081fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7082fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7083fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7084fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7085fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7086fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7087fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7088fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7089fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7090fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7091fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7092fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7093fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7094fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 7095*4c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7096fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7097fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7098fcf5ef2aSThomas Huth 7099fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7100fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7101fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7102fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7103fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7104fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7105fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7106fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7107fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7108fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7109fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7110fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7111fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7112fcf5ef2aSThomas Huth 7113fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7114fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7115fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7116fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7117fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7118fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7119fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7120fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7121fcf5ef2aSThomas Huth 7122fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7123fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7124fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7125fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7126fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7127fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7128fcf5ef2aSThomas Huth 7129fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7130fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7131fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7132fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7133fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7134fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7135fcf5ef2aSThomas Huth #endif 7136fcf5ef2aSThomas Huth 7137fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7138fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7139fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7140fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7141fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7142fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7143fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7144fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7145fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7146fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7147fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7148fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7149fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7150fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7151fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7152fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7153fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7154fcf5ef2aSThomas Huth 7155fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7156fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7157fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7158fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7159fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7160fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7161fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7162fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7163fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7164fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7165fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7166fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7167fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7168fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7169fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7170fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7171fcf5ef2aSThomas Huth #endif 7172fcf5ef2aSThomas Huth 7173fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7174fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7175fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7176fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7177fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7178fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7179fcf5ef2aSThomas Huth PPC_64B) 7180fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7181fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7182fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7183fcf5ef2aSThomas Huth PPC_64B), \ 7184fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7185fcf5ef2aSThomas Huth PPC_64B), \ 7186fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7187fcf5ef2aSThomas Huth PPC_64B) 7188fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7189fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7190fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7191fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7192fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7193fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7194fcf5ef2aSThomas Huth #endif 7195fcf5ef2aSThomas Huth 7196fcf5ef2aSThomas Huth #undef GEN_LD 7197fcf5ef2aSThomas Huth #undef GEN_LDU 7198fcf5ef2aSThomas Huth #undef GEN_LDUX 7199fcf5ef2aSThomas Huth #undef GEN_LDX_E 7200fcf5ef2aSThomas Huth #undef GEN_LDS 7201fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 7202fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7203fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 7204fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7205fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7206fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7207fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7208fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7209fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 7210fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 7211fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 7212fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7213fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7214fcf5ef2aSThomas Huth 7215fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7216fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7217fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7218fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7219fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7220fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7221fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7222fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7223fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7224fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7225fcf5ef2aSThomas Huth 7226fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7227fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7228fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7229fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7230fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7231fcf5ef2aSThomas Huth #endif 7232fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7233fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7234fcf5ef2aSThomas Huth 723550728199SRoman Kapl /* External PID based load */ 723650728199SRoman Kapl #undef GEN_LDEPX 723750728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 723850728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 723950728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 724050728199SRoman Kapl 724150728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 724250728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 724350728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 724450728199SRoman Kapl #if defined(TARGET_PPC64) 724550728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 724650728199SRoman Kapl #endif 724750728199SRoman Kapl 7248fcf5ef2aSThomas Huth #undef GEN_ST 7249fcf5ef2aSThomas Huth #undef GEN_STU 7250fcf5ef2aSThomas Huth #undef GEN_STUX 7251fcf5ef2aSThomas Huth #undef GEN_STX_E 7252fcf5ef2aSThomas Huth #undef GEN_STS 7253fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 7254fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7255fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 7256fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7257fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 7258fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7259fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 72600123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7261fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 7262fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 7263fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 7264fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7265fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 7266fcf5ef2aSThomas Huth 7267fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7268fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7269fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7270fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7271fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7272fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7273fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7274fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7275fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7276fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7277fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7278fcf5ef2aSThomas Huth #endif 7279fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7280fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7281fcf5ef2aSThomas Huth 728250728199SRoman Kapl #undef GEN_STEPX 728350728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 728450728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 728550728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 728650728199SRoman Kapl 728750728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 728850728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 728950728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 729050728199SRoman Kapl #if defined(TARGET_PPC64) 729150728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 729250728199SRoman Kapl #endif 729350728199SRoman Kapl 7294fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7295fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7296fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7297fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7298fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7299fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7300fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7301fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7302fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7303fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7304fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7305fcf5ef2aSThomas Huth 7306fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7307fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7308fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7309fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7310fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7311fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7312fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7313fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7314fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7315fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7316fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7317fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7318fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7319fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7320fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7321fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7322fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7323fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7324fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7325fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7326fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7327fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7328fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7329fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7330fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7331fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7332fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7333fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7334fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7335fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7336fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7337fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7338fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7339fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7340fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7341fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7342fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7343fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7344fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7345fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7346fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7347fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7348fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7349fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7350fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7351fcf5ef2aSThomas Huth 7352fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7353fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7354fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7355fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7356fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7357fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7358fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7359fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7360fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7361fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7362fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7363fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7364fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7365fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7366fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7367fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7368fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7369fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7370fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7371fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7372fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7373fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7374fcf5ef2aSThomas Huth 7375fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 7376fcf5ef2aSThomas Huth 7377fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 7378fcf5ef2aSThomas Huth 7379fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 7380fcf5ef2aSThomas Huth 7381fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 7382fcf5ef2aSThomas Huth 7383fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 7384fcf5ef2aSThomas Huth }; 7385fcf5ef2aSThomas Huth 7386fcf5ef2aSThomas Huth #include "helper_regs.h" 73875b27a92dSPaolo Bonzini #include "translate_init.inc.c" 7388fcf5ef2aSThomas Huth 7389fcf5ef2aSThomas Huth /*****************************************************************************/ 7390fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 7391fcf5ef2aSThomas Huth void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 7392fcf5ef2aSThomas Huth int flags) 7393fcf5ef2aSThomas Huth { 7394fcf5ef2aSThomas Huth #define RGPL 4 7395fcf5ef2aSThomas Huth #define RFPL 4 7396fcf5ef2aSThomas Huth 7397fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7398fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 7399fcf5ef2aSThomas Huth int i; 7400fcf5ef2aSThomas Huth 7401fcf5ef2aSThomas Huth cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7402fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7403fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 7404fcf5ef2aSThomas Huth cs->cpu_index); 7405fcf5ef2aSThomas Huth cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7406fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 7407fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 7408fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 7409fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 7410fcf5ef2aSThomas Huth cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7411fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7412fcf5ef2aSThomas Huth " DECR %08" PRIu32 7413fcf5ef2aSThomas Huth #endif 7414fcf5ef2aSThomas Huth "\n", 7415fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7416fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7417fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 7418fcf5ef2aSThomas Huth #endif 7419fcf5ef2aSThomas Huth ); 7420fcf5ef2aSThomas Huth #endif 7421fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7422fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == 0) 7423fcf5ef2aSThomas Huth cpu_fprintf(f, "GPR%02d", i); 7424fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7425fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == (RGPL - 1)) 7426fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7427fcf5ef2aSThomas Huth } 7428fcf5ef2aSThomas Huth cpu_fprintf(f, "CR "); 7429fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 7430fcf5ef2aSThomas Huth cpu_fprintf(f, "%01x", env->crf[i]); 7431fcf5ef2aSThomas Huth cpu_fprintf(f, " ["); 7432fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 7433fcf5ef2aSThomas Huth char a = '-'; 7434fcf5ef2aSThomas Huth if (env->crf[i] & 0x08) 7435fcf5ef2aSThomas Huth a = 'L'; 7436fcf5ef2aSThomas Huth else if (env->crf[i] & 0x04) 7437fcf5ef2aSThomas Huth a = 'G'; 7438fcf5ef2aSThomas Huth else if (env->crf[i] & 0x02) 7439fcf5ef2aSThomas Huth a = 'E'; 7440fcf5ef2aSThomas Huth cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7441fcf5ef2aSThomas Huth } 7442fcf5ef2aSThomas Huth cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7443fcf5ef2aSThomas Huth env->reserve_addr); 7444685f1ce2SRichard Henderson 7445685f1ce2SRichard Henderson if (flags & CPU_DUMP_FPU) { 7446fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7447685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == 0) { 7448fcf5ef2aSThomas Huth cpu_fprintf(f, "FPR%02d", i); 7449685f1ce2SRichard Henderson } 7450fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 7451685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == (RFPL - 1)) { 7452fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7453fcf5ef2aSThomas Huth } 7454685f1ce2SRichard Henderson } 7455fcf5ef2aSThomas Huth cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7456685f1ce2SRichard Henderson } 7457685f1ce2SRichard Henderson 7458fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7459fcf5ef2aSThomas Huth cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7460fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7461fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7462fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7463fcf5ef2aSThomas Huth 7464fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7465fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7466fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7467fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7468fcf5ef2aSThomas Huth 7469fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7470fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7471fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7472fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7473fcf5ef2aSThomas Huth 7474fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7475fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7476fcf5ef2aSThomas Huth env->excp_model == POWERPC_EXCP_POWER8) { 7477fcf5ef2aSThomas Huth cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7478fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7479fcf5ef2aSThomas Huth } 7480fcf5ef2aSThomas Huth #endif 7481fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 7482fcf5ef2aSThomas Huth cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7483fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7484fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7485fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7486fcf5ef2aSThomas Huth 7487fcf5ef2aSThomas Huth cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7488fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7489fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7490fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7491fcf5ef2aSThomas Huth 7492fcf5ef2aSThomas Huth cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7493fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7494fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7495fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7496fcf5ef2aSThomas Huth 7497fcf5ef2aSThomas Huth cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7498fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7499fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7500fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7501fcf5ef2aSThomas Huth 7502fcf5ef2aSThomas Huth /* FSL-specific */ 7503fcf5ef2aSThomas Huth cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7504fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7505fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7506fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7507fcf5ef2aSThomas Huth 7508fcf5ef2aSThomas Huth /* 7509fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7510fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7511fcf5ef2aSThomas Huth */ 7512fcf5ef2aSThomas Huth } 7513fcf5ef2aSThomas Huth 7514fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7515fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 7516fcf5ef2aSThomas Huth cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7517fcf5ef2aSThomas Huth } 7518fcf5ef2aSThomas Huth #endif 7519fcf5ef2aSThomas Huth 7520d801a61eSSuraj Jitindar Singh if (env->spr_cb[SPR_LPCR].name) 7521d801a61eSSuraj Jitindar Singh cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7522d801a61eSSuraj Jitindar Singh 75230941d728SDavid Gibson switch (env->mmu_model) { 7524fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7525fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7526fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7527fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7528fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 75290941d728SDavid Gibson case POWERPC_MMU_64B: 75300941d728SDavid Gibson case POWERPC_MMU_2_03: 75310941d728SDavid Gibson case POWERPC_MMU_2_06: 75320941d728SDavid Gibson case POWERPC_MMU_2_07: 75330941d728SDavid Gibson case POWERPC_MMU_3_00: 7534fcf5ef2aSThomas Huth #endif 75354f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 75364f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 75374f4f28ffSSuraj Jitindar Singh } 75384a7518e0SCédric Le Goater if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 75394a7518e0SCédric Le Goater cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 75404a7518e0SCédric Le Goater } 75414f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7542fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7543fcf5ef2aSThomas Huth break; 7544fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 7545fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7546fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7547fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7548fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7549fcf5ef2aSThomas Huth 7550fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7551fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7552fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7553fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7554fcf5ef2aSThomas Huth 7555fcf5ef2aSThomas Huth cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7556fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7557fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7558fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7559fcf5ef2aSThomas Huth break; 7560fcf5ef2aSThomas Huth default: 7561fcf5ef2aSThomas Huth break; 7562fcf5ef2aSThomas Huth } 7563fcf5ef2aSThomas Huth #endif 7564fcf5ef2aSThomas Huth 7565fcf5ef2aSThomas Huth #undef RGPL 7566fcf5ef2aSThomas Huth #undef RFPL 7567fcf5ef2aSThomas Huth } 7568fcf5ef2aSThomas Huth 7569fcf5ef2aSThomas Huth void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7570fcf5ef2aSThomas Huth fprintf_function cpu_fprintf, int flags) 7571fcf5ef2aSThomas Huth { 7572fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7573fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7574fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7575fcf5ef2aSThomas Huth int op1, op2, op3; 7576fcf5ef2aSThomas Huth 7577fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7578fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7579fcf5ef2aSThomas Huth handler = t1[op1]; 7580fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7581fcf5ef2aSThomas Huth t2 = ind_table(handler); 7582fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7583fcf5ef2aSThomas Huth handler = t2[op2]; 7584fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7585fcf5ef2aSThomas Huth t3 = ind_table(handler); 7586fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7587fcf5ef2aSThomas Huth handler = t3[op3]; 7588fcf5ef2aSThomas Huth if (handler->count == 0) 7589fcf5ef2aSThomas Huth continue; 7590fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7591fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7592fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7593fcf5ef2aSThomas Huth handler->oname, 7594fcf5ef2aSThomas Huth handler->count, handler->count); 7595fcf5ef2aSThomas Huth } 7596fcf5ef2aSThomas Huth } else { 7597fcf5ef2aSThomas Huth if (handler->count == 0) 7598fcf5ef2aSThomas Huth continue; 7599fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7600fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7601fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7602fcf5ef2aSThomas Huth handler->count, handler->count); 7603fcf5ef2aSThomas Huth } 7604fcf5ef2aSThomas Huth } 7605fcf5ef2aSThomas Huth } else { 7606fcf5ef2aSThomas Huth if (handler->count == 0) 7607fcf5ef2aSThomas Huth continue; 7608fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7609fcf5ef2aSThomas Huth " %" PRId64 "\n", 7610fcf5ef2aSThomas Huth op1, op1, handler->oname, 7611fcf5ef2aSThomas Huth handler->count, handler->count); 7612fcf5ef2aSThomas Huth } 7613fcf5ef2aSThomas Huth } 7614fcf5ef2aSThomas Huth #endif 7615fcf5ef2aSThomas Huth } 7616fcf5ef2aSThomas Huth 7617b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7618fcf5ef2aSThomas Huth { 7619b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 76209c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 7621b0c2d521SEmilio G. Cota int bound; 7622fcf5ef2aSThomas Huth 7623b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 7624b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 7625b0c2d521SEmilio G. Cota ctx->pr = msr_pr; 7626b0c2d521SEmilio G. Cota ctx->mem_idx = env->dmmu_idx; 7627b0c2d521SEmilio G. Cota ctx->dr = msr_dr; 7628fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7629b0c2d521SEmilio G. Cota ctx->hv = msr_hv || !env->has_hv_mode; 7630fcf5ef2aSThomas Huth #endif 7631b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7632b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7633b0c2d521SEmilio G. Cota ctx->access_type = -1; 7634b0c2d521SEmilio G. Cota ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7635b0c2d521SEmilio G. Cota ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7636b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 76370e3bf489SRoman Kapl ctx->flags = env->flags; 7638fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7639b0c2d521SEmilio G. Cota ctx->sf_mode = msr_is_64bit(env, env->msr); 7640b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7641fcf5ef2aSThomas Huth #endif 7642e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7643e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 7644e69ba2b4SDavid Gibson || (env->mmu_model & POWERPC_MMU_64B); 7645fcf5ef2aSThomas Huth 7646b0c2d521SEmilio G. Cota ctx->fpu_enabled = !!msr_fp; 7647fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7648b0c2d521SEmilio G. Cota ctx->spe_enabled = !!msr_spe; 7649fcf5ef2aSThomas Huth else 7650b0c2d521SEmilio G. Cota ctx->spe_enabled = false; 7651fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7652b0c2d521SEmilio G. Cota ctx->altivec_enabled = !!msr_vr; 7653fcf5ef2aSThomas Huth else 7654b0c2d521SEmilio G. Cota ctx->altivec_enabled = false; 7655fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7656b0c2d521SEmilio G. Cota ctx->vsx_enabled = !!msr_vsx; 7657fcf5ef2aSThomas Huth } else { 7658b0c2d521SEmilio G. Cota ctx->vsx_enabled = false; 7659fcf5ef2aSThomas Huth } 7660fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7661fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7662b0c2d521SEmilio G. Cota ctx->tm_enabled = !!msr_tm; 7663fcf5ef2aSThomas Huth } else { 7664b0c2d521SEmilio G. Cota ctx->tm_enabled = false; 7665fcf5ef2aSThomas Huth } 7666fcf5ef2aSThomas Huth #endif 7667b0c2d521SEmilio G. Cota ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7668fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7669b0c2d521SEmilio G. Cota ctx->singlestep_enabled = CPU_SINGLE_STEP; 7670fcf5ef2aSThomas Huth else 7671b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 7672fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7673b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 76740e3bf489SRoman Kapl if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 76750e3bf489SRoman Kapl ctx->singlestep_enabled = 0; 76760e3bf489SRoman Kapl target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 76770e3bf489SRoman Kapl if (dbcr0 & DBCR0_ICMP) { 76780e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_SINGLE_STEP; 76790e3bf489SRoman Kapl } 76800e3bf489SRoman Kapl if (dbcr0 & DBCR0_BRT) { 76810e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_BRANCH_STEP; 76820e3bf489SRoman Kapl } 76830e3bf489SRoman Kapl 76840e3bf489SRoman Kapl } 7685b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7686b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7687fcf5ef2aSThomas Huth } 7688fcf5ef2aSThomas Huth #if defined (DO_SINGLE_STEP) && 0 7689fcf5ef2aSThomas Huth /* Single step trace mode */ 7690fcf5ef2aSThomas Huth msr_se = 1; 7691fcf5ef2aSThomas Huth #endif 7692b0c2d521SEmilio G. Cota 7693b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7694b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7695fcf5ef2aSThomas Huth } 7696fcf5ef2aSThomas Huth 7697b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7698b0c2d521SEmilio G. Cota { 7699b0c2d521SEmilio G. Cota } 7700fcf5ef2aSThomas Huth 7701b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7702b0c2d521SEmilio G. Cota { 7703b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7704b0c2d521SEmilio G. Cota } 7705b0c2d521SEmilio G. Cota 7706b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7707b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 7708b0c2d521SEmilio G. Cota { 7709b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7710b0c2d521SEmilio G. Cota 7711b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 77122a8ceefcSEmilio G. Cota dcbase->is_jmp = DISAS_NORETURN; 7713fcf5ef2aSThomas Huth /* The address covered by the breakpoint must be included in 7714fcf5ef2aSThomas Huth [tb->pc, tb->pc + tb->size) in order to for it to be 7715fcf5ef2aSThomas Huth properly cleared -- thus we increment the PC here so that 7716fcf5ef2aSThomas Huth the logic setting tb->size below does the right thing. */ 7717b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7718b0c2d521SEmilio G. Cota return true; 7719fcf5ef2aSThomas Huth } 7720fcf5ef2aSThomas Huth 7721b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7722b0c2d521SEmilio G. Cota { 7723b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7724b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 7725b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 7726b0c2d521SEmilio G. Cota 7727fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7728fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7729b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7730b0c2d521SEmilio G. Cota 7731b0c2d521SEmilio G. Cota if (unlikely(need_byteswap(ctx))) { 7732b0c2d521SEmilio G. Cota ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); 7733fcf5ef2aSThomas Huth } else { 7734b0c2d521SEmilio G. Cota ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); 7735fcf5ef2aSThomas Huth } 7736fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7737b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7738b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7739b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 7740b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7741fcf5ef2aSThomas Huth table = env->opcodes; 7742b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 7743fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7744fcf5ef2aSThomas Huth table = ind_table(handler); 7745b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 7746fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7747fcf5ef2aSThomas Huth table = ind_table(handler); 7748b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 7749fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7750fcf5ef2aSThomas Huth table = ind_table(handler); 7751b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 7752fcf5ef2aSThomas Huth } 7753fcf5ef2aSThomas Huth } 7754fcf5ef2aSThomas Huth } 7755fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7756fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7757fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7758fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7759fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7760b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7761b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7762b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7763fcf5ef2aSThomas Huth } else { 7764fcf5ef2aSThomas Huth uint32_t inval; 7765fcf5ef2aSThomas Huth 7766b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7767b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 7768fcf5ef2aSThomas Huth inval = handler->inval2; 7769fcf5ef2aSThomas Huth } else { 7770fcf5ef2aSThomas Huth inval = handler->inval1; 7771fcf5ef2aSThomas Huth } 7772fcf5ef2aSThomas Huth 7773b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 7774fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7775fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7776b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 7777b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7778b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7779b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4); 7780b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7781b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 7782b0c2d521SEmilio G. Cota return; 7783fcf5ef2aSThomas Huth } 7784fcf5ef2aSThomas Huth } 7785b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 7786fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7787fcf5ef2aSThomas Huth handler->count++; 7788fcf5ef2aSThomas Huth #endif 7789fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7790b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7791b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7792b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 7793b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 7794b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 77950e3bf489SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_TRACE); 77960e3bf489SRoman Kapl if (excp != POWERPC_EXCP_NONE) 77970e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 7798fcf5ef2aSThomas Huth } 7799b0c2d521SEmilio G. Cota 7800fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7801b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7802b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7803b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7804fcf5ef2aSThomas Huth } 7805b0c2d521SEmilio G. Cota 7806b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7807b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 7808fcf5ef2aSThomas Huth } 7809b0c2d521SEmilio G. Cota 7810b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7811b0c2d521SEmilio G. Cota { 7812b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7813b0c2d521SEmilio G. Cota 7814b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 7815b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 7816b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7817b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7818b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 7819fcf5ef2aSThomas Huth } 7820fcf5ef2aSThomas Huth /* Generate the return instruction */ 782107ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7822fcf5ef2aSThomas Huth } 7823fcf5ef2aSThomas Huth } 7824b0c2d521SEmilio G. Cota 7825b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7826b0c2d521SEmilio G. Cota { 7827b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7828b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7829b0c2d521SEmilio G. Cota } 7830b0c2d521SEmilio G. Cota 7831b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7832b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7833b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7834b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7835b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 7836b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7837b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7838b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7839b0c2d521SEmilio G. Cota }; 7840b0c2d521SEmilio G. Cota 7841b0c2d521SEmilio G. Cota void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 7842b0c2d521SEmilio G. Cota { 7843b0c2d521SEmilio G. Cota DisasContext ctx; 7844b0c2d521SEmilio G. Cota 7845b0c2d521SEmilio G. Cota translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); 7846fcf5ef2aSThomas Huth } 7847fcf5ef2aSThomas Huth 7848fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7849fcf5ef2aSThomas Huth target_ulong *data) 7850fcf5ef2aSThomas Huth { 7851fcf5ef2aSThomas Huth env->nip = data[0]; 7852fcf5ef2aSThomas Huth } 7853