1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 38a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 39fcf5ef2aSThomas Huth 403e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 413e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 44fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 47efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 1572c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 158fcf5ef2aSThomas Huth uint32_t opcode; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 1771db3632aSMatheus Ferst bool hr; 178f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 179f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 180*46d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 189a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 190a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 191a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 192a9b5b3d0SRichard Henderson 193fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 194fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 197fcf5ef2aSThomas Huth return ctx->le_mode; 198fcf5ef2aSThomas Huth #else 199fcf5ef2aSThomas Huth return !ctx->le_mode; 200fcf5ef2aSThomas Huth #endif 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 204fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 206fcf5ef2aSThomas Huth #else 207fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 208fcf5ef2aSThomas Huth #endif 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth struct opc_handler_t { 211fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 212fcf5ef2aSThomas Huth uint32_t inval1; 213fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 214fcf5ef2aSThomas Huth uint32_t inval2; 215fcf5ef2aSThomas Huth /* instruction type */ 216fcf5ef2aSThomas Huth uint64_t type; 217fcf5ef2aSThomas Huth /* extended instruction type */ 218fcf5ef2aSThomas Huth uint64_t type2; 219fcf5ef2aSThomas Huth /* handler */ 220fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 221fcf5ef2aSThomas Huth }; 222fcf5ef2aSThomas Huth 2230e3bf489SRoman Kapl /* SPR load/store helpers */ 2240e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2250e3bf489SRoman Kapl { 2260e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2270e3bf489SRoman Kapl } 2280e3bf489SRoman Kapl 2290e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2300e3bf489SRoman Kapl { 2310e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2320e3bf489SRoman Kapl } 2330e3bf489SRoman Kapl 234fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 235fcf5ef2aSThomas Huth { 236fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 237fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 238fcf5ef2aSThomas Huth ctx->access_type = access_type; 239fcf5ef2aSThomas Huth } 240fcf5ef2aSThomas Huth } 241fcf5ef2aSThomas Huth 242fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 243fcf5ef2aSThomas Huth { 244fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 245fcf5ef2aSThomas Huth nip = (uint32_t)nip; 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 248fcf5ef2aSThomas Huth } 249fcf5ef2aSThomas Huth 250fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 251fcf5ef2aSThomas Huth { 252fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 253fcf5ef2aSThomas Huth 254efe843d8SDavid Gibson /* 255efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 256efe843d8SDavid Gibson * faulting instruction 257fcf5ef2aSThomas Huth */ 2582c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 259fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 260fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 261fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 262fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 263fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2643d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 265fcf5ef2aSThomas Huth } 266fcf5ef2aSThomas Huth 267fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 268fcf5ef2aSThomas Huth { 269fcf5ef2aSThomas Huth TCGv_i32 t0; 270fcf5ef2aSThomas Huth 271efe843d8SDavid Gibson /* 272efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 273efe843d8SDavid Gibson * faulting instruction 274fcf5ef2aSThomas Huth */ 2752c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 276fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 277fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 278fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2793d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth 282fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 283fcf5ef2aSThomas Huth target_ulong nip) 284fcf5ef2aSThomas Huth { 285fcf5ef2aSThomas Huth TCGv_i32 t0; 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 288fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 289fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 290fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2913d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 292fcf5ef2aSThomas Huth } 293fcf5ef2aSThomas Huth 294f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 295f5b6daacSRichard Henderson { 296f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 297f5b6daacSRichard Henderson gen_io_start(); 298f5b6daacSRichard Henderson /* 299f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 300f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 301f5b6daacSRichard Henderson * decide if we need to return to the main loop. 302f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 303f5b6daacSRichard Henderson */ 304f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 305f5b6daacSRichard Henderson } 306f5b6daacSRichard Henderson } 307f5b6daacSRichard Henderson 308e150ac89SRoman Kapl /* 309e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 310e150ac89SRoman Kapl * SPR registers for this exception. 311e150ac89SRoman Kapl * 312e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 313e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3140e3bf489SRoman Kapl */ 315e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3160e3bf489SRoman Kapl { 3170e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3180e3bf489SRoman Kapl target_ulong dbsr = 0; 319e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3200e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 321e150ac89SRoman Kapl } else { 322e150ac89SRoman Kapl /* Must have been branch */ 3230e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3240e3bf489SRoman Kapl } 3250e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3260e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3270e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3280e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3290e3bf489SRoman Kapl tcg_temp_free(t0); 3300e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3310e3bf489SRoman Kapl } else { 332e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3330e3bf489SRoman Kapl } 3340e3bf489SRoman Kapl } 3350e3bf489SRoman Kapl 336fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 337fcf5ef2aSThomas Huth { 3389498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3393d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 340fcf5ef2aSThomas Huth } 341fcf5ef2aSThomas Huth 342fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 343fcf5ef2aSThomas Huth { 344fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 345fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 346fcf5ef2aSThomas Huth } 347fcf5ef2aSThomas Huth 348fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 353fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 354fcf5ef2aSThomas Huth { 355fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 356fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 357fcf5ef2aSThomas Huth } 358fcf5ef2aSThomas Huth 35937f219c8SBruno Larsen (billionai) /*****************************************************************************/ 36037f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 36137f219c8SBruno Larsen (billionai) 362a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36337f219c8SBruno Larsen (billionai) { 36437f219c8SBruno Larsen (billionai) #if 0 36537f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36637f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36737f219c8SBruno Larsen (billionai) #endif 36837f219c8SBruno Larsen (billionai) } 36937f219c8SBruno Larsen (billionai) 37037f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 37137f219c8SBruno Larsen (billionai) 37237f219c8SBruno Larsen (billionai) /* 37337f219c8SBruno Larsen (billionai) * Generic callbacks: 37437f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37537f219c8SBruno Larsen (billionai) */ 37637f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37737f219c8SBruno Larsen (billionai) { 37837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 38037f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 38137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38237f219c8SBruno Larsen (billionai) #endif 38337f219c8SBruno Larsen (billionai) } 38437f219c8SBruno Larsen (billionai) 385a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38637f219c8SBruno Larsen (billionai) { 38737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38937f219c8SBruno Larsen (billionai) } 39037f219c8SBruno Larsen (billionai) 39137f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39237f219c8SBruno Larsen (billionai) { 39337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39537f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39737f219c8SBruno Larsen (billionai) #endif 39837f219c8SBruno Larsen (billionai) } 39937f219c8SBruno Larsen (billionai) 400a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 40137f219c8SBruno Larsen (billionai) { 40237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40437f219c8SBruno Larsen (billionai) } 40537f219c8SBruno Larsen (billionai) 40637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 407a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 40837f219c8SBruno Larsen (billionai) { 40937f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 41037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 41137f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 41237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 41337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 41437f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41537f219c8SBruno Larsen (billionai) #else 41637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 41737f219c8SBruno Larsen (billionai) #endif 41837f219c8SBruno Larsen (billionai) } 41937f219c8SBruno Larsen (billionai) 420a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 42137f219c8SBruno Larsen (billionai) { 42237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42337f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 42437f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 42537f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 42637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 42737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 43037f219c8SBruno Larsen (billionai) } 43137f219c8SBruno Larsen (billionai) 432a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 43337f219c8SBruno Larsen (billionai) { 43437f219c8SBruno Larsen (billionai) } 43537f219c8SBruno Larsen (billionai) 43637f219c8SBruno Larsen (billionai) #endif 43737f219c8SBruno Larsen (billionai) 43837f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 43937f219c8SBruno Larsen (billionai) /* XER */ 440a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 44137f219c8SBruno Larsen (billionai) { 44237f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 44337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 44637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 44737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 44837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 44937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 45037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 45137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 45237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45337f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 45437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 45537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 45737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45837f219c8SBruno Larsen (billionai) } 45937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 46037f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 46137f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 46237f219c8SBruno Larsen (billionai) } 46337f219c8SBruno Larsen (billionai) 464a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 46537f219c8SBruno Larsen (billionai) { 46637f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 46737f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 46837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 46937f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 47037f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 47137f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 47237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 47337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 47437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 47537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 47637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 47737f219c8SBruno Larsen (billionai) } 47837f219c8SBruno Larsen (billionai) 47937f219c8SBruno Larsen (billionai) /* LR */ 480a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 48137f219c8SBruno Larsen (billionai) { 48237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 48337f219c8SBruno Larsen (billionai) } 48437f219c8SBruno Larsen (billionai) 485a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 48637f219c8SBruno Larsen (billionai) { 48737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 48837f219c8SBruno Larsen (billionai) } 48937f219c8SBruno Larsen (billionai) 49037f219c8SBruno Larsen (billionai) /* CFAR */ 49137f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 492a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 49337f219c8SBruno Larsen (billionai) { 49437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 49537f219c8SBruno Larsen (billionai) } 49637f219c8SBruno Larsen (billionai) 497a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 49837f219c8SBruno Larsen (billionai) { 49937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 50037f219c8SBruno Larsen (billionai) } 50137f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 50237f219c8SBruno Larsen (billionai) 50337f219c8SBruno Larsen (billionai) /* CTR */ 504a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 50537f219c8SBruno Larsen (billionai) { 50637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 50737f219c8SBruno Larsen (billionai) } 50837f219c8SBruno Larsen (billionai) 509a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 51037f219c8SBruno Larsen (billionai) { 51137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 51237f219c8SBruno Larsen (billionai) } 51337f219c8SBruno Larsen (billionai) 51437f219c8SBruno Larsen (billionai) /* User read access to SPR */ 51537f219c8SBruno Larsen (billionai) /* USPRx */ 51637f219c8SBruno Larsen (billionai) /* UMMCRx */ 51737f219c8SBruno Larsen (billionai) /* UPMCx */ 51837f219c8SBruno Larsen (billionai) /* USIA */ 51937f219c8SBruno Larsen (billionai) /* UDECR */ 520a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 52137f219c8SBruno Larsen (billionai) { 52237f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 52337f219c8SBruno Larsen (billionai) } 52437f219c8SBruno Larsen (billionai) 52537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 526a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 52737f219c8SBruno Larsen (billionai) { 52837f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 52937f219c8SBruno Larsen (billionai) } 53037f219c8SBruno Larsen (billionai) #endif 53137f219c8SBruno Larsen (billionai) 53237f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 53337f219c8SBruno Larsen (billionai) /* DECR */ 53437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 535a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 53637f219c8SBruno Larsen (billionai) { 537f5b6daacSRichard Henderson gen_icount_io_start(ctx); 53837f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 53937f219c8SBruno Larsen (billionai) } 54037f219c8SBruno Larsen (billionai) 541a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 54237f219c8SBruno Larsen (billionai) { 543f5b6daacSRichard Henderson gen_icount_io_start(ctx); 54437f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 54537f219c8SBruno Larsen (billionai) } 54637f219c8SBruno Larsen (billionai) #endif 54737f219c8SBruno Larsen (billionai) 54837f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 54937f219c8SBruno Larsen (billionai) /* Time base */ 550a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 55137f219c8SBruno Larsen (billionai) { 552f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55337f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 55437f219c8SBruno Larsen (billionai) } 55537f219c8SBruno Larsen (billionai) 556a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 55737f219c8SBruno Larsen (billionai) { 558f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55937f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 56037f219c8SBruno Larsen (billionai) } 56137f219c8SBruno Larsen (billionai) 562a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 56337f219c8SBruno Larsen (billionai) { 56437f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 56537f219c8SBruno Larsen (billionai) } 56637f219c8SBruno Larsen (billionai) 567a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 56837f219c8SBruno Larsen (billionai) { 56937f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 57037f219c8SBruno Larsen (billionai) } 57137f219c8SBruno Larsen (billionai) 57237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 573a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 57437f219c8SBruno Larsen (billionai) { 575f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57637f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 57737f219c8SBruno Larsen (billionai) } 57837f219c8SBruno Larsen (billionai) 579a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 58037f219c8SBruno Larsen (billionai) { 581f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58237f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 58337f219c8SBruno Larsen (billionai) } 58437f219c8SBruno Larsen (billionai) 585a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 58637f219c8SBruno Larsen (billionai) { 58737f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 58837f219c8SBruno Larsen (billionai) } 58937f219c8SBruno Larsen (billionai) 590a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 59137f219c8SBruno Larsen (billionai) { 59237f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 59337f219c8SBruno Larsen (billionai) } 59437f219c8SBruno Larsen (billionai) 59537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 596a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 59737f219c8SBruno Larsen (billionai) { 598f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59937f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 60037f219c8SBruno Larsen (billionai) } 60137f219c8SBruno Larsen (billionai) 602a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 60337f219c8SBruno Larsen (billionai) { 604f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60537f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 60637f219c8SBruno Larsen (billionai) } 60737f219c8SBruno Larsen (billionai) 60837f219c8SBruno Larsen (billionai) /* HDECR */ 609a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 61037f219c8SBruno Larsen (billionai) { 611f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61237f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 61337f219c8SBruno Larsen (billionai) } 61437f219c8SBruno Larsen (billionai) 615a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 61637f219c8SBruno Larsen (billionai) { 617f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61837f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 61937f219c8SBruno Larsen (billionai) } 62037f219c8SBruno Larsen (billionai) 621a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 62237f219c8SBruno Larsen (billionai) { 623f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62437f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 62537f219c8SBruno Larsen (billionai) } 62637f219c8SBruno Larsen (billionai) 627a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 62837f219c8SBruno Larsen (billionai) { 629f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63037f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 63137f219c8SBruno Larsen (billionai) } 63237f219c8SBruno Larsen (billionai) 633a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 63437f219c8SBruno Larsen (billionai) { 635f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63637f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 63737f219c8SBruno Larsen (billionai) } 63837f219c8SBruno Larsen (billionai) 63937f219c8SBruno Larsen (billionai) #endif 64037f219c8SBruno Larsen (billionai) #endif 64137f219c8SBruno Larsen (billionai) 64237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 64337f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 64437f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 645a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 64637f219c8SBruno Larsen (billionai) { 64737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 64837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 64937f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 65037f219c8SBruno Larsen (billionai) } 65137f219c8SBruno Larsen (billionai) 652a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 65337f219c8SBruno Larsen (billionai) { 65437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 65537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 65637f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 65737f219c8SBruno Larsen (billionai) } 65837f219c8SBruno Larsen (billionai) 659a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 66037f219c8SBruno Larsen (billionai) { 66137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 66237f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66437f219c8SBruno Larsen (billionai) } 66537f219c8SBruno Larsen (billionai) 666a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 66737f219c8SBruno Larsen (billionai) { 66837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 66937f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 67037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67137f219c8SBruno Larsen (billionai) } 67237f219c8SBruno Larsen (billionai) 673a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 67437f219c8SBruno Larsen (billionai) { 67537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 67637f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 67737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67837f219c8SBruno Larsen (billionai) } 67937f219c8SBruno Larsen (billionai) 680a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 68137f219c8SBruno Larsen (billionai) { 68237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 68337f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68537f219c8SBruno Larsen (billionai) } 68637f219c8SBruno Larsen (billionai) 68737f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 68837f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 689a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 69037f219c8SBruno Larsen (billionai) { 69137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69337f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 69437f219c8SBruno Larsen (billionai) } 69537f219c8SBruno Larsen (billionai) 696a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 69737f219c8SBruno Larsen (billionai) { 69837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70037f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 70137f219c8SBruno Larsen (billionai) } 70237f219c8SBruno Larsen (billionai) 703a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 70437f219c8SBruno Larsen (billionai) { 70537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 70637f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 70737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70837f219c8SBruno Larsen (billionai) } 70937f219c8SBruno Larsen (billionai) 710a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 71137f219c8SBruno Larsen (billionai) { 71237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 71337f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71537f219c8SBruno Larsen (billionai) } 71637f219c8SBruno Larsen (billionai) 717a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 71837f219c8SBruno Larsen (billionai) { 71937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 72037f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72237f219c8SBruno Larsen (billionai) } 72337f219c8SBruno Larsen (billionai) 724a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 72537f219c8SBruno Larsen (billionai) { 72637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 72737f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72937f219c8SBruno Larsen (billionai) } 73037f219c8SBruno Larsen (billionai) 73137f219c8SBruno Larsen (billionai) /* SDR1 */ 732a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 73337f219c8SBruno Larsen (billionai) { 73437f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 73537f219c8SBruno Larsen (billionai) } 73637f219c8SBruno Larsen (billionai) 73737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 73837f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 73937f219c8SBruno Larsen (billionai) /* PIDR */ 740a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 74137f219c8SBruno Larsen (billionai) { 74237f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 74337f219c8SBruno Larsen (billionai) } 74437f219c8SBruno Larsen (billionai) 745a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 74637f219c8SBruno Larsen (billionai) { 74737f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 74837f219c8SBruno Larsen (billionai) } 74937f219c8SBruno Larsen (billionai) 750a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 75137f219c8SBruno Larsen (billionai) { 75237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 75337f219c8SBruno Larsen (billionai) } 75437f219c8SBruno Larsen (billionai) 755a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 75637f219c8SBruno Larsen (billionai) { 75737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 75837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 75937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 76037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 76137f219c8SBruno Larsen (billionai) } 762a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 76337f219c8SBruno Larsen (billionai) { 76437f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 76537f219c8SBruno Larsen (billionai) } 76637f219c8SBruno Larsen (billionai) 767a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 76837f219c8SBruno Larsen (billionai) { 76937f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 77237f219c8SBruno Larsen (billionai) /* DPDES */ 773a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 77437f219c8SBruno Larsen (billionai) { 77537f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 77637f219c8SBruno Larsen (billionai) } 77737f219c8SBruno Larsen (billionai) 778a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 77937f219c8SBruno Larsen (billionai) { 78037f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 78137f219c8SBruno Larsen (billionai) } 78237f219c8SBruno Larsen (billionai) #endif 78337f219c8SBruno Larsen (billionai) #endif 78437f219c8SBruno Larsen (billionai) 78537f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 78637f219c8SBruno Larsen (billionai) /* RTC */ 787a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 78837f219c8SBruno Larsen (billionai) { 78937f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 79037f219c8SBruno Larsen (billionai) } 79137f219c8SBruno Larsen (billionai) 792a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 79337f219c8SBruno Larsen (billionai) { 79437f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 79537f219c8SBruno Larsen (billionai) } 79637f219c8SBruno Larsen (billionai) 79737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 798a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 79937f219c8SBruno Larsen (billionai) { 80037f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 80137f219c8SBruno Larsen (billionai) } 80237f219c8SBruno Larsen (billionai) 803a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 80437f219c8SBruno Larsen (billionai) { 80537f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 80637f219c8SBruno Larsen (billionai) } 80737f219c8SBruno Larsen (billionai) 808a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 80937f219c8SBruno Larsen (billionai) { 81037f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 81137f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 812d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81337f219c8SBruno Larsen (billionai) } 81437f219c8SBruno Larsen (billionai) #endif 81537f219c8SBruno Larsen (billionai) 81637f219c8SBruno Larsen (billionai) /* Unified bats */ 81737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 818a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 81937f219c8SBruno Larsen (billionai) { 82037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 82137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 82237f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 82337f219c8SBruno Larsen (billionai) } 82437f219c8SBruno Larsen (billionai) 825a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 82637f219c8SBruno Larsen (billionai) { 82737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 82837f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 82937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 83037f219c8SBruno Larsen (billionai) } 83137f219c8SBruno Larsen (billionai) 832a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 83337f219c8SBruno Larsen (billionai) { 83437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 83537f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 83637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 83737f219c8SBruno Larsen (billionai) } 83837f219c8SBruno Larsen (billionai) #endif 83937f219c8SBruno Larsen (billionai) 84037f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 84137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 842a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 84337f219c8SBruno Larsen (billionai) { 844f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84537f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84637f219c8SBruno Larsen (billionai) } 84737f219c8SBruno Larsen (billionai) 848a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84937f219c8SBruno Larsen (billionai) { 850f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85137f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 85237f219c8SBruno Larsen (billionai) } 85337f219c8SBruno Larsen (billionai) 854a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85537f219c8SBruno Larsen (billionai) { 856f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85837f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85937f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 860d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 86137f219c8SBruno Larsen (billionai) } 86237f219c8SBruno Larsen (billionai) 863a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86437f219c8SBruno Larsen (billionai) { 865f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86637f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86737f219c8SBruno Larsen (billionai) } 86837f219c8SBruno Larsen (billionai) 869a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 87037f219c8SBruno Larsen (billionai) { 871f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87237f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 87337f219c8SBruno Larsen (billionai) } 87437f219c8SBruno Larsen (billionai) 875a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 87637f219c8SBruno Larsen (billionai) { 877f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87837f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 87937f219c8SBruno Larsen (billionai) } 88037f219c8SBruno Larsen (billionai) #endif 88137f219c8SBruno Larsen (billionai) 88237f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 88337f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 88437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 885a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 88637f219c8SBruno Larsen (billionai) { 88737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 88837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 88937f219c8SBruno Larsen (billionai) } 89037f219c8SBruno Larsen (billionai) 891a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 89237f219c8SBruno Larsen (billionai) { 89337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 89437f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 89537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89637f219c8SBruno Larsen (billionai) } 89737f219c8SBruno Larsen (billionai) 898a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 89937f219c8SBruno Larsen (billionai) { 90037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90437f219c8SBruno Larsen (billionai) } 90537f219c8SBruno Larsen (billionai) #endif 90637f219c8SBruno Larsen (billionai) 90737f219c8SBruno Larsen (billionai) /* SPE specific registers */ 908a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 90937f219c8SBruno Larsen (billionai) { 91037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91137f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91237f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91437f219c8SBruno Larsen (billionai) } 91537f219c8SBruno Larsen (billionai) 916a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91737f219c8SBruno Larsen (billionai) { 91837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91937f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 92037f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92237f219c8SBruno Larsen (billionai) } 92337f219c8SBruno Larsen (billionai) 92437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92537f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 926a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92737f219c8SBruno Larsen (billionai) { 92837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 93037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 93137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93437f219c8SBruno Larsen (billionai) } 93537f219c8SBruno Larsen (billionai) 936a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93737f219c8SBruno Larsen (billionai) { 93837f219c8SBruno Larsen (billionai) int sprn_offs; 93937f219c8SBruno Larsen (billionai) 94037f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 94137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 94237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94437f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94537f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94637f219c8SBruno Larsen (billionai) } else { 94737f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 94837f219c8SBruno Larsen (billionai) sprn, sprn); 94937f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 95037f219c8SBruno Larsen (billionai) return; 95137f219c8SBruno Larsen (billionai) } 95237f219c8SBruno Larsen (billionai) 95337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95637f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 95937f219c8SBruno Larsen (billionai) } 96037f219c8SBruno Larsen (billionai) #endif 96137f219c8SBruno Larsen (billionai) 96237f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 96337f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 964a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96537f219c8SBruno Larsen (billionai) { 96637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96937f219c8SBruno Larsen (billionai) 97037f219c8SBruno Larsen (billionai) /* 97137f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 97237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97337f219c8SBruno Larsen (billionai) */ 97437f219c8SBruno Larsen (billionai) 97537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97637f219c8SBruno Larsen (billionai) if (ctx->pr) { 97737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97837f219c8SBruno Larsen (billionai) } else { 97937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 98037f219c8SBruno Larsen (billionai) } 98137f219c8SBruno Larsen (billionai) 98237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98437f219c8SBruno Larsen (billionai) 98537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98837f219c8SBruno Larsen (billionai) 98937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 99037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 99137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 99237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 99337f219c8SBruno Larsen (billionai) 99437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 99537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 99637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 99737f219c8SBruno Larsen (billionai) } 99837f219c8SBruno Larsen (billionai) 999a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 100037f219c8SBruno Larsen (billionai) { 100137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100437f219c8SBruno Larsen (billionai) 100537f219c8SBruno Larsen (billionai) /* 100637f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100737f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100837f219c8SBruno Larsen (billionai) */ 100937f219c8SBruno Larsen (billionai) 101037f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 101137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101237f219c8SBruno Larsen (billionai) 101337f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101537f219c8SBruno Larsen (billionai) 101637f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101737f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101837f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101937f219c8SBruno Larsen (billionai) 102037f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 102137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 102337f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 102437f219c8SBruno Larsen (billionai) 102537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102637f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 102737f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 102837f219c8SBruno Larsen (billionai) } 102937f219c8SBruno Larsen (billionai) 1030a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 103137f219c8SBruno Larsen (billionai) { 103237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103337f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103437f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103537f219c8SBruno Larsen (billionai) 103637f219c8SBruno Larsen (billionai) /* 103737f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 103837f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 103937f219c8SBruno Larsen (billionai) */ 104037f219c8SBruno Larsen (billionai) 104137f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104237f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104337f219c8SBruno Larsen (billionai) 104437f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 104637f219c8SBruno Larsen (billionai) 104737f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 104837f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 104937f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 105037f219c8SBruno Larsen (billionai) 105137f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 105437f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 105537f219c8SBruno Larsen (billionai) 105637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 105837f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 105937f219c8SBruno Larsen (billionai) } 106037f219c8SBruno Larsen (billionai) #endif 106137f219c8SBruno Larsen (billionai) #endif 106237f219c8SBruno Larsen (billionai) 106337f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1064a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 106537f219c8SBruno Larsen (billionai) { 106637f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 106737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 106837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 106937f219c8SBruno Larsen (billionai) } 107037f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 107137f219c8SBruno Larsen (billionai) 107237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1073a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 107437f219c8SBruno Larsen (billionai) { 107537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107637f219c8SBruno Larsen (billionai) 107737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 107837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108037f219c8SBruno Larsen (billionai) } 108137f219c8SBruno Larsen (billionai) 1082a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 108337f219c8SBruno Larsen (billionai) { 108437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108537f219c8SBruno Larsen (billionai) 108637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 108737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108937f219c8SBruno Larsen (billionai) } 109037f219c8SBruno Larsen (billionai) 1091a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 109237f219c8SBruno Larsen (billionai) { 109337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109437f219c8SBruno Larsen (billionai) 109537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 109637f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 109737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109937f219c8SBruno Larsen (billionai) } 110037f219c8SBruno Larsen (billionai) 1101a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 110237f219c8SBruno Larsen (billionai) { 110337f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 110437f219c8SBruno Larsen (billionai) } 110537f219c8SBruno Larsen (billionai) 1106a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 110737f219c8SBruno Larsen (billionai) { 110837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 110937f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 111037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 111137f219c8SBruno Larsen (billionai) } 1112a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 111337f219c8SBruno Larsen (billionai) { 111437f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 111537f219c8SBruno Larsen (billionai) } 1116a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 111737f219c8SBruno Larsen (billionai) { 111837f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 111937f219c8SBruno Larsen (billionai) } 112037f219c8SBruno Larsen (billionai) 112137f219c8SBruno Larsen (billionai) #endif 112237f219c8SBruno Larsen (billionai) 112337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1124a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 112537f219c8SBruno Larsen (billionai) { 112637f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 112737f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 112837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 112937f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 113037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 113137f219c8SBruno Larsen (billionai) tcg_temp_free(val); 113237f219c8SBruno Larsen (billionai) } 113337f219c8SBruno Larsen (billionai) 1134a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 113537f219c8SBruno Larsen (billionai) { 113637f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 113737f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 113837f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 113937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 114037f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 114137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 114237f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 114337f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 114437f219c8SBruno Larsen (billionai) } 114537f219c8SBruno Larsen (billionai) 114637f219c8SBruno Larsen (billionai) #endif 114737f219c8SBruno Larsen (billionai) 114837f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 114937f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 115037f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 115137f219c8SBruno Larsen (billionai) { 115237f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 115337f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 115437f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 115537f219c8SBruno Larsen (billionai) 115637f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 115737f219c8SBruno Larsen (billionai) 115837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 115937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 116037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 116137f219c8SBruno Larsen (billionai) } 116237f219c8SBruno Larsen (billionai) 116337f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 116437f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116537f219c8SBruno Larsen (billionai) { 116637f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 116737f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 116837f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116937f219c8SBruno Larsen (billionai) 117037f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 117137f219c8SBruno Larsen (billionai) 117237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 117537f219c8SBruno Larsen (billionai) } 117637f219c8SBruno Larsen (billionai) 1177a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 117837f219c8SBruno Larsen (billionai) { 117937f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 118037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 118137f219c8SBruno Larsen (billionai) 118237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118337f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 118437f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 118537f219c8SBruno Larsen (billionai) 118637f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 118737f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 118837f219c8SBruno Larsen (billionai) } 118937f219c8SBruno Larsen (billionai) 1190a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 119137f219c8SBruno Larsen (billionai) { 119237f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119337f219c8SBruno Larsen (billionai) 119437f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119537f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 119637f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 119737f219c8SBruno Larsen (billionai) 119837f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 119937f219c8SBruno Larsen (billionai) } 120037f219c8SBruno Larsen (billionai) 120137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1202a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 120337f219c8SBruno Larsen (billionai) { 120437f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 120537f219c8SBruno Larsen (billionai) 120637f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 120737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 120837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 120937f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 121037f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 121137f219c8SBruno Larsen (billionai) } 121237f219c8SBruno Larsen (billionai) 1213a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 121437f219c8SBruno Larsen (billionai) { 121537f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 121637f219c8SBruno Larsen (billionai) } 121737f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 121837f219c8SBruno Larsen (billionai) 1219a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 122037f219c8SBruno Larsen (billionai) { 122137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122237f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122337f219c8SBruno Larsen (billionai) } 122437f219c8SBruno Larsen (billionai) 1225a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 122637f219c8SBruno Larsen (billionai) { 122737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 122937f219c8SBruno Larsen (billionai) } 123037f219c8SBruno Larsen (billionai) 1231a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 123237f219c8SBruno Larsen (billionai) { 123337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123437f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123537f219c8SBruno Larsen (billionai) } 123637f219c8SBruno Larsen (billionai) 1237a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 123837f219c8SBruno Larsen (billionai) { 123937f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124037f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124137f219c8SBruno Larsen (billionai) } 124237f219c8SBruno Larsen (billionai) 1243a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 124437f219c8SBruno Larsen (billionai) { 124537f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124637f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124737f219c8SBruno Larsen (billionai) } 124837f219c8SBruno Larsen (billionai) 1249a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 125037f219c8SBruno Larsen (billionai) { 125137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125237f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125337f219c8SBruno Larsen (billionai) } 125437f219c8SBruno Larsen (billionai) 1255a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 125637f219c8SBruno Larsen (billionai) { 125737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125837f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125937f219c8SBruno Larsen (billionai) } 126037f219c8SBruno Larsen (billionai) 1261a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 126237f219c8SBruno Larsen (billionai) { 126337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126437f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126537f219c8SBruno Larsen (billionai) } 126637f219c8SBruno Larsen (billionai) 1267a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 126837f219c8SBruno Larsen (billionai) { 126937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127037f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 127137f219c8SBruno Larsen (billionai) } 127237f219c8SBruno Larsen (billionai) 1273a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 127437f219c8SBruno Larsen (billionai) { 127537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127637f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 127737f219c8SBruno Larsen (billionai) } 127837f219c8SBruno Larsen (billionai) #endif 127937f219c8SBruno Larsen (billionai) 1280fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1281fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1282fcf5ef2aSThomas Huth 1283fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1284fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1285fcf5ef2aSThomas Huth 1286fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1287fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1288fcf5ef2aSThomas Huth 1289fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1290fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1291fcf5ef2aSThomas Huth 1292fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1293fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1294fcf5ef2aSThomas Huth 1295fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1296fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1297fcf5ef2aSThomas Huth 1298fcf5ef2aSThomas Huth typedef struct opcode_t { 1299fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1300fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1301fcf5ef2aSThomas Huth unsigned char pad[4]; 1302fcf5ef2aSThomas Huth #endif 1303fcf5ef2aSThomas Huth opc_handler_t handler; 1304fcf5ef2aSThomas Huth const char *oname; 1305fcf5ef2aSThomas Huth } opcode_t; 1306fcf5ef2aSThomas Huth 1307fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1308fcf5ef2aSThomas Huth #define GEN_PRIV \ 1309fcf5ef2aSThomas Huth do { \ 1310fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1311fcf5ef2aSThomas Huth } while (0) 1312fcf5ef2aSThomas Huth 1313fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1314fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1315fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1316fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1317fcf5ef2aSThomas Huth #else 1318fcf5ef2aSThomas Huth #define CHK_HV \ 1319fcf5ef2aSThomas Huth do { \ 1320fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1321fcf5ef2aSThomas Huth GEN_PRIV; \ 1322fcf5ef2aSThomas Huth } \ 1323fcf5ef2aSThomas Huth } while (0) 1324fcf5ef2aSThomas Huth #define CHK_SV \ 1325fcf5ef2aSThomas Huth do { \ 1326fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1327fcf5ef2aSThomas Huth GEN_PRIV; \ 1328fcf5ef2aSThomas Huth } \ 1329fcf5ef2aSThomas Huth } while (0) 1330fcf5ef2aSThomas Huth #define CHK_HVRM \ 1331fcf5ef2aSThomas Huth do { \ 1332fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1333fcf5ef2aSThomas Huth GEN_PRIV; \ 1334fcf5ef2aSThomas Huth } \ 1335fcf5ef2aSThomas Huth } while (0) 1336fcf5ef2aSThomas Huth #endif 1337fcf5ef2aSThomas Huth 1338fcf5ef2aSThomas Huth #define CHK_NONE 1339fcf5ef2aSThomas Huth 1340fcf5ef2aSThomas Huth /*****************************************************************************/ 1341fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1342fcf5ef2aSThomas Huth 1343fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1344fcf5ef2aSThomas Huth { \ 1345fcf5ef2aSThomas Huth .opc1 = op1, \ 1346fcf5ef2aSThomas Huth .opc2 = op2, \ 1347fcf5ef2aSThomas Huth .opc3 = op3, \ 1348fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1349fcf5ef2aSThomas Huth .handler = { \ 1350fcf5ef2aSThomas Huth .inval1 = invl, \ 1351fcf5ef2aSThomas Huth .type = _typ, \ 1352fcf5ef2aSThomas Huth .type2 = _typ2, \ 1353fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1354fcf5ef2aSThomas Huth }, \ 1355fcf5ef2aSThomas Huth .oname = stringify(name), \ 1356fcf5ef2aSThomas Huth } 1357fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1358fcf5ef2aSThomas Huth { \ 1359fcf5ef2aSThomas Huth .opc1 = op1, \ 1360fcf5ef2aSThomas Huth .opc2 = op2, \ 1361fcf5ef2aSThomas Huth .opc3 = op3, \ 1362fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1363fcf5ef2aSThomas Huth .handler = { \ 1364fcf5ef2aSThomas Huth .inval1 = invl1, \ 1365fcf5ef2aSThomas Huth .inval2 = invl2, \ 1366fcf5ef2aSThomas Huth .type = _typ, \ 1367fcf5ef2aSThomas Huth .type2 = _typ2, \ 1368fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1369fcf5ef2aSThomas Huth }, \ 1370fcf5ef2aSThomas Huth .oname = stringify(name), \ 1371fcf5ef2aSThomas Huth } 1372fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1373fcf5ef2aSThomas Huth { \ 1374fcf5ef2aSThomas Huth .opc1 = op1, \ 1375fcf5ef2aSThomas Huth .opc2 = op2, \ 1376fcf5ef2aSThomas Huth .opc3 = op3, \ 1377fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1378fcf5ef2aSThomas Huth .handler = { \ 1379fcf5ef2aSThomas Huth .inval1 = invl, \ 1380fcf5ef2aSThomas Huth .type = _typ, \ 1381fcf5ef2aSThomas Huth .type2 = _typ2, \ 1382fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1383fcf5ef2aSThomas Huth }, \ 1384fcf5ef2aSThomas Huth .oname = onam, \ 1385fcf5ef2aSThomas Huth } 1386fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1387fcf5ef2aSThomas Huth { \ 1388fcf5ef2aSThomas Huth .opc1 = op1, \ 1389fcf5ef2aSThomas Huth .opc2 = op2, \ 1390fcf5ef2aSThomas Huth .opc3 = op3, \ 1391fcf5ef2aSThomas Huth .opc4 = op4, \ 1392fcf5ef2aSThomas Huth .handler = { \ 1393fcf5ef2aSThomas Huth .inval1 = invl, \ 1394fcf5ef2aSThomas Huth .type = _typ, \ 1395fcf5ef2aSThomas Huth .type2 = _typ2, \ 1396fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1397fcf5ef2aSThomas Huth }, \ 1398fcf5ef2aSThomas Huth .oname = stringify(name), \ 1399fcf5ef2aSThomas Huth } 1400fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1401fcf5ef2aSThomas Huth { \ 1402fcf5ef2aSThomas Huth .opc1 = op1, \ 1403fcf5ef2aSThomas Huth .opc2 = op2, \ 1404fcf5ef2aSThomas Huth .opc3 = op3, \ 1405fcf5ef2aSThomas Huth .opc4 = op4, \ 1406fcf5ef2aSThomas Huth .handler = { \ 1407fcf5ef2aSThomas Huth .inval1 = invl, \ 1408fcf5ef2aSThomas Huth .type = _typ, \ 1409fcf5ef2aSThomas Huth .type2 = _typ2, \ 1410fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1411fcf5ef2aSThomas Huth }, \ 1412fcf5ef2aSThomas Huth .oname = onam, \ 1413fcf5ef2aSThomas Huth } 1414fcf5ef2aSThomas Huth 1415fcf5ef2aSThomas Huth /* Invalid instruction */ 1416fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1417fcf5ef2aSThomas Huth { 1418fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1419fcf5ef2aSThomas Huth } 1420fcf5ef2aSThomas Huth 1421fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1422fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1423fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1424fcf5ef2aSThomas Huth .type = PPC_NONE, 1425fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1426fcf5ef2aSThomas Huth .handler = gen_invalid, 1427fcf5ef2aSThomas Huth }; 1428fcf5ef2aSThomas Huth 1429fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1430fcf5ef2aSThomas Huth 1431fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1432fcf5ef2aSThomas Huth { 1433fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1434b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1435b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1436fcf5ef2aSThomas Huth 1437b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1438b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1439efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1440efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1441b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1442efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1443efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1444b62b3686Spbonzini@redhat.com 1445b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1446fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1447b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1448fcf5ef2aSThomas Huth 1449fcf5ef2aSThomas Huth tcg_temp_free(t0); 1450b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1451b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1452fcf5ef2aSThomas Huth } 1453fcf5ef2aSThomas Huth 1454fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1455fcf5ef2aSThomas Huth { 1456fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1457fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1458fcf5ef2aSThomas Huth tcg_temp_free(t0); 1459fcf5ef2aSThomas Huth } 1460fcf5ef2aSThomas Huth 1461fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1462fcf5ef2aSThomas Huth { 1463fcf5ef2aSThomas Huth TCGv t0, t1; 1464fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1465fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1466fcf5ef2aSThomas Huth if (s) { 1467fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1468fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1469fcf5ef2aSThomas Huth } else { 1470fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1471fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1472fcf5ef2aSThomas Huth } 1473fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1474fcf5ef2aSThomas Huth tcg_temp_free(t1); 1475fcf5ef2aSThomas Huth tcg_temp_free(t0); 1476fcf5ef2aSThomas Huth } 1477fcf5ef2aSThomas Huth 1478fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1479fcf5ef2aSThomas Huth { 1480fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1481fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1482fcf5ef2aSThomas Huth tcg_temp_free(t0); 1483fcf5ef2aSThomas Huth } 1484fcf5ef2aSThomas Huth 1485fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1486fcf5ef2aSThomas Huth { 1487fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1488fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1489fcf5ef2aSThomas Huth } else { 1490fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1491fcf5ef2aSThomas Huth } 1492fcf5ef2aSThomas Huth } 1493fcf5ef2aSThomas Huth 1494fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1495fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1496fcf5ef2aSThomas Huth { 1497fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1498fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1499fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1500fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1501fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1502fcf5ef2aSThomas Huth 1503fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1504fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1505fcf5ef2aSThomas Huth 1506fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1507fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1508fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1509fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1510fcf5ef2aSThomas Huth 1511fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1512fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1513fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1514fcf5ef2aSThomas Huth 1515fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1516fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1517fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1518fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1519fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1520fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1521fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1522fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1523fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1524fcf5ef2aSThomas Huth } 1525efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1526fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1527fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1528fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1529fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1530fcf5ef2aSThomas Huth } 1531fcf5ef2aSThomas Huth 1532fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1533fcf5ef2aSThomas Huth /* cmpeqb */ 1534fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1535fcf5ef2aSThomas Huth { 1536fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1537fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1538fcf5ef2aSThomas Huth } 1539fcf5ef2aSThomas Huth #endif 1540fcf5ef2aSThomas Huth 1541fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1542fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1543fcf5ef2aSThomas Huth { 1544fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1545fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1546fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1547fcf5ef2aSThomas Huth TCGv zr; 1548fcf5ef2aSThomas Huth 1549fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1550fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1551fcf5ef2aSThomas Huth 1552fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1553fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1554fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1555fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1556fcf5ef2aSThomas Huth tcg_temp_free(zr); 1557fcf5ef2aSThomas Huth tcg_temp_free(t0); 1558fcf5ef2aSThomas Huth } 1559fcf5ef2aSThomas Huth 1560fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1561fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1562fcf5ef2aSThomas Huth { 1563fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1564fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1565fcf5ef2aSThomas Huth } 1566fcf5ef2aSThomas Huth 1567fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1568fcf5ef2aSThomas Huth 1569fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1570fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1571fcf5ef2aSThomas Huth { 1572fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1573fcf5ef2aSThomas Huth 1574fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1575fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1576fcf5ef2aSThomas Huth if (sub) { 1577fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1578fcf5ef2aSThomas Huth } else { 1579fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1580fcf5ef2aSThomas Huth } 1581fcf5ef2aSThomas Huth tcg_temp_free(t0); 1582fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1583dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1584dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1585dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1586fcf5ef2aSThomas Huth } 1587dc0ad844SNikunj A Dadhania } else { 1588dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1589dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1590dc0ad844SNikunj A Dadhania } 159138a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1592dc0ad844SNikunj A Dadhania } 1593fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1594fcf5ef2aSThomas Huth } 1595fcf5ef2aSThomas Huth 15966b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15976b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15984c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15996b10d008SNikunj A Dadhania { 16006b10d008SNikunj A Dadhania TCGv t0; 16016b10d008SNikunj A Dadhania 16026b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16036b10d008SNikunj A Dadhania return; 16046b10d008SNikunj A Dadhania } 16056b10d008SNikunj A Dadhania 16066b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 160733903d0aSNikunj A Dadhania if (sub) { 160833903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 160933903d0aSNikunj A Dadhania } else { 16106b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 161133903d0aSNikunj A Dadhania } 16126b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16134c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16146b10d008SNikunj A Dadhania tcg_temp_free(t0); 16156b10d008SNikunj A Dadhania } 16166b10d008SNikunj A Dadhania 1617fcf5ef2aSThomas Huth /* Common add function */ 1618fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16194c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16204c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1621fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1622fcf5ef2aSThomas Huth { 1623fcf5ef2aSThomas Huth TCGv t0 = ret; 1624fcf5ef2aSThomas Huth 1625fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1626fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1627fcf5ef2aSThomas Huth } 1628fcf5ef2aSThomas Huth 1629fcf5ef2aSThomas Huth if (compute_ca) { 1630fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1631efe843d8SDavid Gibson /* 1632efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1633efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1634efe843d8SDavid Gibson * produce the carry into bit 32. 1635efe843d8SDavid Gibson */ 1636fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1637fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1638fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1639fcf5ef2aSThomas Huth if (add_ca) { 16404c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1641fcf5ef2aSThomas Huth } 16424c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1643fcf5ef2aSThomas Huth tcg_temp_free(t1); 16444c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16456b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16464c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16476b10d008SNikunj A Dadhania } 1648fcf5ef2aSThomas Huth } else { 1649fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1650fcf5ef2aSThomas Huth if (add_ca) { 16514c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16524c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1653fcf5ef2aSThomas Huth } else { 16544c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1655fcf5ef2aSThomas Huth } 16564c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1657fcf5ef2aSThomas Huth tcg_temp_free(zero); 1658fcf5ef2aSThomas Huth } 1659fcf5ef2aSThomas Huth } else { 1660fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1661fcf5ef2aSThomas Huth if (add_ca) { 16624c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1663fcf5ef2aSThomas Huth } 1664fcf5ef2aSThomas Huth } 1665fcf5ef2aSThomas Huth 1666fcf5ef2aSThomas Huth if (compute_ov) { 1667fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1668fcf5ef2aSThomas Huth } 1669fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1670fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1671fcf5ef2aSThomas Huth } 1672fcf5ef2aSThomas Huth 167311f4e8f8SRichard Henderson if (t0 != ret) { 1674fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1675fcf5ef2aSThomas Huth tcg_temp_free(t0); 1676fcf5ef2aSThomas Huth } 1677fcf5ef2aSThomas Huth } 1678fcf5ef2aSThomas Huth /* Add functions with two operands */ 16794c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1680fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1681fcf5ef2aSThomas Huth { \ 1682fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1683fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16844c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1685fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1686fcf5ef2aSThomas Huth } 1687fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16884c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1689fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1690fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1691fcf5ef2aSThomas Huth { \ 1692fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1693fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1694fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16954c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1696fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1697fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1698fcf5ef2aSThomas Huth } 1699fcf5ef2aSThomas Huth 1700fcf5ef2aSThomas Huth /* add add. addo addo. */ 17014c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17024c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1703fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17044c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17054c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1706fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17074c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17084c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1709fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17104c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17114c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17124c5920afSSuraj Jitindar Singh /* addex */ 17134c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1714fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17154c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17164c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1717fcf5ef2aSThomas Huth /* addic addic.*/ 1718fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1719fcf5ef2aSThomas Huth { 1720fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1721fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17224c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1723fcf5ef2aSThomas Huth tcg_temp_free(c); 1724fcf5ef2aSThomas Huth } 1725fcf5ef2aSThomas Huth 1726fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1727fcf5ef2aSThomas Huth { 1728fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1729fcf5ef2aSThomas Huth } 1730fcf5ef2aSThomas Huth 1731fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1732fcf5ef2aSThomas Huth { 1733fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1734fcf5ef2aSThomas Huth } 1735fcf5ef2aSThomas Huth 1736fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1737fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1738fcf5ef2aSThomas Huth { 1739fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1740fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1741fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1742fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1743fcf5ef2aSThomas Huth 1744fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1745fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1746fcf5ef2aSThomas Huth if (sign) { 1747fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1748fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1749fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1750fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1751fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1752fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1753fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1754fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1755fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1756fcf5ef2aSThomas Huth } else { 1757fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1758fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1759fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1760fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1761fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1762fcf5ef2aSThomas Huth } 1763fcf5ef2aSThomas Huth if (compute_ov) { 1764fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1765c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1766c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1767c44027ffSNikunj A Dadhania } 1768fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1769fcf5ef2aSThomas Huth } 1770fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1771fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1772fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1773fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1774fcf5ef2aSThomas Huth 1775efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1776fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1777fcf5ef2aSThomas Huth } 1778efe843d8SDavid Gibson } 1779fcf5ef2aSThomas Huth /* Div functions */ 1780fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1781fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1782fcf5ef2aSThomas Huth { \ 1783fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1784fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1785fcf5ef2aSThomas Huth sign, compute_ov); \ 1786fcf5ef2aSThomas Huth } 1787fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1788fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1789fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1790fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1791fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1792fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1793fcf5ef2aSThomas Huth 1794fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1795fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1796fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1797fcf5ef2aSThomas Huth { \ 1798fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1799fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1800fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1801fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1802fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1803fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1804fcf5ef2aSThomas Huth } \ 1805fcf5ef2aSThomas Huth } 1806fcf5ef2aSThomas Huth 1807fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1808fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1809fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1810fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1811fcf5ef2aSThomas Huth 1812fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1813fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1814fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1815fcf5ef2aSThomas Huth { 1816fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1817fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1818fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1819fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1820fcf5ef2aSThomas Huth 1821fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1822fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1823fcf5ef2aSThomas Huth if (sign) { 1824fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1825fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1826fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1827fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1828fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1829fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1830fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1831fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1832fcf5ef2aSThomas Huth } else { 1833fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1834fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1835fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1836fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1837fcf5ef2aSThomas Huth } 1838fcf5ef2aSThomas Huth if (compute_ov) { 1839fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1840c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1841c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1842c44027ffSNikunj A Dadhania } 1843fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1844fcf5ef2aSThomas Huth } 1845fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1846fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1847fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1848fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1849fcf5ef2aSThomas Huth 1850efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1851fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1852fcf5ef2aSThomas Huth } 1853efe843d8SDavid Gibson } 1854fcf5ef2aSThomas Huth 1855fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1856fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1857fcf5ef2aSThomas Huth { \ 1858fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1859fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1860fcf5ef2aSThomas Huth sign, compute_ov); \ 1861fcf5ef2aSThomas Huth } 1862c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1863fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1864fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1865c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1866fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1867fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1868fcf5ef2aSThomas Huth 1869fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1870fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1871fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1872fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1873fcf5ef2aSThomas Huth #endif 1874fcf5ef2aSThomas Huth 1875fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1876fcf5ef2aSThomas Huth TCGv arg2, int sign) 1877fcf5ef2aSThomas Huth { 1878fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1879fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1880fcf5ef2aSThomas Huth 1881fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1882fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1883fcf5ef2aSThomas Huth if (sign) { 1884fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1885fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1886fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1887fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1888fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1889fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1890fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1891fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1892fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1893fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1894fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1895fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1896fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1897fcf5ef2aSThomas Huth } else { 1898fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1899fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1900fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1901fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1902fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1903fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1904fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1905fcf5ef2aSThomas Huth } 1906fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1907fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1908fcf5ef2aSThomas Huth } 1909fcf5ef2aSThomas Huth 1910fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1911fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1912fcf5ef2aSThomas Huth { \ 1913fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1914fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1915fcf5ef2aSThomas Huth sign); \ 1916fcf5ef2aSThomas Huth } 1917fcf5ef2aSThomas Huth 1918fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1919fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1920fcf5ef2aSThomas Huth 1921fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1922fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1923fcf5ef2aSThomas Huth TCGv arg2, int sign) 1924fcf5ef2aSThomas Huth { 1925fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1926fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1927fcf5ef2aSThomas Huth 1928fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1929fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1930fcf5ef2aSThomas Huth if (sign) { 1931fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1932fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1933fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1934fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1935fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1936fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1937fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1938fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1939fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1940fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1941fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1942fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1943fcf5ef2aSThomas Huth } else { 1944fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1945fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1946fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1947fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1948fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1949fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1950fcf5ef2aSThomas Huth } 1951fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1952fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1953fcf5ef2aSThomas Huth } 1954fcf5ef2aSThomas Huth 1955fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1956fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1957fcf5ef2aSThomas Huth { \ 1958fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1959fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1960fcf5ef2aSThomas Huth sign); \ 1961fcf5ef2aSThomas Huth } 1962fcf5ef2aSThomas Huth 1963fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1964fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1965fcf5ef2aSThomas Huth #endif 1966fcf5ef2aSThomas Huth 1967fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1968fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1969fcf5ef2aSThomas Huth { 1970fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1971fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1972fcf5ef2aSThomas Huth 1973fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1974fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1975fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1976fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1977fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1978fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1979efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1980fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1981fcf5ef2aSThomas Huth } 1982efe843d8SDavid Gibson } 1983fcf5ef2aSThomas Huth 1984fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1985fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1986fcf5ef2aSThomas Huth { 1987fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1988fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1989fcf5ef2aSThomas Huth 1990fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1991fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1992fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1993fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1994fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1995fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1996efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1997fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1998fcf5ef2aSThomas Huth } 1999efe843d8SDavid Gibson } 2000fcf5ef2aSThomas Huth 2001fcf5ef2aSThomas Huth /* mullw mullw. */ 2002fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2003fcf5ef2aSThomas Huth { 2004fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2005fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2006fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2007fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2008fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2009fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2010fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2011fcf5ef2aSThomas Huth tcg_temp_free(t0); 2012fcf5ef2aSThomas Huth tcg_temp_free(t1); 2013fcf5ef2aSThomas Huth #else 2014fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2015fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2016fcf5ef2aSThomas Huth #endif 2017efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2018fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2019fcf5ef2aSThomas Huth } 2020efe843d8SDavid Gibson } 2021fcf5ef2aSThomas Huth 2022fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2023fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2024fcf5ef2aSThomas Huth { 2025fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2026fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2027fcf5ef2aSThomas Huth 2028fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2029fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2030fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2031fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2032fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2033fcf5ef2aSThomas Huth #else 2034fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2035fcf5ef2aSThomas Huth #endif 2036fcf5ef2aSThomas Huth 2037fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2038fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2039fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 204061aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 204161aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 204261aa9a69SNikunj A Dadhania } 2043fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2044fcf5ef2aSThomas Huth 2045fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2046fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2047efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2048fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2049fcf5ef2aSThomas Huth } 2050efe843d8SDavid Gibson } 2051fcf5ef2aSThomas Huth 2052fcf5ef2aSThomas Huth /* mulli */ 2053fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2054fcf5ef2aSThomas Huth { 2055fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2056fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2057fcf5ef2aSThomas Huth } 2058fcf5ef2aSThomas Huth 2059fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2060fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2061fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2062fcf5ef2aSThomas Huth { 2063fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2064fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2065fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2066fcf5ef2aSThomas Huth tcg_temp_free(lo); 2067fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2068fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2069fcf5ef2aSThomas Huth } 2070fcf5ef2aSThomas Huth } 2071fcf5ef2aSThomas Huth 2072fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2073fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2074fcf5ef2aSThomas Huth { 2075fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2076fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2077fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2078fcf5ef2aSThomas Huth tcg_temp_free(lo); 2079fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2080fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2081fcf5ef2aSThomas Huth } 2082fcf5ef2aSThomas Huth } 2083fcf5ef2aSThomas Huth 2084fcf5ef2aSThomas Huth /* mulld mulld. */ 2085fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2086fcf5ef2aSThomas Huth { 2087fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2088fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2089efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2090fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2091fcf5ef2aSThomas Huth } 2092efe843d8SDavid Gibson } 2093fcf5ef2aSThomas Huth 2094fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2095fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2096fcf5ef2aSThomas Huth { 2097fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2098fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2099fcf5ef2aSThomas Huth 2100fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2101fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2102fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2103fcf5ef2aSThomas Huth 2104fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2105fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 210661aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 210761aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 210861aa9a69SNikunj A Dadhania } 2109fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2110fcf5ef2aSThomas Huth 2111fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2112fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2113fcf5ef2aSThomas Huth 2114fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2115fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2116fcf5ef2aSThomas Huth } 2117fcf5ef2aSThomas Huth } 2118fcf5ef2aSThomas Huth #endif 2119fcf5ef2aSThomas Huth 2120fcf5ef2aSThomas Huth /* Common subf function */ 2121fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2122fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2123fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2124fcf5ef2aSThomas Huth { 2125fcf5ef2aSThomas Huth TCGv t0 = ret; 2126fcf5ef2aSThomas Huth 2127fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2128fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2129fcf5ef2aSThomas Huth } 2130fcf5ef2aSThomas Huth 2131fcf5ef2aSThomas Huth if (compute_ca) { 2132fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2133fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2134efe843d8SDavid Gibson /* 2135efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2136efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2137efe843d8SDavid Gibson * produce the carry into bit 32. 2138efe843d8SDavid Gibson */ 2139fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2140fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2141fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2142fcf5ef2aSThomas Huth if (add_ca) { 2143fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2144fcf5ef2aSThomas Huth } else { 2145fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2146fcf5ef2aSThomas Huth } 2147fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2148fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2149fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2150fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2151fcf5ef2aSThomas Huth tcg_temp_free(t1); 2152e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 215333903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 215433903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 215533903d0aSNikunj A Dadhania } 2156fcf5ef2aSThomas Huth } else if (add_ca) { 2157fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2158fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2159fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2160fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2161fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21624c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2163fcf5ef2aSThomas Huth tcg_temp_free(zero); 2164fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2165fcf5ef2aSThomas Huth } else { 2166fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2167fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21684c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2169fcf5ef2aSThomas Huth } 2170fcf5ef2aSThomas Huth } else if (add_ca) { 2171efe843d8SDavid Gibson /* 2172efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2173efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2174efe843d8SDavid Gibson */ 2175fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2176fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2177fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2178fcf5ef2aSThomas Huth } else { 2179fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2180fcf5ef2aSThomas Huth } 2181fcf5ef2aSThomas Huth 2182fcf5ef2aSThomas Huth if (compute_ov) { 2183fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2184fcf5ef2aSThomas Huth } 2185fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2186fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2187fcf5ef2aSThomas Huth } 2188fcf5ef2aSThomas Huth 218911f4e8f8SRichard Henderson if (t0 != ret) { 2190fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2191fcf5ef2aSThomas Huth tcg_temp_free(t0); 2192fcf5ef2aSThomas Huth } 2193fcf5ef2aSThomas Huth } 2194fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2195fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2196fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2197fcf5ef2aSThomas Huth { \ 2198fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2199fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2200fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2201fcf5ef2aSThomas Huth } 2202fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2203fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2204fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2205fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2206fcf5ef2aSThomas Huth { \ 2207fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2208fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2209fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2210fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2211fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2212fcf5ef2aSThomas Huth } 2213fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2214fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2215fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2216fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2217fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2218fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2219fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2220fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2221fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2222fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2223fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2224fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2225fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2226fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2227fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2228fcf5ef2aSThomas Huth 2229fcf5ef2aSThomas Huth /* subfic */ 2230fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2231fcf5ef2aSThomas Huth { 2232fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2233fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2234fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2235fcf5ef2aSThomas Huth tcg_temp_free(c); 2236fcf5ef2aSThomas Huth } 2237fcf5ef2aSThomas Huth 2238fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2239fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2240fcf5ef2aSThomas Huth { 2241fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2242fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2243fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2244fcf5ef2aSThomas Huth tcg_temp_free(zero); 2245fcf5ef2aSThomas Huth } 2246fcf5ef2aSThomas Huth 2247fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2248fcf5ef2aSThomas Huth { 22491480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22501480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22511480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22521480d71cSNikunj A Dadhania } 2253fcf5ef2aSThomas Huth } 2254fcf5ef2aSThomas Huth 2255fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2256fcf5ef2aSThomas Huth { 2257fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2258fcf5ef2aSThomas Huth } 2259fcf5ef2aSThomas Huth 2260fcf5ef2aSThomas Huth /*** Integer logical ***/ 2261fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2262fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2263fcf5ef2aSThomas Huth { \ 2264fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2265fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2266fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2267fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2268fcf5ef2aSThomas Huth } 2269fcf5ef2aSThomas Huth 2270fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2271fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2272fcf5ef2aSThomas Huth { \ 2273fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2274fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2275fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2276fcf5ef2aSThomas Huth } 2277fcf5ef2aSThomas Huth 2278fcf5ef2aSThomas Huth /* and & and. */ 2279fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2280fcf5ef2aSThomas Huth /* andc & andc. */ 2281fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2282fcf5ef2aSThomas Huth 2283fcf5ef2aSThomas Huth /* andi. */ 2284fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2285fcf5ef2aSThomas Huth { 2286efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2287efe843d8SDavid Gibson UIMM(ctx->opcode)); 2288fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2289fcf5ef2aSThomas Huth } 2290fcf5ef2aSThomas Huth 2291fcf5ef2aSThomas Huth /* andis. */ 2292fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2293fcf5ef2aSThomas Huth { 2294efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2295efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2296fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2297fcf5ef2aSThomas Huth } 2298fcf5ef2aSThomas Huth 2299fcf5ef2aSThomas Huth /* cntlzw */ 2300fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2301fcf5ef2aSThomas Huth { 23029b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23039b8514e5SRichard Henderson 23049b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23059b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23069b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23079b8514e5SRichard Henderson tcg_temp_free_i32(t); 23089b8514e5SRichard Henderson 2309efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2310fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2311fcf5ef2aSThomas Huth } 2312efe843d8SDavid Gibson } 2313fcf5ef2aSThomas Huth 2314fcf5ef2aSThomas Huth /* cnttzw */ 2315fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2316fcf5ef2aSThomas Huth { 23179b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23189b8514e5SRichard Henderson 23199b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23209b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23219b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23229b8514e5SRichard Henderson tcg_temp_free_i32(t); 23239b8514e5SRichard Henderson 2324fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2325fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2326fcf5ef2aSThomas Huth } 2327fcf5ef2aSThomas Huth } 2328fcf5ef2aSThomas Huth 2329fcf5ef2aSThomas Huth /* eqv & eqv. */ 2330fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2331fcf5ef2aSThomas Huth /* extsb & extsb. */ 2332fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2333fcf5ef2aSThomas Huth /* extsh & extsh. */ 2334fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2335fcf5ef2aSThomas Huth /* nand & nand. */ 2336fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2337fcf5ef2aSThomas Huth /* nor & nor. */ 2338fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2339fcf5ef2aSThomas Huth 2340fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2341fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2342fcf5ef2aSThomas Huth { 2343fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2344fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2345fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2346fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2347fcf5ef2aSThomas Huth 2348fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2349b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2350fcf5ef2aSThomas Huth } 2351fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2352fcf5ef2aSThomas Huth 2353fcf5ef2aSThomas Huth /* or & or. */ 2354fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2355fcf5ef2aSThomas Huth { 2356fcf5ef2aSThomas Huth int rs, ra, rb; 2357fcf5ef2aSThomas Huth 2358fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2359fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2360fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2361fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2362fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2363efe843d8SDavid Gibson if (rs != rb) { 2364fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2365efe843d8SDavid Gibson } else { 2366fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2367efe843d8SDavid Gibson } 2368efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2369fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2370efe843d8SDavid Gibson } 2371fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2372fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2373fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2374fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2375fcf5ef2aSThomas Huth int prio = 0; 2376fcf5ef2aSThomas Huth 2377fcf5ef2aSThomas Huth switch (rs) { 2378fcf5ef2aSThomas Huth case 1: 2379fcf5ef2aSThomas Huth /* Set process priority to low */ 2380fcf5ef2aSThomas Huth prio = 2; 2381fcf5ef2aSThomas Huth break; 2382fcf5ef2aSThomas Huth case 6: 2383fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2384fcf5ef2aSThomas Huth prio = 3; 2385fcf5ef2aSThomas Huth break; 2386fcf5ef2aSThomas Huth case 2: 2387fcf5ef2aSThomas Huth /* Set process priority to normal */ 2388fcf5ef2aSThomas Huth prio = 4; 2389fcf5ef2aSThomas Huth break; 2390fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2391fcf5ef2aSThomas Huth case 31: 2392fcf5ef2aSThomas Huth if (!ctx->pr) { 2393fcf5ef2aSThomas Huth /* Set process priority to very low */ 2394fcf5ef2aSThomas Huth prio = 1; 2395fcf5ef2aSThomas Huth } 2396fcf5ef2aSThomas Huth break; 2397fcf5ef2aSThomas Huth case 5: 2398fcf5ef2aSThomas Huth if (!ctx->pr) { 2399fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2400fcf5ef2aSThomas Huth prio = 5; 2401fcf5ef2aSThomas Huth } 2402fcf5ef2aSThomas Huth break; 2403fcf5ef2aSThomas Huth case 3: 2404fcf5ef2aSThomas Huth if (!ctx->pr) { 2405fcf5ef2aSThomas Huth /* Set process priority to high */ 2406fcf5ef2aSThomas Huth prio = 6; 2407fcf5ef2aSThomas Huth } 2408fcf5ef2aSThomas Huth break; 2409fcf5ef2aSThomas Huth case 7: 2410fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2411fcf5ef2aSThomas Huth /* Set process priority to very high */ 2412fcf5ef2aSThomas Huth prio = 7; 2413fcf5ef2aSThomas Huth } 2414fcf5ef2aSThomas Huth break; 2415fcf5ef2aSThomas Huth #endif 2416fcf5ef2aSThomas Huth default: 2417fcf5ef2aSThomas Huth break; 2418fcf5ef2aSThomas Huth } 2419fcf5ef2aSThomas Huth if (prio) { 2420fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2421fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2422fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2423fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2424fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2425fcf5ef2aSThomas Huth tcg_temp_free(t0); 2426fcf5ef2aSThomas Huth } 2427fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2428efe843d8SDavid Gibson /* 2429efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2430efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2431efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2432efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2433fcf5ef2aSThomas Huth */ 2434fcf5ef2aSThomas Huth gen_pause(ctx); 2435fcf5ef2aSThomas Huth #endif 2436fcf5ef2aSThomas Huth #endif 2437fcf5ef2aSThomas Huth } 2438fcf5ef2aSThomas Huth } 2439fcf5ef2aSThomas Huth /* orc & orc. */ 2440fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2441fcf5ef2aSThomas Huth 2442fcf5ef2aSThomas Huth /* xor & xor. */ 2443fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2444fcf5ef2aSThomas Huth { 2445fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2446efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2447efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2448efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2449efe843d8SDavid Gibson } else { 2450fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2451efe843d8SDavid Gibson } 2452efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2453fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2454fcf5ef2aSThomas Huth } 2455efe843d8SDavid Gibson } 2456fcf5ef2aSThomas Huth 2457fcf5ef2aSThomas Huth /* ori */ 2458fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2459fcf5ef2aSThomas Huth { 2460fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2461fcf5ef2aSThomas Huth 2462fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2463fcf5ef2aSThomas Huth return; 2464fcf5ef2aSThomas Huth } 2465fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2466fcf5ef2aSThomas Huth } 2467fcf5ef2aSThomas Huth 2468fcf5ef2aSThomas Huth /* oris */ 2469fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2470fcf5ef2aSThomas Huth { 2471fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2472fcf5ef2aSThomas Huth 2473fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2474fcf5ef2aSThomas Huth /* NOP */ 2475fcf5ef2aSThomas Huth return; 2476fcf5ef2aSThomas Huth } 2477efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2478efe843d8SDavid Gibson uimm << 16); 2479fcf5ef2aSThomas Huth } 2480fcf5ef2aSThomas Huth 2481fcf5ef2aSThomas Huth /* xori */ 2482fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2483fcf5ef2aSThomas Huth { 2484fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2485fcf5ef2aSThomas Huth 2486fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2487fcf5ef2aSThomas Huth /* NOP */ 2488fcf5ef2aSThomas Huth return; 2489fcf5ef2aSThomas Huth } 2490fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2491fcf5ef2aSThomas Huth } 2492fcf5ef2aSThomas Huth 2493fcf5ef2aSThomas Huth /* xoris */ 2494fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2495fcf5ef2aSThomas Huth { 2496fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2497fcf5ef2aSThomas Huth 2498fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2499fcf5ef2aSThomas Huth /* NOP */ 2500fcf5ef2aSThomas Huth return; 2501fcf5ef2aSThomas Huth } 2502efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2503efe843d8SDavid Gibson uimm << 16); 2504fcf5ef2aSThomas Huth } 2505fcf5ef2aSThomas Huth 2506fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2507fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2508fcf5ef2aSThomas Huth { 2509fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2510fcf5ef2aSThomas Huth } 2511fcf5ef2aSThomas Huth 2512fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2513fcf5ef2aSThomas Huth { 251479770002SRichard Henderson #if defined(TARGET_PPC64) 2515fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251679770002SRichard Henderson #else 251779770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 251879770002SRichard Henderson #endif 2519fcf5ef2aSThomas Huth } 2520fcf5ef2aSThomas Huth 2521fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2522fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2523fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2524fcf5ef2aSThomas Huth { 252579770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2526fcf5ef2aSThomas Huth } 2527fcf5ef2aSThomas Huth #endif 2528fcf5ef2aSThomas Huth 2529fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2530fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2531fcf5ef2aSThomas Huth { 2532fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2533fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2534fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2535fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2536fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2537fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2538fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2539fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2540fcf5ef2aSThomas Huth tcg_temp_free(t0); 2541fcf5ef2aSThomas Huth } 2542fcf5ef2aSThomas Huth 2543fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2544fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2545fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2546fcf5ef2aSThomas Huth { 2547fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2548fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2549fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2550fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2551fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2552fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2553fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2554fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2555fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2556fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2557fcf5ef2aSThomas Huth tcg_temp_free(t0); 2558fcf5ef2aSThomas Huth } 2559fcf5ef2aSThomas Huth #endif 2560fcf5ef2aSThomas Huth 2561fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2562fcf5ef2aSThomas Huth /* bpermd */ 2563fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2564fcf5ef2aSThomas Huth { 2565fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2566fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2567fcf5ef2aSThomas Huth } 2568fcf5ef2aSThomas Huth #endif 2569fcf5ef2aSThomas Huth 2570fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2571fcf5ef2aSThomas Huth /* extsw & extsw. */ 2572fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2573fcf5ef2aSThomas Huth 2574fcf5ef2aSThomas Huth /* cntlzd */ 2575fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2576fcf5ef2aSThomas Huth { 25779b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2578efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2579fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2580fcf5ef2aSThomas Huth } 2581efe843d8SDavid Gibson } 2582fcf5ef2aSThomas Huth 2583fcf5ef2aSThomas Huth /* cnttzd */ 2584fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2585fcf5ef2aSThomas Huth { 25869b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2587fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2588fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2589fcf5ef2aSThomas Huth } 2590fcf5ef2aSThomas Huth } 2591fcf5ef2aSThomas Huth 2592fcf5ef2aSThomas Huth /* darn */ 2593fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2594fcf5ef2aSThomas Huth { 2595fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2596fcf5ef2aSThomas Huth 25977e4357f6SRichard Henderson if (l > 2) { 25987e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25997e4357f6SRichard Henderson } else { 2600f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2601fcf5ef2aSThomas Huth if (l == 0) { 2602fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26037e4357f6SRichard Henderson } else { 2604fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2605fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26067e4357f6SRichard Henderson } 2607fcf5ef2aSThomas Huth } 2608fcf5ef2aSThomas Huth } 2609fcf5ef2aSThomas Huth #endif 2610fcf5ef2aSThomas Huth 2611fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2612fcf5ef2aSThomas Huth 2613fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2614fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2615fcf5ef2aSThomas Huth { 2616fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2617fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2618fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2619fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2620fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2621fcf5ef2aSThomas Huth 2622fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2623fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2624fcf5ef2aSThomas Huth } else { 2625fcf5ef2aSThomas Huth target_ulong mask; 2626c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2627fcf5ef2aSThomas Huth TCGv t1; 2628fcf5ef2aSThomas Huth 2629fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2630fcf5ef2aSThomas Huth mb += 32; 2631fcf5ef2aSThomas Huth me += 32; 2632fcf5ef2aSThomas Huth #endif 2633fcf5ef2aSThomas Huth mask = MASK(mb, me); 2634fcf5ef2aSThomas Huth 2635c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2636c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2637c4f6a4a3SDaniele Buono mask_in_32b = false; 2638c4f6a4a3SDaniele Buono } 2639c4f6a4a3SDaniele Buono #endif 2640fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2641c4f6a4a3SDaniele Buono if (mask_in_32b) { 2642fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2643fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2644fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2645fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2646fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2647fcf5ef2aSThomas Huth } else { 2648fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2649fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2650fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2651fcf5ef2aSThomas Huth #else 2652fcf5ef2aSThomas Huth g_assert_not_reached(); 2653fcf5ef2aSThomas Huth #endif 2654fcf5ef2aSThomas Huth } 2655fcf5ef2aSThomas Huth 2656fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2657fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2658fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2659fcf5ef2aSThomas Huth tcg_temp_free(t1); 2660fcf5ef2aSThomas Huth } 2661fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2662fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2663fcf5ef2aSThomas Huth } 2664fcf5ef2aSThomas Huth } 2665fcf5ef2aSThomas Huth 2666fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2667fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2668fcf5ef2aSThomas Huth { 2669fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2670fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26717b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26727b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26737b4d326fSRichard Henderson int me = ME(ctx->opcode); 26747b4d326fSRichard Henderson int len = me - mb + 1; 26757b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2676fcf5ef2aSThomas Huth 26777b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26787b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26797b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26807b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2681fcf5ef2aSThomas Huth } else { 2682fcf5ef2aSThomas Huth target_ulong mask; 2683c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2684fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2685fcf5ef2aSThomas Huth mb += 32; 2686fcf5ef2aSThomas Huth me += 32; 2687fcf5ef2aSThomas Huth #endif 2688fcf5ef2aSThomas Huth mask = MASK(mb, me); 2689c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2690c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2691c4f6a4a3SDaniele Buono mask_in_32b = false; 2692c4f6a4a3SDaniele Buono } 2693c4f6a4a3SDaniele Buono #endif 2694c4f6a4a3SDaniele Buono if (mask_in_32b) { 26957b4d326fSRichard Henderson if (sh == 0) { 26967b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 269794f040aaSVitaly Chikunov } else { 2698fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2699fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2700fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2701fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2702fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2703fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 270494f040aaSVitaly Chikunov } 2705fcf5ef2aSThomas Huth } else { 2706fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2707fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2708fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2709fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2710fcf5ef2aSThomas Huth #else 2711fcf5ef2aSThomas Huth g_assert_not_reached(); 2712fcf5ef2aSThomas Huth #endif 2713fcf5ef2aSThomas Huth } 2714fcf5ef2aSThomas Huth } 2715fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2716fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2717fcf5ef2aSThomas Huth } 2718fcf5ef2aSThomas Huth } 2719fcf5ef2aSThomas Huth 2720fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2721fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2722fcf5ef2aSThomas Huth { 2723fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2724fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2725fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2726fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2727fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2728fcf5ef2aSThomas Huth target_ulong mask; 2729c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2730fcf5ef2aSThomas Huth 2731fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2732fcf5ef2aSThomas Huth mb += 32; 2733fcf5ef2aSThomas Huth me += 32; 2734fcf5ef2aSThomas Huth #endif 2735fcf5ef2aSThomas Huth mask = MASK(mb, me); 2736fcf5ef2aSThomas Huth 2737c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2738c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2739c4f6a4a3SDaniele Buono mask_in_32b = false; 2740c4f6a4a3SDaniele Buono } 2741c4f6a4a3SDaniele Buono #endif 2742c4f6a4a3SDaniele Buono if (mask_in_32b) { 2743fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2744fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2745fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2746fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2747fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2748fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2749fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2750fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2751fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2752fcf5ef2aSThomas Huth } else { 2753fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2754fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2755fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2756fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2757fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2758fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2759fcf5ef2aSThomas Huth #else 2760fcf5ef2aSThomas Huth g_assert_not_reached(); 2761fcf5ef2aSThomas Huth #endif 2762fcf5ef2aSThomas Huth } 2763fcf5ef2aSThomas Huth 2764fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2765fcf5ef2aSThomas Huth 2766fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2767fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2768fcf5ef2aSThomas Huth } 2769fcf5ef2aSThomas Huth } 2770fcf5ef2aSThomas Huth 2771fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2772fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2773fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2774fcf5ef2aSThomas Huth { \ 2775fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2776fcf5ef2aSThomas Huth } \ 2777fcf5ef2aSThomas Huth \ 2778fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2779fcf5ef2aSThomas Huth { \ 2780fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2781fcf5ef2aSThomas Huth } 2782fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2783fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2784fcf5ef2aSThomas Huth { \ 2785fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2786fcf5ef2aSThomas Huth } \ 2787fcf5ef2aSThomas Huth \ 2788fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2789fcf5ef2aSThomas Huth { \ 2790fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2791fcf5ef2aSThomas Huth } \ 2792fcf5ef2aSThomas Huth \ 2793fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2794fcf5ef2aSThomas Huth { \ 2795fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2796fcf5ef2aSThomas Huth } \ 2797fcf5ef2aSThomas Huth \ 2798fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2799fcf5ef2aSThomas Huth { \ 2800fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2801fcf5ef2aSThomas Huth } 2802fcf5ef2aSThomas Huth 2803fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2804fcf5ef2aSThomas Huth { 2805fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2806fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28077b4d326fSRichard Henderson int len = me - mb + 1; 28087b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2809fcf5ef2aSThomas Huth 28107b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28117b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28127b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28137b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2814fcf5ef2aSThomas Huth } else { 2815fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2816fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2817fcf5ef2aSThomas Huth } 2818fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2819fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2820fcf5ef2aSThomas Huth } 2821fcf5ef2aSThomas Huth } 2822fcf5ef2aSThomas Huth 2823fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2824fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2825fcf5ef2aSThomas Huth { 2826fcf5ef2aSThomas Huth uint32_t sh, mb; 2827fcf5ef2aSThomas Huth 2828fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2829fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2830fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2831fcf5ef2aSThomas Huth } 2832fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2833fcf5ef2aSThomas Huth 2834fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2835fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2836fcf5ef2aSThomas Huth { 2837fcf5ef2aSThomas Huth uint32_t sh, me; 2838fcf5ef2aSThomas Huth 2839fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2840fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2841fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2842fcf5ef2aSThomas Huth } 2843fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2844fcf5ef2aSThomas Huth 2845fcf5ef2aSThomas Huth /* rldic - rldic. */ 2846fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2847fcf5ef2aSThomas Huth { 2848fcf5ef2aSThomas Huth uint32_t sh, mb; 2849fcf5ef2aSThomas Huth 2850fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2851fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2852fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2853fcf5ef2aSThomas Huth } 2854fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2855fcf5ef2aSThomas Huth 2856fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2857fcf5ef2aSThomas Huth { 2858fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2859fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2860fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2861fcf5ef2aSThomas Huth TCGv t0; 2862fcf5ef2aSThomas Huth 2863fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2864fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2865fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2866fcf5ef2aSThomas Huth tcg_temp_free(t0); 2867fcf5ef2aSThomas Huth 2868fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2869fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2870fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2871fcf5ef2aSThomas Huth } 2872fcf5ef2aSThomas Huth } 2873fcf5ef2aSThomas Huth 2874fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2875fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2876fcf5ef2aSThomas Huth { 2877fcf5ef2aSThomas Huth uint32_t mb; 2878fcf5ef2aSThomas Huth 2879fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2880fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2881fcf5ef2aSThomas Huth } 2882fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2883fcf5ef2aSThomas Huth 2884fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2885fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2886fcf5ef2aSThomas Huth { 2887fcf5ef2aSThomas Huth uint32_t me; 2888fcf5ef2aSThomas Huth 2889fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2890fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2891fcf5ef2aSThomas Huth } 2892fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2893fcf5ef2aSThomas Huth 2894fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2895fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2896fcf5ef2aSThomas Huth { 2897fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2898fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2899fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2900fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2901fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2902fcf5ef2aSThomas Huth 2903fcf5ef2aSThomas Huth if (mb <= me) { 2904fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2905fcf5ef2aSThomas Huth } else { 2906fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2907fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2908fcf5ef2aSThomas Huth 2909fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2910fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2911fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2912fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2913fcf5ef2aSThomas Huth tcg_temp_free(t1); 2914fcf5ef2aSThomas Huth } 2915fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2916fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2917fcf5ef2aSThomas Huth } 2918fcf5ef2aSThomas Huth } 2919fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2920fcf5ef2aSThomas Huth #endif 2921fcf5ef2aSThomas Huth 2922fcf5ef2aSThomas Huth /*** Integer shift ***/ 2923fcf5ef2aSThomas Huth 2924fcf5ef2aSThomas Huth /* slw & slw. */ 2925fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2926fcf5ef2aSThomas Huth { 2927fcf5ef2aSThomas Huth TCGv t0, t1; 2928fcf5ef2aSThomas Huth 2929fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2930fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2931fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2932fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2933fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2934fcf5ef2aSThomas Huth #else 2935fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2936fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2937fcf5ef2aSThomas Huth #endif 2938fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2939fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2940fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2941fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2942fcf5ef2aSThomas Huth tcg_temp_free(t1); 2943fcf5ef2aSThomas Huth tcg_temp_free(t0); 2944fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2945efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2946fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2947fcf5ef2aSThomas Huth } 2948efe843d8SDavid Gibson } 2949fcf5ef2aSThomas Huth 2950fcf5ef2aSThomas Huth /* sraw & sraw. */ 2951fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2952fcf5ef2aSThomas Huth { 2953fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2954fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2955efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2956fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2957fcf5ef2aSThomas Huth } 2958efe843d8SDavid Gibson } 2959fcf5ef2aSThomas Huth 2960fcf5ef2aSThomas Huth /* srawi & srawi. */ 2961fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2962fcf5ef2aSThomas Huth { 2963fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2964fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2965fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2966fcf5ef2aSThomas Huth if (sh == 0) { 2967fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2968fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2969af1c259fSSandipan Das if (is_isa300(ctx)) { 2970af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2971af1c259fSSandipan Das } 2972fcf5ef2aSThomas Huth } else { 2973fcf5ef2aSThomas Huth TCGv t0; 2974fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2975fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2976fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2977fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2978fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2979fcf5ef2aSThomas Huth tcg_temp_free(t0); 2980fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2981af1c259fSSandipan Das if (is_isa300(ctx)) { 2982af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2983af1c259fSSandipan Das } 2984fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2985fcf5ef2aSThomas Huth } 2986fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2987fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2988fcf5ef2aSThomas Huth } 2989fcf5ef2aSThomas Huth } 2990fcf5ef2aSThomas Huth 2991fcf5ef2aSThomas Huth /* srw & srw. */ 2992fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2993fcf5ef2aSThomas Huth { 2994fcf5ef2aSThomas Huth TCGv t0, t1; 2995fcf5ef2aSThomas Huth 2996fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2997fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2998fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2999fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3000fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3001fcf5ef2aSThomas Huth #else 3002fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3003fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3004fcf5ef2aSThomas Huth #endif 3005fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3006fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3007fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3008fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3009fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3010fcf5ef2aSThomas Huth tcg_temp_free(t1); 3011fcf5ef2aSThomas Huth tcg_temp_free(t0); 3012efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3013fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3014fcf5ef2aSThomas Huth } 3015efe843d8SDavid Gibson } 3016fcf5ef2aSThomas Huth 3017fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3018fcf5ef2aSThomas Huth /* sld & sld. */ 3019fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3020fcf5ef2aSThomas Huth { 3021fcf5ef2aSThomas Huth TCGv t0, t1; 3022fcf5ef2aSThomas Huth 3023fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3024fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3025fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3026fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3027fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3028fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3029fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3030fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3031fcf5ef2aSThomas Huth tcg_temp_free(t1); 3032fcf5ef2aSThomas Huth tcg_temp_free(t0); 3033efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3034fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3035fcf5ef2aSThomas Huth } 3036efe843d8SDavid Gibson } 3037fcf5ef2aSThomas Huth 3038fcf5ef2aSThomas Huth /* srad & srad. */ 3039fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3040fcf5ef2aSThomas Huth { 3041fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3042fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3043efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3044fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3045fcf5ef2aSThomas Huth } 3046efe843d8SDavid Gibson } 3047fcf5ef2aSThomas Huth /* sradi & sradi. */ 3048fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3049fcf5ef2aSThomas Huth { 3050fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3051fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3052fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3053fcf5ef2aSThomas Huth if (sh == 0) { 3054fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3055fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3056af1c259fSSandipan Das if (is_isa300(ctx)) { 3057af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3058af1c259fSSandipan Das } 3059fcf5ef2aSThomas Huth } else { 3060fcf5ef2aSThomas Huth TCGv t0; 3061fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3062fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3063fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3064fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3065fcf5ef2aSThomas Huth tcg_temp_free(t0); 3066fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3067af1c259fSSandipan Das if (is_isa300(ctx)) { 3068af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3069af1c259fSSandipan Das } 3070fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3071fcf5ef2aSThomas Huth } 3072fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3073fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3074fcf5ef2aSThomas Huth } 3075fcf5ef2aSThomas Huth } 3076fcf5ef2aSThomas Huth 3077fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3078fcf5ef2aSThomas Huth { 3079fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3080fcf5ef2aSThomas Huth } 3081fcf5ef2aSThomas Huth 3082fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3083fcf5ef2aSThomas Huth { 3084fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3085fcf5ef2aSThomas Huth } 3086fcf5ef2aSThomas Huth 3087fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3088fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3089fcf5ef2aSThomas Huth { 3090fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3091fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3092fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3093fcf5ef2aSThomas Huth 3094fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3095fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3096fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3097fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3098fcf5ef2aSThomas Huth } 3099fcf5ef2aSThomas Huth } 3100fcf5ef2aSThomas Huth 3101fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3102fcf5ef2aSThomas Huth { 3103fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3104fcf5ef2aSThomas Huth } 3105fcf5ef2aSThomas Huth 3106fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3107fcf5ef2aSThomas Huth { 3108fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3109fcf5ef2aSThomas Huth } 3110fcf5ef2aSThomas Huth 3111fcf5ef2aSThomas Huth /* srd & srd. */ 3112fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3113fcf5ef2aSThomas Huth { 3114fcf5ef2aSThomas Huth TCGv t0, t1; 3115fcf5ef2aSThomas Huth 3116fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3117fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3118fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3119fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3120fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3121fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3122fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3123fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3124fcf5ef2aSThomas Huth tcg_temp_free(t1); 3125fcf5ef2aSThomas Huth tcg_temp_free(t0); 3126efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3127fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3128fcf5ef2aSThomas Huth } 3129efe843d8SDavid Gibson } 3130fcf5ef2aSThomas Huth #endif 3131fcf5ef2aSThomas Huth 3132fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3133fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3134fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3135fcf5ef2aSThomas Huth target_long maskl) 3136fcf5ef2aSThomas Huth { 3137fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3138fcf5ef2aSThomas Huth 3139fcf5ef2aSThomas Huth simm &= ~maskl; 3140fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3141fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3142fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3143fcf5ef2aSThomas Huth } 3144fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3145fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3146fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3147fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3148fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3149fcf5ef2aSThomas Huth } 3150fcf5ef2aSThomas Huth } else { 3151fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3152fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3153fcf5ef2aSThomas Huth } else { 3154fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3155fcf5ef2aSThomas Huth } 3156fcf5ef2aSThomas Huth } 3157fcf5ef2aSThomas Huth } 3158fcf5ef2aSThomas Huth 3159fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3160fcf5ef2aSThomas Huth { 3161fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3162fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3163fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3164fcf5ef2aSThomas Huth } else { 3165fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3166fcf5ef2aSThomas Huth } 3167fcf5ef2aSThomas Huth } else { 3168fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3169fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3170fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3171fcf5ef2aSThomas Huth } 3172fcf5ef2aSThomas Huth } 3173fcf5ef2aSThomas Huth } 3174fcf5ef2aSThomas Huth 3175fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3176fcf5ef2aSThomas Huth { 3177fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3178fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3179fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3180fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3181fcf5ef2aSThomas Huth } else { 3182fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3183fcf5ef2aSThomas Huth } 3184fcf5ef2aSThomas Huth } 3185fcf5ef2aSThomas Huth 3186fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3187fcf5ef2aSThomas Huth target_long val) 3188fcf5ef2aSThomas Huth { 3189fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3190fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3191fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3192fcf5ef2aSThomas Huth } 3193fcf5ef2aSThomas Huth } 3194fcf5ef2aSThomas Huth 3195fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3196fcf5ef2aSThomas Huth { 3197fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3198fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3199fcf5ef2aSThomas Huth } 3200fcf5ef2aSThomas Huth 3201eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3202eb63efd9SFernando Eckhardt Valle { 3203eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3204eb63efd9SFernando Eckhardt Valle if (ra) { 3205eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3206eb63efd9SFernando Eckhardt Valle } else { 3207eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3208eb63efd9SFernando Eckhardt Valle } 3209eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3210eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3211eb63efd9SFernando Eckhardt Valle } 3212eb63efd9SFernando Eckhardt Valle return ea; 3213eb63efd9SFernando Eckhardt Valle } 3214eb63efd9SFernando Eckhardt Valle 3215fcf5ef2aSThomas Huth /*** Integer load ***/ 3216fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3217fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3218fcf5ef2aSThomas Huth 3219fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3220fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3221fcf5ef2aSThomas Huth TCGv val, \ 3222fcf5ef2aSThomas Huth TCGv addr) \ 3223fcf5ef2aSThomas Huth { \ 3224fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3225fcf5ef2aSThomas Huth } 3226fcf5ef2aSThomas Huth 3227fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3228fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3229fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3230fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3231fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3232fcf5ef2aSThomas Huth 3233fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3234fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3235fcf5ef2aSThomas Huth 3236fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3237fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3238fcf5ef2aSThomas Huth TCGv_i64 val, \ 3239fcf5ef2aSThomas Huth TCGv addr) \ 3240fcf5ef2aSThomas Huth { \ 3241fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3242fcf5ef2aSThomas Huth } 3243fcf5ef2aSThomas Huth 3244fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3245fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3246fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3247fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3248fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3249fcf5ef2aSThomas Huth 3250fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3251fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3252fcf5ef2aSThomas Huth #endif 3253fcf5ef2aSThomas Huth 3254fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3255fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3256fcf5ef2aSThomas Huth TCGv val, \ 3257fcf5ef2aSThomas Huth TCGv addr) \ 3258fcf5ef2aSThomas Huth { \ 3259fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3260fcf5ef2aSThomas Huth } 3261fcf5ef2aSThomas Huth 3262e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3263fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3264e8f4c8d6SRichard Henderson #endif 3265fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3266fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3267fcf5ef2aSThomas Huth 3268fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3269fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3270fcf5ef2aSThomas Huth 3271fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3272fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3273fcf5ef2aSThomas Huth TCGv_i64 val, \ 3274fcf5ef2aSThomas Huth TCGv addr) \ 3275fcf5ef2aSThomas Huth { \ 3276fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3277fcf5ef2aSThomas Huth } 3278fcf5ef2aSThomas Huth 3279fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3280fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3281fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3282fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3283fcf5ef2aSThomas Huth 3284fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3285fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3286fcf5ef2aSThomas Huth #endif 3287fcf5ef2aSThomas Huth 3288fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3289fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3290fcf5ef2aSThomas Huth { \ 3291fcf5ef2aSThomas Huth TCGv EA; \ 3292fcf5ef2aSThomas Huth chk; \ 3293fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3294fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3295fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3296fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3297fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3298fcf5ef2aSThomas Huth } 3299fcf5ef2aSThomas Huth 3300fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3301fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3302fcf5ef2aSThomas Huth 3303fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3304fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3305fcf5ef2aSThomas Huth 330650728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 330750728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 330850728199SRoman Kapl { \ 330950728199SRoman Kapl TCGv EA; \ 331050728199SRoman Kapl CHK_SV; \ 331150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 331250728199SRoman Kapl EA = tcg_temp_new(); \ 331350728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 331450728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 331550728199SRoman Kapl tcg_temp_free(EA); \ 331650728199SRoman Kapl } 331750728199SRoman Kapl 331850728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 331950728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 332050728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 332150728199SRoman Kapl #if defined(TARGET_PPC64) 332250728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 332350728199SRoman Kapl #endif 332450728199SRoman Kapl 3325fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3326fcf5ef2aSThomas Huth /* CI load/store variants */ 3327fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3328fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3329fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3330fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3331fcf5ef2aSThomas Huth #endif 3332fcf5ef2aSThomas Huth 3333fcf5ef2aSThomas Huth /*** Integer store ***/ 3334fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3335fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3336fcf5ef2aSThomas Huth { \ 3337fcf5ef2aSThomas Huth TCGv EA; \ 3338fcf5ef2aSThomas Huth chk; \ 3339fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3340fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3341fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3342fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3343fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3344fcf5ef2aSThomas Huth } 3345fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3346fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3347fcf5ef2aSThomas Huth 3348fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3349fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3350fcf5ef2aSThomas Huth 335150728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 335250728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 335350728199SRoman Kapl { \ 335450728199SRoman Kapl TCGv EA; \ 335550728199SRoman Kapl CHK_SV; \ 335650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 335750728199SRoman Kapl EA = tcg_temp_new(); \ 335850728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 335950728199SRoman Kapl tcg_gen_qemu_st_tl( \ 336050728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 336150728199SRoman Kapl tcg_temp_free(EA); \ 336250728199SRoman Kapl } 336350728199SRoman Kapl 336450728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 336550728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 336650728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 336750728199SRoman Kapl #if defined(TARGET_PPC64) 336850728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 336950728199SRoman Kapl #endif 337050728199SRoman Kapl 3371fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3372fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3373fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3374fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3375fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3376fcf5ef2aSThomas Huth #endif 3377fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3378fcf5ef2aSThomas Huth 3379fcf5ef2aSThomas Huth /* lhbrx */ 3380fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3381fcf5ef2aSThomas Huth 3382fcf5ef2aSThomas Huth /* lwbrx */ 3383fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3384fcf5ef2aSThomas Huth 3385fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3386fcf5ef2aSThomas Huth /* ldbrx */ 3387fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3388fcf5ef2aSThomas Huth /* stdbrx */ 3389fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3390fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3391fcf5ef2aSThomas Huth 3392fcf5ef2aSThomas Huth /* sthbrx */ 3393fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3394fcf5ef2aSThomas Huth /* stwbrx */ 3395fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3396fcf5ef2aSThomas Huth 3397fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3398fcf5ef2aSThomas Huth 3399fcf5ef2aSThomas Huth /* lmw */ 3400fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3401fcf5ef2aSThomas Huth { 3402fcf5ef2aSThomas Huth TCGv t0; 3403fcf5ef2aSThomas Huth TCGv_i32 t1; 3404fcf5ef2aSThomas Huth 3405fcf5ef2aSThomas Huth if (ctx->le_mode) { 3406fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3407fcf5ef2aSThomas Huth return; 3408fcf5ef2aSThomas Huth } 3409fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3410fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3411fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3412fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3413fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3414fcf5ef2aSThomas Huth tcg_temp_free(t0); 3415fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3416fcf5ef2aSThomas Huth } 3417fcf5ef2aSThomas Huth 3418fcf5ef2aSThomas Huth /* stmw */ 3419fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3420fcf5ef2aSThomas Huth { 3421fcf5ef2aSThomas Huth TCGv t0; 3422fcf5ef2aSThomas Huth TCGv_i32 t1; 3423fcf5ef2aSThomas Huth 3424fcf5ef2aSThomas Huth if (ctx->le_mode) { 3425fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3426fcf5ef2aSThomas Huth return; 3427fcf5ef2aSThomas Huth } 3428fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3429fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3430fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3431fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3432fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3433fcf5ef2aSThomas Huth tcg_temp_free(t0); 3434fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3435fcf5ef2aSThomas Huth } 3436fcf5ef2aSThomas Huth 3437fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3438fcf5ef2aSThomas Huth 3439fcf5ef2aSThomas Huth /* lswi */ 3440efe843d8SDavid Gibson /* 3441efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3442efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3443efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3444efe843d8SDavid Gibson * spec... 3445fcf5ef2aSThomas Huth */ 3446fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3447fcf5ef2aSThomas Huth { 3448fcf5ef2aSThomas Huth TCGv t0; 3449fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3450fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3451fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3452fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3453fcf5ef2aSThomas Huth int nr; 3454fcf5ef2aSThomas Huth 3455fcf5ef2aSThomas Huth if (ctx->le_mode) { 3456fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3457fcf5ef2aSThomas Huth return; 3458fcf5ef2aSThomas Huth } 3459efe843d8SDavid Gibson if (nb == 0) { 3460fcf5ef2aSThomas Huth nb = 32; 3461efe843d8SDavid Gibson } 3462f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3463fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3464fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3465fcf5ef2aSThomas Huth return; 3466fcf5ef2aSThomas Huth } 3467fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3468fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3469fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3470fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3471fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3472fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3473fcf5ef2aSThomas Huth tcg_temp_free(t0); 3474fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3475fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3476fcf5ef2aSThomas Huth } 3477fcf5ef2aSThomas Huth 3478fcf5ef2aSThomas Huth /* lswx */ 3479fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3480fcf5ef2aSThomas Huth { 3481fcf5ef2aSThomas Huth TCGv t0; 3482fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3483fcf5ef2aSThomas Huth 3484fcf5ef2aSThomas Huth if (ctx->le_mode) { 3485fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3486fcf5ef2aSThomas Huth return; 3487fcf5ef2aSThomas Huth } 3488fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3489fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3490fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3491fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3492fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3493fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3494fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3495fcf5ef2aSThomas Huth tcg_temp_free(t0); 3496fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3497fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3498fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3499fcf5ef2aSThomas Huth } 3500fcf5ef2aSThomas Huth 3501fcf5ef2aSThomas Huth /* stswi */ 3502fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3503fcf5ef2aSThomas Huth { 3504fcf5ef2aSThomas Huth TCGv t0; 3505fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3506fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3507fcf5ef2aSThomas Huth 3508fcf5ef2aSThomas Huth if (ctx->le_mode) { 3509fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3510fcf5ef2aSThomas Huth return; 3511fcf5ef2aSThomas Huth } 3512fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3513fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3514fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3515efe843d8SDavid Gibson if (nb == 0) { 3516fcf5ef2aSThomas Huth nb = 32; 3517efe843d8SDavid Gibson } 3518fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3519fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3520fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3521fcf5ef2aSThomas Huth tcg_temp_free(t0); 3522fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3523fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3524fcf5ef2aSThomas Huth } 3525fcf5ef2aSThomas Huth 3526fcf5ef2aSThomas Huth /* stswx */ 3527fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3528fcf5ef2aSThomas Huth { 3529fcf5ef2aSThomas Huth TCGv t0; 3530fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3531fcf5ef2aSThomas Huth 3532fcf5ef2aSThomas Huth if (ctx->le_mode) { 3533fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3534fcf5ef2aSThomas Huth return; 3535fcf5ef2aSThomas Huth } 3536fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3537fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3538fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3539fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3540fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3541fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3542fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3543fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3544fcf5ef2aSThomas Huth tcg_temp_free(t0); 3545fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3546fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3547fcf5ef2aSThomas Huth } 3548fcf5ef2aSThomas Huth 3549fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3550fcf5ef2aSThomas Huth /* eieio */ 3551fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3552fcf5ef2aSThomas Huth { 3553c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3554c8fd8373SCédric Le Goater 3555c8fd8373SCédric Le Goater /* 3556c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3557c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3558c8fd8373SCédric Le Goater */ 3559c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3560c8fd8373SCédric Le Goater /* 3561c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3562c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3563c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3564c8fd8373SCédric Le Goater * complain to the user. 3565c8fd8373SCédric Le Goater */ 3566c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3567c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 35682c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3569c8fd8373SCédric Le Goater } else { 3570c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3571c8fd8373SCédric Le Goater } 3572c8fd8373SCédric Le Goater } 3573c8fd8373SCédric Le Goater 3574c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3575fcf5ef2aSThomas Huth } 3576fcf5ef2aSThomas Huth 3577fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3578fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3579fcf5ef2aSThomas Huth { 3580fcf5ef2aSThomas Huth TCGv_i32 t; 3581fcf5ef2aSThomas Huth TCGLabel *l; 3582fcf5ef2aSThomas Huth 3583fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3584fcf5ef2aSThomas Huth return; 3585fcf5ef2aSThomas Huth } 3586fcf5ef2aSThomas Huth l = gen_new_label(); 3587fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3588fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3589fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3590fcf5ef2aSThomas Huth if (global) { 3591fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3592fcf5ef2aSThomas Huth } else { 3593fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3594fcf5ef2aSThomas Huth } 3595fcf5ef2aSThomas Huth gen_set_label(l); 3596fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3597fcf5ef2aSThomas Huth } 3598fcf5ef2aSThomas Huth #else 3599fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3600fcf5ef2aSThomas Huth #endif 3601fcf5ef2aSThomas Huth 3602fcf5ef2aSThomas Huth /* isync */ 3603fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3604fcf5ef2aSThomas Huth { 3605fcf5ef2aSThomas Huth /* 3606fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3607fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3608fcf5ef2aSThomas Huth */ 3609fcf5ef2aSThomas Huth if (!ctx->pr) { 3610fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3611fcf5ef2aSThomas Huth } 36124771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3613d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3614fcf5ef2aSThomas Huth } 3615fcf5ef2aSThomas Huth 3616fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3617fcf5ef2aSThomas Huth 361814776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 36192a4e6c1bSRichard Henderson { 36202a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 36212a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 36222a4e6c1bSRichard Henderson 36232a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 36242a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 36252a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 36262a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 36272a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 36282a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 36292a4e6c1bSRichard Henderson tcg_temp_free(t0); 36302a4e6c1bSRichard Henderson } 36312a4e6c1bSRichard Henderson 3632fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3633fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3634fcf5ef2aSThomas Huth { \ 36352a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3636fcf5ef2aSThomas Huth } 3637fcf5ef2aSThomas Huth 3638fcf5ef2aSThomas Huth /* lwarx */ 3639fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3640fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3641fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3642fcf5ef2aSThomas Huth 364314776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 364420923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 364520923c1dSRichard Henderson { 364620923c1dSRichard Henderson TCGv t = tcg_temp_new(); 364720923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 364820923c1dSRichard Henderson TCGv u = tcg_temp_new(); 364920923c1dSRichard Henderson 365020923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 365120923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 365220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 365320923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 365420923c1dSRichard Henderson 365520923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 365620923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 365720923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 365820923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 365920923c1dSRichard Henderson 366020923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 366120923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 366220923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 366320923c1dSRichard Henderson 366420923c1dSRichard Henderson tcg_temp_free(t); 366520923c1dSRichard Henderson tcg_temp_free(t2); 366620923c1dSRichard Henderson tcg_temp_free(u); 366720923c1dSRichard Henderson } 366820923c1dSRichard Henderson 366914776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 367020ba8504SRichard Henderson { 367120ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 367220ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 367320923c1dSRichard Henderson int rt = rD(ctx->opcode); 367420923c1dSRichard Henderson bool need_serial; 367520ba8504SRichard Henderson TCGv src, dst; 367620ba8504SRichard Henderson 367720ba8504SRichard Henderson gen_addr_register(ctx, EA); 367820923c1dSRichard Henderson dst = cpu_gpr[rt]; 367920923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 368020ba8504SRichard Henderson 368120923c1dSRichard Henderson need_serial = false; 368220ba8504SRichard Henderson memop |= MO_ALIGN; 368320ba8504SRichard Henderson switch (gpr_FC) { 368420ba8504SRichard Henderson case 0: /* Fetch and add */ 368520ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 368620ba8504SRichard Henderson break; 368720ba8504SRichard Henderson case 1: /* Fetch and xor */ 368820ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 368920ba8504SRichard Henderson break; 369020ba8504SRichard Henderson case 2: /* Fetch and or */ 369120ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 369220ba8504SRichard Henderson break; 369320ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 369420ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 369520ba8504SRichard Henderson break; 3696b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3697b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3698b8ce0f86SRichard Henderson break; 3699b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3700b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3701b8ce0f86SRichard Henderson break; 3702b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3703b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3704b8ce0f86SRichard Henderson break; 3705b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3706b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3707b8ce0f86SRichard Henderson break; 370820ba8504SRichard Henderson case 8: /* Swap */ 370920ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 371020ba8504SRichard Henderson break; 371120923c1dSRichard Henderson 371220923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 371320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 371420923c1dSRichard Henderson need_serial = true; 371520923c1dSRichard Henderson } else { 371620923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 371720923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 371820923c1dSRichard Henderson 371920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 372020923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 372120923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 372220923c1dSRichard Henderson } else { 372320923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 372420923c1dSRichard Henderson } 372520923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 372620923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 372720923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 372820923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 372920923c1dSRichard Henderson 373020923c1dSRichard Henderson tcg_temp_free(t0); 373120923c1dSRichard Henderson tcg_temp_free(t1); 373220923c1dSRichard Henderson } 373320ba8504SRichard Henderson break; 373420923c1dSRichard Henderson 373520923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 373620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 373720923c1dSRichard Henderson need_serial = true; 373820923c1dSRichard Henderson } else { 373920923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 374020923c1dSRichard Henderson } 374120923c1dSRichard Henderson break; 374220923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 374320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374420923c1dSRichard Henderson need_serial = true; 374520923c1dSRichard Henderson } else { 374620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 374720923c1dSRichard Henderson } 374820923c1dSRichard Henderson break; 374920923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 375020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 375120923c1dSRichard Henderson need_serial = true; 375220923c1dSRichard Henderson } else { 375320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 375420923c1dSRichard Henderson } 375520923c1dSRichard Henderson break; 375620923c1dSRichard Henderson 375720ba8504SRichard Henderson default: 375820ba8504SRichard Henderson /* invoke data storage error handler */ 375920ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 376020ba8504SRichard Henderson } 376120ba8504SRichard Henderson tcg_temp_free(EA); 376220923c1dSRichard Henderson 376320923c1dSRichard Henderson if (need_serial) { 376420923c1dSRichard Henderson /* Restart with exclusive lock. */ 376520923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 376620923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 376720923c1dSRichard Henderson } 3768a68a6146SBalamuruhan S } 3769a68a6146SBalamuruhan S 377020ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 377120ba8504SRichard Henderson { 377220ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 377320ba8504SRichard Henderson } 377420ba8504SRichard Henderson 377520ba8504SRichard Henderson #ifdef TARGET_PPC64 377620ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 377720ba8504SRichard Henderson { 377820ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 377920ba8504SRichard Henderson } 3780a68a6146SBalamuruhan S #endif 3781a68a6146SBalamuruhan S 378214776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 37839deb041cSRichard Henderson { 37849deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 37859deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 37869deb041cSRichard Henderson TCGv src, discard; 37879deb041cSRichard Henderson 37889deb041cSRichard Henderson gen_addr_register(ctx, EA); 37899deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 37909deb041cSRichard Henderson discard = tcg_temp_new(); 37919deb041cSRichard Henderson 37929deb041cSRichard Henderson memop |= MO_ALIGN; 37939deb041cSRichard Henderson switch (gpr_FC) { 37949deb041cSRichard Henderson case 0: /* add and Store */ 37959deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37969deb041cSRichard Henderson break; 37979deb041cSRichard Henderson case 1: /* xor and Store */ 37989deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37999deb041cSRichard Henderson break; 38009deb041cSRichard Henderson case 2: /* Or and Store */ 38019deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38029deb041cSRichard Henderson break; 38039deb041cSRichard Henderson case 3: /* 'and' and Store */ 38049deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38059deb041cSRichard Henderson break; 38069deb041cSRichard Henderson case 4: /* Store max unsigned */ 3807b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3808b8ce0f86SRichard Henderson break; 38099deb041cSRichard Henderson case 5: /* Store max signed */ 3810b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3811b8ce0f86SRichard Henderson break; 38129deb041cSRichard Henderson case 6: /* Store min unsigned */ 3813b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3814b8ce0f86SRichard Henderson break; 38159deb041cSRichard Henderson case 7: /* Store min signed */ 3816b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3817b8ce0f86SRichard Henderson break; 38189deb041cSRichard Henderson case 24: /* Store twin */ 38197fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 38207fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 38217fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 38227fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 38237fbc2b20SRichard Henderson } else { 38247fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 38257fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 38267fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 38277fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 38287fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 38297fbc2b20SRichard Henderson 38307fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 38317fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 38327fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 38337fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 38347fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 38357fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 38367fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 38377fbc2b20SRichard Henderson 38387fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 38397fbc2b20SRichard Henderson tcg_temp_free(s2); 38407fbc2b20SRichard Henderson tcg_temp_free(s); 38417fbc2b20SRichard Henderson tcg_temp_free(t2); 38427fbc2b20SRichard Henderson tcg_temp_free(t); 38437fbc2b20SRichard Henderson } 38449deb041cSRichard Henderson break; 38459deb041cSRichard Henderson default: 38469deb041cSRichard Henderson /* invoke data storage error handler */ 38479deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 38489deb041cSRichard Henderson } 38499deb041cSRichard Henderson tcg_temp_free(discard); 38509deb041cSRichard Henderson tcg_temp_free(EA); 3851a3401188SBalamuruhan S } 3852a3401188SBalamuruhan S 38539deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 38549deb041cSRichard Henderson { 38559deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 38569deb041cSRichard Henderson } 38579deb041cSRichard Henderson 38589deb041cSRichard Henderson #ifdef TARGET_PPC64 38599deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 38609deb041cSRichard Henderson { 38619deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 38629deb041cSRichard Henderson } 3863a3401188SBalamuruhan S #endif 3864a3401188SBalamuruhan S 386514776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3866fcf5ef2aSThomas Huth { 3867253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3868253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3869d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3870d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3871fcf5ef2aSThomas Huth 3872d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3873d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3874d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3875d8b86898SRichard Henderson tcg_temp_free(t0); 3876253ce7b2SNikunj A Dadhania 3877253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3878253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3879253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3880253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3881253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3882253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3883253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3884253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3885253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3886253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3887253ce7b2SNikunj A Dadhania 3888fcf5ef2aSThomas Huth gen_set_label(l1); 38894771df23SNikunj A Dadhania 3890efe843d8SDavid Gibson /* 3891efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3892efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3893efe843d8SDavid Gibson */ 38944771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3895253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3896253ce7b2SNikunj A Dadhania 3897253ce7b2SNikunj A Dadhania gen_set_label(l2); 3898fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3899fcf5ef2aSThomas Huth } 3900fcf5ef2aSThomas Huth 3901fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3902fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3903fcf5ef2aSThomas Huth { \ 3904d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3905fcf5ef2aSThomas Huth } 3906fcf5ef2aSThomas Huth 3907fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3908fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3909fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3910fcf5ef2aSThomas Huth 3911fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3912fcf5ef2aSThomas Huth /* ldarx */ 3913fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3914fcf5ef2aSThomas Huth /* stdcx. */ 3915fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3916fcf5ef2aSThomas Huth 3917fcf5ef2aSThomas Huth /* lqarx */ 3918fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3919fcf5ef2aSThomas Huth { 3920fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 392194bf2658SRichard Henderson TCGv EA, hi, lo; 3922fcf5ef2aSThomas Huth 3923fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3924fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3925fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3926fcf5ef2aSThomas Huth return; 3927fcf5ef2aSThomas Huth } 3928fcf5ef2aSThomas Huth 3929fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 393094bf2658SRichard Henderson EA = tcg_temp_new(); 3931fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 393294bf2658SRichard Henderson 393394bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 393494bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 393594bf2658SRichard Henderson hi = cpu_gpr[rd]; 393694bf2658SRichard Henderson 393794bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3938f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 393994bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 394094bf2658SRichard Henderson if (ctx->le_mode) { 394168e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 394294bf2658SRichard Henderson ctx->mem_idx)); 394394bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3944fcf5ef2aSThomas Huth } else { 394568e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 394694bf2658SRichard Henderson ctx->mem_idx)); 394794bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3948fcf5ef2aSThomas Huth } 394994bf2658SRichard Henderson tcg_temp_free_i32(oi); 395094bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3951f34ec0f6SRichard Henderson } else { 395294bf2658SRichard Henderson /* Restart with exclusive lock. */ 395394bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 395494bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 395594bf2658SRichard Henderson tcg_temp_free(EA); 395694bf2658SRichard Henderson return; 3957f34ec0f6SRichard Henderson } 395894bf2658SRichard Henderson } else if (ctx->le_mode) { 395994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3960fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3961fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 396294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 396394bf2658SRichard Henderson } else { 396494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 396594bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 396694bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 396794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 396894bf2658SRichard Henderson } 3969fcf5ef2aSThomas Huth tcg_temp_free(EA); 397094bf2658SRichard Henderson 397194bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 397294bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3973fcf5ef2aSThomas Huth } 3974fcf5ef2aSThomas Huth 3975fcf5ef2aSThomas Huth /* stqcx. */ 3976fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3977fcf5ef2aSThomas Huth { 39784a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 39794a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3980fcf5ef2aSThomas Huth 39814a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3982fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3983fcf5ef2aSThomas Huth return; 3984fcf5ef2aSThomas Huth } 39854a9b3c5dSRichard Henderson 3986fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 39874a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3988fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3989fcf5ef2aSThomas Huth 39904a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 39914a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 39924a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3993fcf5ef2aSThomas Huth 39944a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3995f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 399668e33d86SRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 39974a9b3c5dSRichard Henderson if (ctx->le_mode) { 3998f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3999f34ec0f6SRichard Henderson EA, lo, hi, oi); 4000fcf5ef2aSThomas Huth } else { 4001f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4002f34ec0f6SRichard Henderson EA, lo, hi, oi); 4003fcf5ef2aSThomas Huth } 4004f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4005f34ec0f6SRichard Henderson } else { 40064a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 40074a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 40084a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4009f34ec0f6SRichard Henderson } 4010fcf5ef2aSThomas Huth tcg_temp_free(EA); 40114a9b3c5dSRichard Henderson } else { 40124a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 40134a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 40144a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 40154a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4016fcf5ef2aSThomas Huth 40174a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 40184a9b3c5dSRichard Henderson tcg_temp_free(EA); 40194a9b3c5dSRichard Henderson 40204a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 40214a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40224a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 40234a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 40244a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40254a9b3c5dSRichard Henderson 40264a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40274a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 40284a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40294a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 40304a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 40314a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40324a9b3c5dSRichard Henderson 40334a9b3c5dSRichard Henderson /* Success */ 40344a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 40354a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40364a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 40374a9b3c5dSRichard Henderson 40384a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40394a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 40404a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 40414a9b3c5dSRichard Henderson 40424a9b3c5dSRichard Henderson gen_set_label(lab_fail); 40434a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40444a9b3c5dSRichard Henderson 40454a9b3c5dSRichard Henderson gen_set_label(lab_over); 40464a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 40474a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 40484a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 40494a9b3c5dSRichard Henderson } 40504a9b3c5dSRichard Henderson } 4051fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4052fcf5ef2aSThomas Huth 4053fcf5ef2aSThomas Huth /* sync */ 4054fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4055fcf5ef2aSThomas Huth { 4056fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4057fcf5ef2aSThomas Huth 4058fcf5ef2aSThomas Huth /* 4059fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4060fcf5ef2aSThomas Huth * 4061fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4062fcf5ef2aSThomas Huth * 4063fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4064fcf5ef2aSThomas Huth * check MSR_PR as well. 4065fcf5ef2aSThomas Huth */ 4066fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4067fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4068fcf5ef2aSThomas Huth } 40694771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4070fcf5ef2aSThomas Huth } 4071fcf5ef2aSThomas Huth 4072fcf5ef2aSThomas Huth /* wait */ 4073fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4074fcf5ef2aSThomas Huth { 4075fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4076fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4077fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4078fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4079fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4080b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4081fcf5ef2aSThomas Huth } 4082fcf5ef2aSThomas Huth 4083fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4084fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4085fcf5ef2aSThomas Huth { 4086fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4087fcf5ef2aSThomas Huth GEN_PRIV; 4088fcf5ef2aSThomas Huth #else 4089fcf5ef2aSThomas Huth TCGv_i32 t; 4090fcf5ef2aSThomas Huth 4091fcf5ef2aSThomas Huth CHK_HV; 4092fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4093fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4094fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4095154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4096154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4097fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4098fcf5ef2aSThomas Huth } 4099fcf5ef2aSThomas Huth 4100fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4101fcf5ef2aSThomas Huth { 4102fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4103fcf5ef2aSThomas Huth GEN_PRIV; 4104fcf5ef2aSThomas Huth #else 4105fcf5ef2aSThomas Huth TCGv_i32 t; 4106fcf5ef2aSThomas Huth 4107fcf5ef2aSThomas Huth CHK_HV; 4108fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4109fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4110fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4111154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4112154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4113fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4114fcf5ef2aSThomas Huth } 4115fcf5ef2aSThomas Huth 4116cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4117cdee0e72SNikunj A Dadhania { 411821c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 411921c0d66aSBenjamin Herrenschmidt GEN_PRIV; 412021c0d66aSBenjamin Herrenschmidt #else 412121c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 412221c0d66aSBenjamin Herrenschmidt 412321c0d66aSBenjamin Herrenschmidt CHK_HV; 412421c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 412521c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 412621c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 412721c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 412821c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 412921c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4130cdee0e72SNikunj A Dadhania } 4131cdee0e72SNikunj A Dadhania 4132fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4133fcf5ef2aSThomas Huth { 4134fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4135fcf5ef2aSThomas Huth GEN_PRIV; 4136fcf5ef2aSThomas Huth #else 4137fcf5ef2aSThomas Huth TCGv_i32 t; 4138fcf5ef2aSThomas Huth 4139fcf5ef2aSThomas Huth CHK_HV; 4140fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4141fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4142fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4143154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4144154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4145fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4146fcf5ef2aSThomas Huth } 4147fcf5ef2aSThomas Huth 4148fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4149fcf5ef2aSThomas Huth { 4150fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4151fcf5ef2aSThomas Huth GEN_PRIV; 4152fcf5ef2aSThomas Huth #else 4153fcf5ef2aSThomas Huth TCGv_i32 t; 4154fcf5ef2aSThomas Huth 4155fcf5ef2aSThomas Huth CHK_HV; 4156fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4157fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4158fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4159154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4160154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4161fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4162fcf5ef2aSThomas Huth } 4163fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4164fcf5ef2aSThomas Huth 4165fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4166fcf5ef2aSThomas Huth { 4167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4168efe843d8SDavid Gibson if (ctx->has_cfar) { 4169fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4170efe843d8SDavid Gibson } 4171fcf5ef2aSThomas Huth #endif 4172fcf5ef2aSThomas Huth } 4173fcf5ef2aSThomas Huth 4174*46d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 4175*46d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 4176*46d396bdSDaniel Henrique Barboza { 4177*46d396bdSDaniel Henrique Barboza /* 4178*46d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 4179*46d396bdSDaniel Henrique Barboza * instructions. 4180*46d396bdSDaniel Henrique Barboza */ 4181*46d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 4182*46d396bdSDaniel Henrique Barboza return; 4183*46d396bdSDaniel Henrique Barboza } 4184*46d396bdSDaniel Henrique Barboza 4185*46d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4186*46d396bdSDaniel Henrique Barboza /* 4187*46d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 4188*46d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 4189*46d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 4190*46d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 4191*46d396bdSDaniel Henrique Barboza */ 4192*46d396bdSDaniel Henrique Barboza gen_icount_io_start(ctx); 4193*46d396bdSDaniel Henrique Barboza 4194*46d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4195*46d396bdSDaniel Henrique Barboza #else 4196*46d396bdSDaniel Henrique Barboza /* 4197*46d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 4198*46d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 4199*46d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 4200*46d396bdSDaniel Henrique Barboza */ 4201*46d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 4202*46d396bdSDaniel Henrique Barboza 4203*46d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 4204*46d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4205*46d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 4206*46d396bdSDaniel Henrique Barboza 4207*46d396bdSDaniel Henrique Barboza tcg_temp_free(t0); 4208*46d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 4209*46d396bdSDaniel Henrique Barboza } 4210*46d396bdSDaniel Henrique Barboza #else 4211*46d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 4212*46d396bdSDaniel Henrique Barboza { 4213*46d396bdSDaniel Henrique Barboza return; 4214*46d396bdSDaniel Henrique Barboza } 4215*46d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 4216*46d396bdSDaniel Henrique Barboza 4217fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4218fcf5ef2aSThomas Huth { 42196e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4220fcf5ef2aSThomas Huth } 4221fcf5ef2aSThomas Huth 42220e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 42230e3bf489SRoman Kapl { 42249498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 42250e3bf489SRoman Kapl gen_debug_exception(ctx); 42260e3bf489SRoman Kapl } else { 4227*46d396bdSDaniel Henrique Barboza /* 4228*46d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 4229*46d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 4230*46d396bdSDaniel Henrique Barboza */ 4231*46d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4232*46d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4233*46d396bdSDaniel Henrique Barboza } 4234*46d396bdSDaniel Henrique Barboza 42350e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 42360e3bf489SRoman Kapl } 42370e3bf489SRoman Kapl } 42380e3bf489SRoman Kapl 4239fcf5ef2aSThomas Huth /*** Branch ***/ 4240c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4241fcf5ef2aSThomas Huth { 4242fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4243fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4244fcf5ef2aSThomas Huth } 4245fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4246*46d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4247fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4248fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 424907ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4250fcf5ef2aSThomas Huth } else { 4251fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 42520e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4253fcf5ef2aSThomas Huth } 4254fcf5ef2aSThomas Huth } 4255fcf5ef2aSThomas Huth 4256fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4257fcf5ef2aSThomas Huth { 4258fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4259fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4260fcf5ef2aSThomas Huth } 4261fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4262fcf5ef2aSThomas Huth } 4263fcf5ef2aSThomas Huth 4264fcf5ef2aSThomas Huth /* b ba bl bla */ 4265fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4266fcf5ef2aSThomas Huth { 4267fcf5ef2aSThomas Huth target_ulong li, target; 4268fcf5ef2aSThomas Huth 4269fcf5ef2aSThomas Huth /* sign extend LI */ 4270fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4271fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4272fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42732c2bcb1bSRichard Henderson target = ctx->cia + li; 4274fcf5ef2aSThomas Huth } else { 4275fcf5ef2aSThomas Huth target = li; 4276fcf5ef2aSThomas Huth } 4277fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4278b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4279fcf5ef2aSThomas Huth } 42802c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4281fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 42826086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4283fcf5ef2aSThomas Huth } 4284fcf5ef2aSThomas Huth 4285fcf5ef2aSThomas Huth #define BCOND_IM 0 4286fcf5ef2aSThomas Huth #define BCOND_LR 1 4287fcf5ef2aSThomas Huth #define BCOND_CTR 2 4288fcf5ef2aSThomas Huth #define BCOND_TAR 3 4289fcf5ef2aSThomas Huth 4290c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4291fcf5ef2aSThomas Huth { 4292fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4293fcf5ef2aSThomas Huth TCGLabel *l1; 4294fcf5ef2aSThomas Huth TCGv target; 42950e3bf489SRoman Kapl 4296fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4297fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4298efe843d8SDavid Gibson if (type == BCOND_CTR) { 4299fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4300efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4301fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4302efe843d8SDavid Gibson } else { 4303fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4304efe843d8SDavid Gibson } 4305fcf5ef2aSThomas Huth } else { 4306f764718dSRichard Henderson target = NULL; 4307fcf5ef2aSThomas Huth } 4308efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4309b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4310efe843d8SDavid Gibson } 4311fcf5ef2aSThomas Huth l1 = gen_new_label(); 4312fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4313fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4314fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4315fa200c95SGreg Kurz 4316fa200c95SGreg Kurz if (type == BCOND_CTR) { 4317fa200c95SGreg Kurz /* 4318fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4319fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4320fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 432115d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 432215d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 432315d68c5eSGreg Kurz * it basically useless and thus never used in real code. 432415d68c5eSGreg Kurz * 432515d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 432615d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 432715d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 432815d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 432915d68c5eSGreg Kurz * doing anything else harmful. 4330fa200c95SGreg Kurz */ 4331d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4332fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 43339acc95cdSGreg Kurz tcg_temp_free(temp); 43349acc95cdSGreg Kurz tcg_temp_free(target); 4335fcf5ef2aSThomas Huth return; 4336fcf5ef2aSThomas Huth } 4337fa200c95SGreg Kurz 4338fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4339fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4340fa200c95SGreg Kurz } else { 4341fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4342fa200c95SGreg Kurz } 4343fa200c95SGreg Kurz if (bo & 0x2) { 4344fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4345fa200c95SGreg Kurz } else { 4346fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4347fa200c95SGreg Kurz } 4348fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4349fa200c95SGreg Kurz } else { 4350fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4351fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4352fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4353fcf5ef2aSThomas Huth } else { 4354fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4355fcf5ef2aSThomas Huth } 4356fcf5ef2aSThomas Huth if (bo & 0x2) { 4357fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4358fcf5ef2aSThomas Huth } else { 4359fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4360fcf5ef2aSThomas Huth } 4361fa200c95SGreg Kurz } 4362fcf5ef2aSThomas Huth tcg_temp_free(temp); 4363fcf5ef2aSThomas Huth } 4364fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4365fcf5ef2aSThomas Huth /* Test CR */ 4366fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4367fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4368fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4369fcf5ef2aSThomas Huth 4370fcf5ef2aSThomas Huth if (bo & 0x8) { 4371fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4372fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4373fcf5ef2aSThomas Huth } else { 4374fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4375fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4376fcf5ef2aSThomas Huth } 4377fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4378fcf5ef2aSThomas Huth } 43792c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4380fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4381fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4382fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43832c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4384fcf5ef2aSThomas Huth } else { 4385fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4386fcf5ef2aSThomas Huth } 4387fcf5ef2aSThomas Huth } else { 4388fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4389fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4390fcf5ef2aSThomas Huth } else { 4391fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4392fcf5ef2aSThomas Huth } 43930e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4394c4a2e3a9SRichard Henderson tcg_temp_free(target); 4395c4a2e3a9SRichard Henderson } 4396fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 43970e3bf489SRoman Kapl /* fallthrough case */ 4398fcf5ef2aSThomas Huth gen_set_label(l1); 4399b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4400fcf5ef2aSThomas Huth } 44016086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4402fcf5ef2aSThomas Huth } 4403fcf5ef2aSThomas Huth 4404fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4405fcf5ef2aSThomas Huth { 4406fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4407fcf5ef2aSThomas Huth } 4408fcf5ef2aSThomas Huth 4409fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4410fcf5ef2aSThomas Huth { 4411fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4412fcf5ef2aSThomas Huth } 4413fcf5ef2aSThomas Huth 4414fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4415fcf5ef2aSThomas Huth { 4416fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4417fcf5ef2aSThomas Huth } 4418fcf5ef2aSThomas Huth 4419fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4420fcf5ef2aSThomas Huth { 4421fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4422fcf5ef2aSThomas Huth } 4423fcf5ef2aSThomas Huth 4424fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4425fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4426fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4427fcf5ef2aSThomas Huth { \ 4428fcf5ef2aSThomas Huth uint8_t bitmask; \ 4429fcf5ef2aSThomas Huth int sh; \ 4430fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4431fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4432fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4433fcf5ef2aSThomas Huth if (sh > 0) \ 4434fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4435fcf5ef2aSThomas Huth else if (sh < 0) \ 4436fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4437fcf5ef2aSThomas Huth else \ 4438fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4439fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4440fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4441fcf5ef2aSThomas Huth if (sh > 0) \ 4442fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4443fcf5ef2aSThomas Huth else if (sh < 0) \ 4444fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4445fcf5ef2aSThomas Huth else \ 4446fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4447fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4448fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4449fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4450fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4451fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4452fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4453fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4454fcf5ef2aSThomas Huth } 4455fcf5ef2aSThomas Huth 4456fcf5ef2aSThomas Huth /* crand */ 4457fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4458fcf5ef2aSThomas Huth /* crandc */ 4459fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4460fcf5ef2aSThomas Huth /* creqv */ 4461fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4462fcf5ef2aSThomas Huth /* crnand */ 4463fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4464fcf5ef2aSThomas Huth /* crnor */ 4465fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4466fcf5ef2aSThomas Huth /* cror */ 4467fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4468fcf5ef2aSThomas Huth /* crorc */ 4469fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4470fcf5ef2aSThomas Huth /* crxor */ 4471fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4472fcf5ef2aSThomas Huth 4473fcf5ef2aSThomas Huth /* mcrf */ 4474fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4475fcf5ef2aSThomas Huth { 4476fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4477fcf5ef2aSThomas Huth } 4478fcf5ef2aSThomas Huth 4479fcf5ef2aSThomas Huth /*** System linkage ***/ 4480fcf5ef2aSThomas Huth 4481fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4482fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4483fcf5ef2aSThomas Huth { 4484fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4485fcf5ef2aSThomas Huth GEN_PRIV; 4486fcf5ef2aSThomas Huth #else 4487efe843d8SDavid Gibson /* 4488efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4489fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4490fcf5ef2aSThomas Huth */ 4491d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4492fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4493fcf5ef2aSThomas Huth return; 4494fcf5ef2aSThomas Huth } 4495fcf5ef2aSThomas Huth /* Restore CPU state */ 4496fcf5ef2aSThomas Huth CHK_SV; 4497f5b6daacSRichard Henderson gen_icount_io_start(ctx); 44982c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4499fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 450059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4501fcf5ef2aSThomas Huth #endif 4502fcf5ef2aSThomas Huth } 4503fcf5ef2aSThomas Huth 4504fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4505fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4506fcf5ef2aSThomas Huth { 4507fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4508fcf5ef2aSThomas Huth GEN_PRIV; 4509fcf5ef2aSThomas Huth #else 4510fcf5ef2aSThomas Huth /* Restore CPU state */ 4511fcf5ef2aSThomas Huth CHK_SV; 4512f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45132c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4514fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 451559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4516fcf5ef2aSThomas Huth #endif 4517fcf5ef2aSThomas Huth } 4518fcf5ef2aSThomas Huth 45193c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45203c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 45213c89b8d6SNicholas Piggin { 45223c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 45233c89b8d6SNicholas Piggin GEN_PRIV; 45243c89b8d6SNicholas Piggin #else 45253c89b8d6SNicholas Piggin /* Restore CPU state */ 45263c89b8d6SNicholas Piggin CHK_SV; 4527f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45282c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 45293c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 453059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 45313c89b8d6SNicholas Piggin #endif 45323c89b8d6SNicholas Piggin } 45333c89b8d6SNicholas Piggin #endif 45343c89b8d6SNicholas Piggin 4535fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4536fcf5ef2aSThomas Huth { 4537fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4538fcf5ef2aSThomas Huth GEN_PRIV; 4539fcf5ef2aSThomas Huth #else 4540fcf5ef2aSThomas Huth /* Restore CPU state */ 4541fcf5ef2aSThomas Huth CHK_HV; 4542fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 454359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4544fcf5ef2aSThomas Huth #endif 4545fcf5ef2aSThomas Huth } 4546fcf5ef2aSThomas Huth #endif 4547fcf5ef2aSThomas Huth 4548fcf5ef2aSThomas Huth /* sc */ 4549fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4550fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4551fcf5ef2aSThomas Huth #else 4552fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 45533c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4554fcf5ef2aSThomas Huth #endif 4555fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4556fcf5ef2aSThomas Huth { 4557fcf5ef2aSThomas Huth uint32_t lev; 4558fcf5ef2aSThomas Huth 4559fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4560fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4561fcf5ef2aSThomas Huth } 4562fcf5ef2aSThomas Huth 45633c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 45643c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45653c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 45663c89b8d6SNicholas Piggin { 4567f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 45683c89b8d6SNicholas Piggin 4569f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 45702c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4571f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 45723c89b8d6SNicholas Piggin 45737a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 45743c89b8d6SNicholas Piggin } 45753c89b8d6SNicholas Piggin #endif 45763c89b8d6SNicholas Piggin #endif 45773c89b8d6SNicholas Piggin 4578fcf5ef2aSThomas Huth /*** Trap ***/ 4579fcf5ef2aSThomas Huth 4580fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4581fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4582fcf5ef2aSThomas Huth { 4583fcf5ef2aSThomas Huth /* Trap never */ 4584fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4585fcf5ef2aSThomas Huth return true; 4586fcf5ef2aSThomas Huth } 4587fcf5ef2aSThomas Huth /* Trap always */ 4588fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4589fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4590fcf5ef2aSThomas Huth return true; 4591fcf5ef2aSThomas Huth } 4592fcf5ef2aSThomas Huth return false; 4593fcf5ef2aSThomas Huth } 4594fcf5ef2aSThomas Huth 4595fcf5ef2aSThomas Huth /* tw */ 4596fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4597fcf5ef2aSThomas Huth { 4598fcf5ef2aSThomas Huth TCGv_i32 t0; 4599fcf5ef2aSThomas Huth 4600fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4601fcf5ef2aSThomas Huth return; 4602fcf5ef2aSThomas Huth } 4603fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4604fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4605fcf5ef2aSThomas Huth t0); 4606fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4607fcf5ef2aSThomas Huth } 4608fcf5ef2aSThomas Huth 4609fcf5ef2aSThomas Huth /* twi */ 4610fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4611fcf5ef2aSThomas Huth { 4612fcf5ef2aSThomas Huth TCGv t0; 4613fcf5ef2aSThomas Huth TCGv_i32 t1; 4614fcf5ef2aSThomas Huth 4615fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4616fcf5ef2aSThomas Huth return; 4617fcf5ef2aSThomas Huth } 4618fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4619fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4620fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4621fcf5ef2aSThomas Huth tcg_temp_free(t0); 4622fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4623fcf5ef2aSThomas Huth } 4624fcf5ef2aSThomas Huth 4625fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4626fcf5ef2aSThomas Huth /* td */ 4627fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4628fcf5ef2aSThomas Huth { 4629fcf5ef2aSThomas Huth TCGv_i32 t0; 4630fcf5ef2aSThomas Huth 4631fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4632fcf5ef2aSThomas Huth return; 4633fcf5ef2aSThomas Huth } 4634fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4635fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4636fcf5ef2aSThomas Huth t0); 4637fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4638fcf5ef2aSThomas Huth } 4639fcf5ef2aSThomas Huth 4640fcf5ef2aSThomas Huth /* tdi */ 4641fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4642fcf5ef2aSThomas Huth { 4643fcf5ef2aSThomas Huth TCGv t0; 4644fcf5ef2aSThomas Huth TCGv_i32 t1; 4645fcf5ef2aSThomas Huth 4646fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4647fcf5ef2aSThomas Huth return; 4648fcf5ef2aSThomas Huth } 4649fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4650fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4651fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4652fcf5ef2aSThomas Huth tcg_temp_free(t0); 4653fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4654fcf5ef2aSThomas Huth } 4655fcf5ef2aSThomas Huth #endif 4656fcf5ef2aSThomas Huth 4657fcf5ef2aSThomas Huth /*** Processor control ***/ 4658fcf5ef2aSThomas Huth 4659fcf5ef2aSThomas Huth /* mcrxr */ 4660fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4661fcf5ef2aSThomas Huth { 4662fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4663fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4664fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4665fcf5ef2aSThomas Huth 4666fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4667fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4668fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4669fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4670fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4671fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4672fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4673fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4674fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4675fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4676fcf5ef2aSThomas Huth 4677fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4678fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4679fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth 4682b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4683b63d0434SNikunj A Dadhania /* mcrxrx */ 4684b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4685b63d0434SNikunj A Dadhania { 4686b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4687b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4688b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4689b63d0434SNikunj A Dadhania 4690b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4691b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4692b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4693b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4694b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4695b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4696b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4697b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4698b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4699b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4700b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4701b63d0434SNikunj A Dadhania } 4702b63d0434SNikunj A Dadhania #endif 4703b63d0434SNikunj A Dadhania 4704fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4705fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4706fcf5ef2aSThomas Huth { 4707fcf5ef2aSThomas Huth uint32_t crm, crn; 4708fcf5ef2aSThomas Huth 4709fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4710fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4711fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4712fcf5ef2aSThomas Huth crn = ctz32(crm); 4713fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4714fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4715fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4716fcf5ef2aSThomas Huth } 4717fcf5ef2aSThomas Huth } else { 4718fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4719fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4720fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4721fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4722fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4723fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4724fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4725fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4726fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4727fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4728fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4729fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4730fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4731fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4732fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4733fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4734fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4735fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4736fcf5ef2aSThomas Huth } 4737fcf5ef2aSThomas Huth } 4738fcf5ef2aSThomas Huth 4739fcf5ef2aSThomas Huth /* mfmsr */ 4740fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4741fcf5ef2aSThomas Huth { 4742fcf5ef2aSThomas Huth CHK_SV; 4743fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4744fcf5ef2aSThomas Huth } 4745fcf5ef2aSThomas Huth 4746fcf5ef2aSThomas Huth /* mfspr */ 4747fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4748fcf5ef2aSThomas Huth { 4749fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4750fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4751fcf5ef2aSThomas Huth 4752fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4753fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4754fcf5ef2aSThomas Huth #else 4755fcf5ef2aSThomas Huth if (ctx->pr) { 4756fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4757fcf5ef2aSThomas Huth } else if (ctx->hv) { 4758fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4759fcf5ef2aSThomas Huth } else { 4760fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4761fcf5ef2aSThomas Huth } 4762fcf5ef2aSThomas Huth #endif 4763fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4764fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4765fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4766fcf5ef2aSThomas Huth } else { 4767fcf5ef2aSThomas Huth /* Privilege exception */ 4768efe843d8SDavid Gibson /* 4769efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4770fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4771fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4772fcf5ef2aSThomas Huth */ 4773fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 477431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 477531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 47762c2bcb1bSRichard Henderson ctx->cia); 4777fcf5ef2aSThomas Huth } 4778fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4779fcf5ef2aSThomas Huth } 4780fcf5ef2aSThomas Huth } else { 4781fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4782fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4783fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4784fcf5ef2aSThomas Huth /* This is a nop */ 4785fcf5ef2aSThomas Huth return; 4786fcf5ef2aSThomas Huth } 4787fcf5ef2aSThomas Huth /* Not defined */ 478831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 478931085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 47902c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4791fcf5ef2aSThomas Huth 4792efe843d8SDavid Gibson /* 4793efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4794efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4795fcf5ef2aSThomas Huth */ 4796fcf5ef2aSThomas Huth if (sprn & 0x10) { 4797fcf5ef2aSThomas Huth if (ctx->pr) { 4798fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4799fcf5ef2aSThomas Huth } 4800fcf5ef2aSThomas Huth } else { 4801fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4802fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4803fcf5ef2aSThomas Huth } 4804fcf5ef2aSThomas Huth } 4805fcf5ef2aSThomas Huth } 4806fcf5ef2aSThomas Huth } 4807fcf5ef2aSThomas Huth 4808fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4809fcf5ef2aSThomas Huth { 4810fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4811fcf5ef2aSThomas Huth } 4812fcf5ef2aSThomas Huth 4813fcf5ef2aSThomas Huth /* mftb */ 4814fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4815fcf5ef2aSThomas Huth { 4816fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4817fcf5ef2aSThomas Huth } 4818fcf5ef2aSThomas Huth 4819fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4820fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4821fcf5ef2aSThomas Huth { 4822fcf5ef2aSThomas Huth uint32_t crm, crn; 4823fcf5ef2aSThomas Huth 4824fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4825fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4826fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4827fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4828fcf5ef2aSThomas Huth crn = ctz32(crm); 4829fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4830fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4831fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4832fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4833fcf5ef2aSThomas Huth } 4834fcf5ef2aSThomas Huth } else { 4835fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4836fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4837fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4838fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4839fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4840fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4841fcf5ef2aSThomas Huth } 4842fcf5ef2aSThomas Huth } 4843fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4844fcf5ef2aSThomas Huth } 4845fcf5ef2aSThomas Huth } 4846fcf5ef2aSThomas Huth 4847fcf5ef2aSThomas Huth /* mtmsr */ 4848fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4849fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4850fcf5ef2aSThomas Huth { 4851caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4852caf590ddSNicholas Piggin gen_invalid(ctx); 4853caf590ddSNicholas Piggin return; 4854caf590ddSNicholas Piggin } 4855caf590ddSNicholas Piggin 4856fcf5ef2aSThomas Huth CHK_SV; 4857fcf5ef2aSThomas Huth 4858fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48596fa5726bSMatheus Ferst TCGv t0, t1; 48606fa5726bSMatheus Ferst target_ulong mask; 48616fa5726bSMatheus Ferst 48626fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48636fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48646fa5726bSMatheus Ferst 4865f5b6daacSRichard Henderson gen_icount_io_start(ctx); 48666fa5726bSMatheus Ferst 4867fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48685ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48696fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4870fcf5ef2aSThomas Huth } else { 48716fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 48726fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 48736fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4874efe843d8SDavid Gibson /* 4875efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4876efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4877efe843d8SDavid Gibson * ppc_store_msr 4878fcf5ef2aSThomas Huth */ 4879b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4880fcf5ef2aSThomas Huth } 48816fa5726bSMatheus Ferst 48826fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48836fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48846fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48856fa5726bSMatheus Ferst 48866fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48876fa5726bSMatheus Ferst 48885ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4889d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 48906fa5726bSMatheus Ferst 48916fa5726bSMatheus Ferst tcg_temp_free(t0); 48926fa5726bSMatheus Ferst tcg_temp_free(t1); 4893fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4894fcf5ef2aSThomas Huth } 4895fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4896fcf5ef2aSThomas Huth 4897fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4898fcf5ef2aSThomas Huth { 4899fcf5ef2aSThomas Huth CHK_SV; 4900fcf5ef2aSThomas Huth 4901fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49026fa5726bSMatheus Ferst TCGv t0, t1; 49036fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 49046fa5726bSMatheus Ferst 49056fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49066fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49076fa5726bSMatheus Ferst 4908f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4909fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49105ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49116fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4912fcf5ef2aSThomas Huth } else { 49136fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 49146fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4915fcf5ef2aSThomas Huth 4916efe843d8SDavid Gibson /* 4917efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4918efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4919efe843d8SDavid Gibson * ppc_store_msr 4920fcf5ef2aSThomas Huth */ 4921b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4922fcf5ef2aSThomas Huth } 49236fa5726bSMatheus Ferst 49246fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 49256fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 49266fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 49276fa5726bSMatheus Ferst 49286fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 49296fa5726bSMatheus Ferst 49305ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4931d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 49326fa5726bSMatheus Ferst 49336fa5726bSMatheus Ferst tcg_temp_free(t0); 49346fa5726bSMatheus Ferst tcg_temp_free(t1); 4935fcf5ef2aSThomas Huth #endif 4936fcf5ef2aSThomas Huth } 4937fcf5ef2aSThomas Huth 4938fcf5ef2aSThomas Huth /* mtspr */ 4939fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4940fcf5ef2aSThomas Huth { 4941fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4942fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4943fcf5ef2aSThomas Huth 4944fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4945fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4946fcf5ef2aSThomas Huth #else 4947fcf5ef2aSThomas Huth if (ctx->pr) { 4948fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4949fcf5ef2aSThomas Huth } else if (ctx->hv) { 4950fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4951fcf5ef2aSThomas Huth } else { 4952fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4953fcf5ef2aSThomas Huth } 4954fcf5ef2aSThomas Huth #endif 4955fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4956fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4957fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4958fcf5ef2aSThomas Huth } else { 4959fcf5ef2aSThomas Huth /* Privilege exception */ 496031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 496131085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 49622c2bcb1bSRichard Henderson ctx->cia); 4963fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4964fcf5ef2aSThomas Huth } 4965fcf5ef2aSThomas Huth } else { 4966fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4967fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4968fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4969fcf5ef2aSThomas Huth /* This is a nop */ 4970fcf5ef2aSThomas Huth return; 4971fcf5ef2aSThomas Huth } 4972fcf5ef2aSThomas Huth 4973fcf5ef2aSThomas Huth /* Not defined */ 497431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 497531085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 49762c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4977fcf5ef2aSThomas Huth 4978fcf5ef2aSThomas Huth 4979efe843d8SDavid Gibson /* 4980efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4981efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4982fcf5ef2aSThomas Huth */ 4983fcf5ef2aSThomas Huth if (sprn & 0x10) { 4984fcf5ef2aSThomas Huth if (ctx->pr) { 4985fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4986fcf5ef2aSThomas Huth } 4987fcf5ef2aSThomas Huth } else { 4988fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4989fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4990fcf5ef2aSThomas Huth } 4991fcf5ef2aSThomas Huth } 4992fcf5ef2aSThomas Huth } 4993fcf5ef2aSThomas Huth } 4994fcf5ef2aSThomas Huth 4995fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4996fcf5ef2aSThomas Huth /* setb */ 4997fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4998fcf5ef2aSThomas Huth { 4999fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 50006f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 50016f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5002fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5003fcf5ef2aSThomas Huth 5004fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5005fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5006fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5007fcf5ef2aSThomas Huth 5008fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5009fcf5ef2aSThomas Huth } 5010fcf5ef2aSThomas Huth #endif 5011fcf5ef2aSThomas Huth 5012fcf5ef2aSThomas Huth /*** Cache management ***/ 5013fcf5ef2aSThomas Huth 5014fcf5ef2aSThomas Huth /* dcbf */ 5015fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5016fcf5ef2aSThomas Huth { 5017fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5018fcf5ef2aSThomas Huth TCGv t0; 5019fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5020fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5021fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5022fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5023fcf5ef2aSThomas Huth tcg_temp_free(t0); 5024fcf5ef2aSThomas Huth } 5025fcf5ef2aSThomas Huth 502650728199SRoman Kapl /* dcbfep (external PID dcbf) */ 502750728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 502850728199SRoman Kapl { 502950728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 503050728199SRoman Kapl TCGv t0; 503150728199SRoman Kapl CHK_SV; 503250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 503350728199SRoman Kapl t0 = tcg_temp_new(); 503450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 503550728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 503650728199SRoman Kapl tcg_temp_free(t0); 503750728199SRoman Kapl } 503850728199SRoman Kapl 5039fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5040fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5041fcf5ef2aSThomas Huth { 5042fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5043fcf5ef2aSThomas Huth GEN_PRIV; 5044fcf5ef2aSThomas Huth #else 5045fcf5ef2aSThomas Huth TCGv EA, val; 5046fcf5ef2aSThomas Huth 5047fcf5ef2aSThomas Huth CHK_SV; 5048fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5049fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5050fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5051fcf5ef2aSThomas Huth val = tcg_temp_new(); 5052fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5053fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5054fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5055fcf5ef2aSThomas Huth tcg_temp_free(val); 5056fcf5ef2aSThomas Huth tcg_temp_free(EA); 5057fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5058fcf5ef2aSThomas Huth } 5059fcf5ef2aSThomas Huth 5060fcf5ef2aSThomas Huth /* dcdst */ 5061fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5062fcf5ef2aSThomas Huth { 5063fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5064fcf5ef2aSThomas Huth TCGv t0; 5065fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5066fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5067fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5068fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5069fcf5ef2aSThomas Huth tcg_temp_free(t0); 5070fcf5ef2aSThomas Huth } 5071fcf5ef2aSThomas Huth 507250728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 507350728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 507450728199SRoman Kapl { 507550728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 507650728199SRoman Kapl TCGv t0; 507750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 507850728199SRoman Kapl t0 = tcg_temp_new(); 507950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 508050728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 508150728199SRoman Kapl tcg_temp_free(t0); 508250728199SRoman Kapl } 508350728199SRoman Kapl 5084fcf5ef2aSThomas Huth /* dcbt */ 5085fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5086fcf5ef2aSThomas Huth { 5087efe843d8SDavid Gibson /* 5088efe843d8SDavid Gibson * interpreted as no-op 5089efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5090efe843d8SDavid Gibson * does not generate any exception 5091fcf5ef2aSThomas Huth */ 5092fcf5ef2aSThomas Huth } 5093fcf5ef2aSThomas Huth 509450728199SRoman Kapl /* dcbtep */ 509550728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 509650728199SRoman Kapl { 5097efe843d8SDavid Gibson /* 5098efe843d8SDavid Gibson * interpreted as no-op 5099efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5100efe843d8SDavid Gibson * does not generate any exception 510150728199SRoman Kapl */ 510250728199SRoman Kapl } 510350728199SRoman Kapl 5104fcf5ef2aSThomas Huth /* dcbtst */ 5105fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5106fcf5ef2aSThomas Huth { 5107efe843d8SDavid Gibson /* 5108efe843d8SDavid Gibson * interpreted as no-op 5109efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5110efe843d8SDavid Gibson * does not generate any exception 5111fcf5ef2aSThomas Huth */ 5112fcf5ef2aSThomas Huth } 5113fcf5ef2aSThomas Huth 511450728199SRoman Kapl /* dcbtstep */ 511550728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 511650728199SRoman Kapl { 5117efe843d8SDavid Gibson /* 5118efe843d8SDavid Gibson * interpreted as no-op 5119efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5120efe843d8SDavid Gibson * does not generate any exception 512150728199SRoman Kapl */ 512250728199SRoman Kapl } 512350728199SRoman Kapl 5124fcf5ef2aSThomas Huth /* dcbtls */ 5125fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5126fcf5ef2aSThomas Huth { 5127fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5128fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5129fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5130fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5131fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5132fcf5ef2aSThomas Huth tcg_temp_free(t0); 5133fcf5ef2aSThomas Huth } 5134fcf5ef2aSThomas Huth 5135fcf5ef2aSThomas Huth /* dcbz */ 5136fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5137fcf5ef2aSThomas Huth { 5138fcf5ef2aSThomas Huth TCGv tcgv_addr; 5139fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5140fcf5ef2aSThomas Huth 5141fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5142fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5143fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5144fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5145fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5146fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5147fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5148fcf5ef2aSThomas Huth } 5149fcf5ef2aSThomas Huth 515050728199SRoman Kapl /* dcbzep */ 515150728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 515250728199SRoman Kapl { 515350728199SRoman Kapl TCGv tcgv_addr; 515450728199SRoman Kapl TCGv_i32 tcgv_op; 515550728199SRoman Kapl 515650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 515750728199SRoman Kapl tcgv_addr = tcg_temp_new(); 515850728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 515950728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 516050728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 516150728199SRoman Kapl tcg_temp_free(tcgv_addr); 516250728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 516350728199SRoman Kapl } 516450728199SRoman Kapl 5165fcf5ef2aSThomas Huth /* dst / dstt */ 5166fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5167fcf5ef2aSThomas Huth { 5168fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5169fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5170fcf5ef2aSThomas Huth } else { 5171fcf5ef2aSThomas Huth /* interpreted as no-op */ 5172fcf5ef2aSThomas Huth } 5173fcf5ef2aSThomas Huth } 5174fcf5ef2aSThomas Huth 5175fcf5ef2aSThomas Huth /* dstst /dststt */ 5176fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5177fcf5ef2aSThomas Huth { 5178fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5179fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5180fcf5ef2aSThomas Huth } else { 5181fcf5ef2aSThomas Huth /* interpreted as no-op */ 5182fcf5ef2aSThomas Huth } 5183fcf5ef2aSThomas Huth 5184fcf5ef2aSThomas Huth } 5185fcf5ef2aSThomas Huth 5186fcf5ef2aSThomas Huth /* dss / dssall */ 5187fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5188fcf5ef2aSThomas Huth { 5189fcf5ef2aSThomas Huth /* interpreted as no-op */ 5190fcf5ef2aSThomas Huth } 5191fcf5ef2aSThomas Huth 5192fcf5ef2aSThomas Huth /* icbi */ 5193fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5194fcf5ef2aSThomas Huth { 5195fcf5ef2aSThomas Huth TCGv t0; 5196fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5197fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5198fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5199fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5200fcf5ef2aSThomas Huth tcg_temp_free(t0); 5201fcf5ef2aSThomas Huth } 5202fcf5ef2aSThomas Huth 520350728199SRoman Kapl /* icbiep */ 520450728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 520550728199SRoman Kapl { 520650728199SRoman Kapl TCGv t0; 520750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 520850728199SRoman Kapl t0 = tcg_temp_new(); 520950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 521050728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 521150728199SRoman Kapl tcg_temp_free(t0); 521250728199SRoman Kapl } 521350728199SRoman Kapl 5214fcf5ef2aSThomas Huth /* Optional: */ 5215fcf5ef2aSThomas Huth /* dcba */ 5216fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5217fcf5ef2aSThomas Huth { 5218efe843d8SDavid Gibson /* 5219efe843d8SDavid Gibson * interpreted as no-op 5220efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5221fcf5ef2aSThomas Huth * but does not generate any exception 5222fcf5ef2aSThomas Huth */ 5223fcf5ef2aSThomas Huth } 5224fcf5ef2aSThomas Huth 5225fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5226fcf5ef2aSThomas Huth /* Supervisor only: */ 5227fcf5ef2aSThomas Huth 5228fcf5ef2aSThomas Huth /* mfsr */ 5229fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5230fcf5ef2aSThomas Huth { 5231fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5232fcf5ef2aSThomas Huth GEN_PRIV; 5233fcf5ef2aSThomas Huth #else 5234fcf5ef2aSThomas Huth TCGv t0; 5235fcf5ef2aSThomas Huth 5236fcf5ef2aSThomas Huth CHK_SV; 5237fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5238fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5239fcf5ef2aSThomas Huth tcg_temp_free(t0); 5240fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5241fcf5ef2aSThomas Huth } 5242fcf5ef2aSThomas Huth 5243fcf5ef2aSThomas Huth /* mfsrin */ 5244fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5245fcf5ef2aSThomas Huth { 5246fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5247fcf5ef2aSThomas Huth GEN_PRIV; 5248fcf5ef2aSThomas Huth #else 5249fcf5ef2aSThomas Huth TCGv t0; 5250fcf5ef2aSThomas Huth 5251fcf5ef2aSThomas Huth CHK_SV; 5252fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5253e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5254fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5255fcf5ef2aSThomas Huth tcg_temp_free(t0); 5256fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5257fcf5ef2aSThomas Huth } 5258fcf5ef2aSThomas Huth 5259fcf5ef2aSThomas Huth /* mtsr */ 5260fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5261fcf5ef2aSThomas Huth { 5262fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5263fcf5ef2aSThomas Huth GEN_PRIV; 5264fcf5ef2aSThomas Huth #else 5265fcf5ef2aSThomas Huth TCGv t0; 5266fcf5ef2aSThomas Huth 5267fcf5ef2aSThomas Huth CHK_SV; 5268fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5269fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5270fcf5ef2aSThomas Huth tcg_temp_free(t0); 5271fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5272fcf5ef2aSThomas Huth } 5273fcf5ef2aSThomas Huth 5274fcf5ef2aSThomas Huth /* mtsrin */ 5275fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5276fcf5ef2aSThomas Huth { 5277fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5278fcf5ef2aSThomas Huth GEN_PRIV; 5279fcf5ef2aSThomas Huth #else 5280fcf5ef2aSThomas Huth TCGv t0; 5281fcf5ef2aSThomas Huth CHK_SV; 5282fcf5ef2aSThomas Huth 5283fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5284e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5285fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5286fcf5ef2aSThomas Huth tcg_temp_free(t0); 5287fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5288fcf5ef2aSThomas Huth } 5289fcf5ef2aSThomas Huth 5290fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5291fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5292fcf5ef2aSThomas Huth 5293fcf5ef2aSThomas Huth /* mfsr */ 5294fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5295fcf5ef2aSThomas Huth { 5296fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5297fcf5ef2aSThomas Huth GEN_PRIV; 5298fcf5ef2aSThomas Huth #else 5299fcf5ef2aSThomas Huth TCGv t0; 5300fcf5ef2aSThomas Huth 5301fcf5ef2aSThomas Huth CHK_SV; 5302fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5303fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5304fcf5ef2aSThomas Huth tcg_temp_free(t0); 5305fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5306fcf5ef2aSThomas Huth } 5307fcf5ef2aSThomas Huth 5308fcf5ef2aSThomas Huth /* mfsrin */ 5309fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5310fcf5ef2aSThomas Huth { 5311fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5312fcf5ef2aSThomas Huth GEN_PRIV; 5313fcf5ef2aSThomas Huth #else 5314fcf5ef2aSThomas Huth TCGv t0; 5315fcf5ef2aSThomas Huth 5316fcf5ef2aSThomas Huth CHK_SV; 5317fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5318e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5319fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5320fcf5ef2aSThomas Huth tcg_temp_free(t0); 5321fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5322fcf5ef2aSThomas Huth } 5323fcf5ef2aSThomas Huth 5324fcf5ef2aSThomas Huth /* mtsr */ 5325fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5326fcf5ef2aSThomas Huth { 5327fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5328fcf5ef2aSThomas Huth GEN_PRIV; 5329fcf5ef2aSThomas Huth #else 5330fcf5ef2aSThomas Huth TCGv t0; 5331fcf5ef2aSThomas Huth 5332fcf5ef2aSThomas Huth CHK_SV; 5333fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5334fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5335fcf5ef2aSThomas Huth tcg_temp_free(t0); 5336fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5337fcf5ef2aSThomas Huth } 5338fcf5ef2aSThomas Huth 5339fcf5ef2aSThomas Huth /* mtsrin */ 5340fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5341fcf5ef2aSThomas Huth { 5342fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5343fcf5ef2aSThomas Huth GEN_PRIV; 5344fcf5ef2aSThomas Huth #else 5345fcf5ef2aSThomas Huth TCGv t0; 5346fcf5ef2aSThomas Huth 5347fcf5ef2aSThomas Huth CHK_SV; 5348fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5349e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5350fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5351fcf5ef2aSThomas Huth tcg_temp_free(t0); 5352fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5353fcf5ef2aSThomas Huth } 5354fcf5ef2aSThomas Huth 5355fcf5ef2aSThomas Huth /* slbmte */ 5356fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5357fcf5ef2aSThomas Huth { 5358fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5359fcf5ef2aSThomas Huth GEN_PRIV; 5360fcf5ef2aSThomas Huth #else 5361fcf5ef2aSThomas Huth CHK_SV; 5362fcf5ef2aSThomas Huth 5363fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5364fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5365fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5366fcf5ef2aSThomas Huth } 5367fcf5ef2aSThomas Huth 5368fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5369fcf5ef2aSThomas Huth { 5370fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5371fcf5ef2aSThomas Huth GEN_PRIV; 5372fcf5ef2aSThomas Huth #else 5373fcf5ef2aSThomas Huth CHK_SV; 5374fcf5ef2aSThomas Huth 5375fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5376fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5377fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5378fcf5ef2aSThomas Huth } 5379fcf5ef2aSThomas Huth 5380fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5381fcf5ef2aSThomas Huth { 5382fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5383fcf5ef2aSThomas Huth GEN_PRIV; 5384fcf5ef2aSThomas Huth #else 5385fcf5ef2aSThomas Huth CHK_SV; 5386fcf5ef2aSThomas Huth 5387fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5388fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5389fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5390fcf5ef2aSThomas Huth } 5391fcf5ef2aSThomas Huth 5392fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5393fcf5ef2aSThomas Huth { 5394fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5395fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5396fcf5ef2aSThomas Huth #else 5397fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5398fcf5ef2aSThomas Huth 5399fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5400fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5401fcf5ef2aSThomas Huth return; 5402fcf5ef2aSThomas Huth } 5403fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5404fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5405fcf5ef2aSThomas Huth l1 = gen_new_label(); 5406fcf5ef2aSThomas Huth l2 = gen_new_label(); 5407fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5408fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5409efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5410fcf5ef2aSThomas Huth tcg_gen_br(l2); 5411fcf5ef2aSThomas Huth gen_set_label(l1); 5412fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5413fcf5ef2aSThomas Huth gen_set_label(l2); 5414fcf5ef2aSThomas Huth #endif 5415fcf5ef2aSThomas Huth } 5416fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5417fcf5ef2aSThomas Huth 5418fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5419fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5420fcf5ef2aSThomas Huth 5421fcf5ef2aSThomas Huth /* tlbia */ 5422fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5423fcf5ef2aSThomas Huth { 5424fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5425fcf5ef2aSThomas Huth GEN_PRIV; 5426fcf5ef2aSThomas Huth #else 5427fcf5ef2aSThomas Huth CHK_HV; 5428fcf5ef2aSThomas Huth 5429fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5430fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5431fcf5ef2aSThomas Huth } 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth /* tlbiel */ 5434fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5435fcf5ef2aSThomas Huth { 5436fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5437fcf5ef2aSThomas Huth GEN_PRIV; 5438fcf5ef2aSThomas Huth #else 543992fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 544092fb92d3SMatheus Ferst 544192fb92d3SMatheus Ferst if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) { 544292fb92d3SMatheus Ferst /* 544392fb92d3SMatheus Ferst * tlbiel is privileged except when PSR=0 and HR=1, making it 544492fb92d3SMatheus Ferst * hypervisor privileged. 544592fb92d3SMatheus Ferst */ 544692fb92d3SMatheus Ferst GEN_PRIV; 544792fb92d3SMatheus Ferst } 5448fcf5ef2aSThomas Huth 5449fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5450fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5451fcf5ef2aSThomas Huth } 5452fcf5ef2aSThomas Huth 5453fcf5ef2aSThomas Huth /* tlbie */ 5454fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5455fcf5ef2aSThomas Huth { 5456fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5457fcf5ef2aSThomas Huth GEN_PRIV; 5458fcf5ef2aSThomas Huth #else 545992fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 5460fcf5ef2aSThomas Huth TCGv_i32 t1; 5461c6fd28fdSSuraj Jitindar Singh 546292fb92d3SMatheus Ferst if (ctx->pr) { 546392fb92d3SMatheus Ferst /* tlbie is privileged... */ 546492fb92d3SMatheus Ferst GEN_PRIV; 546592fb92d3SMatheus Ferst } else if (!ctx->hv) { 546692fb92d3SMatheus Ferst if (!ctx->gtse || (!psr && ctx->hr)) { 546792fb92d3SMatheus Ferst /* 546892fb92d3SMatheus Ferst * ... except when GTSE=0 or when PSR=0 and HR=1, making it 546992fb92d3SMatheus Ferst * hypervisor privileged. 547092fb92d3SMatheus Ferst */ 547192fb92d3SMatheus Ferst GEN_PRIV; 547292fb92d3SMatheus Ferst } 5473c6fd28fdSSuraj Jitindar Singh } 5474fcf5ef2aSThomas Huth 5475fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5476fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5477fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5478fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5479fcf5ef2aSThomas Huth tcg_temp_free(t0); 5480fcf5ef2aSThomas Huth } else { 5481fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5482fcf5ef2aSThomas Huth } 5483fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5484fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5485fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5486fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5487fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5488fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5489fcf5ef2aSThomas Huth } 5490fcf5ef2aSThomas Huth 5491fcf5ef2aSThomas Huth /* tlbsync */ 5492fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5493fcf5ef2aSThomas Huth { 5494fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5495fcf5ef2aSThomas Huth GEN_PRIV; 5496fcf5ef2aSThomas Huth #else 549791c60f12SCédric Le Goater 549891c60f12SCédric Le Goater if (ctx->gtse) { 549991c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 550091c60f12SCédric Le Goater } else { 550191c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 550291c60f12SCédric Le Goater } 5503fcf5ef2aSThomas Huth 5504fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5505fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5506fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5507fcf5ef2aSThomas Huth } 5508fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5509fcf5ef2aSThomas Huth } 5510fcf5ef2aSThomas Huth 5511fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5512fcf5ef2aSThomas Huth /* slbia */ 5513fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5514fcf5ef2aSThomas Huth { 5515fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5516fcf5ef2aSThomas Huth GEN_PRIV; 5517fcf5ef2aSThomas Huth #else 55180418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 55190418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 55200418bf78SNicholas Piggin 5521fcf5ef2aSThomas Huth CHK_SV; 5522fcf5ef2aSThomas Huth 55230418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 55243119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5525fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5526fcf5ef2aSThomas Huth } 5527fcf5ef2aSThomas Huth 5528fcf5ef2aSThomas Huth /* slbie */ 5529fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5530fcf5ef2aSThomas Huth { 5531fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5532fcf5ef2aSThomas Huth GEN_PRIV; 5533fcf5ef2aSThomas Huth #else 5534fcf5ef2aSThomas Huth CHK_SV; 5535fcf5ef2aSThomas Huth 5536fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5537fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5538fcf5ef2aSThomas Huth } 5539a63f1dfcSNikunj A Dadhania 5540a63f1dfcSNikunj A Dadhania /* slbieg */ 5541a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5542a63f1dfcSNikunj A Dadhania { 5543a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5544a63f1dfcSNikunj A Dadhania GEN_PRIV; 5545a63f1dfcSNikunj A Dadhania #else 5546a63f1dfcSNikunj A Dadhania CHK_SV; 5547a63f1dfcSNikunj A Dadhania 5548a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5549a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5550a63f1dfcSNikunj A Dadhania } 5551a63f1dfcSNikunj A Dadhania 555262d897caSNikunj A Dadhania /* slbsync */ 555362d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 555462d897caSNikunj A Dadhania { 555562d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 555662d897caSNikunj A Dadhania GEN_PRIV; 555762d897caSNikunj A Dadhania #else 555862d897caSNikunj A Dadhania CHK_SV; 555962d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 556062d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 556162d897caSNikunj A Dadhania } 556262d897caSNikunj A Dadhania 5563fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5564fcf5ef2aSThomas Huth 5565fcf5ef2aSThomas Huth /*** External control ***/ 5566fcf5ef2aSThomas Huth /* Optional: */ 5567fcf5ef2aSThomas Huth 5568fcf5ef2aSThomas Huth /* eciwx */ 5569fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5570fcf5ef2aSThomas Huth { 5571fcf5ef2aSThomas Huth TCGv t0; 5572fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5573fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5574fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5575fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5576c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5577c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5578fcf5ef2aSThomas Huth tcg_temp_free(t0); 5579fcf5ef2aSThomas Huth } 5580fcf5ef2aSThomas Huth 5581fcf5ef2aSThomas Huth /* ecowx */ 5582fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5583fcf5ef2aSThomas Huth { 5584fcf5ef2aSThomas Huth TCGv t0; 5585fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5586fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5587fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5588fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5589c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5590c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5591fcf5ef2aSThomas Huth tcg_temp_free(t0); 5592fcf5ef2aSThomas Huth } 5593fcf5ef2aSThomas Huth 5594fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5595fcf5ef2aSThomas Huth 5596fcf5ef2aSThomas Huth /* abs - abs. */ 5597fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5598fcf5ef2aSThomas Huth { 5599fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5600fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5601fe21b785SRichard Henderson 5602fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5603efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5604fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5605fcf5ef2aSThomas Huth } 5606efe843d8SDavid Gibson } 5607fcf5ef2aSThomas Huth 5608fcf5ef2aSThomas Huth /* abso - abso. */ 5609fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5610fcf5ef2aSThomas Huth { 5611fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5612fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5613fe21b785SRichard Henderson 5614fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5615fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5616fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5617efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5618fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5619fcf5ef2aSThomas Huth } 5620efe843d8SDavid Gibson } 5621fcf5ef2aSThomas Huth 5622fcf5ef2aSThomas Huth /* clcs */ 5623fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5624fcf5ef2aSThomas Huth { 5625fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5626fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5627fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5628fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5629fcf5ef2aSThomas Huth } 5630fcf5ef2aSThomas Huth 5631fcf5ef2aSThomas Huth /* div - div. */ 5632fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5633fcf5ef2aSThomas Huth { 5634fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5635fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5636efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5637fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5638fcf5ef2aSThomas Huth } 5639efe843d8SDavid Gibson } 5640fcf5ef2aSThomas Huth 5641fcf5ef2aSThomas Huth /* divo - divo. */ 5642fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5643fcf5ef2aSThomas Huth { 5644fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5645fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5646efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5647fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5648fcf5ef2aSThomas Huth } 5649efe843d8SDavid Gibson } 5650fcf5ef2aSThomas Huth 5651fcf5ef2aSThomas Huth /* divs - divs. */ 5652fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5653fcf5ef2aSThomas Huth { 5654fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5655fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5656efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5657fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5658fcf5ef2aSThomas Huth } 5659efe843d8SDavid Gibson } 5660fcf5ef2aSThomas Huth 5661fcf5ef2aSThomas Huth /* divso - divso. */ 5662fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5663fcf5ef2aSThomas Huth { 5664fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5665fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5666efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5667fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5668fcf5ef2aSThomas Huth } 5669efe843d8SDavid Gibson } 5670fcf5ef2aSThomas Huth 5671fcf5ef2aSThomas Huth /* doz - doz. */ 5672fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5673fcf5ef2aSThomas Huth { 5674fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5675fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5676efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5677efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5678efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5679efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5680fcf5ef2aSThomas Huth tcg_gen_br(l2); 5681fcf5ef2aSThomas Huth gen_set_label(l1); 5682fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5683fcf5ef2aSThomas Huth gen_set_label(l2); 5684efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5685fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5686fcf5ef2aSThomas Huth } 5687efe843d8SDavid Gibson } 5688fcf5ef2aSThomas Huth 5689fcf5ef2aSThomas Huth /* dozo - dozo. */ 5690fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5691fcf5ef2aSThomas Huth { 5692fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5693fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5694fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5695fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5696fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5697fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5698fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5699efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5700efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5701fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5702fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5703fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5704fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5705fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5706fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5707fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5708fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5709fcf5ef2aSThomas Huth tcg_gen_br(l2); 5710fcf5ef2aSThomas Huth gen_set_label(l1); 5711fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5712fcf5ef2aSThomas Huth gen_set_label(l2); 5713fcf5ef2aSThomas Huth tcg_temp_free(t0); 5714fcf5ef2aSThomas Huth tcg_temp_free(t1); 5715fcf5ef2aSThomas Huth tcg_temp_free(t2); 5716efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5717fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5718fcf5ef2aSThomas Huth } 5719efe843d8SDavid Gibson } 5720fcf5ef2aSThomas Huth 5721fcf5ef2aSThomas Huth /* dozi */ 5722fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5723fcf5ef2aSThomas Huth { 5724fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5725fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5726fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5727fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5728fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5729fcf5ef2aSThomas Huth tcg_gen_br(l2); 5730fcf5ef2aSThomas Huth gen_set_label(l1); 5731fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5732fcf5ef2aSThomas Huth gen_set_label(l2); 5733efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5734fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5735fcf5ef2aSThomas Huth } 5736efe843d8SDavid Gibson } 5737fcf5ef2aSThomas Huth 5738fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5739fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5740fcf5ef2aSThomas Huth { 5741fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5742fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5743fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5744fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5745fcf5ef2aSThomas Huth 5746fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5747fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5748fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5749fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5750fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5751fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5752fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5753efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5754fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5755efe843d8SDavid Gibson } 5756fcf5ef2aSThomas Huth tcg_temp_free(t0); 5757fcf5ef2aSThomas Huth } 5758fcf5ef2aSThomas Huth 5759fcf5ef2aSThomas Huth /* maskg - maskg. */ 5760fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5761fcf5ef2aSThomas Huth { 5762fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5763fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5764fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5765fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5766fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5767fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5768fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5769fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5770fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5771fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5772fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5773fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5774fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5775fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5776fcf5ef2aSThomas Huth gen_set_label(l1); 5777fcf5ef2aSThomas Huth tcg_temp_free(t0); 5778fcf5ef2aSThomas Huth tcg_temp_free(t1); 5779fcf5ef2aSThomas Huth tcg_temp_free(t2); 5780fcf5ef2aSThomas Huth tcg_temp_free(t3); 5781efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5782fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5783fcf5ef2aSThomas Huth } 5784efe843d8SDavid Gibson } 5785fcf5ef2aSThomas Huth 5786fcf5ef2aSThomas Huth /* maskir - maskir. */ 5787fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5788fcf5ef2aSThomas Huth { 5789fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5790fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5791fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5792fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5793fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5794fcf5ef2aSThomas Huth tcg_temp_free(t0); 5795fcf5ef2aSThomas Huth tcg_temp_free(t1); 5796efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5797fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5798fcf5ef2aSThomas Huth } 5799efe843d8SDavid Gibson } 5800fcf5ef2aSThomas Huth 5801fcf5ef2aSThomas Huth /* mul - mul. */ 5802fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5803fcf5ef2aSThomas Huth { 5804fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5805fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5806fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5807fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5808fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5809fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5810fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5811fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5812fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5813fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5814fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5815fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5816fcf5ef2aSThomas Huth tcg_temp_free(t2); 5817efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5818fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5819fcf5ef2aSThomas Huth } 5820efe843d8SDavid Gibson } 5821fcf5ef2aSThomas Huth 5822fcf5ef2aSThomas Huth /* mulo - mulo. */ 5823fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5824fcf5ef2aSThomas Huth { 5825fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5826fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5827fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5828fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5829fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5830fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5831fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5832fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5833fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5834fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5835fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5836fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5837fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5838fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5839fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5840fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5841fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5842fcf5ef2aSThomas Huth gen_set_label(l1); 5843fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5844fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5845fcf5ef2aSThomas Huth tcg_temp_free(t2); 5846efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5847fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5848fcf5ef2aSThomas Huth } 5849efe843d8SDavid Gibson } 5850fcf5ef2aSThomas Huth 5851fcf5ef2aSThomas Huth /* nabs - nabs. */ 5852fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5853fcf5ef2aSThomas Huth { 5854fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5855fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5856fe21b785SRichard Henderson 5857fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5858fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5859efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5860fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5861fcf5ef2aSThomas Huth } 5862efe843d8SDavid Gibson } 5863fcf5ef2aSThomas Huth 5864fcf5ef2aSThomas Huth /* nabso - nabso. */ 5865fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5866fcf5ef2aSThomas Huth { 5867fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5868fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5869fe21b785SRichard Henderson 5870fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5871fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5872fcf5ef2aSThomas Huth /* nabs never overflows */ 5873fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5874efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5875fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5876fcf5ef2aSThomas Huth } 5877efe843d8SDavid Gibson } 5878fcf5ef2aSThomas Huth 5879fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5880fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5881fcf5ef2aSThomas Huth { 5882fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5883fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5884fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5885fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5886fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5887fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5888efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5889efe843d8SDavid Gibson ~MASK(mb, me)); 5890fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5891fcf5ef2aSThomas Huth tcg_temp_free(t0); 5892efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5893fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5894fcf5ef2aSThomas Huth } 5895efe843d8SDavid Gibson } 5896fcf5ef2aSThomas Huth 5897fcf5ef2aSThomas Huth /* rrib - rrib. */ 5898fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5899fcf5ef2aSThomas Huth { 5900fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5901fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5902fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5903fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5904fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5905fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5906fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5907fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5908fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5909fcf5ef2aSThomas Huth tcg_temp_free(t0); 5910fcf5ef2aSThomas Huth tcg_temp_free(t1); 5911efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5912fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5913fcf5ef2aSThomas Huth } 5914efe843d8SDavid Gibson } 5915fcf5ef2aSThomas Huth 5916fcf5ef2aSThomas Huth /* sle - sle. */ 5917fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5918fcf5ef2aSThomas Huth { 5919fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5920fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5921fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5922fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5923fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5924fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5925fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5926fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5927fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5928fcf5ef2aSThomas Huth tcg_temp_free(t0); 5929fcf5ef2aSThomas Huth tcg_temp_free(t1); 5930efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5931fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5932fcf5ef2aSThomas Huth } 5933efe843d8SDavid Gibson } 5934fcf5ef2aSThomas Huth 5935fcf5ef2aSThomas Huth /* sleq - sleq. */ 5936fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5937fcf5ef2aSThomas Huth { 5938fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5939fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5940fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5941fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5942fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5943fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5944fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5945fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5946fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5947fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5948fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5949fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5950fcf5ef2aSThomas Huth tcg_temp_free(t0); 5951fcf5ef2aSThomas Huth tcg_temp_free(t1); 5952fcf5ef2aSThomas Huth tcg_temp_free(t2); 5953efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5954fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5955fcf5ef2aSThomas Huth } 5956efe843d8SDavid Gibson } 5957fcf5ef2aSThomas Huth 5958fcf5ef2aSThomas Huth /* sliq - sliq. */ 5959fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5960fcf5ef2aSThomas Huth { 5961fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5962fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5963fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5964fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5965fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5966fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5967fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5968fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5969fcf5ef2aSThomas Huth tcg_temp_free(t0); 5970fcf5ef2aSThomas Huth tcg_temp_free(t1); 5971efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5972fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5973fcf5ef2aSThomas Huth } 5974efe843d8SDavid Gibson } 5975fcf5ef2aSThomas Huth 5976fcf5ef2aSThomas Huth /* slliq - slliq. */ 5977fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5978fcf5ef2aSThomas Huth { 5979fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5980fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5981fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5982fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5983fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5984fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5985fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5986fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5987fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5988fcf5ef2aSThomas Huth tcg_temp_free(t0); 5989fcf5ef2aSThomas Huth tcg_temp_free(t1); 5990efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5991fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5992fcf5ef2aSThomas Huth } 5993efe843d8SDavid Gibson } 5994fcf5ef2aSThomas Huth 5995fcf5ef2aSThomas Huth /* sllq - sllq. */ 5996fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5997fcf5ef2aSThomas Huth { 5998fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5999fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6000fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6001fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6002fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6003fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6004fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6005fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6006fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6007fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6008fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6009fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6010fcf5ef2aSThomas Huth tcg_gen_br(l2); 6011fcf5ef2aSThomas Huth gen_set_label(l1); 6012fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6013fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6014fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6015fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6016fcf5ef2aSThomas Huth gen_set_label(l2); 6017fcf5ef2aSThomas Huth tcg_temp_free(t0); 6018fcf5ef2aSThomas Huth tcg_temp_free(t1); 6019fcf5ef2aSThomas Huth tcg_temp_free(t2); 6020efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6021fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6022fcf5ef2aSThomas Huth } 6023efe843d8SDavid Gibson } 6024fcf5ef2aSThomas Huth 6025fcf5ef2aSThomas Huth /* slq - slq. */ 6026fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6027fcf5ef2aSThomas Huth { 6028fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6029fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6030fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6031fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6032fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6033fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6034fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6035fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6036fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6037fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6038fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6039fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6040fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6041fcf5ef2aSThomas Huth gen_set_label(l1); 6042fcf5ef2aSThomas Huth tcg_temp_free(t0); 6043fcf5ef2aSThomas Huth tcg_temp_free(t1); 6044efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6045fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6046fcf5ef2aSThomas Huth } 6047efe843d8SDavid Gibson } 6048fcf5ef2aSThomas Huth 6049fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6050fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6051fcf5ef2aSThomas Huth { 6052fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6053fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6054fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6055fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6056fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6057fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6058fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6059fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6060fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6061fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6062fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6063fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6064fcf5ef2aSThomas Huth gen_set_label(l1); 6065fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6066fcf5ef2aSThomas Huth tcg_temp_free(t0); 6067fcf5ef2aSThomas Huth tcg_temp_free(t1); 6068efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6069fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6070fcf5ef2aSThomas Huth } 6071efe843d8SDavid Gibson } 6072fcf5ef2aSThomas Huth 6073fcf5ef2aSThomas Huth /* sraq - sraq. */ 6074fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6075fcf5ef2aSThomas Huth { 6076fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6077fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6078fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6079fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6080fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6081fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6082fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6083fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6084fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6085fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6086fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6087fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6088fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6089fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6090fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6091fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6092fcf5ef2aSThomas Huth gen_set_label(l1); 6093fcf5ef2aSThomas Huth tcg_temp_free(t0); 6094fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6095fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6096fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6097fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6098fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6099fcf5ef2aSThomas Huth gen_set_label(l2); 6100fcf5ef2aSThomas Huth tcg_temp_free(t1); 6101fcf5ef2aSThomas Huth tcg_temp_free(t2); 6102efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6103fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6104fcf5ef2aSThomas Huth } 6105efe843d8SDavid Gibson } 6106fcf5ef2aSThomas Huth 6107fcf5ef2aSThomas Huth /* sre - sre. */ 6108fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6109fcf5ef2aSThomas Huth { 6110fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6111fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6112fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6113fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6114fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6115fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6116fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6117fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6118fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6119fcf5ef2aSThomas Huth tcg_temp_free(t0); 6120fcf5ef2aSThomas Huth tcg_temp_free(t1); 6121efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6122fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6123fcf5ef2aSThomas Huth } 6124efe843d8SDavid Gibson } 6125fcf5ef2aSThomas Huth 6126fcf5ef2aSThomas Huth /* srea - srea. */ 6127fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6128fcf5ef2aSThomas Huth { 6129fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6130fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6131fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6132fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6133fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6134fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6135fcf5ef2aSThomas Huth tcg_temp_free(t0); 6136fcf5ef2aSThomas Huth tcg_temp_free(t1); 6137efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6138fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6139fcf5ef2aSThomas Huth } 6140efe843d8SDavid Gibson } 6141fcf5ef2aSThomas Huth 6142fcf5ef2aSThomas Huth /* sreq */ 6143fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6144fcf5ef2aSThomas Huth { 6145fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6146fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6147fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6148fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6149fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6150fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6151fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6152fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6153fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6154fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6155fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6156fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6157fcf5ef2aSThomas Huth tcg_temp_free(t0); 6158fcf5ef2aSThomas Huth tcg_temp_free(t1); 6159fcf5ef2aSThomas Huth tcg_temp_free(t2); 6160efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6161fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6162fcf5ef2aSThomas Huth } 6163efe843d8SDavid Gibson } 6164fcf5ef2aSThomas Huth 6165fcf5ef2aSThomas Huth /* sriq */ 6166fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6167fcf5ef2aSThomas Huth { 6168fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6169fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6170fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6171fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6172fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6173fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6174fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6175fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6176fcf5ef2aSThomas Huth tcg_temp_free(t0); 6177fcf5ef2aSThomas Huth tcg_temp_free(t1); 6178efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6179fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6180fcf5ef2aSThomas Huth } 6181efe843d8SDavid Gibson } 6182fcf5ef2aSThomas Huth 6183fcf5ef2aSThomas Huth /* srliq */ 6184fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6185fcf5ef2aSThomas Huth { 6186fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6187fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6188fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6189fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6190fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6191fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6192fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6193fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6194fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6195fcf5ef2aSThomas Huth tcg_temp_free(t0); 6196fcf5ef2aSThomas Huth tcg_temp_free(t1); 6197efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6198fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6199fcf5ef2aSThomas Huth } 6200efe843d8SDavid Gibson } 6201fcf5ef2aSThomas Huth 6202fcf5ef2aSThomas Huth /* srlq */ 6203fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6204fcf5ef2aSThomas Huth { 6205fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6206fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6207fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6208fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6209fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6210fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6211fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6212fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6213fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6214fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6215fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6216fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6217fcf5ef2aSThomas Huth tcg_gen_br(l2); 6218fcf5ef2aSThomas Huth gen_set_label(l1); 6219fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6220fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6221fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6222fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6223fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6224fcf5ef2aSThomas Huth gen_set_label(l2); 6225fcf5ef2aSThomas Huth tcg_temp_free(t0); 6226fcf5ef2aSThomas Huth tcg_temp_free(t1); 6227fcf5ef2aSThomas Huth tcg_temp_free(t2); 6228efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6229fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6230fcf5ef2aSThomas Huth } 6231efe843d8SDavid Gibson } 6232fcf5ef2aSThomas Huth 6233fcf5ef2aSThomas Huth /* srq */ 6234fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6235fcf5ef2aSThomas Huth { 6236fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6237fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6238fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6239fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6240fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6241fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6242fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6243fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6244fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6245fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6246fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6247fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6248fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6249fcf5ef2aSThomas Huth gen_set_label(l1); 6250fcf5ef2aSThomas Huth tcg_temp_free(t0); 6251fcf5ef2aSThomas Huth tcg_temp_free(t1); 6252efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6253fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6254fcf5ef2aSThomas Huth } 6255efe843d8SDavid Gibson } 6256fcf5ef2aSThomas Huth 6257fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6258fcf5ef2aSThomas Huth 6259fcf5ef2aSThomas Huth /* dsa */ 6260fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6261fcf5ef2aSThomas Huth { 6262fcf5ef2aSThomas Huth /* XXX: TODO */ 6263fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6264fcf5ef2aSThomas Huth } 6265fcf5ef2aSThomas Huth 6266fcf5ef2aSThomas Huth /* esa */ 6267fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6268fcf5ef2aSThomas Huth { 6269fcf5ef2aSThomas Huth /* XXX: TODO */ 6270fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6271fcf5ef2aSThomas Huth } 6272fcf5ef2aSThomas Huth 6273fcf5ef2aSThomas Huth /* mfrom */ 6274fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6275fcf5ef2aSThomas Huth { 6276fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6277fcf5ef2aSThomas Huth GEN_PRIV; 6278fcf5ef2aSThomas Huth #else 6279fcf5ef2aSThomas Huth CHK_SV; 6280fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6281fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6282fcf5ef2aSThomas Huth } 6283fcf5ef2aSThomas Huth 6284fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6285fcf5ef2aSThomas Huth 6286fcf5ef2aSThomas Huth /* tlbld */ 6287fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6288fcf5ef2aSThomas Huth { 6289fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6290fcf5ef2aSThomas Huth GEN_PRIV; 6291fcf5ef2aSThomas Huth #else 6292fcf5ef2aSThomas Huth CHK_SV; 6293fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6294fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6295fcf5ef2aSThomas Huth } 6296fcf5ef2aSThomas Huth 6297fcf5ef2aSThomas Huth /* tlbli */ 6298fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6299fcf5ef2aSThomas Huth { 6300fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6301fcf5ef2aSThomas Huth GEN_PRIV; 6302fcf5ef2aSThomas Huth #else 6303fcf5ef2aSThomas Huth CHK_SV; 6304fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6305fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6306fcf5ef2aSThomas Huth } 6307fcf5ef2aSThomas Huth 6308fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6309fcf5ef2aSThomas Huth 6310fcf5ef2aSThomas Huth /* clf */ 6311fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6312fcf5ef2aSThomas Huth { 6313fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6314fcf5ef2aSThomas Huth } 6315fcf5ef2aSThomas Huth 6316fcf5ef2aSThomas Huth /* cli */ 6317fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6318fcf5ef2aSThomas Huth { 6319fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6320fcf5ef2aSThomas Huth GEN_PRIV; 6321fcf5ef2aSThomas Huth #else 6322fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6323fcf5ef2aSThomas Huth CHK_SV; 6324fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6325fcf5ef2aSThomas Huth } 6326fcf5ef2aSThomas Huth 6327fcf5ef2aSThomas Huth /* dclst */ 6328fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6329fcf5ef2aSThomas Huth { 6330fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6331fcf5ef2aSThomas Huth } 6332fcf5ef2aSThomas Huth 6333fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6334fcf5ef2aSThomas Huth { 6335fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6336fcf5ef2aSThomas Huth GEN_PRIV; 6337fcf5ef2aSThomas Huth #else 6338fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6339fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6340fcf5ef2aSThomas Huth TCGv t0; 6341fcf5ef2aSThomas Huth 6342fcf5ef2aSThomas Huth CHK_SV; 6343fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6344fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6345e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6346fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6347fcf5ef2aSThomas Huth tcg_temp_free(t0); 6348efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6349fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6350efe843d8SDavid Gibson } 6351fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6352fcf5ef2aSThomas Huth } 6353fcf5ef2aSThomas Huth 6354fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6355fcf5ef2aSThomas Huth { 6356fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6357fcf5ef2aSThomas Huth GEN_PRIV; 6358fcf5ef2aSThomas Huth #else 6359fcf5ef2aSThomas Huth TCGv t0; 6360fcf5ef2aSThomas Huth 6361fcf5ef2aSThomas Huth CHK_SV; 6362fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6363fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6364fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6365fcf5ef2aSThomas Huth tcg_temp_free(t0); 6366fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6367fcf5ef2aSThomas Huth } 6368fcf5ef2aSThomas Huth 6369fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6370fcf5ef2aSThomas Huth { 6371fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6372fcf5ef2aSThomas Huth GEN_PRIV; 6373fcf5ef2aSThomas Huth #else 6374fcf5ef2aSThomas Huth CHK_SV; 6375fcf5ef2aSThomas Huth 6376fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 637759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6378fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6379fcf5ef2aSThomas Huth } 6380fcf5ef2aSThomas Huth 6381fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6382fcf5ef2aSThomas Huth 6383fcf5ef2aSThomas Huth /* BookE specific instructions */ 6384fcf5ef2aSThomas Huth 6385fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6386fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6387fcf5ef2aSThomas Huth { 6388fcf5ef2aSThomas Huth /* XXX: TODO */ 6389fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6390fcf5ef2aSThomas Huth } 6391fcf5ef2aSThomas Huth 6392fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6393fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6394fcf5ef2aSThomas Huth { 6395fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6396fcf5ef2aSThomas Huth GEN_PRIV; 6397fcf5ef2aSThomas Huth #else 6398fcf5ef2aSThomas Huth TCGv t0; 6399fcf5ef2aSThomas Huth 6400fcf5ef2aSThomas Huth CHK_SV; 6401fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6402fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6403fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6404fcf5ef2aSThomas Huth tcg_temp_free(t0); 6405fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6406fcf5ef2aSThomas Huth } 6407fcf5ef2aSThomas Huth 6408fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6409fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6410fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6411fcf5ef2aSThomas Huth { 6412fcf5ef2aSThomas Huth TCGv t0, t1; 6413fcf5ef2aSThomas Huth 6414fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6415fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6416fcf5ef2aSThomas Huth 6417fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6418fcf5ef2aSThomas Huth case 0x05: 6419fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6420fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6421fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6422fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6423fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6424fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6425fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6426fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6427fcf5ef2aSThomas Huth break; 6428fcf5ef2aSThomas Huth case 0x04: 6429fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6430fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6431fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6432fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6433fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6434fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6435fcf5ef2aSThomas Huth break; 6436fcf5ef2aSThomas Huth case 0x01: 6437fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6438fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6439fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6440fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6441fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6442fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6443fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6444fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6445fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6446fcf5ef2aSThomas Huth break; 6447fcf5ef2aSThomas Huth case 0x00: 6448fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6449fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6450fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6451fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6452fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6453fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6454fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6455fcf5ef2aSThomas Huth break; 6456fcf5ef2aSThomas Huth case 0x0D: 6457fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6458fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6459fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6460fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6461fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6462fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6463fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6464fcf5ef2aSThomas Huth break; 6465fcf5ef2aSThomas Huth case 0x0C: 6466fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6467fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6468fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6469fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6470fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6471fcf5ef2aSThomas Huth break; 6472fcf5ef2aSThomas Huth } 6473fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6474fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6475fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6476fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6477fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6478fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6479fcf5ef2aSThomas Huth } else { 6480fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6481fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6482fcf5ef2aSThomas Huth } 6483fcf5ef2aSThomas Huth 6484fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6485fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6486fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6487fcf5ef2aSThomas Huth 6488fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6489fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6490fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6491fcf5ef2aSThomas Huth } 6492fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6493fcf5ef2aSThomas Huth /* Signed */ 6494fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6495fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6496fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6497fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6498fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6499fcf5ef2aSThomas Huth /* Saturate */ 6500fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6501fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6502fcf5ef2aSThomas Huth } 6503fcf5ef2aSThomas Huth } else { 6504fcf5ef2aSThomas Huth /* Unsigned */ 6505fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6506fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6507fcf5ef2aSThomas Huth /* Saturate */ 6508fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6509fcf5ef2aSThomas Huth } 6510fcf5ef2aSThomas Huth } 6511fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6512fcf5ef2aSThomas Huth /* Check overflow */ 6513fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6514fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6515fcf5ef2aSThomas Huth } 6516fcf5ef2aSThomas Huth gen_set_label(l1); 6517fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6518fcf5ef2aSThomas Huth } 6519fcf5ef2aSThomas Huth } else { 6520fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6521fcf5ef2aSThomas Huth } 6522fcf5ef2aSThomas Huth tcg_temp_free(t0); 6523fcf5ef2aSThomas Huth tcg_temp_free(t1); 6524fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6525fcf5ef2aSThomas Huth /* Update Rc0 */ 6526fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6527fcf5ef2aSThomas Huth } 6528fcf5ef2aSThomas Huth } 6529fcf5ef2aSThomas Huth 6530fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6531fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6532fcf5ef2aSThomas Huth { \ 6533fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6534fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6535fcf5ef2aSThomas Huth } 6536fcf5ef2aSThomas Huth 6537fcf5ef2aSThomas Huth /* macchw - macchw. */ 6538fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6539fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6540fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6541fcf5ef2aSThomas Huth /* macchws - macchws. */ 6542fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6543fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6544fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6545fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6546fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6547fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6549fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6551fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6553fcf5ef2aSThomas Huth /* machhw - machhw. */ 6554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6555fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6557fcf5ef2aSThomas Huth /* machhws - machhws. */ 6558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6559fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6561fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6563fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6565fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6567fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6569fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6571fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6573fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6575fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6577fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6579fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6581fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6583fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6584fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6585fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6586fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6587fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6588fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6589fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6590fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6591fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6592fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6593fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6594fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6595fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6596fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6597fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6598fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6599fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6600fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6601fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6602fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6603fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6604fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6605fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6606fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6607fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6608fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6609fcf5ef2aSThomas Huth 6610fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6611fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6612fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6613fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6614fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6615fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6616fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6617fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6618fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6619fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6620fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6621fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6622fcf5ef2aSThomas Huth 6623fcf5ef2aSThomas Huth /* mfdcr */ 6624fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6625fcf5ef2aSThomas Huth { 6626fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6627fcf5ef2aSThomas Huth GEN_PRIV; 6628fcf5ef2aSThomas Huth #else 6629fcf5ef2aSThomas Huth TCGv dcrn; 6630fcf5ef2aSThomas Huth 6631fcf5ef2aSThomas Huth CHK_SV; 6632fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6633fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6634fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6635fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6636fcf5ef2aSThomas Huth } 6637fcf5ef2aSThomas Huth 6638fcf5ef2aSThomas Huth /* mtdcr */ 6639fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6640fcf5ef2aSThomas Huth { 6641fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6642fcf5ef2aSThomas Huth GEN_PRIV; 6643fcf5ef2aSThomas Huth #else 6644fcf5ef2aSThomas Huth TCGv dcrn; 6645fcf5ef2aSThomas Huth 6646fcf5ef2aSThomas Huth CHK_SV; 6647fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6648fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6649fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6650fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6651fcf5ef2aSThomas Huth } 6652fcf5ef2aSThomas Huth 6653fcf5ef2aSThomas Huth /* mfdcrx */ 6654fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6655fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6656fcf5ef2aSThomas Huth { 6657fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6658fcf5ef2aSThomas Huth GEN_PRIV; 6659fcf5ef2aSThomas Huth #else 6660fcf5ef2aSThomas Huth CHK_SV; 6661fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6662fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6663fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6664fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6665fcf5ef2aSThomas Huth } 6666fcf5ef2aSThomas Huth 6667fcf5ef2aSThomas Huth /* mtdcrx */ 6668fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6669fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6670fcf5ef2aSThomas Huth { 6671fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6672fcf5ef2aSThomas Huth GEN_PRIV; 6673fcf5ef2aSThomas Huth #else 6674fcf5ef2aSThomas Huth CHK_SV; 6675fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6676fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6677fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6678fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6679fcf5ef2aSThomas Huth } 6680fcf5ef2aSThomas Huth 6681fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6682fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6683fcf5ef2aSThomas Huth { 6684fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6685fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6686fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6687fcf5ef2aSThomas Huth } 6688fcf5ef2aSThomas Huth 6689fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6690fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6691fcf5ef2aSThomas Huth { 6692fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6693fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6694fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6695fcf5ef2aSThomas Huth } 6696fcf5ef2aSThomas Huth 6697fcf5ef2aSThomas Huth /* dccci */ 6698fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6699fcf5ef2aSThomas Huth { 6700fcf5ef2aSThomas Huth CHK_SV; 6701fcf5ef2aSThomas Huth /* interpreted as no-op */ 6702fcf5ef2aSThomas Huth } 6703fcf5ef2aSThomas Huth 6704fcf5ef2aSThomas Huth /* dcread */ 6705fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6706fcf5ef2aSThomas Huth { 6707fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6708fcf5ef2aSThomas Huth GEN_PRIV; 6709fcf5ef2aSThomas Huth #else 6710fcf5ef2aSThomas Huth TCGv EA, val; 6711fcf5ef2aSThomas Huth 6712fcf5ef2aSThomas Huth CHK_SV; 6713fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6714fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6715fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6716fcf5ef2aSThomas Huth val = tcg_temp_new(); 6717fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6718fcf5ef2aSThomas Huth tcg_temp_free(val); 6719fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6720fcf5ef2aSThomas Huth tcg_temp_free(EA); 6721fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6722fcf5ef2aSThomas Huth } 6723fcf5ef2aSThomas Huth 6724fcf5ef2aSThomas Huth /* icbt */ 6725fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6726fcf5ef2aSThomas Huth { 6727efe843d8SDavid Gibson /* 6728efe843d8SDavid Gibson * interpreted as no-op 6729efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6730efe843d8SDavid Gibson * does not generate any exception 6731fcf5ef2aSThomas Huth */ 6732fcf5ef2aSThomas Huth } 6733fcf5ef2aSThomas Huth 6734fcf5ef2aSThomas Huth /* iccci */ 6735fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6736fcf5ef2aSThomas Huth { 6737fcf5ef2aSThomas Huth CHK_SV; 6738fcf5ef2aSThomas Huth /* interpreted as no-op */ 6739fcf5ef2aSThomas Huth } 6740fcf5ef2aSThomas Huth 6741fcf5ef2aSThomas Huth /* icread */ 6742fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6743fcf5ef2aSThomas Huth { 6744fcf5ef2aSThomas Huth CHK_SV; 6745fcf5ef2aSThomas Huth /* interpreted as no-op */ 6746fcf5ef2aSThomas Huth } 6747fcf5ef2aSThomas Huth 6748fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6749fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6750fcf5ef2aSThomas Huth { 6751fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6752fcf5ef2aSThomas Huth GEN_PRIV; 6753fcf5ef2aSThomas Huth #else 6754fcf5ef2aSThomas Huth CHK_SV; 6755fcf5ef2aSThomas Huth /* Restore CPU state */ 6756fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 675759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6758fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6759fcf5ef2aSThomas Huth } 6760fcf5ef2aSThomas Huth 6761fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6762fcf5ef2aSThomas Huth { 6763fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6764fcf5ef2aSThomas Huth GEN_PRIV; 6765fcf5ef2aSThomas Huth #else 6766fcf5ef2aSThomas Huth CHK_SV; 6767fcf5ef2aSThomas Huth /* Restore CPU state */ 6768fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 676959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6770fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6771fcf5ef2aSThomas Huth } 6772fcf5ef2aSThomas Huth 6773fcf5ef2aSThomas Huth /* BookE specific */ 6774fcf5ef2aSThomas Huth 6775fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6776fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6777fcf5ef2aSThomas Huth { 6778fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6779fcf5ef2aSThomas Huth GEN_PRIV; 6780fcf5ef2aSThomas Huth #else 6781fcf5ef2aSThomas Huth CHK_SV; 6782fcf5ef2aSThomas Huth /* Restore CPU state */ 6783fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 678459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6785fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6786fcf5ef2aSThomas Huth } 6787fcf5ef2aSThomas Huth 6788fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6789fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6790fcf5ef2aSThomas Huth { 6791fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6792fcf5ef2aSThomas Huth GEN_PRIV; 6793fcf5ef2aSThomas Huth #else 6794fcf5ef2aSThomas Huth CHK_SV; 6795fcf5ef2aSThomas Huth /* Restore CPU state */ 6796fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 679759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6798fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6799fcf5ef2aSThomas Huth } 6800fcf5ef2aSThomas Huth 6801fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6802fcf5ef2aSThomas Huth 6803fcf5ef2aSThomas Huth /* tlbre */ 6804fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6805fcf5ef2aSThomas Huth { 6806fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6807fcf5ef2aSThomas Huth GEN_PRIV; 6808fcf5ef2aSThomas Huth #else 6809fcf5ef2aSThomas Huth CHK_SV; 6810fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6811fcf5ef2aSThomas Huth case 0: 6812fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6813fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6814fcf5ef2aSThomas Huth break; 6815fcf5ef2aSThomas Huth case 1: 6816fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6817fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6818fcf5ef2aSThomas Huth break; 6819fcf5ef2aSThomas Huth default: 6820fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6821fcf5ef2aSThomas Huth break; 6822fcf5ef2aSThomas Huth } 6823fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6824fcf5ef2aSThomas Huth } 6825fcf5ef2aSThomas Huth 6826fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6827fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6828fcf5ef2aSThomas Huth { 6829fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6830fcf5ef2aSThomas Huth GEN_PRIV; 6831fcf5ef2aSThomas Huth #else 6832fcf5ef2aSThomas Huth TCGv t0; 6833fcf5ef2aSThomas Huth 6834fcf5ef2aSThomas Huth CHK_SV; 6835fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6836fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6837fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6838fcf5ef2aSThomas Huth tcg_temp_free(t0); 6839fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6840fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6841fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6842fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6843fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6844fcf5ef2aSThomas Huth gen_set_label(l1); 6845fcf5ef2aSThomas Huth } 6846fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6847fcf5ef2aSThomas Huth } 6848fcf5ef2aSThomas Huth 6849fcf5ef2aSThomas Huth /* tlbwe */ 6850fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6851fcf5ef2aSThomas Huth { 6852fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6853fcf5ef2aSThomas Huth GEN_PRIV; 6854fcf5ef2aSThomas Huth #else 6855fcf5ef2aSThomas Huth CHK_SV; 6856fcf5ef2aSThomas Huth 6857fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6858fcf5ef2aSThomas Huth case 0: 6859fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6860fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6861fcf5ef2aSThomas Huth break; 6862fcf5ef2aSThomas Huth case 1: 6863fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6864fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6865fcf5ef2aSThomas Huth break; 6866fcf5ef2aSThomas Huth default: 6867fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6868fcf5ef2aSThomas Huth break; 6869fcf5ef2aSThomas Huth } 6870fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6871fcf5ef2aSThomas Huth } 6872fcf5ef2aSThomas Huth 6873fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6874fcf5ef2aSThomas Huth 6875fcf5ef2aSThomas Huth /* tlbre */ 6876fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6877fcf5ef2aSThomas Huth { 6878fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6879fcf5ef2aSThomas Huth GEN_PRIV; 6880fcf5ef2aSThomas Huth #else 6881fcf5ef2aSThomas Huth CHK_SV; 6882fcf5ef2aSThomas Huth 6883fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6884fcf5ef2aSThomas Huth case 0: 6885fcf5ef2aSThomas Huth case 1: 6886fcf5ef2aSThomas Huth case 2: 6887fcf5ef2aSThomas Huth { 6888fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6889fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6890fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6891fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6892fcf5ef2aSThomas Huth } 6893fcf5ef2aSThomas Huth break; 6894fcf5ef2aSThomas Huth default: 6895fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6896fcf5ef2aSThomas Huth break; 6897fcf5ef2aSThomas Huth } 6898fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6899fcf5ef2aSThomas Huth } 6900fcf5ef2aSThomas Huth 6901fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6902fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6903fcf5ef2aSThomas Huth { 6904fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6905fcf5ef2aSThomas Huth GEN_PRIV; 6906fcf5ef2aSThomas Huth #else 6907fcf5ef2aSThomas Huth TCGv t0; 6908fcf5ef2aSThomas Huth 6909fcf5ef2aSThomas Huth CHK_SV; 6910fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6911fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6912fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6913fcf5ef2aSThomas Huth tcg_temp_free(t0); 6914fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6915fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6916fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6917fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6918fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6919fcf5ef2aSThomas Huth gen_set_label(l1); 6920fcf5ef2aSThomas Huth } 6921fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6922fcf5ef2aSThomas Huth } 6923fcf5ef2aSThomas Huth 6924fcf5ef2aSThomas Huth /* tlbwe */ 6925fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6926fcf5ef2aSThomas Huth { 6927fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6928fcf5ef2aSThomas Huth GEN_PRIV; 6929fcf5ef2aSThomas Huth #else 6930fcf5ef2aSThomas Huth CHK_SV; 6931fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6932fcf5ef2aSThomas Huth case 0: 6933fcf5ef2aSThomas Huth case 1: 6934fcf5ef2aSThomas Huth case 2: 6935fcf5ef2aSThomas Huth { 6936fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6937fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6938fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6939fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6940fcf5ef2aSThomas Huth } 6941fcf5ef2aSThomas Huth break; 6942fcf5ef2aSThomas Huth default: 6943fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6944fcf5ef2aSThomas Huth break; 6945fcf5ef2aSThomas Huth } 6946fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6947fcf5ef2aSThomas Huth } 6948fcf5ef2aSThomas Huth 6949fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6950fcf5ef2aSThomas Huth 6951fcf5ef2aSThomas Huth /* tlbre */ 6952fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6953fcf5ef2aSThomas Huth { 6954fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6955fcf5ef2aSThomas Huth GEN_PRIV; 6956fcf5ef2aSThomas Huth #else 6957fcf5ef2aSThomas Huth CHK_SV; 6958fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6959fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6960fcf5ef2aSThomas Huth } 6961fcf5ef2aSThomas Huth 6962fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6963fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6964fcf5ef2aSThomas Huth { 6965fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6966fcf5ef2aSThomas Huth GEN_PRIV; 6967fcf5ef2aSThomas Huth #else 6968fcf5ef2aSThomas Huth TCGv t0; 6969fcf5ef2aSThomas Huth 6970fcf5ef2aSThomas Huth CHK_SV; 6971fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6972fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6973fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6974fcf5ef2aSThomas Huth } else { 6975fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6976fcf5ef2aSThomas Huth } 6977fcf5ef2aSThomas Huth 6978fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6979fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6980fcf5ef2aSThomas Huth tcg_temp_free(t0); 6981fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6982fcf5ef2aSThomas Huth } 6983fcf5ef2aSThomas Huth 6984fcf5ef2aSThomas Huth /* tlbwe */ 6985fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6986fcf5ef2aSThomas Huth { 6987fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6988fcf5ef2aSThomas Huth GEN_PRIV; 6989fcf5ef2aSThomas Huth #else 6990fcf5ef2aSThomas Huth CHK_SV; 6991fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6992fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6993fcf5ef2aSThomas Huth } 6994fcf5ef2aSThomas Huth 6995fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6996fcf5ef2aSThomas Huth { 6997fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6998fcf5ef2aSThomas Huth GEN_PRIV; 6999fcf5ef2aSThomas Huth #else 7000fcf5ef2aSThomas Huth TCGv t0; 7001fcf5ef2aSThomas Huth 7002fcf5ef2aSThomas Huth CHK_SV; 7003fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7004fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7005fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7006fcf5ef2aSThomas Huth tcg_temp_free(t0); 7007fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7008fcf5ef2aSThomas Huth } 7009fcf5ef2aSThomas Huth 7010fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7011fcf5ef2aSThomas Huth { 7012fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7013fcf5ef2aSThomas Huth GEN_PRIV; 7014fcf5ef2aSThomas Huth #else 7015fcf5ef2aSThomas Huth TCGv t0; 7016fcf5ef2aSThomas Huth 7017fcf5ef2aSThomas Huth CHK_SV; 7018fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7019fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7020fcf5ef2aSThomas Huth 7021fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7022fcf5ef2aSThomas Huth case 0: 7023fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7024fcf5ef2aSThomas Huth break; 7025fcf5ef2aSThomas Huth case 1: 7026fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7027fcf5ef2aSThomas Huth break; 7028fcf5ef2aSThomas Huth case 3: 7029fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7030fcf5ef2aSThomas Huth break; 7031fcf5ef2aSThomas Huth default: 7032fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7033fcf5ef2aSThomas Huth break; 7034fcf5ef2aSThomas Huth } 7035fcf5ef2aSThomas Huth 7036fcf5ef2aSThomas Huth tcg_temp_free(t0); 7037fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7038fcf5ef2aSThomas Huth } 7039fcf5ef2aSThomas Huth 7040fcf5ef2aSThomas Huth 7041fcf5ef2aSThomas Huth /* wrtee */ 7042fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7043fcf5ef2aSThomas Huth { 7044fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7045fcf5ef2aSThomas Huth GEN_PRIV; 7046fcf5ef2aSThomas Huth #else 7047fcf5ef2aSThomas Huth TCGv t0; 7048fcf5ef2aSThomas Huth 7049fcf5ef2aSThomas Huth CHK_SV; 7050fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7051fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7052fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7053fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7054fcf5ef2aSThomas Huth tcg_temp_free(t0); 7055efe843d8SDavid Gibson /* 7056efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7057efe843d8SDavid Gibson * just set msr_ee to 1 7058fcf5ef2aSThomas Huth */ 7059d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7060fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7061fcf5ef2aSThomas Huth } 7062fcf5ef2aSThomas Huth 7063fcf5ef2aSThomas Huth /* wrteei */ 7064fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7065fcf5ef2aSThomas Huth { 7066fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7067fcf5ef2aSThomas Huth GEN_PRIV; 7068fcf5ef2aSThomas Huth #else 7069fcf5ef2aSThomas Huth CHK_SV; 7070fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7071fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7072fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7073d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7074fcf5ef2aSThomas Huth } else { 7075fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7076fcf5ef2aSThomas Huth } 7077fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7078fcf5ef2aSThomas Huth } 7079fcf5ef2aSThomas Huth 7080fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7081fcf5ef2aSThomas Huth 7082fcf5ef2aSThomas Huth /* dlmzb */ 7083fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7084fcf5ef2aSThomas Huth { 7085fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7086fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7087fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7088fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7089fcf5ef2aSThomas Huth } 7090fcf5ef2aSThomas Huth 7091fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7092fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7093fcf5ef2aSThomas Huth { 7094fcf5ef2aSThomas Huth /* interpreted as no-op */ 7095fcf5ef2aSThomas Huth } 7096fcf5ef2aSThomas Huth 7097fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7098fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7099fcf5ef2aSThomas Huth { 710027a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 710127a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 710227a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 710327a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 710427a3ea7eSBALATON Zoltan } 710527a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7106fcf5ef2aSThomas Huth } 7107fcf5ef2aSThomas Huth 7108fcf5ef2aSThomas Huth /* icbt */ 7109fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7110fcf5ef2aSThomas Huth { 7111efe843d8SDavid Gibson /* 7112efe843d8SDavid Gibson * interpreted as no-op 7113efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7114efe843d8SDavid Gibson * does not generate any exception 7115fcf5ef2aSThomas Huth */ 7116fcf5ef2aSThomas Huth } 7117fcf5ef2aSThomas Huth 7118fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7119fcf5ef2aSThomas Huth 7120fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7121fcf5ef2aSThomas Huth { 7122fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7123fcf5ef2aSThomas Huth GEN_PRIV; 7124fcf5ef2aSThomas Huth #else 7125ebca5e6dSCédric Le Goater CHK_HV; 7126d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 71277af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71287af1e7b0SCédric Le Goater } else { 7129fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71307af1e7b0SCédric Le Goater } 7131fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7132fcf5ef2aSThomas Huth } 7133fcf5ef2aSThomas Huth 7134fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7135fcf5ef2aSThomas Huth { 7136fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7137fcf5ef2aSThomas Huth GEN_PRIV; 7138fcf5ef2aSThomas Huth #else 7139ebca5e6dSCédric Le Goater CHK_HV; 7140d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 71417af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 71427af1e7b0SCédric Le Goater } else { 7143fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 71447af1e7b0SCédric Le Goater } 7145fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7146fcf5ef2aSThomas Huth } 7147fcf5ef2aSThomas Huth 71485ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 71495ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 71505ba7ba1dSCédric Le Goater { 71515ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 71525ba7ba1dSCédric Le Goater GEN_PRIV; 71535ba7ba1dSCédric Le Goater #else 71545ba7ba1dSCédric Le Goater CHK_SV; 71555ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71565ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 71575ba7ba1dSCédric Le Goater } 71585ba7ba1dSCédric Le Goater 71595ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 71605ba7ba1dSCédric Le Goater { 71615ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 71625ba7ba1dSCédric Le Goater GEN_PRIV; 71635ba7ba1dSCédric Le Goater #else 71645ba7ba1dSCédric Le Goater CHK_SV; 71655ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71665ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 71675ba7ba1dSCédric Le Goater } 71685ba7ba1dSCédric Le Goater #endif 71695ba7ba1dSCédric Le Goater 71707af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 71717af1e7b0SCédric Le Goater { 71727af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 71737af1e7b0SCédric Le Goater GEN_PRIV; 71747af1e7b0SCédric Le Goater #else 71757af1e7b0SCédric Le Goater CHK_HV; 71767af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 71777af1e7b0SCédric Le Goater /* interpreted as no-op */ 71787af1e7b0SCédric Le Goater } 7179fcf5ef2aSThomas Huth 7180fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7181fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7182fcf5ef2aSThomas Huth { 7183fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7184fcf5ef2aSThomas Huth 7185fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7186fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7187fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7188fcf5ef2aSThomas Huth } 7189fcf5ef2aSThomas Huth 7190fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7191fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7192fcf5ef2aSThomas Huth { 7193fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7194fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7195fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7196fcf5ef2aSThomas Huth 7197fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7198fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7199fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7200fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7201fcf5ef2aSThomas Huth } else { 7202fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7203fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7204fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7205fcf5ef2aSThomas Huth } 7206fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7207fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7208fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7209fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7210fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7211fcf5ef2aSThomas Huth } 7212fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7213fcf5ef2aSThomas Huth 7214fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7215fcf5ef2aSThomas Huth { 7216fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7217fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7218fcf5ef2aSThomas Huth return; 7219fcf5ef2aSThomas Huth } 7220fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7221fcf5ef2aSThomas Huth } 7222fcf5ef2aSThomas Huth 7223fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7224fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7225fcf5ef2aSThomas Huth { \ 7226fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7227fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7228fcf5ef2aSThomas Huth return; \ 7229fcf5ef2aSThomas Huth } \ 7230efe843d8SDavid Gibson /* \ 7231efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7232fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7233fcf5ef2aSThomas Huth * \ 7234fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7235fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7236fcf5ef2aSThomas Huth */ \ 7237fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7238fcf5ef2aSThomas Huth } 7239fcf5ef2aSThomas Huth 7240fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7241fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7242fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7243fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7244fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7245fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7246fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7247efe843d8SDavid Gibson 7248b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7249b8b4576eSSuraj Jitindar Singh { 7250efe843d8SDavid Gibson /* Do Nothing */ 7251b8b4576eSSuraj Jitindar Singh } 7252fcf5ef2aSThomas Huth 725380b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 725480b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 725580b8c1eeSNikunj A Dadhania { \ 7256efe843d8SDavid Gibson /* \ 7257efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7258efe843d8SDavid Gibson * implementation of the copy paste facility \ 725980b8c1eeSNikunj A Dadhania */ \ 726080b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 726180b8c1eeSNikunj A Dadhania } 726280b8c1eeSNikunj A Dadhania 726380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 726480b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 726580b8c1eeSNikunj A Dadhania 7266fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7267fcf5ef2aSThomas Huth { 7268fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7269fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7270fcf5ef2aSThomas Huth return; 7271fcf5ef2aSThomas Huth } 7272efe843d8SDavid Gibson /* 7273efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7274efe843d8SDavid Gibson * simple: 7275fcf5ef2aSThomas Huth * 7276fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7277fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7278fcf5ef2aSThomas Huth */ 7279fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7280fcf5ef2aSThomas Huth } 7281fcf5ef2aSThomas Huth 7282fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7283fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7284fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7285fcf5ef2aSThomas Huth { \ 7286fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7287fcf5ef2aSThomas Huth } 7288fcf5ef2aSThomas Huth 7289fcf5ef2aSThomas Huth #else 7290fcf5ef2aSThomas Huth 7291fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7292fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7293fcf5ef2aSThomas Huth { \ 7294fcf5ef2aSThomas Huth CHK_SV; \ 7295fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7296fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7297fcf5ef2aSThomas Huth return; \ 7298fcf5ef2aSThomas Huth } \ 7299efe843d8SDavid Gibson /* \ 7300efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7301fcf5ef2aSThomas Huth * simple: \ 7302fcf5ef2aSThomas Huth * \ 7303fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7304fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7305fcf5ef2aSThomas Huth */ \ 7306fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7307fcf5ef2aSThomas Huth } 7308fcf5ef2aSThomas Huth 7309fcf5ef2aSThomas Huth #endif 7310fcf5ef2aSThomas Huth 7311fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7312fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7313fcf5ef2aSThomas Huth 73141a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 73151a404c91SMark Cave-Ayland { 7316e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 73171a404c91SMark Cave-Ayland } 73181a404c91SMark Cave-Ayland 73191a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 73201a404c91SMark Cave-Ayland { 7321e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 73221a404c91SMark Cave-Ayland } 73231a404c91SMark Cave-Ayland 7324c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7325c4a18dbfSMark Cave-Ayland { 732637da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7327c4a18dbfSMark Cave-Ayland } 7328c4a18dbfSMark Cave-Ayland 7329c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7330c4a18dbfSMark Cave-Ayland { 733137da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7332c4a18dbfSMark Cave-Ayland } 7333c4a18dbfSMark Cave-Ayland 7334c9826ae9SRichard Henderson /* 7335f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 7336f2aabda8SRichard Henderson */ 7337d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 7338d39b2cc7SLuis Pires { 7339d39b2cc7SLuis Pires return x * 2; 7340d39b2cc7SLuis Pires } 7341d39b2cc7SLuis Pires 7342f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 7343f2aabda8SRichard Henderson { 7344f2aabda8SRichard Henderson return x * 4; 7345f2aabda8SRichard Henderson } 7346f2aabda8SRichard Henderson 7347e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 7348e10271e1SMatheus Ferst { 7349e10271e1SMatheus Ferst return x * 16; 7350e10271e1SMatheus Ferst } 7351e10271e1SMatheus Ferst 7352f2aabda8SRichard Henderson /* 7353c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 7354c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 7355c9826ae9SRichard Henderson * proper variable. 7356c9826ae9SRichard Henderson */ 7357c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7358c9826ae9SRichard Henderson do { \ 7359c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7360c9826ae9SRichard Henderson return false; \ 7361c9826ae9SRichard Henderson } \ 7362c9826ae9SRichard Henderson } while (0) 7363c9826ae9SRichard Henderson 7364c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7365c9826ae9SRichard Henderson do { \ 7366c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7367c9826ae9SRichard Henderson return false; \ 7368c9826ae9SRichard Henderson } \ 7369c9826ae9SRichard Henderson } while (0) 7370c9826ae9SRichard Henderson 7371c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7372c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 7373c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 7374c9826ae9SRichard Henderson #else 7375c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7376c9826ae9SRichard Henderson #endif 7377c9826ae9SRichard Henderson 7378e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 7379e2205a46SBruno Larsen do { \ 7380e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 7381e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 7382e2205a46SBruno Larsen return true; \ 7383e2205a46SBruno Larsen } \ 7384e2205a46SBruno Larsen } while (0) 7385e2205a46SBruno Larsen 73868226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 73878226cb2dSBruno Larsen (billionai) do { \ 73888226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 73898226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 73908226cb2dSBruno Larsen (billionai) return true; \ 73918226cb2dSBruno Larsen (billionai) } \ 73928226cb2dSBruno Larsen (billionai) } while (0) 73938226cb2dSBruno Larsen (billionai) 739486057426SFernando Valle #define REQUIRE_FPU(ctx) \ 739586057426SFernando Valle do { \ 739686057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 739786057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 739886057426SFernando Valle return true; \ 739986057426SFernando Valle } \ 740086057426SFernando Valle } while (0) 740186057426SFernando Valle 7402f2aabda8SRichard Henderson /* 7403f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 7404f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 7405f2aabda8SRichard Henderson */ 7406f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 7407f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7408f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 7409f2aabda8SRichard Henderson 7410f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 7411f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7412f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 7413f2aabda8SRichard Henderson 7414f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 7415f2aabda8SRichard Henderson 7416f2aabda8SRichard Henderson 741799082815SRichard Henderson #include "decode-insn32.c.inc" 741899082815SRichard Henderson #include "decode-insn64.c.inc" 7419565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 7420565cb109SGustavo Romero 7421725b2d4dSFernando Eckhardt Valle /* 7422725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 7423725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 7424725b2d4dSFernando Eckhardt Valle */ 7425725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 7426725b2d4dSFernando Eckhardt Valle { 7427725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 7428725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 7429725b2d4dSFernando Eckhardt Valle d->si = a->si; 7430725b2d4dSFernando Eckhardt Valle if (a->r) { 7431725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 7432725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 7433725b2d4dSFernando Eckhardt Valle return false; 7434725b2d4dSFernando Eckhardt Valle } 7435725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 7436725b2d4dSFernando Eckhardt Valle } 7437725b2d4dSFernando Eckhardt Valle return true; 7438725b2d4dSFernando Eckhardt Valle } 7439725b2d4dSFernando Eckhardt Valle 744099082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 744199082815SRichard Henderson 7442139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7443fcf5ef2aSThomas Huth 7444139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7445fcf5ef2aSThomas Huth 7446139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7447fcf5ef2aSThomas Huth 7448139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7449fcf5ef2aSThomas Huth 7450139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7451fcf5ef2aSThomas Huth 74525cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 74535cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 74545cb091a4SNikunj A Dadhania { 74555cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 74565cb091a4SNikunj A Dadhania case 0: /* lfdp */ 74575cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 74585cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 74595cb091a4SNikunj A Dadhania } 74605cb091a4SNikunj A Dadhania break; 74615cb091a4SNikunj A Dadhania case 2: /* lxsd */ 74625cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 74635cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 74645cb091a4SNikunj A Dadhania } 74655cb091a4SNikunj A Dadhania break; 74665cb091a4SNikunj A Dadhania case 3: /* lxssp */ 74675cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 74685cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 74695cb091a4SNikunj A Dadhania } 74705cb091a4SNikunj A Dadhania break; 74715cb091a4SNikunj A Dadhania } 74725cb091a4SNikunj A Dadhania return gen_invalid(ctx); 74735cb091a4SNikunj A Dadhania } 74745cb091a4SNikunj A Dadhania 7475d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7476e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7477e3001664SNikunj A Dadhania { 747872b70d5cSLucas Mateus Castro (alqotel) if ((ctx->opcode & 3) != 1) { /* DS-FORM */ 7479e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7480e3001664SNikunj A Dadhania case 0: /* stfdp */ 7481e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7482e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7483e3001664SNikunj A Dadhania } 7484e3001664SNikunj A Dadhania break; 7485e3001664SNikunj A Dadhania case 2: /* stxsd */ 7486e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7487e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7488e3001664SNikunj A Dadhania } 7489e3001664SNikunj A Dadhania break; 7490e3001664SNikunj A Dadhania case 3: /* stxssp */ 7491e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7492e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7493e3001664SNikunj A Dadhania } 7494e3001664SNikunj A Dadhania break; 7495e3001664SNikunj A Dadhania } 7496e3001664SNikunj A Dadhania } 7497e3001664SNikunj A Dadhania return gen_invalid(ctx); 7498e3001664SNikunj A Dadhania } 7499e3001664SNikunj A Dadhania 75009d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75019d69cfa2SLijun Pan /* brd */ 75029d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 75039d69cfa2SLijun Pan { 75049d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75059d69cfa2SLijun Pan } 75069d69cfa2SLijun Pan 75079d69cfa2SLijun Pan /* brw */ 75089d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 75099d69cfa2SLijun Pan { 75109d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75119d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 75129d69cfa2SLijun Pan 75139d69cfa2SLijun Pan } 75149d69cfa2SLijun Pan 75159d69cfa2SLijun Pan /* brh */ 75169d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 75179d69cfa2SLijun Pan { 7518491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 75199d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 75209d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 75219d69cfa2SLijun Pan 75229d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 7523491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 7524491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 75259d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 75269d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 75279d69cfa2SLijun Pan 75289d69cfa2SLijun Pan tcg_temp_free_i64(t1); 75299d69cfa2SLijun Pan tcg_temp_free_i64(t2); 75309d69cfa2SLijun Pan } 75319d69cfa2SLijun Pan #endif 75329d69cfa2SLijun Pan 7533fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 75349d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75359d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 75369d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 75379d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 75389d69cfa2SLijun Pan #endif 7539fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7540fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7541fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7542fcf5ef2aSThomas Huth #endif 7543fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7544fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7545fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7546fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7547fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7548fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7549fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7550fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7551fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7552fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7553fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7554fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7555fcf5ef2aSThomas Huth #endif 7556fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7557fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7558fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7559fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7560fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7561fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7562fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 756380b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7564b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 756580b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7566fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7567fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7568fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7569fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7570fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7571fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7572fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7573fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7574fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7575fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7576fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7577fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7578fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7579fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7580fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7581fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7582fcf5ef2aSThomas Huth #endif 7583fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7584fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7585fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7586fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7587fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7588fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7589fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7590fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7591fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7592fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7593fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7594fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7595fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7596fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7597fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7598fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7599fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7600fcf5ef2aSThomas Huth #endif 76015cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 76025cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 760372b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 7604e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7605fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7606fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7607fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7608fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7609fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7610fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7611c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7612fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7613fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7614fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7615fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7616a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7617a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7618fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7619fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7620fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7621fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7622a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7623a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7624fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7625fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7626fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7627fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7628fcf5ef2aSThomas Huth #endif 7629fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7630fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7631c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7632fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7633fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7634fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7635fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7636fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7637fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7638fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7639fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7640fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 76413c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 76423c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 76433c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 76443c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 76453c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 76463c89b8d6SNicholas Piggin #endif 7647cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7648fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7649fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7650fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7651fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7652fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7653fcf5ef2aSThomas Huth #endif 76543c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 76553c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 76563c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7657fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7658fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7659fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7660fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7661fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7662fcf5ef2aSThomas Huth #endif 7663fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7664fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7665fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7666fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7667fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7668fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7669fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7670fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7671fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7672b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7673fcf5ef2aSThomas Huth #endif 7674fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7675fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7676fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 767750728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7678fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7679fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 768050728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7681fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 768250728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7683fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 768450728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7685fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7686fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 768750728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7688fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 768999d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7690fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7691fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 769250728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7693fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7694fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7695fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7696fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7697fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7698fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7699fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7700fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7701fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7702fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7703fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7704fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7705fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7706fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7707fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7708fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7709fcf5ef2aSThomas Huth #endif 7710fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7711efe843d8SDavid Gibson /* 7712efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7713efe843d8SDavid Gibson * different ISA versions 7714efe843d8SDavid Gibson */ 7715fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7716fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7717c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7718c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7719fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7720fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7721fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7722fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7723a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 772462d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7725fcf5ef2aSThomas Huth #endif 7726fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7727fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7728fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7729fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7730fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7731fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7732fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7733fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7734fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7735fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7736fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7737fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7738fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7739fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7740fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7741fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7742fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7743fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7744fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7745fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7746fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7747fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7748fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7749fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7750fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7751fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7752fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7753fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7754fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7755fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7756fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7757fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7758fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7759fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7760fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7761fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7762fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7763fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7764fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7765fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7766fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7767fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7768fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7769fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7770fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7771fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7772fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7773fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7774fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7775fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7776fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7777fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7778fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7779fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7780fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7781fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7782fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7783fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7784fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7785fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7786fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7787fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7788fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7789fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7790fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7791fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7792fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7793fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7794fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7795fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7796fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7797fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7798fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7799fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7800fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7801fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7802fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7803fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7804fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7805fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7806fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7807fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7808fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7809fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7810fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7811fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7812fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7813fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7814fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7815fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7816fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7817fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 78187af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 78197af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7820fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7821fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7822fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7823fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7824fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 782527a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7826fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7827fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 78280c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 78290c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7830fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7831fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7832fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7833fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7834fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7835fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7836fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7837fcf5ef2aSThomas Huth PPC2_ISA300), 7838fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 78395ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 78405ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 78415ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 78425ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 7843fcf5ef2aSThomas Huth #endif 7844fcf5ef2aSThomas Huth 7845fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7846fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7847fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7848fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7849fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7850fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7851fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7852fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7853fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7854fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7855fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7856fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7857fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7858fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7859fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 78604c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7861fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7862fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7863fcf5ef2aSThomas Huth 7864fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7865fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7866fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7867fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7868fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7869fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7870fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7871fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7872fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7873fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7874fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7875fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7876fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7877fcf5ef2aSThomas Huth 7878fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7879fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7880fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7881fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7882fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7883fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7884fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7885fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7886fcf5ef2aSThomas Huth 7887fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7888fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7889fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7890fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7891fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7892fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7893fcf5ef2aSThomas Huth 7894fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7895fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7896fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7897fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7898fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7899fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7900fcf5ef2aSThomas Huth #endif 7901fcf5ef2aSThomas Huth 7902fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7903fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7904fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7905fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7906fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7907fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7908fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7909fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7910fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7911fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7912fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7913fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7914fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7915fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7916fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7917fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7918fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7919fcf5ef2aSThomas Huth 7920fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7921fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7922fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7923fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7924fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7925fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7926fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7927fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7928fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7929fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7930fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7931fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7932fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7933fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7934fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7935fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7936fcf5ef2aSThomas Huth #endif 7937fcf5ef2aSThomas Huth 7938fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7939fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7940fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7941fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7942fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7943fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7944fcf5ef2aSThomas Huth PPC_64B) 7945fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7946fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7947fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7948fcf5ef2aSThomas Huth PPC_64B), \ 7949fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7950fcf5ef2aSThomas Huth PPC_64B), \ 7951fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7952fcf5ef2aSThomas Huth PPC_64B) 7953fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7954fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7955fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7956fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7957fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7958fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7959fcf5ef2aSThomas Huth #endif 7960fcf5ef2aSThomas Huth 7961fcf5ef2aSThomas Huth #undef GEN_LDX_E 7962fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7963fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7964fcf5ef2aSThomas Huth 7965fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7966fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7967fcf5ef2aSThomas Huth 7968fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7969fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7970fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7971fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7972fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7973fcf5ef2aSThomas Huth #endif 7974fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7975fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7976fcf5ef2aSThomas Huth 797750728199SRoman Kapl /* External PID based load */ 797850728199SRoman Kapl #undef GEN_LDEPX 797950728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 798050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 798150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 798250728199SRoman Kapl 798350728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 798450728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 798550728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 798650728199SRoman Kapl #if defined(TARGET_PPC64) 798750728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 798850728199SRoman Kapl #endif 798950728199SRoman Kapl 7990fcf5ef2aSThomas Huth #undef GEN_STX_E 7991fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 79920123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7993fcf5ef2aSThomas Huth 7994fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7995fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7996fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7997fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7998fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7999fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8000fcf5ef2aSThomas Huth #endif 8001fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8002fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8003fcf5ef2aSThomas Huth 800450728199SRoman Kapl #undef GEN_STEPX 800550728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 800650728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 800750728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 800850728199SRoman Kapl 800950728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 801050728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 801150728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 801250728199SRoman Kapl #if defined(TARGET_PPC64) 801350728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 801450728199SRoman Kapl #endif 801550728199SRoman Kapl 8016fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8017fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8018fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8019fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8020fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8021fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8022fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8023fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8024fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8025fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8026fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8027fcf5ef2aSThomas Huth 8028fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8029fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8030fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8031fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8032fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8033fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8034fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8035fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8036fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8037fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8038fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8039fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8040fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8041fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8042fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8043fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8044fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8045fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8046fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8047fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8048fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8049fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8050fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8051fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8052fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8053fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8054fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8055fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8056fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8057fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8058fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8059fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8060fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8061fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8062fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8063fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8064fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8065fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8066fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8067fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8068fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8069fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8070fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8071fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8072fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8073fcf5ef2aSThomas Huth 8074fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8075fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8076fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8077fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8078fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8079fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8080fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8081fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8082fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8083fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8084fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8085fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8086fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8087fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8088fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8089fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8090fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8091fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8092fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8093fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8094fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8095fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8096fcf5ef2aSThomas Huth 8097139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8098fcf5ef2aSThomas Huth 8099139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8100fcf5ef2aSThomas Huth 8101139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8102fcf5ef2aSThomas Huth 8103139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8104fcf5ef2aSThomas Huth }; 8105fcf5ef2aSThomas Huth 81067468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 81077468e2c8SBruno Larsen (billionai) /* Opcode types */ 81087468e2c8SBruno Larsen (billionai) enum { 81097468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 81107468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 81117468e2c8SBruno Larsen (billionai) }; 81127468e2c8SBruno Larsen (billionai) 81137468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 81147468e2c8SBruno Larsen (billionai) 81157468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 81167468e2c8SBruno Larsen (billionai) { 81177468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 81187468e2c8SBruno Larsen (billionai) } 81197468e2c8SBruno Larsen (billionai) 81207468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 81217468e2c8SBruno Larsen (billionai) { 81227468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 81237468e2c8SBruno Larsen (billionai) } 81247468e2c8SBruno Larsen (billionai) 81257468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 81267468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 81277468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 81287468e2c8SBruno Larsen (billionai) { 81297468e2c8SBruno Larsen (billionai) int i; 81307468e2c8SBruno Larsen (billionai) 81317468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 81327468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 81337468e2c8SBruno Larsen (billionai) } 81347468e2c8SBruno Larsen (billionai) } 81357468e2c8SBruno Larsen (billionai) 81367468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 81377468e2c8SBruno Larsen (billionai) { 81387468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 81397468e2c8SBruno Larsen (billionai) 81407468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 81417468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 81427468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 81437468e2c8SBruno Larsen (billionai) 81447468e2c8SBruno Larsen (billionai) return 0; 81457468e2c8SBruno Larsen (billionai) } 81467468e2c8SBruno Larsen (billionai) 81477468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 81487468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 81497468e2c8SBruno Larsen (billionai) { 81507468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 81517468e2c8SBruno Larsen (billionai) return -1; 81527468e2c8SBruno Larsen (billionai) } 81537468e2c8SBruno Larsen (billionai) table[idx] = handler; 81547468e2c8SBruno Larsen (billionai) 81557468e2c8SBruno Larsen (billionai) return 0; 81567468e2c8SBruno Larsen (billionai) } 81577468e2c8SBruno Larsen (billionai) 81587468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 81597468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 81607468e2c8SBruno Larsen (billionai) { 81617468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 81627468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 81637468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 81647468e2c8SBruno Larsen (billionai) return -1; 81657468e2c8SBruno Larsen (billionai) } 81667468e2c8SBruno Larsen (billionai) 81677468e2c8SBruno Larsen (billionai) return 0; 81687468e2c8SBruno Larsen (billionai) } 81697468e2c8SBruno Larsen (billionai) 81707468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 81717468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 81727468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 81737468e2c8SBruno Larsen (billionai) { 81747468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 81757468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 81767468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 81777468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 81787468e2c8SBruno Larsen (billionai) return -1; 81797468e2c8SBruno Larsen (billionai) } 81807468e2c8SBruno Larsen (billionai) } else { 81817468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 81827468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 81837468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 81847468e2c8SBruno Larsen (billionai) return -1; 81857468e2c8SBruno Larsen (billionai) } 81867468e2c8SBruno Larsen (billionai) } 81877468e2c8SBruno Larsen (billionai) if (handler != NULL && 81887468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 81897468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 81907468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 81917468e2c8SBruno Larsen (billionai) return -1; 81927468e2c8SBruno Larsen (billionai) } 81937468e2c8SBruno Larsen (billionai) 81947468e2c8SBruno Larsen (billionai) return 0; 81957468e2c8SBruno Larsen (billionai) } 81967468e2c8SBruno Larsen (billionai) 81977468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 81987468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 81997468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82007468e2c8SBruno Larsen (billionai) { 82017468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 82027468e2c8SBruno Larsen (billionai) } 82037468e2c8SBruno Larsen (billionai) 82047468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 82057468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82067468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 82077468e2c8SBruno Larsen (billionai) { 82087468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82097468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82107468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82117468e2c8SBruno Larsen (billionai) return -1; 82127468e2c8SBruno Larsen (billionai) } 82137468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 82147468e2c8SBruno Larsen (billionai) handler) < 0) { 82157468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 82167468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 82177468e2c8SBruno Larsen (billionai) return -1; 82187468e2c8SBruno Larsen (billionai) } 82197468e2c8SBruno Larsen (billionai) 82207468e2c8SBruno Larsen (billionai) return 0; 82217468e2c8SBruno Larsen (billionai) } 82227468e2c8SBruno Larsen (billionai) 82237468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 82247468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82257468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 82267468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82277468e2c8SBruno Larsen (billionai) { 82287468e2c8SBruno Larsen (billionai) opc_handler_t **table; 82297468e2c8SBruno Larsen (billionai) 82307468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82317468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82327468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82337468e2c8SBruno Larsen (billionai) return -1; 82347468e2c8SBruno Larsen (billionai) } 82357468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 82367468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 82377468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 82387468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 82397468e2c8SBruno Larsen (billionai) return -1; 82407468e2c8SBruno Larsen (billionai) } 82417468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 82427468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 82437468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 82447468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 82457468e2c8SBruno Larsen (billionai) return -1; 82467468e2c8SBruno Larsen (billionai) } 82477468e2c8SBruno Larsen (billionai) return 0; 82487468e2c8SBruno Larsen (billionai) } 82497468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 82507468e2c8SBruno Larsen (billionai) { 82517468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 82527468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 82537468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 82547468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 82557468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 82567468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 82577468e2c8SBruno Larsen (billionai) return -1; 82587468e2c8SBruno Larsen (billionai) } 82597468e2c8SBruno Larsen (billionai) } else { 82607468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 82617468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 82627468e2c8SBruno Larsen (billionai) return -1; 82637468e2c8SBruno Larsen (billionai) } 82647468e2c8SBruno Larsen (billionai) } 82657468e2c8SBruno Larsen (billionai) } else { 82667468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 82677468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 82687468e2c8SBruno Larsen (billionai) return -1; 82697468e2c8SBruno Larsen (billionai) } 82707468e2c8SBruno Larsen (billionai) } 82717468e2c8SBruno Larsen (billionai) } else { 82727468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 82737468e2c8SBruno Larsen (billionai) return -1; 82747468e2c8SBruno Larsen (billionai) } 82757468e2c8SBruno Larsen (billionai) } 82767468e2c8SBruno Larsen (billionai) 82777468e2c8SBruno Larsen (billionai) return 0; 82787468e2c8SBruno Larsen (billionai) } 82797468e2c8SBruno Larsen (billionai) 82807468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 82817468e2c8SBruno Larsen (billionai) { 82827468e2c8SBruno Larsen (billionai) int i, count, tmp; 82837468e2c8SBruno Larsen (billionai) 82847468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 82857468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 82867468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 82877468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 82887468e2c8SBruno Larsen (billionai) } 82897468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 82907468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 82917468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 82927468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 82937468e2c8SBruno Larsen (billionai) if (tmp == 0) { 82947468e2c8SBruno Larsen (billionai) free(table[i]); 82957468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 82967468e2c8SBruno Larsen (billionai) } else { 82977468e2c8SBruno Larsen (billionai) count++; 82987468e2c8SBruno Larsen (billionai) } 82997468e2c8SBruno Larsen (billionai) } else { 83007468e2c8SBruno Larsen (billionai) count++; 83017468e2c8SBruno Larsen (billionai) } 83027468e2c8SBruno Larsen (billionai) } 83037468e2c8SBruno Larsen (billionai) } 83047468e2c8SBruno Larsen (billionai) 83057468e2c8SBruno Larsen (billionai) return count; 83067468e2c8SBruno Larsen (billionai) } 83077468e2c8SBruno Larsen (billionai) 83087468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 83097468e2c8SBruno Larsen (billionai) { 83107468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 83117468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 83127468e2c8SBruno Larsen (billionai) } 83137468e2c8SBruno Larsen (billionai) } 83147468e2c8SBruno Larsen (billionai) 83157468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 83167468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 83177468e2c8SBruno Larsen (billionai) { 83187468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 83197468e2c8SBruno Larsen (billionai) opcode_t *opc; 83207468e2c8SBruno Larsen (billionai) 83217468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 83227468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 83237468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 83247468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 83257468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 83267468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 83277468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 83287468e2c8SBruno Larsen (billionai) opc->opc3); 83297468e2c8SBruno Larsen (billionai) return; 83307468e2c8SBruno Larsen (billionai) } 83317468e2c8SBruno Larsen (billionai) } 83327468e2c8SBruno Larsen (billionai) } 83337468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 83347468e2c8SBruno Larsen (billionai) fflush(stdout); 83357468e2c8SBruno Larsen (billionai) fflush(stderr); 83367468e2c8SBruno Larsen (billionai) } 83377468e2c8SBruno Larsen (billionai) 83387468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 83397468e2c8SBruno Larsen (billionai) { 83407468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 83417468e2c8SBruno Larsen (billionai) int i, j, k; 83427468e2c8SBruno Larsen (billionai) 83437468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 83447468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 83457468e2c8SBruno Larsen (billionai) continue; 83467468e2c8SBruno Larsen (billionai) } 83477468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 83487468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 83497468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 83507468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 83517468e2c8SBruno Larsen (billionai) continue; 83527468e2c8SBruno Larsen (billionai) } 83537468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 83547468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 83557468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 83567468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 83577468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 83587468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 83597468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 83607468e2c8SBruno Larsen (billionai) } 83617468e2c8SBruno Larsen (billionai) } 83627468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 83637468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 83647468e2c8SBruno Larsen (billionai) } 83657468e2c8SBruno Larsen (billionai) } 83667468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 83677468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 83687468e2c8SBruno Larsen (billionai) } 83697468e2c8SBruno Larsen (billionai) } 83707468e2c8SBruno Larsen (billionai) } 83717468e2c8SBruno Larsen (billionai) 83727468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 83737468e2c8SBruno Larsen (billionai) { 83747468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 83757468e2c8SBruno Larsen (billionai) 83767468e2c8SBruno Larsen (billionai) /* 83777468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 83787468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 83797468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 83807468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 83817468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 83827468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 83837468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 83847468e2c8SBruno Larsen (billionai) */ 83857468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 83867468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 83877468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 83887468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 83897468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 83907468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 83917468e2c8SBruno Larsen (billionai) } 83927468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 83937468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 83947468e2c8SBruno Larsen (billionai) return 0; 83957468e2c8SBruno Larsen (billionai) } 83967468e2c8SBruno Larsen (billionai) 8397624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8398624cb07fSRichard Henderson { 8399624cb07fSRichard Henderson opc_handler_t **table, *handler; 8400624cb07fSRichard Henderson uint32_t inval; 8401624cb07fSRichard Henderson 8402624cb07fSRichard Henderson ctx->opcode = insn; 8403624cb07fSRichard Henderson 8404624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8405624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8406624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8407624cb07fSRichard Henderson 8408624cb07fSRichard Henderson table = cpu->opcodes; 8409624cb07fSRichard Henderson handler = table[opc1(insn)]; 8410624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8411624cb07fSRichard Henderson table = ind_table(handler); 8412624cb07fSRichard Henderson handler = table[opc2(insn)]; 8413624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8414624cb07fSRichard Henderson table = ind_table(handler); 8415624cb07fSRichard Henderson handler = table[opc3(insn)]; 8416624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8417624cb07fSRichard Henderson table = ind_table(handler); 8418624cb07fSRichard Henderson handler = table[opc4(insn)]; 8419624cb07fSRichard Henderson } 8420624cb07fSRichard Henderson } 8421624cb07fSRichard Henderson } 8422624cb07fSRichard Henderson 8423624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8424624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8425624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8426624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8427624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8428624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8429624cb07fSRichard Henderson insn, ctx->cia); 8430624cb07fSRichard Henderson return false; 8431624cb07fSRichard Henderson } 8432624cb07fSRichard Henderson 8433624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8434624cb07fSRichard Henderson && Rc(insn))) { 8435624cb07fSRichard Henderson inval = handler->inval2; 8436624cb07fSRichard Henderson } else { 8437624cb07fSRichard Henderson inval = handler->inval1; 8438624cb07fSRichard Henderson } 8439624cb07fSRichard Henderson 8440624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8441624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8442624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8443624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8444624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8445624cb07fSRichard Henderson insn, ctx->cia); 8446624cb07fSRichard Henderson return false; 8447624cb07fSRichard Henderson } 8448624cb07fSRichard Henderson 8449624cb07fSRichard Henderson handler->handler(ctx); 8450624cb07fSRichard Henderson return true; 8451624cb07fSRichard Henderson } 8452624cb07fSRichard Henderson 8453b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8454fcf5ef2aSThomas Huth { 8455b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 84569c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 84572df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8458fcf5ef2aSThomas Huth 8459b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 84602df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8461d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 84622df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 84632df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 8464b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 8465b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 8466b0c2d521SEmilio G. Cota ctx->access_type = -1; 8467d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 84682df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8469b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 84700e3bf489SRoman Kapl ctx->flags = env->flags; 8471fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 84722df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8473b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8474fcf5ef2aSThomas Huth #endif 8475e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8476e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 8477d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 8478fcf5ef2aSThomas Huth 84792df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 84802df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 84812df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 84822df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 84832df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8484f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 84851db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 8486f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 8487f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 8488*46d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 84892df4fe7aSRichard Henderson 8490b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 84912df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 84922df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 84939498d103SRichard Henderson ctx->base.max_insns = 1; 8494efe843d8SDavid Gibson } 84952df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 8496b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8497efe843d8SDavid Gibson } 849813b45575SRichard Henderson } 8499fcf5ef2aSThomas Huth 8500b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8501b0c2d521SEmilio G. Cota { 8502b0c2d521SEmilio G. Cota } 8503fcf5ef2aSThomas Huth 8504b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8505b0c2d521SEmilio G. Cota { 8506b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 8507b0c2d521SEmilio G. Cota } 8508b0c2d521SEmilio G. Cota 850999082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 851099082815SRichard Henderson { 851199082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 851299082815SRichard Henderson return opc1(insn) == 1; 851399082815SRichard Henderson } 851499082815SRichard Henderson 8515b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8516b0c2d521SEmilio G. Cota { 8517b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 851828876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 8519b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 852099082815SRichard Henderson target_ulong pc; 8521624cb07fSRichard Henderson uint32_t insn; 8522624cb07fSRichard Henderson bool ok; 8523b0c2d521SEmilio G. Cota 8524fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 8525fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8526b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8527b0c2d521SEmilio G. Cota 852899082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 85294e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 853099082815SRichard Henderson ctx->base.pc_next = pc += 4; 8531fcf5ef2aSThomas Huth 853299082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 853399082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 853499082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 853599082815SRichard Henderson } else if ((pc & 63) == 0) { 853699082815SRichard Henderson /* 853799082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 853899082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 853999082815SRichard Henderson * 64-byte address boundary (system alignment error). 854099082815SRichard Henderson */ 854199082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 854299082815SRichard Henderson ok = true; 854399082815SRichard Henderson } else { 85444e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 85454e116893SIlya Leoshkevich need_byteswap(ctx)); 854699082815SRichard Henderson ctx->base.pc_next = pc += 4; 854799082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 854899082815SRichard Henderson } 8549624cb07fSRichard Henderson if (!ok) { 8550624cb07fSRichard Henderson gen_invalid(ctx); 8551fcf5ef2aSThomas Huth } 8552624cb07fSRichard Henderson 855364a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 855499082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 855564a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 855664a0f644SRichard Henderson } 855764a0f644SRichard Henderson 855851eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 8559fcf5ef2aSThomas Huth } 8560b0c2d521SEmilio G. Cota 8561b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8562b0c2d521SEmilio G. Cota { 8563b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8564a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 8565a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 8566b0c2d521SEmilio G. Cota 8567a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 8568a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 85693d8a5b69SRichard Henderson return; 85703d8a5b69SRichard Henderson } 85713d8a5b69SRichard Henderson 8572a9b5b3d0SRichard Henderson /* Honor single stepping. */ 85739498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 85749498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 8575a9b5b3d0SRichard Henderson switch (is_jmp) { 8576a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8577a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8578a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8579a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8580a9b5b3d0SRichard Henderson break; 8581a9b5b3d0SRichard Henderson case DISAS_EXIT: 8582a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8583a9b5b3d0SRichard Henderson break; 8584a9b5b3d0SRichard Henderson default: 8585a9b5b3d0SRichard Henderson g_assert_not_reached(); 8586fcf5ef2aSThomas Huth } 858713b45575SRichard Henderson 8588a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 8589a9b5b3d0SRichard Henderson return; 8590a9b5b3d0SRichard Henderson } 8591a9b5b3d0SRichard Henderson 8592a9b5b3d0SRichard Henderson switch (is_jmp) { 8593a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8594a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 8595*46d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 8596a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 8597a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8598a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 8599a9b5b3d0SRichard Henderson break; 8600a9b5b3d0SRichard Henderson } 8601a9b5b3d0SRichard Henderson /* fall through */ 8602a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8603a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8604a9b5b3d0SRichard Henderson /* fall through */ 8605a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8606*46d396bdSDaniel Henrique Barboza /* 8607*46d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 8608*46d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 8609*46d396bdSDaniel Henrique Barboza */ 8610*46d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 8611*46d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 8612*46d396bdSDaniel Henrique Barboza } 8613*46d396bdSDaniel Henrique Barboza 8614a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 8615a9b5b3d0SRichard Henderson break; 8616a9b5b3d0SRichard Henderson 8617a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8618a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8619a9b5b3d0SRichard Henderson /* fall through */ 8620a9b5b3d0SRichard Henderson case DISAS_EXIT: 8621*46d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 862207ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8623a9b5b3d0SRichard Henderson break; 8624a9b5b3d0SRichard Henderson 8625a9b5b3d0SRichard Henderson default: 8626a9b5b3d0SRichard Henderson g_assert_not_reached(); 8627fcf5ef2aSThomas Huth } 8628fcf5ef2aSThomas Huth } 8629b0c2d521SEmilio G. Cota 8630b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8631b0c2d521SEmilio G. Cota { 8632b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8633b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8634b0c2d521SEmilio G. Cota } 8635b0c2d521SEmilio G. Cota 8636b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8637b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8638b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8639b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8640b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8641b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8642b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8643b0c2d521SEmilio G. Cota }; 8644b0c2d521SEmilio G. Cota 86458b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8646b0c2d521SEmilio G. Cota { 8647b0c2d521SEmilio G. Cota DisasContext ctx; 8648b0c2d521SEmilio G. Cota 86498b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8650fcf5ef2aSThomas Huth } 8651fcf5ef2aSThomas Huth 8652fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8653fcf5ef2aSThomas Huth target_ulong *data) 8654fcf5ef2aSThomas Huth { 8655fcf5ef2aSThomas Huth env->nip = data[0]; 8656fcf5ef2aSThomas Huth } 8657